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-------------------------------------------------------------------------------
-- $Id: xbic_addr_decode.vhd,v 1.2.2.1 2008/12/16 22:23:17 dougt Exp $
-------------------------------------------------------------------------------
-- xbic_addr_decode.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2007, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: xbic_addr_decode.vhd
-- Version: v1_00_a
-- Description: Simple address decoder function for one Base Addr Pair.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- xps_bram_if_cntlr.vhd
-- |
-- |- xbic_slave_attach_sngl
-- | |
-- | |- xbic_addr_decode
-- | |- xbic_addr_be_support
-- | |- xbic_data_steer_mirror
-- |
-- |- xbic_slave_attach_burst
-- |
-- |- xbic_addr_decode
-- |- xbic_addr_be_support
-- |- xbic_data_steer_mirror
-- |- xbic_addr_cntr
-- | |
-- | |- xbic_be_reset_gen.vhd
-- |
-- |- xbic_dbeat_control
-- |- xbic_data_steer_mirror
--
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- History:
--
-- DET Feb-5-07
-- ~~~~~~
-- -- Special version for the XPS BRAM IF Cntlr that is adapted
-- from xps_bram_if_cntlr_v1_00_a library
-- -- Bypassed input address and qualifiers registering to remove
-- one clock of latency during address phase.
-- ^^^^^^
--
-- DET 5/24/2007 Jm
-- ~~~~~~
-- - Recoded to utilize behavorial address decode instead of calling
-- the pselect_f module from proc common. This reduced the timing
-- problem paths found with the pselect_f decoder in Spartan3x
-- devices.
-- ^^^^^^
--
-- DET 8/25/2008 v1_00_b
-- ~~~~~~
-- - Updated to proc_common_v3_00_a library.
-- ^^^^^^
--
-- DET 9/9/2008 v1_00_b for EDK 11.x release
-- ~~~~~~
-- - Updated Disclaimer in header section.
-- ^^^^^^
--
-- DET 12/16/2008 v1_01_b
-- ~~~~~~
-- - Updated eula/header to latest version.
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_type"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.family_support.all;
-- Xilinx Primitive Library
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity xbic_addr_decode is
generic (
C_SPLB_AWIDTH : integer := 32;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF" -- IP user0 high address
);
C_FAMILY : string := "virtex5"
);
port (
-- PLB Interface signals
Address_In : in std_logic_vector(0 to
C_SPLB_AWIDTH-1);
Address_Valid : in std_logic;
-- Decode output signals
Addr_Match : out std_logic
);
end entity xbic_addr_decode;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture implementation of xbic_addr_decode is
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_SPLB_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_SPLB_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_SPLB_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_SPLB_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
return(C_SPLB_AWIDTH);
end function Addr_Bits;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_SPLB_AWIDTH);
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
Constant NUM_BITS_TO_DECODE : integer := DECODE_BITS(0);
constant BASE_ADDR_BITS_TO_USE : unsigned(0 to NUM_BITS_TO_DECODE-1) :=
UNSIGNED(ARD_ADDR_RANGE_ARRAY(0)(0 to NUM_BITS_TO_DECODE-1));
----------------------------------------------------------------
-- Signals
----------------------------------------------------------------
signal decode_hit : std_logic;
Signal sig_input_addr_bits_to_use : unsigned(0 to NUM_BITS_TO_DECODE-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
Addr_Match <= decode_hit;
-- rip only the bits needed for the address range decode
sig_input_addr_bits_to_use <= UNSIGNED(Address_In(0 to NUM_BITS_TO_DECODE-1));
-- Behavorial compare of input address decode bits to the Base address
-- decode bits
decode_hit <= '1'
When (sig_input_addr_bits_to_use = BASE_ADDR_BITS_TO_USE)
Else '0';
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- converts a string into integer
function str_to_int( s : string ) return integer ;
-- converts a character into integer
function char_to_int( c : character ) return integer ;
-- converts a string into integer
-- function str_to_real(s : string ) return real ;
function str_nextchar (str: string; str_begin: integer; char: character) return integer ;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- converts a std_logic_vector into a hex string.
-- function substring(str: string, str_begin: integer, str_end: integer) return string is
-- begin
-- return str(str_begin to str_end);
-- end substring;
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
--print(c);
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
-- procedure str_write(file out_file: TEXT;
-- new_string: in string) is
-- begin
-- for i in new_string'range loop
-- print(out_file, new_string(i));
-- if new_string(i) = LF then -- end of string
-- exit;
-- end if;
-- end loop;
-- end str_write;
function str_to_int( s : string ) return integer is
variable len : integer := s'length;
variable ivalue : integer := 0;
variable digit : integer;
-- variable myline: line;
begin
for i in 1 to len loop
case s(i) is
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 10 + digit;
end loop;
return ivalue;
end;
function char_to_int( c : character ) return integer is
variable digit : integer;
begin
case c is
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character in char parameter! "
SEVERITY ERROR;
end case;
return digit;
end char_to_int;
function str_nextchar(str: string; str_begin: integer; char: character) return integer is
variable ivalue : integer := -1;
begin
if(str_begin>str'length ) then
ASSERT FALSE
REPORT "Parser Error: Out of range "& char & "in string parameter! "
SEVERITY ERROR;
return -1;
else
for i in str_begin to str'length loop
if(str(i)= char) then
return i;
end if;
if i = str'length then
return i;
end if;
end loop;
end if;
return ivalue;
end str_nextchar;
-- function str_to_real( s : string ) return real is
-- variable beginner: integer:=0;
-- variable value: real:=0.0;
-- variable is_decimal_digits: boolean;
-- variable val: integer := 0;
--
-- begin
---- -- decimal_digits:=FALSE;
-- for i in 1 to s'length loop
----
-- if (s(i)='.') then
-- is_decimal_digits:=true;
--- val:= str_to_int ( s(beginner to i-1) ) ;
-- value:= val+0.0;
-- value:= value + (str_to_int(s(i+1 to s'length)))/ (10**(s'length-i) );
-- return value;
-- else
-- if(s(i)/='0' and beginner=0) then
---- beginner:=i;
-- end if;
-- end if;
--
-- end loop;
-- value:= value + str_to_int( s(beginner to s'length));
--
-- return value;
--
-- end str_to_real;
end txt_util;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:46:23 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_mdm_1_0/system_mdm_1_0_sim_netlist.vhdl
-- Design : system_mdm_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_mdm_1_0_MB_BSCANE2 is
port (
Dbg_Capture_0 : out STD_LOGIC;
drck_i : out STD_LOGIC;
Ext_JTAG_RESET : out STD_LOGIC;
sel : out STD_LOGIC;
\Use_Serial_Unified_Completion.count_reg[5]\ : out STD_LOGIC;
Ext_JTAG_TDI : out STD_LOGIC;
Dbg_Update_31 : out STD_LOGIC;
\Use_Serial_Unified_Completion.count_reg[5]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
shift_n_reset : out STD_LOGIC;
AR : out STD_LOGIC_VECTOR ( 0 to 0 );
\Use_Serial_Unified_Completion.count_reg[5]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\shift_Count_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Use_Serial_Unified_Completion.mb_instr_overrun_reg\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
tdo : in STD_LOGIC;
\p_20_out__0\ : in STD_LOGIC;
\p_43_out__0\ : in STD_LOGIC;
Scan_Reset : in STD_LOGIC;
Scan_Reset_Sel : in STD_LOGIC;
\Use_Serial_Unified_Completion.count_reg[5]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
Dbg_TDO_0 : in STD_LOGIC;
\Use_Serial_Unified_Completion.sample_1_reg[15]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_mdm_1_0_MB_BSCANE2 : entity is "MB_BSCANE2";
end system_mdm_1_0_MB_BSCANE2;
architecture STRUCTURE of system_mdm_1_0_MB_BSCANE2 is
signal \^dbg_capture_0\ : STD_LOGIC;
signal \Use_E2.BSCANE2_I_n_3\ : STD_LOGIC;
signal \Use_E2.BSCANE2_I_n_6\ : STD_LOGIC;
signal \Use_E2.BSCANE2_I_n_8\ : STD_LOGIC;
signal \^use_serial_unified_completion.count_reg[5]\ : STD_LOGIC;
signal \^sel\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Use_BSCAN.Config_Reg[30]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \Use_BSCAN.PORT_Selector[3]_i_1\ : label is "soft_lutpair18";
attribute box_type : string;
attribute box_type of \Use_E2.BSCANE2_I\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[15]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[15]_i_2\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.count[0]__0_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.count[5]_i_1\ : label is "soft_lutpair19";
begin
Dbg_Capture_0 <= \^dbg_capture_0\;
\Use_Serial_Unified_Completion.count_reg[5]\ <= \^use_serial_unified_completion.count_reg[5]\;
sel <= \^sel\;
\Use_BSCAN.Config_Reg[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => Scan_Reset,
I1 => Scan_Reset_Sel,
I2 => \^use_serial_unified_completion.count_reg[5]\,
O => shift_n_reset
);
\Use_BSCAN.PORT_Selector[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => Scan_Reset,
I1 => Scan_Reset_Sel,
I2 => \^sel\,
O => AR(0)
);
\Use_E2.BSCANE2_I\: unisim.vcomponents.BSCANE2
generic map(
DISABLE_JTAG => "FALSE",
JTAG_CHAIN => 2
)
port map (
CAPTURE => \^dbg_capture_0\,
DRCK => drck_i,
RESET => Ext_JTAG_RESET,
RUNTEST => \Use_E2.BSCANE2_I_n_3\,
SEL => \^sel\,
SHIFT => \^use_serial_unified_completion.count_reg[5]\,
TCK => \Use_E2.BSCANE2_I_n_6\,
TDI => Ext_JTAG_TDI,
TDO => tdo,
TMS => \Use_E2.BSCANE2_I_n_8\,
UPDATE => Dbg_Update_31
);
\Use_Serial_Unified_Completion.completion_status[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \p_43_out__0\,
I1 => \^dbg_capture_0\,
I2 => \^use_serial_unified_completion.count_reg[5]\,
O => E(0)
);
\Use_Serial_Unified_Completion.completion_status[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^dbg_capture_0\,
I1 => \Use_Serial_Unified_Completion.sample_1_reg[15]\(0),
O => D(0)
);
\Use_Serial_Unified_Completion.count[0]__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \p_20_out__0\,
I1 => \^dbg_capture_0\,
I2 => \^use_serial_unified_completion.count_reg[5]\,
O => \Use_Serial_Unified_Completion.count_reg[5]_0\(0)
);
\Use_Serial_Unified_Completion.count[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^dbg_capture_0\,
I1 => \Use_Serial_Unified_Completion.count_reg[5]_2\(0),
O => \Use_Serial_Unified_Completion.count_reg[5]_1\(0)
);
\Use_Serial_Unified_Completion.mb_instr_overrun_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Dbg_TDO_0,
I1 => \^dbg_capture_0\,
O => \Use_Serial_Unified_Completion.mb_instr_overrun_reg\
);
\shift_Count[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^use_serial_unified_completion.count_reg[5]\,
I1 => Q(0),
O => \shift_Count_reg[0]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_mdm_1_0_MB_BUFG is
port (
Dbg_Clk_31 : out STD_LOGIC;
drck_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_mdm_1_0_MB_BUFG : entity is "MB_BUFG";
end system_mdm_1_0_MB_BUFG;
architecture STRUCTURE of system_mdm_1_0_MB_BUFG is
attribute box_type : string;
attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.BUFG
port map (
I => drck_i,
O => Dbg_Clk_31
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_mdm_1_0_MB_FDC_1 is
port (
D_0 : out STD_LOGIC;
Dbg_Shift_0 : out STD_LOGIC;
\p_20_out__0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
\Use_Serial_Unified_Completion.completion_block_reg\ : out STD_LOGIC;
sample_1 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Use_Serial_Unified_Completion.sample_reg[15]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\shifting_Data1__0\ : out STD_LOGIC;
Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
CE : out STD_LOGIC;
\command_1_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Use_Serial_Unified_Completion.mb_instr_overrun_reg\ : out STD_LOGIC;
\Use_Serial_Unified_Completion.mb_instr_overrun_reg_0\ : out STD_LOGIC;
\Use_Serial_Unified_Completion.mb_instr_error_reg\ : out STD_LOGIC;
\Use_Serial_Unified_Completion.mb_data_overrun_reg\ : out STD_LOGIC;
\completion_ctrl_reg[0]\ : out STD_LOGIC;
\Use_Serial_Unified_Completion.completion_block_reg_0\ : out STD_LOGIC;
Debug_Rst_i_reg : out STD_LOGIC;
Debug_SYS_Rst_i_reg : out STD_LOGIC;
Ext_NM_BRK_i_reg : out STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]\ : in STD_LOGIC;
sel_n : in STD_LOGIC;
\command_reg[6]\ : in STD_LOGIC;
\command_reg[4]\ : in STD_LOGIC;
\command_reg[0]\ : in STD_LOGIC;
sync : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_0\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
\Use_Serial_Unified_Completion.completion_block_reg_1\ : in STD_LOGIC;
\command_reg[7]\ : in STD_LOGIC;
\Use_Serial_Unified_Completion.completion_status_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
\Use_Serial_Unified_Completion.completion_status_reg[2]\ : in STD_LOGIC;
\Use_Serial_Unified_Completion.completion_status_reg[3]\ : in STD_LOGIC;
\Use_Serial_Unified_Completion.completion_status_reg[4]\ : in STD_LOGIC;
\Use_Serial_Unified_Completion.completion_status_reg[5]\ : in STD_LOGIC;
\Use_Serial_Unified_Completion.completion_status_reg[7]\ : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_1\ : in STD_LOGIC;
\Use_Serial_Unified_Completion.sample_reg[15]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\tdi_shifter_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\Use_BSCAN.PORT_Selector_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_2\ : in STD_LOGIC;
\p_22_out__0\ : in STD_LOGIC;
\Use_Serial_Unified_Completion.count_reg[1]\ : in STD_LOGIC;
Dbg_TDO_0 : in STD_LOGIC;
\Use_Serial_Unified_Completion.count_reg[5]\ : in STD_LOGIC;
completion_ctrl : in STD_LOGIC;
\Use_Serial_Unified_Completion.sample_1_reg[15]\ : in STD_LOGIC;
Dbg_Rst_0 : in STD_LOGIC;
Debug_SYS_Rst : in STD_LOGIC;
Ext_NM_BRK : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_mdm_1_0_MB_FDC_1 : entity is "MB_FDC_1";
end system_mdm_1_0_MB_FDC_1;
architecture STRUCTURE of system_mdm_1_0_MB_FDC_1 is
signal \^d_0\ : STD_LOGIC;
signal Dbg_Shift_31_INST_0_i_2_n_0 : STD_LOGIC;
signal Debug_Rst_i0 : STD_LOGIC;
signal \^use_serial_unified_completion.completion_block_reg\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.mb_instr_overrun_i_4_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.mb_instr_overrun_i_6_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.sample_1[15]_i_2_n_0\ : STD_LOGIC;
signal \Using_FPGA.Native_i_2_n_0\ : STD_LOGIC;
signal completion_ctrl0 : STD_LOGIC;
signal data_cmd_noblock : STD_LOGIC;
signal \^p_20_out__0\ : STD_LOGIC;
signal \^sample_1\ : STD_LOGIC;
signal \^shifting_data1__0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Dbg_Reg_En_0[0]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \Dbg_Reg_En_0[1]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \Dbg_Reg_En_0[2]_INST_0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \Dbg_Reg_En_0[3]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \Dbg_Reg_En_0[4]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \Dbg_Reg_En_0[5]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \Dbg_Reg_En_0[6]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \Dbg_Reg_En_0[7]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of Dbg_Shift_31_INST_0_i_2 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Debug_Rst_i_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of Ext_NM_BRK_i_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of Ext_NM_BRK_i_i_3 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[15]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.mb_instr_overrun_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.sample[13]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.sample[14]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.sample_1[15]_i_2\ : label is "soft_lutpair9";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDC_1";
attribute box_type : string;
attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \Using_FPGA.Native_i_1__0\ : label is "soft_lutpair9";
begin
D_0 <= \^d_0\;
\Use_Serial_Unified_Completion.completion_block_reg\ <= \^use_serial_unified_completion.completion_block_reg\;
\p_20_out__0\ <= \^p_20_out__0\;
sample_1 <= \^sample_1\;
\shifting_Data1__0\ <= \^shifting_data1__0\;
\Dbg_Reg_En_0[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I1 => data_cmd_noblock,
I2 => Q(7),
O => Dbg_Reg_En_0(0)
);
\Dbg_Reg_En_0[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I1 => data_cmd_noblock,
I2 => Q(6),
O => Dbg_Reg_En_0(1)
);
\Dbg_Reg_En_0[2]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I1 => data_cmd_noblock,
I2 => Q(5),
O => Dbg_Reg_En_0(2)
);
\Dbg_Reg_En_0[3]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I1 => data_cmd_noblock,
I2 => Q(4),
O => Dbg_Reg_En_0(3)
);
\Dbg_Reg_En_0[4]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I1 => data_cmd_noblock,
I2 => Q(3),
O => Dbg_Reg_En_0(4)
);
\Dbg_Reg_En_0[5]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I1 => data_cmd_noblock,
I2 => Q(2),
O => Dbg_Reg_En_0(5)
);
\Dbg_Reg_En_0[6]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I1 => data_cmd_noblock,
I2 => Q(1),
O => Dbg_Reg_En_0(6)
);
\Dbg_Reg_En_0[7]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I1 => data_cmd_noblock,
I2 => Q(0),
O => Dbg_Reg_En_0(7)
);
Dbg_Shift_31_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7FF00000000"
)
port map (
I0 => \command_reg[6]\,
I1 => Dbg_Shift_31_INST_0_i_2_n_0,
I2 => \command_reg[4]\,
I3 => \command_reg[0]\,
I4 => sync,
I5 => \Use_BSCAN.PORT_Selector_reg[0]_0\,
O => Dbg_Shift_0
);
Dbg_Shift_31_INST_0_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => data_cmd_noblock,
I1 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
O => Dbg_Shift_31_INST_0_i_2_n_0
);
Debug_Rst_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \tdi_shifter_reg[0]\(7),
I1 => Debug_Rst_i0,
I2 => Dbg_Rst_0,
O => Debug_Rst_i_reg
);
Debug_SYS_Rst_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \tdi_shifter_reg[0]\(6),
I1 => Debug_Rst_i0,
I2 => Debug_SYS_Rst,
O => Debug_SYS_Rst_i_reg
);
Ext_NM_BRK_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \tdi_shifter_reg[0]\(4),
I1 => Debug_Rst_i0,
I2 => Ext_NM_BRK,
O => Ext_NM_BRK_i_reg
);
Ext_NM_BRK_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00020000"
)
port map (
I0 => data_cmd_noblock,
I1 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I2 => Q(1),
I3 => Q(5),
I4 => \command_reg[7]\,
O => Debug_Rst_i0
);
\Use_Serial_Unified_Completion.completion_block_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF5FFF5F000C0000"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I1 => \Use_Serial_Unified_Completion.sample_1_reg[15]\,
I2 => completion_ctrl0,
I3 => \^use_serial_unified_completion.completion_block_reg\,
I4 => completion_ctrl,
I5 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
O => \Use_Serial_Unified_Completion.completion_block_reg_0\
);
\Use_Serial_Unified_Completion.completion_status[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => \^use_serial_unified_completion.completion_block_reg\,
I1 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(1),
I2 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(0),
I3 => \^sample_1\,
O => D(0)
);
\Use_Serial_Unified_Completion.completion_status[15]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => Q(1),
I1 => Q(5),
I2 => data_cmd_noblock,
I3 => \command_reg[7]\,
O => \^use_serial_unified_completion.completion_block_reg\
);
\Use_Serial_Unified_Completion.completion_status[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF606060"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(1),
I1 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(0),
I2 => \^sample_1\,
I3 => \^use_serial_unified_completion.completion_block_reg\,
I4 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(2),
O => D(1)
);
\Use_Serial_Unified_Completion.completion_status[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF6A006A006A00"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(2),
I1 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(1),
I2 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(0),
I3 => \^sample_1\,
I4 => \^use_serial_unified_completion.completion_block_reg\,
I5 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(3),
O => D(2)
);
\Use_Serial_Unified_Completion.completion_status[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF606060"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(3),
I1 => \Use_Serial_Unified_Completion.completion_status_reg[2]\,
I2 => \^sample_1\,
I3 => \^use_serial_unified_completion.completion_block_reg\,
I4 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(4),
O => D(3)
);
\Use_Serial_Unified_Completion.completion_status[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF606060"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(4),
I1 => \Use_Serial_Unified_Completion.completion_status_reg[3]\,
I2 => \^sample_1\,
I3 => \^use_serial_unified_completion.completion_block_reg\,
I4 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(5),
O => D(4)
);
\Use_Serial_Unified_Completion.completion_status[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF484848"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(5),
I1 => \^sample_1\,
I2 => \Use_Serial_Unified_Completion.completion_status_reg[4]\,
I3 => \^use_serial_unified_completion.completion_block_reg\,
I4 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(6),
O => D(5)
);
\Use_Serial_Unified_Completion.completion_status[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF484848"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(6),
I1 => \^sample_1\,
I2 => \Use_Serial_Unified_Completion.completion_status_reg[5]\,
I3 => \^use_serial_unified_completion.completion_block_reg\,
I4 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(7),
O => D(6)
);
\Use_Serial_Unified_Completion.completion_status[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF488848884888"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(7),
I1 => \^sample_1\,
I2 => \Use_Serial_Unified_Completion.completion_status_reg[5]\,
I3 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(6),
I4 => \^use_serial_unified_completion.completion_block_reg\,
I5 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(8),
O => D(7)
);
\Use_Serial_Unified_Completion.completion_status[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF484848"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(8),
I1 => \^sample_1\,
I2 => \Use_Serial_Unified_Completion.completion_status_reg[7]\,
I3 => \^use_serial_unified_completion.completion_block_reg\,
I4 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(9),
O => D(8)
);
\Use_Serial_Unified_Completion.completion_status[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0CA00CA00CA00FA0"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[0]_0\,
I1 => completion_ctrl0,
I2 => \^use_serial_unified_completion.completion_block_reg\,
I3 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I4 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I5 => data_cmd_noblock,
O => E(0)
);
\Use_Serial_Unified_Completion.completion_status[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF488848884888"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(9),
I1 => \^sample_1\,
I2 => \Use_Serial_Unified_Completion.completion_status_reg[7]\,
I3 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(8),
I4 => \^use_serial_unified_completion.completion_block_reg\,
I5 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(10),
O => D(9)
);
\Use_Serial_Unified_Completion.completion_status[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_1[15]_i_2_n_0\,
I1 => Q(1),
I2 => Q(0),
I3 => Q(3),
I4 => Q(2),
I5 => \command_reg[0]\,
O => completion_ctrl0
);
\Use_Serial_Unified_Completion.count[0]__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000080000000000"
)
port map (
I0 => Q(2),
I1 => Q(1),
I2 => Q(0),
I3 => Dbg_Shift_31_INST_0_i_2_n_0,
I4 => \command_reg[4]\,
I5 => \command_reg[0]\,
O => \^p_20_out__0\
);
\Use_Serial_Unified_Completion.count[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040000000000"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => Dbg_Shift_31_INST_0_i_2_n_0,
I4 => \command_reg[4]\,
I5 => \command_reg[0]\,
O => \^shifting_data1__0\
);
\Use_Serial_Unified_Completion.mb_data_overrun_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"113F333F11000000"
)
port map (
I0 => Dbg_TDO_0,
I1 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I2 => completion_ctrl0,
I3 => \^p_20_out__0\,
I4 => \Use_Serial_Unified_Completion.count_reg[5]\,
I5 => \Use_Serial_Unified_Completion.sample_reg[15]_0\(2),
O => \Use_Serial_Unified_Completion.mb_data_overrun_reg\
);
\Use_Serial_Unified_Completion.mb_instr_error_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0BFFFA0A08000"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I1 => \p_22_out__0\,
I2 => \^shifting_data1__0\,
I3 => \Use_Serial_Unified_Completion.count_reg[1]\,
I4 => \Use_Serial_Unified_Completion.mb_instr_overrun_i_4_n_0\,
I5 => \Use_Serial_Unified_Completion.sample_reg[15]_0\(1),
O => \Use_Serial_Unified_Completion.mb_instr_error_reg\
);
\Use_Serial_Unified_Completion.mb_instr_overrun_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0FFBFA0A00080"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I1 => \p_22_out__0\,
I2 => \^shifting_data1__0\,
I3 => \Use_Serial_Unified_Completion.count_reg[1]\,
I4 => \Use_Serial_Unified_Completion.mb_instr_overrun_i_4_n_0\,
I5 => \Use_Serial_Unified_Completion.sample_reg[15]_0\(0),
O => \Use_Serial_Unified_Completion.mb_instr_overrun_reg_0\
);
\Use_Serial_Unified_Completion.mb_instr_overrun_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00000008000000"
)
port map (
I0 => \command_reg[6]\,
I1 => Dbg_Shift_31_INST_0_i_2_n_0,
I2 => \command_reg[4]\,
I3 => \command_reg[0]\,
I4 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I5 => \Use_Serial_Unified_Completion.mb_instr_overrun_i_6_n_0\,
O => \Use_Serial_Unified_Completion.mb_instr_overrun_i_4_n_0\
);
\Use_Serial_Unified_Completion.mb_instr_overrun_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I1 => data_cmd_noblock,
I2 => Q(5),
I3 => Q(3),
O => \Use_Serial_Unified_Completion.mb_instr_overrun_reg\
);
\Use_Serial_Unified_Completion.mb_instr_overrun_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => Q(2),
I1 => Q(3),
I2 => Q(0),
I3 => Q(1),
I4 => data_cmd_noblock,
I5 => Q(5),
O => \Use_Serial_Unified_Completion.mb_instr_overrun_i_6_n_0\
);
\Use_Serial_Unified_Completion.sample[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_reg[15]_0\(3),
I1 => \^sample_1\,
O => \Use_Serial_Unified_Completion.sample_reg[15]\(0)
);
\Use_Serial_Unified_Completion.sample[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_reg[15]_0\(4),
I1 => \^sample_1\,
O => \Use_Serial_Unified_Completion.sample_reg[15]\(1)
);
\Use_Serial_Unified_Completion.sample[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_reg[15]_0\(5),
I1 => \^sample_1\,
O => \Use_Serial_Unified_Completion.sample_reg[15]\(2)
);
\Use_Serial_Unified_Completion.sample_1[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDF7FFFFFFFFFFF"
)
port map (
I0 => \command_reg[0]\,
I1 => Q(2),
I2 => Q(3),
I3 => Q(0),
I4 => Q(1),
I5 => \Use_Serial_Unified_Completion.sample_1[15]_i_2_n_0\,
O => \^sample_1\
);
\Use_Serial_Unified_Completion.sample_1[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => Q(5),
I1 => data_cmd_noblock,
O => \Use_Serial_Unified_Completion.sample_1[15]_i_2_n_0\
);
\Using_FPGA.Native\: unisim.vcomponents.FDCE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => '1',
CLR => sel_n,
D => \^d_0\,
Q => data_cmd_noblock
);
\Using_FPGA.Native_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => \Using_FPGA.Native_i_2_n_0\,
I1 => \tdi_shifter_reg[0]\(3),
I2 => \tdi_shifter_reg[0]\(2),
I3 => \tdi_shifter_reg[0]\(0),
I4 => \tdi_shifter_reg[0]\(1),
O => CE
);
\Using_FPGA.Native_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => data_cmd_noblock,
O => \^d_0\
);
\Using_FPGA.Native_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => \tdi_shifter_reg[0]\(5),
I1 => \tdi_shifter_reg[0]\(4),
I2 => \tdi_shifter_reg[0]\(6),
I3 => \tdi_shifter_reg[0]\(7),
I4 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I5 => data_cmd_noblock,
O => \Using_FPGA.Native_i_2_n_0\
);
\command_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000001000000"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[3]\(2),
I1 => \Use_BSCAN.PORT_Selector_reg[3]\(3),
I2 => \Use_BSCAN.PORT_Selector_reg[3]\(1),
I3 => \Use_BSCAN.PORT_Selector_reg[3]\(0),
I4 => sel,
I5 => Dbg_Shift_31_INST_0_i_2_n_0,
O => \command_1_reg[7]\(0)
);
\completion_ctrl[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \tdi_shifter_reg[0]\(7),
I1 => completion_ctrl0,
I2 => completion_ctrl,
O => \completion_ctrl_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_mdm_1_0_MB_FDRE_1 is
port (
sync : out STD_LOGIC;
\p_22_out__0\ : out STD_LOGIC;
D_0 : in STD_LOGIC;
CE : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]\ : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_0\ : in STD_LOGIC;
\command_reg[0]\ : in STD_LOGIC;
\Use_Serial_Unified_Completion.completion_block_reg\ : in STD_LOGIC;
\command_reg[6]\ : in STD_LOGIC;
\Use_Serial_Unified_Completion.count_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_mdm_1_0_MB_FDRE_1 : entity is "MB_FDRE_1";
end system_mdm_1_0_MB_FDRE_1;
architecture STRUCTURE of system_mdm_1_0_MB_FDRE_1 is
signal \^sync\ : STD_LOGIC;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDRE_1";
attribute box_type : string;
attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
sync <= \^sync\;
\Use_Serial_Unified_Completion.mb_instr_overrun_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008AAAAAAA"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[0]_0\,
I1 => \^sync\,
I2 => \command_reg[0]\,
I3 => \Use_Serial_Unified_Completion.completion_block_reg\,
I4 => \command_reg[6]\,
I5 => \Use_Serial_Unified_Completion.count_reg[0]\,
O => \p_22_out__0\
);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => CE,
D => '1',
Q => \^sync\,
R => D_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_mdm_1_0_MB_SRL16E is
port (
tdo : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
\Use_BSCAN.PORT_Selector_reg[0]\ : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[2]\ : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\command_reg[0]\ : in STD_LOGIC;
\command_reg[5]\ : in STD_LOGIC;
\command_reg[0]_0\ : in STD_LOGIC;
\command_reg[3]\ : in STD_LOGIC;
\command_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Dbg_TDO_0 : in STD_LOGIC;
\Use_Serial_Unified_Completion.completion_status_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
config_TDO_2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_mdm_1_0_MB_SRL16E : entity is "MB_SRL16E";
end system_mdm_1_0_MB_SRL16E;
architecture STRUCTURE of system_mdm_1_0_MB_SRL16E is
signal \Use_E2.BSCANE2_I_i_4_n_0\ : STD_LOGIC;
signal \Use_E2.BSCANE2_I_i_8_n_0\ : STD_LOGIC;
signal \Use_unisim.MB_SRL16E_I1_n_0\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MDM_Core_I1/JTAG_CONTROL_I/Use_Config_SRL16E.SRL16E_1/Use_unisim.MB_SRL16E_I1 ";
begin
\Use_E2.BSCANE2_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEAEAEAEAEA"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[2]\,
I1 => \Use_BSCAN.PORT_Selector_reg[0]_0\(0),
I2 => \command_reg[0]\,
I3 => \Use_E2.BSCANE2_I_i_4_n_0\,
I4 => \command_reg[5]\,
I5 => \command_reg[0]_0\,
O => tdo
);
\Use_E2.BSCANE2_I_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEEBAAA"
)
port map (
I0 => \command_reg[3]\,
I1 => \command_reg[4]\(0),
I2 => \command_reg[4]\(2),
I3 => \Use_E2.BSCANE2_I_i_8_n_0\,
I4 => Dbg_TDO_0,
O => \Use_E2.BSCANE2_I_i_4_n_0\
);
\Use_E2.BSCANE2_I_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FACA0ACA"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[0]\(0),
I1 => \Use_unisim.MB_SRL16E_I1_n_0\,
I2 => \command_reg[4]\(1),
I3 => Q(4),
I4 => config_TDO_2,
O => \Use_E2.BSCANE2_I_i_8_n_0\
);
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0167",
IS_CLK_INVERTED => '0'
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => '0',
CLK => \Use_BSCAN.PORT_Selector_reg[0]\,
D => '0',
Q => \Use_unisim.MB_SRL16E_I1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_mdm_1_0_MB_SRL16E__parameterized1\ is
port (
config_TDO_2 : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\Use_BSCAN.PORT_Selector_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_mdm_1_0_MB_SRL16E__parameterized1\ : entity is "MB_SRL16E";
end \system_mdm_1_0_MB_SRL16E__parameterized1\;
architecture STRUCTURE of \system_mdm_1_0_MB_SRL16E__parameterized1\ is
attribute box_type : string;
attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MDM_Core_I1/JTAG_CONTROL_I/Use_Config_SRL16E.SRL16E_2/Use_unisim.MB_SRL16E_I1 ";
begin
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
generic map(
INIT => X"4287",
IS_CLK_INVERTED => '0'
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => '0',
CLK => \Use_BSCAN.PORT_Selector_reg[0]\,
D => '0',
Q => config_TDO_2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_mdm_1_0_MB_SRL16E__parameterized3\ is
port (
\tdi_shifter_reg[0]\ : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
\Use_BSCAN.PORT_Selector_reg[0]\ : in STD_LOGIC;
\command_reg[1]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
ID_TDO_2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_mdm_1_0_MB_SRL16E__parameterized3\ : entity is "MB_SRL16E";
end \system_mdm_1_0_MB_SRL16E__parameterized3\;
architecture STRUCTURE of \system_mdm_1_0_MB_SRL16E__parameterized3\ is
signal Q0_out : STD_LOGIC;
signal \Use_E2.BSCANE2_I_i_9_n_0\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MDM_Core_I1/JTAG_CONTROL_I/Use_ID_SRL16E.SRL16E_ID_1/Use_unisim.MB_SRL16E_I1 ";
begin
\Use_E2.BSCANE2_I_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFB88CC"
)
port map (
I0 => \command_reg[1]\(2),
I1 => \command_reg[1]\(1),
I2 => \command_reg[1]\(3),
I3 => \command_reg[1]\(4),
I4 => \command_reg[1]\(5),
I5 => \Use_E2.BSCANE2_I_i_9_n_0\,
O => \tdi_shifter_reg[0]\
);
\Use_E2.BSCANE2_I_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"0101010000000100"
)
port map (
I0 => \command_reg[1]\(1),
I1 => \command_reg[1]\(0),
I2 => \command_reg[1]\(2),
I3 => Q0_out,
I4 => Q(4),
I5 => ID_TDO_2,
O => \Use_E2.BSCANE2_I_i_9_n_0\
);
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
generic map(
INIT => X"4443",
IS_CLK_INVERTED => '0'
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => '0',
CLK => \Use_BSCAN.PORT_Selector_reg[0]\,
D => '0',
Q => Q0_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_mdm_1_0_MB_SRL16E__parameterized5\ is
port (
ID_TDO_2 : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\Use_BSCAN.PORT_Selector_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_mdm_1_0_MB_SRL16E__parameterized5\ : entity is "MB_SRL16E";
end \system_mdm_1_0_MB_SRL16E__parameterized5\;
architecture STRUCTURE of \system_mdm_1_0_MB_SRL16E__parameterized5\ is
attribute box_type : string;
attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MDM_Core_I1/JTAG_CONTROL_I/Use_ID_SRL16E.SRL16E_ID_2/Use_unisim.MB_SRL16E_I1 ";
begin
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
generic map(
INIT => X"584D",
IS_CLK_INVERTED => '0'
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => '0',
CLK => \Use_BSCAN.PORT_Selector_reg[0]\,
D => '0',
Q => ID_TDO_2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_mdm_1_0_JTAG_CONTROL is
port (
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
AR : out STD_LOGIC_VECTOR ( 0 to 0 );
Ext_NM_BRK : out STD_LOGIC;
Debug_SYS_Rst : out STD_LOGIC;
Dbg_Rst_0 : out STD_LOGIC;
Dbg_Shift_0 : out STD_LOGIC;
\p_20_out__0\ : out STD_LOGIC;
\Use_Serial_Unified_Completion.completion_block_reg_0\ : out STD_LOGIC;
Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
tdo : out STD_LOGIC;
\Use_Serial_Unified_Completion.count_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Use_Serial_Unified_Completion.completion_status_reg[15]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Use_BSCAN.PORT_Selector_reg[0]\ : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_0\ : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_1\ : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_2\ : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[2]\ : in STD_LOGIC;
Dbg_TDO_0 : in STD_LOGIC;
Scan_Reset : in STD_LOGIC;
Scan_Reset_Sel : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_3\ : in STD_LOGIC;
Ext_JTAG_TDI : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
\command_reg[5]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\Use_Serial_Unified_Completion.count_reg[5]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\shift_Count_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_mdm_1_0_JTAG_CONTROL : entity is "JTAG_CONTROL";
end system_mdm_1_0_JTAG_CONTROL;
architecture STRUCTURE of system_mdm_1_0_JTAG_CONTROL is
signal A1 : STD_LOGIC;
signal A2 : STD_LOGIC;
signal A3 : STD_LOGIC;
signal \^ar\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal CE : STD_LOGIC;
signal D_0 : STD_LOGIC;
signal \^dbg_rst_0\ : STD_LOGIC;
signal Dbg_Shift_31_INST_0_i_1_n_0 : STD_LOGIC;
signal Dbg_Shift_31_INST_0_i_3_n_0 : STD_LOGIC;
signal Dbg_Shift_31_INST_0_i_4_n_0 : STD_LOGIC;
signal \^debug_sys_rst\ : STD_LOGIC;
signal \^ext_nm_brk\ : STD_LOGIC;
signal Ext_NM_BRK_i_i_4_n_0 : STD_LOGIC;
signal FDC_I_n_15 : STD_LOGIC;
signal FDC_I_n_16 : STD_LOGIC;
signal FDC_I_n_17 : STD_LOGIC;
signal FDC_I_n_18 : STD_LOGIC;
signal FDC_I_n_30 : STD_LOGIC;
signal FDC_I_n_31 : STD_LOGIC;
signal FDC_I_n_32 : STD_LOGIC;
signal FDC_I_n_33 : STD_LOGIC;
signal FDC_I_n_34 : STD_LOGIC;
signal FDC_I_n_35 : STD_LOGIC;
signal FDC_I_n_36 : STD_LOGIC;
signal FDC_I_n_37 : STD_LOGIC;
signal FDC_I_n_38 : STD_LOGIC;
signal ID_TDO_2 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \Use_E2.BSCANE2_I_i_10_n_0\ : STD_LOGIC;
signal \Use_E2.BSCANE2_I_i_11_n_0\ : STD_LOGIC;
signal \Use_E2.BSCANE2_I_i_3_n_0\ : STD_LOGIC;
signal \Use_E2.BSCANE2_I_i_6_n_0\ : STD_LOGIC;
signal \Use_E2.BSCANE2_I_i_7_n_0\ : STD_LOGIC;
signal \Use_ID_SRL16E.SRL16E_ID_1_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.completion_block_i_2_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.completion_block_i_3_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.completion_block_i_4_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.completion_block_reg_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.completion_status[3]_i_2_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.completion_status[4]_i_2_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.completion_status[5]_i_2_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.completion_status[7]_i_2_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.completion_status[9]_i_4_n_0\ : STD_LOGIC;
signal \^use_serial_unified_completion.completion_status_reg[15]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \Use_Serial_Unified_Completion.count[0]__0_i_4_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.count[0]_i_1_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.count[1]_i_1_n_0\ : STD_LOGIC;
signal \^use_serial_unified_completion.count_reg[4]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \Use_Serial_Unified_Completion.count_reg__1\ : STD_LOGIC_VECTOR ( 0 to 4 );
signal \Use_Serial_Unified_Completion.count_reg_n_0_[0]\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.count_reg_n_0_[1]\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.mb_data_overrun_i_2_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.mb_data_overrun_i_3_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.mb_data_overrun_reg_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.mb_instr_error_reg_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.sample_1_reg_n_0_[10]\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.sample_1_reg_n_0_[11]\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.sample_1_reg_n_0_[12]\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.sample_1_reg_n_0_[13]\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.sample_1_reg_n_0_[14]\ : STD_LOGIC;
signal command : STD_LOGIC_VECTOR ( 0 to 7 );
signal \command[0]_i_1_n_0\ : STD_LOGIC;
signal command_1 : STD_LOGIC_VECTOR ( 0 to 7 );
signal command_10 : STD_LOGIC;
signal command_regn_0_0 : STD_LOGIC;
signal completion_ctrl : STD_LOGIC;
signal completion_status : STD_LOGIC_VECTOR ( 15 downto 0 );
signal config_TDO_2 : STD_LOGIC;
signal mb_instr_overrun : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 1 );
signal p_0_in_1 : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 4 downto 1 );
signal p_1_in : STD_LOGIC_VECTOR ( 14 downto 0 );
signal \p_22_out__0\ : STD_LOGIC;
signal sample : STD_LOGIC_VECTOR ( 15 downto 13 );
attribute async_reg : string;
attribute async_reg of sample : signal is "true";
signal sample_1 : STD_LOGIC;
signal sel_n : STD_LOGIC;
signal sel_n_i_1_n_0 : STD_LOGIC;
signal \shift_Count_reg__0\ : STD_LOGIC_VECTOR ( 4 to 4 );
signal \shifting_Data1__0\ : STD_LOGIC;
signal sync : STD_LOGIC;
signal tdi_shifter0 : STD_LOGIC;
signal \tdi_shifter_reg_n_0_[1]\ : STD_LOGIC;
signal \tdi_shifter_reg_n_0_[2]\ : STD_LOGIC;
signal \tdi_shifter_reg_n_0_[3]\ : STD_LOGIC;
signal \tdi_shifter_reg_n_0_[4]\ : STD_LOGIC;
signal \tdi_shifter_reg_n_0_[5]\ : STD_LOGIC;
signal \tdi_shifter_reg_n_0_[6]\ : STD_LOGIC;
signal \tdi_shifter_reg_n_0_[7]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Use_E2.BSCANE2_I_i_3\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \Use_E2.BSCANE2_I_i_6\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[11]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[12]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[13]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[14]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[4]_i_2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[5]_i_2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.count[0]__0_i_4\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.count[2]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.count[3]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.mb_data_overrun_i_2\ : label is "soft_lutpair13";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Use_Serial_Unified_Completion.sample_reg[13]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Use_Serial_Unified_Completion.sample_reg[13]\ : label is "yes";
attribute ASYNC_REG_boolean of \Use_Serial_Unified_Completion.sample_reg[14]\ : label is std.standard.true;
attribute KEEP of \Use_Serial_Unified_Completion.sample_reg[14]\ : label is "yes";
attribute ASYNC_REG_boolean of \Use_Serial_Unified_Completion.sample_reg[15]\ : label is std.standard.true;
attribute KEEP of \Use_Serial_Unified_Completion.sample_reg[15]\ : label is "yes";
attribute SOFT_HLUTNM of \shift_Count[2]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \shift_Count[3]_i_1\ : label is "soft_lutpair10";
begin
AR(0) <= \^ar\(0);
Dbg_Rst_0 <= \^dbg_rst_0\;
Debug_SYS_Rst <= \^debug_sys_rst\;
Ext_NM_BRK <= \^ext_nm_brk\;
Q(0) <= \^q\(0);
\Use_Serial_Unified_Completion.completion_status_reg[15]_0\(0) <= \^use_serial_unified_completion.completion_status_reg[15]_0\(0);
\Use_Serial_Unified_Completion.count_reg[4]_0\(0) <= \^use_serial_unified_completion.count_reg[4]_0\(0);
Dbg_Shift_31_INST_0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => command(6),
I1 => command(5),
I2 => command(7),
O => Dbg_Shift_31_INST_0_i_1_n_0
);
Dbg_Shift_31_INST_0_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => command(4),
I1 => command(2),
O => Dbg_Shift_31_INST_0_i_3_n_0
);
Dbg_Shift_31_INST_0_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => command(0),
I1 => command(1),
I2 => command(3),
O => Dbg_Shift_31_INST_0_i_4_n_0
);
Debug_Rst_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_36,
Q => \^dbg_rst_0\
);
Debug_SYS_Rst_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_37,
Q => \^debug_sys_rst\
);
Ext_NM_BRK_i_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => Scan_Reset,
I1 => Scan_Reset_Sel,
O => \^ar\(0)
);
Ext_NM_BRK_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => command(7),
I1 => command(4),
I2 => command(5),
I3 => command(3),
I4 => command(1),
I5 => command(0),
O => Ext_NM_BRK_i_i_4_n_0
);
Ext_NM_BRK_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_38,
Q => \^ext_nm_brk\
);
FDC_I: entity work.system_mdm_1_0_MB_FDC_1
port map (
CE => CE,
D(9 downto 0) => p_1_in(9 downto 0),
D_0 => D_0,
Dbg_Reg_En_0(0 to 7) => Dbg_Reg_En_0(0 to 7),
Dbg_Rst_0 => \^dbg_rst_0\,
Dbg_Shift_0 => Dbg_Shift_0,
Dbg_TDO_0 => Dbg_TDO_0,
Debug_Rst_i_reg => FDC_I_n_36,
Debug_SYS_Rst => \^debug_sys_rst\,
Debug_SYS_Rst_i_reg => FDC_I_n_37,
E(0) => FDC_I_n_15,
Ext_NM_BRK => \^ext_nm_brk\,
Ext_NM_BRK_i_reg => FDC_I_n_38,
Q(7) => command(0),
Q(6) => command(1),
Q(5) => command(2),
Q(4) => command(3),
Q(3) => command(4),
Q(2) => command(5),
Q(1) => command(6),
Q(0) => command(7),
\Use_BSCAN.PORT_Selector_reg[0]\ => \Use_BSCAN.PORT_Selector_reg[0]\,
\Use_BSCAN.PORT_Selector_reg[0]_0\ => \Use_BSCAN.PORT_Selector_reg[0]_1\,
\Use_BSCAN.PORT_Selector_reg[0]_1\ => \Use_BSCAN.PORT_Selector_reg[0]_2\,
\Use_BSCAN.PORT_Selector_reg[0]_2\ => \Use_BSCAN.PORT_Selector_reg[0]_3\,
\Use_BSCAN.PORT_Selector_reg[3]\(3 downto 0) => \Use_BSCAN.PORT_Selector_reg[3]\(3 downto 0),
\Use_Serial_Unified_Completion.completion_block_reg\ => \Use_Serial_Unified_Completion.completion_block_reg_0\,
\Use_Serial_Unified_Completion.completion_block_reg_0\ => FDC_I_n_35,
\Use_Serial_Unified_Completion.completion_block_reg_1\ => \Use_Serial_Unified_Completion.completion_block_reg_n_0\,
\Use_Serial_Unified_Completion.completion_status_reg[10]\(10 downto 0) => completion_status(10 downto 0),
\Use_Serial_Unified_Completion.completion_status_reg[2]\ => \Use_Serial_Unified_Completion.completion_status[3]_i_2_n_0\,
\Use_Serial_Unified_Completion.completion_status_reg[3]\ => \Use_Serial_Unified_Completion.completion_status[4]_i_2_n_0\,
\Use_Serial_Unified_Completion.completion_status_reg[4]\ => \Use_Serial_Unified_Completion.completion_status[5]_i_2_n_0\,
\Use_Serial_Unified_Completion.completion_status_reg[5]\ => \Use_Serial_Unified_Completion.completion_status[7]_i_2_n_0\,
\Use_Serial_Unified_Completion.completion_status_reg[7]\ => \Use_Serial_Unified_Completion.completion_status[9]_i_4_n_0\,
\Use_Serial_Unified_Completion.count_reg[1]\ => \Use_Serial_Unified_Completion.count_reg_n_0_[1]\,
\Use_Serial_Unified_Completion.count_reg[5]\ => \Use_Serial_Unified_Completion.mb_data_overrun_i_2_n_0\,
\Use_Serial_Unified_Completion.mb_data_overrun_reg\ => FDC_I_n_33,
\Use_Serial_Unified_Completion.mb_instr_error_reg\ => FDC_I_n_32,
\Use_Serial_Unified_Completion.mb_instr_overrun_reg\ => FDC_I_n_30,
\Use_Serial_Unified_Completion.mb_instr_overrun_reg_0\ => FDC_I_n_31,
\Use_Serial_Unified_Completion.sample_1_reg[15]\ => \Use_Serial_Unified_Completion.completion_block_i_2_n_0\,
\Use_Serial_Unified_Completion.sample_reg[15]\(2) => FDC_I_n_16,
\Use_Serial_Unified_Completion.sample_reg[15]\(1) => FDC_I_n_17,
\Use_Serial_Unified_Completion.sample_reg[15]\(0) => FDC_I_n_18,
\Use_Serial_Unified_Completion.sample_reg[15]_0\(5 downto 3) => sample(15 downto 13),
\Use_Serial_Unified_Completion.sample_reg[15]_0\(2) => \Use_Serial_Unified_Completion.mb_data_overrun_reg_n_0\,
\Use_Serial_Unified_Completion.sample_reg[15]_0\(1) => \Use_Serial_Unified_Completion.mb_instr_error_reg_n_0\,
\Use_Serial_Unified_Completion.sample_reg[15]_0\(0) => mb_instr_overrun,
\command_1_reg[7]\(0) => command_10,
\command_reg[0]\ => Dbg_Shift_31_INST_0_i_4_n_0,
\command_reg[4]\ => Dbg_Shift_31_INST_0_i_3_n_0,
\command_reg[6]\ => Dbg_Shift_31_INST_0_i_1_n_0,
\command_reg[7]\ => Ext_NM_BRK_i_i_4_n_0,
completion_ctrl => completion_ctrl,
\completion_ctrl_reg[0]\ => FDC_I_n_34,
\p_20_out__0\ => \p_20_out__0\,
\p_22_out__0\ => \p_22_out__0\,
sample_1 => sample_1,
sel => sel,
sel_n => sel_n,
\shifting_Data1__0\ => \shifting_Data1__0\,
sync => sync,
\tdi_shifter_reg[0]\(7) => p_0_in_1,
\tdi_shifter_reg[0]\(6) => \tdi_shifter_reg_n_0_[1]\,
\tdi_shifter_reg[0]\(5) => \tdi_shifter_reg_n_0_[2]\,
\tdi_shifter_reg[0]\(4) => \tdi_shifter_reg_n_0_[3]\,
\tdi_shifter_reg[0]\(3) => \tdi_shifter_reg_n_0_[4]\,
\tdi_shifter_reg[0]\(2) => \tdi_shifter_reg_n_0_[5]\,
\tdi_shifter_reg[0]\(1) => \tdi_shifter_reg_n_0_[6]\,
\tdi_shifter_reg[0]\(0) => \tdi_shifter_reg_n_0_[7]\
);
SYNC_FDRE: entity work.system_mdm_1_0_MB_FDRE_1
port map (
CE => CE,
D_0 => D_0,
\Use_BSCAN.PORT_Selector_reg[0]\ => \Use_BSCAN.PORT_Selector_reg[0]_0\,
\Use_BSCAN.PORT_Selector_reg[0]_0\ => \Use_BSCAN.PORT_Selector_reg[0]_1\,
\Use_Serial_Unified_Completion.completion_block_reg\ => FDC_I_n_30,
\Use_Serial_Unified_Completion.count_reg[0]\ => \Use_Serial_Unified_Completion.count_reg_n_0_[0]\,
\command_reg[0]\ => Dbg_Shift_31_INST_0_i_4_n_0,
\command_reg[6]\ => Dbg_Shift_31_INST_0_i_1_n_0,
\p_22_out__0\ => \p_22_out__0\,
sync => sync
);
\Use_Config_SRL16E.SRL16E_1\: entity work.system_mdm_1_0_MB_SRL16E
port map (
Dbg_TDO_0 => Dbg_TDO_0,
Q(4) => \shift_Count_reg__0\(4),
Q(3) => A3,
Q(2) => A2,
Q(1) => A1,
Q(0) => \^q\(0),
\Use_BSCAN.PORT_Selector_reg[0]\ => \Use_BSCAN.PORT_Selector_reg[0]_0\,
\Use_BSCAN.PORT_Selector_reg[0]_0\(0) => \Use_BSCAN.PORT_Selector_reg[3]\(0),
\Use_BSCAN.PORT_Selector_reg[2]\ => \Use_BSCAN.PORT_Selector_reg[2]\,
\Use_Serial_Unified_Completion.completion_status_reg[0]\(0) => completion_status(0),
\command_reg[0]\ => \Use_E2.BSCANE2_I_i_3_n_0\,
\command_reg[0]_0\ => \Use_E2.BSCANE2_I_i_6_n_0\,
\command_reg[3]\ => \Use_E2.BSCANE2_I_i_7_n_0\,
\command_reg[4]\(2) => command(4),
\command_reg[4]\(1) => command(5),
\command_reg[4]\(0) => command(7),
\command_reg[5]\ => \Use_ID_SRL16E.SRL16E_ID_1_n_0\,
config_TDO_2 => config_TDO_2,
tdo => tdo
);
\Use_Config_SRL16E.SRL16E_2\: entity work.\system_mdm_1_0_MB_SRL16E__parameterized1\
port map (
Q(3) => A3,
Q(2) => A2,
Q(1) => A1,
Q(0) => \^q\(0),
\Use_BSCAN.PORT_Selector_reg[0]\ => \Use_BSCAN.PORT_Selector_reg[0]_0\,
config_TDO_2 => config_TDO_2
);
\Use_E2.BSCANE2_I_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFCFFFFFFFFFF"
)
port map (
I0 => command(1),
I1 => command(3),
I2 => command(5),
I3 => command(4),
I4 => command(2),
I5 => command(6),
O => \Use_E2.BSCANE2_I_i_10_n_0\
);
\Use_E2.BSCANE2_I_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000010000001"
)
port map (
I0 => command(1),
I1 => command(3),
I2 => command(2),
I3 => command(6),
I4 => command(4),
I5 => command(5),
O => \Use_E2.BSCANE2_I_i_11_n_0\
);
\Use_E2.BSCANE2_I_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => command(0),
I1 => Dbg_TDO_0,
I2 => \Use_BSCAN.PORT_Selector_reg[3]\(1),
O => \Use_E2.BSCANE2_I_i_3_n_0\
);
\Use_E2.BSCANE2_I_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"00F8"
)
port map (
I0 => \Use_E2.BSCANE2_I_i_10_n_0\,
I1 => Dbg_TDO_0,
I2 => \Use_E2.BSCANE2_I_i_11_n_0\,
I3 => command(0),
O => \Use_E2.BSCANE2_I_i_6_n_0\
);
\Use_E2.BSCANE2_I_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"88BC88FFAABEAABE"
)
port map (
I0 => command(3),
I1 => command(4),
I2 => command(5),
I3 => command(6),
I4 => command(1),
I5 => command(2),
O => \Use_E2.BSCANE2_I_i_7_n_0\
);
\Use_ID_SRL16E.SRL16E_ID_1\: entity work.\system_mdm_1_0_MB_SRL16E__parameterized3\
port map (
ID_TDO_2 => ID_TDO_2,
Q(4) => \shift_Count_reg__0\(4),
Q(3) => A3,
Q(2) => A2,
Q(1) => A1,
Q(0) => \^q\(0),
\Use_BSCAN.PORT_Selector_reg[0]\ => \Use_BSCAN.PORT_Selector_reg[0]_0\,
\command_reg[1]\(5) => command(1),
\command_reg[1]\(4) => command(2),
\command_reg[1]\(3) => command(4),
\command_reg[1]\(2) => command(5),
\command_reg[1]\(1) => command(6),
\command_reg[1]\(0) => command(7),
\tdi_shifter_reg[0]\ => \Use_ID_SRL16E.SRL16E_ID_1_n_0\
);
\Use_ID_SRL16E.SRL16E_ID_2\: entity work.\system_mdm_1_0_MB_SRL16E__parameterized5\
port map (
ID_TDO_2 => ID_TDO_2,
Q(3) => A3,
Q(2) => A2,
Q(1) => A1,
Q(0) => \^q\(0),
\Use_BSCAN.PORT_Selector_reg[0]\ => \Use_BSCAN.PORT_Selector_reg[0]_0\
);
\Use_Serial_Unified_Completion.completion_block_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFBAFFBABA"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_i_3_n_0\,
I1 => \^use_serial_unified_completion.completion_status_reg[15]_0\(0),
I2 => sample(15),
I3 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[10]\,
I4 => mb_instr_overrun,
I5 => \Use_Serial_Unified_Completion.completion_block_i_4_n_0\,
O => \Use_Serial_Unified_Completion.completion_block_i_2_n_0\
);
\Use_Serial_Unified_Completion.completion_block_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[11]\,
I1 => \Use_Serial_Unified_Completion.mb_instr_error_reg_n_0\,
I2 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[13]\,
I3 => sample(13),
O => \Use_Serial_Unified_Completion.completion_block_i_3_n_0\
);
\Use_Serial_Unified_Completion.completion_block_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[12]\,
I1 => \Use_Serial_Unified_Completion.mb_data_overrun_reg_n_0\,
I2 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[14]\,
I3 => sample(14),
O => \Use_Serial_Unified_Completion.completion_block_i_4_n_0\
);
\Use_Serial_Unified_Completion.completion_block_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_35,
Q => \Use_Serial_Unified_Completion.completion_block_reg_n_0\
);
\Use_Serial_Unified_Completion.completion_status[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[10]\,
I1 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I2 => completion_status(11),
O => p_1_in(10)
);
\Use_Serial_Unified_Completion.completion_status[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[11]\,
I1 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I2 => completion_status(12),
O => p_1_in(11)
);
\Use_Serial_Unified_Completion.completion_status[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[12]\,
I1 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I2 => completion_status(13),
O => p_1_in(12)
);
\Use_Serial_Unified_Completion.completion_status[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[13]\,
I1 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I2 => completion_status(14),
O => p_1_in(13)
);
\Use_Serial_Unified_Completion.completion_status[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[14]\,
I1 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I2 => completion_status(15),
O => p_1_in(14)
);
\Use_Serial_Unified_Completion.completion_status[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => completion_status(2),
I1 => completion_status(0),
I2 => completion_status(1),
O => \Use_Serial_Unified_Completion.completion_status[3]_i_2_n_0\
);
\Use_Serial_Unified_Completion.completion_status[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => completion_status(3),
I1 => completion_status(1),
I2 => completion_status(0),
I3 => completion_status(2),
O => \Use_Serial_Unified_Completion.completion_status[4]_i_2_n_0\
);
\Use_Serial_Unified_Completion.completion_status[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => completion_status(4),
I1 => completion_status(2),
I2 => completion_status(0),
I3 => completion_status(1),
I4 => completion_status(3),
O => \Use_Serial_Unified_Completion.completion_status[5]_i_2_n_0\
);
\Use_Serial_Unified_Completion.completion_status[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => completion_status(5),
I1 => completion_status(3),
I2 => completion_status(1),
I3 => completion_status(0),
I4 => completion_status(2),
I5 => completion_status(4),
O => \Use_Serial_Unified_Completion.completion_status[7]_i_2_n_0\
);
\Use_Serial_Unified_Completion.completion_status[9]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => completion_status(7),
I1 => \Use_Serial_Unified_Completion.completion_status[7]_i_2_n_0\,
I2 => completion_status(6),
O => \Use_Serial_Unified_Completion.completion_status[9]_i_4_n_0\
);
\Use_Serial_Unified_Completion.completion_status_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(0),
Q => completion_status(0)
);
\Use_Serial_Unified_Completion.completion_status_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => E(0),
CLR => \^ar\(0),
D => p_1_in(10),
Q => completion_status(10)
);
\Use_Serial_Unified_Completion.completion_status_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => E(0),
CLR => \^ar\(0),
D => p_1_in(11),
Q => completion_status(11)
);
\Use_Serial_Unified_Completion.completion_status_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => E(0),
CLR => \^ar\(0),
D => p_1_in(12),
Q => completion_status(12)
);
\Use_Serial_Unified_Completion.completion_status_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => E(0),
CLR => \^ar\(0),
D => p_1_in(13),
Q => completion_status(13)
);
\Use_Serial_Unified_Completion.completion_status_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => E(0),
CLR => \^ar\(0),
D => p_1_in(14),
Q => completion_status(14)
);
\Use_Serial_Unified_Completion.completion_status_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => E(0),
CLR => \^ar\(0),
D => D(0),
Q => completion_status(15)
);
\Use_Serial_Unified_Completion.completion_status_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(1),
Q => completion_status(1)
);
\Use_Serial_Unified_Completion.completion_status_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(2),
Q => completion_status(2)
);
\Use_Serial_Unified_Completion.completion_status_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(3),
Q => completion_status(3)
);
\Use_Serial_Unified_Completion.completion_status_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(4),
Q => completion_status(4)
);
\Use_Serial_Unified_Completion.completion_status_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(5),
Q => completion_status(5)
);
\Use_Serial_Unified_Completion.completion_status_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(6),
Q => completion_status(6)
);
\Use_Serial_Unified_Completion.completion_status_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(7),
Q => completion_status(7)
);
\Use_Serial_Unified_Completion.completion_status_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(8),
Q => completion_status(8)
);
\Use_Serial_Unified_Completion.completion_status_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(9),
Q => completion_status(9)
);
\Use_Serial_Unified_Completion.count[0]__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0078"
)
port map (
I0 => \Use_Serial_Unified_Completion.count_reg__1\(1),
I1 => \Use_Serial_Unified_Completion.count[0]__0_i_4_n_0\,
I2 => \Use_Serial_Unified_Completion.count_reg__1\(0),
I3 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
O => p_0_in(5)
);
\Use_Serial_Unified_Completion.count[0]__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \Use_Serial_Unified_Completion.count_reg__1\(2),
I1 => \Use_Serial_Unified_Completion.count_reg__1\(4),
I2 => \^use_serial_unified_completion.count_reg[4]_0\(0),
I3 => \Use_Serial_Unified_Completion.count_reg__1\(3),
O => \Use_Serial_Unified_Completion.count[0]__0_i_4_n_0\
);
\Use_Serial_Unified_Completion.count[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FF80FF00FF00"
)
port map (
I0 => \Use_Serial_Unified_Completion.count_reg_n_0_[1]\,
I1 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I2 => sync,
I3 => \Use_Serial_Unified_Completion.count_reg_n_0_[0]\,
I4 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I5 => \shifting_Data1__0\,
O => \Use_Serial_Unified_Completion.count[0]_i_1_n_0\
);
\Use_Serial_Unified_Completion.count[1]__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000007FFF8000"
)
port map (
I0 => \Use_Serial_Unified_Completion.count_reg__1\(2),
I1 => \Use_Serial_Unified_Completion.count_reg__1\(4),
I2 => \^use_serial_unified_completion.count_reg[4]_0\(0),
I3 => \Use_Serial_Unified_Completion.count_reg__1\(3),
I4 => \Use_Serial_Unified_Completion.count_reg__1\(1),
I5 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
O => p_0_in(4)
);
\Use_Serial_Unified_Completion.count[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00F7FFFF00080000"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I1 => sync,
I2 => \Use_Serial_Unified_Completion.count_reg_n_0_[0]\,
I3 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I4 => \shifting_Data1__0\,
I5 => \Use_Serial_Unified_Completion.count_reg_n_0_[1]\,
O => \Use_Serial_Unified_Completion.count[1]_i_1_n_0\
);
\Use_Serial_Unified_Completion.count[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00007F80"
)
port map (
I0 => \Use_Serial_Unified_Completion.count_reg__1\(3),
I1 => \^use_serial_unified_completion.count_reg[4]_0\(0),
I2 => \Use_Serial_Unified_Completion.count_reg__1\(4),
I3 => \Use_Serial_Unified_Completion.count_reg__1\(2),
I4 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
O => p_0_in(3)
);
\Use_Serial_Unified_Completion.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0078"
)
port map (
I0 => \Use_Serial_Unified_Completion.count_reg__1\(4),
I1 => \^use_serial_unified_completion.count_reg[4]_0\(0),
I2 => \Use_Serial_Unified_Completion.count_reg__1\(3),
I3 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
O => p_0_in(2)
);
\Use_Serial_Unified_Completion.count[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"06"
)
port map (
I0 => \^use_serial_unified_completion.count_reg[4]_0\(0),
I1 => \Use_Serial_Unified_Completion.count_reg__1\(4),
I2 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
O => p_0_in(1)
);
\Use_Serial_Unified_Completion.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => \Use_Serial_Unified_Completion.count[0]_i_1_n_0\,
Q => \Use_Serial_Unified_Completion.count_reg_n_0_[0]\
);
\Use_Serial_Unified_Completion.count_reg[0]__0\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => \command_reg[5]_0\(0),
CLR => \^ar\(0),
D => p_0_in(5),
Q => \Use_Serial_Unified_Completion.count_reg__1\(0)
);
\Use_Serial_Unified_Completion.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => \Use_Serial_Unified_Completion.count[1]_i_1_n_0\,
Q => \Use_Serial_Unified_Completion.count_reg_n_0_[1]\
);
\Use_Serial_Unified_Completion.count_reg[1]__0\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => \command_reg[5]_0\(0),
CLR => \^ar\(0),
D => p_0_in(4),
Q => \Use_Serial_Unified_Completion.count_reg__1\(1)
);
\Use_Serial_Unified_Completion.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => \command_reg[5]_0\(0),
CLR => \^ar\(0),
D => p_0_in(3),
Q => \Use_Serial_Unified_Completion.count_reg__1\(2)
);
\Use_Serial_Unified_Completion.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => \command_reg[5]_0\(0),
CLR => \^ar\(0),
D => p_0_in(2),
Q => \Use_Serial_Unified_Completion.count_reg__1\(3)
);
\Use_Serial_Unified_Completion.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => \command_reg[5]_0\(0),
CLR => \^ar\(0),
D => p_0_in(1),
Q => \Use_Serial_Unified_Completion.count_reg__1\(4)
);
\Use_Serial_Unified_Completion.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => \command_reg[5]_0\(0),
CLR => \^ar\(0),
D => \Use_Serial_Unified_Completion.count_reg[5]_0\(0),
Q => \^use_serial_unified_completion.count_reg[4]_0\(0)
);
\Use_Serial_Unified_Completion.mb_data_overrun_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \Use_Serial_Unified_Completion.mb_data_overrun_i_3_n_0\,
I1 => \^use_serial_unified_completion.count_reg[4]_0\(0),
I2 => \Use_Serial_Unified_Completion.count_reg__1\(4),
I3 => \Use_Serial_Unified_Completion.count_reg__1\(3),
O => \Use_Serial_Unified_Completion.mb_data_overrun_i_2_n_0\
);
\Use_Serial_Unified_Completion.mb_data_overrun_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I1 => \Use_Serial_Unified_Completion.count_reg__1\(0),
I2 => \Use_Serial_Unified_Completion.count_reg__1\(1),
I3 => \Use_Serial_Unified_Completion.count_reg__1\(2),
O => \Use_Serial_Unified_Completion.mb_data_overrun_i_3_n_0\
);
\Use_Serial_Unified_Completion.mb_data_overrun_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_33,
Q => \Use_Serial_Unified_Completion.mb_data_overrun_reg_n_0\
);
\Use_Serial_Unified_Completion.mb_instr_error_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_32,
Q => \Use_Serial_Unified_Completion.mb_instr_error_reg_n_0\
);
\Use_Serial_Unified_Completion.mb_instr_overrun_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_31,
Q => mb_instr_overrun
);
\Use_Serial_Unified_Completion.sample_1_reg[10]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => sample_1,
CLR => \^ar\(0),
D => mb_instr_overrun,
Q => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[10]\
);
\Use_Serial_Unified_Completion.sample_1_reg[11]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => sample_1,
CLR => \^ar\(0),
D => \Use_Serial_Unified_Completion.mb_instr_error_reg_n_0\,
Q => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[11]\
);
\Use_Serial_Unified_Completion.sample_1_reg[12]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => sample_1,
CLR => \^ar\(0),
D => \Use_Serial_Unified_Completion.mb_data_overrun_reg_n_0\,
Q => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[12]\
);
\Use_Serial_Unified_Completion.sample_1_reg[13]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => sample_1,
CLR => \^ar\(0),
D => sample(13),
Q => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[13]\
);
\Use_Serial_Unified_Completion.sample_1_reg[14]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => sample_1,
CLR => \^ar\(0),
D => sample(14),
Q => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[14]\
);
\Use_Serial_Unified_Completion.sample_1_reg[15]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => sample_1,
CLR => \^ar\(0),
D => sample(15),
Q => \^use_serial_unified_completion.completion_status_reg[15]_0\(0)
);
\Use_Serial_Unified_Completion.sample_reg[13]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_18,
Q => sample(13)
);
\Use_Serial_Unified_Completion.sample_reg[14]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_17,
Q => sample(14)
);
\Use_Serial_Unified_Completion.sample_reg[15]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_16,
Q => sample(15)
);
\command[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000008"
)
port map (
I0 => sel,
I1 => \Use_BSCAN.PORT_Selector_reg[3]\(0),
I2 => \Use_BSCAN.PORT_Selector_reg[3]\(1),
I3 => \Use_BSCAN.PORT_Selector_reg[3]\(3),
I4 => \Use_BSCAN.PORT_Selector_reg[3]\(2),
O => \command[0]_i_1_n_0\
);
\command_1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => command_10,
CLR => \^ar\(0),
D => p_0_in_1,
Q => command_1(0)
);
\command_1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => command_10,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[1]\,
Q => command_1(1)
);
\command_1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => command_10,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[2]\,
Q => command_1(2)
);
\command_1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => command_10,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[3]\,
Q => command_1(3)
);
\command_1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => command_10,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[4]\,
Q => command_1(4)
);
\command_1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => command_10,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[5]\,
Q => command_1(5)
);
\command_1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => command_10,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[6]\,
Q => command_1(6)
);
\command_1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => command_10,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[7]\,
Q => command_1(7)
);
\command_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => command_regn_0_0,
CE => \command[0]_i_1_n_0\,
CLR => \^ar\(0),
D => command_1(0),
Q => command(0)
);
\command_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => command_regn_0_0,
CE => \command[0]_i_1_n_0\,
CLR => \^ar\(0),
D => command_1(1),
Q => command(1)
);
\command_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => command_regn_0_0,
CE => \command[0]_i_1_n_0\,
CLR => \^ar\(0),
D => command_1(2),
Q => command(2)
);
\command_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => command_regn_0_0,
CE => \command[0]_i_1_n_0\,
CLR => \^ar\(0),
D => command_1(3),
Q => command(3)
);
\command_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => command_regn_0_0,
CE => \command[0]_i_1_n_0\,
CLR => \^ar\(0),
D => command_1(4),
Q => command(4)
);
\command_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => command_regn_0_0,
CE => \command[0]_i_1_n_0\,
CLR => \^ar\(0),
D => command_1(5),
Q => command(5)
);
\command_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => command_regn_0_0,
CE => \command[0]_i_1_n_0\,
CLR => \^ar\(0),
D => command_1(6),
Q => command(6)
);
\command_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => command_regn_0_0,
CE => \command[0]_i_1_n_0\,
CLR => \^ar\(0),
D => command_1(7),
Q => command(7)
);
command_regi_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[0]\,
O => command_regn_0_0
);
\completion_ctrl_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_34,
Q => completion_ctrl
);
sel_n_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \command[0]_i_1_n_0\,
I1 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I2 => sel_n,
O => sel_n_i_1_n_0
);
sel_n_reg: unisim.vcomponents.FDPE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
D => sel_n_i_1_n_0,
PRE => \^ar\(0),
Q => sel_n
);
\shift_Count[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"48"
)
port map (
I0 => \^q\(0),
I1 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I2 => A1,
O => \p_0_in__0\(1)
);
\shift_Count[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7080"
)
port map (
I0 => A1,
I1 => \^q\(0),
I2 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I3 => A2,
O => \p_0_in__0\(2)
);
\shift_Count[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F008000"
)
port map (
I0 => A2,
I1 => \^q\(0),
I2 => A1,
I3 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I4 => A3,
O => \p_0_in__0\(3)
);
\shift_Count[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => A3,
I1 => A1,
I2 => \^q\(0),
I3 => A2,
I4 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I5 => \shift_Count_reg__0\(4),
O => \p_0_in__0\(4)
);
\shift_Count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => \shift_Count_reg[0]_0\(0),
Q => \^q\(0)
);
\shift_Count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => \p_0_in__0\(1),
Q => A1
);
\shift_Count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => \p_0_in__0\(2),
Q => A2
);
\shift_Count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => \p_0_in__0\(3),
Q => A3
);
\shift_Count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => \p_0_in__0\(4),
Q => \shift_Count_reg__0\(4)
);
\tdi_shifter[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[3]\(2),
I1 => \Use_BSCAN.PORT_Selector_reg[3]\(3),
I2 => \Use_BSCAN.PORT_Selector_reg[3]\(1),
I3 => \Use_BSCAN.PORT_Selector_reg[3]\(0),
I4 => sel,
I5 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
O => tdi_shifter0
);
\tdi_shifter_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => tdi_shifter0,
CLR => \^ar\(0),
D => Ext_JTAG_TDI,
Q => p_0_in_1
);
\tdi_shifter_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => tdi_shifter0,
CLR => \^ar\(0),
D => p_0_in_1,
Q => \tdi_shifter_reg_n_0_[1]\
);
\tdi_shifter_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => tdi_shifter0,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[1]\,
Q => \tdi_shifter_reg_n_0_[2]\
);
\tdi_shifter_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => tdi_shifter0,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[2]\,
Q => \tdi_shifter_reg_n_0_[3]\
);
\tdi_shifter_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => tdi_shifter0,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[3]\,
Q => \tdi_shifter_reg_n_0_[4]\
);
\tdi_shifter_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => tdi_shifter0,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[4]\,
Q => \tdi_shifter_reg_n_0_[5]\
);
\tdi_shifter_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => tdi_shifter0,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[5]\,
Q => \tdi_shifter_reg_n_0_[6]\
);
\tdi_shifter_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => tdi_shifter0,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[6]\,
Q => \tdi_shifter_reg_n_0_[7]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_mdm_1_0_MDM_Core is
port (
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
Dbg_Disable_0 : out STD_LOGIC;
Ext_NM_BRK : out STD_LOGIC;
Debug_SYS_Rst : out STD_LOGIC;
Dbg_Rst_0 : out STD_LOGIC;
Dbg_Shift_0 : out STD_LOGIC;
\p_20_out__0\ : out STD_LOGIC;
\p_43_out__0\ : out STD_LOGIC;
Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
tdo : out STD_LOGIC;
Ext_JTAG_SEL : out STD_LOGIC;
\Use_Serial_Unified_Completion.count_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Use_Serial_Unified_Completion.completion_status_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Use_BSCAN.PORT_Selector_reg[0]_0\ : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_1\ : in STD_LOGIC;
shift_n_reset : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_2\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
\Use_BSCAN.PORT_Selector_reg[0]_3\ : in STD_LOGIC;
sel : in STD_LOGIC;
Dbg_TDO_0 : in STD_LOGIC;
Ext_JTAG_TDO : in STD_LOGIC;
\Use_Serial_Unified_Completion.count_reg[5]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\shift_Count_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Scan_Reset : in STD_LOGIC;
Scan_Reset_Sel : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_4\ : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
Ext_JTAG_TDI : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\command_reg[5]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_mdm_1_0_MDM_Core : entity is "MDM_Core";
end system_mdm_1_0_MDM_Core;
architecture STRUCTURE of system_mdm_1_0_MDM_Core is
signal Config_Reg : STD_LOGIC_VECTOR ( 0 to 0 );
signal MDM_SEL : STD_LOGIC;
signal PORT_Selector : STD_LOGIC_VECTOR ( 3 downto 0 );
signal PORT_Selector_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal TDI_Shifter : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \Use_BSCAN.Config_Reg_reg[11]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_12_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg[27]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_1_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg[4]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_3_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_0_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_10_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_11_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_12_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_1_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_2_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_3_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_4_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_5_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_6_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_7_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_8_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_9_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_gate__0_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_gate__1_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_gate_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_n_0_[10]\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_n_0_[1]\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_n_0_[25]\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_n_0_[26]\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_n_0_[2]\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_n_0_[30]\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_n_0_[3]\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_n_0_[9]\ : STD_LOGIC;
signal \Use_BSCAN.PORT_Selector_regn_0_0\ : STD_LOGIC;
signal \Use_E2.BSCANE2_I_i_2_n_0\ : STD_LOGIC;
signal config_with_scan_reset : STD_LOGIC;
signal p_0_out : STD_LOGIC;
attribute srl_bus_name : string;
attribute srl_bus_name of \Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11\ : label is "U0/\MDM_Core_I1/Use_BSCAN.Config_Reg_reg ";
attribute srl_name : string;
attribute srl_name of \Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11\ : label is "U0/\MDM_Core_I1/Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11 ";
attribute srl_bus_name of \Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0\ : label is "U0/\MDM_Core_I1/Use_BSCAN.Config_Reg_reg ";
attribute srl_name of \Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0\ : label is "U0/\MDM_Core_I1/Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0 ";
attribute srl_bus_name of \Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2\ : label is "U0/\MDM_Core_I1/Use_BSCAN.Config_Reg_reg ";
attribute srl_name of \Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2\ : label is "U0/\MDM_Core_I1/Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2 ";
begin
Ext_JTAG_SEL_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"00000008"
)
port map (
I0 => sel,
I1 => PORT_Selector(1),
I2 => PORT_Selector(0),
I3 => PORT_Selector(3),
I4 => PORT_Selector(2),
O => Ext_JTAG_SEL
);
JTAG_CONTROL_I: entity work.system_mdm_1_0_JTAG_CONTROL
port map (
AR(0) => config_with_scan_reset,
D(0) => D(0),
Dbg_Reg_En_0(0 to 7) => Dbg_Reg_En_0(0 to 7),
Dbg_Rst_0 => Dbg_Rst_0,
Dbg_Shift_0 => Dbg_Shift_0,
Dbg_TDO_0 => Dbg_TDO_0,
Debug_SYS_Rst => Debug_SYS_Rst,
E(0) => E(0),
Ext_JTAG_TDI => Ext_JTAG_TDI,
Ext_NM_BRK => Ext_NM_BRK,
Q(0) => Q(0),
Scan_Reset => Scan_Reset,
Scan_Reset_Sel => Scan_Reset_Sel,
\Use_BSCAN.PORT_Selector_reg[0]\ => \Use_BSCAN.PORT_Selector_reg[0]_0\,
\Use_BSCAN.PORT_Selector_reg[0]_0\ => \Use_BSCAN.PORT_Selector_reg[0]_1\,
\Use_BSCAN.PORT_Selector_reg[0]_1\ => \Use_BSCAN.PORT_Selector_reg[0]_2\,
\Use_BSCAN.PORT_Selector_reg[0]_2\ => \Use_BSCAN.PORT_Selector_reg[0]_3\,
\Use_BSCAN.PORT_Selector_reg[0]_3\ => \Use_BSCAN.PORT_Selector_reg[0]_4\,
\Use_BSCAN.PORT_Selector_reg[2]\ => \Use_E2.BSCANE2_I_i_2_n_0\,
\Use_BSCAN.PORT_Selector_reg[3]\(3 downto 0) => PORT_Selector(3 downto 0),
\Use_Serial_Unified_Completion.completion_block_reg_0\ => \p_43_out__0\,
\Use_Serial_Unified_Completion.completion_status_reg[15]_0\(0) => \Use_Serial_Unified_Completion.completion_status_reg[15]\(0),
\Use_Serial_Unified_Completion.count_reg[4]_0\(0) => \Use_Serial_Unified_Completion.count_reg[4]\(0),
\Use_Serial_Unified_Completion.count_reg[5]_0\(0) => \Use_Serial_Unified_Completion.count_reg[5]\(0),
\command_reg[5]_0\(0) => \command_reg[5]\(0),
\p_20_out__0\ => \p_20_out__0\,
sel => sel,
\shift_Count_reg[0]_0\(0) => \shift_Count_reg[0]\(0),
tdo => tdo
);
\Use_BSCAN.Config_Reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_n_0_[1]\,
Q => Config_Reg(0)
);
\Use_BSCAN.Config_Reg_reg[10]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_gate__0_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_n_0_[10]\
);
\Use_BSCAN.Config_Reg_reg[11]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_12\: unisim.vcomponents.FDRE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
D => \Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11_n_0\,
Q => \Use_BSCAN.Config_Reg_reg[11]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_12_n_0\,
R => '0'
);
\Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '0',
A1 => '0',
A2 => '1',
A3 => '1',
CE => '1',
CLK => \Use_BSCAN.PORT_Selector_reg[0]_1\,
D => \Use_BSCAN.Config_Reg_reg_n_0_[25]\,
Q => \Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11_n_0\
);
\Use_BSCAN.Config_Reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
D => \Use_BSCAN.Config_Reg_reg_n_0_[2]\,
PRE => shift_n_reset,
Q => \Use_BSCAN.Config_Reg_reg_n_0_[1]\
);
\Use_BSCAN.Config_Reg_reg[25]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
D => \Use_BSCAN.Config_Reg_reg_n_0_[26]\,
PRE => shift_n_reset,
Q => \Use_BSCAN.Config_Reg_reg_n_0_[25]\
);
\Use_BSCAN.Config_Reg_reg[26]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_gate_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_n_0_[26]\
);
\Use_BSCAN.Config_Reg_reg[27]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_1\: unisim.vcomponents.FDRE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
D => \Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0_n_0\,
Q => \Use_BSCAN.Config_Reg_reg[27]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_1_n_0\,
R => '0'
);
\Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => '1',
CLK => \Use_BSCAN.PORT_Selector_reg[0]_1\,
D => \Use_BSCAN.Config_Reg_reg_n_0_[30]\,
Q => \Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0_n_0\
);
\Use_BSCAN.Config_Reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
D => \Use_BSCAN.Config_Reg_reg_n_0_[3]\,
PRE => shift_n_reset,
Q => \Use_BSCAN.Config_Reg_reg_n_0_[2]\
);
\Use_BSCAN.Config_Reg_reg[30]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
D => '0',
PRE => shift_n_reset,
Q => \Use_BSCAN.Config_Reg_reg_n_0_[30]\
);
\Use_BSCAN.Config_Reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_gate__1_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_n_0_[3]\
);
\Use_BSCAN.Config_Reg_reg[4]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_3\: unisim.vcomponents.FDRE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
D => \Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2_n_0\,
Q => \Use_BSCAN.Config_Reg_reg[4]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_3_n_0\,
R => '0'
);
\Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '1',
A2 => '0',
A3 => '0',
CE => '1',
CLK => \Use_BSCAN.PORT_Selector_reg[0]_1\,
D => \Use_BSCAN.Config_Reg_reg_n_0_[9]\,
Q => \Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2_n_0\
);
\Use_BSCAN.Config_Reg_reg[9]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
D => \Use_BSCAN.Config_Reg_reg_n_0_[10]\,
PRE => shift_n_reset,
Q => \Use_BSCAN.Config_Reg_reg_n_0_[9]\
);
\Use_BSCAN.Config_Reg_reg_c\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => '1',
Q => \Use_BSCAN.Config_Reg_reg_c_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_0\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_0_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_1\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_0_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_1_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_10\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_9_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_10_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_11\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_10_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_11_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_12\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_11_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_12_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_2\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_1_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_2_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_3\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_2_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_3_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_4\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_3_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_4_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_5\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_4_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_5_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_6\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_5_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_6_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_7\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_6_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_7_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_8\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_7_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_8_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_9\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_8_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_9_n_0\
);
\Use_BSCAN.Config_Reg_reg_gate\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \Use_BSCAN.Config_Reg_reg[27]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_1_n_0\,
I1 => \Use_BSCAN.Config_Reg_reg_c_1_n_0\,
O => \Use_BSCAN.Config_Reg_reg_gate_n_0\
);
\Use_BSCAN.Config_Reg_reg_gate__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \Use_BSCAN.Config_Reg_reg[11]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_12_n_0\,
I1 => \Use_BSCAN.Config_Reg_reg_c_12_n_0\,
O => \Use_BSCAN.Config_Reg_reg_gate__0_n_0\
);
\Use_BSCAN.Config_Reg_reg_gate__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \Use_BSCAN.Config_Reg_reg[4]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_3_n_0\,
I1 => \Use_BSCAN.Config_Reg_reg_c_3_n_0\,
O => \Use_BSCAN.Config_Reg_reg_gate__1_n_0\
);
\Use_BSCAN.PORT_Selector_1[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => sel,
I1 => PORT_Selector(0),
I2 => PORT_Selector(1),
I3 => PORT_Selector(3),
I4 => PORT_Selector(2),
O => MDM_SEL
);
\Use_BSCAN.PORT_Selector_1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => MDM_SEL,
CLR => AR(0),
D => TDI_Shifter(0),
Q => PORT_Selector_1(0)
);
\Use_BSCAN.PORT_Selector_1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => MDM_SEL,
CLR => AR(0),
D => TDI_Shifter(1),
Q => PORT_Selector_1(1)
);
\Use_BSCAN.PORT_Selector_1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => MDM_SEL,
CLR => AR(0),
D => TDI_Shifter(2),
Q => PORT_Selector_1(2)
);
\Use_BSCAN.PORT_Selector_1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => MDM_SEL,
CLR => AR(0),
D => TDI_Shifter(3),
Q => PORT_Selector_1(3)
);
\Use_BSCAN.PORT_Selector_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_regn_0_0\,
CE => '1',
CLR => AR(0),
D => PORT_Selector_1(0),
Q => PORT_Selector(0)
);
\Use_BSCAN.PORT_Selector_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_regn_0_0\,
CE => '1',
CLR => AR(0),
D => PORT_Selector_1(1),
Q => PORT_Selector(1)
);
\Use_BSCAN.PORT_Selector_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_regn_0_0\,
CE => '1',
CLR => AR(0),
D => PORT_Selector_1(2),
Q => PORT_Selector(2)
);
\Use_BSCAN.PORT_Selector_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_regn_0_0\,
CE => '1',
CLR => AR(0),
D => PORT_Selector_1(3),
Q => PORT_Selector(3)
);
\Use_BSCAN.PORT_Selector_regi_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[0]_0\,
O => \Use_BSCAN.PORT_Selector_regn_0_0\
);
\Use_BSCAN.TDI_Shifter[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => PORT_Selector(2),
I1 => PORT_Selector(3),
I2 => PORT_Selector(1),
I3 => PORT_Selector(0),
I4 => sel,
I5 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
O => p_0_out
);
\Use_BSCAN.TDI_Shifter_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => p_0_out,
CLR => AR(0),
D => TDI_Shifter(1),
Q => TDI_Shifter(0)
);
\Use_BSCAN.TDI_Shifter_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => p_0_out,
CLR => AR(0),
D => TDI_Shifter(2),
Q => TDI_Shifter(1)
);
\Use_BSCAN.TDI_Shifter_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => p_0_out,
CLR => AR(0),
D => TDI_Shifter(3),
Q => TDI_Shifter(2)
);
\Use_BSCAN.TDI_Shifter_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => p_0_out,
CLR => AR(0),
D => Ext_JTAG_TDI,
Q => TDI_Shifter(3)
);
\Use_BSCAN.jtag_disable_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
D => '0',
PRE => config_with_scan_reset,
Q => Dbg_Disable_0
);
\Use_E2.BSCANE2_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFEEEFFEEEE"
)
port map (
I0 => PORT_Selector(2),
I1 => PORT_Selector(3),
I2 => Ext_JTAG_TDO,
I3 => PORT_Selector(0),
I4 => Config_Reg(0),
I5 => PORT_Selector(1),
O => \Use_E2.BSCANE2_I_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_mdm_1_0_MDM is
port (
Config_Reset : in STD_LOGIC;
Scan_Reset_Sel : in STD_LOGIC;
Scan_Reset : in STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
M_AXI_ACLK : in STD_LOGIC;
M_AXI_ARESETN : in STD_LOGIC;
M_AXIS_ACLK : in STD_LOGIC;
M_AXIS_ARESETN : in STD_LOGIC;
Interrupt : out STD_LOGIC;
Ext_BRK : out STD_LOGIC;
Ext_NM_BRK : out STD_LOGIC;
Debug_SYS_Rst : out STD_LOGIC;
Trig_In_0 : in STD_LOGIC;
Trig_Ack_In_0 : out STD_LOGIC;
Trig_Out_0 : out STD_LOGIC;
Trig_Ack_Out_0 : in STD_LOGIC;
Trig_In_1 : in STD_LOGIC;
Trig_Ack_In_1 : out STD_LOGIC;
Trig_Out_1 : out STD_LOGIC;
Trig_Ack_Out_1 : in STD_LOGIC;
Trig_In_2 : in STD_LOGIC;
Trig_Ack_In_2 : out STD_LOGIC;
Trig_Out_2 : out STD_LOGIC;
Trig_Ack_Out_2 : in STD_LOGIC;
Trig_In_3 : in STD_LOGIC;
Trig_Ack_In_3 : out STD_LOGIC;
Trig_Out_3 : out STD_LOGIC;
Trig_Ack_Out_3 : in STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_BVALID : out STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_AWLOCK : out STD_LOGIC;
M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_AWVALID : out STD_LOGIC;
M_AXI_AWREADY : in STD_LOGIC;
M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_WLAST : out STD_LOGIC;
M_AXI_WVALID : out STD_LOGIC;
M_AXI_WREADY : in STD_LOGIC;
M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_BVALID : in STD_LOGIC;
M_AXI_BREADY : out STD_LOGIC;
M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_ARLOCK : out STD_LOGIC;
M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_ARVALID : out STD_LOGIC;
M_AXI_ARREADY : in STD_LOGIC;
M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_RLAST : in STD_LOGIC;
M_AXI_RVALID : in STD_LOGIC;
M_AXI_RREADY : out STD_LOGIC;
LMB_Data_Addr_0 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_0 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_0 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_0 : out STD_LOGIC;
LMB_Read_Strobe_0 : out STD_LOGIC;
LMB_Write_Strobe_0 : out STD_LOGIC;
LMB_Ready_0 : in STD_LOGIC;
LMB_Wait_0 : in STD_LOGIC;
LMB_CE_0 : in STD_LOGIC;
LMB_UE_0 : in STD_LOGIC;
LMB_Byte_Enable_0 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_1 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_1 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_1 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_1 : out STD_LOGIC;
LMB_Read_Strobe_1 : out STD_LOGIC;
LMB_Write_Strobe_1 : out STD_LOGIC;
LMB_Ready_1 : in STD_LOGIC;
LMB_Wait_1 : in STD_LOGIC;
LMB_CE_1 : in STD_LOGIC;
LMB_UE_1 : in STD_LOGIC;
LMB_Byte_Enable_1 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_2 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_2 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_2 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_2 : out STD_LOGIC;
LMB_Read_Strobe_2 : out STD_LOGIC;
LMB_Write_Strobe_2 : out STD_LOGIC;
LMB_Ready_2 : in STD_LOGIC;
LMB_Wait_2 : in STD_LOGIC;
LMB_CE_2 : in STD_LOGIC;
LMB_UE_2 : in STD_LOGIC;
LMB_Byte_Enable_2 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_3 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_3 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_3 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_3 : out STD_LOGIC;
LMB_Read_Strobe_3 : out STD_LOGIC;
LMB_Write_Strobe_3 : out STD_LOGIC;
LMB_Ready_3 : in STD_LOGIC;
LMB_Wait_3 : in STD_LOGIC;
LMB_CE_3 : in STD_LOGIC;
LMB_UE_3 : in STD_LOGIC;
LMB_Byte_Enable_3 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_4 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_4 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_4 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_4 : out STD_LOGIC;
LMB_Read_Strobe_4 : out STD_LOGIC;
LMB_Write_Strobe_4 : out STD_LOGIC;
LMB_Ready_4 : in STD_LOGIC;
LMB_Wait_4 : in STD_LOGIC;
LMB_CE_4 : in STD_LOGIC;
LMB_UE_4 : in STD_LOGIC;
LMB_Byte_Enable_4 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_5 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_5 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_5 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_5 : out STD_LOGIC;
LMB_Read_Strobe_5 : out STD_LOGIC;
LMB_Write_Strobe_5 : out STD_LOGIC;
LMB_Ready_5 : in STD_LOGIC;
LMB_Wait_5 : in STD_LOGIC;
LMB_CE_5 : in STD_LOGIC;
LMB_UE_5 : in STD_LOGIC;
LMB_Byte_Enable_5 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_6 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_6 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_6 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_6 : out STD_LOGIC;
LMB_Read_Strobe_6 : out STD_LOGIC;
LMB_Write_Strobe_6 : out STD_LOGIC;
LMB_Ready_6 : in STD_LOGIC;
LMB_Wait_6 : in STD_LOGIC;
LMB_CE_6 : in STD_LOGIC;
LMB_UE_6 : in STD_LOGIC;
LMB_Byte_Enable_6 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_7 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_7 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_7 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_7 : out STD_LOGIC;
LMB_Read_Strobe_7 : out STD_LOGIC;
LMB_Write_Strobe_7 : out STD_LOGIC;
LMB_Ready_7 : in STD_LOGIC;
LMB_Wait_7 : in STD_LOGIC;
LMB_CE_7 : in STD_LOGIC;
LMB_UE_7 : in STD_LOGIC;
LMB_Byte_Enable_7 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_8 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_8 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_8 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_8 : out STD_LOGIC;
LMB_Read_Strobe_8 : out STD_LOGIC;
LMB_Write_Strobe_8 : out STD_LOGIC;
LMB_Ready_8 : in STD_LOGIC;
LMB_Wait_8 : in STD_LOGIC;
LMB_CE_8 : in STD_LOGIC;
LMB_UE_8 : in STD_LOGIC;
LMB_Byte_Enable_8 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_9 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_9 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_9 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_9 : out STD_LOGIC;
LMB_Read_Strobe_9 : out STD_LOGIC;
LMB_Write_Strobe_9 : out STD_LOGIC;
LMB_Ready_9 : in STD_LOGIC;
LMB_Wait_9 : in STD_LOGIC;
LMB_CE_9 : in STD_LOGIC;
LMB_UE_9 : in STD_LOGIC;
LMB_Byte_Enable_9 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_10 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_10 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_10 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_10 : out STD_LOGIC;
LMB_Read_Strobe_10 : out STD_LOGIC;
LMB_Write_Strobe_10 : out STD_LOGIC;
LMB_Ready_10 : in STD_LOGIC;
LMB_Wait_10 : in STD_LOGIC;
LMB_CE_10 : in STD_LOGIC;
LMB_UE_10 : in STD_LOGIC;
LMB_Byte_Enable_10 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_11 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_11 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_11 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_11 : out STD_LOGIC;
LMB_Read_Strobe_11 : out STD_LOGIC;
LMB_Write_Strobe_11 : out STD_LOGIC;
LMB_Ready_11 : in STD_LOGIC;
LMB_Wait_11 : in STD_LOGIC;
LMB_CE_11 : in STD_LOGIC;
LMB_UE_11 : in STD_LOGIC;
LMB_Byte_Enable_11 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_12 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_12 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_12 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_12 : out STD_LOGIC;
LMB_Read_Strobe_12 : out STD_LOGIC;
LMB_Write_Strobe_12 : out STD_LOGIC;
LMB_Ready_12 : in STD_LOGIC;
LMB_Wait_12 : in STD_LOGIC;
LMB_CE_12 : in STD_LOGIC;
LMB_UE_12 : in STD_LOGIC;
LMB_Byte_Enable_12 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_13 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_13 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_13 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_13 : out STD_LOGIC;
LMB_Read_Strobe_13 : out STD_LOGIC;
LMB_Write_Strobe_13 : out STD_LOGIC;
LMB_Ready_13 : in STD_LOGIC;
LMB_Wait_13 : in STD_LOGIC;
LMB_CE_13 : in STD_LOGIC;
LMB_UE_13 : in STD_LOGIC;
LMB_Byte_Enable_13 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_14 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_14 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_14 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_14 : out STD_LOGIC;
LMB_Read_Strobe_14 : out STD_LOGIC;
LMB_Write_Strobe_14 : out STD_LOGIC;
LMB_Ready_14 : in STD_LOGIC;
LMB_Wait_14 : in STD_LOGIC;
LMB_CE_14 : in STD_LOGIC;
LMB_UE_14 : in STD_LOGIC;
LMB_Byte_Enable_14 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_15 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_15 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_15 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_15 : out STD_LOGIC;
LMB_Read_Strobe_15 : out STD_LOGIC;
LMB_Write_Strobe_15 : out STD_LOGIC;
LMB_Ready_15 : in STD_LOGIC;
LMB_Wait_15 : in STD_LOGIC;
LMB_CE_15 : in STD_LOGIC;
LMB_UE_15 : in STD_LOGIC;
LMB_Byte_Enable_15 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_16 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_16 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_16 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_16 : out STD_LOGIC;
LMB_Read_Strobe_16 : out STD_LOGIC;
LMB_Write_Strobe_16 : out STD_LOGIC;
LMB_Ready_16 : in STD_LOGIC;
LMB_Wait_16 : in STD_LOGIC;
LMB_CE_16 : in STD_LOGIC;
LMB_UE_16 : in STD_LOGIC;
LMB_Byte_Enable_16 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_17 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_17 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_17 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_17 : out STD_LOGIC;
LMB_Read_Strobe_17 : out STD_LOGIC;
LMB_Write_Strobe_17 : out STD_LOGIC;
LMB_Ready_17 : in STD_LOGIC;
LMB_Wait_17 : in STD_LOGIC;
LMB_CE_17 : in STD_LOGIC;
LMB_UE_17 : in STD_LOGIC;
LMB_Byte_Enable_17 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_18 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_18 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_18 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_18 : out STD_LOGIC;
LMB_Read_Strobe_18 : out STD_LOGIC;
LMB_Write_Strobe_18 : out STD_LOGIC;
LMB_Ready_18 : in STD_LOGIC;
LMB_Wait_18 : in STD_LOGIC;
LMB_CE_18 : in STD_LOGIC;
LMB_UE_18 : in STD_LOGIC;
LMB_Byte_Enable_18 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_19 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_19 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_19 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_19 : out STD_LOGIC;
LMB_Read_Strobe_19 : out STD_LOGIC;
LMB_Write_Strobe_19 : out STD_LOGIC;
LMB_Ready_19 : in STD_LOGIC;
LMB_Wait_19 : in STD_LOGIC;
LMB_CE_19 : in STD_LOGIC;
LMB_UE_19 : in STD_LOGIC;
LMB_Byte_Enable_19 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_20 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_20 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_20 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_20 : out STD_LOGIC;
LMB_Read_Strobe_20 : out STD_LOGIC;
LMB_Write_Strobe_20 : out STD_LOGIC;
LMB_Ready_20 : in STD_LOGIC;
LMB_Wait_20 : in STD_LOGIC;
LMB_CE_20 : in STD_LOGIC;
LMB_UE_20 : in STD_LOGIC;
LMB_Byte_Enable_20 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_21 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_21 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_21 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_21 : out STD_LOGIC;
LMB_Read_Strobe_21 : out STD_LOGIC;
LMB_Write_Strobe_21 : out STD_LOGIC;
LMB_Ready_21 : in STD_LOGIC;
LMB_Wait_21 : in STD_LOGIC;
LMB_CE_21 : in STD_LOGIC;
LMB_UE_21 : in STD_LOGIC;
LMB_Byte_Enable_21 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_22 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_22 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_22 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_22 : out STD_LOGIC;
LMB_Read_Strobe_22 : out STD_LOGIC;
LMB_Write_Strobe_22 : out STD_LOGIC;
LMB_Ready_22 : in STD_LOGIC;
LMB_Wait_22 : in STD_LOGIC;
LMB_CE_22 : in STD_LOGIC;
LMB_UE_22 : in STD_LOGIC;
LMB_Byte_Enable_22 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_23 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_23 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_23 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_23 : out STD_LOGIC;
LMB_Read_Strobe_23 : out STD_LOGIC;
LMB_Write_Strobe_23 : out STD_LOGIC;
LMB_Ready_23 : in STD_LOGIC;
LMB_Wait_23 : in STD_LOGIC;
LMB_CE_23 : in STD_LOGIC;
LMB_UE_23 : in STD_LOGIC;
LMB_Byte_Enable_23 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_24 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_24 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_24 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_24 : out STD_LOGIC;
LMB_Read_Strobe_24 : out STD_LOGIC;
LMB_Write_Strobe_24 : out STD_LOGIC;
LMB_Ready_24 : in STD_LOGIC;
LMB_Wait_24 : in STD_LOGIC;
LMB_CE_24 : in STD_LOGIC;
LMB_UE_24 : in STD_LOGIC;
LMB_Byte_Enable_24 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_25 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_25 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_25 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_25 : out STD_LOGIC;
LMB_Read_Strobe_25 : out STD_LOGIC;
LMB_Write_Strobe_25 : out STD_LOGIC;
LMB_Ready_25 : in STD_LOGIC;
LMB_Wait_25 : in STD_LOGIC;
LMB_CE_25 : in STD_LOGIC;
LMB_UE_25 : in STD_LOGIC;
LMB_Byte_Enable_25 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_26 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_26 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_26 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_26 : out STD_LOGIC;
LMB_Read_Strobe_26 : out STD_LOGIC;
LMB_Write_Strobe_26 : out STD_LOGIC;
LMB_Ready_26 : in STD_LOGIC;
LMB_Wait_26 : in STD_LOGIC;
LMB_CE_26 : in STD_LOGIC;
LMB_UE_26 : in STD_LOGIC;
LMB_Byte_Enable_26 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_27 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_27 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_27 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_27 : out STD_LOGIC;
LMB_Read_Strobe_27 : out STD_LOGIC;
LMB_Write_Strobe_27 : out STD_LOGIC;
LMB_Ready_27 : in STD_LOGIC;
LMB_Wait_27 : in STD_LOGIC;
LMB_CE_27 : in STD_LOGIC;
LMB_UE_27 : in STD_LOGIC;
LMB_Byte_Enable_27 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_28 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_28 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_28 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_28 : out STD_LOGIC;
LMB_Read_Strobe_28 : out STD_LOGIC;
LMB_Write_Strobe_28 : out STD_LOGIC;
LMB_Ready_28 : in STD_LOGIC;
LMB_Wait_28 : in STD_LOGIC;
LMB_CE_28 : in STD_LOGIC;
LMB_UE_28 : in STD_LOGIC;
LMB_Byte_Enable_28 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_29 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_29 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_29 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_29 : out STD_LOGIC;
LMB_Read_Strobe_29 : out STD_LOGIC;
LMB_Write_Strobe_29 : out STD_LOGIC;
LMB_Ready_29 : in STD_LOGIC;
LMB_Wait_29 : in STD_LOGIC;
LMB_CE_29 : in STD_LOGIC;
LMB_UE_29 : in STD_LOGIC;
LMB_Byte_Enable_29 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_30 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_30 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_30 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_30 : out STD_LOGIC;
LMB_Read_Strobe_30 : out STD_LOGIC;
LMB_Write_Strobe_30 : out STD_LOGIC;
LMB_Ready_30 : in STD_LOGIC;
LMB_Wait_30 : in STD_LOGIC;
LMB_CE_30 : in STD_LOGIC;
LMB_UE_30 : in STD_LOGIC;
LMB_Byte_Enable_30 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_31 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_31 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_31 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_31 : out STD_LOGIC;
LMB_Read_Strobe_31 : out STD_LOGIC;
LMB_Write_Strobe_31 : out STD_LOGIC;
LMB_Ready_31 : in STD_LOGIC;
LMB_Wait_31 : in STD_LOGIC;
LMB_CE_31 : in STD_LOGIC;
LMB_UE_31 : in STD_LOGIC;
LMB_Byte_Enable_31 : out STD_LOGIC_VECTOR ( 0 to 3 );
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TID : out STD_LOGIC_VECTOR ( 6 downto 0 );
M_AXIS_TREADY : in STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
TRACE_CLK_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_Disable_0 : out STD_LOGIC;
Dbg_Clk_0 : out STD_LOGIC;
Dbg_TDI_0 : out STD_LOGIC;
Dbg_TDO_0 : in STD_LOGIC;
Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_0 : out STD_LOGIC;
Dbg_Shift_0 : out STD_LOGIC;
Dbg_Update_0 : out STD_LOGIC;
Dbg_Rst_0 : out STD_LOGIC;
Dbg_Trig_In_0 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_0 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_0 : out STD_LOGIC;
Dbg_TrData_0 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_0 : out STD_LOGIC;
Dbg_TrValid_0 : in STD_LOGIC;
Dbg_AWADDR_0 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_0 : out STD_LOGIC;
Dbg_AWREADY_0 : in STD_LOGIC;
Dbg_WDATA_0 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_0 : out STD_LOGIC;
Dbg_WREADY_0 : in STD_LOGIC;
Dbg_BRESP_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_0 : in STD_LOGIC;
Dbg_BREADY_0 : out STD_LOGIC;
Dbg_ARADDR_0 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_0 : out STD_LOGIC;
Dbg_ARREADY_0 : in STD_LOGIC;
Dbg_RDATA_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_0 : in STD_LOGIC;
Dbg_RREADY_0 : out STD_LOGIC;
Dbg_Disable_1 : out STD_LOGIC;
Dbg_Clk_1 : out STD_LOGIC;
Dbg_TDI_1 : out STD_LOGIC;
Dbg_TDO_1 : in STD_LOGIC;
Dbg_Reg_En_1 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_1 : out STD_LOGIC;
Dbg_Shift_1 : out STD_LOGIC;
Dbg_Update_1 : out STD_LOGIC;
Dbg_Rst_1 : out STD_LOGIC;
Dbg_Trig_In_1 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_1 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_1 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_1 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_1 : out STD_LOGIC;
Dbg_TrData_1 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_1 : out STD_LOGIC;
Dbg_TrValid_1 : in STD_LOGIC;
Dbg_AWADDR_1 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_1 : out STD_LOGIC;
Dbg_AWREADY_1 : in STD_LOGIC;
Dbg_WDATA_1 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_1 : out STD_LOGIC;
Dbg_WREADY_1 : in STD_LOGIC;
Dbg_BRESP_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_1 : in STD_LOGIC;
Dbg_BREADY_1 : out STD_LOGIC;
Dbg_ARADDR_1 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_1 : out STD_LOGIC;
Dbg_ARREADY_1 : in STD_LOGIC;
Dbg_RDATA_1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_1 : in STD_LOGIC;
Dbg_RREADY_1 : out STD_LOGIC;
Dbg_Disable_2 : out STD_LOGIC;
Dbg_Clk_2 : out STD_LOGIC;
Dbg_TDI_2 : out STD_LOGIC;
Dbg_TDO_2 : in STD_LOGIC;
Dbg_Reg_En_2 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_2 : out STD_LOGIC;
Dbg_Shift_2 : out STD_LOGIC;
Dbg_Update_2 : out STD_LOGIC;
Dbg_Rst_2 : out STD_LOGIC;
Dbg_Trig_In_2 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_2 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_2 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_2 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_2 : out STD_LOGIC;
Dbg_TrData_2 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_2 : out STD_LOGIC;
Dbg_TrValid_2 : in STD_LOGIC;
Dbg_AWADDR_2 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_2 : out STD_LOGIC;
Dbg_AWREADY_2 : in STD_LOGIC;
Dbg_WDATA_2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_2 : out STD_LOGIC;
Dbg_WREADY_2 : in STD_LOGIC;
Dbg_BRESP_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_2 : in STD_LOGIC;
Dbg_BREADY_2 : out STD_LOGIC;
Dbg_ARADDR_2 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_2 : out STD_LOGIC;
Dbg_ARREADY_2 : in STD_LOGIC;
Dbg_RDATA_2 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_2 : in STD_LOGIC;
Dbg_RREADY_2 : out STD_LOGIC;
Dbg_Disable_3 : out STD_LOGIC;
Dbg_Clk_3 : out STD_LOGIC;
Dbg_TDI_3 : out STD_LOGIC;
Dbg_TDO_3 : in STD_LOGIC;
Dbg_Reg_En_3 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_3 : out STD_LOGIC;
Dbg_Shift_3 : out STD_LOGIC;
Dbg_Update_3 : out STD_LOGIC;
Dbg_Rst_3 : out STD_LOGIC;
Dbg_Trig_In_3 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_3 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_3 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_3 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_3 : out STD_LOGIC;
Dbg_TrData_3 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_3 : out STD_LOGIC;
Dbg_TrValid_3 : in STD_LOGIC;
Dbg_AWADDR_3 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_3 : out STD_LOGIC;
Dbg_AWREADY_3 : in STD_LOGIC;
Dbg_WDATA_3 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_3 : out STD_LOGIC;
Dbg_WREADY_3 : in STD_LOGIC;
Dbg_BRESP_3 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_3 : in STD_LOGIC;
Dbg_BREADY_3 : out STD_LOGIC;
Dbg_ARADDR_3 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_3 : out STD_LOGIC;
Dbg_ARREADY_3 : in STD_LOGIC;
Dbg_RDATA_3 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_3 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_3 : in STD_LOGIC;
Dbg_RREADY_3 : out STD_LOGIC;
Dbg_Disable_4 : out STD_LOGIC;
Dbg_Clk_4 : out STD_LOGIC;
Dbg_TDI_4 : out STD_LOGIC;
Dbg_TDO_4 : in STD_LOGIC;
Dbg_Reg_En_4 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_4 : out STD_LOGIC;
Dbg_Shift_4 : out STD_LOGIC;
Dbg_Update_4 : out STD_LOGIC;
Dbg_Rst_4 : out STD_LOGIC;
Dbg_Trig_In_4 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_4 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_4 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_4 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_4 : out STD_LOGIC;
Dbg_TrData_4 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_4 : out STD_LOGIC;
Dbg_TrValid_4 : in STD_LOGIC;
Dbg_AWADDR_4 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_4 : out STD_LOGIC;
Dbg_AWREADY_4 : in STD_LOGIC;
Dbg_WDATA_4 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_4 : out STD_LOGIC;
Dbg_WREADY_4 : in STD_LOGIC;
Dbg_BRESP_4 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_4 : in STD_LOGIC;
Dbg_BREADY_4 : out STD_LOGIC;
Dbg_ARADDR_4 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_4 : out STD_LOGIC;
Dbg_ARREADY_4 : in STD_LOGIC;
Dbg_RDATA_4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_4 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_4 : in STD_LOGIC;
Dbg_RREADY_4 : out STD_LOGIC;
Dbg_Disable_5 : out STD_LOGIC;
Dbg_Clk_5 : out STD_LOGIC;
Dbg_TDI_5 : out STD_LOGIC;
Dbg_TDO_5 : in STD_LOGIC;
Dbg_Reg_En_5 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_5 : out STD_LOGIC;
Dbg_Shift_5 : out STD_LOGIC;
Dbg_Update_5 : out STD_LOGIC;
Dbg_Rst_5 : out STD_LOGIC;
Dbg_Trig_In_5 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_5 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_5 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_5 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_5 : out STD_LOGIC;
Dbg_TrData_5 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_5 : out STD_LOGIC;
Dbg_TrValid_5 : in STD_LOGIC;
Dbg_AWADDR_5 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_5 : out STD_LOGIC;
Dbg_AWREADY_5 : in STD_LOGIC;
Dbg_WDATA_5 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_5 : out STD_LOGIC;
Dbg_WREADY_5 : in STD_LOGIC;
Dbg_BRESP_5 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_5 : in STD_LOGIC;
Dbg_BREADY_5 : out STD_LOGIC;
Dbg_ARADDR_5 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_5 : out STD_LOGIC;
Dbg_ARREADY_5 : in STD_LOGIC;
Dbg_RDATA_5 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_5 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_5 : in STD_LOGIC;
Dbg_RREADY_5 : out STD_LOGIC;
Dbg_Disable_6 : out STD_LOGIC;
Dbg_Clk_6 : out STD_LOGIC;
Dbg_TDI_6 : out STD_LOGIC;
Dbg_TDO_6 : in STD_LOGIC;
Dbg_Reg_En_6 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_6 : out STD_LOGIC;
Dbg_Shift_6 : out STD_LOGIC;
Dbg_Update_6 : out STD_LOGIC;
Dbg_Rst_6 : out STD_LOGIC;
Dbg_Trig_In_6 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_6 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_6 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_6 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_6 : out STD_LOGIC;
Dbg_TrData_6 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_6 : out STD_LOGIC;
Dbg_TrValid_6 : in STD_LOGIC;
Dbg_AWADDR_6 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_6 : out STD_LOGIC;
Dbg_AWREADY_6 : in STD_LOGIC;
Dbg_WDATA_6 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_6 : out STD_LOGIC;
Dbg_WREADY_6 : in STD_LOGIC;
Dbg_BRESP_6 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_6 : in STD_LOGIC;
Dbg_BREADY_6 : out STD_LOGIC;
Dbg_ARADDR_6 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_6 : out STD_LOGIC;
Dbg_ARREADY_6 : in STD_LOGIC;
Dbg_RDATA_6 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_6 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_6 : in STD_LOGIC;
Dbg_RREADY_6 : out STD_LOGIC;
Dbg_Disable_7 : out STD_LOGIC;
Dbg_Clk_7 : out STD_LOGIC;
Dbg_TDI_7 : out STD_LOGIC;
Dbg_TDO_7 : in STD_LOGIC;
Dbg_Reg_En_7 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_7 : out STD_LOGIC;
Dbg_Shift_7 : out STD_LOGIC;
Dbg_Update_7 : out STD_LOGIC;
Dbg_Rst_7 : out STD_LOGIC;
Dbg_Trig_In_7 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_7 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_7 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_7 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_7 : out STD_LOGIC;
Dbg_TrData_7 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_7 : out STD_LOGIC;
Dbg_TrValid_7 : in STD_LOGIC;
Dbg_AWADDR_7 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_7 : out STD_LOGIC;
Dbg_AWREADY_7 : in STD_LOGIC;
Dbg_WDATA_7 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_7 : out STD_LOGIC;
Dbg_WREADY_7 : in STD_LOGIC;
Dbg_BRESP_7 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_7 : in STD_LOGIC;
Dbg_BREADY_7 : out STD_LOGIC;
Dbg_ARADDR_7 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_7 : out STD_LOGIC;
Dbg_ARREADY_7 : in STD_LOGIC;
Dbg_RDATA_7 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_7 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_7 : in STD_LOGIC;
Dbg_RREADY_7 : out STD_LOGIC;
Dbg_Disable_8 : out STD_LOGIC;
Dbg_Clk_8 : out STD_LOGIC;
Dbg_TDI_8 : out STD_LOGIC;
Dbg_TDO_8 : in STD_LOGIC;
Dbg_Reg_En_8 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_8 : out STD_LOGIC;
Dbg_Shift_8 : out STD_LOGIC;
Dbg_Update_8 : out STD_LOGIC;
Dbg_Rst_8 : out STD_LOGIC;
Dbg_Trig_In_8 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_8 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_8 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_8 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_8 : out STD_LOGIC;
Dbg_TrData_8 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_8 : out STD_LOGIC;
Dbg_TrValid_8 : in STD_LOGIC;
Dbg_AWADDR_8 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_8 : out STD_LOGIC;
Dbg_AWREADY_8 : in STD_LOGIC;
Dbg_WDATA_8 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_8 : out STD_LOGIC;
Dbg_WREADY_8 : in STD_LOGIC;
Dbg_BRESP_8 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_8 : in STD_LOGIC;
Dbg_BREADY_8 : out STD_LOGIC;
Dbg_ARADDR_8 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_8 : out STD_LOGIC;
Dbg_ARREADY_8 : in STD_LOGIC;
Dbg_RDATA_8 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_8 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_8 : in STD_LOGIC;
Dbg_RREADY_8 : out STD_LOGIC;
Dbg_Disable_9 : out STD_LOGIC;
Dbg_Clk_9 : out STD_LOGIC;
Dbg_TDI_9 : out STD_LOGIC;
Dbg_TDO_9 : in STD_LOGIC;
Dbg_Reg_En_9 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_9 : out STD_LOGIC;
Dbg_Shift_9 : out STD_LOGIC;
Dbg_Update_9 : out STD_LOGIC;
Dbg_Rst_9 : out STD_LOGIC;
Dbg_Trig_In_9 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_9 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_9 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_9 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_9 : out STD_LOGIC;
Dbg_TrData_9 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_9 : out STD_LOGIC;
Dbg_TrValid_9 : in STD_LOGIC;
Dbg_AWADDR_9 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_9 : out STD_LOGIC;
Dbg_AWREADY_9 : in STD_LOGIC;
Dbg_WDATA_9 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_9 : out STD_LOGIC;
Dbg_WREADY_9 : in STD_LOGIC;
Dbg_BRESP_9 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_9 : in STD_LOGIC;
Dbg_BREADY_9 : out STD_LOGIC;
Dbg_ARADDR_9 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_9 : out STD_LOGIC;
Dbg_ARREADY_9 : in STD_LOGIC;
Dbg_RDATA_9 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_9 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_9 : in STD_LOGIC;
Dbg_RREADY_9 : out STD_LOGIC;
Dbg_Disable_10 : out STD_LOGIC;
Dbg_Clk_10 : out STD_LOGIC;
Dbg_TDI_10 : out STD_LOGIC;
Dbg_TDO_10 : in STD_LOGIC;
Dbg_Reg_En_10 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_10 : out STD_LOGIC;
Dbg_Shift_10 : out STD_LOGIC;
Dbg_Update_10 : out STD_LOGIC;
Dbg_Rst_10 : out STD_LOGIC;
Dbg_Trig_In_10 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_10 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_10 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_10 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_10 : out STD_LOGIC;
Dbg_TrData_10 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_10 : out STD_LOGIC;
Dbg_TrValid_10 : in STD_LOGIC;
Dbg_AWADDR_10 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_10 : out STD_LOGIC;
Dbg_AWREADY_10 : in STD_LOGIC;
Dbg_WDATA_10 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_10 : out STD_LOGIC;
Dbg_WREADY_10 : in STD_LOGIC;
Dbg_BRESP_10 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_10 : in STD_LOGIC;
Dbg_BREADY_10 : out STD_LOGIC;
Dbg_ARADDR_10 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_10 : out STD_LOGIC;
Dbg_ARREADY_10 : in STD_LOGIC;
Dbg_RDATA_10 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_10 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_10 : in STD_LOGIC;
Dbg_RREADY_10 : out STD_LOGIC;
Dbg_Disable_11 : out STD_LOGIC;
Dbg_Clk_11 : out STD_LOGIC;
Dbg_TDI_11 : out STD_LOGIC;
Dbg_TDO_11 : in STD_LOGIC;
Dbg_Reg_En_11 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_11 : out STD_LOGIC;
Dbg_Shift_11 : out STD_LOGIC;
Dbg_Update_11 : out STD_LOGIC;
Dbg_Rst_11 : out STD_LOGIC;
Dbg_Trig_In_11 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_11 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_11 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_11 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_11 : out STD_LOGIC;
Dbg_TrData_11 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_11 : out STD_LOGIC;
Dbg_TrValid_11 : in STD_LOGIC;
Dbg_AWADDR_11 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_11 : out STD_LOGIC;
Dbg_AWREADY_11 : in STD_LOGIC;
Dbg_WDATA_11 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_11 : out STD_LOGIC;
Dbg_WREADY_11 : in STD_LOGIC;
Dbg_BRESP_11 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_11 : in STD_LOGIC;
Dbg_BREADY_11 : out STD_LOGIC;
Dbg_ARADDR_11 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_11 : out STD_LOGIC;
Dbg_ARREADY_11 : in STD_LOGIC;
Dbg_RDATA_11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_11 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_11 : in STD_LOGIC;
Dbg_RREADY_11 : out STD_LOGIC;
Dbg_Disable_12 : out STD_LOGIC;
Dbg_Clk_12 : out STD_LOGIC;
Dbg_TDI_12 : out STD_LOGIC;
Dbg_TDO_12 : in STD_LOGIC;
Dbg_Reg_En_12 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_12 : out STD_LOGIC;
Dbg_Shift_12 : out STD_LOGIC;
Dbg_Update_12 : out STD_LOGIC;
Dbg_Rst_12 : out STD_LOGIC;
Dbg_Trig_In_12 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_12 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_12 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_12 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_12 : out STD_LOGIC;
Dbg_TrData_12 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_12 : out STD_LOGIC;
Dbg_TrValid_12 : in STD_LOGIC;
Dbg_AWADDR_12 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_12 : out STD_LOGIC;
Dbg_AWREADY_12 : in STD_LOGIC;
Dbg_WDATA_12 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_12 : out STD_LOGIC;
Dbg_WREADY_12 : in STD_LOGIC;
Dbg_BRESP_12 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_12 : in STD_LOGIC;
Dbg_BREADY_12 : out STD_LOGIC;
Dbg_ARADDR_12 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_12 : out STD_LOGIC;
Dbg_ARREADY_12 : in STD_LOGIC;
Dbg_RDATA_12 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_12 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_12 : in STD_LOGIC;
Dbg_RREADY_12 : out STD_LOGIC;
Dbg_Disable_13 : out STD_LOGIC;
Dbg_Clk_13 : out STD_LOGIC;
Dbg_TDI_13 : out STD_LOGIC;
Dbg_TDO_13 : in STD_LOGIC;
Dbg_Reg_En_13 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_13 : out STD_LOGIC;
Dbg_Shift_13 : out STD_LOGIC;
Dbg_Update_13 : out STD_LOGIC;
Dbg_Rst_13 : out STD_LOGIC;
Dbg_Trig_In_13 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_13 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_13 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_13 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_13 : out STD_LOGIC;
Dbg_TrData_13 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_13 : out STD_LOGIC;
Dbg_TrValid_13 : in STD_LOGIC;
Dbg_AWADDR_13 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_13 : out STD_LOGIC;
Dbg_AWREADY_13 : in STD_LOGIC;
Dbg_WDATA_13 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_13 : out STD_LOGIC;
Dbg_WREADY_13 : in STD_LOGIC;
Dbg_BRESP_13 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_13 : in STD_LOGIC;
Dbg_BREADY_13 : out STD_LOGIC;
Dbg_ARADDR_13 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_13 : out STD_LOGIC;
Dbg_ARREADY_13 : in STD_LOGIC;
Dbg_RDATA_13 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_13 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_13 : in STD_LOGIC;
Dbg_RREADY_13 : out STD_LOGIC;
Dbg_Disable_14 : out STD_LOGIC;
Dbg_Clk_14 : out STD_LOGIC;
Dbg_TDI_14 : out STD_LOGIC;
Dbg_TDO_14 : in STD_LOGIC;
Dbg_Reg_En_14 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_14 : out STD_LOGIC;
Dbg_Shift_14 : out STD_LOGIC;
Dbg_Update_14 : out STD_LOGIC;
Dbg_Rst_14 : out STD_LOGIC;
Dbg_Trig_In_14 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_14 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_14 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_14 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_14 : out STD_LOGIC;
Dbg_TrData_14 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_14 : out STD_LOGIC;
Dbg_TrValid_14 : in STD_LOGIC;
Dbg_AWADDR_14 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_14 : out STD_LOGIC;
Dbg_AWREADY_14 : in STD_LOGIC;
Dbg_WDATA_14 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_14 : out STD_LOGIC;
Dbg_WREADY_14 : in STD_LOGIC;
Dbg_BRESP_14 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_14 : in STD_LOGIC;
Dbg_BREADY_14 : out STD_LOGIC;
Dbg_ARADDR_14 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_14 : out STD_LOGIC;
Dbg_ARREADY_14 : in STD_LOGIC;
Dbg_RDATA_14 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_14 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_14 : in STD_LOGIC;
Dbg_RREADY_14 : out STD_LOGIC;
Dbg_Disable_15 : out STD_LOGIC;
Dbg_Clk_15 : out STD_LOGIC;
Dbg_TDI_15 : out STD_LOGIC;
Dbg_TDO_15 : in STD_LOGIC;
Dbg_Reg_En_15 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_15 : out STD_LOGIC;
Dbg_Shift_15 : out STD_LOGIC;
Dbg_Update_15 : out STD_LOGIC;
Dbg_Rst_15 : out STD_LOGIC;
Dbg_Trig_In_15 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_15 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_15 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_15 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_15 : out STD_LOGIC;
Dbg_TrData_15 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_15 : out STD_LOGIC;
Dbg_TrValid_15 : in STD_LOGIC;
Dbg_AWADDR_15 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_15 : out STD_LOGIC;
Dbg_AWREADY_15 : in STD_LOGIC;
Dbg_WDATA_15 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_15 : out STD_LOGIC;
Dbg_WREADY_15 : in STD_LOGIC;
Dbg_BRESP_15 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_15 : in STD_LOGIC;
Dbg_BREADY_15 : out STD_LOGIC;
Dbg_ARADDR_15 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_15 : out STD_LOGIC;
Dbg_ARREADY_15 : in STD_LOGIC;
Dbg_RDATA_15 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_15 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_15 : in STD_LOGIC;
Dbg_RREADY_15 : out STD_LOGIC;
Dbg_Disable_16 : out STD_LOGIC;
Dbg_Clk_16 : out STD_LOGIC;
Dbg_TDI_16 : out STD_LOGIC;
Dbg_TDO_16 : in STD_LOGIC;
Dbg_Reg_En_16 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_16 : out STD_LOGIC;
Dbg_Shift_16 : out STD_LOGIC;
Dbg_Update_16 : out STD_LOGIC;
Dbg_Rst_16 : out STD_LOGIC;
Dbg_Trig_In_16 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_16 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_16 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_16 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_16 : out STD_LOGIC;
Dbg_TrData_16 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_16 : out STD_LOGIC;
Dbg_TrValid_16 : in STD_LOGIC;
Dbg_AWADDR_16 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_16 : out STD_LOGIC;
Dbg_AWREADY_16 : in STD_LOGIC;
Dbg_WDATA_16 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_16 : out STD_LOGIC;
Dbg_WREADY_16 : in STD_LOGIC;
Dbg_BRESP_16 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_16 : in STD_LOGIC;
Dbg_BREADY_16 : out STD_LOGIC;
Dbg_ARADDR_16 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_16 : out STD_LOGIC;
Dbg_ARREADY_16 : in STD_LOGIC;
Dbg_RDATA_16 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_16 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_16 : in STD_LOGIC;
Dbg_RREADY_16 : out STD_LOGIC;
Dbg_Disable_17 : out STD_LOGIC;
Dbg_Clk_17 : out STD_LOGIC;
Dbg_TDI_17 : out STD_LOGIC;
Dbg_TDO_17 : in STD_LOGIC;
Dbg_Reg_En_17 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_17 : out STD_LOGIC;
Dbg_Shift_17 : out STD_LOGIC;
Dbg_Update_17 : out STD_LOGIC;
Dbg_Rst_17 : out STD_LOGIC;
Dbg_Trig_In_17 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_17 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_17 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_17 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_17 : out STD_LOGIC;
Dbg_TrData_17 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_17 : out STD_LOGIC;
Dbg_TrValid_17 : in STD_LOGIC;
Dbg_AWADDR_17 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_17 : out STD_LOGIC;
Dbg_AWREADY_17 : in STD_LOGIC;
Dbg_WDATA_17 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_17 : out STD_LOGIC;
Dbg_WREADY_17 : in STD_LOGIC;
Dbg_BRESP_17 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_17 : in STD_LOGIC;
Dbg_BREADY_17 : out STD_LOGIC;
Dbg_ARADDR_17 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_17 : out STD_LOGIC;
Dbg_ARREADY_17 : in STD_LOGIC;
Dbg_RDATA_17 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_17 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_17 : in STD_LOGIC;
Dbg_RREADY_17 : out STD_LOGIC;
Dbg_Disable_18 : out STD_LOGIC;
Dbg_Clk_18 : out STD_LOGIC;
Dbg_TDI_18 : out STD_LOGIC;
Dbg_TDO_18 : in STD_LOGIC;
Dbg_Reg_En_18 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_18 : out STD_LOGIC;
Dbg_Shift_18 : out STD_LOGIC;
Dbg_Update_18 : out STD_LOGIC;
Dbg_Rst_18 : out STD_LOGIC;
Dbg_Trig_In_18 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_18 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_18 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_18 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_18 : out STD_LOGIC;
Dbg_TrData_18 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_18 : out STD_LOGIC;
Dbg_TrValid_18 : in STD_LOGIC;
Dbg_AWADDR_18 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_18 : out STD_LOGIC;
Dbg_AWREADY_18 : in STD_LOGIC;
Dbg_WDATA_18 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_18 : out STD_LOGIC;
Dbg_WREADY_18 : in STD_LOGIC;
Dbg_BRESP_18 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_18 : in STD_LOGIC;
Dbg_BREADY_18 : out STD_LOGIC;
Dbg_ARADDR_18 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_18 : out STD_LOGIC;
Dbg_ARREADY_18 : in STD_LOGIC;
Dbg_RDATA_18 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_18 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_18 : in STD_LOGIC;
Dbg_RREADY_18 : out STD_LOGIC;
Dbg_Disable_19 : out STD_LOGIC;
Dbg_Clk_19 : out STD_LOGIC;
Dbg_TDI_19 : out STD_LOGIC;
Dbg_TDO_19 : in STD_LOGIC;
Dbg_Reg_En_19 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_19 : out STD_LOGIC;
Dbg_Shift_19 : out STD_LOGIC;
Dbg_Update_19 : out STD_LOGIC;
Dbg_Rst_19 : out STD_LOGIC;
Dbg_Trig_In_19 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_19 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_19 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_19 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_19 : out STD_LOGIC;
Dbg_TrData_19 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_19 : out STD_LOGIC;
Dbg_TrValid_19 : in STD_LOGIC;
Dbg_AWADDR_19 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_19 : out STD_LOGIC;
Dbg_AWREADY_19 : in STD_LOGIC;
Dbg_WDATA_19 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_19 : out STD_LOGIC;
Dbg_WREADY_19 : in STD_LOGIC;
Dbg_BRESP_19 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_19 : in STD_LOGIC;
Dbg_BREADY_19 : out STD_LOGIC;
Dbg_ARADDR_19 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_19 : out STD_LOGIC;
Dbg_ARREADY_19 : in STD_LOGIC;
Dbg_RDATA_19 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_19 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_19 : in STD_LOGIC;
Dbg_RREADY_19 : out STD_LOGIC;
Dbg_Disable_20 : out STD_LOGIC;
Dbg_Clk_20 : out STD_LOGIC;
Dbg_TDI_20 : out STD_LOGIC;
Dbg_TDO_20 : in STD_LOGIC;
Dbg_Reg_En_20 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_20 : out STD_LOGIC;
Dbg_Shift_20 : out STD_LOGIC;
Dbg_Update_20 : out STD_LOGIC;
Dbg_Rst_20 : out STD_LOGIC;
Dbg_Trig_In_20 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_20 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_20 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_20 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_20 : out STD_LOGIC;
Dbg_TrData_20 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_20 : out STD_LOGIC;
Dbg_TrValid_20 : in STD_LOGIC;
Dbg_AWADDR_20 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_20 : out STD_LOGIC;
Dbg_AWREADY_20 : in STD_LOGIC;
Dbg_WDATA_20 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_20 : out STD_LOGIC;
Dbg_WREADY_20 : in STD_LOGIC;
Dbg_BRESP_20 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_20 : in STD_LOGIC;
Dbg_BREADY_20 : out STD_LOGIC;
Dbg_ARADDR_20 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_20 : out STD_LOGIC;
Dbg_ARREADY_20 : in STD_LOGIC;
Dbg_RDATA_20 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_20 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_20 : in STD_LOGIC;
Dbg_RREADY_20 : out STD_LOGIC;
Dbg_Disable_21 : out STD_LOGIC;
Dbg_Clk_21 : out STD_LOGIC;
Dbg_TDI_21 : out STD_LOGIC;
Dbg_TDO_21 : in STD_LOGIC;
Dbg_Reg_En_21 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_21 : out STD_LOGIC;
Dbg_Shift_21 : out STD_LOGIC;
Dbg_Update_21 : out STD_LOGIC;
Dbg_Rst_21 : out STD_LOGIC;
Dbg_Trig_In_21 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_21 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_21 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_21 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_21 : out STD_LOGIC;
Dbg_TrData_21 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_21 : out STD_LOGIC;
Dbg_TrValid_21 : in STD_LOGIC;
Dbg_AWADDR_21 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_21 : out STD_LOGIC;
Dbg_AWREADY_21 : in STD_LOGIC;
Dbg_WDATA_21 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_21 : out STD_LOGIC;
Dbg_WREADY_21 : in STD_LOGIC;
Dbg_BRESP_21 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_21 : in STD_LOGIC;
Dbg_BREADY_21 : out STD_LOGIC;
Dbg_ARADDR_21 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_21 : out STD_LOGIC;
Dbg_ARREADY_21 : in STD_LOGIC;
Dbg_RDATA_21 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_21 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_21 : in STD_LOGIC;
Dbg_RREADY_21 : out STD_LOGIC;
Dbg_Disable_22 : out STD_LOGIC;
Dbg_Clk_22 : out STD_LOGIC;
Dbg_TDI_22 : out STD_LOGIC;
Dbg_TDO_22 : in STD_LOGIC;
Dbg_Reg_En_22 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_22 : out STD_LOGIC;
Dbg_Shift_22 : out STD_LOGIC;
Dbg_Update_22 : out STD_LOGIC;
Dbg_Rst_22 : out STD_LOGIC;
Dbg_Trig_In_22 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_22 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_22 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_22 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_22 : out STD_LOGIC;
Dbg_TrData_22 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_22 : out STD_LOGIC;
Dbg_TrValid_22 : in STD_LOGIC;
Dbg_AWADDR_22 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_22 : out STD_LOGIC;
Dbg_AWREADY_22 : in STD_LOGIC;
Dbg_WDATA_22 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_22 : out STD_LOGIC;
Dbg_WREADY_22 : in STD_LOGIC;
Dbg_BRESP_22 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_22 : in STD_LOGIC;
Dbg_BREADY_22 : out STD_LOGIC;
Dbg_ARADDR_22 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_22 : out STD_LOGIC;
Dbg_ARREADY_22 : in STD_LOGIC;
Dbg_RDATA_22 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_22 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_22 : in STD_LOGIC;
Dbg_RREADY_22 : out STD_LOGIC;
Dbg_Disable_23 : out STD_LOGIC;
Dbg_Clk_23 : out STD_LOGIC;
Dbg_TDI_23 : out STD_LOGIC;
Dbg_TDO_23 : in STD_LOGIC;
Dbg_Reg_En_23 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_23 : out STD_LOGIC;
Dbg_Shift_23 : out STD_LOGIC;
Dbg_Update_23 : out STD_LOGIC;
Dbg_Rst_23 : out STD_LOGIC;
Dbg_Trig_In_23 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_23 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_23 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_23 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_23 : out STD_LOGIC;
Dbg_TrData_23 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_23 : out STD_LOGIC;
Dbg_TrValid_23 : in STD_LOGIC;
Dbg_AWADDR_23 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_23 : out STD_LOGIC;
Dbg_AWREADY_23 : in STD_LOGIC;
Dbg_WDATA_23 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_23 : out STD_LOGIC;
Dbg_WREADY_23 : in STD_LOGIC;
Dbg_BRESP_23 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_23 : in STD_LOGIC;
Dbg_BREADY_23 : out STD_LOGIC;
Dbg_ARADDR_23 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_23 : out STD_LOGIC;
Dbg_ARREADY_23 : in STD_LOGIC;
Dbg_RDATA_23 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_23 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_23 : in STD_LOGIC;
Dbg_RREADY_23 : out STD_LOGIC;
Dbg_Disable_24 : out STD_LOGIC;
Dbg_Clk_24 : out STD_LOGIC;
Dbg_TDI_24 : out STD_LOGIC;
Dbg_TDO_24 : in STD_LOGIC;
Dbg_Reg_En_24 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_24 : out STD_LOGIC;
Dbg_Shift_24 : out STD_LOGIC;
Dbg_Update_24 : out STD_LOGIC;
Dbg_Rst_24 : out STD_LOGIC;
Dbg_Trig_In_24 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_24 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_24 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_24 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_24 : out STD_LOGIC;
Dbg_TrData_24 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_24 : out STD_LOGIC;
Dbg_TrValid_24 : in STD_LOGIC;
Dbg_AWADDR_24 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_24 : out STD_LOGIC;
Dbg_AWREADY_24 : in STD_LOGIC;
Dbg_WDATA_24 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_24 : out STD_LOGIC;
Dbg_WREADY_24 : in STD_LOGIC;
Dbg_BRESP_24 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_24 : in STD_LOGIC;
Dbg_BREADY_24 : out STD_LOGIC;
Dbg_ARADDR_24 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_24 : out STD_LOGIC;
Dbg_ARREADY_24 : in STD_LOGIC;
Dbg_RDATA_24 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_24 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_24 : in STD_LOGIC;
Dbg_RREADY_24 : out STD_LOGIC;
Dbg_Disable_25 : out STD_LOGIC;
Dbg_Clk_25 : out STD_LOGIC;
Dbg_TDI_25 : out STD_LOGIC;
Dbg_TDO_25 : in STD_LOGIC;
Dbg_Reg_En_25 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_25 : out STD_LOGIC;
Dbg_Shift_25 : out STD_LOGIC;
Dbg_Update_25 : out STD_LOGIC;
Dbg_Rst_25 : out STD_LOGIC;
Dbg_Trig_In_25 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_25 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_25 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_25 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_25 : out STD_LOGIC;
Dbg_TrData_25 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_25 : out STD_LOGIC;
Dbg_TrValid_25 : in STD_LOGIC;
Dbg_AWADDR_25 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_25 : out STD_LOGIC;
Dbg_AWREADY_25 : in STD_LOGIC;
Dbg_WDATA_25 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_25 : out STD_LOGIC;
Dbg_WREADY_25 : in STD_LOGIC;
Dbg_BRESP_25 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_25 : in STD_LOGIC;
Dbg_BREADY_25 : out STD_LOGIC;
Dbg_ARADDR_25 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_25 : out STD_LOGIC;
Dbg_ARREADY_25 : in STD_LOGIC;
Dbg_RDATA_25 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_25 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_25 : in STD_LOGIC;
Dbg_RREADY_25 : out STD_LOGIC;
Dbg_Disable_26 : out STD_LOGIC;
Dbg_Clk_26 : out STD_LOGIC;
Dbg_TDI_26 : out STD_LOGIC;
Dbg_TDO_26 : in STD_LOGIC;
Dbg_Reg_En_26 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_26 : out STD_LOGIC;
Dbg_Shift_26 : out STD_LOGIC;
Dbg_Update_26 : out STD_LOGIC;
Dbg_Rst_26 : out STD_LOGIC;
Dbg_Trig_In_26 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_26 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_26 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_26 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_26 : out STD_LOGIC;
Dbg_TrData_26 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_26 : out STD_LOGIC;
Dbg_TrValid_26 : in STD_LOGIC;
Dbg_AWADDR_26 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_26 : out STD_LOGIC;
Dbg_AWREADY_26 : in STD_LOGIC;
Dbg_WDATA_26 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_26 : out STD_LOGIC;
Dbg_WREADY_26 : in STD_LOGIC;
Dbg_BRESP_26 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_26 : in STD_LOGIC;
Dbg_BREADY_26 : out STD_LOGIC;
Dbg_ARADDR_26 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_26 : out STD_LOGIC;
Dbg_ARREADY_26 : in STD_LOGIC;
Dbg_RDATA_26 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_26 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_26 : in STD_LOGIC;
Dbg_RREADY_26 : out STD_LOGIC;
Dbg_Disable_27 : out STD_LOGIC;
Dbg_Clk_27 : out STD_LOGIC;
Dbg_TDI_27 : out STD_LOGIC;
Dbg_TDO_27 : in STD_LOGIC;
Dbg_Reg_En_27 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_27 : out STD_LOGIC;
Dbg_Shift_27 : out STD_LOGIC;
Dbg_Update_27 : out STD_LOGIC;
Dbg_Rst_27 : out STD_LOGIC;
Dbg_Trig_In_27 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_27 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_27 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_27 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_27 : out STD_LOGIC;
Dbg_TrData_27 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_27 : out STD_LOGIC;
Dbg_TrValid_27 : in STD_LOGIC;
Dbg_AWADDR_27 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_27 : out STD_LOGIC;
Dbg_AWREADY_27 : in STD_LOGIC;
Dbg_WDATA_27 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_27 : out STD_LOGIC;
Dbg_WREADY_27 : in STD_LOGIC;
Dbg_BRESP_27 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_27 : in STD_LOGIC;
Dbg_BREADY_27 : out STD_LOGIC;
Dbg_ARADDR_27 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_27 : out STD_LOGIC;
Dbg_ARREADY_27 : in STD_LOGIC;
Dbg_RDATA_27 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_27 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_27 : in STD_LOGIC;
Dbg_RREADY_27 : out STD_LOGIC;
Dbg_Disable_28 : out STD_LOGIC;
Dbg_Clk_28 : out STD_LOGIC;
Dbg_TDI_28 : out STD_LOGIC;
Dbg_TDO_28 : in STD_LOGIC;
Dbg_Reg_En_28 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_28 : out STD_LOGIC;
Dbg_Shift_28 : out STD_LOGIC;
Dbg_Update_28 : out STD_LOGIC;
Dbg_Rst_28 : out STD_LOGIC;
Dbg_Trig_In_28 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_28 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_28 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_28 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_28 : out STD_LOGIC;
Dbg_TrData_28 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_28 : out STD_LOGIC;
Dbg_TrValid_28 : in STD_LOGIC;
Dbg_AWADDR_28 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_28 : out STD_LOGIC;
Dbg_AWREADY_28 : in STD_LOGIC;
Dbg_WDATA_28 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_28 : out STD_LOGIC;
Dbg_WREADY_28 : in STD_LOGIC;
Dbg_BRESP_28 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_28 : in STD_LOGIC;
Dbg_BREADY_28 : out STD_LOGIC;
Dbg_ARADDR_28 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_28 : out STD_LOGIC;
Dbg_ARREADY_28 : in STD_LOGIC;
Dbg_RDATA_28 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_28 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_28 : in STD_LOGIC;
Dbg_RREADY_28 : out STD_LOGIC;
Dbg_Disable_29 : out STD_LOGIC;
Dbg_Clk_29 : out STD_LOGIC;
Dbg_TDI_29 : out STD_LOGIC;
Dbg_TDO_29 : in STD_LOGIC;
Dbg_Reg_En_29 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_29 : out STD_LOGIC;
Dbg_Shift_29 : out STD_LOGIC;
Dbg_Update_29 : out STD_LOGIC;
Dbg_Rst_29 : out STD_LOGIC;
Dbg_Trig_In_29 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_29 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_29 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_29 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_29 : out STD_LOGIC;
Dbg_TrData_29 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_29 : out STD_LOGIC;
Dbg_TrValid_29 : in STD_LOGIC;
Dbg_AWADDR_29 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_29 : out STD_LOGIC;
Dbg_AWREADY_29 : in STD_LOGIC;
Dbg_WDATA_29 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_29 : out STD_LOGIC;
Dbg_WREADY_29 : in STD_LOGIC;
Dbg_BRESP_29 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_29 : in STD_LOGIC;
Dbg_BREADY_29 : out STD_LOGIC;
Dbg_ARADDR_29 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_29 : out STD_LOGIC;
Dbg_ARREADY_29 : in STD_LOGIC;
Dbg_RDATA_29 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_29 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_29 : in STD_LOGIC;
Dbg_RREADY_29 : out STD_LOGIC;
Dbg_Disable_30 : out STD_LOGIC;
Dbg_Clk_30 : out STD_LOGIC;
Dbg_TDI_30 : out STD_LOGIC;
Dbg_TDO_30 : in STD_LOGIC;
Dbg_Reg_En_30 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_30 : out STD_LOGIC;
Dbg_Shift_30 : out STD_LOGIC;
Dbg_Update_30 : out STD_LOGIC;
Dbg_Rst_30 : out STD_LOGIC;
Dbg_Trig_In_30 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_30 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_30 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_30 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_30 : out STD_LOGIC;
Dbg_TrData_30 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_30 : out STD_LOGIC;
Dbg_TrValid_30 : in STD_LOGIC;
Dbg_AWADDR_30 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_30 : out STD_LOGIC;
Dbg_AWREADY_30 : in STD_LOGIC;
Dbg_WDATA_30 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_30 : out STD_LOGIC;
Dbg_WREADY_30 : in STD_LOGIC;
Dbg_BRESP_30 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_30 : in STD_LOGIC;
Dbg_BREADY_30 : out STD_LOGIC;
Dbg_ARADDR_30 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_30 : out STD_LOGIC;
Dbg_ARREADY_30 : in STD_LOGIC;
Dbg_RDATA_30 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_30 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_30 : in STD_LOGIC;
Dbg_RREADY_30 : out STD_LOGIC;
Dbg_Disable_31 : out STD_LOGIC;
Dbg_Clk_31 : out STD_LOGIC;
Dbg_TDI_31 : out STD_LOGIC;
Dbg_TDO_31 : in STD_LOGIC;
Dbg_Reg_En_31 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_31 : out STD_LOGIC;
Dbg_Shift_31 : out STD_LOGIC;
Dbg_Update_31 : out STD_LOGIC;
Dbg_Rst_31 : out STD_LOGIC;
Dbg_Trig_In_31 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_31 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_31 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_31 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_31 : out STD_LOGIC;
Dbg_TrData_31 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_31 : out STD_LOGIC;
Dbg_TrValid_31 : in STD_LOGIC;
Dbg_AWADDR_31 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_31 : out STD_LOGIC;
Dbg_AWREADY_31 : in STD_LOGIC;
Dbg_WDATA_31 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_31 : out STD_LOGIC;
Dbg_WREADY_31 : in STD_LOGIC;
Dbg_BRESP_31 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_31 : in STD_LOGIC;
Dbg_BREADY_31 : out STD_LOGIC;
Dbg_ARADDR_31 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_31 : out STD_LOGIC;
Dbg_ARREADY_31 : in STD_LOGIC;
Dbg_RDATA_31 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_31 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_31 : in STD_LOGIC;
Dbg_RREADY_31 : out STD_LOGIC;
bscan_ext_tdi : in STD_LOGIC;
bscan_ext_reset : in STD_LOGIC;
bscan_ext_shift : in STD_LOGIC;
bscan_ext_update : in STD_LOGIC;
bscan_ext_capture : in STD_LOGIC;
bscan_ext_sel : in STD_LOGIC;
bscan_ext_drck : in STD_LOGIC;
bscan_ext_tdo : out STD_LOGIC;
Ext_JTAG_DRCK : out STD_LOGIC;
Ext_JTAG_RESET : out STD_LOGIC;
Ext_JTAG_SEL : out STD_LOGIC;
Ext_JTAG_CAPTURE : out STD_LOGIC;
Ext_JTAG_SHIFT : out STD_LOGIC;
Ext_JTAG_UPDATE : out STD_LOGIC;
Ext_JTAG_TDI : out STD_LOGIC;
Ext_JTAG_TDO : in STD_LOGIC
);
attribute C_DATA_SIZE : integer;
attribute C_DATA_SIZE of system_mdm_1_0_MDM : entity is 32;
attribute C_DBG_MEM_ACCESS : integer;
attribute C_DBG_MEM_ACCESS of system_mdm_1_0_MDM : entity is 0;
attribute C_DBG_REG_ACCESS : integer;
attribute C_DBG_REG_ACCESS of system_mdm_1_0_MDM : entity is 0;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of system_mdm_1_0_MDM : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_mdm_1_0_MDM : entity is "artix7";
attribute C_INTERCONNECT : integer;
attribute C_INTERCONNECT of system_mdm_1_0_MDM : entity is 2;
attribute C_JTAG_CHAIN : integer;
attribute C_JTAG_CHAIN of system_mdm_1_0_MDM : entity is 2;
attribute C_MB_DBG_PORTS : integer;
attribute C_MB_DBG_PORTS of system_mdm_1_0_MDM : entity is 1;
attribute C_M_AXIS_DATA_WIDTH : integer;
attribute C_M_AXIS_DATA_WIDTH of system_mdm_1_0_MDM : entity is 32;
attribute C_M_AXIS_ID_WIDTH : integer;
attribute C_M_AXIS_ID_WIDTH of system_mdm_1_0_MDM : entity is 7;
attribute C_M_AXI_ADDR_WIDTH : integer;
attribute C_M_AXI_ADDR_WIDTH of system_mdm_1_0_MDM : entity is 32;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of system_mdm_1_0_MDM : entity is 32;
attribute C_M_AXI_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_THREAD_ID_WIDTH of system_mdm_1_0_MDM : entity is 1;
attribute C_S_AXI_ACLK_FREQ_HZ : integer;
attribute C_S_AXI_ACLK_FREQ_HZ of system_mdm_1_0_MDM : entity is 100000000;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_mdm_1_0_MDM : entity is 4;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_mdm_1_0_MDM : entity is 32;
attribute C_TRACE_CLK_FREQ_HZ : integer;
attribute C_TRACE_CLK_FREQ_HZ of system_mdm_1_0_MDM : entity is 200000000;
attribute C_TRACE_CLK_OUT_PHASE : integer;
attribute C_TRACE_CLK_OUT_PHASE of system_mdm_1_0_MDM : entity is 90;
attribute C_TRACE_DATA_WIDTH : integer;
attribute C_TRACE_DATA_WIDTH of system_mdm_1_0_MDM : entity is 32;
attribute C_TRACE_OUTPUT : integer;
attribute C_TRACE_OUTPUT of system_mdm_1_0_MDM : entity is 0;
attribute C_USE_BSCAN : integer;
attribute C_USE_BSCAN of system_mdm_1_0_MDM : entity is 0;
attribute C_USE_CONFIG_RESET : integer;
attribute C_USE_CONFIG_RESET of system_mdm_1_0_MDM : entity is 0;
attribute C_USE_CROSS_TRIGGER : integer;
attribute C_USE_CROSS_TRIGGER of system_mdm_1_0_MDM : entity is 0;
attribute C_USE_UART : integer;
attribute C_USE_UART of system_mdm_1_0_MDM : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_mdm_1_0_MDM : entity is "MDM";
end system_mdm_1_0_MDM;
architecture STRUCTURE of system_mdm_1_0_MDM is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^dbg_clk_31\ : STD_LOGIC;
signal \^dbg_shift_0\ : STD_LOGIC;
signal \^dbg_update_31\ : STD_LOGIC;
signal \^ext_jtag_capture\ : STD_LOGIC;
signal \^ext_jtag_shift\ : STD_LOGIC;
signal \^ext_jtag_tdi\ : STD_LOGIC;
signal \JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg\ : STD_LOGIC_VECTOR ( 5 to 5 );
signal \JTAG_CONTROL_I/p_20_out__0\ : STD_LOGIC;
signal \JTAG_CONTROL_I/p_43_out__0\ : STD_LOGIC;
signal \JTAG_CONTROL_I/sel\ : STD_LOGIC;
signal MDM_Core_I1_n_0 : STD_LOGIC;
signal MDM_Core_I1_n_19 : STD_LOGIC;
signal \Use_E2.BSCAN_I_n_13\ : STD_LOGIC;
signal \Use_E2.BSCAN_I_n_8\ : STD_LOGIC;
signal drck_i : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 15 to 15 );
signal sel : STD_LOGIC;
signal sel_n_reset : STD_LOGIC;
signal shift_n_reset : STD_LOGIC;
signal tdo : STD_LOGIC;
begin
Dbg_ARADDR_0(14) <= \<const0>\;
Dbg_ARADDR_0(13) <= \<const0>\;
Dbg_ARADDR_0(12) <= \<const0>\;
Dbg_ARADDR_0(11) <= \<const0>\;
Dbg_ARADDR_0(10) <= \<const0>\;
Dbg_ARADDR_0(9) <= \<const0>\;
Dbg_ARADDR_0(8) <= \<const0>\;
Dbg_ARADDR_0(7) <= \<const0>\;
Dbg_ARADDR_0(6) <= \<const0>\;
Dbg_ARADDR_0(5) <= \<const0>\;
Dbg_ARADDR_0(4) <= \<const0>\;
Dbg_ARADDR_0(3) <= \<const0>\;
Dbg_ARADDR_0(2) <= \<const0>\;
Dbg_ARADDR_1(14) <= \<const0>\;
Dbg_ARADDR_1(13) <= \<const0>\;
Dbg_ARADDR_1(12) <= \<const0>\;
Dbg_ARADDR_1(11) <= \<const0>\;
Dbg_ARADDR_1(10) <= \<const0>\;
Dbg_ARADDR_1(9) <= \<const0>\;
Dbg_ARADDR_1(8) <= \<const0>\;
Dbg_ARADDR_1(7) <= \<const0>\;
Dbg_ARADDR_1(6) <= \<const0>\;
Dbg_ARADDR_1(5) <= \<const0>\;
Dbg_ARADDR_1(4) <= \<const0>\;
Dbg_ARADDR_1(3) <= \<const0>\;
Dbg_ARADDR_1(2) <= \<const0>\;
Dbg_ARADDR_10(14) <= \<const0>\;
Dbg_ARADDR_10(13) <= \<const0>\;
Dbg_ARADDR_10(12) <= \<const0>\;
Dbg_ARADDR_10(11) <= \<const0>\;
Dbg_ARADDR_10(10) <= \<const0>\;
Dbg_ARADDR_10(9) <= \<const0>\;
Dbg_ARADDR_10(8) <= \<const0>\;
Dbg_ARADDR_10(7) <= \<const0>\;
Dbg_ARADDR_10(6) <= \<const0>\;
Dbg_ARADDR_10(5) <= \<const0>\;
Dbg_ARADDR_10(4) <= \<const0>\;
Dbg_ARADDR_10(3) <= \<const0>\;
Dbg_ARADDR_10(2) <= \<const0>\;
Dbg_ARADDR_11(14) <= \<const0>\;
Dbg_ARADDR_11(13) <= \<const0>\;
Dbg_ARADDR_11(12) <= \<const0>\;
Dbg_ARADDR_11(11) <= \<const0>\;
Dbg_ARADDR_11(10) <= \<const0>\;
Dbg_ARADDR_11(9) <= \<const0>\;
Dbg_ARADDR_11(8) <= \<const0>\;
Dbg_ARADDR_11(7) <= \<const0>\;
Dbg_ARADDR_11(6) <= \<const0>\;
Dbg_ARADDR_11(5) <= \<const0>\;
Dbg_ARADDR_11(4) <= \<const0>\;
Dbg_ARADDR_11(3) <= \<const0>\;
Dbg_ARADDR_11(2) <= \<const0>\;
Dbg_ARADDR_12(14) <= \<const0>\;
Dbg_ARADDR_12(13) <= \<const0>\;
Dbg_ARADDR_12(12) <= \<const0>\;
Dbg_ARADDR_12(11) <= \<const0>\;
Dbg_ARADDR_12(10) <= \<const0>\;
Dbg_ARADDR_12(9) <= \<const0>\;
Dbg_ARADDR_12(8) <= \<const0>\;
Dbg_ARADDR_12(7) <= \<const0>\;
Dbg_ARADDR_12(6) <= \<const0>\;
Dbg_ARADDR_12(5) <= \<const0>\;
Dbg_ARADDR_12(4) <= \<const0>\;
Dbg_ARADDR_12(3) <= \<const0>\;
Dbg_ARADDR_12(2) <= \<const0>\;
Dbg_ARADDR_13(14) <= \<const0>\;
Dbg_ARADDR_13(13) <= \<const0>\;
Dbg_ARADDR_13(12) <= \<const0>\;
Dbg_ARADDR_13(11) <= \<const0>\;
Dbg_ARADDR_13(10) <= \<const0>\;
Dbg_ARADDR_13(9) <= \<const0>\;
Dbg_ARADDR_13(8) <= \<const0>\;
Dbg_ARADDR_13(7) <= \<const0>\;
Dbg_ARADDR_13(6) <= \<const0>\;
Dbg_ARADDR_13(5) <= \<const0>\;
Dbg_ARADDR_13(4) <= \<const0>\;
Dbg_ARADDR_13(3) <= \<const0>\;
Dbg_ARADDR_13(2) <= \<const0>\;
Dbg_ARADDR_14(14) <= \<const0>\;
Dbg_ARADDR_14(13) <= \<const0>\;
Dbg_ARADDR_14(12) <= \<const0>\;
Dbg_ARADDR_14(11) <= \<const0>\;
Dbg_ARADDR_14(10) <= \<const0>\;
Dbg_ARADDR_14(9) <= \<const0>\;
Dbg_ARADDR_14(8) <= \<const0>\;
Dbg_ARADDR_14(7) <= \<const0>\;
Dbg_ARADDR_14(6) <= \<const0>\;
Dbg_ARADDR_14(5) <= \<const0>\;
Dbg_ARADDR_14(4) <= \<const0>\;
Dbg_ARADDR_14(3) <= \<const0>\;
Dbg_ARADDR_14(2) <= \<const0>\;
Dbg_ARADDR_15(14) <= \<const0>\;
Dbg_ARADDR_15(13) <= \<const0>\;
Dbg_ARADDR_15(12) <= \<const0>\;
Dbg_ARADDR_15(11) <= \<const0>\;
Dbg_ARADDR_15(10) <= \<const0>\;
Dbg_ARADDR_15(9) <= \<const0>\;
Dbg_ARADDR_15(8) <= \<const0>\;
Dbg_ARADDR_15(7) <= \<const0>\;
Dbg_ARADDR_15(6) <= \<const0>\;
Dbg_ARADDR_15(5) <= \<const0>\;
Dbg_ARADDR_15(4) <= \<const0>\;
Dbg_ARADDR_15(3) <= \<const0>\;
Dbg_ARADDR_15(2) <= \<const0>\;
Dbg_ARADDR_16(14) <= \<const0>\;
Dbg_ARADDR_16(13) <= \<const0>\;
Dbg_ARADDR_16(12) <= \<const0>\;
Dbg_ARADDR_16(11) <= \<const0>\;
Dbg_ARADDR_16(10) <= \<const0>\;
Dbg_ARADDR_16(9) <= \<const0>\;
Dbg_ARADDR_16(8) <= \<const0>\;
Dbg_ARADDR_16(7) <= \<const0>\;
Dbg_ARADDR_16(6) <= \<const0>\;
Dbg_ARADDR_16(5) <= \<const0>\;
Dbg_ARADDR_16(4) <= \<const0>\;
Dbg_ARADDR_16(3) <= \<const0>\;
Dbg_ARADDR_16(2) <= \<const0>\;
Dbg_ARADDR_17(14) <= \<const0>\;
Dbg_ARADDR_17(13) <= \<const0>\;
Dbg_ARADDR_17(12) <= \<const0>\;
Dbg_ARADDR_17(11) <= \<const0>\;
Dbg_ARADDR_17(10) <= \<const0>\;
Dbg_ARADDR_17(9) <= \<const0>\;
Dbg_ARADDR_17(8) <= \<const0>\;
Dbg_ARADDR_17(7) <= \<const0>\;
Dbg_ARADDR_17(6) <= \<const0>\;
Dbg_ARADDR_17(5) <= \<const0>\;
Dbg_ARADDR_17(4) <= \<const0>\;
Dbg_ARADDR_17(3) <= \<const0>\;
Dbg_ARADDR_17(2) <= \<const0>\;
Dbg_ARADDR_18(14) <= \<const0>\;
Dbg_ARADDR_18(13) <= \<const0>\;
Dbg_ARADDR_18(12) <= \<const0>\;
Dbg_ARADDR_18(11) <= \<const0>\;
Dbg_ARADDR_18(10) <= \<const0>\;
Dbg_ARADDR_18(9) <= \<const0>\;
Dbg_ARADDR_18(8) <= \<const0>\;
Dbg_ARADDR_18(7) <= \<const0>\;
Dbg_ARADDR_18(6) <= \<const0>\;
Dbg_ARADDR_18(5) <= \<const0>\;
Dbg_ARADDR_18(4) <= \<const0>\;
Dbg_ARADDR_18(3) <= \<const0>\;
Dbg_ARADDR_18(2) <= \<const0>\;
Dbg_ARADDR_19(14) <= \<const0>\;
Dbg_ARADDR_19(13) <= \<const0>\;
Dbg_ARADDR_19(12) <= \<const0>\;
Dbg_ARADDR_19(11) <= \<const0>\;
Dbg_ARADDR_19(10) <= \<const0>\;
Dbg_ARADDR_19(9) <= \<const0>\;
Dbg_ARADDR_19(8) <= \<const0>\;
Dbg_ARADDR_19(7) <= \<const0>\;
Dbg_ARADDR_19(6) <= \<const0>\;
Dbg_ARADDR_19(5) <= \<const0>\;
Dbg_ARADDR_19(4) <= \<const0>\;
Dbg_ARADDR_19(3) <= \<const0>\;
Dbg_ARADDR_19(2) <= \<const0>\;
Dbg_ARADDR_2(14) <= \<const0>\;
Dbg_ARADDR_2(13) <= \<const0>\;
Dbg_ARADDR_2(12) <= \<const0>\;
Dbg_ARADDR_2(11) <= \<const0>\;
Dbg_ARADDR_2(10) <= \<const0>\;
Dbg_ARADDR_2(9) <= \<const0>\;
Dbg_ARADDR_2(8) <= \<const0>\;
Dbg_ARADDR_2(7) <= \<const0>\;
Dbg_ARADDR_2(6) <= \<const0>\;
Dbg_ARADDR_2(5) <= \<const0>\;
Dbg_ARADDR_2(4) <= \<const0>\;
Dbg_ARADDR_2(3) <= \<const0>\;
Dbg_ARADDR_2(2) <= \<const0>\;
Dbg_ARADDR_20(14) <= \<const0>\;
Dbg_ARADDR_20(13) <= \<const0>\;
Dbg_ARADDR_20(12) <= \<const0>\;
Dbg_ARADDR_20(11) <= \<const0>\;
Dbg_ARADDR_20(10) <= \<const0>\;
Dbg_ARADDR_20(9) <= \<const0>\;
Dbg_ARADDR_20(8) <= \<const0>\;
Dbg_ARADDR_20(7) <= \<const0>\;
Dbg_ARADDR_20(6) <= \<const0>\;
Dbg_ARADDR_20(5) <= \<const0>\;
Dbg_ARADDR_20(4) <= \<const0>\;
Dbg_ARADDR_20(3) <= \<const0>\;
Dbg_ARADDR_20(2) <= \<const0>\;
Dbg_ARADDR_21(14) <= \<const0>\;
Dbg_ARADDR_21(13) <= \<const0>\;
Dbg_ARADDR_21(12) <= \<const0>\;
Dbg_ARADDR_21(11) <= \<const0>\;
Dbg_ARADDR_21(10) <= \<const0>\;
Dbg_ARADDR_21(9) <= \<const0>\;
Dbg_ARADDR_21(8) <= \<const0>\;
Dbg_ARADDR_21(7) <= \<const0>\;
Dbg_ARADDR_21(6) <= \<const0>\;
Dbg_ARADDR_21(5) <= \<const0>\;
Dbg_ARADDR_21(4) <= \<const0>\;
Dbg_ARADDR_21(3) <= \<const0>\;
Dbg_ARADDR_21(2) <= \<const0>\;
Dbg_ARADDR_22(14) <= \<const0>\;
Dbg_ARADDR_22(13) <= \<const0>\;
Dbg_ARADDR_22(12) <= \<const0>\;
Dbg_ARADDR_22(11) <= \<const0>\;
Dbg_ARADDR_22(10) <= \<const0>\;
Dbg_ARADDR_22(9) <= \<const0>\;
Dbg_ARADDR_22(8) <= \<const0>\;
Dbg_ARADDR_22(7) <= \<const0>\;
Dbg_ARADDR_22(6) <= \<const0>\;
Dbg_ARADDR_22(5) <= \<const0>\;
Dbg_ARADDR_22(4) <= \<const0>\;
Dbg_ARADDR_22(3) <= \<const0>\;
Dbg_ARADDR_22(2) <= \<const0>\;
Dbg_ARADDR_23(14) <= \<const0>\;
Dbg_ARADDR_23(13) <= \<const0>\;
Dbg_ARADDR_23(12) <= \<const0>\;
Dbg_ARADDR_23(11) <= \<const0>\;
Dbg_ARADDR_23(10) <= \<const0>\;
Dbg_ARADDR_23(9) <= \<const0>\;
Dbg_ARADDR_23(8) <= \<const0>\;
Dbg_ARADDR_23(7) <= \<const0>\;
Dbg_ARADDR_23(6) <= \<const0>\;
Dbg_ARADDR_23(5) <= \<const0>\;
Dbg_ARADDR_23(4) <= \<const0>\;
Dbg_ARADDR_23(3) <= \<const0>\;
Dbg_ARADDR_23(2) <= \<const0>\;
Dbg_ARADDR_24(14) <= \<const0>\;
Dbg_ARADDR_24(13) <= \<const0>\;
Dbg_ARADDR_24(12) <= \<const0>\;
Dbg_ARADDR_24(11) <= \<const0>\;
Dbg_ARADDR_24(10) <= \<const0>\;
Dbg_ARADDR_24(9) <= \<const0>\;
Dbg_ARADDR_24(8) <= \<const0>\;
Dbg_ARADDR_24(7) <= \<const0>\;
Dbg_ARADDR_24(6) <= \<const0>\;
Dbg_ARADDR_24(5) <= \<const0>\;
Dbg_ARADDR_24(4) <= \<const0>\;
Dbg_ARADDR_24(3) <= \<const0>\;
Dbg_ARADDR_24(2) <= \<const0>\;
Dbg_ARADDR_25(14) <= \<const0>\;
Dbg_ARADDR_25(13) <= \<const0>\;
Dbg_ARADDR_25(12) <= \<const0>\;
Dbg_ARADDR_25(11) <= \<const0>\;
Dbg_ARADDR_25(10) <= \<const0>\;
Dbg_ARADDR_25(9) <= \<const0>\;
Dbg_ARADDR_25(8) <= \<const0>\;
Dbg_ARADDR_25(7) <= \<const0>\;
Dbg_ARADDR_25(6) <= \<const0>\;
Dbg_ARADDR_25(5) <= \<const0>\;
Dbg_ARADDR_25(4) <= \<const0>\;
Dbg_ARADDR_25(3) <= \<const0>\;
Dbg_ARADDR_25(2) <= \<const0>\;
Dbg_ARADDR_26(14) <= \<const0>\;
Dbg_ARADDR_26(13) <= \<const0>\;
Dbg_ARADDR_26(12) <= \<const0>\;
Dbg_ARADDR_26(11) <= \<const0>\;
Dbg_ARADDR_26(10) <= \<const0>\;
Dbg_ARADDR_26(9) <= \<const0>\;
Dbg_ARADDR_26(8) <= \<const0>\;
Dbg_ARADDR_26(7) <= \<const0>\;
Dbg_ARADDR_26(6) <= \<const0>\;
Dbg_ARADDR_26(5) <= \<const0>\;
Dbg_ARADDR_26(4) <= \<const0>\;
Dbg_ARADDR_26(3) <= \<const0>\;
Dbg_ARADDR_26(2) <= \<const0>\;
Dbg_ARADDR_27(14) <= \<const0>\;
Dbg_ARADDR_27(13) <= \<const0>\;
Dbg_ARADDR_27(12) <= \<const0>\;
Dbg_ARADDR_27(11) <= \<const0>\;
Dbg_ARADDR_27(10) <= \<const0>\;
Dbg_ARADDR_27(9) <= \<const0>\;
Dbg_ARADDR_27(8) <= \<const0>\;
Dbg_ARADDR_27(7) <= \<const0>\;
Dbg_ARADDR_27(6) <= \<const0>\;
Dbg_ARADDR_27(5) <= \<const0>\;
Dbg_ARADDR_27(4) <= \<const0>\;
Dbg_ARADDR_27(3) <= \<const0>\;
Dbg_ARADDR_27(2) <= \<const0>\;
Dbg_ARADDR_28(14) <= \<const0>\;
Dbg_ARADDR_28(13) <= \<const0>\;
Dbg_ARADDR_28(12) <= \<const0>\;
Dbg_ARADDR_28(11) <= \<const0>\;
Dbg_ARADDR_28(10) <= \<const0>\;
Dbg_ARADDR_28(9) <= \<const0>\;
Dbg_ARADDR_28(8) <= \<const0>\;
Dbg_ARADDR_28(7) <= \<const0>\;
Dbg_ARADDR_28(6) <= \<const0>\;
Dbg_ARADDR_28(5) <= \<const0>\;
Dbg_ARADDR_28(4) <= \<const0>\;
Dbg_ARADDR_28(3) <= \<const0>\;
Dbg_ARADDR_28(2) <= \<const0>\;
Dbg_ARADDR_29(14) <= \<const0>\;
Dbg_ARADDR_29(13) <= \<const0>\;
Dbg_ARADDR_29(12) <= \<const0>\;
Dbg_ARADDR_29(11) <= \<const0>\;
Dbg_ARADDR_29(10) <= \<const0>\;
Dbg_ARADDR_29(9) <= \<const0>\;
Dbg_ARADDR_29(8) <= \<const0>\;
Dbg_ARADDR_29(7) <= \<const0>\;
Dbg_ARADDR_29(6) <= \<const0>\;
Dbg_ARADDR_29(5) <= \<const0>\;
Dbg_ARADDR_29(4) <= \<const0>\;
Dbg_ARADDR_29(3) <= \<const0>\;
Dbg_ARADDR_29(2) <= \<const0>\;
Dbg_ARADDR_3(14) <= \<const0>\;
Dbg_ARADDR_3(13) <= \<const0>\;
Dbg_ARADDR_3(12) <= \<const0>\;
Dbg_ARADDR_3(11) <= \<const0>\;
Dbg_ARADDR_3(10) <= \<const0>\;
Dbg_ARADDR_3(9) <= \<const0>\;
Dbg_ARADDR_3(8) <= \<const0>\;
Dbg_ARADDR_3(7) <= \<const0>\;
Dbg_ARADDR_3(6) <= \<const0>\;
Dbg_ARADDR_3(5) <= \<const0>\;
Dbg_ARADDR_3(4) <= \<const0>\;
Dbg_ARADDR_3(3) <= \<const0>\;
Dbg_ARADDR_3(2) <= \<const0>\;
Dbg_ARADDR_30(14) <= \<const0>\;
Dbg_ARADDR_30(13) <= \<const0>\;
Dbg_ARADDR_30(12) <= \<const0>\;
Dbg_ARADDR_30(11) <= \<const0>\;
Dbg_ARADDR_30(10) <= \<const0>\;
Dbg_ARADDR_30(9) <= \<const0>\;
Dbg_ARADDR_30(8) <= \<const0>\;
Dbg_ARADDR_30(7) <= \<const0>\;
Dbg_ARADDR_30(6) <= \<const0>\;
Dbg_ARADDR_30(5) <= \<const0>\;
Dbg_ARADDR_30(4) <= \<const0>\;
Dbg_ARADDR_30(3) <= \<const0>\;
Dbg_ARADDR_30(2) <= \<const0>\;
Dbg_ARADDR_31(14) <= \<const0>\;
Dbg_ARADDR_31(13) <= \<const0>\;
Dbg_ARADDR_31(12) <= \<const0>\;
Dbg_ARADDR_31(11) <= \<const0>\;
Dbg_ARADDR_31(10) <= \<const0>\;
Dbg_ARADDR_31(9) <= \<const0>\;
Dbg_ARADDR_31(8) <= \<const0>\;
Dbg_ARADDR_31(7) <= \<const0>\;
Dbg_ARADDR_31(6) <= \<const0>\;
Dbg_ARADDR_31(5) <= \<const0>\;
Dbg_ARADDR_31(4) <= \<const0>\;
Dbg_ARADDR_31(3) <= \<const0>\;
Dbg_ARADDR_31(2) <= \<const0>\;
Dbg_ARADDR_4(14) <= \<const0>\;
Dbg_ARADDR_4(13) <= \<const0>\;
Dbg_ARADDR_4(12) <= \<const0>\;
Dbg_ARADDR_4(11) <= \<const0>\;
Dbg_ARADDR_4(10) <= \<const0>\;
Dbg_ARADDR_4(9) <= \<const0>\;
Dbg_ARADDR_4(8) <= \<const0>\;
Dbg_ARADDR_4(7) <= \<const0>\;
Dbg_ARADDR_4(6) <= \<const0>\;
Dbg_ARADDR_4(5) <= \<const0>\;
Dbg_ARADDR_4(4) <= \<const0>\;
Dbg_ARADDR_4(3) <= \<const0>\;
Dbg_ARADDR_4(2) <= \<const0>\;
Dbg_ARADDR_5(14) <= \<const0>\;
Dbg_ARADDR_5(13) <= \<const0>\;
Dbg_ARADDR_5(12) <= \<const0>\;
Dbg_ARADDR_5(11) <= \<const0>\;
Dbg_ARADDR_5(10) <= \<const0>\;
Dbg_ARADDR_5(9) <= \<const0>\;
Dbg_ARADDR_5(8) <= \<const0>\;
Dbg_ARADDR_5(7) <= \<const0>\;
Dbg_ARADDR_5(6) <= \<const0>\;
Dbg_ARADDR_5(5) <= \<const0>\;
Dbg_ARADDR_5(4) <= \<const0>\;
Dbg_ARADDR_5(3) <= \<const0>\;
Dbg_ARADDR_5(2) <= \<const0>\;
Dbg_ARADDR_6(14) <= \<const0>\;
Dbg_ARADDR_6(13) <= \<const0>\;
Dbg_ARADDR_6(12) <= \<const0>\;
Dbg_ARADDR_6(11) <= \<const0>\;
Dbg_ARADDR_6(10) <= \<const0>\;
Dbg_ARADDR_6(9) <= \<const0>\;
Dbg_ARADDR_6(8) <= \<const0>\;
Dbg_ARADDR_6(7) <= \<const0>\;
Dbg_ARADDR_6(6) <= \<const0>\;
Dbg_ARADDR_6(5) <= \<const0>\;
Dbg_ARADDR_6(4) <= \<const0>\;
Dbg_ARADDR_6(3) <= \<const0>\;
Dbg_ARADDR_6(2) <= \<const0>\;
Dbg_ARADDR_7(14) <= \<const0>\;
Dbg_ARADDR_7(13) <= \<const0>\;
Dbg_ARADDR_7(12) <= \<const0>\;
Dbg_ARADDR_7(11) <= \<const0>\;
Dbg_ARADDR_7(10) <= \<const0>\;
Dbg_ARADDR_7(9) <= \<const0>\;
Dbg_ARADDR_7(8) <= \<const0>\;
Dbg_ARADDR_7(7) <= \<const0>\;
Dbg_ARADDR_7(6) <= \<const0>\;
Dbg_ARADDR_7(5) <= \<const0>\;
Dbg_ARADDR_7(4) <= \<const0>\;
Dbg_ARADDR_7(3) <= \<const0>\;
Dbg_ARADDR_7(2) <= \<const0>\;
Dbg_ARADDR_8(14) <= \<const0>\;
Dbg_ARADDR_8(13) <= \<const0>\;
Dbg_ARADDR_8(12) <= \<const0>\;
Dbg_ARADDR_8(11) <= \<const0>\;
Dbg_ARADDR_8(10) <= \<const0>\;
Dbg_ARADDR_8(9) <= \<const0>\;
Dbg_ARADDR_8(8) <= \<const0>\;
Dbg_ARADDR_8(7) <= \<const0>\;
Dbg_ARADDR_8(6) <= \<const0>\;
Dbg_ARADDR_8(5) <= \<const0>\;
Dbg_ARADDR_8(4) <= \<const0>\;
Dbg_ARADDR_8(3) <= \<const0>\;
Dbg_ARADDR_8(2) <= \<const0>\;
Dbg_ARADDR_9(14) <= \<const0>\;
Dbg_ARADDR_9(13) <= \<const0>\;
Dbg_ARADDR_9(12) <= \<const0>\;
Dbg_ARADDR_9(11) <= \<const0>\;
Dbg_ARADDR_9(10) <= \<const0>\;
Dbg_ARADDR_9(9) <= \<const0>\;
Dbg_ARADDR_9(8) <= \<const0>\;
Dbg_ARADDR_9(7) <= \<const0>\;
Dbg_ARADDR_9(6) <= \<const0>\;
Dbg_ARADDR_9(5) <= \<const0>\;
Dbg_ARADDR_9(4) <= \<const0>\;
Dbg_ARADDR_9(3) <= \<const0>\;
Dbg_ARADDR_9(2) <= \<const0>\;
Dbg_ARVALID_0 <= \<const0>\;
Dbg_ARVALID_1 <= \<const0>\;
Dbg_ARVALID_10 <= \<const0>\;
Dbg_ARVALID_11 <= \<const0>\;
Dbg_ARVALID_12 <= \<const0>\;
Dbg_ARVALID_13 <= \<const0>\;
Dbg_ARVALID_14 <= \<const0>\;
Dbg_ARVALID_15 <= \<const0>\;
Dbg_ARVALID_16 <= \<const0>\;
Dbg_ARVALID_17 <= \<const0>\;
Dbg_ARVALID_18 <= \<const0>\;
Dbg_ARVALID_19 <= \<const0>\;
Dbg_ARVALID_2 <= \<const0>\;
Dbg_ARVALID_20 <= \<const0>\;
Dbg_ARVALID_21 <= \<const0>\;
Dbg_ARVALID_22 <= \<const0>\;
Dbg_ARVALID_23 <= \<const0>\;
Dbg_ARVALID_24 <= \<const0>\;
Dbg_ARVALID_25 <= \<const0>\;
Dbg_ARVALID_26 <= \<const0>\;
Dbg_ARVALID_27 <= \<const0>\;
Dbg_ARVALID_28 <= \<const0>\;
Dbg_ARVALID_29 <= \<const0>\;
Dbg_ARVALID_3 <= \<const0>\;
Dbg_ARVALID_30 <= \<const0>\;
Dbg_ARVALID_31 <= \<const0>\;
Dbg_ARVALID_4 <= \<const0>\;
Dbg_ARVALID_5 <= \<const0>\;
Dbg_ARVALID_6 <= \<const0>\;
Dbg_ARVALID_7 <= \<const0>\;
Dbg_ARVALID_8 <= \<const0>\;
Dbg_ARVALID_9 <= \<const0>\;
Dbg_AWADDR_0(14) <= \<const0>\;
Dbg_AWADDR_0(13) <= \<const0>\;
Dbg_AWADDR_0(12) <= \<const0>\;
Dbg_AWADDR_0(11) <= \<const0>\;
Dbg_AWADDR_0(10) <= \<const0>\;
Dbg_AWADDR_0(9) <= \<const0>\;
Dbg_AWADDR_0(8) <= \<const0>\;
Dbg_AWADDR_0(7) <= \<const0>\;
Dbg_AWADDR_0(6) <= \<const0>\;
Dbg_AWADDR_0(5) <= \<const0>\;
Dbg_AWADDR_0(4) <= \<const0>\;
Dbg_AWADDR_0(3) <= \<const0>\;
Dbg_AWADDR_0(2) <= \<const0>\;
Dbg_AWADDR_1(14) <= \<const0>\;
Dbg_AWADDR_1(13) <= \<const0>\;
Dbg_AWADDR_1(12) <= \<const0>\;
Dbg_AWADDR_1(11) <= \<const0>\;
Dbg_AWADDR_1(10) <= \<const0>\;
Dbg_AWADDR_1(9) <= \<const0>\;
Dbg_AWADDR_1(8) <= \<const0>\;
Dbg_AWADDR_1(7) <= \<const0>\;
Dbg_AWADDR_1(6) <= \<const0>\;
Dbg_AWADDR_1(5) <= \<const0>\;
Dbg_AWADDR_1(4) <= \<const0>\;
Dbg_AWADDR_1(3) <= \<const0>\;
Dbg_AWADDR_1(2) <= \<const0>\;
Dbg_AWADDR_10(14) <= \<const0>\;
Dbg_AWADDR_10(13) <= \<const0>\;
Dbg_AWADDR_10(12) <= \<const0>\;
Dbg_AWADDR_10(11) <= \<const0>\;
Dbg_AWADDR_10(10) <= \<const0>\;
Dbg_AWADDR_10(9) <= \<const0>\;
Dbg_AWADDR_10(8) <= \<const0>\;
Dbg_AWADDR_10(7) <= \<const0>\;
Dbg_AWADDR_10(6) <= \<const0>\;
Dbg_AWADDR_10(5) <= \<const0>\;
Dbg_AWADDR_10(4) <= \<const0>\;
Dbg_AWADDR_10(3) <= \<const0>\;
Dbg_AWADDR_10(2) <= \<const0>\;
Dbg_AWADDR_11(14) <= \<const0>\;
Dbg_AWADDR_11(13) <= \<const0>\;
Dbg_AWADDR_11(12) <= \<const0>\;
Dbg_AWADDR_11(11) <= \<const0>\;
Dbg_AWADDR_11(10) <= \<const0>\;
Dbg_AWADDR_11(9) <= \<const0>\;
Dbg_AWADDR_11(8) <= \<const0>\;
Dbg_AWADDR_11(7) <= \<const0>\;
Dbg_AWADDR_11(6) <= \<const0>\;
Dbg_AWADDR_11(5) <= \<const0>\;
Dbg_AWADDR_11(4) <= \<const0>\;
Dbg_AWADDR_11(3) <= \<const0>\;
Dbg_AWADDR_11(2) <= \<const0>\;
Dbg_AWADDR_12(14) <= \<const0>\;
Dbg_AWADDR_12(13) <= \<const0>\;
Dbg_AWADDR_12(12) <= \<const0>\;
Dbg_AWADDR_12(11) <= \<const0>\;
Dbg_AWADDR_12(10) <= \<const0>\;
Dbg_AWADDR_12(9) <= \<const0>\;
Dbg_AWADDR_12(8) <= \<const0>\;
Dbg_AWADDR_12(7) <= \<const0>\;
Dbg_AWADDR_12(6) <= \<const0>\;
Dbg_AWADDR_12(5) <= \<const0>\;
Dbg_AWADDR_12(4) <= \<const0>\;
Dbg_AWADDR_12(3) <= \<const0>\;
Dbg_AWADDR_12(2) <= \<const0>\;
Dbg_AWADDR_13(14) <= \<const0>\;
Dbg_AWADDR_13(13) <= \<const0>\;
Dbg_AWADDR_13(12) <= \<const0>\;
Dbg_AWADDR_13(11) <= \<const0>\;
Dbg_AWADDR_13(10) <= \<const0>\;
Dbg_AWADDR_13(9) <= \<const0>\;
Dbg_AWADDR_13(8) <= \<const0>\;
Dbg_AWADDR_13(7) <= \<const0>\;
Dbg_AWADDR_13(6) <= \<const0>\;
Dbg_AWADDR_13(5) <= \<const0>\;
Dbg_AWADDR_13(4) <= \<const0>\;
Dbg_AWADDR_13(3) <= \<const0>\;
Dbg_AWADDR_13(2) <= \<const0>\;
Dbg_AWADDR_14(14) <= \<const0>\;
Dbg_AWADDR_14(13) <= \<const0>\;
Dbg_AWADDR_14(12) <= \<const0>\;
Dbg_AWADDR_14(11) <= \<const0>\;
Dbg_AWADDR_14(10) <= \<const0>\;
Dbg_AWADDR_14(9) <= \<const0>\;
Dbg_AWADDR_14(8) <= \<const0>\;
Dbg_AWADDR_14(7) <= \<const0>\;
Dbg_AWADDR_14(6) <= \<const0>\;
Dbg_AWADDR_14(5) <= \<const0>\;
Dbg_AWADDR_14(4) <= \<const0>\;
Dbg_AWADDR_14(3) <= \<const0>\;
Dbg_AWADDR_14(2) <= \<const0>\;
Dbg_AWADDR_15(14) <= \<const0>\;
Dbg_AWADDR_15(13) <= \<const0>\;
Dbg_AWADDR_15(12) <= \<const0>\;
Dbg_AWADDR_15(11) <= \<const0>\;
Dbg_AWADDR_15(10) <= \<const0>\;
Dbg_AWADDR_15(9) <= \<const0>\;
Dbg_AWADDR_15(8) <= \<const0>\;
Dbg_AWADDR_15(7) <= \<const0>\;
Dbg_AWADDR_15(6) <= \<const0>\;
Dbg_AWADDR_15(5) <= \<const0>\;
Dbg_AWADDR_15(4) <= \<const0>\;
Dbg_AWADDR_15(3) <= \<const0>\;
Dbg_AWADDR_15(2) <= \<const0>\;
Dbg_AWADDR_16(14) <= \<const0>\;
Dbg_AWADDR_16(13) <= \<const0>\;
Dbg_AWADDR_16(12) <= \<const0>\;
Dbg_AWADDR_16(11) <= \<const0>\;
Dbg_AWADDR_16(10) <= \<const0>\;
Dbg_AWADDR_16(9) <= \<const0>\;
Dbg_AWADDR_16(8) <= \<const0>\;
Dbg_AWADDR_16(7) <= \<const0>\;
Dbg_AWADDR_16(6) <= \<const0>\;
Dbg_AWADDR_16(5) <= \<const0>\;
Dbg_AWADDR_16(4) <= \<const0>\;
Dbg_AWADDR_16(3) <= \<const0>\;
Dbg_AWADDR_16(2) <= \<const0>\;
Dbg_AWADDR_17(14) <= \<const0>\;
Dbg_AWADDR_17(13) <= \<const0>\;
Dbg_AWADDR_17(12) <= \<const0>\;
Dbg_AWADDR_17(11) <= \<const0>\;
Dbg_AWADDR_17(10) <= \<const0>\;
Dbg_AWADDR_17(9) <= \<const0>\;
Dbg_AWADDR_17(8) <= \<const0>\;
Dbg_AWADDR_17(7) <= \<const0>\;
Dbg_AWADDR_17(6) <= \<const0>\;
Dbg_AWADDR_17(5) <= \<const0>\;
Dbg_AWADDR_17(4) <= \<const0>\;
Dbg_AWADDR_17(3) <= \<const0>\;
Dbg_AWADDR_17(2) <= \<const0>\;
Dbg_AWADDR_18(14) <= \<const0>\;
Dbg_AWADDR_18(13) <= \<const0>\;
Dbg_AWADDR_18(12) <= \<const0>\;
Dbg_AWADDR_18(11) <= \<const0>\;
Dbg_AWADDR_18(10) <= \<const0>\;
Dbg_AWADDR_18(9) <= \<const0>\;
Dbg_AWADDR_18(8) <= \<const0>\;
Dbg_AWADDR_18(7) <= \<const0>\;
Dbg_AWADDR_18(6) <= \<const0>\;
Dbg_AWADDR_18(5) <= \<const0>\;
Dbg_AWADDR_18(4) <= \<const0>\;
Dbg_AWADDR_18(3) <= \<const0>\;
Dbg_AWADDR_18(2) <= \<const0>\;
Dbg_AWADDR_19(14) <= \<const0>\;
Dbg_AWADDR_19(13) <= \<const0>\;
Dbg_AWADDR_19(12) <= \<const0>\;
Dbg_AWADDR_19(11) <= \<const0>\;
Dbg_AWADDR_19(10) <= \<const0>\;
Dbg_AWADDR_19(9) <= \<const0>\;
Dbg_AWADDR_19(8) <= \<const0>\;
Dbg_AWADDR_19(7) <= \<const0>\;
Dbg_AWADDR_19(6) <= \<const0>\;
Dbg_AWADDR_19(5) <= \<const0>\;
Dbg_AWADDR_19(4) <= \<const0>\;
Dbg_AWADDR_19(3) <= \<const0>\;
Dbg_AWADDR_19(2) <= \<const0>\;
Dbg_AWADDR_2(14) <= \<const0>\;
Dbg_AWADDR_2(13) <= \<const0>\;
Dbg_AWADDR_2(12) <= \<const0>\;
Dbg_AWADDR_2(11) <= \<const0>\;
Dbg_AWADDR_2(10) <= \<const0>\;
Dbg_AWADDR_2(9) <= \<const0>\;
Dbg_AWADDR_2(8) <= \<const0>\;
Dbg_AWADDR_2(7) <= \<const0>\;
Dbg_AWADDR_2(6) <= \<const0>\;
Dbg_AWADDR_2(5) <= \<const0>\;
Dbg_AWADDR_2(4) <= \<const0>\;
Dbg_AWADDR_2(3) <= \<const0>\;
Dbg_AWADDR_2(2) <= \<const0>\;
Dbg_AWADDR_20(14) <= \<const0>\;
Dbg_AWADDR_20(13) <= \<const0>\;
Dbg_AWADDR_20(12) <= \<const0>\;
Dbg_AWADDR_20(11) <= \<const0>\;
Dbg_AWADDR_20(10) <= \<const0>\;
Dbg_AWADDR_20(9) <= \<const0>\;
Dbg_AWADDR_20(8) <= \<const0>\;
Dbg_AWADDR_20(7) <= \<const0>\;
Dbg_AWADDR_20(6) <= \<const0>\;
Dbg_AWADDR_20(5) <= \<const0>\;
Dbg_AWADDR_20(4) <= \<const0>\;
Dbg_AWADDR_20(3) <= \<const0>\;
Dbg_AWADDR_20(2) <= \<const0>\;
Dbg_AWADDR_21(14) <= \<const0>\;
Dbg_AWADDR_21(13) <= \<const0>\;
Dbg_AWADDR_21(12) <= \<const0>\;
Dbg_AWADDR_21(11) <= \<const0>\;
Dbg_AWADDR_21(10) <= \<const0>\;
Dbg_AWADDR_21(9) <= \<const0>\;
Dbg_AWADDR_21(8) <= \<const0>\;
Dbg_AWADDR_21(7) <= \<const0>\;
Dbg_AWADDR_21(6) <= \<const0>\;
Dbg_AWADDR_21(5) <= \<const0>\;
Dbg_AWADDR_21(4) <= \<const0>\;
Dbg_AWADDR_21(3) <= \<const0>\;
Dbg_AWADDR_21(2) <= \<const0>\;
Dbg_AWADDR_22(14) <= \<const0>\;
Dbg_AWADDR_22(13) <= \<const0>\;
Dbg_AWADDR_22(12) <= \<const0>\;
Dbg_AWADDR_22(11) <= \<const0>\;
Dbg_AWADDR_22(10) <= \<const0>\;
Dbg_AWADDR_22(9) <= \<const0>\;
Dbg_AWADDR_22(8) <= \<const0>\;
Dbg_AWADDR_22(7) <= \<const0>\;
Dbg_AWADDR_22(6) <= \<const0>\;
Dbg_AWADDR_22(5) <= \<const0>\;
Dbg_AWADDR_22(4) <= \<const0>\;
Dbg_AWADDR_22(3) <= \<const0>\;
Dbg_AWADDR_22(2) <= \<const0>\;
Dbg_AWADDR_23(14) <= \<const0>\;
Dbg_AWADDR_23(13) <= \<const0>\;
Dbg_AWADDR_23(12) <= \<const0>\;
Dbg_AWADDR_23(11) <= \<const0>\;
Dbg_AWADDR_23(10) <= \<const0>\;
Dbg_AWADDR_23(9) <= \<const0>\;
Dbg_AWADDR_23(8) <= \<const0>\;
Dbg_AWADDR_23(7) <= \<const0>\;
Dbg_AWADDR_23(6) <= \<const0>\;
Dbg_AWADDR_23(5) <= \<const0>\;
Dbg_AWADDR_23(4) <= \<const0>\;
Dbg_AWADDR_23(3) <= \<const0>\;
Dbg_AWADDR_23(2) <= \<const0>\;
Dbg_AWADDR_24(14) <= \<const0>\;
Dbg_AWADDR_24(13) <= \<const0>\;
Dbg_AWADDR_24(12) <= \<const0>\;
Dbg_AWADDR_24(11) <= \<const0>\;
Dbg_AWADDR_24(10) <= \<const0>\;
Dbg_AWADDR_24(9) <= \<const0>\;
Dbg_AWADDR_24(8) <= \<const0>\;
Dbg_AWADDR_24(7) <= \<const0>\;
Dbg_AWADDR_24(6) <= \<const0>\;
Dbg_AWADDR_24(5) <= \<const0>\;
Dbg_AWADDR_24(4) <= \<const0>\;
Dbg_AWADDR_24(3) <= \<const0>\;
Dbg_AWADDR_24(2) <= \<const0>\;
Dbg_AWADDR_25(14) <= \<const0>\;
Dbg_AWADDR_25(13) <= \<const0>\;
Dbg_AWADDR_25(12) <= \<const0>\;
Dbg_AWADDR_25(11) <= \<const0>\;
Dbg_AWADDR_25(10) <= \<const0>\;
Dbg_AWADDR_25(9) <= \<const0>\;
Dbg_AWADDR_25(8) <= \<const0>\;
Dbg_AWADDR_25(7) <= \<const0>\;
Dbg_AWADDR_25(6) <= \<const0>\;
Dbg_AWADDR_25(5) <= \<const0>\;
Dbg_AWADDR_25(4) <= \<const0>\;
Dbg_AWADDR_25(3) <= \<const0>\;
Dbg_AWADDR_25(2) <= \<const0>\;
Dbg_AWADDR_26(14) <= \<const0>\;
Dbg_AWADDR_26(13) <= \<const0>\;
Dbg_AWADDR_26(12) <= \<const0>\;
Dbg_AWADDR_26(11) <= \<const0>\;
Dbg_AWADDR_26(10) <= \<const0>\;
Dbg_AWADDR_26(9) <= \<const0>\;
Dbg_AWADDR_26(8) <= \<const0>\;
Dbg_AWADDR_26(7) <= \<const0>\;
Dbg_AWADDR_26(6) <= \<const0>\;
Dbg_AWADDR_26(5) <= \<const0>\;
Dbg_AWADDR_26(4) <= \<const0>\;
Dbg_AWADDR_26(3) <= \<const0>\;
Dbg_AWADDR_26(2) <= \<const0>\;
Dbg_AWADDR_27(14) <= \<const0>\;
Dbg_AWADDR_27(13) <= \<const0>\;
Dbg_AWADDR_27(12) <= \<const0>\;
Dbg_AWADDR_27(11) <= \<const0>\;
Dbg_AWADDR_27(10) <= \<const0>\;
Dbg_AWADDR_27(9) <= \<const0>\;
Dbg_AWADDR_27(8) <= \<const0>\;
Dbg_AWADDR_27(7) <= \<const0>\;
Dbg_AWADDR_27(6) <= \<const0>\;
Dbg_AWADDR_27(5) <= \<const0>\;
Dbg_AWADDR_27(4) <= \<const0>\;
Dbg_AWADDR_27(3) <= \<const0>\;
Dbg_AWADDR_27(2) <= \<const0>\;
Dbg_AWADDR_28(14) <= \<const0>\;
Dbg_AWADDR_28(13) <= \<const0>\;
Dbg_AWADDR_28(12) <= \<const0>\;
Dbg_AWADDR_28(11) <= \<const0>\;
Dbg_AWADDR_28(10) <= \<const0>\;
Dbg_AWADDR_28(9) <= \<const0>\;
Dbg_AWADDR_28(8) <= \<const0>\;
Dbg_AWADDR_28(7) <= \<const0>\;
Dbg_AWADDR_28(6) <= \<const0>\;
Dbg_AWADDR_28(5) <= \<const0>\;
Dbg_AWADDR_28(4) <= \<const0>\;
Dbg_AWADDR_28(3) <= \<const0>\;
Dbg_AWADDR_28(2) <= \<const0>\;
Dbg_AWADDR_29(14) <= \<const0>\;
Dbg_AWADDR_29(13) <= \<const0>\;
Dbg_AWADDR_29(12) <= \<const0>\;
Dbg_AWADDR_29(11) <= \<const0>\;
Dbg_AWADDR_29(10) <= \<const0>\;
Dbg_AWADDR_29(9) <= \<const0>\;
Dbg_AWADDR_29(8) <= \<const0>\;
Dbg_AWADDR_29(7) <= \<const0>\;
Dbg_AWADDR_29(6) <= \<const0>\;
Dbg_AWADDR_29(5) <= \<const0>\;
Dbg_AWADDR_29(4) <= \<const0>\;
Dbg_AWADDR_29(3) <= \<const0>\;
Dbg_AWADDR_29(2) <= \<const0>\;
Dbg_AWADDR_3(14) <= \<const0>\;
Dbg_AWADDR_3(13) <= \<const0>\;
Dbg_AWADDR_3(12) <= \<const0>\;
Dbg_AWADDR_3(11) <= \<const0>\;
Dbg_AWADDR_3(10) <= \<const0>\;
Dbg_AWADDR_3(9) <= \<const0>\;
Dbg_AWADDR_3(8) <= \<const0>\;
Dbg_AWADDR_3(7) <= \<const0>\;
Dbg_AWADDR_3(6) <= \<const0>\;
Dbg_AWADDR_3(5) <= \<const0>\;
Dbg_AWADDR_3(4) <= \<const0>\;
Dbg_AWADDR_3(3) <= \<const0>\;
Dbg_AWADDR_3(2) <= \<const0>\;
Dbg_AWADDR_30(14) <= \<const0>\;
Dbg_AWADDR_30(13) <= \<const0>\;
Dbg_AWADDR_30(12) <= \<const0>\;
Dbg_AWADDR_30(11) <= \<const0>\;
Dbg_AWADDR_30(10) <= \<const0>\;
Dbg_AWADDR_30(9) <= \<const0>\;
Dbg_AWADDR_30(8) <= \<const0>\;
Dbg_AWADDR_30(7) <= \<const0>\;
Dbg_AWADDR_30(6) <= \<const0>\;
Dbg_AWADDR_30(5) <= \<const0>\;
Dbg_AWADDR_30(4) <= \<const0>\;
Dbg_AWADDR_30(3) <= \<const0>\;
Dbg_AWADDR_30(2) <= \<const0>\;
Dbg_AWADDR_31(14) <= \<const0>\;
Dbg_AWADDR_31(13) <= \<const0>\;
Dbg_AWADDR_31(12) <= \<const0>\;
Dbg_AWADDR_31(11) <= \<const0>\;
Dbg_AWADDR_31(10) <= \<const0>\;
Dbg_AWADDR_31(9) <= \<const0>\;
Dbg_AWADDR_31(8) <= \<const0>\;
Dbg_AWADDR_31(7) <= \<const0>\;
Dbg_AWADDR_31(6) <= \<const0>\;
Dbg_AWADDR_31(5) <= \<const0>\;
Dbg_AWADDR_31(4) <= \<const0>\;
Dbg_AWADDR_31(3) <= \<const0>\;
Dbg_AWADDR_31(2) <= \<const0>\;
Dbg_AWADDR_4(14) <= \<const0>\;
Dbg_AWADDR_4(13) <= \<const0>\;
Dbg_AWADDR_4(12) <= \<const0>\;
Dbg_AWADDR_4(11) <= \<const0>\;
Dbg_AWADDR_4(10) <= \<const0>\;
Dbg_AWADDR_4(9) <= \<const0>\;
Dbg_AWADDR_4(8) <= \<const0>\;
Dbg_AWADDR_4(7) <= \<const0>\;
Dbg_AWADDR_4(6) <= \<const0>\;
Dbg_AWADDR_4(5) <= \<const0>\;
Dbg_AWADDR_4(4) <= \<const0>\;
Dbg_AWADDR_4(3) <= \<const0>\;
Dbg_AWADDR_4(2) <= \<const0>\;
Dbg_AWADDR_5(14) <= \<const0>\;
Dbg_AWADDR_5(13) <= \<const0>\;
Dbg_AWADDR_5(12) <= \<const0>\;
Dbg_AWADDR_5(11) <= \<const0>\;
Dbg_AWADDR_5(10) <= \<const0>\;
Dbg_AWADDR_5(9) <= \<const0>\;
Dbg_AWADDR_5(8) <= \<const0>\;
Dbg_AWADDR_5(7) <= \<const0>\;
Dbg_AWADDR_5(6) <= \<const0>\;
Dbg_AWADDR_5(5) <= \<const0>\;
Dbg_AWADDR_5(4) <= \<const0>\;
Dbg_AWADDR_5(3) <= \<const0>\;
Dbg_AWADDR_5(2) <= \<const0>\;
Dbg_AWADDR_6(14) <= \<const0>\;
Dbg_AWADDR_6(13) <= \<const0>\;
Dbg_AWADDR_6(12) <= \<const0>\;
Dbg_AWADDR_6(11) <= \<const0>\;
Dbg_AWADDR_6(10) <= \<const0>\;
Dbg_AWADDR_6(9) <= \<const0>\;
Dbg_AWADDR_6(8) <= \<const0>\;
Dbg_AWADDR_6(7) <= \<const0>\;
Dbg_AWADDR_6(6) <= \<const0>\;
Dbg_AWADDR_6(5) <= \<const0>\;
Dbg_AWADDR_6(4) <= \<const0>\;
Dbg_AWADDR_6(3) <= \<const0>\;
Dbg_AWADDR_6(2) <= \<const0>\;
Dbg_AWADDR_7(14) <= \<const0>\;
Dbg_AWADDR_7(13) <= \<const0>\;
Dbg_AWADDR_7(12) <= \<const0>\;
Dbg_AWADDR_7(11) <= \<const0>\;
Dbg_AWADDR_7(10) <= \<const0>\;
Dbg_AWADDR_7(9) <= \<const0>\;
Dbg_AWADDR_7(8) <= \<const0>\;
Dbg_AWADDR_7(7) <= \<const0>\;
Dbg_AWADDR_7(6) <= \<const0>\;
Dbg_AWADDR_7(5) <= \<const0>\;
Dbg_AWADDR_7(4) <= \<const0>\;
Dbg_AWADDR_7(3) <= \<const0>\;
Dbg_AWADDR_7(2) <= \<const0>\;
Dbg_AWADDR_8(14) <= \<const0>\;
Dbg_AWADDR_8(13) <= \<const0>\;
Dbg_AWADDR_8(12) <= \<const0>\;
Dbg_AWADDR_8(11) <= \<const0>\;
Dbg_AWADDR_8(10) <= \<const0>\;
Dbg_AWADDR_8(9) <= \<const0>\;
Dbg_AWADDR_8(8) <= \<const0>\;
Dbg_AWADDR_8(7) <= \<const0>\;
Dbg_AWADDR_8(6) <= \<const0>\;
Dbg_AWADDR_8(5) <= \<const0>\;
Dbg_AWADDR_8(4) <= \<const0>\;
Dbg_AWADDR_8(3) <= \<const0>\;
Dbg_AWADDR_8(2) <= \<const0>\;
Dbg_AWADDR_9(14) <= \<const0>\;
Dbg_AWADDR_9(13) <= \<const0>\;
Dbg_AWADDR_9(12) <= \<const0>\;
Dbg_AWADDR_9(11) <= \<const0>\;
Dbg_AWADDR_9(10) <= \<const0>\;
Dbg_AWADDR_9(9) <= \<const0>\;
Dbg_AWADDR_9(8) <= \<const0>\;
Dbg_AWADDR_9(7) <= \<const0>\;
Dbg_AWADDR_9(6) <= \<const0>\;
Dbg_AWADDR_9(5) <= \<const0>\;
Dbg_AWADDR_9(4) <= \<const0>\;
Dbg_AWADDR_9(3) <= \<const0>\;
Dbg_AWADDR_9(2) <= \<const0>\;
Dbg_AWVALID_0 <= \<const0>\;
Dbg_AWVALID_1 <= \<const0>\;
Dbg_AWVALID_10 <= \<const0>\;
Dbg_AWVALID_11 <= \<const0>\;
Dbg_AWVALID_12 <= \<const0>\;
Dbg_AWVALID_13 <= \<const0>\;
Dbg_AWVALID_14 <= \<const0>\;
Dbg_AWVALID_15 <= \<const0>\;
Dbg_AWVALID_16 <= \<const0>\;
Dbg_AWVALID_17 <= \<const0>\;
Dbg_AWVALID_18 <= \<const0>\;
Dbg_AWVALID_19 <= \<const0>\;
Dbg_AWVALID_2 <= \<const0>\;
Dbg_AWVALID_20 <= \<const0>\;
Dbg_AWVALID_21 <= \<const0>\;
Dbg_AWVALID_22 <= \<const0>\;
Dbg_AWVALID_23 <= \<const0>\;
Dbg_AWVALID_24 <= \<const0>\;
Dbg_AWVALID_25 <= \<const0>\;
Dbg_AWVALID_26 <= \<const0>\;
Dbg_AWVALID_27 <= \<const0>\;
Dbg_AWVALID_28 <= \<const0>\;
Dbg_AWVALID_29 <= \<const0>\;
Dbg_AWVALID_3 <= \<const0>\;
Dbg_AWVALID_30 <= \<const0>\;
Dbg_AWVALID_31 <= \<const0>\;
Dbg_AWVALID_4 <= \<const0>\;
Dbg_AWVALID_5 <= \<const0>\;
Dbg_AWVALID_6 <= \<const0>\;
Dbg_AWVALID_7 <= \<const0>\;
Dbg_AWVALID_8 <= \<const0>\;
Dbg_AWVALID_9 <= \<const0>\;
Dbg_BREADY_0 <= \<const0>\;
Dbg_BREADY_1 <= \<const0>\;
Dbg_BREADY_10 <= \<const0>\;
Dbg_BREADY_11 <= \<const0>\;
Dbg_BREADY_12 <= \<const0>\;
Dbg_BREADY_13 <= \<const0>\;
Dbg_BREADY_14 <= \<const0>\;
Dbg_BREADY_15 <= \<const0>\;
Dbg_BREADY_16 <= \<const0>\;
Dbg_BREADY_17 <= \<const0>\;
Dbg_BREADY_18 <= \<const0>\;
Dbg_BREADY_19 <= \<const0>\;
Dbg_BREADY_2 <= \<const0>\;
Dbg_BREADY_20 <= \<const0>\;
Dbg_BREADY_21 <= \<const0>\;
Dbg_BREADY_22 <= \<const0>\;
Dbg_BREADY_23 <= \<const0>\;
Dbg_BREADY_24 <= \<const0>\;
Dbg_BREADY_25 <= \<const0>\;
Dbg_BREADY_26 <= \<const0>\;
Dbg_BREADY_27 <= \<const0>\;
Dbg_BREADY_28 <= \<const0>\;
Dbg_BREADY_29 <= \<const0>\;
Dbg_BREADY_3 <= \<const0>\;
Dbg_BREADY_30 <= \<const0>\;
Dbg_BREADY_31 <= \<const0>\;
Dbg_BREADY_4 <= \<const0>\;
Dbg_BREADY_5 <= \<const0>\;
Dbg_BREADY_6 <= \<const0>\;
Dbg_BREADY_7 <= \<const0>\;
Dbg_BREADY_8 <= \<const0>\;
Dbg_BREADY_9 <= \<const0>\;
Dbg_Capture_0 <= \^ext_jtag_capture\;
Dbg_Capture_1 <= \^ext_jtag_capture\;
Dbg_Capture_10 <= \^ext_jtag_capture\;
Dbg_Capture_11 <= \^ext_jtag_capture\;
Dbg_Capture_12 <= \^ext_jtag_capture\;
Dbg_Capture_13 <= \^ext_jtag_capture\;
Dbg_Capture_14 <= \^ext_jtag_capture\;
Dbg_Capture_15 <= \^ext_jtag_capture\;
Dbg_Capture_16 <= \^ext_jtag_capture\;
Dbg_Capture_17 <= \^ext_jtag_capture\;
Dbg_Capture_18 <= \^ext_jtag_capture\;
Dbg_Capture_19 <= \^ext_jtag_capture\;
Dbg_Capture_2 <= \^ext_jtag_capture\;
Dbg_Capture_20 <= \^ext_jtag_capture\;
Dbg_Capture_21 <= \^ext_jtag_capture\;
Dbg_Capture_22 <= \^ext_jtag_capture\;
Dbg_Capture_23 <= \^ext_jtag_capture\;
Dbg_Capture_24 <= \^ext_jtag_capture\;
Dbg_Capture_25 <= \^ext_jtag_capture\;
Dbg_Capture_26 <= \^ext_jtag_capture\;
Dbg_Capture_27 <= \^ext_jtag_capture\;
Dbg_Capture_28 <= \^ext_jtag_capture\;
Dbg_Capture_29 <= \^ext_jtag_capture\;
Dbg_Capture_3 <= \^ext_jtag_capture\;
Dbg_Capture_30 <= \^ext_jtag_capture\;
Dbg_Capture_31 <= \^ext_jtag_capture\;
Dbg_Capture_4 <= \^ext_jtag_capture\;
Dbg_Capture_5 <= \^ext_jtag_capture\;
Dbg_Capture_6 <= \^ext_jtag_capture\;
Dbg_Capture_7 <= \^ext_jtag_capture\;
Dbg_Capture_8 <= \^ext_jtag_capture\;
Dbg_Capture_9 <= \^ext_jtag_capture\;
Dbg_Clk_0 <= \^dbg_clk_31\;
Dbg_Clk_1 <= \^dbg_clk_31\;
Dbg_Clk_10 <= \^dbg_clk_31\;
Dbg_Clk_11 <= \^dbg_clk_31\;
Dbg_Clk_12 <= \^dbg_clk_31\;
Dbg_Clk_13 <= \^dbg_clk_31\;
Dbg_Clk_14 <= \^dbg_clk_31\;
Dbg_Clk_15 <= \^dbg_clk_31\;
Dbg_Clk_16 <= \^dbg_clk_31\;
Dbg_Clk_17 <= \^dbg_clk_31\;
Dbg_Clk_18 <= \^dbg_clk_31\;
Dbg_Clk_19 <= \^dbg_clk_31\;
Dbg_Clk_2 <= \^dbg_clk_31\;
Dbg_Clk_20 <= \^dbg_clk_31\;
Dbg_Clk_21 <= \^dbg_clk_31\;
Dbg_Clk_22 <= \^dbg_clk_31\;
Dbg_Clk_23 <= \^dbg_clk_31\;
Dbg_Clk_24 <= \^dbg_clk_31\;
Dbg_Clk_25 <= \^dbg_clk_31\;
Dbg_Clk_26 <= \^dbg_clk_31\;
Dbg_Clk_27 <= \^dbg_clk_31\;
Dbg_Clk_28 <= \^dbg_clk_31\;
Dbg_Clk_29 <= \^dbg_clk_31\;
Dbg_Clk_3 <= \^dbg_clk_31\;
Dbg_Clk_30 <= \^dbg_clk_31\;
Dbg_Clk_31 <= \^dbg_clk_31\;
Dbg_Clk_4 <= \^dbg_clk_31\;
Dbg_Clk_5 <= \^dbg_clk_31\;
Dbg_Clk_6 <= \^dbg_clk_31\;
Dbg_Clk_7 <= \^dbg_clk_31\;
Dbg_Clk_8 <= \^dbg_clk_31\;
Dbg_Clk_9 <= \^dbg_clk_31\;
Dbg_Disable_1 <= \<const1>\;
Dbg_Disable_10 <= \<const1>\;
Dbg_Disable_11 <= \<const1>\;
Dbg_Disable_12 <= \<const1>\;
Dbg_Disable_13 <= \<const1>\;
Dbg_Disable_14 <= \<const1>\;
Dbg_Disable_15 <= \<const1>\;
Dbg_Disable_16 <= \<const1>\;
Dbg_Disable_17 <= \<const1>\;
Dbg_Disable_18 <= \<const1>\;
Dbg_Disable_19 <= \<const1>\;
Dbg_Disable_2 <= \<const1>\;
Dbg_Disable_20 <= \<const1>\;
Dbg_Disable_21 <= \<const1>\;
Dbg_Disable_22 <= \<const1>\;
Dbg_Disable_23 <= \<const1>\;
Dbg_Disable_24 <= \<const1>\;
Dbg_Disable_25 <= \<const1>\;
Dbg_Disable_26 <= \<const1>\;
Dbg_Disable_27 <= \<const1>\;
Dbg_Disable_28 <= \<const1>\;
Dbg_Disable_29 <= \<const1>\;
Dbg_Disable_3 <= \<const1>\;
Dbg_Disable_30 <= \<const1>\;
Dbg_Disable_31 <= \<const1>\;
Dbg_Disable_4 <= \<const1>\;
Dbg_Disable_5 <= \<const1>\;
Dbg_Disable_6 <= \<const1>\;
Dbg_Disable_7 <= \<const1>\;
Dbg_Disable_8 <= \<const1>\;
Dbg_Disable_9 <= \<const1>\;
Dbg_RREADY_0 <= \<const0>\;
Dbg_RREADY_1 <= \<const0>\;
Dbg_RREADY_10 <= \<const0>\;
Dbg_RREADY_11 <= \<const0>\;
Dbg_RREADY_12 <= \<const0>\;
Dbg_RREADY_13 <= \<const0>\;
Dbg_RREADY_14 <= \<const0>\;
Dbg_RREADY_15 <= \<const0>\;
Dbg_RREADY_16 <= \<const0>\;
Dbg_RREADY_17 <= \<const0>\;
Dbg_RREADY_18 <= \<const0>\;
Dbg_RREADY_19 <= \<const0>\;
Dbg_RREADY_2 <= \<const0>\;
Dbg_RREADY_20 <= \<const0>\;
Dbg_RREADY_21 <= \<const0>\;
Dbg_RREADY_22 <= \<const0>\;
Dbg_RREADY_23 <= \<const0>\;
Dbg_RREADY_24 <= \<const0>\;
Dbg_RREADY_25 <= \<const0>\;
Dbg_RREADY_26 <= \<const0>\;
Dbg_RREADY_27 <= \<const0>\;
Dbg_RREADY_28 <= \<const0>\;
Dbg_RREADY_29 <= \<const0>\;
Dbg_RREADY_3 <= \<const0>\;
Dbg_RREADY_30 <= \<const0>\;
Dbg_RREADY_31 <= \<const0>\;
Dbg_RREADY_4 <= \<const0>\;
Dbg_RREADY_5 <= \<const0>\;
Dbg_RREADY_6 <= \<const0>\;
Dbg_RREADY_7 <= \<const0>\;
Dbg_RREADY_8 <= \<const0>\;
Dbg_RREADY_9 <= \<const0>\;
Dbg_Reg_En_1(0) <= \<const0>\;
Dbg_Reg_En_1(1) <= \<const0>\;
Dbg_Reg_En_1(2) <= \<const0>\;
Dbg_Reg_En_1(3) <= \<const0>\;
Dbg_Reg_En_1(4) <= \<const0>\;
Dbg_Reg_En_1(5) <= \<const0>\;
Dbg_Reg_En_1(6) <= \<const0>\;
Dbg_Reg_En_1(7) <= \<const0>\;
Dbg_Reg_En_10(0) <= \<const0>\;
Dbg_Reg_En_10(1) <= \<const0>\;
Dbg_Reg_En_10(2) <= \<const0>\;
Dbg_Reg_En_10(3) <= \<const0>\;
Dbg_Reg_En_10(4) <= \<const0>\;
Dbg_Reg_En_10(5) <= \<const0>\;
Dbg_Reg_En_10(6) <= \<const0>\;
Dbg_Reg_En_10(7) <= \<const0>\;
Dbg_Reg_En_11(0) <= \<const0>\;
Dbg_Reg_En_11(1) <= \<const0>\;
Dbg_Reg_En_11(2) <= \<const0>\;
Dbg_Reg_En_11(3) <= \<const0>\;
Dbg_Reg_En_11(4) <= \<const0>\;
Dbg_Reg_En_11(5) <= \<const0>\;
Dbg_Reg_En_11(6) <= \<const0>\;
Dbg_Reg_En_11(7) <= \<const0>\;
Dbg_Reg_En_12(0) <= \<const0>\;
Dbg_Reg_En_12(1) <= \<const0>\;
Dbg_Reg_En_12(2) <= \<const0>\;
Dbg_Reg_En_12(3) <= \<const0>\;
Dbg_Reg_En_12(4) <= \<const0>\;
Dbg_Reg_En_12(5) <= \<const0>\;
Dbg_Reg_En_12(6) <= \<const0>\;
Dbg_Reg_En_12(7) <= \<const0>\;
Dbg_Reg_En_13(0) <= \<const0>\;
Dbg_Reg_En_13(1) <= \<const0>\;
Dbg_Reg_En_13(2) <= \<const0>\;
Dbg_Reg_En_13(3) <= \<const0>\;
Dbg_Reg_En_13(4) <= \<const0>\;
Dbg_Reg_En_13(5) <= \<const0>\;
Dbg_Reg_En_13(6) <= \<const0>\;
Dbg_Reg_En_13(7) <= \<const0>\;
Dbg_Reg_En_14(0) <= \<const0>\;
Dbg_Reg_En_14(1) <= \<const0>\;
Dbg_Reg_En_14(2) <= \<const0>\;
Dbg_Reg_En_14(3) <= \<const0>\;
Dbg_Reg_En_14(4) <= \<const0>\;
Dbg_Reg_En_14(5) <= \<const0>\;
Dbg_Reg_En_14(6) <= \<const0>\;
Dbg_Reg_En_14(7) <= \<const0>\;
Dbg_Reg_En_15(0) <= \<const0>\;
Dbg_Reg_En_15(1) <= \<const0>\;
Dbg_Reg_En_15(2) <= \<const0>\;
Dbg_Reg_En_15(3) <= \<const0>\;
Dbg_Reg_En_15(4) <= \<const0>\;
Dbg_Reg_En_15(5) <= \<const0>\;
Dbg_Reg_En_15(6) <= \<const0>\;
Dbg_Reg_En_15(7) <= \<const0>\;
Dbg_Reg_En_16(0) <= \<const0>\;
Dbg_Reg_En_16(1) <= \<const0>\;
Dbg_Reg_En_16(2) <= \<const0>\;
Dbg_Reg_En_16(3) <= \<const0>\;
Dbg_Reg_En_16(4) <= \<const0>\;
Dbg_Reg_En_16(5) <= \<const0>\;
Dbg_Reg_En_16(6) <= \<const0>\;
Dbg_Reg_En_16(7) <= \<const0>\;
Dbg_Reg_En_17(0) <= \<const0>\;
Dbg_Reg_En_17(1) <= \<const0>\;
Dbg_Reg_En_17(2) <= \<const0>\;
Dbg_Reg_En_17(3) <= \<const0>\;
Dbg_Reg_En_17(4) <= \<const0>\;
Dbg_Reg_En_17(5) <= \<const0>\;
Dbg_Reg_En_17(6) <= \<const0>\;
Dbg_Reg_En_17(7) <= \<const0>\;
Dbg_Reg_En_18(0) <= \<const0>\;
Dbg_Reg_En_18(1) <= \<const0>\;
Dbg_Reg_En_18(2) <= \<const0>\;
Dbg_Reg_En_18(3) <= \<const0>\;
Dbg_Reg_En_18(4) <= \<const0>\;
Dbg_Reg_En_18(5) <= \<const0>\;
Dbg_Reg_En_18(6) <= \<const0>\;
Dbg_Reg_En_18(7) <= \<const0>\;
Dbg_Reg_En_19(0) <= \<const0>\;
Dbg_Reg_En_19(1) <= \<const0>\;
Dbg_Reg_En_19(2) <= \<const0>\;
Dbg_Reg_En_19(3) <= \<const0>\;
Dbg_Reg_En_19(4) <= \<const0>\;
Dbg_Reg_En_19(5) <= \<const0>\;
Dbg_Reg_En_19(6) <= \<const0>\;
Dbg_Reg_En_19(7) <= \<const0>\;
Dbg_Reg_En_2(0) <= \<const0>\;
Dbg_Reg_En_2(1) <= \<const0>\;
Dbg_Reg_En_2(2) <= \<const0>\;
Dbg_Reg_En_2(3) <= \<const0>\;
Dbg_Reg_En_2(4) <= \<const0>\;
Dbg_Reg_En_2(5) <= \<const0>\;
Dbg_Reg_En_2(6) <= \<const0>\;
Dbg_Reg_En_2(7) <= \<const0>\;
Dbg_Reg_En_20(0) <= \<const0>\;
Dbg_Reg_En_20(1) <= \<const0>\;
Dbg_Reg_En_20(2) <= \<const0>\;
Dbg_Reg_En_20(3) <= \<const0>\;
Dbg_Reg_En_20(4) <= \<const0>\;
Dbg_Reg_En_20(5) <= \<const0>\;
Dbg_Reg_En_20(6) <= \<const0>\;
Dbg_Reg_En_20(7) <= \<const0>\;
Dbg_Reg_En_21(0) <= \<const0>\;
Dbg_Reg_En_21(1) <= \<const0>\;
Dbg_Reg_En_21(2) <= \<const0>\;
Dbg_Reg_En_21(3) <= \<const0>\;
Dbg_Reg_En_21(4) <= \<const0>\;
Dbg_Reg_En_21(5) <= \<const0>\;
Dbg_Reg_En_21(6) <= \<const0>\;
Dbg_Reg_En_21(7) <= \<const0>\;
Dbg_Reg_En_22(0) <= \<const0>\;
Dbg_Reg_En_22(1) <= \<const0>\;
Dbg_Reg_En_22(2) <= \<const0>\;
Dbg_Reg_En_22(3) <= \<const0>\;
Dbg_Reg_En_22(4) <= \<const0>\;
Dbg_Reg_En_22(5) <= \<const0>\;
Dbg_Reg_En_22(6) <= \<const0>\;
Dbg_Reg_En_22(7) <= \<const0>\;
Dbg_Reg_En_23(0) <= \<const0>\;
Dbg_Reg_En_23(1) <= \<const0>\;
Dbg_Reg_En_23(2) <= \<const0>\;
Dbg_Reg_En_23(3) <= \<const0>\;
Dbg_Reg_En_23(4) <= \<const0>\;
Dbg_Reg_En_23(5) <= \<const0>\;
Dbg_Reg_En_23(6) <= \<const0>\;
Dbg_Reg_En_23(7) <= \<const0>\;
Dbg_Reg_En_24(0) <= \<const0>\;
Dbg_Reg_En_24(1) <= \<const0>\;
Dbg_Reg_En_24(2) <= \<const0>\;
Dbg_Reg_En_24(3) <= \<const0>\;
Dbg_Reg_En_24(4) <= \<const0>\;
Dbg_Reg_En_24(5) <= \<const0>\;
Dbg_Reg_En_24(6) <= \<const0>\;
Dbg_Reg_En_24(7) <= \<const0>\;
Dbg_Reg_En_25(0) <= \<const0>\;
Dbg_Reg_En_25(1) <= \<const0>\;
Dbg_Reg_En_25(2) <= \<const0>\;
Dbg_Reg_En_25(3) <= \<const0>\;
Dbg_Reg_En_25(4) <= \<const0>\;
Dbg_Reg_En_25(5) <= \<const0>\;
Dbg_Reg_En_25(6) <= \<const0>\;
Dbg_Reg_En_25(7) <= \<const0>\;
Dbg_Reg_En_26(0) <= \<const0>\;
Dbg_Reg_En_26(1) <= \<const0>\;
Dbg_Reg_En_26(2) <= \<const0>\;
Dbg_Reg_En_26(3) <= \<const0>\;
Dbg_Reg_En_26(4) <= \<const0>\;
Dbg_Reg_En_26(5) <= \<const0>\;
Dbg_Reg_En_26(6) <= \<const0>\;
Dbg_Reg_En_26(7) <= \<const0>\;
Dbg_Reg_En_27(0) <= \<const0>\;
Dbg_Reg_En_27(1) <= \<const0>\;
Dbg_Reg_En_27(2) <= \<const0>\;
Dbg_Reg_En_27(3) <= \<const0>\;
Dbg_Reg_En_27(4) <= \<const0>\;
Dbg_Reg_En_27(5) <= \<const0>\;
Dbg_Reg_En_27(6) <= \<const0>\;
Dbg_Reg_En_27(7) <= \<const0>\;
Dbg_Reg_En_28(0) <= \<const0>\;
Dbg_Reg_En_28(1) <= \<const0>\;
Dbg_Reg_En_28(2) <= \<const0>\;
Dbg_Reg_En_28(3) <= \<const0>\;
Dbg_Reg_En_28(4) <= \<const0>\;
Dbg_Reg_En_28(5) <= \<const0>\;
Dbg_Reg_En_28(6) <= \<const0>\;
Dbg_Reg_En_28(7) <= \<const0>\;
Dbg_Reg_En_29(0) <= \<const0>\;
Dbg_Reg_En_29(1) <= \<const0>\;
Dbg_Reg_En_29(2) <= \<const0>\;
Dbg_Reg_En_29(3) <= \<const0>\;
Dbg_Reg_En_29(4) <= \<const0>\;
Dbg_Reg_En_29(5) <= \<const0>\;
Dbg_Reg_En_29(6) <= \<const0>\;
Dbg_Reg_En_29(7) <= \<const0>\;
Dbg_Reg_En_3(0) <= \<const0>\;
Dbg_Reg_En_3(1) <= \<const0>\;
Dbg_Reg_En_3(2) <= \<const0>\;
Dbg_Reg_En_3(3) <= \<const0>\;
Dbg_Reg_En_3(4) <= \<const0>\;
Dbg_Reg_En_3(5) <= \<const0>\;
Dbg_Reg_En_3(6) <= \<const0>\;
Dbg_Reg_En_3(7) <= \<const0>\;
Dbg_Reg_En_30(0) <= \<const0>\;
Dbg_Reg_En_30(1) <= \<const0>\;
Dbg_Reg_En_30(2) <= \<const0>\;
Dbg_Reg_En_30(3) <= \<const0>\;
Dbg_Reg_En_30(4) <= \<const0>\;
Dbg_Reg_En_30(5) <= \<const0>\;
Dbg_Reg_En_30(6) <= \<const0>\;
Dbg_Reg_En_30(7) <= \<const0>\;
Dbg_Reg_En_31(0) <= \<const0>\;
Dbg_Reg_En_31(1) <= \<const0>\;
Dbg_Reg_En_31(2) <= \<const0>\;
Dbg_Reg_En_31(3) <= \<const0>\;
Dbg_Reg_En_31(4) <= \<const0>\;
Dbg_Reg_En_31(5) <= \<const0>\;
Dbg_Reg_En_31(6) <= \<const0>\;
Dbg_Reg_En_31(7) <= \<const0>\;
Dbg_Reg_En_4(0) <= \<const0>\;
Dbg_Reg_En_4(1) <= \<const0>\;
Dbg_Reg_En_4(2) <= \<const0>\;
Dbg_Reg_En_4(3) <= \<const0>\;
Dbg_Reg_En_4(4) <= \<const0>\;
Dbg_Reg_En_4(5) <= \<const0>\;
Dbg_Reg_En_4(6) <= \<const0>\;
Dbg_Reg_En_4(7) <= \<const0>\;
Dbg_Reg_En_5(0) <= \<const0>\;
Dbg_Reg_En_5(1) <= \<const0>\;
Dbg_Reg_En_5(2) <= \<const0>\;
Dbg_Reg_En_5(3) <= \<const0>\;
Dbg_Reg_En_5(4) <= \<const0>\;
Dbg_Reg_En_5(5) <= \<const0>\;
Dbg_Reg_En_5(6) <= \<const0>\;
Dbg_Reg_En_5(7) <= \<const0>\;
Dbg_Reg_En_6(0) <= \<const0>\;
Dbg_Reg_En_6(1) <= \<const0>\;
Dbg_Reg_En_6(2) <= \<const0>\;
Dbg_Reg_En_6(3) <= \<const0>\;
Dbg_Reg_En_6(4) <= \<const0>\;
Dbg_Reg_En_6(5) <= \<const0>\;
Dbg_Reg_En_6(6) <= \<const0>\;
Dbg_Reg_En_6(7) <= \<const0>\;
Dbg_Reg_En_7(0) <= \<const0>\;
Dbg_Reg_En_7(1) <= \<const0>\;
Dbg_Reg_En_7(2) <= \<const0>\;
Dbg_Reg_En_7(3) <= \<const0>\;
Dbg_Reg_En_7(4) <= \<const0>\;
Dbg_Reg_En_7(5) <= \<const0>\;
Dbg_Reg_En_7(6) <= \<const0>\;
Dbg_Reg_En_7(7) <= \<const0>\;
Dbg_Reg_En_8(0) <= \<const0>\;
Dbg_Reg_En_8(1) <= \<const0>\;
Dbg_Reg_En_8(2) <= \<const0>\;
Dbg_Reg_En_8(3) <= \<const0>\;
Dbg_Reg_En_8(4) <= \<const0>\;
Dbg_Reg_En_8(5) <= \<const0>\;
Dbg_Reg_En_8(6) <= \<const0>\;
Dbg_Reg_En_8(7) <= \<const0>\;
Dbg_Reg_En_9(0) <= \<const0>\;
Dbg_Reg_En_9(1) <= \<const0>\;
Dbg_Reg_En_9(2) <= \<const0>\;
Dbg_Reg_En_9(3) <= \<const0>\;
Dbg_Reg_En_9(4) <= \<const0>\;
Dbg_Reg_En_9(5) <= \<const0>\;
Dbg_Reg_En_9(6) <= \<const0>\;
Dbg_Reg_En_9(7) <= \<const0>\;
Dbg_Rst_1 <= \<const0>\;
Dbg_Rst_10 <= \<const0>\;
Dbg_Rst_11 <= \<const0>\;
Dbg_Rst_12 <= \<const0>\;
Dbg_Rst_13 <= \<const0>\;
Dbg_Rst_14 <= \<const0>\;
Dbg_Rst_15 <= \<const0>\;
Dbg_Rst_16 <= \<const0>\;
Dbg_Rst_17 <= \<const0>\;
Dbg_Rst_18 <= \<const0>\;
Dbg_Rst_19 <= \<const0>\;
Dbg_Rst_2 <= \<const0>\;
Dbg_Rst_20 <= \<const0>\;
Dbg_Rst_21 <= \<const0>\;
Dbg_Rst_22 <= \<const0>\;
Dbg_Rst_23 <= \<const0>\;
Dbg_Rst_24 <= \<const0>\;
Dbg_Rst_25 <= \<const0>\;
Dbg_Rst_26 <= \<const0>\;
Dbg_Rst_27 <= \<const0>\;
Dbg_Rst_28 <= \<const0>\;
Dbg_Rst_29 <= \<const0>\;
Dbg_Rst_3 <= \<const0>\;
Dbg_Rst_30 <= \<const0>\;
Dbg_Rst_31 <= \<const0>\;
Dbg_Rst_4 <= \<const0>\;
Dbg_Rst_5 <= \<const0>\;
Dbg_Rst_6 <= \<const0>\;
Dbg_Rst_7 <= \<const0>\;
Dbg_Rst_8 <= \<const0>\;
Dbg_Rst_9 <= \<const0>\;
Dbg_Shift_0 <= \^dbg_shift_0\;
Dbg_Shift_1 <= \^dbg_shift_0\;
Dbg_Shift_10 <= \^dbg_shift_0\;
Dbg_Shift_11 <= \^dbg_shift_0\;
Dbg_Shift_12 <= \^dbg_shift_0\;
Dbg_Shift_13 <= \^dbg_shift_0\;
Dbg_Shift_14 <= \^dbg_shift_0\;
Dbg_Shift_15 <= \^dbg_shift_0\;
Dbg_Shift_16 <= \^dbg_shift_0\;
Dbg_Shift_17 <= \^dbg_shift_0\;
Dbg_Shift_18 <= \^dbg_shift_0\;
Dbg_Shift_19 <= \^dbg_shift_0\;
Dbg_Shift_2 <= \^dbg_shift_0\;
Dbg_Shift_20 <= \^dbg_shift_0\;
Dbg_Shift_21 <= \^dbg_shift_0\;
Dbg_Shift_22 <= \^dbg_shift_0\;
Dbg_Shift_23 <= \^dbg_shift_0\;
Dbg_Shift_24 <= \^dbg_shift_0\;
Dbg_Shift_25 <= \^dbg_shift_0\;
Dbg_Shift_26 <= \^dbg_shift_0\;
Dbg_Shift_27 <= \^dbg_shift_0\;
Dbg_Shift_28 <= \^dbg_shift_0\;
Dbg_Shift_29 <= \^dbg_shift_0\;
Dbg_Shift_3 <= \^dbg_shift_0\;
Dbg_Shift_30 <= \^dbg_shift_0\;
Dbg_Shift_31 <= \^dbg_shift_0\;
Dbg_Shift_4 <= \^dbg_shift_0\;
Dbg_Shift_5 <= \^dbg_shift_0\;
Dbg_Shift_6 <= \^dbg_shift_0\;
Dbg_Shift_7 <= \^dbg_shift_0\;
Dbg_Shift_8 <= \^dbg_shift_0\;
Dbg_Shift_9 <= \^dbg_shift_0\;
Dbg_TDI_0 <= \^ext_jtag_tdi\;
Dbg_TDI_1 <= \^ext_jtag_tdi\;
Dbg_TDI_10 <= \^ext_jtag_tdi\;
Dbg_TDI_11 <= \^ext_jtag_tdi\;
Dbg_TDI_12 <= \^ext_jtag_tdi\;
Dbg_TDI_13 <= \^ext_jtag_tdi\;
Dbg_TDI_14 <= \^ext_jtag_tdi\;
Dbg_TDI_15 <= \^ext_jtag_tdi\;
Dbg_TDI_16 <= \^ext_jtag_tdi\;
Dbg_TDI_17 <= \^ext_jtag_tdi\;
Dbg_TDI_18 <= \^ext_jtag_tdi\;
Dbg_TDI_19 <= \^ext_jtag_tdi\;
Dbg_TDI_2 <= \^ext_jtag_tdi\;
Dbg_TDI_20 <= \^ext_jtag_tdi\;
Dbg_TDI_21 <= \^ext_jtag_tdi\;
Dbg_TDI_22 <= \^ext_jtag_tdi\;
Dbg_TDI_23 <= \^ext_jtag_tdi\;
Dbg_TDI_24 <= \^ext_jtag_tdi\;
Dbg_TDI_25 <= \^ext_jtag_tdi\;
Dbg_TDI_26 <= \^ext_jtag_tdi\;
Dbg_TDI_27 <= \^ext_jtag_tdi\;
Dbg_TDI_28 <= \^ext_jtag_tdi\;
Dbg_TDI_29 <= \^ext_jtag_tdi\;
Dbg_TDI_3 <= \^ext_jtag_tdi\;
Dbg_TDI_30 <= \^ext_jtag_tdi\;
Dbg_TDI_31 <= \^ext_jtag_tdi\;
Dbg_TDI_4 <= \^ext_jtag_tdi\;
Dbg_TDI_5 <= \^ext_jtag_tdi\;
Dbg_TDI_6 <= \^ext_jtag_tdi\;
Dbg_TDI_7 <= \^ext_jtag_tdi\;
Dbg_TDI_8 <= \^ext_jtag_tdi\;
Dbg_TDI_9 <= \^ext_jtag_tdi\;
Dbg_TrClk_0 <= \<const0>\;
Dbg_TrClk_1 <= \<const0>\;
Dbg_TrClk_10 <= \<const0>\;
Dbg_TrClk_11 <= \<const0>\;
Dbg_TrClk_12 <= \<const0>\;
Dbg_TrClk_13 <= \<const0>\;
Dbg_TrClk_14 <= \<const0>\;
Dbg_TrClk_15 <= \<const0>\;
Dbg_TrClk_16 <= \<const0>\;
Dbg_TrClk_17 <= \<const0>\;
Dbg_TrClk_18 <= \<const0>\;
Dbg_TrClk_19 <= \<const0>\;
Dbg_TrClk_2 <= \<const0>\;
Dbg_TrClk_20 <= \<const0>\;
Dbg_TrClk_21 <= \<const0>\;
Dbg_TrClk_22 <= \<const0>\;
Dbg_TrClk_23 <= \<const0>\;
Dbg_TrClk_24 <= \<const0>\;
Dbg_TrClk_25 <= \<const0>\;
Dbg_TrClk_26 <= \<const0>\;
Dbg_TrClk_27 <= \<const0>\;
Dbg_TrClk_28 <= \<const0>\;
Dbg_TrClk_29 <= \<const0>\;
Dbg_TrClk_3 <= \<const0>\;
Dbg_TrClk_30 <= \<const0>\;
Dbg_TrClk_31 <= \<const0>\;
Dbg_TrClk_4 <= \<const0>\;
Dbg_TrClk_5 <= \<const0>\;
Dbg_TrClk_6 <= \<const0>\;
Dbg_TrClk_7 <= \<const0>\;
Dbg_TrClk_8 <= \<const0>\;
Dbg_TrClk_9 <= \<const0>\;
Dbg_TrReady_0 <= \<const0>\;
Dbg_TrReady_1 <= \<const0>\;
Dbg_TrReady_10 <= \<const0>\;
Dbg_TrReady_11 <= \<const0>\;
Dbg_TrReady_12 <= \<const0>\;
Dbg_TrReady_13 <= \<const0>\;
Dbg_TrReady_14 <= \<const0>\;
Dbg_TrReady_15 <= \<const0>\;
Dbg_TrReady_16 <= \<const0>\;
Dbg_TrReady_17 <= \<const0>\;
Dbg_TrReady_18 <= \<const0>\;
Dbg_TrReady_19 <= \<const0>\;
Dbg_TrReady_2 <= \<const0>\;
Dbg_TrReady_20 <= \<const0>\;
Dbg_TrReady_21 <= \<const0>\;
Dbg_TrReady_22 <= \<const0>\;
Dbg_TrReady_23 <= \<const0>\;
Dbg_TrReady_24 <= \<const0>\;
Dbg_TrReady_25 <= \<const0>\;
Dbg_TrReady_26 <= \<const0>\;
Dbg_TrReady_27 <= \<const0>\;
Dbg_TrReady_28 <= \<const0>\;
Dbg_TrReady_29 <= \<const0>\;
Dbg_TrReady_3 <= \<const0>\;
Dbg_TrReady_30 <= \<const0>\;
Dbg_TrReady_31 <= \<const0>\;
Dbg_TrReady_4 <= \<const0>\;
Dbg_TrReady_5 <= \<const0>\;
Dbg_TrReady_6 <= \<const0>\;
Dbg_TrReady_7 <= \<const0>\;
Dbg_TrReady_8 <= \<const0>\;
Dbg_TrReady_9 <= \<const0>\;
Dbg_Trig_Ack_In_0(0) <= \<const0>\;
Dbg_Trig_Ack_In_0(1) <= \<const0>\;
Dbg_Trig_Ack_In_0(2) <= \<const0>\;
Dbg_Trig_Ack_In_0(3) <= \<const0>\;
Dbg_Trig_Ack_In_0(4) <= \<const0>\;
Dbg_Trig_Ack_In_0(5) <= \<const0>\;
Dbg_Trig_Ack_In_0(6) <= \<const0>\;
Dbg_Trig_Ack_In_0(7) <= \<const0>\;
Dbg_Trig_Ack_In_1(0) <= \<const0>\;
Dbg_Trig_Ack_In_1(1) <= \<const0>\;
Dbg_Trig_Ack_In_1(2) <= \<const0>\;
Dbg_Trig_Ack_In_1(3) <= \<const0>\;
Dbg_Trig_Ack_In_1(4) <= \<const0>\;
Dbg_Trig_Ack_In_1(5) <= \<const0>\;
Dbg_Trig_Ack_In_1(6) <= \<const0>\;
Dbg_Trig_Ack_In_1(7) <= \<const0>\;
Dbg_Trig_Ack_In_10(0) <= \<const0>\;
Dbg_Trig_Ack_In_10(1) <= \<const0>\;
Dbg_Trig_Ack_In_10(2) <= \<const0>\;
Dbg_Trig_Ack_In_10(3) <= \<const0>\;
Dbg_Trig_Ack_In_10(4) <= \<const0>\;
Dbg_Trig_Ack_In_10(5) <= \<const0>\;
Dbg_Trig_Ack_In_10(6) <= \<const0>\;
Dbg_Trig_Ack_In_10(7) <= \<const0>\;
Dbg_Trig_Ack_In_11(0) <= \<const0>\;
Dbg_Trig_Ack_In_11(1) <= \<const0>\;
Dbg_Trig_Ack_In_11(2) <= \<const0>\;
Dbg_Trig_Ack_In_11(3) <= \<const0>\;
Dbg_Trig_Ack_In_11(4) <= \<const0>\;
Dbg_Trig_Ack_In_11(5) <= \<const0>\;
Dbg_Trig_Ack_In_11(6) <= \<const0>\;
Dbg_Trig_Ack_In_11(7) <= \<const0>\;
Dbg_Trig_Ack_In_12(0) <= \<const0>\;
Dbg_Trig_Ack_In_12(1) <= \<const0>\;
Dbg_Trig_Ack_In_12(2) <= \<const0>\;
Dbg_Trig_Ack_In_12(3) <= \<const0>\;
Dbg_Trig_Ack_In_12(4) <= \<const0>\;
Dbg_Trig_Ack_In_12(5) <= \<const0>\;
Dbg_Trig_Ack_In_12(6) <= \<const0>\;
Dbg_Trig_Ack_In_12(7) <= \<const0>\;
Dbg_Trig_Ack_In_13(0) <= \<const0>\;
Dbg_Trig_Ack_In_13(1) <= \<const0>\;
Dbg_Trig_Ack_In_13(2) <= \<const0>\;
Dbg_Trig_Ack_In_13(3) <= \<const0>\;
Dbg_Trig_Ack_In_13(4) <= \<const0>\;
Dbg_Trig_Ack_In_13(5) <= \<const0>\;
Dbg_Trig_Ack_In_13(6) <= \<const0>\;
Dbg_Trig_Ack_In_13(7) <= \<const0>\;
Dbg_Trig_Ack_In_14(0) <= \<const0>\;
Dbg_Trig_Ack_In_14(1) <= \<const0>\;
Dbg_Trig_Ack_In_14(2) <= \<const0>\;
Dbg_Trig_Ack_In_14(3) <= \<const0>\;
Dbg_Trig_Ack_In_14(4) <= \<const0>\;
Dbg_Trig_Ack_In_14(5) <= \<const0>\;
Dbg_Trig_Ack_In_14(6) <= \<const0>\;
Dbg_Trig_Ack_In_14(7) <= \<const0>\;
Dbg_Trig_Ack_In_15(0) <= \<const0>\;
Dbg_Trig_Ack_In_15(1) <= \<const0>\;
Dbg_Trig_Ack_In_15(2) <= \<const0>\;
Dbg_Trig_Ack_In_15(3) <= \<const0>\;
Dbg_Trig_Ack_In_15(4) <= \<const0>\;
Dbg_Trig_Ack_In_15(5) <= \<const0>\;
Dbg_Trig_Ack_In_15(6) <= \<const0>\;
Dbg_Trig_Ack_In_15(7) <= \<const0>\;
Dbg_Trig_Ack_In_16(0) <= \<const0>\;
Dbg_Trig_Ack_In_16(1) <= \<const0>\;
Dbg_Trig_Ack_In_16(2) <= \<const0>\;
Dbg_Trig_Ack_In_16(3) <= \<const0>\;
Dbg_Trig_Ack_In_16(4) <= \<const0>\;
Dbg_Trig_Ack_In_16(5) <= \<const0>\;
Dbg_Trig_Ack_In_16(6) <= \<const0>\;
Dbg_Trig_Ack_In_16(7) <= \<const0>\;
Dbg_Trig_Ack_In_17(0) <= \<const0>\;
Dbg_Trig_Ack_In_17(1) <= \<const0>\;
Dbg_Trig_Ack_In_17(2) <= \<const0>\;
Dbg_Trig_Ack_In_17(3) <= \<const0>\;
Dbg_Trig_Ack_In_17(4) <= \<const0>\;
Dbg_Trig_Ack_In_17(5) <= \<const0>\;
Dbg_Trig_Ack_In_17(6) <= \<const0>\;
Dbg_Trig_Ack_In_17(7) <= \<const0>\;
Dbg_Trig_Ack_In_18(0) <= \<const0>\;
Dbg_Trig_Ack_In_18(1) <= \<const0>\;
Dbg_Trig_Ack_In_18(2) <= \<const0>\;
Dbg_Trig_Ack_In_18(3) <= \<const0>\;
Dbg_Trig_Ack_In_18(4) <= \<const0>\;
Dbg_Trig_Ack_In_18(5) <= \<const0>\;
Dbg_Trig_Ack_In_18(6) <= \<const0>\;
Dbg_Trig_Ack_In_18(7) <= \<const0>\;
Dbg_Trig_Ack_In_19(0) <= \<const0>\;
Dbg_Trig_Ack_In_19(1) <= \<const0>\;
Dbg_Trig_Ack_In_19(2) <= \<const0>\;
Dbg_Trig_Ack_In_19(3) <= \<const0>\;
Dbg_Trig_Ack_In_19(4) <= \<const0>\;
Dbg_Trig_Ack_In_19(5) <= \<const0>\;
Dbg_Trig_Ack_In_19(6) <= \<const0>\;
Dbg_Trig_Ack_In_19(7) <= \<const0>\;
Dbg_Trig_Ack_In_2(0) <= \<const0>\;
Dbg_Trig_Ack_In_2(1) <= \<const0>\;
Dbg_Trig_Ack_In_2(2) <= \<const0>\;
Dbg_Trig_Ack_In_2(3) <= \<const0>\;
Dbg_Trig_Ack_In_2(4) <= \<const0>\;
Dbg_Trig_Ack_In_2(5) <= \<const0>\;
Dbg_Trig_Ack_In_2(6) <= \<const0>\;
Dbg_Trig_Ack_In_2(7) <= \<const0>\;
Dbg_Trig_Ack_In_20(0) <= \<const0>\;
Dbg_Trig_Ack_In_20(1) <= \<const0>\;
Dbg_Trig_Ack_In_20(2) <= \<const0>\;
Dbg_Trig_Ack_In_20(3) <= \<const0>\;
Dbg_Trig_Ack_In_20(4) <= \<const0>\;
Dbg_Trig_Ack_In_20(5) <= \<const0>\;
Dbg_Trig_Ack_In_20(6) <= \<const0>\;
Dbg_Trig_Ack_In_20(7) <= \<const0>\;
Dbg_Trig_Ack_In_21(0) <= \<const0>\;
Dbg_Trig_Ack_In_21(1) <= \<const0>\;
Dbg_Trig_Ack_In_21(2) <= \<const0>\;
Dbg_Trig_Ack_In_21(3) <= \<const0>\;
Dbg_Trig_Ack_In_21(4) <= \<const0>\;
Dbg_Trig_Ack_In_21(5) <= \<const0>\;
Dbg_Trig_Ack_In_21(6) <= \<const0>\;
Dbg_Trig_Ack_In_21(7) <= \<const0>\;
Dbg_Trig_Ack_In_22(0) <= \<const0>\;
Dbg_Trig_Ack_In_22(1) <= \<const0>\;
Dbg_Trig_Ack_In_22(2) <= \<const0>\;
Dbg_Trig_Ack_In_22(3) <= \<const0>\;
Dbg_Trig_Ack_In_22(4) <= \<const0>\;
Dbg_Trig_Ack_In_22(5) <= \<const0>\;
Dbg_Trig_Ack_In_22(6) <= \<const0>\;
Dbg_Trig_Ack_In_22(7) <= \<const0>\;
Dbg_Trig_Ack_In_23(0) <= \<const0>\;
Dbg_Trig_Ack_In_23(1) <= \<const0>\;
Dbg_Trig_Ack_In_23(2) <= \<const0>\;
Dbg_Trig_Ack_In_23(3) <= \<const0>\;
Dbg_Trig_Ack_In_23(4) <= \<const0>\;
Dbg_Trig_Ack_In_23(5) <= \<const0>\;
Dbg_Trig_Ack_In_23(6) <= \<const0>\;
Dbg_Trig_Ack_In_23(7) <= \<const0>\;
Dbg_Trig_Ack_In_24(0) <= \<const0>\;
Dbg_Trig_Ack_In_24(1) <= \<const0>\;
Dbg_Trig_Ack_In_24(2) <= \<const0>\;
Dbg_Trig_Ack_In_24(3) <= \<const0>\;
Dbg_Trig_Ack_In_24(4) <= \<const0>\;
Dbg_Trig_Ack_In_24(5) <= \<const0>\;
Dbg_Trig_Ack_In_24(6) <= \<const0>\;
Dbg_Trig_Ack_In_24(7) <= \<const0>\;
Dbg_Trig_Ack_In_25(0) <= \<const0>\;
Dbg_Trig_Ack_In_25(1) <= \<const0>\;
Dbg_Trig_Ack_In_25(2) <= \<const0>\;
Dbg_Trig_Ack_In_25(3) <= \<const0>\;
Dbg_Trig_Ack_In_25(4) <= \<const0>\;
Dbg_Trig_Ack_In_25(5) <= \<const0>\;
Dbg_Trig_Ack_In_25(6) <= \<const0>\;
Dbg_Trig_Ack_In_25(7) <= \<const0>\;
Dbg_Trig_Ack_In_26(0) <= \<const0>\;
Dbg_Trig_Ack_In_26(1) <= \<const0>\;
Dbg_Trig_Ack_In_26(2) <= \<const0>\;
Dbg_Trig_Ack_In_26(3) <= \<const0>\;
Dbg_Trig_Ack_In_26(4) <= \<const0>\;
Dbg_Trig_Ack_In_26(5) <= \<const0>\;
Dbg_Trig_Ack_In_26(6) <= \<const0>\;
Dbg_Trig_Ack_In_26(7) <= \<const0>\;
Dbg_Trig_Ack_In_27(0) <= \<const0>\;
Dbg_Trig_Ack_In_27(1) <= \<const0>\;
Dbg_Trig_Ack_In_27(2) <= \<const0>\;
Dbg_Trig_Ack_In_27(3) <= \<const0>\;
Dbg_Trig_Ack_In_27(4) <= \<const0>\;
Dbg_Trig_Ack_In_27(5) <= \<const0>\;
Dbg_Trig_Ack_In_27(6) <= \<const0>\;
Dbg_Trig_Ack_In_27(7) <= \<const0>\;
Dbg_Trig_Ack_In_28(0) <= \<const0>\;
Dbg_Trig_Ack_In_28(1) <= \<const0>\;
Dbg_Trig_Ack_In_28(2) <= \<const0>\;
Dbg_Trig_Ack_In_28(3) <= \<const0>\;
Dbg_Trig_Ack_In_28(4) <= \<const0>\;
Dbg_Trig_Ack_In_28(5) <= \<const0>\;
Dbg_Trig_Ack_In_28(6) <= \<const0>\;
Dbg_Trig_Ack_In_28(7) <= \<const0>\;
Dbg_Trig_Ack_In_29(0) <= \<const0>\;
Dbg_Trig_Ack_In_29(1) <= \<const0>\;
Dbg_Trig_Ack_In_29(2) <= \<const0>\;
Dbg_Trig_Ack_In_29(3) <= \<const0>\;
Dbg_Trig_Ack_In_29(4) <= \<const0>\;
Dbg_Trig_Ack_In_29(5) <= \<const0>\;
Dbg_Trig_Ack_In_29(6) <= \<const0>\;
Dbg_Trig_Ack_In_29(7) <= \<const0>\;
Dbg_Trig_Ack_In_3(0) <= \<const0>\;
Dbg_Trig_Ack_In_3(1) <= \<const0>\;
Dbg_Trig_Ack_In_3(2) <= \<const0>\;
Dbg_Trig_Ack_In_3(3) <= \<const0>\;
Dbg_Trig_Ack_In_3(4) <= \<const0>\;
Dbg_Trig_Ack_In_3(5) <= \<const0>\;
Dbg_Trig_Ack_In_3(6) <= \<const0>\;
Dbg_Trig_Ack_In_3(7) <= \<const0>\;
Dbg_Trig_Ack_In_30(0) <= \<const0>\;
Dbg_Trig_Ack_In_30(1) <= \<const0>\;
Dbg_Trig_Ack_In_30(2) <= \<const0>\;
Dbg_Trig_Ack_In_30(3) <= \<const0>\;
Dbg_Trig_Ack_In_30(4) <= \<const0>\;
Dbg_Trig_Ack_In_30(5) <= \<const0>\;
Dbg_Trig_Ack_In_30(6) <= \<const0>\;
Dbg_Trig_Ack_In_30(7) <= \<const0>\;
Dbg_Trig_Ack_In_31(0) <= \<const0>\;
Dbg_Trig_Ack_In_31(1) <= \<const0>\;
Dbg_Trig_Ack_In_31(2) <= \<const0>\;
Dbg_Trig_Ack_In_31(3) <= \<const0>\;
Dbg_Trig_Ack_In_31(4) <= \<const0>\;
Dbg_Trig_Ack_In_31(5) <= \<const0>\;
Dbg_Trig_Ack_In_31(6) <= \<const0>\;
Dbg_Trig_Ack_In_31(7) <= \<const0>\;
Dbg_Trig_Ack_In_4(0) <= \<const0>\;
Dbg_Trig_Ack_In_4(1) <= \<const0>\;
Dbg_Trig_Ack_In_4(2) <= \<const0>\;
Dbg_Trig_Ack_In_4(3) <= \<const0>\;
Dbg_Trig_Ack_In_4(4) <= \<const0>\;
Dbg_Trig_Ack_In_4(5) <= \<const0>\;
Dbg_Trig_Ack_In_4(6) <= \<const0>\;
Dbg_Trig_Ack_In_4(7) <= \<const0>\;
Dbg_Trig_Ack_In_5(0) <= \<const0>\;
Dbg_Trig_Ack_In_5(1) <= \<const0>\;
Dbg_Trig_Ack_In_5(2) <= \<const0>\;
Dbg_Trig_Ack_In_5(3) <= \<const0>\;
Dbg_Trig_Ack_In_5(4) <= \<const0>\;
Dbg_Trig_Ack_In_5(5) <= \<const0>\;
Dbg_Trig_Ack_In_5(6) <= \<const0>\;
Dbg_Trig_Ack_In_5(7) <= \<const0>\;
Dbg_Trig_Ack_In_6(0) <= \<const0>\;
Dbg_Trig_Ack_In_6(1) <= \<const0>\;
Dbg_Trig_Ack_In_6(2) <= \<const0>\;
Dbg_Trig_Ack_In_6(3) <= \<const0>\;
Dbg_Trig_Ack_In_6(4) <= \<const0>\;
Dbg_Trig_Ack_In_6(5) <= \<const0>\;
Dbg_Trig_Ack_In_6(6) <= \<const0>\;
Dbg_Trig_Ack_In_6(7) <= \<const0>\;
Dbg_Trig_Ack_In_7(0) <= \<const0>\;
Dbg_Trig_Ack_In_7(1) <= \<const0>\;
Dbg_Trig_Ack_In_7(2) <= \<const0>\;
Dbg_Trig_Ack_In_7(3) <= \<const0>\;
Dbg_Trig_Ack_In_7(4) <= \<const0>\;
Dbg_Trig_Ack_In_7(5) <= \<const0>\;
Dbg_Trig_Ack_In_7(6) <= \<const0>\;
Dbg_Trig_Ack_In_7(7) <= \<const0>\;
Dbg_Trig_Ack_In_8(0) <= \<const0>\;
Dbg_Trig_Ack_In_8(1) <= \<const0>\;
Dbg_Trig_Ack_In_8(2) <= \<const0>\;
Dbg_Trig_Ack_In_8(3) <= \<const0>\;
Dbg_Trig_Ack_In_8(4) <= \<const0>\;
Dbg_Trig_Ack_In_8(5) <= \<const0>\;
Dbg_Trig_Ack_In_8(6) <= \<const0>\;
Dbg_Trig_Ack_In_8(7) <= \<const0>\;
Dbg_Trig_Ack_In_9(0) <= \<const0>\;
Dbg_Trig_Ack_In_9(1) <= \<const0>\;
Dbg_Trig_Ack_In_9(2) <= \<const0>\;
Dbg_Trig_Ack_In_9(3) <= \<const0>\;
Dbg_Trig_Ack_In_9(4) <= \<const0>\;
Dbg_Trig_Ack_In_9(5) <= \<const0>\;
Dbg_Trig_Ack_In_9(6) <= \<const0>\;
Dbg_Trig_Ack_In_9(7) <= \<const0>\;
Dbg_Trig_Out_0(0) <= \<const0>\;
Dbg_Trig_Out_0(1) <= \<const0>\;
Dbg_Trig_Out_0(2) <= \<const0>\;
Dbg_Trig_Out_0(3) <= \<const0>\;
Dbg_Trig_Out_0(4) <= \<const0>\;
Dbg_Trig_Out_0(5) <= \<const0>\;
Dbg_Trig_Out_0(6) <= \<const0>\;
Dbg_Trig_Out_0(7) <= \<const0>\;
Dbg_Trig_Out_1(0) <= \<const0>\;
Dbg_Trig_Out_1(1) <= \<const0>\;
Dbg_Trig_Out_1(2) <= \<const0>\;
Dbg_Trig_Out_1(3) <= \<const0>\;
Dbg_Trig_Out_1(4) <= \<const0>\;
Dbg_Trig_Out_1(5) <= \<const0>\;
Dbg_Trig_Out_1(6) <= \<const0>\;
Dbg_Trig_Out_1(7) <= \<const0>\;
Dbg_Trig_Out_10(0) <= \<const0>\;
Dbg_Trig_Out_10(1) <= \<const0>\;
Dbg_Trig_Out_10(2) <= \<const0>\;
Dbg_Trig_Out_10(3) <= \<const0>\;
Dbg_Trig_Out_10(4) <= \<const0>\;
Dbg_Trig_Out_10(5) <= \<const0>\;
Dbg_Trig_Out_10(6) <= \<const0>\;
Dbg_Trig_Out_10(7) <= \<const0>\;
Dbg_Trig_Out_11(0) <= \<const0>\;
Dbg_Trig_Out_11(1) <= \<const0>\;
Dbg_Trig_Out_11(2) <= \<const0>\;
Dbg_Trig_Out_11(3) <= \<const0>\;
Dbg_Trig_Out_11(4) <= \<const0>\;
Dbg_Trig_Out_11(5) <= \<const0>\;
Dbg_Trig_Out_11(6) <= \<const0>\;
Dbg_Trig_Out_11(7) <= \<const0>\;
Dbg_Trig_Out_12(0) <= \<const0>\;
Dbg_Trig_Out_12(1) <= \<const0>\;
Dbg_Trig_Out_12(2) <= \<const0>\;
Dbg_Trig_Out_12(3) <= \<const0>\;
Dbg_Trig_Out_12(4) <= \<const0>\;
Dbg_Trig_Out_12(5) <= \<const0>\;
Dbg_Trig_Out_12(6) <= \<const0>\;
Dbg_Trig_Out_12(7) <= \<const0>\;
Dbg_Trig_Out_13(0) <= \<const0>\;
Dbg_Trig_Out_13(1) <= \<const0>\;
Dbg_Trig_Out_13(2) <= \<const0>\;
Dbg_Trig_Out_13(3) <= \<const0>\;
Dbg_Trig_Out_13(4) <= \<const0>\;
Dbg_Trig_Out_13(5) <= \<const0>\;
Dbg_Trig_Out_13(6) <= \<const0>\;
Dbg_Trig_Out_13(7) <= \<const0>\;
Dbg_Trig_Out_14(0) <= \<const0>\;
Dbg_Trig_Out_14(1) <= \<const0>\;
Dbg_Trig_Out_14(2) <= \<const0>\;
Dbg_Trig_Out_14(3) <= \<const0>\;
Dbg_Trig_Out_14(4) <= \<const0>\;
Dbg_Trig_Out_14(5) <= \<const0>\;
Dbg_Trig_Out_14(6) <= \<const0>\;
Dbg_Trig_Out_14(7) <= \<const0>\;
Dbg_Trig_Out_15(0) <= \<const0>\;
Dbg_Trig_Out_15(1) <= \<const0>\;
Dbg_Trig_Out_15(2) <= \<const0>\;
Dbg_Trig_Out_15(3) <= \<const0>\;
Dbg_Trig_Out_15(4) <= \<const0>\;
Dbg_Trig_Out_15(5) <= \<const0>\;
Dbg_Trig_Out_15(6) <= \<const0>\;
Dbg_Trig_Out_15(7) <= \<const0>\;
Dbg_Trig_Out_16(0) <= \<const0>\;
Dbg_Trig_Out_16(1) <= \<const0>\;
Dbg_Trig_Out_16(2) <= \<const0>\;
Dbg_Trig_Out_16(3) <= \<const0>\;
Dbg_Trig_Out_16(4) <= \<const0>\;
Dbg_Trig_Out_16(5) <= \<const0>\;
Dbg_Trig_Out_16(6) <= \<const0>\;
Dbg_Trig_Out_16(7) <= \<const0>\;
Dbg_Trig_Out_17(0) <= \<const0>\;
Dbg_Trig_Out_17(1) <= \<const0>\;
Dbg_Trig_Out_17(2) <= \<const0>\;
Dbg_Trig_Out_17(3) <= \<const0>\;
Dbg_Trig_Out_17(4) <= \<const0>\;
Dbg_Trig_Out_17(5) <= \<const0>\;
Dbg_Trig_Out_17(6) <= \<const0>\;
Dbg_Trig_Out_17(7) <= \<const0>\;
Dbg_Trig_Out_18(0) <= \<const0>\;
Dbg_Trig_Out_18(1) <= \<const0>\;
Dbg_Trig_Out_18(2) <= \<const0>\;
Dbg_Trig_Out_18(3) <= \<const0>\;
Dbg_Trig_Out_18(4) <= \<const0>\;
Dbg_Trig_Out_18(5) <= \<const0>\;
Dbg_Trig_Out_18(6) <= \<const0>\;
Dbg_Trig_Out_18(7) <= \<const0>\;
Dbg_Trig_Out_19(0) <= \<const0>\;
Dbg_Trig_Out_19(1) <= \<const0>\;
Dbg_Trig_Out_19(2) <= \<const0>\;
Dbg_Trig_Out_19(3) <= \<const0>\;
Dbg_Trig_Out_19(4) <= \<const0>\;
Dbg_Trig_Out_19(5) <= \<const0>\;
Dbg_Trig_Out_19(6) <= \<const0>\;
Dbg_Trig_Out_19(7) <= \<const0>\;
Dbg_Trig_Out_2(0) <= \<const0>\;
Dbg_Trig_Out_2(1) <= \<const0>\;
Dbg_Trig_Out_2(2) <= \<const0>\;
Dbg_Trig_Out_2(3) <= \<const0>\;
Dbg_Trig_Out_2(4) <= \<const0>\;
Dbg_Trig_Out_2(5) <= \<const0>\;
Dbg_Trig_Out_2(6) <= \<const0>\;
Dbg_Trig_Out_2(7) <= \<const0>\;
Dbg_Trig_Out_20(0) <= \<const0>\;
Dbg_Trig_Out_20(1) <= \<const0>\;
Dbg_Trig_Out_20(2) <= \<const0>\;
Dbg_Trig_Out_20(3) <= \<const0>\;
Dbg_Trig_Out_20(4) <= \<const0>\;
Dbg_Trig_Out_20(5) <= \<const0>\;
Dbg_Trig_Out_20(6) <= \<const0>\;
Dbg_Trig_Out_20(7) <= \<const0>\;
Dbg_Trig_Out_21(0) <= \<const0>\;
Dbg_Trig_Out_21(1) <= \<const0>\;
Dbg_Trig_Out_21(2) <= \<const0>\;
Dbg_Trig_Out_21(3) <= \<const0>\;
Dbg_Trig_Out_21(4) <= \<const0>\;
Dbg_Trig_Out_21(5) <= \<const0>\;
Dbg_Trig_Out_21(6) <= \<const0>\;
Dbg_Trig_Out_21(7) <= \<const0>\;
Dbg_Trig_Out_22(0) <= \<const0>\;
Dbg_Trig_Out_22(1) <= \<const0>\;
Dbg_Trig_Out_22(2) <= \<const0>\;
Dbg_Trig_Out_22(3) <= \<const0>\;
Dbg_Trig_Out_22(4) <= \<const0>\;
Dbg_Trig_Out_22(5) <= \<const0>\;
Dbg_Trig_Out_22(6) <= \<const0>\;
Dbg_Trig_Out_22(7) <= \<const0>\;
Dbg_Trig_Out_23(0) <= \<const0>\;
Dbg_Trig_Out_23(1) <= \<const0>\;
Dbg_Trig_Out_23(2) <= \<const0>\;
Dbg_Trig_Out_23(3) <= \<const0>\;
Dbg_Trig_Out_23(4) <= \<const0>\;
Dbg_Trig_Out_23(5) <= \<const0>\;
Dbg_Trig_Out_23(6) <= \<const0>\;
Dbg_Trig_Out_23(7) <= \<const0>\;
Dbg_Trig_Out_24(0) <= \<const0>\;
Dbg_Trig_Out_24(1) <= \<const0>\;
Dbg_Trig_Out_24(2) <= \<const0>\;
Dbg_Trig_Out_24(3) <= \<const0>\;
Dbg_Trig_Out_24(4) <= \<const0>\;
Dbg_Trig_Out_24(5) <= \<const0>\;
Dbg_Trig_Out_24(6) <= \<const0>\;
Dbg_Trig_Out_24(7) <= \<const0>\;
Dbg_Trig_Out_25(0) <= \<const0>\;
Dbg_Trig_Out_25(1) <= \<const0>\;
Dbg_Trig_Out_25(2) <= \<const0>\;
Dbg_Trig_Out_25(3) <= \<const0>\;
Dbg_Trig_Out_25(4) <= \<const0>\;
Dbg_Trig_Out_25(5) <= \<const0>\;
Dbg_Trig_Out_25(6) <= \<const0>\;
Dbg_Trig_Out_25(7) <= \<const0>\;
Dbg_Trig_Out_26(0) <= \<const0>\;
Dbg_Trig_Out_26(1) <= \<const0>\;
Dbg_Trig_Out_26(2) <= \<const0>\;
Dbg_Trig_Out_26(3) <= \<const0>\;
Dbg_Trig_Out_26(4) <= \<const0>\;
Dbg_Trig_Out_26(5) <= \<const0>\;
Dbg_Trig_Out_26(6) <= \<const0>\;
Dbg_Trig_Out_26(7) <= \<const0>\;
Dbg_Trig_Out_27(0) <= \<const0>\;
Dbg_Trig_Out_27(1) <= \<const0>\;
Dbg_Trig_Out_27(2) <= \<const0>\;
Dbg_Trig_Out_27(3) <= \<const0>\;
Dbg_Trig_Out_27(4) <= \<const0>\;
Dbg_Trig_Out_27(5) <= \<const0>\;
Dbg_Trig_Out_27(6) <= \<const0>\;
Dbg_Trig_Out_27(7) <= \<const0>\;
Dbg_Trig_Out_28(0) <= \<const0>\;
Dbg_Trig_Out_28(1) <= \<const0>\;
Dbg_Trig_Out_28(2) <= \<const0>\;
Dbg_Trig_Out_28(3) <= \<const0>\;
Dbg_Trig_Out_28(4) <= \<const0>\;
Dbg_Trig_Out_28(5) <= \<const0>\;
Dbg_Trig_Out_28(6) <= \<const0>\;
Dbg_Trig_Out_28(7) <= \<const0>\;
Dbg_Trig_Out_29(0) <= \<const0>\;
Dbg_Trig_Out_29(1) <= \<const0>\;
Dbg_Trig_Out_29(2) <= \<const0>\;
Dbg_Trig_Out_29(3) <= \<const0>\;
Dbg_Trig_Out_29(4) <= \<const0>\;
Dbg_Trig_Out_29(5) <= \<const0>\;
Dbg_Trig_Out_29(6) <= \<const0>\;
Dbg_Trig_Out_29(7) <= \<const0>\;
Dbg_Trig_Out_3(0) <= \<const0>\;
Dbg_Trig_Out_3(1) <= \<const0>\;
Dbg_Trig_Out_3(2) <= \<const0>\;
Dbg_Trig_Out_3(3) <= \<const0>\;
Dbg_Trig_Out_3(4) <= \<const0>\;
Dbg_Trig_Out_3(5) <= \<const0>\;
Dbg_Trig_Out_3(6) <= \<const0>\;
Dbg_Trig_Out_3(7) <= \<const0>\;
Dbg_Trig_Out_30(0) <= \<const0>\;
Dbg_Trig_Out_30(1) <= \<const0>\;
Dbg_Trig_Out_30(2) <= \<const0>\;
Dbg_Trig_Out_30(3) <= \<const0>\;
Dbg_Trig_Out_30(4) <= \<const0>\;
Dbg_Trig_Out_30(5) <= \<const0>\;
Dbg_Trig_Out_30(6) <= \<const0>\;
Dbg_Trig_Out_30(7) <= \<const0>\;
Dbg_Trig_Out_31(0) <= \<const0>\;
Dbg_Trig_Out_31(1) <= \<const0>\;
Dbg_Trig_Out_31(2) <= \<const0>\;
Dbg_Trig_Out_31(3) <= \<const0>\;
Dbg_Trig_Out_31(4) <= \<const0>\;
Dbg_Trig_Out_31(5) <= \<const0>\;
Dbg_Trig_Out_31(6) <= \<const0>\;
Dbg_Trig_Out_31(7) <= \<const0>\;
Dbg_Trig_Out_4(0) <= \<const0>\;
Dbg_Trig_Out_4(1) <= \<const0>\;
Dbg_Trig_Out_4(2) <= \<const0>\;
Dbg_Trig_Out_4(3) <= \<const0>\;
Dbg_Trig_Out_4(4) <= \<const0>\;
Dbg_Trig_Out_4(5) <= \<const0>\;
Dbg_Trig_Out_4(6) <= \<const0>\;
Dbg_Trig_Out_4(7) <= \<const0>\;
Dbg_Trig_Out_5(0) <= \<const0>\;
Dbg_Trig_Out_5(1) <= \<const0>\;
Dbg_Trig_Out_5(2) <= \<const0>\;
Dbg_Trig_Out_5(3) <= \<const0>\;
Dbg_Trig_Out_5(4) <= \<const0>\;
Dbg_Trig_Out_5(5) <= \<const0>\;
Dbg_Trig_Out_5(6) <= \<const0>\;
Dbg_Trig_Out_5(7) <= \<const0>\;
Dbg_Trig_Out_6(0) <= \<const0>\;
Dbg_Trig_Out_6(1) <= \<const0>\;
Dbg_Trig_Out_6(2) <= \<const0>\;
Dbg_Trig_Out_6(3) <= \<const0>\;
Dbg_Trig_Out_6(4) <= \<const0>\;
Dbg_Trig_Out_6(5) <= \<const0>\;
Dbg_Trig_Out_6(6) <= \<const0>\;
Dbg_Trig_Out_6(7) <= \<const0>\;
Dbg_Trig_Out_7(0) <= \<const0>\;
Dbg_Trig_Out_7(1) <= \<const0>\;
Dbg_Trig_Out_7(2) <= \<const0>\;
Dbg_Trig_Out_7(3) <= \<const0>\;
Dbg_Trig_Out_7(4) <= \<const0>\;
Dbg_Trig_Out_7(5) <= \<const0>\;
Dbg_Trig_Out_7(6) <= \<const0>\;
Dbg_Trig_Out_7(7) <= \<const0>\;
Dbg_Trig_Out_8(0) <= \<const0>\;
Dbg_Trig_Out_8(1) <= \<const0>\;
Dbg_Trig_Out_8(2) <= \<const0>\;
Dbg_Trig_Out_8(3) <= \<const0>\;
Dbg_Trig_Out_8(4) <= \<const0>\;
Dbg_Trig_Out_8(5) <= \<const0>\;
Dbg_Trig_Out_8(6) <= \<const0>\;
Dbg_Trig_Out_8(7) <= \<const0>\;
Dbg_Trig_Out_9(0) <= \<const0>\;
Dbg_Trig_Out_9(1) <= \<const0>\;
Dbg_Trig_Out_9(2) <= \<const0>\;
Dbg_Trig_Out_9(3) <= \<const0>\;
Dbg_Trig_Out_9(4) <= \<const0>\;
Dbg_Trig_Out_9(5) <= \<const0>\;
Dbg_Trig_Out_9(6) <= \<const0>\;
Dbg_Trig_Out_9(7) <= \<const0>\;
Dbg_Update_0 <= \^dbg_update_31\;
Dbg_Update_1 <= \^dbg_update_31\;
Dbg_Update_10 <= \^dbg_update_31\;
Dbg_Update_11 <= \^dbg_update_31\;
Dbg_Update_12 <= \^dbg_update_31\;
Dbg_Update_13 <= \^dbg_update_31\;
Dbg_Update_14 <= \^dbg_update_31\;
Dbg_Update_15 <= \^dbg_update_31\;
Dbg_Update_16 <= \^dbg_update_31\;
Dbg_Update_17 <= \^dbg_update_31\;
Dbg_Update_18 <= \^dbg_update_31\;
Dbg_Update_19 <= \^dbg_update_31\;
Dbg_Update_2 <= \^dbg_update_31\;
Dbg_Update_20 <= \^dbg_update_31\;
Dbg_Update_21 <= \^dbg_update_31\;
Dbg_Update_22 <= \^dbg_update_31\;
Dbg_Update_23 <= \^dbg_update_31\;
Dbg_Update_24 <= \^dbg_update_31\;
Dbg_Update_25 <= \^dbg_update_31\;
Dbg_Update_26 <= \^dbg_update_31\;
Dbg_Update_27 <= \^dbg_update_31\;
Dbg_Update_28 <= \^dbg_update_31\;
Dbg_Update_29 <= \^dbg_update_31\;
Dbg_Update_3 <= \^dbg_update_31\;
Dbg_Update_30 <= \^dbg_update_31\;
Dbg_Update_31 <= \^dbg_update_31\;
Dbg_Update_4 <= \^dbg_update_31\;
Dbg_Update_5 <= \^dbg_update_31\;
Dbg_Update_6 <= \^dbg_update_31\;
Dbg_Update_7 <= \^dbg_update_31\;
Dbg_Update_8 <= \^dbg_update_31\;
Dbg_Update_9 <= \^dbg_update_31\;
Dbg_WDATA_0(31) <= \<const0>\;
Dbg_WDATA_0(30) <= \<const0>\;
Dbg_WDATA_0(29) <= \<const0>\;
Dbg_WDATA_0(28) <= \<const0>\;
Dbg_WDATA_0(27) <= \<const0>\;
Dbg_WDATA_0(26) <= \<const0>\;
Dbg_WDATA_0(25) <= \<const0>\;
Dbg_WDATA_0(24) <= \<const0>\;
Dbg_WDATA_0(23) <= \<const0>\;
Dbg_WDATA_0(22) <= \<const0>\;
Dbg_WDATA_0(21) <= \<const0>\;
Dbg_WDATA_0(20) <= \<const0>\;
Dbg_WDATA_0(19) <= \<const0>\;
Dbg_WDATA_0(18) <= \<const0>\;
Dbg_WDATA_0(17) <= \<const0>\;
Dbg_WDATA_0(16) <= \<const0>\;
Dbg_WDATA_0(15) <= \<const0>\;
Dbg_WDATA_0(14) <= \<const0>\;
Dbg_WDATA_0(13) <= \<const0>\;
Dbg_WDATA_0(12) <= \<const0>\;
Dbg_WDATA_0(11) <= \<const0>\;
Dbg_WDATA_0(10) <= \<const0>\;
Dbg_WDATA_0(9) <= \<const0>\;
Dbg_WDATA_0(8) <= \<const0>\;
Dbg_WDATA_0(7) <= \<const0>\;
Dbg_WDATA_0(6) <= \<const0>\;
Dbg_WDATA_0(5) <= \<const0>\;
Dbg_WDATA_0(4) <= \<const0>\;
Dbg_WDATA_0(3) <= \<const0>\;
Dbg_WDATA_0(2) <= \<const0>\;
Dbg_WDATA_0(1) <= \<const0>\;
Dbg_WDATA_0(0) <= \<const0>\;
Dbg_WDATA_1(31) <= \<const0>\;
Dbg_WDATA_1(30) <= \<const0>\;
Dbg_WDATA_1(29) <= \<const0>\;
Dbg_WDATA_1(28) <= \<const0>\;
Dbg_WDATA_1(27) <= \<const0>\;
Dbg_WDATA_1(26) <= \<const0>\;
Dbg_WDATA_1(25) <= \<const0>\;
Dbg_WDATA_1(24) <= \<const0>\;
Dbg_WDATA_1(23) <= \<const0>\;
Dbg_WDATA_1(22) <= \<const0>\;
Dbg_WDATA_1(21) <= \<const0>\;
Dbg_WDATA_1(20) <= \<const0>\;
Dbg_WDATA_1(19) <= \<const0>\;
Dbg_WDATA_1(18) <= \<const0>\;
Dbg_WDATA_1(17) <= \<const0>\;
Dbg_WDATA_1(16) <= \<const0>\;
Dbg_WDATA_1(15) <= \<const0>\;
Dbg_WDATA_1(14) <= \<const0>\;
Dbg_WDATA_1(13) <= \<const0>\;
Dbg_WDATA_1(12) <= \<const0>\;
Dbg_WDATA_1(11) <= \<const0>\;
Dbg_WDATA_1(10) <= \<const0>\;
Dbg_WDATA_1(9) <= \<const0>\;
Dbg_WDATA_1(8) <= \<const0>\;
Dbg_WDATA_1(7) <= \<const0>\;
Dbg_WDATA_1(6) <= \<const0>\;
Dbg_WDATA_1(5) <= \<const0>\;
Dbg_WDATA_1(4) <= \<const0>\;
Dbg_WDATA_1(3) <= \<const0>\;
Dbg_WDATA_1(2) <= \<const0>\;
Dbg_WDATA_1(1) <= \<const0>\;
Dbg_WDATA_1(0) <= \<const0>\;
Dbg_WDATA_10(31) <= \<const0>\;
Dbg_WDATA_10(30) <= \<const0>\;
Dbg_WDATA_10(29) <= \<const0>\;
Dbg_WDATA_10(28) <= \<const0>\;
Dbg_WDATA_10(27) <= \<const0>\;
Dbg_WDATA_10(26) <= \<const0>\;
Dbg_WDATA_10(25) <= \<const0>\;
Dbg_WDATA_10(24) <= \<const0>\;
Dbg_WDATA_10(23) <= \<const0>\;
Dbg_WDATA_10(22) <= \<const0>\;
Dbg_WDATA_10(21) <= \<const0>\;
Dbg_WDATA_10(20) <= \<const0>\;
Dbg_WDATA_10(19) <= \<const0>\;
Dbg_WDATA_10(18) <= \<const0>\;
Dbg_WDATA_10(17) <= \<const0>\;
Dbg_WDATA_10(16) <= \<const0>\;
Dbg_WDATA_10(15) <= \<const0>\;
Dbg_WDATA_10(14) <= \<const0>\;
Dbg_WDATA_10(13) <= \<const0>\;
Dbg_WDATA_10(12) <= \<const0>\;
Dbg_WDATA_10(11) <= \<const0>\;
Dbg_WDATA_10(10) <= \<const0>\;
Dbg_WDATA_10(9) <= \<const0>\;
Dbg_WDATA_10(8) <= \<const0>\;
Dbg_WDATA_10(7) <= \<const0>\;
Dbg_WDATA_10(6) <= \<const0>\;
Dbg_WDATA_10(5) <= \<const0>\;
Dbg_WDATA_10(4) <= \<const0>\;
Dbg_WDATA_10(3) <= \<const0>\;
Dbg_WDATA_10(2) <= \<const0>\;
Dbg_WDATA_10(1) <= \<const0>\;
Dbg_WDATA_10(0) <= \<const0>\;
Dbg_WDATA_11(31) <= \<const0>\;
Dbg_WDATA_11(30) <= \<const0>\;
Dbg_WDATA_11(29) <= \<const0>\;
Dbg_WDATA_11(28) <= \<const0>\;
Dbg_WDATA_11(27) <= \<const0>\;
Dbg_WDATA_11(26) <= \<const0>\;
Dbg_WDATA_11(25) <= \<const0>\;
Dbg_WDATA_11(24) <= \<const0>\;
Dbg_WDATA_11(23) <= \<const0>\;
Dbg_WDATA_11(22) <= \<const0>\;
Dbg_WDATA_11(21) <= \<const0>\;
Dbg_WDATA_11(20) <= \<const0>\;
Dbg_WDATA_11(19) <= \<const0>\;
Dbg_WDATA_11(18) <= \<const0>\;
Dbg_WDATA_11(17) <= \<const0>\;
Dbg_WDATA_11(16) <= \<const0>\;
Dbg_WDATA_11(15) <= \<const0>\;
Dbg_WDATA_11(14) <= \<const0>\;
Dbg_WDATA_11(13) <= \<const0>\;
Dbg_WDATA_11(12) <= \<const0>\;
Dbg_WDATA_11(11) <= \<const0>\;
Dbg_WDATA_11(10) <= \<const0>\;
Dbg_WDATA_11(9) <= \<const0>\;
Dbg_WDATA_11(8) <= \<const0>\;
Dbg_WDATA_11(7) <= \<const0>\;
Dbg_WDATA_11(6) <= \<const0>\;
Dbg_WDATA_11(5) <= \<const0>\;
Dbg_WDATA_11(4) <= \<const0>\;
Dbg_WDATA_11(3) <= \<const0>\;
Dbg_WDATA_11(2) <= \<const0>\;
Dbg_WDATA_11(1) <= \<const0>\;
Dbg_WDATA_11(0) <= \<const0>\;
Dbg_WDATA_12(31) <= \<const0>\;
Dbg_WDATA_12(30) <= \<const0>\;
Dbg_WDATA_12(29) <= \<const0>\;
Dbg_WDATA_12(28) <= \<const0>\;
Dbg_WDATA_12(27) <= \<const0>\;
Dbg_WDATA_12(26) <= \<const0>\;
Dbg_WDATA_12(25) <= \<const0>\;
Dbg_WDATA_12(24) <= \<const0>\;
Dbg_WDATA_12(23) <= \<const0>\;
Dbg_WDATA_12(22) <= \<const0>\;
Dbg_WDATA_12(21) <= \<const0>\;
Dbg_WDATA_12(20) <= \<const0>\;
Dbg_WDATA_12(19) <= \<const0>\;
Dbg_WDATA_12(18) <= \<const0>\;
Dbg_WDATA_12(17) <= \<const0>\;
Dbg_WDATA_12(16) <= \<const0>\;
Dbg_WDATA_12(15) <= \<const0>\;
Dbg_WDATA_12(14) <= \<const0>\;
Dbg_WDATA_12(13) <= \<const0>\;
Dbg_WDATA_12(12) <= \<const0>\;
Dbg_WDATA_12(11) <= \<const0>\;
Dbg_WDATA_12(10) <= \<const0>\;
Dbg_WDATA_12(9) <= \<const0>\;
Dbg_WDATA_12(8) <= \<const0>\;
Dbg_WDATA_12(7) <= \<const0>\;
Dbg_WDATA_12(6) <= \<const0>\;
Dbg_WDATA_12(5) <= \<const0>\;
Dbg_WDATA_12(4) <= \<const0>\;
Dbg_WDATA_12(3) <= \<const0>\;
Dbg_WDATA_12(2) <= \<const0>\;
Dbg_WDATA_12(1) <= \<const0>\;
Dbg_WDATA_12(0) <= \<const0>\;
Dbg_WDATA_13(31) <= \<const0>\;
Dbg_WDATA_13(30) <= \<const0>\;
Dbg_WDATA_13(29) <= \<const0>\;
Dbg_WDATA_13(28) <= \<const0>\;
Dbg_WDATA_13(27) <= \<const0>\;
Dbg_WDATA_13(26) <= \<const0>\;
Dbg_WDATA_13(25) <= \<const0>\;
Dbg_WDATA_13(24) <= \<const0>\;
Dbg_WDATA_13(23) <= \<const0>\;
Dbg_WDATA_13(22) <= \<const0>\;
Dbg_WDATA_13(21) <= \<const0>\;
Dbg_WDATA_13(20) <= \<const0>\;
Dbg_WDATA_13(19) <= \<const0>\;
Dbg_WDATA_13(18) <= \<const0>\;
Dbg_WDATA_13(17) <= \<const0>\;
Dbg_WDATA_13(16) <= \<const0>\;
Dbg_WDATA_13(15) <= \<const0>\;
Dbg_WDATA_13(14) <= \<const0>\;
Dbg_WDATA_13(13) <= \<const0>\;
Dbg_WDATA_13(12) <= \<const0>\;
Dbg_WDATA_13(11) <= \<const0>\;
Dbg_WDATA_13(10) <= \<const0>\;
Dbg_WDATA_13(9) <= \<const0>\;
Dbg_WDATA_13(8) <= \<const0>\;
Dbg_WDATA_13(7) <= \<const0>\;
Dbg_WDATA_13(6) <= \<const0>\;
Dbg_WDATA_13(5) <= \<const0>\;
Dbg_WDATA_13(4) <= \<const0>\;
Dbg_WDATA_13(3) <= \<const0>\;
Dbg_WDATA_13(2) <= \<const0>\;
Dbg_WDATA_13(1) <= \<const0>\;
Dbg_WDATA_13(0) <= \<const0>\;
Dbg_WDATA_14(31) <= \<const0>\;
Dbg_WDATA_14(30) <= \<const0>\;
Dbg_WDATA_14(29) <= \<const0>\;
Dbg_WDATA_14(28) <= \<const0>\;
Dbg_WDATA_14(27) <= \<const0>\;
Dbg_WDATA_14(26) <= \<const0>\;
Dbg_WDATA_14(25) <= \<const0>\;
Dbg_WDATA_14(24) <= \<const0>\;
Dbg_WDATA_14(23) <= \<const0>\;
Dbg_WDATA_14(22) <= \<const0>\;
Dbg_WDATA_14(21) <= \<const0>\;
Dbg_WDATA_14(20) <= \<const0>\;
Dbg_WDATA_14(19) <= \<const0>\;
Dbg_WDATA_14(18) <= \<const0>\;
Dbg_WDATA_14(17) <= \<const0>\;
Dbg_WDATA_14(16) <= \<const0>\;
Dbg_WDATA_14(15) <= \<const0>\;
Dbg_WDATA_14(14) <= \<const0>\;
Dbg_WDATA_14(13) <= \<const0>\;
Dbg_WDATA_14(12) <= \<const0>\;
Dbg_WDATA_14(11) <= \<const0>\;
Dbg_WDATA_14(10) <= \<const0>\;
Dbg_WDATA_14(9) <= \<const0>\;
Dbg_WDATA_14(8) <= \<const0>\;
Dbg_WDATA_14(7) <= \<const0>\;
Dbg_WDATA_14(6) <= \<const0>\;
Dbg_WDATA_14(5) <= \<const0>\;
Dbg_WDATA_14(4) <= \<const0>\;
Dbg_WDATA_14(3) <= \<const0>\;
Dbg_WDATA_14(2) <= \<const0>\;
Dbg_WDATA_14(1) <= \<const0>\;
Dbg_WDATA_14(0) <= \<const0>\;
Dbg_WDATA_15(31) <= \<const0>\;
Dbg_WDATA_15(30) <= \<const0>\;
Dbg_WDATA_15(29) <= \<const0>\;
Dbg_WDATA_15(28) <= \<const0>\;
Dbg_WDATA_15(27) <= \<const0>\;
Dbg_WDATA_15(26) <= \<const0>\;
Dbg_WDATA_15(25) <= \<const0>\;
Dbg_WDATA_15(24) <= \<const0>\;
Dbg_WDATA_15(23) <= \<const0>\;
Dbg_WDATA_15(22) <= \<const0>\;
Dbg_WDATA_15(21) <= \<const0>\;
Dbg_WDATA_15(20) <= \<const0>\;
Dbg_WDATA_15(19) <= \<const0>\;
Dbg_WDATA_15(18) <= \<const0>\;
Dbg_WDATA_15(17) <= \<const0>\;
Dbg_WDATA_15(16) <= \<const0>\;
Dbg_WDATA_15(15) <= \<const0>\;
Dbg_WDATA_15(14) <= \<const0>\;
Dbg_WDATA_15(13) <= \<const0>\;
Dbg_WDATA_15(12) <= \<const0>\;
Dbg_WDATA_15(11) <= \<const0>\;
Dbg_WDATA_15(10) <= \<const0>\;
Dbg_WDATA_15(9) <= \<const0>\;
Dbg_WDATA_15(8) <= \<const0>\;
Dbg_WDATA_15(7) <= \<const0>\;
Dbg_WDATA_15(6) <= \<const0>\;
Dbg_WDATA_15(5) <= \<const0>\;
Dbg_WDATA_15(4) <= \<const0>\;
Dbg_WDATA_15(3) <= \<const0>\;
Dbg_WDATA_15(2) <= \<const0>\;
Dbg_WDATA_15(1) <= \<const0>\;
Dbg_WDATA_15(0) <= \<const0>\;
Dbg_WDATA_16(31) <= \<const0>\;
Dbg_WDATA_16(30) <= \<const0>\;
Dbg_WDATA_16(29) <= \<const0>\;
Dbg_WDATA_16(28) <= \<const0>\;
Dbg_WDATA_16(27) <= \<const0>\;
Dbg_WDATA_16(26) <= \<const0>\;
Dbg_WDATA_16(25) <= \<const0>\;
Dbg_WDATA_16(24) <= \<const0>\;
Dbg_WDATA_16(23) <= \<const0>\;
Dbg_WDATA_16(22) <= \<const0>\;
Dbg_WDATA_16(21) <= \<const0>\;
Dbg_WDATA_16(20) <= \<const0>\;
Dbg_WDATA_16(19) <= \<const0>\;
Dbg_WDATA_16(18) <= \<const0>\;
Dbg_WDATA_16(17) <= \<const0>\;
Dbg_WDATA_16(16) <= \<const0>\;
Dbg_WDATA_16(15) <= \<const0>\;
Dbg_WDATA_16(14) <= \<const0>\;
Dbg_WDATA_16(13) <= \<const0>\;
Dbg_WDATA_16(12) <= \<const0>\;
Dbg_WDATA_16(11) <= \<const0>\;
Dbg_WDATA_16(10) <= \<const0>\;
Dbg_WDATA_16(9) <= \<const0>\;
Dbg_WDATA_16(8) <= \<const0>\;
Dbg_WDATA_16(7) <= \<const0>\;
Dbg_WDATA_16(6) <= \<const0>\;
Dbg_WDATA_16(5) <= \<const0>\;
Dbg_WDATA_16(4) <= \<const0>\;
Dbg_WDATA_16(3) <= \<const0>\;
Dbg_WDATA_16(2) <= \<const0>\;
Dbg_WDATA_16(1) <= \<const0>\;
Dbg_WDATA_16(0) <= \<const0>\;
Dbg_WDATA_17(31) <= \<const0>\;
Dbg_WDATA_17(30) <= \<const0>\;
Dbg_WDATA_17(29) <= \<const0>\;
Dbg_WDATA_17(28) <= \<const0>\;
Dbg_WDATA_17(27) <= \<const0>\;
Dbg_WDATA_17(26) <= \<const0>\;
Dbg_WDATA_17(25) <= \<const0>\;
Dbg_WDATA_17(24) <= \<const0>\;
Dbg_WDATA_17(23) <= \<const0>\;
Dbg_WDATA_17(22) <= \<const0>\;
Dbg_WDATA_17(21) <= \<const0>\;
Dbg_WDATA_17(20) <= \<const0>\;
Dbg_WDATA_17(19) <= \<const0>\;
Dbg_WDATA_17(18) <= \<const0>\;
Dbg_WDATA_17(17) <= \<const0>\;
Dbg_WDATA_17(16) <= \<const0>\;
Dbg_WDATA_17(15) <= \<const0>\;
Dbg_WDATA_17(14) <= \<const0>\;
Dbg_WDATA_17(13) <= \<const0>\;
Dbg_WDATA_17(12) <= \<const0>\;
Dbg_WDATA_17(11) <= \<const0>\;
Dbg_WDATA_17(10) <= \<const0>\;
Dbg_WDATA_17(9) <= \<const0>\;
Dbg_WDATA_17(8) <= \<const0>\;
Dbg_WDATA_17(7) <= \<const0>\;
Dbg_WDATA_17(6) <= \<const0>\;
Dbg_WDATA_17(5) <= \<const0>\;
Dbg_WDATA_17(4) <= \<const0>\;
Dbg_WDATA_17(3) <= \<const0>\;
Dbg_WDATA_17(2) <= \<const0>\;
Dbg_WDATA_17(1) <= \<const0>\;
Dbg_WDATA_17(0) <= \<const0>\;
Dbg_WDATA_18(31) <= \<const0>\;
Dbg_WDATA_18(30) <= \<const0>\;
Dbg_WDATA_18(29) <= \<const0>\;
Dbg_WDATA_18(28) <= \<const0>\;
Dbg_WDATA_18(27) <= \<const0>\;
Dbg_WDATA_18(26) <= \<const0>\;
Dbg_WDATA_18(25) <= \<const0>\;
Dbg_WDATA_18(24) <= \<const0>\;
Dbg_WDATA_18(23) <= \<const0>\;
Dbg_WDATA_18(22) <= \<const0>\;
Dbg_WDATA_18(21) <= \<const0>\;
Dbg_WDATA_18(20) <= \<const0>\;
Dbg_WDATA_18(19) <= \<const0>\;
Dbg_WDATA_18(18) <= \<const0>\;
Dbg_WDATA_18(17) <= \<const0>\;
Dbg_WDATA_18(16) <= \<const0>\;
Dbg_WDATA_18(15) <= \<const0>\;
Dbg_WDATA_18(14) <= \<const0>\;
Dbg_WDATA_18(13) <= \<const0>\;
Dbg_WDATA_18(12) <= \<const0>\;
Dbg_WDATA_18(11) <= \<const0>\;
Dbg_WDATA_18(10) <= \<const0>\;
Dbg_WDATA_18(9) <= \<const0>\;
Dbg_WDATA_18(8) <= \<const0>\;
Dbg_WDATA_18(7) <= \<const0>\;
Dbg_WDATA_18(6) <= \<const0>\;
Dbg_WDATA_18(5) <= \<const0>\;
Dbg_WDATA_18(4) <= \<const0>\;
Dbg_WDATA_18(3) <= \<const0>\;
Dbg_WDATA_18(2) <= \<const0>\;
Dbg_WDATA_18(1) <= \<const0>\;
Dbg_WDATA_18(0) <= \<const0>\;
Dbg_WDATA_19(31) <= \<const0>\;
Dbg_WDATA_19(30) <= \<const0>\;
Dbg_WDATA_19(29) <= \<const0>\;
Dbg_WDATA_19(28) <= \<const0>\;
Dbg_WDATA_19(27) <= \<const0>\;
Dbg_WDATA_19(26) <= \<const0>\;
Dbg_WDATA_19(25) <= \<const0>\;
Dbg_WDATA_19(24) <= \<const0>\;
Dbg_WDATA_19(23) <= \<const0>\;
Dbg_WDATA_19(22) <= \<const0>\;
Dbg_WDATA_19(21) <= \<const0>\;
Dbg_WDATA_19(20) <= \<const0>\;
Dbg_WDATA_19(19) <= \<const0>\;
Dbg_WDATA_19(18) <= \<const0>\;
Dbg_WDATA_19(17) <= \<const0>\;
Dbg_WDATA_19(16) <= \<const0>\;
Dbg_WDATA_19(15) <= \<const0>\;
Dbg_WDATA_19(14) <= \<const0>\;
Dbg_WDATA_19(13) <= \<const0>\;
Dbg_WDATA_19(12) <= \<const0>\;
Dbg_WDATA_19(11) <= \<const0>\;
Dbg_WDATA_19(10) <= \<const0>\;
Dbg_WDATA_19(9) <= \<const0>\;
Dbg_WDATA_19(8) <= \<const0>\;
Dbg_WDATA_19(7) <= \<const0>\;
Dbg_WDATA_19(6) <= \<const0>\;
Dbg_WDATA_19(5) <= \<const0>\;
Dbg_WDATA_19(4) <= \<const0>\;
Dbg_WDATA_19(3) <= \<const0>\;
Dbg_WDATA_19(2) <= \<const0>\;
Dbg_WDATA_19(1) <= \<const0>\;
Dbg_WDATA_19(0) <= \<const0>\;
Dbg_WDATA_2(31) <= \<const0>\;
Dbg_WDATA_2(30) <= \<const0>\;
Dbg_WDATA_2(29) <= \<const0>\;
Dbg_WDATA_2(28) <= \<const0>\;
Dbg_WDATA_2(27) <= \<const0>\;
Dbg_WDATA_2(26) <= \<const0>\;
Dbg_WDATA_2(25) <= \<const0>\;
Dbg_WDATA_2(24) <= \<const0>\;
Dbg_WDATA_2(23) <= \<const0>\;
Dbg_WDATA_2(22) <= \<const0>\;
Dbg_WDATA_2(21) <= \<const0>\;
Dbg_WDATA_2(20) <= \<const0>\;
Dbg_WDATA_2(19) <= \<const0>\;
Dbg_WDATA_2(18) <= \<const0>\;
Dbg_WDATA_2(17) <= \<const0>\;
Dbg_WDATA_2(16) <= \<const0>\;
Dbg_WDATA_2(15) <= \<const0>\;
Dbg_WDATA_2(14) <= \<const0>\;
Dbg_WDATA_2(13) <= \<const0>\;
Dbg_WDATA_2(12) <= \<const0>\;
Dbg_WDATA_2(11) <= \<const0>\;
Dbg_WDATA_2(10) <= \<const0>\;
Dbg_WDATA_2(9) <= \<const0>\;
Dbg_WDATA_2(8) <= \<const0>\;
Dbg_WDATA_2(7) <= \<const0>\;
Dbg_WDATA_2(6) <= \<const0>\;
Dbg_WDATA_2(5) <= \<const0>\;
Dbg_WDATA_2(4) <= \<const0>\;
Dbg_WDATA_2(3) <= \<const0>\;
Dbg_WDATA_2(2) <= \<const0>\;
Dbg_WDATA_2(1) <= \<const0>\;
Dbg_WDATA_2(0) <= \<const0>\;
Dbg_WDATA_20(31) <= \<const0>\;
Dbg_WDATA_20(30) <= \<const0>\;
Dbg_WDATA_20(29) <= \<const0>\;
Dbg_WDATA_20(28) <= \<const0>\;
Dbg_WDATA_20(27) <= \<const0>\;
Dbg_WDATA_20(26) <= \<const0>\;
Dbg_WDATA_20(25) <= \<const0>\;
Dbg_WDATA_20(24) <= \<const0>\;
Dbg_WDATA_20(23) <= \<const0>\;
Dbg_WDATA_20(22) <= \<const0>\;
Dbg_WDATA_20(21) <= \<const0>\;
Dbg_WDATA_20(20) <= \<const0>\;
Dbg_WDATA_20(19) <= \<const0>\;
Dbg_WDATA_20(18) <= \<const0>\;
Dbg_WDATA_20(17) <= \<const0>\;
Dbg_WDATA_20(16) <= \<const0>\;
Dbg_WDATA_20(15) <= \<const0>\;
Dbg_WDATA_20(14) <= \<const0>\;
Dbg_WDATA_20(13) <= \<const0>\;
Dbg_WDATA_20(12) <= \<const0>\;
Dbg_WDATA_20(11) <= \<const0>\;
Dbg_WDATA_20(10) <= \<const0>\;
Dbg_WDATA_20(9) <= \<const0>\;
Dbg_WDATA_20(8) <= \<const0>\;
Dbg_WDATA_20(7) <= \<const0>\;
Dbg_WDATA_20(6) <= \<const0>\;
Dbg_WDATA_20(5) <= \<const0>\;
Dbg_WDATA_20(4) <= \<const0>\;
Dbg_WDATA_20(3) <= \<const0>\;
Dbg_WDATA_20(2) <= \<const0>\;
Dbg_WDATA_20(1) <= \<const0>\;
Dbg_WDATA_20(0) <= \<const0>\;
Dbg_WDATA_21(31) <= \<const0>\;
Dbg_WDATA_21(30) <= \<const0>\;
Dbg_WDATA_21(29) <= \<const0>\;
Dbg_WDATA_21(28) <= \<const0>\;
Dbg_WDATA_21(27) <= \<const0>\;
Dbg_WDATA_21(26) <= \<const0>\;
Dbg_WDATA_21(25) <= \<const0>\;
Dbg_WDATA_21(24) <= \<const0>\;
Dbg_WDATA_21(23) <= \<const0>\;
Dbg_WDATA_21(22) <= \<const0>\;
Dbg_WDATA_21(21) <= \<const0>\;
Dbg_WDATA_21(20) <= \<const0>\;
Dbg_WDATA_21(19) <= \<const0>\;
Dbg_WDATA_21(18) <= \<const0>\;
Dbg_WDATA_21(17) <= \<const0>\;
Dbg_WDATA_21(16) <= \<const0>\;
Dbg_WDATA_21(15) <= \<const0>\;
Dbg_WDATA_21(14) <= \<const0>\;
Dbg_WDATA_21(13) <= \<const0>\;
Dbg_WDATA_21(12) <= \<const0>\;
Dbg_WDATA_21(11) <= \<const0>\;
Dbg_WDATA_21(10) <= \<const0>\;
Dbg_WDATA_21(9) <= \<const0>\;
Dbg_WDATA_21(8) <= \<const0>\;
Dbg_WDATA_21(7) <= \<const0>\;
Dbg_WDATA_21(6) <= \<const0>\;
Dbg_WDATA_21(5) <= \<const0>\;
Dbg_WDATA_21(4) <= \<const0>\;
Dbg_WDATA_21(3) <= \<const0>\;
Dbg_WDATA_21(2) <= \<const0>\;
Dbg_WDATA_21(1) <= \<const0>\;
Dbg_WDATA_21(0) <= \<const0>\;
Dbg_WDATA_22(31) <= \<const0>\;
Dbg_WDATA_22(30) <= \<const0>\;
Dbg_WDATA_22(29) <= \<const0>\;
Dbg_WDATA_22(28) <= \<const0>\;
Dbg_WDATA_22(27) <= \<const0>\;
Dbg_WDATA_22(26) <= \<const0>\;
Dbg_WDATA_22(25) <= \<const0>\;
Dbg_WDATA_22(24) <= \<const0>\;
Dbg_WDATA_22(23) <= \<const0>\;
Dbg_WDATA_22(22) <= \<const0>\;
Dbg_WDATA_22(21) <= \<const0>\;
Dbg_WDATA_22(20) <= \<const0>\;
Dbg_WDATA_22(19) <= \<const0>\;
Dbg_WDATA_22(18) <= \<const0>\;
Dbg_WDATA_22(17) <= \<const0>\;
Dbg_WDATA_22(16) <= \<const0>\;
Dbg_WDATA_22(15) <= \<const0>\;
Dbg_WDATA_22(14) <= \<const0>\;
Dbg_WDATA_22(13) <= \<const0>\;
Dbg_WDATA_22(12) <= \<const0>\;
Dbg_WDATA_22(11) <= \<const0>\;
Dbg_WDATA_22(10) <= \<const0>\;
Dbg_WDATA_22(9) <= \<const0>\;
Dbg_WDATA_22(8) <= \<const0>\;
Dbg_WDATA_22(7) <= \<const0>\;
Dbg_WDATA_22(6) <= \<const0>\;
Dbg_WDATA_22(5) <= \<const0>\;
Dbg_WDATA_22(4) <= \<const0>\;
Dbg_WDATA_22(3) <= \<const0>\;
Dbg_WDATA_22(2) <= \<const0>\;
Dbg_WDATA_22(1) <= \<const0>\;
Dbg_WDATA_22(0) <= \<const0>\;
Dbg_WDATA_23(31) <= \<const0>\;
Dbg_WDATA_23(30) <= \<const0>\;
Dbg_WDATA_23(29) <= \<const0>\;
Dbg_WDATA_23(28) <= \<const0>\;
Dbg_WDATA_23(27) <= \<const0>\;
Dbg_WDATA_23(26) <= \<const0>\;
Dbg_WDATA_23(25) <= \<const0>\;
Dbg_WDATA_23(24) <= \<const0>\;
Dbg_WDATA_23(23) <= \<const0>\;
Dbg_WDATA_23(22) <= \<const0>\;
Dbg_WDATA_23(21) <= \<const0>\;
Dbg_WDATA_23(20) <= \<const0>\;
Dbg_WDATA_23(19) <= \<const0>\;
Dbg_WDATA_23(18) <= \<const0>\;
Dbg_WDATA_23(17) <= \<const0>\;
Dbg_WDATA_23(16) <= \<const0>\;
Dbg_WDATA_23(15) <= \<const0>\;
Dbg_WDATA_23(14) <= \<const0>\;
Dbg_WDATA_23(13) <= \<const0>\;
Dbg_WDATA_23(12) <= \<const0>\;
Dbg_WDATA_23(11) <= \<const0>\;
Dbg_WDATA_23(10) <= \<const0>\;
Dbg_WDATA_23(9) <= \<const0>\;
Dbg_WDATA_23(8) <= \<const0>\;
Dbg_WDATA_23(7) <= \<const0>\;
Dbg_WDATA_23(6) <= \<const0>\;
Dbg_WDATA_23(5) <= \<const0>\;
Dbg_WDATA_23(4) <= \<const0>\;
Dbg_WDATA_23(3) <= \<const0>\;
Dbg_WDATA_23(2) <= \<const0>\;
Dbg_WDATA_23(1) <= \<const0>\;
Dbg_WDATA_23(0) <= \<const0>\;
Dbg_WDATA_24(31) <= \<const0>\;
Dbg_WDATA_24(30) <= \<const0>\;
Dbg_WDATA_24(29) <= \<const0>\;
Dbg_WDATA_24(28) <= \<const0>\;
Dbg_WDATA_24(27) <= \<const0>\;
Dbg_WDATA_24(26) <= \<const0>\;
Dbg_WDATA_24(25) <= \<const0>\;
Dbg_WDATA_24(24) <= \<const0>\;
Dbg_WDATA_24(23) <= \<const0>\;
Dbg_WDATA_24(22) <= \<const0>\;
Dbg_WDATA_24(21) <= \<const0>\;
Dbg_WDATA_24(20) <= \<const0>\;
Dbg_WDATA_24(19) <= \<const0>\;
Dbg_WDATA_24(18) <= \<const0>\;
Dbg_WDATA_24(17) <= \<const0>\;
Dbg_WDATA_24(16) <= \<const0>\;
Dbg_WDATA_24(15) <= \<const0>\;
Dbg_WDATA_24(14) <= \<const0>\;
Dbg_WDATA_24(13) <= \<const0>\;
Dbg_WDATA_24(12) <= \<const0>\;
Dbg_WDATA_24(11) <= \<const0>\;
Dbg_WDATA_24(10) <= \<const0>\;
Dbg_WDATA_24(9) <= \<const0>\;
Dbg_WDATA_24(8) <= \<const0>\;
Dbg_WDATA_24(7) <= \<const0>\;
Dbg_WDATA_24(6) <= \<const0>\;
Dbg_WDATA_24(5) <= \<const0>\;
Dbg_WDATA_24(4) <= \<const0>\;
Dbg_WDATA_24(3) <= \<const0>\;
Dbg_WDATA_24(2) <= \<const0>\;
Dbg_WDATA_24(1) <= \<const0>\;
Dbg_WDATA_24(0) <= \<const0>\;
Dbg_WDATA_25(31) <= \<const0>\;
Dbg_WDATA_25(30) <= \<const0>\;
Dbg_WDATA_25(29) <= \<const0>\;
Dbg_WDATA_25(28) <= \<const0>\;
Dbg_WDATA_25(27) <= \<const0>\;
Dbg_WDATA_25(26) <= \<const0>\;
Dbg_WDATA_25(25) <= \<const0>\;
Dbg_WDATA_25(24) <= \<const0>\;
Dbg_WDATA_25(23) <= \<const0>\;
Dbg_WDATA_25(22) <= \<const0>\;
Dbg_WDATA_25(21) <= \<const0>\;
Dbg_WDATA_25(20) <= \<const0>\;
Dbg_WDATA_25(19) <= \<const0>\;
Dbg_WDATA_25(18) <= \<const0>\;
Dbg_WDATA_25(17) <= \<const0>\;
Dbg_WDATA_25(16) <= \<const0>\;
Dbg_WDATA_25(15) <= \<const0>\;
Dbg_WDATA_25(14) <= \<const0>\;
Dbg_WDATA_25(13) <= \<const0>\;
Dbg_WDATA_25(12) <= \<const0>\;
Dbg_WDATA_25(11) <= \<const0>\;
Dbg_WDATA_25(10) <= \<const0>\;
Dbg_WDATA_25(9) <= \<const0>\;
Dbg_WDATA_25(8) <= \<const0>\;
Dbg_WDATA_25(7) <= \<const0>\;
Dbg_WDATA_25(6) <= \<const0>\;
Dbg_WDATA_25(5) <= \<const0>\;
Dbg_WDATA_25(4) <= \<const0>\;
Dbg_WDATA_25(3) <= \<const0>\;
Dbg_WDATA_25(2) <= \<const0>\;
Dbg_WDATA_25(1) <= \<const0>\;
Dbg_WDATA_25(0) <= \<const0>\;
Dbg_WDATA_26(31) <= \<const0>\;
Dbg_WDATA_26(30) <= \<const0>\;
Dbg_WDATA_26(29) <= \<const0>\;
Dbg_WDATA_26(28) <= \<const0>\;
Dbg_WDATA_26(27) <= \<const0>\;
Dbg_WDATA_26(26) <= \<const0>\;
Dbg_WDATA_26(25) <= \<const0>\;
Dbg_WDATA_26(24) <= \<const0>\;
Dbg_WDATA_26(23) <= \<const0>\;
Dbg_WDATA_26(22) <= \<const0>\;
Dbg_WDATA_26(21) <= \<const0>\;
Dbg_WDATA_26(20) <= \<const0>\;
Dbg_WDATA_26(19) <= \<const0>\;
Dbg_WDATA_26(18) <= \<const0>\;
Dbg_WDATA_26(17) <= \<const0>\;
Dbg_WDATA_26(16) <= \<const0>\;
Dbg_WDATA_26(15) <= \<const0>\;
Dbg_WDATA_26(14) <= \<const0>\;
Dbg_WDATA_26(13) <= \<const0>\;
Dbg_WDATA_26(12) <= \<const0>\;
Dbg_WDATA_26(11) <= \<const0>\;
Dbg_WDATA_26(10) <= \<const0>\;
Dbg_WDATA_26(9) <= \<const0>\;
Dbg_WDATA_26(8) <= \<const0>\;
Dbg_WDATA_26(7) <= \<const0>\;
Dbg_WDATA_26(6) <= \<const0>\;
Dbg_WDATA_26(5) <= \<const0>\;
Dbg_WDATA_26(4) <= \<const0>\;
Dbg_WDATA_26(3) <= \<const0>\;
Dbg_WDATA_26(2) <= \<const0>\;
Dbg_WDATA_26(1) <= \<const0>\;
Dbg_WDATA_26(0) <= \<const0>\;
Dbg_WDATA_27(31) <= \<const0>\;
Dbg_WDATA_27(30) <= \<const0>\;
Dbg_WDATA_27(29) <= \<const0>\;
Dbg_WDATA_27(28) <= \<const0>\;
Dbg_WDATA_27(27) <= \<const0>\;
Dbg_WDATA_27(26) <= \<const0>\;
Dbg_WDATA_27(25) <= \<const0>\;
Dbg_WDATA_27(24) <= \<const0>\;
Dbg_WDATA_27(23) <= \<const0>\;
Dbg_WDATA_27(22) <= \<const0>\;
Dbg_WDATA_27(21) <= \<const0>\;
Dbg_WDATA_27(20) <= \<const0>\;
Dbg_WDATA_27(19) <= \<const0>\;
Dbg_WDATA_27(18) <= \<const0>\;
Dbg_WDATA_27(17) <= \<const0>\;
Dbg_WDATA_27(16) <= \<const0>\;
Dbg_WDATA_27(15) <= \<const0>\;
Dbg_WDATA_27(14) <= \<const0>\;
Dbg_WDATA_27(13) <= \<const0>\;
Dbg_WDATA_27(12) <= \<const0>\;
Dbg_WDATA_27(11) <= \<const0>\;
Dbg_WDATA_27(10) <= \<const0>\;
Dbg_WDATA_27(9) <= \<const0>\;
Dbg_WDATA_27(8) <= \<const0>\;
Dbg_WDATA_27(7) <= \<const0>\;
Dbg_WDATA_27(6) <= \<const0>\;
Dbg_WDATA_27(5) <= \<const0>\;
Dbg_WDATA_27(4) <= \<const0>\;
Dbg_WDATA_27(3) <= \<const0>\;
Dbg_WDATA_27(2) <= \<const0>\;
Dbg_WDATA_27(1) <= \<const0>\;
Dbg_WDATA_27(0) <= \<const0>\;
Dbg_WDATA_28(31) <= \<const0>\;
Dbg_WDATA_28(30) <= \<const0>\;
Dbg_WDATA_28(29) <= \<const0>\;
Dbg_WDATA_28(28) <= \<const0>\;
Dbg_WDATA_28(27) <= \<const0>\;
Dbg_WDATA_28(26) <= \<const0>\;
Dbg_WDATA_28(25) <= \<const0>\;
Dbg_WDATA_28(24) <= \<const0>\;
Dbg_WDATA_28(23) <= \<const0>\;
Dbg_WDATA_28(22) <= \<const0>\;
Dbg_WDATA_28(21) <= \<const0>\;
Dbg_WDATA_28(20) <= \<const0>\;
Dbg_WDATA_28(19) <= \<const0>\;
Dbg_WDATA_28(18) <= \<const0>\;
Dbg_WDATA_28(17) <= \<const0>\;
Dbg_WDATA_28(16) <= \<const0>\;
Dbg_WDATA_28(15) <= \<const0>\;
Dbg_WDATA_28(14) <= \<const0>\;
Dbg_WDATA_28(13) <= \<const0>\;
Dbg_WDATA_28(12) <= \<const0>\;
Dbg_WDATA_28(11) <= \<const0>\;
Dbg_WDATA_28(10) <= \<const0>\;
Dbg_WDATA_28(9) <= \<const0>\;
Dbg_WDATA_28(8) <= \<const0>\;
Dbg_WDATA_28(7) <= \<const0>\;
Dbg_WDATA_28(6) <= \<const0>\;
Dbg_WDATA_28(5) <= \<const0>\;
Dbg_WDATA_28(4) <= \<const0>\;
Dbg_WDATA_28(3) <= \<const0>\;
Dbg_WDATA_28(2) <= \<const0>\;
Dbg_WDATA_28(1) <= \<const0>\;
Dbg_WDATA_28(0) <= \<const0>\;
Dbg_WDATA_29(31) <= \<const0>\;
Dbg_WDATA_29(30) <= \<const0>\;
Dbg_WDATA_29(29) <= \<const0>\;
Dbg_WDATA_29(28) <= \<const0>\;
Dbg_WDATA_29(27) <= \<const0>\;
Dbg_WDATA_29(26) <= \<const0>\;
Dbg_WDATA_29(25) <= \<const0>\;
Dbg_WDATA_29(24) <= \<const0>\;
Dbg_WDATA_29(23) <= \<const0>\;
Dbg_WDATA_29(22) <= \<const0>\;
Dbg_WDATA_29(21) <= \<const0>\;
Dbg_WDATA_29(20) <= \<const0>\;
Dbg_WDATA_29(19) <= \<const0>\;
Dbg_WDATA_29(18) <= \<const0>\;
Dbg_WDATA_29(17) <= \<const0>\;
Dbg_WDATA_29(16) <= \<const0>\;
Dbg_WDATA_29(15) <= \<const0>\;
Dbg_WDATA_29(14) <= \<const0>\;
Dbg_WDATA_29(13) <= \<const0>\;
Dbg_WDATA_29(12) <= \<const0>\;
Dbg_WDATA_29(11) <= \<const0>\;
Dbg_WDATA_29(10) <= \<const0>\;
Dbg_WDATA_29(9) <= \<const0>\;
Dbg_WDATA_29(8) <= \<const0>\;
Dbg_WDATA_29(7) <= \<const0>\;
Dbg_WDATA_29(6) <= \<const0>\;
Dbg_WDATA_29(5) <= \<const0>\;
Dbg_WDATA_29(4) <= \<const0>\;
Dbg_WDATA_29(3) <= \<const0>\;
Dbg_WDATA_29(2) <= \<const0>\;
Dbg_WDATA_29(1) <= \<const0>\;
Dbg_WDATA_29(0) <= \<const0>\;
Dbg_WDATA_3(31) <= \<const0>\;
Dbg_WDATA_3(30) <= \<const0>\;
Dbg_WDATA_3(29) <= \<const0>\;
Dbg_WDATA_3(28) <= \<const0>\;
Dbg_WDATA_3(27) <= \<const0>\;
Dbg_WDATA_3(26) <= \<const0>\;
Dbg_WDATA_3(25) <= \<const0>\;
Dbg_WDATA_3(24) <= \<const0>\;
Dbg_WDATA_3(23) <= \<const0>\;
Dbg_WDATA_3(22) <= \<const0>\;
Dbg_WDATA_3(21) <= \<const0>\;
Dbg_WDATA_3(20) <= \<const0>\;
Dbg_WDATA_3(19) <= \<const0>\;
Dbg_WDATA_3(18) <= \<const0>\;
Dbg_WDATA_3(17) <= \<const0>\;
Dbg_WDATA_3(16) <= \<const0>\;
Dbg_WDATA_3(15) <= \<const0>\;
Dbg_WDATA_3(14) <= \<const0>\;
Dbg_WDATA_3(13) <= \<const0>\;
Dbg_WDATA_3(12) <= \<const0>\;
Dbg_WDATA_3(11) <= \<const0>\;
Dbg_WDATA_3(10) <= \<const0>\;
Dbg_WDATA_3(9) <= \<const0>\;
Dbg_WDATA_3(8) <= \<const0>\;
Dbg_WDATA_3(7) <= \<const0>\;
Dbg_WDATA_3(6) <= \<const0>\;
Dbg_WDATA_3(5) <= \<const0>\;
Dbg_WDATA_3(4) <= \<const0>\;
Dbg_WDATA_3(3) <= \<const0>\;
Dbg_WDATA_3(2) <= \<const0>\;
Dbg_WDATA_3(1) <= \<const0>\;
Dbg_WDATA_3(0) <= \<const0>\;
Dbg_WDATA_30(31) <= \<const0>\;
Dbg_WDATA_30(30) <= \<const0>\;
Dbg_WDATA_30(29) <= \<const0>\;
Dbg_WDATA_30(28) <= \<const0>\;
Dbg_WDATA_30(27) <= \<const0>\;
Dbg_WDATA_30(26) <= \<const0>\;
Dbg_WDATA_30(25) <= \<const0>\;
Dbg_WDATA_30(24) <= \<const0>\;
Dbg_WDATA_30(23) <= \<const0>\;
Dbg_WDATA_30(22) <= \<const0>\;
Dbg_WDATA_30(21) <= \<const0>\;
Dbg_WDATA_30(20) <= \<const0>\;
Dbg_WDATA_30(19) <= \<const0>\;
Dbg_WDATA_30(18) <= \<const0>\;
Dbg_WDATA_30(17) <= \<const0>\;
Dbg_WDATA_30(16) <= \<const0>\;
Dbg_WDATA_30(15) <= \<const0>\;
Dbg_WDATA_30(14) <= \<const0>\;
Dbg_WDATA_30(13) <= \<const0>\;
Dbg_WDATA_30(12) <= \<const0>\;
Dbg_WDATA_30(11) <= \<const0>\;
Dbg_WDATA_30(10) <= \<const0>\;
Dbg_WDATA_30(9) <= \<const0>\;
Dbg_WDATA_30(8) <= \<const0>\;
Dbg_WDATA_30(7) <= \<const0>\;
Dbg_WDATA_30(6) <= \<const0>\;
Dbg_WDATA_30(5) <= \<const0>\;
Dbg_WDATA_30(4) <= \<const0>\;
Dbg_WDATA_30(3) <= \<const0>\;
Dbg_WDATA_30(2) <= \<const0>\;
Dbg_WDATA_30(1) <= \<const0>\;
Dbg_WDATA_30(0) <= \<const0>\;
Dbg_WDATA_31(31) <= \<const0>\;
Dbg_WDATA_31(30) <= \<const0>\;
Dbg_WDATA_31(29) <= \<const0>\;
Dbg_WDATA_31(28) <= \<const0>\;
Dbg_WDATA_31(27) <= \<const0>\;
Dbg_WDATA_31(26) <= \<const0>\;
Dbg_WDATA_31(25) <= \<const0>\;
Dbg_WDATA_31(24) <= \<const0>\;
Dbg_WDATA_31(23) <= \<const0>\;
Dbg_WDATA_31(22) <= \<const0>\;
Dbg_WDATA_31(21) <= \<const0>\;
Dbg_WDATA_31(20) <= \<const0>\;
Dbg_WDATA_31(19) <= \<const0>\;
Dbg_WDATA_31(18) <= \<const0>\;
Dbg_WDATA_31(17) <= \<const0>\;
Dbg_WDATA_31(16) <= \<const0>\;
Dbg_WDATA_31(15) <= \<const0>\;
Dbg_WDATA_31(14) <= \<const0>\;
Dbg_WDATA_31(13) <= \<const0>\;
Dbg_WDATA_31(12) <= \<const0>\;
Dbg_WDATA_31(11) <= \<const0>\;
Dbg_WDATA_31(10) <= \<const0>\;
Dbg_WDATA_31(9) <= \<const0>\;
Dbg_WDATA_31(8) <= \<const0>\;
Dbg_WDATA_31(7) <= \<const0>\;
Dbg_WDATA_31(6) <= \<const0>\;
Dbg_WDATA_31(5) <= \<const0>\;
Dbg_WDATA_31(4) <= \<const0>\;
Dbg_WDATA_31(3) <= \<const0>\;
Dbg_WDATA_31(2) <= \<const0>\;
Dbg_WDATA_31(1) <= \<const0>\;
Dbg_WDATA_31(0) <= \<const0>\;
Dbg_WDATA_4(31) <= \<const0>\;
Dbg_WDATA_4(30) <= \<const0>\;
Dbg_WDATA_4(29) <= \<const0>\;
Dbg_WDATA_4(28) <= \<const0>\;
Dbg_WDATA_4(27) <= \<const0>\;
Dbg_WDATA_4(26) <= \<const0>\;
Dbg_WDATA_4(25) <= \<const0>\;
Dbg_WDATA_4(24) <= \<const0>\;
Dbg_WDATA_4(23) <= \<const0>\;
Dbg_WDATA_4(22) <= \<const0>\;
Dbg_WDATA_4(21) <= \<const0>\;
Dbg_WDATA_4(20) <= \<const0>\;
Dbg_WDATA_4(19) <= \<const0>\;
Dbg_WDATA_4(18) <= \<const0>\;
Dbg_WDATA_4(17) <= \<const0>\;
Dbg_WDATA_4(16) <= \<const0>\;
Dbg_WDATA_4(15) <= \<const0>\;
Dbg_WDATA_4(14) <= \<const0>\;
Dbg_WDATA_4(13) <= \<const0>\;
Dbg_WDATA_4(12) <= \<const0>\;
Dbg_WDATA_4(11) <= \<const0>\;
Dbg_WDATA_4(10) <= \<const0>\;
Dbg_WDATA_4(9) <= \<const0>\;
Dbg_WDATA_4(8) <= \<const0>\;
Dbg_WDATA_4(7) <= \<const0>\;
Dbg_WDATA_4(6) <= \<const0>\;
Dbg_WDATA_4(5) <= \<const0>\;
Dbg_WDATA_4(4) <= \<const0>\;
Dbg_WDATA_4(3) <= \<const0>\;
Dbg_WDATA_4(2) <= \<const0>\;
Dbg_WDATA_4(1) <= \<const0>\;
Dbg_WDATA_4(0) <= \<const0>\;
Dbg_WDATA_5(31) <= \<const0>\;
Dbg_WDATA_5(30) <= \<const0>\;
Dbg_WDATA_5(29) <= \<const0>\;
Dbg_WDATA_5(28) <= \<const0>\;
Dbg_WDATA_5(27) <= \<const0>\;
Dbg_WDATA_5(26) <= \<const0>\;
Dbg_WDATA_5(25) <= \<const0>\;
Dbg_WDATA_5(24) <= \<const0>\;
Dbg_WDATA_5(23) <= \<const0>\;
Dbg_WDATA_5(22) <= \<const0>\;
Dbg_WDATA_5(21) <= \<const0>\;
Dbg_WDATA_5(20) <= \<const0>\;
Dbg_WDATA_5(19) <= \<const0>\;
Dbg_WDATA_5(18) <= \<const0>\;
Dbg_WDATA_5(17) <= \<const0>\;
Dbg_WDATA_5(16) <= \<const0>\;
Dbg_WDATA_5(15) <= \<const0>\;
Dbg_WDATA_5(14) <= \<const0>\;
Dbg_WDATA_5(13) <= \<const0>\;
Dbg_WDATA_5(12) <= \<const0>\;
Dbg_WDATA_5(11) <= \<const0>\;
Dbg_WDATA_5(10) <= \<const0>\;
Dbg_WDATA_5(9) <= \<const0>\;
Dbg_WDATA_5(8) <= \<const0>\;
Dbg_WDATA_5(7) <= \<const0>\;
Dbg_WDATA_5(6) <= \<const0>\;
Dbg_WDATA_5(5) <= \<const0>\;
Dbg_WDATA_5(4) <= \<const0>\;
Dbg_WDATA_5(3) <= \<const0>\;
Dbg_WDATA_5(2) <= \<const0>\;
Dbg_WDATA_5(1) <= \<const0>\;
Dbg_WDATA_5(0) <= \<const0>\;
Dbg_WDATA_6(31) <= \<const0>\;
Dbg_WDATA_6(30) <= \<const0>\;
Dbg_WDATA_6(29) <= \<const0>\;
Dbg_WDATA_6(28) <= \<const0>\;
Dbg_WDATA_6(27) <= \<const0>\;
Dbg_WDATA_6(26) <= \<const0>\;
Dbg_WDATA_6(25) <= \<const0>\;
Dbg_WDATA_6(24) <= \<const0>\;
Dbg_WDATA_6(23) <= \<const0>\;
Dbg_WDATA_6(22) <= \<const0>\;
Dbg_WDATA_6(21) <= \<const0>\;
Dbg_WDATA_6(20) <= \<const0>\;
Dbg_WDATA_6(19) <= \<const0>\;
Dbg_WDATA_6(18) <= \<const0>\;
Dbg_WDATA_6(17) <= \<const0>\;
Dbg_WDATA_6(16) <= \<const0>\;
Dbg_WDATA_6(15) <= \<const0>\;
Dbg_WDATA_6(14) <= \<const0>\;
Dbg_WDATA_6(13) <= \<const0>\;
Dbg_WDATA_6(12) <= \<const0>\;
Dbg_WDATA_6(11) <= \<const0>\;
Dbg_WDATA_6(10) <= \<const0>\;
Dbg_WDATA_6(9) <= \<const0>\;
Dbg_WDATA_6(8) <= \<const0>\;
Dbg_WDATA_6(7) <= \<const0>\;
Dbg_WDATA_6(6) <= \<const0>\;
Dbg_WDATA_6(5) <= \<const0>\;
Dbg_WDATA_6(4) <= \<const0>\;
Dbg_WDATA_6(3) <= \<const0>\;
Dbg_WDATA_6(2) <= \<const0>\;
Dbg_WDATA_6(1) <= \<const0>\;
Dbg_WDATA_6(0) <= \<const0>\;
Dbg_WDATA_7(31) <= \<const0>\;
Dbg_WDATA_7(30) <= \<const0>\;
Dbg_WDATA_7(29) <= \<const0>\;
Dbg_WDATA_7(28) <= \<const0>\;
Dbg_WDATA_7(27) <= \<const0>\;
Dbg_WDATA_7(26) <= \<const0>\;
Dbg_WDATA_7(25) <= \<const0>\;
Dbg_WDATA_7(24) <= \<const0>\;
Dbg_WDATA_7(23) <= \<const0>\;
Dbg_WDATA_7(22) <= \<const0>\;
Dbg_WDATA_7(21) <= \<const0>\;
Dbg_WDATA_7(20) <= \<const0>\;
Dbg_WDATA_7(19) <= \<const0>\;
Dbg_WDATA_7(18) <= \<const0>\;
Dbg_WDATA_7(17) <= \<const0>\;
Dbg_WDATA_7(16) <= \<const0>\;
Dbg_WDATA_7(15) <= \<const0>\;
Dbg_WDATA_7(14) <= \<const0>\;
Dbg_WDATA_7(13) <= \<const0>\;
Dbg_WDATA_7(12) <= \<const0>\;
Dbg_WDATA_7(11) <= \<const0>\;
Dbg_WDATA_7(10) <= \<const0>\;
Dbg_WDATA_7(9) <= \<const0>\;
Dbg_WDATA_7(8) <= \<const0>\;
Dbg_WDATA_7(7) <= \<const0>\;
Dbg_WDATA_7(6) <= \<const0>\;
Dbg_WDATA_7(5) <= \<const0>\;
Dbg_WDATA_7(4) <= \<const0>\;
Dbg_WDATA_7(3) <= \<const0>\;
Dbg_WDATA_7(2) <= \<const0>\;
Dbg_WDATA_7(1) <= \<const0>\;
Dbg_WDATA_7(0) <= \<const0>\;
Dbg_WDATA_8(31) <= \<const0>\;
Dbg_WDATA_8(30) <= \<const0>\;
Dbg_WDATA_8(29) <= \<const0>\;
Dbg_WDATA_8(28) <= \<const0>\;
Dbg_WDATA_8(27) <= \<const0>\;
Dbg_WDATA_8(26) <= \<const0>\;
Dbg_WDATA_8(25) <= \<const0>\;
Dbg_WDATA_8(24) <= \<const0>\;
Dbg_WDATA_8(23) <= \<const0>\;
Dbg_WDATA_8(22) <= \<const0>\;
Dbg_WDATA_8(21) <= \<const0>\;
Dbg_WDATA_8(20) <= \<const0>\;
Dbg_WDATA_8(19) <= \<const0>\;
Dbg_WDATA_8(18) <= \<const0>\;
Dbg_WDATA_8(17) <= \<const0>\;
Dbg_WDATA_8(16) <= \<const0>\;
Dbg_WDATA_8(15) <= \<const0>\;
Dbg_WDATA_8(14) <= \<const0>\;
Dbg_WDATA_8(13) <= \<const0>\;
Dbg_WDATA_8(12) <= \<const0>\;
Dbg_WDATA_8(11) <= \<const0>\;
Dbg_WDATA_8(10) <= \<const0>\;
Dbg_WDATA_8(9) <= \<const0>\;
Dbg_WDATA_8(8) <= \<const0>\;
Dbg_WDATA_8(7) <= \<const0>\;
Dbg_WDATA_8(6) <= \<const0>\;
Dbg_WDATA_8(5) <= \<const0>\;
Dbg_WDATA_8(4) <= \<const0>\;
Dbg_WDATA_8(3) <= \<const0>\;
Dbg_WDATA_8(2) <= \<const0>\;
Dbg_WDATA_8(1) <= \<const0>\;
Dbg_WDATA_8(0) <= \<const0>\;
Dbg_WDATA_9(31) <= \<const0>\;
Dbg_WDATA_9(30) <= \<const0>\;
Dbg_WDATA_9(29) <= \<const0>\;
Dbg_WDATA_9(28) <= \<const0>\;
Dbg_WDATA_9(27) <= \<const0>\;
Dbg_WDATA_9(26) <= \<const0>\;
Dbg_WDATA_9(25) <= \<const0>\;
Dbg_WDATA_9(24) <= \<const0>\;
Dbg_WDATA_9(23) <= \<const0>\;
Dbg_WDATA_9(22) <= \<const0>\;
Dbg_WDATA_9(21) <= \<const0>\;
Dbg_WDATA_9(20) <= \<const0>\;
Dbg_WDATA_9(19) <= \<const0>\;
Dbg_WDATA_9(18) <= \<const0>\;
Dbg_WDATA_9(17) <= \<const0>\;
Dbg_WDATA_9(16) <= \<const0>\;
Dbg_WDATA_9(15) <= \<const0>\;
Dbg_WDATA_9(14) <= \<const0>\;
Dbg_WDATA_9(13) <= \<const0>\;
Dbg_WDATA_9(12) <= \<const0>\;
Dbg_WDATA_9(11) <= \<const0>\;
Dbg_WDATA_9(10) <= \<const0>\;
Dbg_WDATA_9(9) <= \<const0>\;
Dbg_WDATA_9(8) <= \<const0>\;
Dbg_WDATA_9(7) <= \<const0>\;
Dbg_WDATA_9(6) <= \<const0>\;
Dbg_WDATA_9(5) <= \<const0>\;
Dbg_WDATA_9(4) <= \<const0>\;
Dbg_WDATA_9(3) <= \<const0>\;
Dbg_WDATA_9(2) <= \<const0>\;
Dbg_WDATA_9(1) <= \<const0>\;
Dbg_WDATA_9(0) <= \<const0>\;
Dbg_WVALID_0 <= \<const0>\;
Dbg_WVALID_1 <= \<const0>\;
Dbg_WVALID_10 <= \<const0>\;
Dbg_WVALID_11 <= \<const0>\;
Dbg_WVALID_12 <= \<const0>\;
Dbg_WVALID_13 <= \<const0>\;
Dbg_WVALID_14 <= \<const0>\;
Dbg_WVALID_15 <= \<const0>\;
Dbg_WVALID_16 <= \<const0>\;
Dbg_WVALID_17 <= \<const0>\;
Dbg_WVALID_18 <= \<const0>\;
Dbg_WVALID_19 <= \<const0>\;
Dbg_WVALID_2 <= \<const0>\;
Dbg_WVALID_20 <= \<const0>\;
Dbg_WVALID_21 <= \<const0>\;
Dbg_WVALID_22 <= \<const0>\;
Dbg_WVALID_23 <= \<const0>\;
Dbg_WVALID_24 <= \<const0>\;
Dbg_WVALID_25 <= \<const0>\;
Dbg_WVALID_26 <= \<const0>\;
Dbg_WVALID_27 <= \<const0>\;
Dbg_WVALID_28 <= \<const0>\;
Dbg_WVALID_29 <= \<const0>\;
Dbg_WVALID_3 <= \<const0>\;
Dbg_WVALID_30 <= \<const0>\;
Dbg_WVALID_31 <= \<const0>\;
Dbg_WVALID_4 <= \<const0>\;
Dbg_WVALID_5 <= \<const0>\;
Dbg_WVALID_6 <= \<const0>\;
Dbg_WVALID_7 <= \<const0>\;
Dbg_WVALID_8 <= \<const0>\;
Dbg_WVALID_9 <= \<const0>\;
Ext_BRK <= \<const0>\;
Ext_JTAG_CAPTURE <= \^ext_jtag_capture\;
Ext_JTAG_DRCK <= \^dbg_clk_31\;
Ext_JTAG_SHIFT <= \^ext_jtag_shift\;
Ext_JTAG_TDI <= \^ext_jtag_tdi\;
Ext_JTAG_UPDATE <= \^dbg_update_31\;
Interrupt <= \<const0>\;
LMB_Addr_Strobe_0 <= \<const0>\;
LMB_Addr_Strobe_1 <= \<const0>\;
LMB_Addr_Strobe_10 <= \<const0>\;
LMB_Addr_Strobe_11 <= \<const0>\;
LMB_Addr_Strobe_12 <= \<const0>\;
LMB_Addr_Strobe_13 <= \<const0>\;
LMB_Addr_Strobe_14 <= \<const0>\;
LMB_Addr_Strobe_15 <= \<const0>\;
LMB_Addr_Strobe_16 <= \<const0>\;
LMB_Addr_Strobe_17 <= \<const0>\;
LMB_Addr_Strobe_18 <= \<const0>\;
LMB_Addr_Strobe_19 <= \<const0>\;
LMB_Addr_Strobe_2 <= \<const0>\;
LMB_Addr_Strobe_20 <= \<const0>\;
LMB_Addr_Strobe_21 <= \<const0>\;
LMB_Addr_Strobe_22 <= \<const0>\;
LMB_Addr_Strobe_23 <= \<const0>\;
LMB_Addr_Strobe_24 <= \<const0>\;
LMB_Addr_Strobe_25 <= \<const0>\;
LMB_Addr_Strobe_26 <= \<const0>\;
LMB_Addr_Strobe_27 <= \<const0>\;
LMB_Addr_Strobe_28 <= \<const0>\;
LMB_Addr_Strobe_29 <= \<const0>\;
LMB_Addr_Strobe_3 <= \<const0>\;
LMB_Addr_Strobe_30 <= \<const0>\;
LMB_Addr_Strobe_31 <= \<const0>\;
LMB_Addr_Strobe_4 <= \<const0>\;
LMB_Addr_Strobe_5 <= \<const0>\;
LMB_Addr_Strobe_6 <= \<const0>\;
LMB_Addr_Strobe_7 <= \<const0>\;
LMB_Addr_Strobe_8 <= \<const0>\;
LMB_Addr_Strobe_9 <= \<const0>\;
LMB_Byte_Enable_0(0) <= \<const0>\;
LMB_Byte_Enable_0(1) <= \<const0>\;
LMB_Byte_Enable_0(2) <= \<const0>\;
LMB_Byte_Enable_0(3) <= \<const0>\;
LMB_Byte_Enable_1(0) <= \<const0>\;
LMB_Byte_Enable_1(1) <= \<const0>\;
LMB_Byte_Enable_1(2) <= \<const0>\;
LMB_Byte_Enable_1(3) <= \<const0>\;
LMB_Byte_Enable_10(0) <= \<const0>\;
LMB_Byte_Enable_10(1) <= \<const0>\;
LMB_Byte_Enable_10(2) <= \<const0>\;
LMB_Byte_Enable_10(3) <= \<const0>\;
LMB_Byte_Enable_11(0) <= \<const0>\;
LMB_Byte_Enable_11(1) <= \<const0>\;
LMB_Byte_Enable_11(2) <= \<const0>\;
LMB_Byte_Enable_11(3) <= \<const0>\;
LMB_Byte_Enable_12(0) <= \<const0>\;
LMB_Byte_Enable_12(1) <= \<const0>\;
LMB_Byte_Enable_12(2) <= \<const0>\;
LMB_Byte_Enable_12(3) <= \<const0>\;
LMB_Byte_Enable_13(0) <= \<const0>\;
LMB_Byte_Enable_13(1) <= \<const0>\;
LMB_Byte_Enable_13(2) <= \<const0>\;
LMB_Byte_Enable_13(3) <= \<const0>\;
LMB_Byte_Enable_14(0) <= \<const0>\;
LMB_Byte_Enable_14(1) <= \<const0>\;
LMB_Byte_Enable_14(2) <= \<const0>\;
LMB_Byte_Enable_14(3) <= \<const0>\;
LMB_Byte_Enable_15(0) <= \<const0>\;
LMB_Byte_Enable_15(1) <= \<const0>\;
LMB_Byte_Enable_15(2) <= \<const0>\;
LMB_Byte_Enable_15(3) <= \<const0>\;
LMB_Byte_Enable_16(0) <= \<const0>\;
LMB_Byte_Enable_16(1) <= \<const0>\;
LMB_Byte_Enable_16(2) <= \<const0>\;
LMB_Byte_Enable_16(3) <= \<const0>\;
LMB_Byte_Enable_17(0) <= \<const0>\;
LMB_Byte_Enable_17(1) <= \<const0>\;
LMB_Byte_Enable_17(2) <= \<const0>\;
LMB_Byte_Enable_17(3) <= \<const0>\;
LMB_Byte_Enable_18(0) <= \<const0>\;
LMB_Byte_Enable_18(1) <= \<const0>\;
LMB_Byte_Enable_18(2) <= \<const0>\;
LMB_Byte_Enable_18(3) <= \<const0>\;
LMB_Byte_Enable_19(0) <= \<const0>\;
LMB_Byte_Enable_19(1) <= \<const0>\;
LMB_Byte_Enable_19(2) <= \<const0>\;
LMB_Byte_Enable_19(3) <= \<const0>\;
LMB_Byte_Enable_2(0) <= \<const0>\;
LMB_Byte_Enable_2(1) <= \<const0>\;
LMB_Byte_Enable_2(2) <= \<const0>\;
LMB_Byte_Enable_2(3) <= \<const0>\;
LMB_Byte_Enable_20(0) <= \<const0>\;
LMB_Byte_Enable_20(1) <= \<const0>\;
LMB_Byte_Enable_20(2) <= \<const0>\;
LMB_Byte_Enable_20(3) <= \<const0>\;
LMB_Byte_Enable_21(0) <= \<const0>\;
LMB_Byte_Enable_21(1) <= \<const0>\;
LMB_Byte_Enable_21(2) <= \<const0>\;
LMB_Byte_Enable_21(3) <= \<const0>\;
LMB_Byte_Enable_22(0) <= \<const0>\;
LMB_Byte_Enable_22(1) <= \<const0>\;
LMB_Byte_Enable_22(2) <= \<const0>\;
LMB_Byte_Enable_22(3) <= \<const0>\;
LMB_Byte_Enable_23(0) <= \<const0>\;
LMB_Byte_Enable_23(1) <= \<const0>\;
LMB_Byte_Enable_23(2) <= \<const0>\;
LMB_Byte_Enable_23(3) <= \<const0>\;
LMB_Byte_Enable_24(0) <= \<const0>\;
LMB_Byte_Enable_24(1) <= \<const0>\;
LMB_Byte_Enable_24(2) <= \<const0>\;
LMB_Byte_Enable_24(3) <= \<const0>\;
LMB_Byte_Enable_25(0) <= \<const0>\;
LMB_Byte_Enable_25(1) <= \<const0>\;
LMB_Byte_Enable_25(2) <= \<const0>\;
LMB_Byte_Enable_25(3) <= \<const0>\;
LMB_Byte_Enable_26(0) <= \<const0>\;
LMB_Byte_Enable_26(1) <= \<const0>\;
LMB_Byte_Enable_26(2) <= \<const0>\;
LMB_Byte_Enable_26(3) <= \<const0>\;
LMB_Byte_Enable_27(0) <= \<const0>\;
LMB_Byte_Enable_27(1) <= \<const0>\;
LMB_Byte_Enable_27(2) <= \<const0>\;
LMB_Byte_Enable_27(3) <= \<const0>\;
LMB_Byte_Enable_28(0) <= \<const0>\;
LMB_Byte_Enable_28(1) <= \<const0>\;
LMB_Byte_Enable_28(2) <= \<const0>\;
LMB_Byte_Enable_28(3) <= \<const0>\;
LMB_Byte_Enable_29(0) <= \<const0>\;
LMB_Byte_Enable_29(1) <= \<const0>\;
LMB_Byte_Enable_29(2) <= \<const0>\;
LMB_Byte_Enable_29(3) <= \<const0>\;
LMB_Byte_Enable_3(0) <= \<const0>\;
LMB_Byte_Enable_3(1) <= \<const0>\;
LMB_Byte_Enable_3(2) <= \<const0>\;
LMB_Byte_Enable_3(3) <= \<const0>\;
LMB_Byte_Enable_30(0) <= \<const0>\;
LMB_Byte_Enable_30(1) <= \<const0>\;
LMB_Byte_Enable_30(2) <= \<const0>\;
LMB_Byte_Enable_30(3) <= \<const0>\;
LMB_Byte_Enable_31(0) <= \<const0>\;
LMB_Byte_Enable_31(1) <= \<const0>\;
LMB_Byte_Enable_31(2) <= \<const0>\;
LMB_Byte_Enable_31(3) <= \<const0>\;
LMB_Byte_Enable_4(0) <= \<const0>\;
LMB_Byte_Enable_4(1) <= \<const0>\;
LMB_Byte_Enable_4(2) <= \<const0>\;
LMB_Byte_Enable_4(3) <= \<const0>\;
LMB_Byte_Enable_5(0) <= \<const0>\;
LMB_Byte_Enable_5(1) <= \<const0>\;
LMB_Byte_Enable_5(2) <= \<const0>\;
LMB_Byte_Enable_5(3) <= \<const0>\;
LMB_Byte_Enable_6(0) <= \<const0>\;
LMB_Byte_Enable_6(1) <= \<const0>\;
LMB_Byte_Enable_6(2) <= \<const0>\;
LMB_Byte_Enable_6(3) <= \<const0>\;
LMB_Byte_Enable_7(0) <= \<const0>\;
LMB_Byte_Enable_7(1) <= \<const0>\;
LMB_Byte_Enable_7(2) <= \<const0>\;
LMB_Byte_Enable_7(3) <= \<const0>\;
LMB_Byte_Enable_8(0) <= \<const0>\;
LMB_Byte_Enable_8(1) <= \<const0>\;
LMB_Byte_Enable_8(2) <= \<const0>\;
LMB_Byte_Enable_8(3) <= \<const0>\;
LMB_Byte_Enable_9(0) <= \<const0>\;
LMB_Byte_Enable_9(1) <= \<const0>\;
LMB_Byte_Enable_9(2) <= \<const0>\;
LMB_Byte_Enable_9(3) <= \<const0>\;
LMB_Data_Addr_0(0) <= \<const0>\;
LMB_Data_Addr_0(1) <= \<const0>\;
LMB_Data_Addr_0(2) <= \<const0>\;
LMB_Data_Addr_0(3) <= \<const0>\;
LMB_Data_Addr_0(4) <= \<const0>\;
LMB_Data_Addr_0(5) <= \<const0>\;
LMB_Data_Addr_0(6) <= \<const0>\;
LMB_Data_Addr_0(7) <= \<const0>\;
LMB_Data_Addr_0(8) <= \<const0>\;
LMB_Data_Addr_0(9) <= \<const0>\;
LMB_Data_Addr_0(10) <= \<const0>\;
LMB_Data_Addr_0(11) <= \<const0>\;
LMB_Data_Addr_0(12) <= \<const0>\;
LMB_Data_Addr_0(13) <= \<const0>\;
LMB_Data_Addr_0(14) <= \<const0>\;
LMB_Data_Addr_0(15) <= \<const0>\;
LMB_Data_Addr_0(16) <= \<const0>\;
LMB_Data_Addr_0(17) <= \<const0>\;
LMB_Data_Addr_0(18) <= \<const0>\;
LMB_Data_Addr_0(19) <= \<const0>\;
LMB_Data_Addr_0(20) <= \<const0>\;
LMB_Data_Addr_0(21) <= \<const0>\;
LMB_Data_Addr_0(22) <= \<const0>\;
LMB_Data_Addr_0(23) <= \<const0>\;
LMB_Data_Addr_0(24) <= \<const0>\;
LMB_Data_Addr_0(25) <= \<const0>\;
LMB_Data_Addr_0(26) <= \<const0>\;
LMB_Data_Addr_0(27) <= \<const0>\;
LMB_Data_Addr_0(28) <= \<const0>\;
LMB_Data_Addr_0(29) <= \<const0>\;
LMB_Data_Addr_0(30) <= \<const0>\;
LMB_Data_Addr_0(31) <= \<const0>\;
LMB_Data_Addr_1(0) <= \<const0>\;
LMB_Data_Addr_1(1) <= \<const0>\;
LMB_Data_Addr_1(2) <= \<const0>\;
LMB_Data_Addr_1(3) <= \<const0>\;
LMB_Data_Addr_1(4) <= \<const0>\;
LMB_Data_Addr_1(5) <= \<const0>\;
LMB_Data_Addr_1(6) <= \<const0>\;
LMB_Data_Addr_1(7) <= \<const0>\;
LMB_Data_Addr_1(8) <= \<const0>\;
LMB_Data_Addr_1(9) <= \<const0>\;
LMB_Data_Addr_1(10) <= \<const0>\;
LMB_Data_Addr_1(11) <= \<const0>\;
LMB_Data_Addr_1(12) <= \<const0>\;
LMB_Data_Addr_1(13) <= \<const0>\;
LMB_Data_Addr_1(14) <= \<const0>\;
LMB_Data_Addr_1(15) <= \<const0>\;
LMB_Data_Addr_1(16) <= \<const0>\;
LMB_Data_Addr_1(17) <= \<const0>\;
LMB_Data_Addr_1(18) <= \<const0>\;
LMB_Data_Addr_1(19) <= \<const0>\;
LMB_Data_Addr_1(20) <= \<const0>\;
LMB_Data_Addr_1(21) <= \<const0>\;
LMB_Data_Addr_1(22) <= \<const0>\;
LMB_Data_Addr_1(23) <= \<const0>\;
LMB_Data_Addr_1(24) <= \<const0>\;
LMB_Data_Addr_1(25) <= \<const0>\;
LMB_Data_Addr_1(26) <= \<const0>\;
LMB_Data_Addr_1(27) <= \<const0>\;
LMB_Data_Addr_1(28) <= \<const0>\;
LMB_Data_Addr_1(29) <= \<const0>\;
LMB_Data_Addr_1(30) <= \<const0>\;
LMB_Data_Addr_1(31) <= \<const0>\;
LMB_Data_Addr_10(0) <= \<const0>\;
LMB_Data_Addr_10(1) <= \<const0>\;
LMB_Data_Addr_10(2) <= \<const0>\;
LMB_Data_Addr_10(3) <= \<const0>\;
LMB_Data_Addr_10(4) <= \<const0>\;
LMB_Data_Addr_10(5) <= \<const0>\;
LMB_Data_Addr_10(6) <= \<const0>\;
LMB_Data_Addr_10(7) <= \<const0>\;
LMB_Data_Addr_10(8) <= \<const0>\;
LMB_Data_Addr_10(9) <= \<const0>\;
LMB_Data_Addr_10(10) <= \<const0>\;
LMB_Data_Addr_10(11) <= \<const0>\;
LMB_Data_Addr_10(12) <= \<const0>\;
LMB_Data_Addr_10(13) <= \<const0>\;
LMB_Data_Addr_10(14) <= \<const0>\;
LMB_Data_Addr_10(15) <= \<const0>\;
LMB_Data_Addr_10(16) <= \<const0>\;
LMB_Data_Addr_10(17) <= \<const0>\;
LMB_Data_Addr_10(18) <= \<const0>\;
LMB_Data_Addr_10(19) <= \<const0>\;
LMB_Data_Addr_10(20) <= \<const0>\;
LMB_Data_Addr_10(21) <= \<const0>\;
LMB_Data_Addr_10(22) <= \<const0>\;
LMB_Data_Addr_10(23) <= \<const0>\;
LMB_Data_Addr_10(24) <= \<const0>\;
LMB_Data_Addr_10(25) <= \<const0>\;
LMB_Data_Addr_10(26) <= \<const0>\;
LMB_Data_Addr_10(27) <= \<const0>\;
LMB_Data_Addr_10(28) <= \<const0>\;
LMB_Data_Addr_10(29) <= \<const0>\;
LMB_Data_Addr_10(30) <= \<const0>\;
LMB_Data_Addr_10(31) <= \<const0>\;
LMB_Data_Addr_11(0) <= \<const0>\;
LMB_Data_Addr_11(1) <= \<const0>\;
LMB_Data_Addr_11(2) <= \<const0>\;
LMB_Data_Addr_11(3) <= \<const0>\;
LMB_Data_Addr_11(4) <= \<const0>\;
LMB_Data_Addr_11(5) <= \<const0>\;
LMB_Data_Addr_11(6) <= \<const0>\;
LMB_Data_Addr_11(7) <= \<const0>\;
LMB_Data_Addr_11(8) <= \<const0>\;
LMB_Data_Addr_11(9) <= \<const0>\;
LMB_Data_Addr_11(10) <= \<const0>\;
LMB_Data_Addr_11(11) <= \<const0>\;
LMB_Data_Addr_11(12) <= \<const0>\;
LMB_Data_Addr_11(13) <= \<const0>\;
LMB_Data_Addr_11(14) <= \<const0>\;
LMB_Data_Addr_11(15) <= \<const0>\;
LMB_Data_Addr_11(16) <= \<const0>\;
LMB_Data_Addr_11(17) <= \<const0>\;
LMB_Data_Addr_11(18) <= \<const0>\;
LMB_Data_Addr_11(19) <= \<const0>\;
LMB_Data_Addr_11(20) <= \<const0>\;
LMB_Data_Addr_11(21) <= \<const0>\;
LMB_Data_Addr_11(22) <= \<const0>\;
LMB_Data_Addr_11(23) <= \<const0>\;
LMB_Data_Addr_11(24) <= \<const0>\;
LMB_Data_Addr_11(25) <= \<const0>\;
LMB_Data_Addr_11(26) <= \<const0>\;
LMB_Data_Addr_11(27) <= \<const0>\;
LMB_Data_Addr_11(28) <= \<const0>\;
LMB_Data_Addr_11(29) <= \<const0>\;
LMB_Data_Addr_11(30) <= \<const0>\;
LMB_Data_Addr_11(31) <= \<const0>\;
LMB_Data_Addr_12(0) <= \<const0>\;
LMB_Data_Addr_12(1) <= \<const0>\;
LMB_Data_Addr_12(2) <= \<const0>\;
LMB_Data_Addr_12(3) <= \<const0>\;
LMB_Data_Addr_12(4) <= \<const0>\;
LMB_Data_Addr_12(5) <= \<const0>\;
LMB_Data_Addr_12(6) <= \<const0>\;
LMB_Data_Addr_12(7) <= \<const0>\;
LMB_Data_Addr_12(8) <= \<const0>\;
LMB_Data_Addr_12(9) <= \<const0>\;
LMB_Data_Addr_12(10) <= \<const0>\;
LMB_Data_Addr_12(11) <= \<const0>\;
LMB_Data_Addr_12(12) <= \<const0>\;
LMB_Data_Addr_12(13) <= \<const0>\;
LMB_Data_Addr_12(14) <= \<const0>\;
LMB_Data_Addr_12(15) <= \<const0>\;
LMB_Data_Addr_12(16) <= \<const0>\;
LMB_Data_Addr_12(17) <= \<const0>\;
LMB_Data_Addr_12(18) <= \<const0>\;
LMB_Data_Addr_12(19) <= \<const0>\;
LMB_Data_Addr_12(20) <= \<const0>\;
LMB_Data_Addr_12(21) <= \<const0>\;
LMB_Data_Addr_12(22) <= \<const0>\;
LMB_Data_Addr_12(23) <= \<const0>\;
LMB_Data_Addr_12(24) <= \<const0>\;
LMB_Data_Addr_12(25) <= \<const0>\;
LMB_Data_Addr_12(26) <= \<const0>\;
LMB_Data_Addr_12(27) <= \<const0>\;
LMB_Data_Addr_12(28) <= \<const0>\;
LMB_Data_Addr_12(29) <= \<const0>\;
LMB_Data_Addr_12(30) <= \<const0>\;
LMB_Data_Addr_12(31) <= \<const0>\;
LMB_Data_Addr_13(0) <= \<const0>\;
LMB_Data_Addr_13(1) <= \<const0>\;
LMB_Data_Addr_13(2) <= \<const0>\;
LMB_Data_Addr_13(3) <= \<const0>\;
LMB_Data_Addr_13(4) <= \<const0>\;
LMB_Data_Addr_13(5) <= \<const0>\;
LMB_Data_Addr_13(6) <= \<const0>\;
LMB_Data_Addr_13(7) <= \<const0>\;
LMB_Data_Addr_13(8) <= \<const0>\;
LMB_Data_Addr_13(9) <= \<const0>\;
LMB_Data_Addr_13(10) <= \<const0>\;
LMB_Data_Addr_13(11) <= \<const0>\;
LMB_Data_Addr_13(12) <= \<const0>\;
LMB_Data_Addr_13(13) <= \<const0>\;
LMB_Data_Addr_13(14) <= \<const0>\;
LMB_Data_Addr_13(15) <= \<const0>\;
LMB_Data_Addr_13(16) <= \<const0>\;
LMB_Data_Addr_13(17) <= \<const0>\;
LMB_Data_Addr_13(18) <= \<const0>\;
LMB_Data_Addr_13(19) <= \<const0>\;
LMB_Data_Addr_13(20) <= \<const0>\;
LMB_Data_Addr_13(21) <= \<const0>\;
LMB_Data_Addr_13(22) <= \<const0>\;
LMB_Data_Addr_13(23) <= \<const0>\;
LMB_Data_Addr_13(24) <= \<const0>\;
LMB_Data_Addr_13(25) <= \<const0>\;
LMB_Data_Addr_13(26) <= \<const0>\;
LMB_Data_Addr_13(27) <= \<const0>\;
LMB_Data_Addr_13(28) <= \<const0>\;
LMB_Data_Addr_13(29) <= \<const0>\;
LMB_Data_Addr_13(30) <= \<const0>\;
LMB_Data_Addr_13(31) <= \<const0>\;
LMB_Data_Addr_14(0) <= \<const0>\;
LMB_Data_Addr_14(1) <= \<const0>\;
LMB_Data_Addr_14(2) <= \<const0>\;
LMB_Data_Addr_14(3) <= \<const0>\;
LMB_Data_Addr_14(4) <= \<const0>\;
LMB_Data_Addr_14(5) <= \<const0>\;
LMB_Data_Addr_14(6) <= \<const0>\;
LMB_Data_Addr_14(7) <= \<const0>\;
LMB_Data_Addr_14(8) <= \<const0>\;
LMB_Data_Addr_14(9) <= \<const0>\;
LMB_Data_Addr_14(10) <= \<const0>\;
LMB_Data_Addr_14(11) <= \<const0>\;
LMB_Data_Addr_14(12) <= \<const0>\;
LMB_Data_Addr_14(13) <= \<const0>\;
LMB_Data_Addr_14(14) <= \<const0>\;
LMB_Data_Addr_14(15) <= \<const0>\;
LMB_Data_Addr_14(16) <= \<const0>\;
LMB_Data_Addr_14(17) <= \<const0>\;
LMB_Data_Addr_14(18) <= \<const0>\;
LMB_Data_Addr_14(19) <= \<const0>\;
LMB_Data_Addr_14(20) <= \<const0>\;
LMB_Data_Addr_14(21) <= \<const0>\;
LMB_Data_Addr_14(22) <= \<const0>\;
LMB_Data_Addr_14(23) <= \<const0>\;
LMB_Data_Addr_14(24) <= \<const0>\;
LMB_Data_Addr_14(25) <= \<const0>\;
LMB_Data_Addr_14(26) <= \<const0>\;
LMB_Data_Addr_14(27) <= \<const0>\;
LMB_Data_Addr_14(28) <= \<const0>\;
LMB_Data_Addr_14(29) <= \<const0>\;
LMB_Data_Addr_14(30) <= \<const0>\;
LMB_Data_Addr_14(31) <= \<const0>\;
LMB_Data_Addr_15(0) <= \<const0>\;
LMB_Data_Addr_15(1) <= \<const0>\;
LMB_Data_Addr_15(2) <= \<const0>\;
LMB_Data_Addr_15(3) <= \<const0>\;
LMB_Data_Addr_15(4) <= \<const0>\;
LMB_Data_Addr_15(5) <= \<const0>\;
LMB_Data_Addr_15(6) <= \<const0>\;
LMB_Data_Addr_15(7) <= \<const0>\;
LMB_Data_Addr_15(8) <= \<const0>\;
LMB_Data_Addr_15(9) <= \<const0>\;
LMB_Data_Addr_15(10) <= \<const0>\;
LMB_Data_Addr_15(11) <= \<const0>\;
LMB_Data_Addr_15(12) <= \<const0>\;
LMB_Data_Addr_15(13) <= \<const0>\;
LMB_Data_Addr_15(14) <= \<const0>\;
LMB_Data_Addr_15(15) <= \<const0>\;
LMB_Data_Addr_15(16) <= \<const0>\;
LMB_Data_Addr_15(17) <= \<const0>\;
LMB_Data_Addr_15(18) <= \<const0>\;
LMB_Data_Addr_15(19) <= \<const0>\;
LMB_Data_Addr_15(20) <= \<const0>\;
LMB_Data_Addr_15(21) <= \<const0>\;
LMB_Data_Addr_15(22) <= \<const0>\;
LMB_Data_Addr_15(23) <= \<const0>\;
LMB_Data_Addr_15(24) <= \<const0>\;
LMB_Data_Addr_15(25) <= \<const0>\;
LMB_Data_Addr_15(26) <= \<const0>\;
LMB_Data_Addr_15(27) <= \<const0>\;
LMB_Data_Addr_15(28) <= \<const0>\;
LMB_Data_Addr_15(29) <= \<const0>\;
LMB_Data_Addr_15(30) <= \<const0>\;
LMB_Data_Addr_15(31) <= \<const0>\;
LMB_Data_Addr_16(0) <= \<const0>\;
LMB_Data_Addr_16(1) <= \<const0>\;
LMB_Data_Addr_16(2) <= \<const0>\;
LMB_Data_Addr_16(3) <= \<const0>\;
LMB_Data_Addr_16(4) <= \<const0>\;
LMB_Data_Addr_16(5) <= \<const0>\;
LMB_Data_Addr_16(6) <= \<const0>\;
LMB_Data_Addr_16(7) <= \<const0>\;
LMB_Data_Addr_16(8) <= \<const0>\;
LMB_Data_Addr_16(9) <= \<const0>\;
LMB_Data_Addr_16(10) <= \<const0>\;
LMB_Data_Addr_16(11) <= \<const0>\;
LMB_Data_Addr_16(12) <= \<const0>\;
LMB_Data_Addr_16(13) <= \<const0>\;
LMB_Data_Addr_16(14) <= \<const0>\;
LMB_Data_Addr_16(15) <= \<const0>\;
LMB_Data_Addr_16(16) <= \<const0>\;
LMB_Data_Addr_16(17) <= \<const0>\;
LMB_Data_Addr_16(18) <= \<const0>\;
LMB_Data_Addr_16(19) <= \<const0>\;
LMB_Data_Addr_16(20) <= \<const0>\;
LMB_Data_Addr_16(21) <= \<const0>\;
LMB_Data_Addr_16(22) <= \<const0>\;
LMB_Data_Addr_16(23) <= \<const0>\;
LMB_Data_Addr_16(24) <= \<const0>\;
LMB_Data_Addr_16(25) <= \<const0>\;
LMB_Data_Addr_16(26) <= \<const0>\;
LMB_Data_Addr_16(27) <= \<const0>\;
LMB_Data_Addr_16(28) <= \<const0>\;
LMB_Data_Addr_16(29) <= \<const0>\;
LMB_Data_Addr_16(30) <= \<const0>\;
LMB_Data_Addr_16(31) <= \<const0>\;
LMB_Data_Addr_17(0) <= \<const0>\;
LMB_Data_Addr_17(1) <= \<const0>\;
LMB_Data_Addr_17(2) <= \<const0>\;
LMB_Data_Addr_17(3) <= \<const0>\;
LMB_Data_Addr_17(4) <= \<const0>\;
LMB_Data_Addr_17(5) <= \<const0>\;
LMB_Data_Addr_17(6) <= \<const0>\;
LMB_Data_Addr_17(7) <= \<const0>\;
LMB_Data_Addr_17(8) <= \<const0>\;
LMB_Data_Addr_17(9) <= \<const0>\;
LMB_Data_Addr_17(10) <= \<const0>\;
LMB_Data_Addr_17(11) <= \<const0>\;
LMB_Data_Addr_17(12) <= \<const0>\;
LMB_Data_Addr_17(13) <= \<const0>\;
LMB_Data_Addr_17(14) <= \<const0>\;
LMB_Data_Addr_17(15) <= \<const0>\;
LMB_Data_Addr_17(16) <= \<const0>\;
LMB_Data_Addr_17(17) <= \<const0>\;
LMB_Data_Addr_17(18) <= \<const0>\;
LMB_Data_Addr_17(19) <= \<const0>\;
LMB_Data_Addr_17(20) <= \<const0>\;
LMB_Data_Addr_17(21) <= \<const0>\;
LMB_Data_Addr_17(22) <= \<const0>\;
LMB_Data_Addr_17(23) <= \<const0>\;
LMB_Data_Addr_17(24) <= \<const0>\;
LMB_Data_Addr_17(25) <= \<const0>\;
LMB_Data_Addr_17(26) <= \<const0>\;
LMB_Data_Addr_17(27) <= \<const0>\;
LMB_Data_Addr_17(28) <= \<const0>\;
LMB_Data_Addr_17(29) <= \<const0>\;
LMB_Data_Addr_17(30) <= \<const0>\;
LMB_Data_Addr_17(31) <= \<const0>\;
LMB_Data_Addr_18(0) <= \<const0>\;
LMB_Data_Addr_18(1) <= \<const0>\;
LMB_Data_Addr_18(2) <= \<const0>\;
LMB_Data_Addr_18(3) <= \<const0>\;
LMB_Data_Addr_18(4) <= \<const0>\;
LMB_Data_Addr_18(5) <= \<const0>\;
LMB_Data_Addr_18(6) <= \<const0>\;
LMB_Data_Addr_18(7) <= \<const0>\;
LMB_Data_Addr_18(8) <= \<const0>\;
LMB_Data_Addr_18(9) <= \<const0>\;
LMB_Data_Addr_18(10) <= \<const0>\;
LMB_Data_Addr_18(11) <= \<const0>\;
LMB_Data_Addr_18(12) <= \<const0>\;
LMB_Data_Addr_18(13) <= \<const0>\;
LMB_Data_Addr_18(14) <= \<const0>\;
LMB_Data_Addr_18(15) <= \<const0>\;
LMB_Data_Addr_18(16) <= \<const0>\;
LMB_Data_Addr_18(17) <= \<const0>\;
LMB_Data_Addr_18(18) <= \<const0>\;
LMB_Data_Addr_18(19) <= \<const0>\;
LMB_Data_Addr_18(20) <= \<const0>\;
LMB_Data_Addr_18(21) <= \<const0>\;
LMB_Data_Addr_18(22) <= \<const0>\;
LMB_Data_Addr_18(23) <= \<const0>\;
LMB_Data_Addr_18(24) <= \<const0>\;
LMB_Data_Addr_18(25) <= \<const0>\;
LMB_Data_Addr_18(26) <= \<const0>\;
LMB_Data_Addr_18(27) <= \<const0>\;
LMB_Data_Addr_18(28) <= \<const0>\;
LMB_Data_Addr_18(29) <= \<const0>\;
LMB_Data_Addr_18(30) <= \<const0>\;
LMB_Data_Addr_18(31) <= \<const0>\;
LMB_Data_Addr_19(0) <= \<const0>\;
LMB_Data_Addr_19(1) <= \<const0>\;
LMB_Data_Addr_19(2) <= \<const0>\;
LMB_Data_Addr_19(3) <= \<const0>\;
LMB_Data_Addr_19(4) <= \<const0>\;
LMB_Data_Addr_19(5) <= \<const0>\;
LMB_Data_Addr_19(6) <= \<const0>\;
LMB_Data_Addr_19(7) <= \<const0>\;
LMB_Data_Addr_19(8) <= \<const0>\;
LMB_Data_Addr_19(9) <= \<const0>\;
LMB_Data_Addr_19(10) <= \<const0>\;
LMB_Data_Addr_19(11) <= \<const0>\;
LMB_Data_Addr_19(12) <= \<const0>\;
LMB_Data_Addr_19(13) <= \<const0>\;
LMB_Data_Addr_19(14) <= \<const0>\;
LMB_Data_Addr_19(15) <= \<const0>\;
LMB_Data_Addr_19(16) <= \<const0>\;
LMB_Data_Addr_19(17) <= \<const0>\;
LMB_Data_Addr_19(18) <= \<const0>\;
LMB_Data_Addr_19(19) <= \<const0>\;
LMB_Data_Addr_19(20) <= \<const0>\;
LMB_Data_Addr_19(21) <= \<const0>\;
LMB_Data_Addr_19(22) <= \<const0>\;
LMB_Data_Addr_19(23) <= \<const0>\;
LMB_Data_Addr_19(24) <= \<const0>\;
LMB_Data_Addr_19(25) <= \<const0>\;
LMB_Data_Addr_19(26) <= \<const0>\;
LMB_Data_Addr_19(27) <= \<const0>\;
LMB_Data_Addr_19(28) <= \<const0>\;
LMB_Data_Addr_19(29) <= \<const0>\;
LMB_Data_Addr_19(30) <= \<const0>\;
LMB_Data_Addr_19(31) <= \<const0>\;
LMB_Data_Addr_2(0) <= \<const0>\;
LMB_Data_Addr_2(1) <= \<const0>\;
LMB_Data_Addr_2(2) <= \<const0>\;
LMB_Data_Addr_2(3) <= \<const0>\;
LMB_Data_Addr_2(4) <= \<const0>\;
LMB_Data_Addr_2(5) <= \<const0>\;
LMB_Data_Addr_2(6) <= \<const0>\;
LMB_Data_Addr_2(7) <= \<const0>\;
LMB_Data_Addr_2(8) <= \<const0>\;
LMB_Data_Addr_2(9) <= \<const0>\;
LMB_Data_Addr_2(10) <= \<const0>\;
LMB_Data_Addr_2(11) <= \<const0>\;
LMB_Data_Addr_2(12) <= \<const0>\;
LMB_Data_Addr_2(13) <= \<const0>\;
LMB_Data_Addr_2(14) <= \<const0>\;
LMB_Data_Addr_2(15) <= \<const0>\;
LMB_Data_Addr_2(16) <= \<const0>\;
LMB_Data_Addr_2(17) <= \<const0>\;
LMB_Data_Addr_2(18) <= \<const0>\;
LMB_Data_Addr_2(19) <= \<const0>\;
LMB_Data_Addr_2(20) <= \<const0>\;
LMB_Data_Addr_2(21) <= \<const0>\;
LMB_Data_Addr_2(22) <= \<const0>\;
LMB_Data_Addr_2(23) <= \<const0>\;
LMB_Data_Addr_2(24) <= \<const0>\;
LMB_Data_Addr_2(25) <= \<const0>\;
LMB_Data_Addr_2(26) <= \<const0>\;
LMB_Data_Addr_2(27) <= \<const0>\;
LMB_Data_Addr_2(28) <= \<const0>\;
LMB_Data_Addr_2(29) <= \<const0>\;
LMB_Data_Addr_2(30) <= \<const0>\;
LMB_Data_Addr_2(31) <= \<const0>\;
LMB_Data_Addr_20(0) <= \<const0>\;
LMB_Data_Addr_20(1) <= \<const0>\;
LMB_Data_Addr_20(2) <= \<const0>\;
LMB_Data_Addr_20(3) <= \<const0>\;
LMB_Data_Addr_20(4) <= \<const0>\;
LMB_Data_Addr_20(5) <= \<const0>\;
LMB_Data_Addr_20(6) <= \<const0>\;
LMB_Data_Addr_20(7) <= \<const0>\;
LMB_Data_Addr_20(8) <= \<const0>\;
LMB_Data_Addr_20(9) <= \<const0>\;
LMB_Data_Addr_20(10) <= \<const0>\;
LMB_Data_Addr_20(11) <= \<const0>\;
LMB_Data_Addr_20(12) <= \<const0>\;
LMB_Data_Addr_20(13) <= \<const0>\;
LMB_Data_Addr_20(14) <= \<const0>\;
LMB_Data_Addr_20(15) <= \<const0>\;
LMB_Data_Addr_20(16) <= \<const0>\;
LMB_Data_Addr_20(17) <= \<const0>\;
LMB_Data_Addr_20(18) <= \<const0>\;
LMB_Data_Addr_20(19) <= \<const0>\;
LMB_Data_Addr_20(20) <= \<const0>\;
LMB_Data_Addr_20(21) <= \<const0>\;
LMB_Data_Addr_20(22) <= \<const0>\;
LMB_Data_Addr_20(23) <= \<const0>\;
LMB_Data_Addr_20(24) <= \<const0>\;
LMB_Data_Addr_20(25) <= \<const0>\;
LMB_Data_Addr_20(26) <= \<const0>\;
LMB_Data_Addr_20(27) <= \<const0>\;
LMB_Data_Addr_20(28) <= \<const0>\;
LMB_Data_Addr_20(29) <= \<const0>\;
LMB_Data_Addr_20(30) <= \<const0>\;
LMB_Data_Addr_20(31) <= \<const0>\;
LMB_Data_Addr_21(0) <= \<const0>\;
LMB_Data_Addr_21(1) <= \<const0>\;
LMB_Data_Addr_21(2) <= \<const0>\;
LMB_Data_Addr_21(3) <= \<const0>\;
LMB_Data_Addr_21(4) <= \<const0>\;
LMB_Data_Addr_21(5) <= \<const0>\;
LMB_Data_Addr_21(6) <= \<const0>\;
LMB_Data_Addr_21(7) <= \<const0>\;
LMB_Data_Addr_21(8) <= \<const0>\;
LMB_Data_Addr_21(9) <= \<const0>\;
LMB_Data_Addr_21(10) <= \<const0>\;
LMB_Data_Addr_21(11) <= \<const0>\;
LMB_Data_Addr_21(12) <= \<const0>\;
LMB_Data_Addr_21(13) <= \<const0>\;
LMB_Data_Addr_21(14) <= \<const0>\;
LMB_Data_Addr_21(15) <= \<const0>\;
LMB_Data_Addr_21(16) <= \<const0>\;
LMB_Data_Addr_21(17) <= \<const0>\;
LMB_Data_Addr_21(18) <= \<const0>\;
LMB_Data_Addr_21(19) <= \<const0>\;
LMB_Data_Addr_21(20) <= \<const0>\;
LMB_Data_Addr_21(21) <= \<const0>\;
LMB_Data_Addr_21(22) <= \<const0>\;
LMB_Data_Addr_21(23) <= \<const0>\;
LMB_Data_Addr_21(24) <= \<const0>\;
LMB_Data_Addr_21(25) <= \<const0>\;
LMB_Data_Addr_21(26) <= \<const0>\;
LMB_Data_Addr_21(27) <= \<const0>\;
LMB_Data_Addr_21(28) <= \<const0>\;
LMB_Data_Addr_21(29) <= \<const0>\;
LMB_Data_Addr_21(30) <= \<const0>\;
LMB_Data_Addr_21(31) <= \<const0>\;
LMB_Data_Addr_22(0) <= \<const0>\;
LMB_Data_Addr_22(1) <= \<const0>\;
LMB_Data_Addr_22(2) <= \<const0>\;
LMB_Data_Addr_22(3) <= \<const0>\;
LMB_Data_Addr_22(4) <= \<const0>\;
LMB_Data_Addr_22(5) <= \<const0>\;
LMB_Data_Addr_22(6) <= \<const0>\;
LMB_Data_Addr_22(7) <= \<const0>\;
LMB_Data_Addr_22(8) <= \<const0>\;
LMB_Data_Addr_22(9) <= \<const0>\;
LMB_Data_Addr_22(10) <= \<const0>\;
LMB_Data_Addr_22(11) <= \<const0>\;
LMB_Data_Addr_22(12) <= \<const0>\;
LMB_Data_Addr_22(13) <= \<const0>\;
LMB_Data_Addr_22(14) <= \<const0>\;
LMB_Data_Addr_22(15) <= \<const0>\;
LMB_Data_Addr_22(16) <= \<const0>\;
LMB_Data_Addr_22(17) <= \<const0>\;
LMB_Data_Addr_22(18) <= \<const0>\;
LMB_Data_Addr_22(19) <= \<const0>\;
LMB_Data_Addr_22(20) <= \<const0>\;
LMB_Data_Addr_22(21) <= \<const0>\;
LMB_Data_Addr_22(22) <= \<const0>\;
LMB_Data_Addr_22(23) <= \<const0>\;
LMB_Data_Addr_22(24) <= \<const0>\;
LMB_Data_Addr_22(25) <= \<const0>\;
LMB_Data_Addr_22(26) <= \<const0>\;
LMB_Data_Addr_22(27) <= \<const0>\;
LMB_Data_Addr_22(28) <= \<const0>\;
LMB_Data_Addr_22(29) <= \<const0>\;
LMB_Data_Addr_22(30) <= \<const0>\;
LMB_Data_Addr_22(31) <= \<const0>\;
LMB_Data_Addr_23(0) <= \<const0>\;
LMB_Data_Addr_23(1) <= \<const0>\;
LMB_Data_Addr_23(2) <= \<const0>\;
LMB_Data_Addr_23(3) <= \<const0>\;
LMB_Data_Addr_23(4) <= \<const0>\;
LMB_Data_Addr_23(5) <= \<const0>\;
LMB_Data_Addr_23(6) <= \<const0>\;
LMB_Data_Addr_23(7) <= \<const0>\;
LMB_Data_Addr_23(8) <= \<const0>\;
LMB_Data_Addr_23(9) <= \<const0>\;
LMB_Data_Addr_23(10) <= \<const0>\;
LMB_Data_Addr_23(11) <= \<const0>\;
LMB_Data_Addr_23(12) <= \<const0>\;
LMB_Data_Addr_23(13) <= \<const0>\;
LMB_Data_Addr_23(14) <= \<const0>\;
LMB_Data_Addr_23(15) <= \<const0>\;
LMB_Data_Addr_23(16) <= \<const0>\;
LMB_Data_Addr_23(17) <= \<const0>\;
LMB_Data_Addr_23(18) <= \<const0>\;
LMB_Data_Addr_23(19) <= \<const0>\;
LMB_Data_Addr_23(20) <= \<const0>\;
LMB_Data_Addr_23(21) <= \<const0>\;
LMB_Data_Addr_23(22) <= \<const0>\;
LMB_Data_Addr_23(23) <= \<const0>\;
LMB_Data_Addr_23(24) <= \<const0>\;
LMB_Data_Addr_23(25) <= \<const0>\;
LMB_Data_Addr_23(26) <= \<const0>\;
LMB_Data_Addr_23(27) <= \<const0>\;
LMB_Data_Addr_23(28) <= \<const0>\;
LMB_Data_Addr_23(29) <= \<const0>\;
LMB_Data_Addr_23(30) <= \<const0>\;
LMB_Data_Addr_23(31) <= \<const0>\;
LMB_Data_Addr_24(0) <= \<const0>\;
LMB_Data_Addr_24(1) <= \<const0>\;
LMB_Data_Addr_24(2) <= \<const0>\;
LMB_Data_Addr_24(3) <= \<const0>\;
LMB_Data_Addr_24(4) <= \<const0>\;
LMB_Data_Addr_24(5) <= \<const0>\;
LMB_Data_Addr_24(6) <= \<const0>\;
LMB_Data_Addr_24(7) <= \<const0>\;
LMB_Data_Addr_24(8) <= \<const0>\;
LMB_Data_Addr_24(9) <= \<const0>\;
LMB_Data_Addr_24(10) <= \<const0>\;
LMB_Data_Addr_24(11) <= \<const0>\;
LMB_Data_Addr_24(12) <= \<const0>\;
LMB_Data_Addr_24(13) <= \<const0>\;
LMB_Data_Addr_24(14) <= \<const0>\;
LMB_Data_Addr_24(15) <= \<const0>\;
LMB_Data_Addr_24(16) <= \<const0>\;
LMB_Data_Addr_24(17) <= \<const0>\;
LMB_Data_Addr_24(18) <= \<const0>\;
LMB_Data_Addr_24(19) <= \<const0>\;
LMB_Data_Addr_24(20) <= \<const0>\;
LMB_Data_Addr_24(21) <= \<const0>\;
LMB_Data_Addr_24(22) <= \<const0>\;
LMB_Data_Addr_24(23) <= \<const0>\;
LMB_Data_Addr_24(24) <= \<const0>\;
LMB_Data_Addr_24(25) <= \<const0>\;
LMB_Data_Addr_24(26) <= \<const0>\;
LMB_Data_Addr_24(27) <= \<const0>\;
LMB_Data_Addr_24(28) <= \<const0>\;
LMB_Data_Addr_24(29) <= \<const0>\;
LMB_Data_Addr_24(30) <= \<const0>\;
LMB_Data_Addr_24(31) <= \<const0>\;
LMB_Data_Addr_25(0) <= \<const0>\;
LMB_Data_Addr_25(1) <= \<const0>\;
LMB_Data_Addr_25(2) <= \<const0>\;
LMB_Data_Addr_25(3) <= \<const0>\;
LMB_Data_Addr_25(4) <= \<const0>\;
LMB_Data_Addr_25(5) <= \<const0>\;
LMB_Data_Addr_25(6) <= \<const0>\;
LMB_Data_Addr_25(7) <= \<const0>\;
LMB_Data_Addr_25(8) <= \<const0>\;
LMB_Data_Addr_25(9) <= \<const0>\;
LMB_Data_Addr_25(10) <= \<const0>\;
LMB_Data_Addr_25(11) <= \<const0>\;
LMB_Data_Addr_25(12) <= \<const0>\;
LMB_Data_Addr_25(13) <= \<const0>\;
LMB_Data_Addr_25(14) <= \<const0>\;
LMB_Data_Addr_25(15) <= \<const0>\;
LMB_Data_Addr_25(16) <= \<const0>\;
LMB_Data_Addr_25(17) <= \<const0>\;
LMB_Data_Addr_25(18) <= \<const0>\;
LMB_Data_Addr_25(19) <= \<const0>\;
LMB_Data_Addr_25(20) <= \<const0>\;
LMB_Data_Addr_25(21) <= \<const0>\;
LMB_Data_Addr_25(22) <= \<const0>\;
LMB_Data_Addr_25(23) <= \<const0>\;
LMB_Data_Addr_25(24) <= \<const0>\;
LMB_Data_Addr_25(25) <= \<const0>\;
LMB_Data_Addr_25(26) <= \<const0>\;
LMB_Data_Addr_25(27) <= \<const0>\;
LMB_Data_Addr_25(28) <= \<const0>\;
LMB_Data_Addr_25(29) <= \<const0>\;
LMB_Data_Addr_25(30) <= \<const0>\;
LMB_Data_Addr_25(31) <= \<const0>\;
LMB_Data_Addr_26(0) <= \<const0>\;
LMB_Data_Addr_26(1) <= \<const0>\;
LMB_Data_Addr_26(2) <= \<const0>\;
LMB_Data_Addr_26(3) <= \<const0>\;
LMB_Data_Addr_26(4) <= \<const0>\;
LMB_Data_Addr_26(5) <= \<const0>\;
LMB_Data_Addr_26(6) <= \<const0>\;
LMB_Data_Addr_26(7) <= \<const0>\;
LMB_Data_Addr_26(8) <= \<const0>\;
LMB_Data_Addr_26(9) <= \<const0>\;
LMB_Data_Addr_26(10) <= \<const0>\;
LMB_Data_Addr_26(11) <= \<const0>\;
LMB_Data_Addr_26(12) <= \<const0>\;
LMB_Data_Addr_26(13) <= \<const0>\;
LMB_Data_Addr_26(14) <= \<const0>\;
LMB_Data_Addr_26(15) <= \<const0>\;
LMB_Data_Addr_26(16) <= \<const0>\;
LMB_Data_Addr_26(17) <= \<const0>\;
LMB_Data_Addr_26(18) <= \<const0>\;
LMB_Data_Addr_26(19) <= \<const0>\;
LMB_Data_Addr_26(20) <= \<const0>\;
LMB_Data_Addr_26(21) <= \<const0>\;
LMB_Data_Addr_26(22) <= \<const0>\;
LMB_Data_Addr_26(23) <= \<const0>\;
LMB_Data_Addr_26(24) <= \<const0>\;
LMB_Data_Addr_26(25) <= \<const0>\;
LMB_Data_Addr_26(26) <= \<const0>\;
LMB_Data_Addr_26(27) <= \<const0>\;
LMB_Data_Addr_26(28) <= \<const0>\;
LMB_Data_Addr_26(29) <= \<const0>\;
LMB_Data_Addr_26(30) <= \<const0>\;
LMB_Data_Addr_26(31) <= \<const0>\;
LMB_Data_Addr_27(0) <= \<const0>\;
LMB_Data_Addr_27(1) <= \<const0>\;
LMB_Data_Addr_27(2) <= \<const0>\;
LMB_Data_Addr_27(3) <= \<const0>\;
LMB_Data_Addr_27(4) <= \<const0>\;
LMB_Data_Addr_27(5) <= \<const0>\;
LMB_Data_Addr_27(6) <= \<const0>\;
LMB_Data_Addr_27(7) <= \<const0>\;
LMB_Data_Addr_27(8) <= \<const0>\;
LMB_Data_Addr_27(9) <= \<const0>\;
LMB_Data_Addr_27(10) <= \<const0>\;
LMB_Data_Addr_27(11) <= \<const0>\;
LMB_Data_Addr_27(12) <= \<const0>\;
LMB_Data_Addr_27(13) <= \<const0>\;
LMB_Data_Addr_27(14) <= \<const0>\;
LMB_Data_Addr_27(15) <= \<const0>\;
LMB_Data_Addr_27(16) <= \<const0>\;
LMB_Data_Addr_27(17) <= \<const0>\;
LMB_Data_Addr_27(18) <= \<const0>\;
LMB_Data_Addr_27(19) <= \<const0>\;
LMB_Data_Addr_27(20) <= \<const0>\;
LMB_Data_Addr_27(21) <= \<const0>\;
LMB_Data_Addr_27(22) <= \<const0>\;
LMB_Data_Addr_27(23) <= \<const0>\;
LMB_Data_Addr_27(24) <= \<const0>\;
LMB_Data_Addr_27(25) <= \<const0>\;
LMB_Data_Addr_27(26) <= \<const0>\;
LMB_Data_Addr_27(27) <= \<const0>\;
LMB_Data_Addr_27(28) <= \<const0>\;
LMB_Data_Addr_27(29) <= \<const0>\;
LMB_Data_Addr_27(30) <= \<const0>\;
LMB_Data_Addr_27(31) <= \<const0>\;
LMB_Data_Addr_28(0) <= \<const0>\;
LMB_Data_Addr_28(1) <= \<const0>\;
LMB_Data_Addr_28(2) <= \<const0>\;
LMB_Data_Addr_28(3) <= \<const0>\;
LMB_Data_Addr_28(4) <= \<const0>\;
LMB_Data_Addr_28(5) <= \<const0>\;
LMB_Data_Addr_28(6) <= \<const0>\;
LMB_Data_Addr_28(7) <= \<const0>\;
LMB_Data_Addr_28(8) <= \<const0>\;
LMB_Data_Addr_28(9) <= \<const0>\;
LMB_Data_Addr_28(10) <= \<const0>\;
LMB_Data_Addr_28(11) <= \<const0>\;
LMB_Data_Addr_28(12) <= \<const0>\;
LMB_Data_Addr_28(13) <= \<const0>\;
LMB_Data_Addr_28(14) <= \<const0>\;
LMB_Data_Addr_28(15) <= \<const0>\;
LMB_Data_Addr_28(16) <= \<const0>\;
LMB_Data_Addr_28(17) <= \<const0>\;
LMB_Data_Addr_28(18) <= \<const0>\;
LMB_Data_Addr_28(19) <= \<const0>\;
LMB_Data_Addr_28(20) <= \<const0>\;
LMB_Data_Addr_28(21) <= \<const0>\;
LMB_Data_Addr_28(22) <= \<const0>\;
LMB_Data_Addr_28(23) <= \<const0>\;
LMB_Data_Addr_28(24) <= \<const0>\;
LMB_Data_Addr_28(25) <= \<const0>\;
LMB_Data_Addr_28(26) <= \<const0>\;
LMB_Data_Addr_28(27) <= \<const0>\;
LMB_Data_Addr_28(28) <= \<const0>\;
LMB_Data_Addr_28(29) <= \<const0>\;
LMB_Data_Addr_28(30) <= \<const0>\;
LMB_Data_Addr_28(31) <= \<const0>\;
LMB_Data_Addr_29(0) <= \<const0>\;
LMB_Data_Addr_29(1) <= \<const0>\;
LMB_Data_Addr_29(2) <= \<const0>\;
LMB_Data_Addr_29(3) <= \<const0>\;
LMB_Data_Addr_29(4) <= \<const0>\;
LMB_Data_Addr_29(5) <= \<const0>\;
LMB_Data_Addr_29(6) <= \<const0>\;
LMB_Data_Addr_29(7) <= \<const0>\;
LMB_Data_Addr_29(8) <= \<const0>\;
LMB_Data_Addr_29(9) <= \<const0>\;
LMB_Data_Addr_29(10) <= \<const0>\;
LMB_Data_Addr_29(11) <= \<const0>\;
LMB_Data_Addr_29(12) <= \<const0>\;
LMB_Data_Addr_29(13) <= \<const0>\;
LMB_Data_Addr_29(14) <= \<const0>\;
LMB_Data_Addr_29(15) <= \<const0>\;
LMB_Data_Addr_29(16) <= \<const0>\;
LMB_Data_Addr_29(17) <= \<const0>\;
LMB_Data_Addr_29(18) <= \<const0>\;
LMB_Data_Addr_29(19) <= \<const0>\;
LMB_Data_Addr_29(20) <= \<const0>\;
LMB_Data_Addr_29(21) <= \<const0>\;
LMB_Data_Addr_29(22) <= \<const0>\;
LMB_Data_Addr_29(23) <= \<const0>\;
LMB_Data_Addr_29(24) <= \<const0>\;
LMB_Data_Addr_29(25) <= \<const0>\;
LMB_Data_Addr_29(26) <= \<const0>\;
LMB_Data_Addr_29(27) <= \<const0>\;
LMB_Data_Addr_29(28) <= \<const0>\;
LMB_Data_Addr_29(29) <= \<const0>\;
LMB_Data_Addr_29(30) <= \<const0>\;
LMB_Data_Addr_29(31) <= \<const0>\;
LMB_Data_Addr_3(0) <= \<const0>\;
LMB_Data_Addr_3(1) <= \<const0>\;
LMB_Data_Addr_3(2) <= \<const0>\;
LMB_Data_Addr_3(3) <= \<const0>\;
LMB_Data_Addr_3(4) <= \<const0>\;
LMB_Data_Addr_3(5) <= \<const0>\;
LMB_Data_Addr_3(6) <= \<const0>\;
LMB_Data_Addr_3(7) <= \<const0>\;
LMB_Data_Addr_3(8) <= \<const0>\;
LMB_Data_Addr_3(9) <= \<const0>\;
LMB_Data_Addr_3(10) <= \<const0>\;
LMB_Data_Addr_3(11) <= \<const0>\;
LMB_Data_Addr_3(12) <= \<const0>\;
LMB_Data_Addr_3(13) <= \<const0>\;
LMB_Data_Addr_3(14) <= \<const0>\;
LMB_Data_Addr_3(15) <= \<const0>\;
LMB_Data_Addr_3(16) <= \<const0>\;
LMB_Data_Addr_3(17) <= \<const0>\;
LMB_Data_Addr_3(18) <= \<const0>\;
LMB_Data_Addr_3(19) <= \<const0>\;
LMB_Data_Addr_3(20) <= \<const0>\;
LMB_Data_Addr_3(21) <= \<const0>\;
LMB_Data_Addr_3(22) <= \<const0>\;
LMB_Data_Addr_3(23) <= \<const0>\;
LMB_Data_Addr_3(24) <= \<const0>\;
LMB_Data_Addr_3(25) <= \<const0>\;
LMB_Data_Addr_3(26) <= \<const0>\;
LMB_Data_Addr_3(27) <= \<const0>\;
LMB_Data_Addr_3(28) <= \<const0>\;
LMB_Data_Addr_3(29) <= \<const0>\;
LMB_Data_Addr_3(30) <= \<const0>\;
LMB_Data_Addr_3(31) <= \<const0>\;
LMB_Data_Addr_30(0) <= \<const0>\;
LMB_Data_Addr_30(1) <= \<const0>\;
LMB_Data_Addr_30(2) <= \<const0>\;
LMB_Data_Addr_30(3) <= \<const0>\;
LMB_Data_Addr_30(4) <= \<const0>\;
LMB_Data_Addr_30(5) <= \<const0>\;
LMB_Data_Addr_30(6) <= \<const0>\;
LMB_Data_Addr_30(7) <= \<const0>\;
LMB_Data_Addr_30(8) <= \<const0>\;
LMB_Data_Addr_30(9) <= \<const0>\;
LMB_Data_Addr_30(10) <= \<const0>\;
LMB_Data_Addr_30(11) <= \<const0>\;
LMB_Data_Addr_30(12) <= \<const0>\;
LMB_Data_Addr_30(13) <= \<const0>\;
LMB_Data_Addr_30(14) <= \<const0>\;
LMB_Data_Addr_30(15) <= \<const0>\;
LMB_Data_Addr_30(16) <= \<const0>\;
LMB_Data_Addr_30(17) <= \<const0>\;
LMB_Data_Addr_30(18) <= \<const0>\;
LMB_Data_Addr_30(19) <= \<const0>\;
LMB_Data_Addr_30(20) <= \<const0>\;
LMB_Data_Addr_30(21) <= \<const0>\;
LMB_Data_Addr_30(22) <= \<const0>\;
LMB_Data_Addr_30(23) <= \<const0>\;
LMB_Data_Addr_30(24) <= \<const0>\;
LMB_Data_Addr_30(25) <= \<const0>\;
LMB_Data_Addr_30(26) <= \<const0>\;
LMB_Data_Addr_30(27) <= \<const0>\;
LMB_Data_Addr_30(28) <= \<const0>\;
LMB_Data_Addr_30(29) <= \<const0>\;
LMB_Data_Addr_30(30) <= \<const0>\;
LMB_Data_Addr_30(31) <= \<const0>\;
LMB_Data_Addr_31(0) <= \<const0>\;
LMB_Data_Addr_31(1) <= \<const0>\;
LMB_Data_Addr_31(2) <= \<const0>\;
LMB_Data_Addr_31(3) <= \<const0>\;
LMB_Data_Addr_31(4) <= \<const0>\;
LMB_Data_Addr_31(5) <= \<const0>\;
LMB_Data_Addr_31(6) <= \<const0>\;
LMB_Data_Addr_31(7) <= \<const0>\;
LMB_Data_Addr_31(8) <= \<const0>\;
LMB_Data_Addr_31(9) <= \<const0>\;
LMB_Data_Addr_31(10) <= \<const0>\;
LMB_Data_Addr_31(11) <= \<const0>\;
LMB_Data_Addr_31(12) <= \<const0>\;
LMB_Data_Addr_31(13) <= \<const0>\;
LMB_Data_Addr_31(14) <= \<const0>\;
LMB_Data_Addr_31(15) <= \<const0>\;
LMB_Data_Addr_31(16) <= \<const0>\;
LMB_Data_Addr_31(17) <= \<const0>\;
LMB_Data_Addr_31(18) <= \<const0>\;
LMB_Data_Addr_31(19) <= \<const0>\;
LMB_Data_Addr_31(20) <= \<const0>\;
LMB_Data_Addr_31(21) <= \<const0>\;
LMB_Data_Addr_31(22) <= \<const0>\;
LMB_Data_Addr_31(23) <= \<const0>\;
LMB_Data_Addr_31(24) <= \<const0>\;
LMB_Data_Addr_31(25) <= \<const0>\;
LMB_Data_Addr_31(26) <= \<const0>\;
LMB_Data_Addr_31(27) <= \<const0>\;
LMB_Data_Addr_31(28) <= \<const0>\;
LMB_Data_Addr_31(29) <= \<const0>\;
LMB_Data_Addr_31(30) <= \<const0>\;
LMB_Data_Addr_31(31) <= \<const0>\;
LMB_Data_Addr_4(0) <= \<const0>\;
LMB_Data_Addr_4(1) <= \<const0>\;
LMB_Data_Addr_4(2) <= \<const0>\;
LMB_Data_Addr_4(3) <= \<const0>\;
LMB_Data_Addr_4(4) <= \<const0>\;
LMB_Data_Addr_4(5) <= \<const0>\;
LMB_Data_Addr_4(6) <= \<const0>\;
LMB_Data_Addr_4(7) <= \<const0>\;
LMB_Data_Addr_4(8) <= \<const0>\;
LMB_Data_Addr_4(9) <= \<const0>\;
LMB_Data_Addr_4(10) <= \<const0>\;
LMB_Data_Addr_4(11) <= \<const0>\;
LMB_Data_Addr_4(12) <= \<const0>\;
LMB_Data_Addr_4(13) <= \<const0>\;
LMB_Data_Addr_4(14) <= \<const0>\;
LMB_Data_Addr_4(15) <= \<const0>\;
LMB_Data_Addr_4(16) <= \<const0>\;
LMB_Data_Addr_4(17) <= \<const0>\;
LMB_Data_Addr_4(18) <= \<const0>\;
LMB_Data_Addr_4(19) <= \<const0>\;
LMB_Data_Addr_4(20) <= \<const0>\;
LMB_Data_Addr_4(21) <= \<const0>\;
LMB_Data_Addr_4(22) <= \<const0>\;
LMB_Data_Addr_4(23) <= \<const0>\;
LMB_Data_Addr_4(24) <= \<const0>\;
LMB_Data_Addr_4(25) <= \<const0>\;
LMB_Data_Addr_4(26) <= \<const0>\;
LMB_Data_Addr_4(27) <= \<const0>\;
LMB_Data_Addr_4(28) <= \<const0>\;
LMB_Data_Addr_4(29) <= \<const0>\;
LMB_Data_Addr_4(30) <= \<const0>\;
LMB_Data_Addr_4(31) <= \<const0>\;
LMB_Data_Addr_5(0) <= \<const0>\;
LMB_Data_Addr_5(1) <= \<const0>\;
LMB_Data_Addr_5(2) <= \<const0>\;
LMB_Data_Addr_5(3) <= \<const0>\;
LMB_Data_Addr_5(4) <= \<const0>\;
LMB_Data_Addr_5(5) <= \<const0>\;
LMB_Data_Addr_5(6) <= \<const0>\;
LMB_Data_Addr_5(7) <= \<const0>\;
LMB_Data_Addr_5(8) <= \<const0>\;
LMB_Data_Addr_5(9) <= \<const0>\;
LMB_Data_Addr_5(10) <= \<const0>\;
LMB_Data_Addr_5(11) <= \<const0>\;
LMB_Data_Addr_5(12) <= \<const0>\;
LMB_Data_Addr_5(13) <= \<const0>\;
LMB_Data_Addr_5(14) <= \<const0>\;
LMB_Data_Addr_5(15) <= \<const0>\;
LMB_Data_Addr_5(16) <= \<const0>\;
LMB_Data_Addr_5(17) <= \<const0>\;
LMB_Data_Addr_5(18) <= \<const0>\;
LMB_Data_Addr_5(19) <= \<const0>\;
LMB_Data_Addr_5(20) <= \<const0>\;
LMB_Data_Addr_5(21) <= \<const0>\;
LMB_Data_Addr_5(22) <= \<const0>\;
LMB_Data_Addr_5(23) <= \<const0>\;
LMB_Data_Addr_5(24) <= \<const0>\;
LMB_Data_Addr_5(25) <= \<const0>\;
LMB_Data_Addr_5(26) <= \<const0>\;
LMB_Data_Addr_5(27) <= \<const0>\;
LMB_Data_Addr_5(28) <= \<const0>\;
LMB_Data_Addr_5(29) <= \<const0>\;
LMB_Data_Addr_5(30) <= \<const0>\;
LMB_Data_Addr_5(31) <= \<const0>\;
LMB_Data_Addr_6(0) <= \<const0>\;
LMB_Data_Addr_6(1) <= \<const0>\;
LMB_Data_Addr_6(2) <= \<const0>\;
LMB_Data_Addr_6(3) <= \<const0>\;
LMB_Data_Addr_6(4) <= \<const0>\;
LMB_Data_Addr_6(5) <= \<const0>\;
LMB_Data_Addr_6(6) <= \<const0>\;
LMB_Data_Addr_6(7) <= \<const0>\;
LMB_Data_Addr_6(8) <= \<const0>\;
LMB_Data_Addr_6(9) <= \<const0>\;
LMB_Data_Addr_6(10) <= \<const0>\;
LMB_Data_Addr_6(11) <= \<const0>\;
LMB_Data_Addr_6(12) <= \<const0>\;
LMB_Data_Addr_6(13) <= \<const0>\;
LMB_Data_Addr_6(14) <= \<const0>\;
LMB_Data_Addr_6(15) <= \<const0>\;
LMB_Data_Addr_6(16) <= \<const0>\;
LMB_Data_Addr_6(17) <= \<const0>\;
LMB_Data_Addr_6(18) <= \<const0>\;
LMB_Data_Addr_6(19) <= \<const0>\;
LMB_Data_Addr_6(20) <= \<const0>\;
LMB_Data_Addr_6(21) <= \<const0>\;
LMB_Data_Addr_6(22) <= \<const0>\;
LMB_Data_Addr_6(23) <= \<const0>\;
LMB_Data_Addr_6(24) <= \<const0>\;
LMB_Data_Addr_6(25) <= \<const0>\;
LMB_Data_Addr_6(26) <= \<const0>\;
LMB_Data_Addr_6(27) <= \<const0>\;
LMB_Data_Addr_6(28) <= \<const0>\;
LMB_Data_Addr_6(29) <= \<const0>\;
LMB_Data_Addr_6(30) <= \<const0>\;
LMB_Data_Addr_6(31) <= \<const0>\;
LMB_Data_Addr_7(0) <= \<const0>\;
LMB_Data_Addr_7(1) <= \<const0>\;
LMB_Data_Addr_7(2) <= \<const0>\;
LMB_Data_Addr_7(3) <= \<const0>\;
LMB_Data_Addr_7(4) <= \<const0>\;
LMB_Data_Addr_7(5) <= \<const0>\;
LMB_Data_Addr_7(6) <= \<const0>\;
LMB_Data_Addr_7(7) <= \<const0>\;
LMB_Data_Addr_7(8) <= \<const0>\;
LMB_Data_Addr_7(9) <= \<const0>\;
LMB_Data_Addr_7(10) <= \<const0>\;
LMB_Data_Addr_7(11) <= \<const0>\;
LMB_Data_Addr_7(12) <= \<const0>\;
LMB_Data_Addr_7(13) <= \<const0>\;
LMB_Data_Addr_7(14) <= \<const0>\;
LMB_Data_Addr_7(15) <= \<const0>\;
LMB_Data_Addr_7(16) <= \<const0>\;
LMB_Data_Addr_7(17) <= \<const0>\;
LMB_Data_Addr_7(18) <= \<const0>\;
LMB_Data_Addr_7(19) <= \<const0>\;
LMB_Data_Addr_7(20) <= \<const0>\;
LMB_Data_Addr_7(21) <= \<const0>\;
LMB_Data_Addr_7(22) <= \<const0>\;
LMB_Data_Addr_7(23) <= \<const0>\;
LMB_Data_Addr_7(24) <= \<const0>\;
LMB_Data_Addr_7(25) <= \<const0>\;
LMB_Data_Addr_7(26) <= \<const0>\;
LMB_Data_Addr_7(27) <= \<const0>\;
LMB_Data_Addr_7(28) <= \<const0>\;
LMB_Data_Addr_7(29) <= \<const0>\;
LMB_Data_Addr_7(30) <= \<const0>\;
LMB_Data_Addr_7(31) <= \<const0>\;
LMB_Data_Addr_8(0) <= \<const0>\;
LMB_Data_Addr_8(1) <= \<const0>\;
LMB_Data_Addr_8(2) <= \<const0>\;
LMB_Data_Addr_8(3) <= \<const0>\;
LMB_Data_Addr_8(4) <= \<const0>\;
LMB_Data_Addr_8(5) <= \<const0>\;
LMB_Data_Addr_8(6) <= \<const0>\;
LMB_Data_Addr_8(7) <= \<const0>\;
LMB_Data_Addr_8(8) <= \<const0>\;
LMB_Data_Addr_8(9) <= \<const0>\;
LMB_Data_Addr_8(10) <= \<const0>\;
LMB_Data_Addr_8(11) <= \<const0>\;
LMB_Data_Addr_8(12) <= \<const0>\;
LMB_Data_Addr_8(13) <= \<const0>\;
LMB_Data_Addr_8(14) <= \<const0>\;
LMB_Data_Addr_8(15) <= \<const0>\;
LMB_Data_Addr_8(16) <= \<const0>\;
LMB_Data_Addr_8(17) <= \<const0>\;
LMB_Data_Addr_8(18) <= \<const0>\;
LMB_Data_Addr_8(19) <= \<const0>\;
LMB_Data_Addr_8(20) <= \<const0>\;
LMB_Data_Addr_8(21) <= \<const0>\;
LMB_Data_Addr_8(22) <= \<const0>\;
LMB_Data_Addr_8(23) <= \<const0>\;
LMB_Data_Addr_8(24) <= \<const0>\;
LMB_Data_Addr_8(25) <= \<const0>\;
LMB_Data_Addr_8(26) <= \<const0>\;
LMB_Data_Addr_8(27) <= \<const0>\;
LMB_Data_Addr_8(28) <= \<const0>\;
LMB_Data_Addr_8(29) <= \<const0>\;
LMB_Data_Addr_8(30) <= \<const0>\;
LMB_Data_Addr_8(31) <= \<const0>\;
LMB_Data_Addr_9(0) <= \<const0>\;
LMB_Data_Addr_9(1) <= \<const0>\;
LMB_Data_Addr_9(2) <= \<const0>\;
LMB_Data_Addr_9(3) <= \<const0>\;
LMB_Data_Addr_9(4) <= \<const0>\;
LMB_Data_Addr_9(5) <= \<const0>\;
LMB_Data_Addr_9(6) <= \<const0>\;
LMB_Data_Addr_9(7) <= \<const0>\;
LMB_Data_Addr_9(8) <= \<const0>\;
LMB_Data_Addr_9(9) <= \<const0>\;
LMB_Data_Addr_9(10) <= \<const0>\;
LMB_Data_Addr_9(11) <= \<const0>\;
LMB_Data_Addr_9(12) <= \<const0>\;
LMB_Data_Addr_9(13) <= \<const0>\;
LMB_Data_Addr_9(14) <= \<const0>\;
LMB_Data_Addr_9(15) <= \<const0>\;
LMB_Data_Addr_9(16) <= \<const0>\;
LMB_Data_Addr_9(17) <= \<const0>\;
LMB_Data_Addr_9(18) <= \<const0>\;
LMB_Data_Addr_9(19) <= \<const0>\;
LMB_Data_Addr_9(20) <= \<const0>\;
LMB_Data_Addr_9(21) <= \<const0>\;
LMB_Data_Addr_9(22) <= \<const0>\;
LMB_Data_Addr_9(23) <= \<const0>\;
LMB_Data_Addr_9(24) <= \<const0>\;
LMB_Data_Addr_9(25) <= \<const0>\;
LMB_Data_Addr_9(26) <= \<const0>\;
LMB_Data_Addr_9(27) <= \<const0>\;
LMB_Data_Addr_9(28) <= \<const0>\;
LMB_Data_Addr_9(29) <= \<const0>\;
LMB_Data_Addr_9(30) <= \<const0>\;
LMB_Data_Addr_9(31) <= \<const0>\;
LMB_Data_Write_0(0) <= \<const0>\;
LMB_Data_Write_0(1) <= \<const0>\;
LMB_Data_Write_0(2) <= \<const0>\;
LMB_Data_Write_0(3) <= \<const0>\;
LMB_Data_Write_0(4) <= \<const0>\;
LMB_Data_Write_0(5) <= \<const0>\;
LMB_Data_Write_0(6) <= \<const0>\;
LMB_Data_Write_0(7) <= \<const0>\;
LMB_Data_Write_0(8) <= \<const0>\;
LMB_Data_Write_0(9) <= \<const0>\;
LMB_Data_Write_0(10) <= \<const0>\;
LMB_Data_Write_0(11) <= \<const0>\;
LMB_Data_Write_0(12) <= \<const0>\;
LMB_Data_Write_0(13) <= \<const0>\;
LMB_Data_Write_0(14) <= \<const0>\;
LMB_Data_Write_0(15) <= \<const0>\;
LMB_Data_Write_0(16) <= \<const0>\;
LMB_Data_Write_0(17) <= \<const0>\;
LMB_Data_Write_0(18) <= \<const0>\;
LMB_Data_Write_0(19) <= \<const0>\;
LMB_Data_Write_0(20) <= \<const0>\;
LMB_Data_Write_0(21) <= \<const0>\;
LMB_Data_Write_0(22) <= \<const0>\;
LMB_Data_Write_0(23) <= \<const0>\;
LMB_Data_Write_0(24) <= \<const0>\;
LMB_Data_Write_0(25) <= \<const0>\;
LMB_Data_Write_0(26) <= \<const0>\;
LMB_Data_Write_0(27) <= \<const0>\;
LMB_Data_Write_0(28) <= \<const0>\;
LMB_Data_Write_0(29) <= \<const0>\;
LMB_Data_Write_0(30) <= \<const0>\;
LMB_Data_Write_0(31) <= \<const0>\;
LMB_Data_Write_1(0) <= \<const0>\;
LMB_Data_Write_1(1) <= \<const0>\;
LMB_Data_Write_1(2) <= \<const0>\;
LMB_Data_Write_1(3) <= \<const0>\;
LMB_Data_Write_1(4) <= \<const0>\;
LMB_Data_Write_1(5) <= \<const0>\;
LMB_Data_Write_1(6) <= \<const0>\;
LMB_Data_Write_1(7) <= \<const0>\;
LMB_Data_Write_1(8) <= \<const0>\;
LMB_Data_Write_1(9) <= \<const0>\;
LMB_Data_Write_1(10) <= \<const0>\;
LMB_Data_Write_1(11) <= \<const0>\;
LMB_Data_Write_1(12) <= \<const0>\;
LMB_Data_Write_1(13) <= \<const0>\;
LMB_Data_Write_1(14) <= \<const0>\;
LMB_Data_Write_1(15) <= \<const0>\;
LMB_Data_Write_1(16) <= \<const0>\;
LMB_Data_Write_1(17) <= \<const0>\;
LMB_Data_Write_1(18) <= \<const0>\;
LMB_Data_Write_1(19) <= \<const0>\;
LMB_Data_Write_1(20) <= \<const0>\;
LMB_Data_Write_1(21) <= \<const0>\;
LMB_Data_Write_1(22) <= \<const0>\;
LMB_Data_Write_1(23) <= \<const0>\;
LMB_Data_Write_1(24) <= \<const0>\;
LMB_Data_Write_1(25) <= \<const0>\;
LMB_Data_Write_1(26) <= \<const0>\;
LMB_Data_Write_1(27) <= \<const0>\;
LMB_Data_Write_1(28) <= \<const0>\;
LMB_Data_Write_1(29) <= \<const0>\;
LMB_Data_Write_1(30) <= \<const0>\;
LMB_Data_Write_1(31) <= \<const0>\;
LMB_Data_Write_10(0) <= \<const0>\;
LMB_Data_Write_10(1) <= \<const0>\;
LMB_Data_Write_10(2) <= \<const0>\;
LMB_Data_Write_10(3) <= \<const0>\;
LMB_Data_Write_10(4) <= \<const0>\;
LMB_Data_Write_10(5) <= \<const0>\;
LMB_Data_Write_10(6) <= \<const0>\;
LMB_Data_Write_10(7) <= \<const0>\;
LMB_Data_Write_10(8) <= \<const0>\;
LMB_Data_Write_10(9) <= \<const0>\;
LMB_Data_Write_10(10) <= \<const0>\;
LMB_Data_Write_10(11) <= \<const0>\;
LMB_Data_Write_10(12) <= \<const0>\;
LMB_Data_Write_10(13) <= \<const0>\;
LMB_Data_Write_10(14) <= \<const0>\;
LMB_Data_Write_10(15) <= \<const0>\;
LMB_Data_Write_10(16) <= \<const0>\;
LMB_Data_Write_10(17) <= \<const0>\;
LMB_Data_Write_10(18) <= \<const0>\;
LMB_Data_Write_10(19) <= \<const0>\;
LMB_Data_Write_10(20) <= \<const0>\;
LMB_Data_Write_10(21) <= \<const0>\;
LMB_Data_Write_10(22) <= \<const0>\;
LMB_Data_Write_10(23) <= \<const0>\;
LMB_Data_Write_10(24) <= \<const0>\;
LMB_Data_Write_10(25) <= \<const0>\;
LMB_Data_Write_10(26) <= \<const0>\;
LMB_Data_Write_10(27) <= \<const0>\;
LMB_Data_Write_10(28) <= \<const0>\;
LMB_Data_Write_10(29) <= \<const0>\;
LMB_Data_Write_10(30) <= \<const0>\;
LMB_Data_Write_10(31) <= \<const0>\;
LMB_Data_Write_11(0) <= \<const0>\;
LMB_Data_Write_11(1) <= \<const0>\;
LMB_Data_Write_11(2) <= \<const0>\;
LMB_Data_Write_11(3) <= \<const0>\;
LMB_Data_Write_11(4) <= \<const0>\;
LMB_Data_Write_11(5) <= \<const0>\;
LMB_Data_Write_11(6) <= \<const0>\;
LMB_Data_Write_11(7) <= \<const0>\;
LMB_Data_Write_11(8) <= \<const0>\;
LMB_Data_Write_11(9) <= \<const0>\;
LMB_Data_Write_11(10) <= \<const0>\;
LMB_Data_Write_11(11) <= \<const0>\;
LMB_Data_Write_11(12) <= \<const0>\;
LMB_Data_Write_11(13) <= \<const0>\;
LMB_Data_Write_11(14) <= \<const0>\;
LMB_Data_Write_11(15) <= \<const0>\;
LMB_Data_Write_11(16) <= \<const0>\;
LMB_Data_Write_11(17) <= \<const0>\;
LMB_Data_Write_11(18) <= \<const0>\;
LMB_Data_Write_11(19) <= \<const0>\;
LMB_Data_Write_11(20) <= \<const0>\;
LMB_Data_Write_11(21) <= \<const0>\;
LMB_Data_Write_11(22) <= \<const0>\;
LMB_Data_Write_11(23) <= \<const0>\;
LMB_Data_Write_11(24) <= \<const0>\;
LMB_Data_Write_11(25) <= \<const0>\;
LMB_Data_Write_11(26) <= \<const0>\;
LMB_Data_Write_11(27) <= \<const0>\;
LMB_Data_Write_11(28) <= \<const0>\;
LMB_Data_Write_11(29) <= \<const0>\;
LMB_Data_Write_11(30) <= \<const0>\;
LMB_Data_Write_11(31) <= \<const0>\;
LMB_Data_Write_12(0) <= \<const0>\;
LMB_Data_Write_12(1) <= \<const0>\;
LMB_Data_Write_12(2) <= \<const0>\;
LMB_Data_Write_12(3) <= \<const0>\;
LMB_Data_Write_12(4) <= \<const0>\;
LMB_Data_Write_12(5) <= \<const0>\;
LMB_Data_Write_12(6) <= \<const0>\;
LMB_Data_Write_12(7) <= \<const0>\;
LMB_Data_Write_12(8) <= \<const0>\;
LMB_Data_Write_12(9) <= \<const0>\;
LMB_Data_Write_12(10) <= \<const0>\;
LMB_Data_Write_12(11) <= \<const0>\;
LMB_Data_Write_12(12) <= \<const0>\;
LMB_Data_Write_12(13) <= \<const0>\;
LMB_Data_Write_12(14) <= \<const0>\;
LMB_Data_Write_12(15) <= \<const0>\;
LMB_Data_Write_12(16) <= \<const0>\;
LMB_Data_Write_12(17) <= \<const0>\;
LMB_Data_Write_12(18) <= \<const0>\;
LMB_Data_Write_12(19) <= \<const0>\;
LMB_Data_Write_12(20) <= \<const0>\;
LMB_Data_Write_12(21) <= \<const0>\;
LMB_Data_Write_12(22) <= \<const0>\;
LMB_Data_Write_12(23) <= \<const0>\;
LMB_Data_Write_12(24) <= \<const0>\;
LMB_Data_Write_12(25) <= \<const0>\;
LMB_Data_Write_12(26) <= \<const0>\;
LMB_Data_Write_12(27) <= \<const0>\;
LMB_Data_Write_12(28) <= \<const0>\;
LMB_Data_Write_12(29) <= \<const0>\;
LMB_Data_Write_12(30) <= \<const0>\;
LMB_Data_Write_12(31) <= \<const0>\;
LMB_Data_Write_13(0) <= \<const0>\;
LMB_Data_Write_13(1) <= \<const0>\;
LMB_Data_Write_13(2) <= \<const0>\;
LMB_Data_Write_13(3) <= \<const0>\;
LMB_Data_Write_13(4) <= \<const0>\;
LMB_Data_Write_13(5) <= \<const0>\;
LMB_Data_Write_13(6) <= \<const0>\;
LMB_Data_Write_13(7) <= \<const0>\;
LMB_Data_Write_13(8) <= \<const0>\;
LMB_Data_Write_13(9) <= \<const0>\;
LMB_Data_Write_13(10) <= \<const0>\;
LMB_Data_Write_13(11) <= \<const0>\;
LMB_Data_Write_13(12) <= \<const0>\;
LMB_Data_Write_13(13) <= \<const0>\;
LMB_Data_Write_13(14) <= \<const0>\;
LMB_Data_Write_13(15) <= \<const0>\;
LMB_Data_Write_13(16) <= \<const0>\;
LMB_Data_Write_13(17) <= \<const0>\;
LMB_Data_Write_13(18) <= \<const0>\;
LMB_Data_Write_13(19) <= \<const0>\;
LMB_Data_Write_13(20) <= \<const0>\;
LMB_Data_Write_13(21) <= \<const0>\;
LMB_Data_Write_13(22) <= \<const0>\;
LMB_Data_Write_13(23) <= \<const0>\;
LMB_Data_Write_13(24) <= \<const0>\;
LMB_Data_Write_13(25) <= \<const0>\;
LMB_Data_Write_13(26) <= \<const0>\;
LMB_Data_Write_13(27) <= \<const0>\;
LMB_Data_Write_13(28) <= \<const0>\;
LMB_Data_Write_13(29) <= \<const0>\;
LMB_Data_Write_13(30) <= \<const0>\;
LMB_Data_Write_13(31) <= \<const0>\;
LMB_Data_Write_14(0) <= \<const0>\;
LMB_Data_Write_14(1) <= \<const0>\;
LMB_Data_Write_14(2) <= \<const0>\;
LMB_Data_Write_14(3) <= \<const0>\;
LMB_Data_Write_14(4) <= \<const0>\;
LMB_Data_Write_14(5) <= \<const0>\;
LMB_Data_Write_14(6) <= \<const0>\;
LMB_Data_Write_14(7) <= \<const0>\;
LMB_Data_Write_14(8) <= \<const0>\;
LMB_Data_Write_14(9) <= \<const0>\;
LMB_Data_Write_14(10) <= \<const0>\;
LMB_Data_Write_14(11) <= \<const0>\;
LMB_Data_Write_14(12) <= \<const0>\;
LMB_Data_Write_14(13) <= \<const0>\;
LMB_Data_Write_14(14) <= \<const0>\;
LMB_Data_Write_14(15) <= \<const0>\;
LMB_Data_Write_14(16) <= \<const0>\;
LMB_Data_Write_14(17) <= \<const0>\;
LMB_Data_Write_14(18) <= \<const0>\;
LMB_Data_Write_14(19) <= \<const0>\;
LMB_Data_Write_14(20) <= \<const0>\;
LMB_Data_Write_14(21) <= \<const0>\;
LMB_Data_Write_14(22) <= \<const0>\;
LMB_Data_Write_14(23) <= \<const0>\;
LMB_Data_Write_14(24) <= \<const0>\;
LMB_Data_Write_14(25) <= \<const0>\;
LMB_Data_Write_14(26) <= \<const0>\;
LMB_Data_Write_14(27) <= \<const0>\;
LMB_Data_Write_14(28) <= \<const0>\;
LMB_Data_Write_14(29) <= \<const0>\;
LMB_Data_Write_14(30) <= \<const0>\;
LMB_Data_Write_14(31) <= \<const0>\;
LMB_Data_Write_15(0) <= \<const0>\;
LMB_Data_Write_15(1) <= \<const0>\;
LMB_Data_Write_15(2) <= \<const0>\;
LMB_Data_Write_15(3) <= \<const0>\;
LMB_Data_Write_15(4) <= \<const0>\;
LMB_Data_Write_15(5) <= \<const0>\;
LMB_Data_Write_15(6) <= \<const0>\;
LMB_Data_Write_15(7) <= \<const0>\;
LMB_Data_Write_15(8) <= \<const0>\;
LMB_Data_Write_15(9) <= \<const0>\;
LMB_Data_Write_15(10) <= \<const0>\;
LMB_Data_Write_15(11) <= \<const0>\;
LMB_Data_Write_15(12) <= \<const0>\;
LMB_Data_Write_15(13) <= \<const0>\;
LMB_Data_Write_15(14) <= \<const0>\;
LMB_Data_Write_15(15) <= \<const0>\;
LMB_Data_Write_15(16) <= \<const0>\;
LMB_Data_Write_15(17) <= \<const0>\;
LMB_Data_Write_15(18) <= \<const0>\;
LMB_Data_Write_15(19) <= \<const0>\;
LMB_Data_Write_15(20) <= \<const0>\;
LMB_Data_Write_15(21) <= \<const0>\;
LMB_Data_Write_15(22) <= \<const0>\;
LMB_Data_Write_15(23) <= \<const0>\;
LMB_Data_Write_15(24) <= \<const0>\;
LMB_Data_Write_15(25) <= \<const0>\;
LMB_Data_Write_15(26) <= \<const0>\;
LMB_Data_Write_15(27) <= \<const0>\;
LMB_Data_Write_15(28) <= \<const0>\;
LMB_Data_Write_15(29) <= \<const0>\;
LMB_Data_Write_15(30) <= \<const0>\;
LMB_Data_Write_15(31) <= \<const0>\;
LMB_Data_Write_16(0) <= \<const0>\;
LMB_Data_Write_16(1) <= \<const0>\;
LMB_Data_Write_16(2) <= \<const0>\;
LMB_Data_Write_16(3) <= \<const0>\;
LMB_Data_Write_16(4) <= \<const0>\;
LMB_Data_Write_16(5) <= \<const0>\;
LMB_Data_Write_16(6) <= \<const0>\;
LMB_Data_Write_16(7) <= \<const0>\;
LMB_Data_Write_16(8) <= \<const0>\;
LMB_Data_Write_16(9) <= \<const0>\;
LMB_Data_Write_16(10) <= \<const0>\;
LMB_Data_Write_16(11) <= \<const0>\;
LMB_Data_Write_16(12) <= \<const0>\;
LMB_Data_Write_16(13) <= \<const0>\;
LMB_Data_Write_16(14) <= \<const0>\;
LMB_Data_Write_16(15) <= \<const0>\;
LMB_Data_Write_16(16) <= \<const0>\;
LMB_Data_Write_16(17) <= \<const0>\;
LMB_Data_Write_16(18) <= \<const0>\;
LMB_Data_Write_16(19) <= \<const0>\;
LMB_Data_Write_16(20) <= \<const0>\;
LMB_Data_Write_16(21) <= \<const0>\;
LMB_Data_Write_16(22) <= \<const0>\;
LMB_Data_Write_16(23) <= \<const0>\;
LMB_Data_Write_16(24) <= \<const0>\;
LMB_Data_Write_16(25) <= \<const0>\;
LMB_Data_Write_16(26) <= \<const0>\;
LMB_Data_Write_16(27) <= \<const0>\;
LMB_Data_Write_16(28) <= \<const0>\;
LMB_Data_Write_16(29) <= \<const0>\;
LMB_Data_Write_16(30) <= \<const0>\;
LMB_Data_Write_16(31) <= \<const0>\;
LMB_Data_Write_17(0) <= \<const0>\;
LMB_Data_Write_17(1) <= \<const0>\;
LMB_Data_Write_17(2) <= \<const0>\;
LMB_Data_Write_17(3) <= \<const0>\;
LMB_Data_Write_17(4) <= \<const0>\;
LMB_Data_Write_17(5) <= \<const0>\;
LMB_Data_Write_17(6) <= \<const0>\;
LMB_Data_Write_17(7) <= \<const0>\;
LMB_Data_Write_17(8) <= \<const0>\;
LMB_Data_Write_17(9) <= \<const0>\;
LMB_Data_Write_17(10) <= \<const0>\;
LMB_Data_Write_17(11) <= \<const0>\;
LMB_Data_Write_17(12) <= \<const0>\;
LMB_Data_Write_17(13) <= \<const0>\;
LMB_Data_Write_17(14) <= \<const0>\;
LMB_Data_Write_17(15) <= \<const0>\;
LMB_Data_Write_17(16) <= \<const0>\;
LMB_Data_Write_17(17) <= \<const0>\;
LMB_Data_Write_17(18) <= \<const0>\;
LMB_Data_Write_17(19) <= \<const0>\;
LMB_Data_Write_17(20) <= \<const0>\;
LMB_Data_Write_17(21) <= \<const0>\;
LMB_Data_Write_17(22) <= \<const0>\;
LMB_Data_Write_17(23) <= \<const0>\;
LMB_Data_Write_17(24) <= \<const0>\;
LMB_Data_Write_17(25) <= \<const0>\;
LMB_Data_Write_17(26) <= \<const0>\;
LMB_Data_Write_17(27) <= \<const0>\;
LMB_Data_Write_17(28) <= \<const0>\;
LMB_Data_Write_17(29) <= \<const0>\;
LMB_Data_Write_17(30) <= \<const0>\;
LMB_Data_Write_17(31) <= \<const0>\;
LMB_Data_Write_18(0) <= \<const0>\;
LMB_Data_Write_18(1) <= \<const0>\;
LMB_Data_Write_18(2) <= \<const0>\;
LMB_Data_Write_18(3) <= \<const0>\;
LMB_Data_Write_18(4) <= \<const0>\;
LMB_Data_Write_18(5) <= \<const0>\;
LMB_Data_Write_18(6) <= \<const0>\;
LMB_Data_Write_18(7) <= \<const0>\;
LMB_Data_Write_18(8) <= \<const0>\;
LMB_Data_Write_18(9) <= \<const0>\;
LMB_Data_Write_18(10) <= \<const0>\;
LMB_Data_Write_18(11) <= \<const0>\;
LMB_Data_Write_18(12) <= \<const0>\;
LMB_Data_Write_18(13) <= \<const0>\;
LMB_Data_Write_18(14) <= \<const0>\;
LMB_Data_Write_18(15) <= \<const0>\;
LMB_Data_Write_18(16) <= \<const0>\;
LMB_Data_Write_18(17) <= \<const0>\;
LMB_Data_Write_18(18) <= \<const0>\;
LMB_Data_Write_18(19) <= \<const0>\;
LMB_Data_Write_18(20) <= \<const0>\;
LMB_Data_Write_18(21) <= \<const0>\;
LMB_Data_Write_18(22) <= \<const0>\;
LMB_Data_Write_18(23) <= \<const0>\;
LMB_Data_Write_18(24) <= \<const0>\;
LMB_Data_Write_18(25) <= \<const0>\;
LMB_Data_Write_18(26) <= \<const0>\;
LMB_Data_Write_18(27) <= \<const0>\;
LMB_Data_Write_18(28) <= \<const0>\;
LMB_Data_Write_18(29) <= \<const0>\;
LMB_Data_Write_18(30) <= \<const0>\;
LMB_Data_Write_18(31) <= \<const0>\;
LMB_Data_Write_19(0) <= \<const0>\;
LMB_Data_Write_19(1) <= \<const0>\;
LMB_Data_Write_19(2) <= \<const0>\;
LMB_Data_Write_19(3) <= \<const0>\;
LMB_Data_Write_19(4) <= \<const0>\;
LMB_Data_Write_19(5) <= \<const0>\;
LMB_Data_Write_19(6) <= \<const0>\;
LMB_Data_Write_19(7) <= \<const0>\;
LMB_Data_Write_19(8) <= \<const0>\;
LMB_Data_Write_19(9) <= \<const0>\;
LMB_Data_Write_19(10) <= \<const0>\;
LMB_Data_Write_19(11) <= \<const0>\;
LMB_Data_Write_19(12) <= \<const0>\;
LMB_Data_Write_19(13) <= \<const0>\;
LMB_Data_Write_19(14) <= \<const0>\;
LMB_Data_Write_19(15) <= \<const0>\;
LMB_Data_Write_19(16) <= \<const0>\;
LMB_Data_Write_19(17) <= \<const0>\;
LMB_Data_Write_19(18) <= \<const0>\;
LMB_Data_Write_19(19) <= \<const0>\;
LMB_Data_Write_19(20) <= \<const0>\;
LMB_Data_Write_19(21) <= \<const0>\;
LMB_Data_Write_19(22) <= \<const0>\;
LMB_Data_Write_19(23) <= \<const0>\;
LMB_Data_Write_19(24) <= \<const0>\;
LMB_Data_Write_19(25) <= \<const0>\;
LMB_Data_Write_19(26) <= \<const0>\;
LMB_Data_Write_19(27) <= \<const0>\;
LMB_Data_Write_19(28) <= \<const0>\;
LMB_Data_Write_19(29) <= \<const0>\;
LMB_Data_Write_19(30) <= \<const0>\;
LMB_Data_Write_19(31) <= \<const0>\;
LMB_Data_Write_2(0) <= \<const0>\;
LMB_Data_Write_2(1) <= \<const0>\;
LMB_Data_Write_2(2) <= \<const0>\;
LMB_Data_Write_2(3) <= \<const0>\;
LMB_Data_Write_2(4) <= \<const0>\;
LMB_Data_Write_2(5) <= \<const0>\;
LMB_Data_Write_2(6) <= \<const0>\;
LMB_Data_Write_2(7) <= \<const0>\;
LMB_Data_Write_2(8) <= \<const0>\;
LMB_Data_Write_2(9) <= \<const0>\;
LMB_Data_Write_2(10) <= \<const0>\;
LMB_Data_Write_2(11) <= \<const0>\;
LMB_Data_Write_2(12) <= \<const0>\;
LMB_Data_Write_2(13) <= \<const0>\;
LMB_Data_Write_2(14) <= \<const0>\;
LMB_Data_Write_2(15) <= \<const0>\;
LMB_Data_Write_2(16) <= \<const0>\;
LMB_Data_Write_2(17) <= \<const0>\;
LMB_Data_Write_2(18) <= \<const0>\;
LMB_Data_Write_2(19) <= \<const0>\;
LMB_Data_Write_2(20) <= \<const0>\;
LMB_Data_Write_2(21) <= \<const0>\;
LMB_Data_Write_2(22) <= \<const0>\;
LMB_Data_Write_2(23) <= \<const0>\;
LMB_Data_Write_2(24) <= \<const0>\;
LMB_Data_Write_2(25) <= \<const0>\;
LMB_Data_Write_2(26) <= \<const0>\;
LMB_Data_Write_2(27) <= \<const0>\;
LMB_Data_Write_2(28) <= \<const0>\;
LMB_Data_Write_2(29) <= \<const0>\;
LMB_Data_Write_2(30) <= \<const0>\;
LMB_Data_Write_2(31) <= \<const0>\;
LMB_Data_Write_20(0) <= \<const0>\;
LMB_Data_Write_20(1) <= \<const0>\;
LMB_Data_Write_20(2) <= \<const0>\;
LMB_Data_Write_20(3) <= \<const0>\;
LMB_Data_Write_20(4) <= \<const0>\;
LMB_Data_Write_20(5) <= \<const0>\;
LMB_Data_Write_20(6) <= \<const0>\;
LMB_Data_Write_20(7) <= \<const0>\;
LMB_Data_Write_20(8) <= \<const0>\;
LMB_Data_Write_20(9) <= \<const0>\;
LMB_Data_Write_20(10) <= \<const0>\;
LMB_Data_Write_20(11) <= \<const0>\;
LMB_Data_Write_20(12) <= \<const0>\;
LMB_Data_Write_20(13) <= \<const0>\;
LMB_Data_Write_20(14) <= \<const0>\;
LMB_Data_Write_20(15) <= \<const0>\;
LMB_Data_Write_20(16) <= \<const0>\;
LMB_Data_Write_20(17) <= \<const0>\;
LMB_Data_Write_20(18) <= \<const0>\;
LMB_Data_Write_20(19) <= \<const0>\;
LMB_Data_Write_20(20) <= \<const0>\;
LMB_Data_Write_20(21) <= \<const0>\;
LMB_Data_Write_20(22) <= \<const0>\;
LMB_Data_Write_20(23) <= \<const0>\;
LMB_Data_Write_20(24) <= \<const0>\;
LMB_Data_Write_20(25) <= \<const0>\;
LMB_Data_Write_20(26) <= \<const0>\;
LMB_Data_Write_20(27) <= \<const0>\;
LMB_Data_Write_20(28) <= \<const0>\;
LMB_Data_Write_20(29) <= \<const0>\;
LMB_Data_Write_20(30) <= \<const0>\;
LMB_Data_Write_20(31) <= \<const0>\;
LMB_Data_Write_21(0) <= \<const0>\;
LMB_Data_Write_21(1) <= \<const0>\;
LMB_Data_Write_21(2) <= \<const0>\;
LMB_Data_Write_21(3) <= \<const0>\;
LMB_Data_Write_21(4) <= \<const0>\;
LMB_Data_Write_21(5) <= \<const0>\;
LMB_Data_Write_21(6) <= \<const0>\;
LMB_Data_Write_21(7) <= \<const0>\;
LMB_Data_Write_21(8) <= \<const0>\;
LMB_Data_Write_21(9) <= \<const0>\;
LMB_Data_Write_21(10) <= \<const0>\;
LMB_Data_Write_21(11) <= \<const0>\;
LMB_Data_Write_21(12) <= \<const0>\;
LMB_Data_Write_21(13) <= \<const0>\;
LMB_Data_Write_21(14) <= \<const0>\;
LMB_Data_Write_21(15) <= \<const0>\;
LMB_Data_Write_21(16) <= \<const0>\;
LMB_Data_Write_21(17) <= \<const0>\;
LMB_Data_Write_21(18) <= \<const0>\;
LMB_Data_Write_21(19) <= \<const0>\;
LMB_Data_Write_21(20) <= \<const0>\;
LMB_Data_Write_21(21) <= \<const0>\;
LMB_Data_Write_21(22) <= \<const0>\;
LMB_Data_Write_21(23) <= \<const0>\;
LMB_Data_Write_21(24) <= \<const0>\;
LMB_Data_Write_21(25) <= \<const0>\;
LMB_Data_Write_21(26) <= \<const0>\;
LMB_Data_Write_21(27) <= \<const0>\;
LMB_Data_Write_21(28) <= \<const0>\;
LMB_Data_Write_21(29) <= \<const0>\;
LMB_Data_Write_21(30) <= \<const0>\;
LMB_Data_Write_21(31) <= \<const0>\;
LMB_Data_Write_22(0) <= \<const0>\;
LMB_Data_Write_22(1) <= \<const0>\;
LMB_Data_Write_22(2) <= \<const0>\;
LMB_Data_Write_22(3) <= \<const0>\;
LMB_Data_Write_22(4) <= \<const0>\;
LMB_Data_Write_22(5) <= \<const0>\;
LMB_Data_Write_22(6) <= \<const0>\;
LMB_Data_Write_22(7) <= \<const0>\;
LMB_Data_Write_22(8) <= \<const0>\;
LMB_Data_Write_22(9) <= \<const0>\;
LMB_Data_Write_22(10) <= \<const0>\;
LMB_Data_Write_22(11) <= \<const0>\;
LMB_Data_Write_22(12) <= \<const0>\;
LMB_Data_Write_22(13) <= \<const0>\;
LMB_Data_Write_22(14) <= \<const0>\;
LMB_Data_Write_22(15) <= \<const0>\;
LMB_Data_Write_22(16) <= \<const0>\;
LMB_Data_Write_22(17) <= \<const0>\;
LMB_Data_Write_22(18) <= \<const0>\;
LMB_Data_Write_22(19) <= \<const0>\;
LMB_Data_Write_22(20) <= \<const0>\;
LMB_Data_Write_22(21) <= \<const0>\;
LMB_Data_Write_22(22) <= \<const0>\;
LMB_Data_Write_22(23) <= \<const0>\;
LMB_Data_Write_22(24) <= \<const0>\;
LMB_Data_Write_22(25) <= \<const0>\;
LMB_Data_Write_22(26) <= \<const0>\;
LMB_Data_Write_22(27) <= \<const0>\;
LMB_Data_Write_22(28) <= \<const0>\;
LMB_Data_Write_22(29) <= \<const0>\;
LMB_Data_Write_22(30) <= \<const0>\;
LMB_Data_Write_22(31) <= \<const0>\;
LMB_Data_Write_23(0) <= \<const0>\;
LMB_Data_Write_23(1) <= \<const0>\;
LMB_Data_Write_23(2) <= \<const0>\;
LMB_Data_Write_23(3) <= \<const0>\;
LMB_Data_Write_23(4) <= \<const0>\;
LMB_Data_Write_23(5) <= \<const0>\;
LMB_Data_Write_23(6) <= \<const0>\;
LMB_Data_Write_23(7) <= \<const0>\;
LMB_Data_Write_23(8) <= \<const0>\;
LMB_Data_Write_23(9) <= \<const0>\;
LMB_Data_Write_23(10) <= \<const0>\;
LMB_Data_Write_23(11) <= \<const0>\;
LMB_Data_Write_23(12) <= \<const0>\;
LMB_Data_Write_23(13) <= \<const0>\;
LMB_Data_Write_23(14) <= \<const0>\;
LMB_Data_Write_23(15) <= \<const0>\;
LMB_Data_Write_23(16) <= \<const0>\;
LMB_Data_Write_23(17) <= \<const0>\;
LMB_Data_Write_23(18) <= \<const0>\;
LMB_Data_Write_23(19) <= \<const0>\;
LMB_Data_Write_23(20) <= \<const0>\;
LMB_Data_Write_23(21) <= \<const0>\;
LMB_Data_Write_23(22) <= \<const0>\;
LMB_Data_Write_23(23) <= \<const0>\;
LMB_Data_Write_23(24) <= \<const0>\;
LMB_Data_Write_23(25) <= \<const0>\;
LMB_Data_Write_23(26) <= \<const0>\;
LMB_Data_Write_23(27) <= \<const0>\;
LMB_Data_Write_23(28) <= \<const0>\;
LMB_Data_Write_23(29) <= \<const0>\;
LMB_Data_Write_23(30) <= \<const0>\;
LMB_Data_Write_23(31) <= \<const0>\;
LMB_Data_Write_24(0) <= \<const0>\;
LMB_Data_Write_24(1) <= \<const0>\;
LMB_Data_Write_24(2) <= \<const0>\;
LMB_Data_Write_24(3) <= \<const0>\;
LMB_Data_Write_24(4) <= \<const0>\;
LMB_Data_Write_24(5) <= \<const0>\;
LMB_Data_Write_24(6) <= \<const0>\;
LMB_Data_Write_24(7) <= \<const0>\;
LMB_Data_Write_24(8) <= \<const0>\;
LMB_Data_Write_24(9) <= \<const0>\;
LMB_Data_Write_24(10) <= \<const0>\;
LMB_Data_Write_24(11) <= \<const0>\;
LMB_Data_Write_24(12) <= \<const0>\;
LMB_Data_Write_24(13) <= \<const0>\;
LMB_Data_Write_24(14) <= \<const0>\;
LMB_Data_Write_24(15) <= \<const0>\;
LMB_Data_Write_24(16) <= \<const0>\;
LMB_Data_Write_24(17) <= \<const0>\;
LMB_Data_Write_24(18) <= \<const0>\;
LMB_Data_Write_24(19) <= \<const0>\;
LMB_Data_Write_24(20) <= \<const0>\;
LMB_Data_Write_24(21) <= \<const0>\;
LMB_Data_Write_24(22) <= \<const0>\;
LMB_Data_Write_24(23) <= \<const0>\;
LMB_Data_Write_24(24) <= \<const0>\;
LMB_Data_Write_24(25) <= \<const0>\;
LMB_Data_Write_24(26) <= \<const0>\;
LMB_Data_Write_24(27) <= \<const0>\;
LMB_Data_Write_24(28) <= \<const0>\;
LMB_Data_Write_24(29) <= \<const0>\;
LMB_Data_Write_24(30) <= \<const0>\;
LMB_Data_Write_24(31) <= \<const0>\;
LMB_Data_Write_25(0) <= \<const0>\;
LMB_Data_Write_25(1) <= \<const0>\;
LMB_Data_Write_25(2) <= \<const0>\;
LMB_Data_Write_25(3) <= \<const0>\;
LMB_Data_Write_25(4) <= \<const0>\;
LMB_Data_Write_25(5) <= \<const0>\;
LMB_Data_Write_25(6) <= \<const0>\;
LMB_Data_Write_25(7) <= \<const0>\;
LMB_Data_Write_25(8) <= \<const0>\;
LMB_Data_Write_25(9) <= \<const0>\;
LMB_Data_Write_25(10) <= \<const0>\;
LMB_Data_Write_25(11) <= \<const0>\;
LMB_Data_Write_25(12) <= \<const0>\;
LMB_Data_Write_25(13) <= \<const0>\;
LMB_Data_Write_25(14) <= \<const0>\;
LMB_Data_Write_25(15) <= \<const0>\;
LMB_Data_Write_25(16) <= \<const0>\;
LMB_Data_Write_25(17) <= \<const0>\;
LMB_Data_Write_25(18) <= \<const0>\;
LMB_Data_Write_25(19) <= \<const0>\;
LMB_Data_Write_25(20) <= \<const0>\;
LMB_Data_Write_25(21) <= \<const0>\;
LMB_Data_Write_25(22) <= \<const0>\;
LMB_Data_Write_25(23) <= \<const0>\;
LMB_Data_Write_25(24) <= \<const0>\;
LMB_Data_Write_25(25) <= \<const0>\;
LMB_Data_Write_25(26) <= \<const0>\;
LMB_Data_Write_25(27) <= \<const0>\;
LMB_Data_Write_25(28) <= \<const0>\;
LMB_Data_Write_25(29) <= \<const0>\;
LMB_Data_Write_25(30) <= \<const0>\;
LMB_Data_Write_25(31) <= \<const0>\;
LMB_Data_Write_26(0) <= \<const0>\;
LMB_Data_Write_26(1) <= \<const0>\;
LMB_Data_Write_26(2) <= \<const0>\;
LMB_Data_Write_26(3) <= \<const0>\;
LMB_Data_Write_26(4) <= \<const0>\;
LMB_Data_Write_26(5) <= \<const0>\;
LMB_Data_Write_26(6) <= \<const0>\;
LMB_Data_Write_26(7) <= \<const0>\;
LMB_Data_Write_26(8) <= \<const0>\;
LMB_Data_Write_26(9) <= \<const0>\;
LMB_Data_Write_26(10) <= \<const0>\;
LMB_Data_Write_26(11) <= \<const0>\;
LMB_Data_Write_26(12) <= \<const0>\;
LMB_Data_Write_26(13) <= \<const0>\;
LMB_Data_Write_26(14) <= \<const0>\;
LMB_Data_Write_26(15) <= \<const0>\;
LMB_Data_Write_26(16) <= \<const0>\;
LMB_Data_Write_26(17) <= \<const0>\;
LMB_Data_Write_26(18) <= \<const0>\;
LMB_Data_Write_26(19) <= \<const0>\;
LMB_Data_Write_26(20) <= \<const0>\;
LMB_Data_Write_26(21) <= \<const0>\;
LMB_Data_Write_26(22) <= \<const0>\;
LMB_Data_Write_26(23) <= \<const0>\;
LMB_Data_Write_26(24) <= \<const0>\;
LMB_Data_Write_26(25) <= \<const0>\;
LMB_Data_Write_26(26) <= \<const0>\;
LMB_Data_Write_26(27) <= \<const0>\;
LMB_Data_Write_26(28) <= \<const0>\;
LMB_Data_Write_26(29) <= \<const0>\;
LMB_Data_Write_26(30) <= \<const0>\;
LMB_Data_Write_26(31) <= \<const0>\;
LMB_Data_Write_27(0) <= \<const0>\;
LMB_Data_Write_27(1) <= \<const0>\;
LMB_Data_Write_27(2) <= \<const0>\;
LMB_Data_Write_27(3) <= \<const0>\;
LMB_Data_Write_27(4) <= \<const0>\;
LMB_Data_Write_27(5) <= \<const0>\;
LMB_Data_Write_27(6) <= \<const0>\;
LMB_Data_Write_27(7) <= \<const0>\;
LMB_Data_Write_27(8) <= \<const0>\;
LMB_Data_Write_27(9) <= \<const0>\;
LMB_Data_Write_27(10) <= \<const0>\;
LMB_Data_Write_27(11) <= \<const0>\;
LMB_Data_Write_27(12) <= \<const0>\;
LMB_Data_Write_27(13) <= \<const0>\;
LMB_Data_Write_27(14) <= \<const0>\;
LMB_Data_Write_27(15) <= \<const0>\;
LMB_Data_Write_27(16) <= \<const0>\;
LMB_Data_Write_27(17) <= \<const0>\;
LMB_Data_Write_27(18) <= \<const0>\;
LMB_Data_Write_27(19) <= \<const0>\;
LMB_Data_Write_27(20) <= \<const0>\;
LMB_Data_Write_27(21) <= \<const0>\;
LMB_Data_Write_27(22) <= \<const0>\;
LMB_Data_Write_27(23) <= \<const0>\;
LMB_Data_Write_27(24) <= \<const0>\;
LMB_Data_Write_27(25) <= \<const0>\;
LMB_Data_Write_27(26) <= \<const0>\;
LMB_Data_Write_27(27) <= \<const0>\;
LMB_Data_Write_27(28) <= \<const0>\;
LMB_Data_Write_27(29) <= \<const0>\;
LMB_Data_Write_27(30) <= \<const0>\;
LMB_Data_Write_27(31) <= \<const0>\;
LMB_Data_Write_28(0) <= \<const0>\;
LMB_Data_Write_28(1) <= \<const0>\;
LMB_Data_Write_28(2) <= \<const0>\;
LMB_Data_Write_28(3) <= \<const0>\;
LMB_Data_Write_28(4) <= \<const0>\;
LMB_Data_Write_28(5) <= \<const0>\;
LMB_Data_Write_28(6) <= \<const0>\;
LMB_Data_Write_28(7) <= \<const0>\;
LMB_Data_Write_28(8) <= \<const0>\;
LMB_Data_Write_28(9) <= \<const0>\;
LMB_Data_Write_28(10) <= \<const0>\;
LMB_Data_Write_28(11) <= \<const0>\;
LMB_Data_Write_28(12) <= \<const0>\;
LMB_Data_Write_28(13) <= \<const0>\;
LMB_Data_Write_28(14) <= \<const0>\;
LMB_Data_Write_28(15) <= \<const0>\;
LMB_Data_Write_28(16) <= \<const0>\;
LMB_Data_Write_28(17) <= \<const0>\;
LMB_Data_Write_28(18) <= \<const0>\;
LMB_Data_Write_28(19) <= \<const0>\;
LMB_Data_Write_28(20) <= \<const0>\;
LMB_Data_Write_28(21) <= \<const0>\;
LMB_Data_Write_28(22) <= \<const0>\;
LMB_Data_Write_28(23) <= \<const0>\;
LMB_Data_Write_28(24) <= \<const0>\;
LMB_Data_Write_28(25) <= \<const0>\;
LMB_Data_Write_28(26) <= \<const0>\;
LMB_Data_Write_28(27) <= \<const0>\;
LMB_Data_Write_28(28) <= \<const0>\;
LMB_Data_Write_28(29) <= \<const0>\;
LMB_Data_Write_28(30) <= \<const0>\;
LMB_Data_Write_28(31) <= \<const0>\;
LMB_Data_Write_29(0) <= \<const0>\;
LMB_Data_Write_29(1) <= \<const0>\;
LMB_Data_Write_29(2) <= \<const0>\;
LMB_Data_Write_29(3) <= \<const0>\;
LMB_Data_Write_29(4) <= \<const0>\;
LMB_Data_Write_29(5) <= \<const0>\;
LMB_Data_Write_29(6) <= \<const0>\;
LMB_Data_Write_29(7) <= \<const0>\;
LMB_Data_Write_29(8) <= \<const0>\;
LMB_Data_Write_29(9) <= \<const0>\;
LMB_Data_Write_29(10) <= \<const0>\;
LMB_Data_Write_29(11) <= \<const0>\;
LMB_Data_Write_29(12) <= \<const0>\;
LMB_Data_Write_29(13) <= \<const0>\;
LMB_Data_Write_29(14) <= \<const0>\;
LMB_Data_Write_29(15) <= \<const0>\;
LMB_Data_Write_29(16) <= \<const0>\;
LMB_Data_Write_29(17) <= \<const0>\;
LMB_Data_Write_29(18) <= \<const0>\;
LMB_Data_Write_29(19) <= \<const0>\;
LMB_Data_Write_29(20) <= \<const0>\;
LMB_Data_Write_29(21) <= \<const0>\;
LMB_Data_Write_29(22) <= \<const0>\;
LMB_Data_Write_29(23) <= \<const0>\;
LMB_Data_Write_29(24) <= \<const0>\;
LMB_Data_Write_29(25) <= \<const0>\;
LMB_Data_Write_29(26) <= \<const0>\;
LMB_Data_Write_29(27) <= \<const0>\;
LMB_Data_Write_29(28) <= \<const0>\;
LMB_Data_Write_29(29) <= \<const0>\;
LMB_Data_Write_29(30) <= \<const0>\;
LMB_Data_Write_29(31) <= \<const0>\;
LMB_Data_Write_3(0) <= \<const0>\;
LMB_Data_Write_3(1) <= \<const0>\;
LMB_Data_Write_3(2) <= \<const0>\;
LMB_Data_Write_3(3) <= \<const0>\;
LMB_Data_Write_3(4) <= \<const0>\;
LMB_Data_Write_3(5) <= \<const0>\;
LMB_Data_Write_3(6) <= \<const0>\;
LMB_Data_Write_3(7) <= \<const0>\;
LMB_Data_Write_3(8) <= \<const0>\;
LMB_Data_Write_3(9) <= \<const0>\;
LMB_Data_Write_3(10) <= \<const0>\;
LMB_Data_Write_3(11) <= \<const0>\;
LMB_Data_Write_3(12) <= \<const0>\;
LMB_Data_Write_3(13) <= \<const0>\;
LMB_Data_Write_3(14) <= \<const0>\;
LMB_Data_Write_3(15) <= \<const0>\;
LMB_Data_Write_3(16) <= \<const0>\;
LMB_Data_Write_3(17) <= \<const0>\;
LMB_Data_Write_3(18) <= \<const0>\;
LMB_Data_Write_3(19) <= \<const0>\;
LMB_Data_Write_3(20) <= \<const0>\;
LMB_Data_Write_3(21) <= \<const0>\;
LMB_Data_Write_3(22) <= \<const0>\;
LMB_Data_Write_3(23) <= \<const0>\;
LMB_Data_Write_3(24) <= \<const0>\;
LMB_Data_Write_3(25) <= \<const0>\;
LMB_Data_Write_3(26) <= \<const0>\;
LMB_Data_Write_3(27) <= \<const0>\;
LMB_Data_Write_3(28) <= \<const0>\;
LMB_Data_Write_3(29) <= \<const0>\;
LMB_Data_Write_3(30) <= \<const0>\;
LMB_Data_Write_3(31) <= \<const0>\;
LMB_Data_Write_30(0) <= \<const0>\;
LMB_Data_Write_30(1) <= \<const0>\;
LMB_Data_Write_30(2) <= \<const0>\;
LMB_Data_Write_30(3) <= \<const0>\;
LMB_Data_Write_30(4) <= \<const0>\;
LMB_Data_Write_30(5) <= \<const0>\;
LMB_Data_Write_30(6) <= \<const0>\;
LMB_Data_Write_30(7) <= \<const0>\;
LMB_Data_Write_30(8) <= \<const0>\;
LMB_Data_Write_30(9) <= \<const0>\;
LMB_Data_Write_30(10) <= \<const0>\;
LMB_Data_Write_30(11) <= \<const0>\;
LMB_Data_Write_30(12) <= \<const0>\;
LMB_Data_Write_30(13) <= \<const0>\;
LMB_Data_Write_30(14) <= \<const0>\;
LMB_Data_Write_30(15) <= \<const0>\;
LMB_Data_Write_30(16) <= \<const0>\;
LMB_Data_Write_30(17) <= \<const0>\;
LMB_Data_Write_30(18) <= \<const0>\;
LMB_Data_Write_30(19) <= \<const0>\;
LMB_Data_Write_30(20) <= \<const0>\;
LMB_Data_Write_30(21) <= \<const0>\;
LMB_Data_Write_30(22) <= \<const0>\;
LMB_Data_Write_30(23) <= \<const0>\;
LMB_Data_Write_30(24) <= \<const0>\;
LMB_Data_Write_30(25) <= \<const0>\;
LMB_Data_Write_30(26) <= \<const0>\;
LMB_Data_Write_30(27) <= \<const0>\;
LMB_Data_Write_30(28) <= \<const0>\;
LMB_Data_Write_30(29) <= \<const0>\;
LMB_Data_Write_30(30) <= \<const0>\;
LMB_Data_Write_30(31) <= \<const0>\;
LMB_Data_Write_31(0) <= \<const0>\;
LMB_Data_Write_31(1) <= \<const0>\;
LMB_Data_Write_31(2) <= \<const0>\;
LMB_Data_Write_31(3) <= \<const0>\;
LMB_Data_Write_31(4) <= \<const0>\;
LMB_Data_Write_31(5) <= \<const0>\;
LMB_Data_Write_31(6) <= \<const0>\;
LMB_Data_Write_31(7) <= \<const0>\;
LMB_Data_Write_31(8) <= \<const0>\;
LMB_Data_Write_31(9) <= \<const0>\;
LMB_Data_Write_31(10) <= \<const0>\;
LMB_Data_Write_31(11) <= \<const0>\;
LMB_Data_Write_31(12) <= \<const0>\;
LMB_Data_Write_31(13) <= \<const0>\;
LMB_Data_Write_31(14) <= \<const0>\;
LMB_Data_Write_31(15) <= \<const0>\;
LMB_Data_Write_31(16) <= \<const0>\;
LMB_Data_Write_31(17) <= \<const0>\;
LMB_Data_Write_31(18) <= \<const0>\;
LMB_Data_Write_31(19) <= \<const0>\;
LMB_Data_Write_31(20) <= \<const0>\;
LMB_Data_Write_31(21) <= \<const0>\;
LMB_Data_Write_31(22) <= \<const0>\;
LMB_Data_Write_31(23) <= \<const0>\;
LMB_Data_Write_31(24) <= \<const0>\;
LMB_Data_Write_31(25) <= \<const0>\;
LMB_Data_Write_31(26) <= \<const0>\;
LMB_Data_Write_31(27) <= \<const0>\;
LMB_Data_Write_31(28) <= \<const0>\;
LMB_Data_Write_31(29) <= \<const0>\;
LMB_Data_Write_31(30) <= \<const0>\;
LMB_Data_Write_31(31) <= \<const0>\;
LMB_Data_Write_4(0) <= \<const0>\;
LMB_Data_Write_4(1) <= \<const0>\;
LMB_Data_Write_4(2) <= \<const0>\;
LMB_Data_Write_4(3) <= \<const0>\;
LMB_Data_Write_4(4) <= \<const0>\;
LMB_Data_Write_4(5) <= \<const0>\;
LMB_Data_Write_4(6) <= \<const0>\;
LMB_Data_Write_4(7) <= \<const0>\;
LMB_Data_Write_4(8) <= \<const0>\;
LMB_Data_Write_4(9) <= \<const0>\;
LMB_Data_Write_4(10) <= \<const0>\;
LMB_Data_Write_4(11) <= \<const0>\;
LMB_Data_Write_4(12) <= \<const0>\;
LMB_Data_Write_4(13) <= \<const0>\;
LMB_Data_Write_4(14) <= \<const0>\;
LMB_Data_Write_4(15) <= \<const0>\;
LMB_Data_Write_4(16) <= \<const0>\;
LMB_Data_Write_4(17) <= \<const0>\;
LMB_Data_Write_4(18) <= \<const0>\;
LMB_Data_Write_4(19) <= \<const0>\;
LMB_Data_Write_4(20) <= \<const0>\;
LMB_Data_Write_4(21) <= \<const0>\;
LMB_Data_Write_4(22) <= \<const0>\;
LMB_Data_Write_4(23) <= \<const0>\;
LMB_Data_Write_4(24) <= \<const0>\;
LMB_Data_Write_4(25) <= \<const0>\;
LMB_Data_Write_4(26) <= \<const0>\;
LMB_Data_Write_4(27) <= \<const0>\;
LMB_Data_Write_4(28) <= \<const0>\;
LMB_Data_Write_4(29) <= \<const0>\;
LMB_Data_Write_4(30) <= \<const0>\;
LMB_Data_Write_4(31) <= \<const0>\;
LMB_Data_Write_5(0) <= \<const0>\;
LMB_Data_Write_5(1) <= \<const0>\;
LMB_Data_Write_5(2) <= \<const0>\;
LMB_Data_Write_5(3) <= \<const0>\;
LMB_Data_Write_5(4) <= \<const0>\;
LMB_Data_Write_5(5) <= \<const0>\;
LMB_Data_Write_5(6) <= \<const0>\;
LMB_Data_Write_5(7) <= \<const0>\;
LMB_Data_Write_5(8) <= \<const0>\;
LMB_Data_Write_5(9) <= \<const0>\;
LMB_Data_Write_5(10) <= \<const0>\;
LMB_Data_Write_5(11) <= \<const0>\;
LMB_Data_Write_5(12) <= \<const0>\;
LMB_Data_Write_5(13) <= \<const0>\;
LMB_Data_Write_5(14) <= \<const0>\;
LMB_Data_Write_5(15) <= \<const0>\;
LMB_Data_Write_5(16) <= \<const0>\;
LMB_Data_Write_5(17) <= \<const0>\;
LMB_Data_Write_5(18) <= \<const0>\;
LMB_Data_Write_5(19) <= \<const0>\;
LMB_Data_Write_5(20) <= \<const0>\;
LMB_Data_Write_5(21) <= \<const0>\;
LMB_Data_Write_5(22) <= \<const0>\;
LMB_Data_Write_5(23) <= \<const0>\;
LMB_Data_Write_5(24) <= \<const0>\;
LMB_Data_Write_5(25) <= \<const0>\;
LMB_Data_Write_5(26) <= \<const0>\;
LMB_Data_Write_5(27) <= \<const0>\;
LMB_Data_Write_5(28) <= \<const0>\;
LMB_Data_Write_5(29) <= \<const0>\;
LMB_Data_Write_5(30) <= \<const0>\;
LMB_Data_Write_5(31) <= \<const0>\;
LMB_Data_Write_6(0) <= \<const0>\;
LMB_Data_Write_6(1) <= \<const0>\;
LMB_Data_Write_6(2) <= \<const0>\;
LMB_Data_Write_6(3) <= \<const0>\;
LMB_Data_Write_6(4) <= \<const0>\;
LMB_Data_Write_6(5) <= \<const0>\;
LMB_Data_Write_6(6) <= \<const0>\;
LMB_Data_Write_6(7) <= \<const0>\;
LMB_Data_Write_6(8) <= \<const0>\;
LMB_Data_Write_6(9) <= \<const0>\;
LMB_Data_Write_6(10) <= \<const0>\;
LMB_Data_Write_6(11) <= \<const0>\;
LMB_Data_Write_6(12) <= \<const0>\;
LMB_Data_Write_6(13) <= \<const0>\;
LMB_Data_Write_6(14) <= \<const0>\;
LMB_Data_Write_6(15) <= \<const0>\;
LMB_Data_Write_6(16) <= \<const0>\;
LMB_Data_Write_6(17) <= \<const0>\;
LMB_Data_Write_6(18) <= \<const0>\;
LMB_Data_Write_6(19) <= \<const0>\;
LMB_Data_Write_6(20) <= \<const0>\;
LMB_Data_Write_6(21) <= \<const0>\;
LMB_Data_Write_6(22) <= \<const0>\;
LMB_Data_Write_6(23) <= \<const0>\;
LMB_Data_Write_6(24) <= \<const0>\;
LMB_Data_Write_6(25) <= \<const0>\;
LMB_Data_Write_6(26) <= \<const0>\;
LMB_Data_Write_6(27) <= \<const0>\;
LMB_Data_Write_6(28) <= \<const0>\;
LMB_Data_Write_6(29) <= \<const0>\;
LMB_Data_Write_6(30) <= \<const0>\;
LMB_Data_Write_6(31) <= \<const0>\;
LMB_Data_Write_7(0) <= \<const0>\;
LMB_Data_Write_7(1) <= \<const0>\;
LMB_Data_Write_7(2) <= \<const0>\;
LMB_Data_Write_7(3) <= \<const0>\;
LMB_Data_Write_7(4) <= \<const0>\;
LMB_Data_Write_7(5) <= \<const0>\;
LMB_Data_Write_7(6) <= \<const0>\;
LMB_Data_Write_7(7) <= \<const0>\;
LMB_Data_Write_7(8) <= \<const0>\;
LMB_Data_Write_7(9) <= \<const0>\;
LMB_Data_Write_7(10) <= \<const0>\;
LMB_Data_Write_7(11) <= \<const0>\;
LMB_Data_Write_7(12) <= \<const0>\;
LMB_Data_Write_7(13) <= \<const0>\;
LMB_Data_Write_7(14) <= \<const0>\;
LMB_Data_Write_7(15) <= \<const0>\;
LMB_Data_Write_7(16) <= \<const0>\;
LMB_Data_Write_7(17) <= \<const0>\;
LMB_Data_Write_7(18) <= \<const0>\;
LMB_Data_Write_7(19) <= \<const0>\;
LMB_Data_Write_7(20) <= \<const0>\;
LMB_Data_Write_7(21) <= \<const0>\;
LMB_Data_Write_7(22) <= \<const0>\;
LMB_Data_Write_7(23) <= \<const0>\;
LMB_Data_Write_7(24) <= \<const0>\;
LMB_Data_Write_7(25) <= \<const0>\;
LMB_Data_Write_7(26) <= \<const0>\;
LMB_Data_Write_7(27) <= \<const0>\;
LMB_Data_Write_7(28) <= \<const0>\;
LMB_Data_Write_7(29) <= \<const0>\;
LMB_Data_Write_7(30) <= \<const0>\;
LMB_Data_Write_7(31) <= \<const0>\;
LMB_Data_Write_8(0) <= \<const0>\;
LMB_Data_Write_8(1) <= \<const0>\;
LMB_Data_Write_8(2) <= \<const0>\;
LMB_Data_Write_8(3) <= \<const0>\;
LMB_Data_Write_8(4) <= \<const0>\;
LMB_Data_Write_8(5) <= \<const0>\;
LMB_Data_Write_8(6) <= \<const0>\;
LMB_Data_Write_8(7) <= \<const0>\;
LMB_Data_Write_8(8) <= \<const0>\;
LMB_Data_Write_8(9) <= \<const0>\;
LMB_Data_Write_8(10) <= \<const0>\;
LMB_Data_Write_8(11) <= \<const0>\;
LMB_Data_Write_8(12) <= \<const0>\;
LMB_Data_Write_8(13) <= \<const0>\;
LMB_Data_Write_8(14) <= \<const0>\;
LMB_Data_Write_8(15) <= \<const0>\;
LMB_Data_Write_8(16) <= \<const0>\;
LMB_Data_Write_8(17) <= \<const0>\;
LMB_Data_Write_8(18) <= \<const0>\;
LMB_Data_Write_8(19) <= \<const0>\;
LMB_Data_Write_8(20) <= \<const0>\;
LMB_Data_Write_8(21) <= \<const0>\;
LMB_Data_Write_8(22) <= \<const0>\;
LMB_Data_Write_8(23) <= \<const0>\;
LMB_Data_Write_8(24) <= \<const0>\;
LMB_Data_Write_8(25) <= \<const0>\;
LMB_Data_Write_8(26) <= \<const0>\;
LMB_Data_Write_8(27) <= \<const0>\;
LMB_Data_Write_8(28) <= \<const0>\;
LMB_Data_Write_8(29) <= \<const0>\;
LMB_Data_Write_8(30) <= \<const0>\;
LMB_Data_Write_8(31) <= \<const0>\;
LMB_Data_Write_9(0) <= \<const0>\;
LMB_Data_Write_9(1) <= \<const0>\;
LMB_Data_Write_9(2) <= \<const0>\;
LMB_Data_Write_9(3) <= \<const0>\;
LMB_Data_Write_9(4) <= \<const0>\;
LMB_Data_Write_9(5) <= \<const0>\;
LMB_Data_Write_9(6) <= \<const0>\;
LMB_Data_Write_9(7) <= \<const0>\;
LMB_Data_Write_9(8) <= \<const0>\;
LMB_Data_Write_9(9) <= \<const0>\;
LMB_Data_Write_9(10) <= \<const0>\;
LMB_Data_Write_9(11) <= \<const0>\;
LMB_Data_Write_9(12) <= \<const0>\;
LMB_Data_Write_9(13) <= \<const0>\;
LMB_Data_Write_9(14) <= \<const0>\;
LMB_Data_Write_9(15) <= \<const0>\;
LMB_Data_Write_9(16) <= \<const0>\;
LMB_Data_Write_9(17) <= \<const0>\;
LMB_Data_Write_9(18) <= \<const0>\;
LMB_Data_Write_9(19) <= \<const0>\;
LMB_Data_Write_9(20) <= \<const0>\;
LMB_Data_Write_9(21) <= \<const0>\;
LMB_Data_Write_9(22) <= \<const0>\;
LMB_Data_Write_9(23) <= \<const0>\;
LMB_Data_Write_9(24) <= \<const0>\;
LMB_Data_Write_9(25) <= \<const0>\;
LMB_Data_Write_9(26) <= \<const0>\;
LMB_Data_Write_9(27) <= \<const0>\;
LMB_Data_Write_9(28) <= \<const0>\;
LMB_Data_Write_9(29) <= \<const0>\;
LMB_Data_Write_9(30) <= \<const0>\;
LMB_Data_Write_9(31) <= \<const0>\;
LMB_Read_Strobe_0 <= \<const0>\;
LMB_Read_Strobe_1 <= \<const0>\;
LMB_Read_Strobe_10 <= \<const0>\;
LMB_Read_Strobe_11 <= \<const0>\;
LMB_Read_Strobe_12 <= \<const0>\;
LMB_Read_Strobe_13 <= \<const0>\;
LMB_Read_Strobe_14 <= \<const0>\;
LMB_Read_Strobe_15 <= \<const0>\;
LMB_Read_Strobe_16 <= \<const0>\;
LMB_Read_Strobe_17 <= \<const0>\;
LMB_Read_Strobe_18 <= \<const0>\;
LMB_Read_Strobe_19 <= \<const0>\;
LMB_Read_Strobe_2 <= \<const0>\;
LMB_Read_Strobe_20 <= \<const0>\;
LMB_Read_Strobe_21 <= \<const0>\;
LMB_Read_Strobe_22 <= \<const0>\;
LMB_Read_Strobe_23 <= \<const0>\;
LMB_Read_Strobe_24 <= \<const0>\;
LMB_Read_Strobe_25 <= \<const0>\;
LMB_Read_Strobe_26 <= \<const0>\;
LMB_Read_Strobe_27 <= \<const0>\;
LMB_Read_Strobe_28 <= \<const0>\;
LMB_Read_Strobe_29 <= \<const0>\;
LMB_Read_Strobe_3 <= \<const0>\;
LMB_Read_Strobe_30 <= \<const0>\;
LMB_Read_Strobe_31 <= \<const0>\;
LMB_Read_Strobe_4 <= \<const0>\;
LMB_Read_Strobe_5 <= \<const0>\;
LMB_Read_Strobe_6 <= \<const0>\;
LMB_Read_Strobe_7 <= \<const0>\;
LMB_Read_Strobe_8 <= \<const0>\;
LMB_Read_Strobe_9 <= \<const0>\;
LMB_Write_Strobe_0 <= \<const0>\;
LMB_Write_Strobe_1 <= \<const0>\;
LMB_Write_Strobe_10 <= \<const0>\;
LMB_Write_Strobe_11 <= \<const0>\;
LMB_Write_Strobe_12 <= \<const0>\;
LMB_Write_Strobe_13 <= \<const0>\;
LMB_Write_Strobe_14 <= \<const0>\;
LMB_Write_Strobe_15 <= \<const0>\;
LMB_Write_Strobe_16 <= \<const0>\;
LMB_Write_Strobe_17 <= \<const0>\;
LMB_Write_Strobe_18 <= \<const0>\;
LMB_Write_Strobe_19 <= \<const0>\;
LMB_Write_Strobe_2 <= \<const0>\;
LMB_Write_Strobe_20 <= \<const0>\;
LMB_Write_Strobe_21 <= \<const0>\;
LMB_Write_Strobe_22 <= \<const0>\;
LMB_Write_Strobe_23 <= \<const0>\;
LMB_Write_Strobe_24 <= \<const0>\;
LMB_Write_Strobe_25 <= \<const0>\;
LMB_Write_Strobe_26 <= \<const0>\;
LMB_Write_Strobe_27 <= \<const0>\;
LMB_Write_Strobe_28 <= \<const0>\;
LMB_Write_Strobe_29 <= \<const0>\;
LMB_Write_Strobe_3 <= \<const0>\;
LMB_Write_Strobe_30 <= \<const0>\;
LMB_Write_Strobe_31 <= \<const0>\;
LMB_Write_Strobe_4 <= \<const0>\;
LMB_Write_Strobe_5 <= \<const0>\;
LMB_Write_Strobe_6 <= \<const0>\;
LMB_Write_Strobe_7 <= \<const0>\;
LMB_Write_Strobe_8 <= \<const0>\;
LMB_Write_Strobe_9 <= \<const0>\;
M_AXIS_TDATA(31) <= \<const0>\;
M_AXIS_TDATA(30) <= \<const0>\;
M_AXIS_TDATA(29) <= \<const0>\;
M_AXIS_TDATA(28) <= \<const0>\;
M_AXIS_TDATA(27) <= \<const0>\;
M_AXIS_TDATA(26) <= \<const0>\;
M_AXIS_TDATA(25) <= \<const0>\;
M_AXIS_TDATA(24) <= \<const0>\;
M_AXIS_TDATA(23) <= \<const0>\;
M_AXIS_TDATA(22) <= \<const0>\;
M_AXIS_TDATA(21) <= \<const0>\;
M_AXIS_TDATA(20) <= \<const0>\;
M_AXIS_TDATA(19) <= \<const0>\;
M_AXIS_TDATA(18) <= \<const0>\;
M_AXIS_TDATA(17) <= \<const0>\;
M_AXIS_TDATA(16) <= \<const0>\;
M_AXIS_TDATA(15) <= \<const0>\;
M_AXIS_TDATA(14) <= \<const0>\;
M_AXIS_TDATA(13) <= \<const0>\;
M_AXIS_TDATA(12) <= \<const0>\;
M_AXIS_TDATA(11) <= \<const0>\;
M_AXIS_TDATA(10) <= \<const0>\;
M_AXIS_TDATA(9) <= \<const0>\;
M_AXIS_TDATA(8) <= \<const0>\;
M_AXIS_TDATA(7) <= \<const0>\;
M_AXIS_TDATA(6) <= \<const0>\;
M_AXIS_TDATA(5) <= \<const0>\;
M_AXIS_TDATA(4) <= \<const0>\;
M_AXIS_TDATA(3) <= \<const0>\;
M_AXIS_TDATA(2) <= \<const0>\;
M_AXIS_TDATA(1) <= \<const0>\;
M_AXIS_TDATA(0) <= \<const0>\;
M_AXIS_TID(6) <= \<const0>\;
M_AXIS_TID(5) <= \<const0>\;
M_AXIS_TID(4) <= \<const0>\;
M_AXIS_TID(3) <= \<const0>\;
M_AXIS_TID(2) <= \<const0>\;
M_AXIS_TID(1) <= \<const0>\;
M_AXIS_TID(0) <= \<const0>\;
M_AXIS_TVALID <= \<const0>\;
M_AXI_ARADDR(31) <= \<const0>\;
M_AXI_ARADDR(30) <= \<const0>\;
M_AXI_ARADDR(29) <= \<const0>\;
M_AXI_ARADDR(28) <= \<const0>\;
M_AXI_ARADDR(27) <= \<const0>\;
M_AXI_ARADDR(26) <= \<const0>\;
M_AXI_ARADDR(25) <= \<const0>\;
M_AXI_ARADDR(24) <= \<const0>\;
M_AXI_ARADDR(23) <= \<const0>\;
M_AXI_ARADDR(22) <= \<const0>\;
M_AXI_ARADDR(21) <= \<const0>\;
M_AXI_ARADDR(20) <= \<const0>\;
M_AXI_ARADDR(19) <= \<const0>\;
M_AXI_ARADDR(18) <= \<const0>\;
M_AXI_ARADDR(17) <= \<const0>\;
M_AXI_ARADDR(16) <= \<const0>\;
M_AXI_ARADDR(15) <= \<const0>\;
M_AXI_ARADDR(14) <= \<const0>\;
M_AXI_ARADDR(13) <= \<const0>\;
M_AXI_ARADDR(12) <= \<const0>\;
M_AXI_ARADDR(11) <= \<const0>\;
M_AXI_ARADDR(10) <= \<const0>\;
M_AXI_ARADDR(9) <= \<const0>\;
M_AXI_ARADDR(8) <= \<const0>\;
M_AXI_ARADDR(7) <= \<const0>\;
M_AXI_ARADDR(6) <= \<const0>\;
M_AXI_ARADDR(5) <= \<const0>\;
M_AXI_ARADDR(4) <= \<const0>\;
M_AXI_ARADDR(3) <= \<const0>\;
M_AXI_ARADDR(2) <= \<const0>\;
M_AXI_ARADDR(1) <= \<const0>\;
M_AXI_ARADDR(0) <= \<const0>\;
M_AXI_ARBURST(1) <= \<const0>\;
M_AXI_ARBURST(0) <= \<const0>\;
M_AXI_ARCACHE(3) <= \<const0>\;
M_AXI_ARCACHE(2) <= \<const0>\;
M_AXI_ARCACHE(1) <= \<const0>\;
M_AXI_ARCACHE(0) <= \<const0>\;
M_AXI_ARID(0) <= \<const0>\;
M_AXI_ARLEN(7) <= \<const0>\;
M_AXI_ARLEN(6) <= \<const0>\;
M_AXI_ARLEN(5) <= \<const0>\;
M_AXI_ARLEN(4) <= \<const0>\;
M_AXI_ARLEN(3) <= \<const0>\;
M_AXI_ARLEN(2) <= \<const0>\;
M_AXI_ARLEN(1) <= \<const0>\;
M_AXI_ARLEN(0) <= \<const0>\;
M_AXI_ARLOCK <= \<const0>\;
M_AXI_ARPROT(2) <= \<const0>\;
M_AXI_ARPROT(1) <= \<const0>\;
M_AXI_ARPROT(0) <= \<const0>\;
M_AXI_ARQOS(3) <= \<const0>\;
M_AXI_ARQOS(2) <= \<const0>\;
M_AXI_ARQOS(1) <= \<const0>\;
M_AXI_ARQOS(0) <= \<const0>\;
M_AXI_ARSIZE(2) <= \<const0>\;
M_AXI_ARSIZE(1) <= \<const0>\;
M_AXI_ARSIZE(0) <= \<const0>\;
M_AXI_ARVALID <= \<const0>\;
M_AXI_AWADDR(31) <= \<const0>\;
M_AXI_AWADDR(30) <= \<const0>\;
M_AXI_AWADDR(29) <= \<const0>\;
M_AXI_AWADDR(28) <= \<const0>\;
M_AXI_AWADDR(27) <= \<const0>\;
M_AXI_AWADDR(26) <= \<const0>\;
M_AXI_AWADDR(25) <= \<const0>\;
M_AXI_AWADDR(24) <= \<const0>\;
M_AXI_AWADDR(23) <= \<const0>\;
M_AXI_AWADDR(22) <= \<const0>\;
M_AXI_AWADDR(21) <= \<const0>\;
M_AXI_AWADDR(20) <= \<const0>\;
M_AXI_AWADDR(19) <= \<const0>\;
M_AXI_AWADDR(18) <= \<const0>\;
M_AXI_AWADDR(17) <= \<const0>\;
M_AXI_AWADDR(16) <= \<const0>\;
M_AXI_AWADDR(15) <= \<const0>\;
M_AXI_AWADDR(14) <= \<const0>\;
M_AXI_AWADDR(13) <= \<const0>\;
M_AXI_AWADDR(12) <= \<const0>\;
M_AXI_AWADDR(11) <= \<const0>\;
M_AXI_AWADDR(10) <= \<const0>\;
M_AXI_AWADDR(9) <= \<const0>\;
M_AXI_AWADDR(8) <= \<const0>\;
M_AXI_AWADDR(7) <= \<const0>\;
M_AXI_AWADDR(6) <= \<const0>\;
M_AXI_AWADDR(5) <= \<const0>\;
M_AXI_AWADDR(4) <= \<const0>\;
M_AXI_AWADDR(3) <= \<const0>\;
M_AXI_AWADDR(2) <= \<const0>\;
M_AXI_AWADDR(1) <= \<const0>\;
M_AXI_AWADDR(0) <= \<const0>\;
M_AXI_AWBURST(1) <= \<const0>\;
M_AXI_AWBURST(0) <= \<const0>\;
M_AXI_AWCACHE(3) <= \<const0>\;
M_AXI_AWCACHE(2) <= \<const0>\;
M_AXI_AWCACHE(1) <= \<const0>\;
M_AXI_AWCACHE(0) <= \<const0>\;
M_AXI_AWID(0) <= \<const0>\;
M_AXI_AWLEN(7) <= \<const0>\;
M_AXI_AWLEN(6) <= \<const0>\;
M_AXI_AWLEN(5) <= \<const0>\;
M_AXI_AWLEN(4) <= \<const0>\;
M_AXI_AWLEN(3) <= \<const0>\;
M_AXI_AWLEN(2) <= \<const0>\;
M_AXI_AWLEN(1) <= \<const0>\;
M_AXI_AWLEN(0) <= \<const0>\;
M_AXI_AWLOCK <= \<const0>\;
M_AXI_AWPROT(2) <= \<const0>\;
M_AXI_AWPROT(1) <= \<const0>\;
M_AXI_AWPROT(0) <= \<const0>\;
M_AXI_AWQOS(3) <= \<const0>\;
M_AXI_AWQOS(2) <= \<const0>\;
M_AXI_AWQOS(1) <= \<const0>\;
M_AXI_AWQOS(0) <= \<const0>\;
M_AXI_AWSIZE(2) <= \<const0>\;
M_AXI_AWSIZE(1) <= \<const0>\;
M_AXI_AWSIZE(0) <= \<const0>\;
M_AXI_AWVALID <= \<const0>\;
M_AXI_BREADY <= \<const0>\;
M_AXI_RREADY <= \<const0>\;
M_AXI_WDATA(31) <= \<const0>\;
M_AXI_WDATA(30) <= \<const0>\;
M_AXI_WDATA(29) <= \<const0>\;
M_AXI_WDATA(28) <= \<const0>\;
M_AXI_WDATA(27) <= \<const0>\;
M_AXI_WDATA(26) <= \<const0>\;
M_AXI_WDATA(25) <= \<const0>\;
M_AXI_WDATA(24) <= \<const0>\;
M_AXI_WDATA(23) <= \<const0>\;
M_AXI_WDATA(22) <= \<const0>\;
M_AXI_WDATA(21) <= \<const0>\;
M_AXI_WDATA(20) <= \<const0>\;
M_AXI_WDATA(19) <= \<const0>\;
M_AXI_WDATA(18) <= \<const0>\;
M_AXI_WDATA(17) <= \<const0>\;
M_AXI_WDATA(16) <= \<const0>\;
M_AXI_WDATA(15) <= \<const0>\;
M_AXI_WDATA(14) <= \<const0>\;
M_AXI_WDATA(13) <= \<const0>\;
M_AXI_WDATA(12) <= \<const0>\;
M_AXI_WDATA(11) <= \<const0>\;
M_AXI_WDATA(10) <= \<const0>\;
M_AXI_WDATA(9) <= \<const0>\;
M_AXI_WDATA(8) <= \<const0>\;
M_AXI_WDATA(7) <= \<const0>\;
M_AXI_WDATA(6) <= \<const0>\;
M_AXI_WDATA(5) <= \<const0>\;
M_AXI_WDATA(4) <= \<const0>\;
M_AXI_WDATA(3) <= \<const0>\;
M_AXI_WDATA(2) <= \<const0>\;
M_AXI_WDATA(1) <= \<const0>\;
M_AXI_WDATA(0) <= \<const0>\;
M_AXI_WLAST <= \<const0>\;
M_AXI_WSTRB(3) <= \<const0>\;
M_AXI_WSTRB(2) <= \<const0>\;
M_AXI_WSTRB(1) <= \<const0>\;
M_AXI_WSTRB(0) <= \<const0>\;
M_AXI_WVALID <= \<const0>\;
S_AXI_ARREADY <= \<const0>\;
S_AXI_AWREADY <= \<const0>\;
S_AXI_BRESP(1) <= \<const0>\;
S_AXI_BRESP(0) <= \<const0>\;
S_AXI_BVALID <= \<const0>\;
S_AXI_RDATA(31) <= \<const0>\;
S_AXI_RDATA(30) <= \<const0>\;
S_AXI_RDATA(29) <= \<const0>\;
S_AXI_RDATA(28) <= \<const0>\;
S_AXI_RDATA(27) <= \<const0>\;
S_AXI_RDATA(26) <= \<const0>\;
S_AXI_RDATA(25) <= \<const0>\;
S_AXI_RDATA(24) <= \<const0>\;
S_AXI_RDATA(23) <= \<const0>\;
S_AXI_RDATA(22) <= \<const0>\;
S_AXI_RDATA(21) <= \<const0>\;
S_AXI_RDATA(20) <= \<const0>\;
S_AXI_RDATA(19) <= \<const0>\;
S_AXI_RDATA(18) <= \<const0>\;
S_AXI_RDATA(17) <= \<const0>\;
S_AXI_RDATA(16) <= \<const0>\;
S_AXI_RDATA(15) <= \<const0>\;
S_AXI_RDATA(14) <= \<const0>\;
S_AXI_RDATA(13) <= \<const0>\;
S_AXI_RDATA(12) <= \<const0>\;
S_AXI_RDATA(11) <= \<const0>\;
S_AXI_RDATA(10) <= \<const0>\;
S_AXI_RDATA(9) <= \<const0>\;
S_AXI_RDATA(8) <= \<const0>\;
S_AXI_RDATA(7) <= \<const0>\;
S_AXI_RDATA(6) <= \<const0>\;
S_AXI_RDATA(5) <= \<const0>\;
S_AXI_RDATA(4) <= \<const0>\;
S_AXI_RDATA(3) <= \<const0>\;
S_AXI_RDATA(2) <= \<const0>\;
S_AXI_RDATA(1) <= \<const0>\;
S_AXI_RDATA(0) <= \<const0>\;
S_AXI_RRESP(1) <= \<const0>\;
S_AXI_RRESP(0) <= \<const0>\;
S_AXI_RVALID <= \<const0>\;
S_AXI_WREADY <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \<const1>\;
TRACE_DATA(31) <= \<const0>\;
TRACE_DATA(30) <= \<const0>\;
TRACE_DATA(29) <= \<const0>\;
TRACE_DATA(28) <= \<const0>\;
TRACE_DATA(27) <= \<const0>\;
TRACE_DATA(26) <= \<const0>\;
TRACE_DATA(25) <= \<const0>\;
TRACE_DATA(24) <= \<const0>\;
TRACE_DATA(23) <= \<const0>\;
TRACE_DATA(22) <= \<const0>\;
TRACE_DATA(21) <= \<const0>\;
TRACE_DATA(20) <= \<const0>\;
TRACE_DATA(19) <= \<const0>\;
TRACE_DATA(18) <= \<const0>\;
TRACE_DATA(17) <= \<const0>\;
TRACE_DATA(16) <= \<const0>\;
TRACE_DATA(15) <= \<const0>\;
TRACE_DATA(14) <= \<const0>\;
TRACE_DATA(13) <= \<const0>\;
TRACE_DATA(12) <= \<const0>\;
TRACE_DATA(11) <= \<const0>\;
TRACE_DATA(10) <= \<const0>\;
TRACE_DATA(9) <= \<const0>\;
TRACE_DATA(8) <= \<const0>\;
TRACE_DATA(7) <= \<const0>\;
TRACE_DATA(6) <= \<const0>\;
TRACE_DATA(5) <= \<const0>\;
TRACE_DATA(4) <= \<const0>\;
TRACE_DATA(3) <= \<const0>\;
TRACE_DATA(2) <= \<const0>\;
TRACE_DATA(1) <= \<const0>\;
TRACE_DATA(0) <= \<const0>\;
Trig_Ack_In_0 <= \<const0>\;
Trig_Ack_In_1 <= \<const0>\;
Trig_Ack_In_2 <= \<const0>\;
Trig_Ack_In_3 <= \<const0>\;
Trig_Out_0 <= \<const0>\;
Trig_Out_1 <= \<const0>\;
Trig_Out_2 <= \<const0>\;
Trig_Out_3 <= \<const0>\;
bscan_ext_tdo <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
MDM_Core_I1: entity work.system_mdm_1_0_MDM_Core
port map (
AR(0) => sel_n_reset,
D(0) => p_1_in(15),
Dbg_Disable_0 => Dbg_Disable_0,
Dbg_Reg_En_0(0 to 7) => Dbg_Reg_En_0(0 to 7),
Dbg_Rst_0 => Dbg_Rst_0,
Dbg_Shift_0 => \^dbg_shift_0\,
Dbg_TDO_0 => Dbg_TDO_0,
Debug_SYS_Rst => Debug_SYS_Rst,
E(0) => \Use_E2.BSCAN_I_n_8\,
Ext_JTAG_SEL => Ext_JTAG_SEL,
Ext_JTAG_TDI => \^ext_jtag_tdi\,
Ext_JTAG_TDO => Ext_JTAG_TDO,
Ext_NM_BRK => Ext_NM_BRK,
Q(0) => MDM_Core_I1_n_0,
Scan_Reset => Scan_Reset,
Scan_Reset_Sel => Scan_Reset_Sel,
\Use_BSCAN.PORT_Selector_reg[0]_0\ => \^dbg_update_31\,
\Use_BSCAN.PORT_Selector_reg[0]_1\ => \^dbg_clk_31\,
\Use_BSCAN.PORT_Selector_reg[0]_2\ => \^ext_jtag_shift\,
\Use_BSCAN.PORT_Selector_reg[0]_3\ => \^ext_jtag_capture\,
\Use_BSCAN.PORT_Selector_reg[0]_4\ => \Use_E2.BSCAN_I_n_13\,
\Use_Serial_Unified_Completion.completion_status_reg[15]\(0) => MDM_Core_I1_n_19,
\Use_Serial_Unified_Completion.count_reg[4]\(0) => \JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg\(5),
\Use_Serial_Unified_Completion.count_reg[5]\(0) => p_0_in(0),
\command_reg[5]\(0) => \JTAG_CONTROL_I/sel\,
\p_20_out__0\ => \JTAG_CONTROL_I/p_20_out__0\,
\p_43_out__0\ => \JTAG_CONTROL_I/p_43_out__0\,
sel => sel,
\shift_Count_reg[0]\(0) => \p_0_in__0\(0),
shift_n_reset => shift_n_reset,
tdo => tdo
);
\No_Dbg_Reg_Access.BUFG_DRCK\: entity work.system_mdm_1_0_MB_BUFG
port map (
Dbg_Clk_31 => \^dbg_clk_31\,
drck_i => drck_i
);
\Use_E2.BSCAN_I\: entity work.system_mdm_1_0_MB_BSCANE2
port map (
AR(0) => sel_n_reset,
D(0) => p_1_in(15),
Dbg_Capture_0 => \^ext_jtag_capture\,
Dbg_TDO_0 => Dbg_TDO_0,
Dbg_Update_31 => \^dbg_update_31\,
E(0) => \Use_E2.BSCAN_I_n_8\,
Ext_JTAG_RESET => Ext_JTAG_RESET,
Ext_JTAG_TDI => \^ext_jtag_tdi\,
Q(0) => MDM_Core_I1_n_0,
Scan_Reset => Scan_Reset,
Scan_Reset_Sel => Scan_Reset_Sel,
\Use_Serial_Unified_Completion.count_reg[5]\ => \^ext_jtag_shift\,
\Use_Serial_Unified_Completion.count_reg[5]_0\(0) => \JTAG_CONTROL_I/sel\,
\Use_Serial_Unified_Completion.count_reg[5]_1\(0) => p_0_in(0),
\Use_Serial_Unified_Completion.count_reg[5]_2\(0) => \JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg\(5),
\Use_Serial_Unified_Completion.mb_instr_overrun_reg\ => \Use_E2.BSCAN_I_n_13\,
\Use_Serial_Unified_Completion.sample_1_reg[15]\(0) => MDM_Core_I1_n_19,
drck_i => drck_i,
\p_20_out__0\ => \JTAG_CONTROL_I/p_20_out__0\,
\p_43_out__0\ => \JTAG_CONTROL_I/p_43_out__0\,
sel => sel,
\shift_Count_reg[0]\(0) => \p_0_in__0\(0),
shift_n_reset => shift_n_reset,
tdo => tdo
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_mdm_1_0 is
port (
Debug_SYS_Rst : out STD_LOGIC;
Dbg_Clk_0 : out STD_LOGIC;
Dbg_TDI_0 : out STD_LOGIC;
Dbg_TDO_0 : in STD_LOGIC;
Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_0 : out STD_LOGIC;
Dbg_Shift_0 : out STD_LOGIC;
Dbg_Update_0 : out STD_LOGIC;
Dbg_Rst_0 : out STD_LOGIC;
Dbg_Disable_0 : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_mdm_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_mdm_1_0 : entity is "system_mdm_1_0,MDM,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_mdm_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_mdm_1_0 : entity is "MDM,Vivado 2016.4";
end system_mdm_1_0;
architecture STRUCTURE of system_mdm_1_0 is
signal NLW_U0_Dbg_ARVALID_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Ext_BRK_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Ext_JTAG_CAPTURE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Ext_JTAG_DRCK_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Ext_JTAG_RESET_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Ext_JTAG_SEL_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Ext_JTAG_SHIFT_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Ext_JTAG_TDI_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Ext_JTAG_UPDATE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Ext_NM_BRK_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_M_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
signal NLW_U0_M_AXI_ARLOCK_UNCONNECTED : STD_LOGIC;
signal NLW_U0_M_AXI_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_U0_M_AXI_AWLOCK_UNCONNECTED : STD_LOGIC;
signal NLW_U0_M_AXI_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_U0_M_AXI_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_M_AXI_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_M_AXI_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_U0_M_AXI_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_U0_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Trig_Ack_In_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Trig_Ack_In_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Trig_Ack_In_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Trig_Ack_In_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Trig_Out_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Trig_Out_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Trig_Out_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Trig_Out_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_bscan_ext_tdo_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARADDR_0_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_1_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_10_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_11_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_12_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_13_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_14_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_15_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_16_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_17_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_18_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_19_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_2_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_20_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_21_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_22_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_23_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_24_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_25_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_26_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_27_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_28_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_29_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_3_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_30_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_31_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_4_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_5_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_6_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_7_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_8_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_9_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_0_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_1_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_10_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_11_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_12_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_13_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_14_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_15_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_16_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_17_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_18_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_19_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_2_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_20_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_21_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_22_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_23_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_24_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_25_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_26_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_27_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_28_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_29_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_3_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_30_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_31_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_4_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_5_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_6_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_7_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_8_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_9_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_Reg_En_1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_WDATA_0_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_1_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_10_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_11_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_12_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_13_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_14_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_15_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_16_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_17_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_18_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_19_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_2_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_20_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_21_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_22_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_23_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_24_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_25_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_26_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_27_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_28_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_29_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_3_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_30_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_31_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_4_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_5_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_6_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_7_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_8_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_9_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_LMB_Byte_Enable_0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Data_Addr_0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_M_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_M_AXIS_TID_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 );
signal NLW_U0_M_AXI_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_M_AXI_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_M_AXI_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_M_AXI_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_M_AXI_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_M_AXI_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_M_AXI_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_M_AXI_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_M_AXI_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_M_AXI_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_M_AXI_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_M_AXI_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_M_AXI_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_M_AXI_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_M_AXI_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_S_AXI_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_S_AXI_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_S_AXI_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute C_DATA_SIZE : integer;
attribute C_DATA_SIZE of U0 : label is 32;
attribute C_DBG_MEM_ACCESS : integer;
attribute C_DBG_MEM_ACCESS of U0 : label is 0;
attribute C_DBG_REG_ACCESS : integer;
attribute C_DBG_REG_ACCESS of U0 : label is 0;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_INTERCONNECT : integer;
attribute C_INTERCONNECT of U0 : label is 2;
attribute C_JTAG_CHAIN : integer;
attribute C_JTAG_CHAIN of U0 : label is 2;
attribute C_MB_DBG_PORTS : integer;
attribute C_MB_DBG_PORTS of U0 : label is 1;
attribute C_M_AXIS_DATA_WIDTH : integer;
attribute C_M_AXIS_DATA_WIDTH of U0 : label is 32;
attribute C_M_AXIS_ID_WIDTH : integer;
attribute C_M_AXIS_ID_WIDTH of U0 : label is 7;
attribute C_M_AXI_ADDR_WIDTH : integer;
attribute C_M_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_M_AXI_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_THREAD_ID_WIDTH of U0 : label is 1;
attribute C_S_AXI_ACLK_FREQ_HZ : integer;
attribute C_S_AXI_ACLK_FREQ_HZ of U0 : label is 100000000;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 4;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRACE_CLK_FREQ_HZ : integer;
attribute C_TRACE_CLK_FREQ_HZ of U0 : label is 200000000;
attribute C_TRACE_CLK_OUT_PHASE : integer;
attribute C_TRACE_CLK_OUT_PHASE of U0 : label is 90;
attribute C_TRACE_DATA_WIDTH : integer;
attribute C_TRACE_DATA_WIDTH of U0 : label is 32;
attribute C_TRACE_OUTPUT : integer;
attribute C_TRACE_OUTPUT of U0 : label is 0;
attribute C_USE_BSCAN : integer;
attribute C_USE_BSCAN of U0 : label is 0;
attribute C_USE_CONFIG_RESET : integer;
attribute C_USE_CONFIG_RESET of U0 : label is 0;
attribute C_USE_CROSS_TRIGGER : integer;
attribute C_USE_CROSS_TRIGGER of U0 : label is 0;
attribute C_USE_UART : integer;
attribute C_USE_UART of U0 : label is 0;
begin
U0: entity work.system_mdm_1_0_MDM
port map (
Config_Reset => '0',
Dbg_ARADDR_0(14 downto 2) => NLW_U0_Dbg_ARADDR_0_UNCONNECTED(14 downto 2),
Dbg_ARADDR_1(14 downto 2) => NLW_U0_Dbg_ARADDR_1_UNCONNECTED(14 downto 2),
Dbg_ARADDR_10(14 downto 2) => NLW_U0_Dbg_ARADDR_10_UNCONNECTED(14 downto 2),
Dbg_ARADDR_11(14 downto 2) => NLW_U0_Dbg_ARADDR_11_UNCONNECTED(14 downto 2),
Dbg_ARADDR_12(14 downto 2) => NLW_U0_Dbg_ARADDR_12_UNCONNECTED(14 downto 2),
Dbg_ARADDR_13(14 downto 2) => NLW_U0_Dbg_ARADDR_13_UNCONNECTED(14 downto 2),
Dbg_ARADDR_14(14 downto 2) => NLW_U0_Dbg_ARADDR_14_UNCONNECTED(14 downto 2),
Dbg_ARADDR_15(14 downto 2) => NLW_U0_Dbg_ARADDR_15_UNCONNECTED(14 downto 2),
Dbg_ARADDR_16(14 downto 2) => NLW_U0_Dbg_ARADDR_16_UNCONNECTED(14 downto 2),
Dbg_ARADDR_17(14 downto 2) => NLW_U0_Dbg_ARADDR_17_UNCONNECTED(14 downto 2),
Dbg_ARADDR_18(14 downto 2) => NLW_U0_Dbg_ARADDR_18_UNCONNECTED(14 downto 2),
Dbg_ARADDR_19(14 downto 2) => NLW_U0_Dbg_ARADDR_19_UNCONNECTED(14 downto 2),
Dbg_ARADDR_2(14 downto 2) => NLW_U0_Dbg_ARADDR_2_UNCONNECTED(14 downto 2),
Dbg_ARADDR_20(14 downto 2) => NLW_U0_Dbg_ARADDR_20_UNCONNECTED(14 downto 2),
Dbg_ARADDR_21(14 downto 2) => NLW_U0_Dbg_ARADDR_21_UNCONNECTED(14 downto 2),
Dbg_ARADDR_22(14 downto 2) => NLW_U0_Dbg_ARADDR_22_UNCONNECTED(14 downto 2),
Dbg_ARADDR_23(14 downto 2) => NLW_U0_Dbg_ARADDR_23_UNCONNECTED(14 downto 2),
Dbg_ARADDR_24(14 downto 2) => NLW_U0_Dbg_ARADDR_24_UNCONNECTED(14 downto 2),
Dbg_ARADDR_25(14 downto 2) => NLW_U0_Dbg_ARADDR_25_UNCONNECTED(14 downto 2),
Dbg_ARADDR_26(14 downto 2) => NLW_U0_Dbg_ARADDR_26_UNCONNECTED(14 downto 2),
Dbg_ARADDR_27(14 downto 2) => NLW_U0_Dbg_ARADDR_27_UNCONNECTED(14 downto 2),
Dbg_ARADDR_28(14 downto 2) => NLW_U0_Dbg_ARADDR_28_UNCONNECTED(14 downto 2),
Dbg_ARADDR_29(14 downto 2) => NLW_U0_Dbg_ARADDR_29_UNCONNECTED(14 downto 2),
Dbg_ARADDR_3(14 downto 2) => NLW_U0_Dbg_ARADDR_3_UNCONNECTED(14 downto 2),
Dbg_ARADDR_30(14 downto 2) => NLW_U0_Dbg_ARADDR_30_UNCONNECTED(14 downto 2),
Dbg_ARADDR_31(14 downto 2) => NLW_U0_Dbg_ARADDR_31_UNCONNECTED(14 downto 2),
Dbg_ARADDR_4(14 downto 2) => NLW_U0_Dbg_ARADDR_4_UNCONNECTED(14 downto 2),
Dbg_ARADDR_5(14 downto 2) => NLW_U0_Dbg_ARADDR_5_UNCONNECTED(14 downto 2),
Dbg_ARADDR_6(14 downto 2) => NLW_U0_Dbg_ARADDR_6_UNCONNECTED(14 downto 2),
Dbg_ARADDR_7(14 downto 2) => NLW_U0_Dbg_ARADDR_7_UNCONNECTED(14 downto 2),
Dbg_ARADDR_8(14 downto 2) => NLW_U0_Dbg_ARADDR_8_UNCONNECTED(14 downto 2),
Dbg_ARADDR_9(14 downto 2) => NLW_U0_Dbg_ARADDR_9_UNCONNECTED(14 downto 2),
Dbg_ARREADY_0 => '0',
Dbg_ARREADY_1 => '0',
Dbg_ARREADY_10 => '0',
Dbg_ARREADY_11 => '0',
Dbg_ARREADY_12 => '0',
Dbg_ARREADY_13 => '0',
Dbg_ARREADY_14 => '0',
Dbg_ARREADY_15 => '0',
Dbg_ARREADY_16 => '0',
Dbg_ARREADY_17 => '0',
Dbg_ARREADY_18 => '0',
Dbg_ARREADY_19 => '0',
Dbg_ARREADY_2 => '0',
Dbg_ARREADY_20 => '0',
Dbg_ARREADY_21 => '0',
Dbg_ARREADY_22 => '0',
Dbg_ARREADY_23 => '0',
Dbg_ARREADY_24 => '0',
Dbg_ARREADY_25 => '0',
Dbg_ARREADY_26 => '0',
Dbg_ARREADY_27 => '0',
Dbg_ARREADY_28 => '0',
Dbg_ARREADY_29 => '0',
Dbg_ARREADY_3 => '0',
Dbg_ARREADY_30 => '0',
Dbg_ARREADY_31 => '0',
Dbg_ARREADY_4 => '0',
Dbg_ARREADY_5 => '0',
Dbg_ARREADY_6 => '0',
Dbg_ARREADY_7 => '0',
Dbg_ARREADY_8 => '0',
Dbg_ARREADY_9 => '0',
Dbg_ARVALID_0 => NLW_U0_Dbg_ARVALID_0_UNCONNECTED,
Dbg_ARVALID_1 => NLW_U0_Dbg_ARVALID_1_UNCONNECTED,
Dbg_ARVALID_10 => NLW_U0_Dbg_ARVALID_10_UNCONNECTED,
Dbg_ARVALID_11 => NLW_U0_Dbg_ARVALID_11_UNCONNECTED,
Dbg_ARVALID_12 => NLW_U0_Dbg_ARVALID_12_UNCONNECTED,
Dbg_ARVALID_13 => NLW_U0_Dbg_ARVALID_13_UNCONNECTED,
Dbg_ARVALID_14 => NLW_U0_Dbg_ARVALID_14_UNCONNECTED,
Dbg_ARVALID_15 => NLW_U0_Dbg_ARVALID_15_UNCONNECTED,
Dbg_ARVALID_16 => NLW_U0_Dbg_ARVALID_16_UNCONNECTED,
Dbg_ARVALID_17 => NLW_U0_Dbg_ARVALID_17_UNCONNECTED,
Dbg_ARVALID_18 => NLW_U0_Dbg_ARVALID_18_UNCONNECTED,
Dbg_ARVALID_19 => NLW_U0_Dbg_ARVALID_19_UNCONNECTED,
Dbg_ARVALID_2 => NLW_U0_Dbg_ARVALID_2_UNCONNECTED,
Dbg_ARVALID_20 => NLW_U0_Dbg_ARVALID_20_UNCONNECTED,
Dbg_ARVALID_21 => NLW_U0_Dbg_ARVALID_21_UNCONNECTED,
Dbg_ARVALID_22 => NLW_U0_Dbg_ARVALID_22_UNCONNECTED,
Dbg_ARVALID_23 => NLW_U0_Dbg_ARVALID_23_UNCONNECTED,
Dbg_ARVALID_24 => NLW_U0_Dbg_ARVALID_24_UNCONNECTED,
Dbg_ARVALID_25 => NLW_U0_Dbg_ARVALID_25_UNCONNECTED,
Dbg_ARVALID_26 => NLW_U0_Dbg_ARVALID_26_UNCONNECTED,
Dbg_ARVALID_27 => NLW_U0_Dbg_ARVALID_27_UNCONNECTED,
Dbg_ARVALID_28 => NLW_U0_Dbg_ARVALID_28_UNCONNECTED,
Dbg_ARVALID_29 => NLW_U0_Dbg_ARVALID_29_UNCONNECTED,
Dbg_ARVALID_3 => NLW_U0_Dbg_ARVALID_3_UNCONNECTED,
Dbg_ARVALID_30 => NLW_U0_Dbg_ARVALID_30_UNCONNECTED,
Dbg_ARVALID_31 => NLW_U0_Dbg_ARVALID_31_UNCONNECTED,
Dbg_ARVALID_4 => NLW_U0_Dbg_ARVALID_4_UNCONNECTED,
Dbg_ARVALID_5 => NLW_U0_Dbg_ARVALID_5_UNCONNECTED,
Dbg_ARVALID_6 => NLW_U0_Dbg_ARVALID_6_UNCONNECTED,
Dbg_ARVALID_7 => NLW_U0_Dbg_ARVALID_7_UNCONNECTED,
Dbg_ARVALID_8 => NLW_U0_Dbg_ARVALID_8_UNCONNECTED,
Dbg_ARVALID_9 => NLW_U0_Dbg_ARVALID_9_UNCONNECTED,
Dbg_AWADDR_0(14 downto 2) => NLW_U0_Dbg_AWADDR_0_UNCONNECTED(14 downto 2),
Dbg_AWADDR_1(14 downto 2) => NLW_U0_Dbg_AWADDR_1_UNCONNECTED(14 downto 2),
Dbg_AWADDR_10(14 downto 2) => NLW_U0_Dbg_AWADDR_10_UNCONNECTED(14 downto 2),
Dbg_AWADDR_11(14 downto 2) => NLW_U0_Dbg_AWADDR_11_UNCONNECTED(14 downto 2),
Dbg_AWADDR_12(14 downto 2) => NLW_U0_Dbg_AWADDR_12_UNCONNECTED(14 downto 2),
Dbg_AWADDR_13(14 downto 2) => NLW_U0_Dbg_AWADDR_13_UNCONNECTED(14 downto 2),
Dbg_AWADDR_14(14 downto 2) => NLW_U0_Dbg_AWADDR_14_UNCONNECTED(14 downto 2),
Dbg_AWADDR_15(14 downto 2) => NLW_U0_Dbg_AWADDR_15_UNCONNECTED(14 downto 2),
Dbg_AWADDR_16(14 downto 2) => NLW_U0_Dbg_AWADDR_16_UNCONNECTED(14 downto 2),
Dbg_AWADDR_17(14 downto 2) => NLW_U0_Dbg_AWADDR_17_UNCONNECTED(14 downto 2),
Dbg_AWADDR_18(14 downto 2) => NLW_U0_Dbg_AWADDR_18_UNCONNECTED(14 downto 2),
Dbg_AWADDR_19(14 downto 2) => NLW_U0_Dbg_AWADDR_19_UNCONNECTED(14 downto 2),
Dbg_AWADDR_2(14 downto 2) => NLW_U0_Dbg_AWADDR_2_UNCONNECTED(14 downto 2),
Dbg_AWADDR_20(14 downto 2) => NLW_U0_Dbg_AWADDR_20_UNCONNECTED(14 downto 2),
Dbg_AWADDR_21(14 downto 2) => NLW_U0_Dbg_AWADDR_21_UNCONNECTED(14 downto 2),
Dbg_AWADDR_22(14 downto 2) => NLW_U0_Dbg_AWADDR_22_UNCONNECTED(14 downto 2),
Dbg_AWADDR_23(14 downto 2) => NLW_U0_Dbg_AWADDR_23_UNCONNECTED(14 downto 2),
Dbg_AWADDR_24(14 downto 2) => NLW_U0_Dbg_AWADDR_24_UNCONNECTED(14 downto 2),
Dbg_AWADDR_25(14 downto 2) => NLW_U0_Dbg_AWADDR_25_UNCONNECTED(14 downto 2),
Dbg_AWADDR_26(14 downto 2) => NLW_U0_Dbg_AWADDR_26_UNCONNECTED(14 downto 2),
Dbg_AWADDR_27(14 downto 2) => NLW_U0_Dbg_AWADDR_27_UNCONNECTED(14 downto 2),
Dbg_AWADDR_28(14 downto 2) => NLW_U0_Dbg_AWADDR_28_UNCONNECTED(14 downto 2),
Dbg_AWADDR_29(14 downto 2) => NLW_U0_Dbg_AWADDR_29_UNCONNECTED(14 downto 2),
Dbg_AWADDR_3(14 downto 2) => NLW_U0_Dbg_AWADDR_3_UNCONNECTED(14 downto 2),
Dbg_AWADDR_30(14 downto 2) => NLW_U0_Dbg_AWADDR_30_UNCONNECTED(14 downto 2),
Dbg_AWADDR_31(14 downto 2) => NLW_U0_Dbg_AWADDR_31_UNCONNECTED(14 downto 2),
Dbg_AWADDR_4(14 downto 2) => NLW_U0_Dbg_AWADDR_4_UNCONNECTED(14 downto 2),
Dbg_AWADDR_5(14 downto 2) => NLW_U0_Dbg_AWADDR_5_UNCONNECTED(14 downto 2),
Dbg_AWADDR_6(14 downto 2) => NLW_U0_Dbg_AWADDR_6_UNCONNECTED(14 downto 2),
Dbg_AWADDR_7(14 downto 2) => NLW_U0_Dbg_AWADDR_7_UNCONNECTED(14 downto 2),
Dbg_AWADDR_8(14 downto 2) => NLW_U0_Dbg_AWADDR_8_UNCONNECTED(14 downto 2),
Dbg_AWADDR_9(14 downto 2) => NLW_U0_Dbg_AWADDR_9_UNCONNECTED(14 downto 2),
Dbg_AWREADY_0 => '0',
Dbg_AWREADY_1 => '0',
Dbg_AWREADY_10 => '0',
Dbg_AWREADY_11 => '0',
Dbg_AWREADY_12 => '0',
Dbg_AWREADY_13 => '0',
Dbg_AWREADY_14 => '0',
Dbg_AWREADY_15 => '0',
Dbg_AWREADY_16 => '0',
Dbg_AWREADY_17 => '0',
Dbg_AWREADY_18 => '0',
Dbg_AWREADY_19 => '0',
Dbg_AWREADY_2 => '0',
Dbg_AWREADY_20 => '0',
Dbg_AWREADY_21 => '0',
Dbg_AWREADY_22 => '0',
Dbg_AWREADY_23 => '0',
Dbg_AWREADY_24 => '0',
Dbg_AWREADY_25 => '0',
Dbg_AWREADY_26 => '0',
Dbg_AWREADY_27 => '0',
Dbg_AWREADY_28 => '0',
Dbg_AWREADY_29 => '0',
Dbg_AWREADY_3 => '0',
Dbg_AWREADY_30 => '0',
Dbg_AWREADY_31 => '0',
Dbg_AWREADY_4 => '0',
Dbg_AWREADY_5 => '0',
Dbg_AWREADY_6 => '0',
Dbg_AWREADY_7 => '0',
Dbg_AWREADY_8 => '0',
Dbg_AWREADY_9 => '0',
Dbg_AWVALID_0 => NLW_U0_Dbg_AWVALID_0_UNCONNECTED,
Dbg_AWVALID_1 => NLW_U0_Dbg_AWVALID_1_UNCONNECTED,
Dbg_AWVALID_10 => NLW_U0_Dbg_AWVALID_10_UNCONNECTED,
Dbg_AWVALID_11 => NLW_U0_Dbg_AWVALID_11_UNCONNECTED,
Dbg_AWVALID_12 => NLW_U0_Dbg_AWVALID_12_UNCONNECTED,
Dbg_AWVALID_13 => NLW_U0_Dbg_AWVALID_13_UNCONNECTED,
Dbg_AWVALID_14 => NLW_U0_Dbg_AWVALID_14_UNCONNECTED,
Dbg_AWVALID_15 => NLW_U0_Dbg_AWVALID_15_UNCONNECTED,
Dbg_AWVALID_16 => NLW_U0_Dbg_AWVALID_16_UNCONNECTED,
Dbg_AWVALID_17 => NLW_U0_Dbg_AWVALID_17_UNCONNECTED,
Dbg_AWVALID_18 => NLW_U0_Dbg_AWVALID_18_UNCONNECTED,
Dbg_AWVALID_19 => NLW_U0_Dbg_AWVALID_19_UNCONNECTED,
Dbg_AWVALID_2 => NLW_U0_Dbg_AWVALID_2_UNCONNECTED,
Dbg_AWVALID_20 => NLW_U0_Dbg_AWVALID_20_UNCONNECTED,
Dbg_AWVALID_21 => NLW_U0_Dbg_AWVALID_21_UNCONNECTED,
Dbg_AWVALID_22 => NLW_U0_Dbg_AWVALID_22_UNCONNECTED,
Dbg_AWVALID_23 => NLW_U0_Dbg_AWVALID_23_UNCONNECTED,
Dbg_AWVALID_24 => NLW_U0_Dbg_AWVALID_24_UNCONNECTED,
Dbg_AWVALID_25 => NLW_U0_Dbg_AWVALID_25_UNCONNECTED,
Dbg_AWVALID_26 => NLW_U0_Dbg_AWVALID_26_UNCONNECTED,
Dbg_AWVALID_27 => NLW_U0_Dbg_AWVALID_27_UNCONNECTED,
Dbg_AWVALID_28 => NLW_U0_Dbg_AWVALID_28_UNCONNECTED,
Dbg_AWVALID_29 => NLW_U0_Dbg_AWVALID_29_UNCONNECTED,
Dbg_AWVALID_3 => NLW_U0_Dbg_AWVALID_3_UNCONNECTED,
Dbg_AWVALID_30 => NLW_U0_Dbg_AWVALID_30_UNCONNECTED,
Dbg_AWVALID_31 => NLW_U0_Dbg_AWVALID_31_UNCONNECTED,
Dbg_AWVALID_4 => NLW_U0_Dbg_AWVALID_4_UNCONNECTED,
Dbg_AWVALID_5 => NLW_U0_Dbg_AWVALID_5_UNCONNECTED,
Dbg_AWVALID_6 => NLW_U0_Dbg_AWVALID_6_UNCONNECTED,
Dbg_AWVALID_7 => NLW_U0_Dbg_AWVALID_7_UNCONNECTED,
Dbg_AWVALID_8 => NLW_U0_Dbg_AWVALID_8_UNCONNECTED,
Dbg_AWVALID_9 => NLW_U0_Dbg_AWVALID_9_UNCONNECTED,
Dbg_BREADY_0 => NLW_U0_Dbg_BREADY_0_UNCONNECTED,
Dbg_BREADY_1 => NLW_U0_Dbg_BREADY_1_UNCONNECTED,
Dbg_BREADY_10 => NLW_U0_Dbg_BREADY_10_UNCONNECTED,
Dbg_BREADY_11 => NLW_U0_Dbg_BREADY_11_UNCONNECTED,
Dbg_BREADY_12 => NLW_U0_Dbg_BREADY_12_UNCONNECTED,
Dbg_BREADY_13 => NLW_U0_Dbg_BREADY_13_UNCONNECTED,
Dbg_BREADY_14 => NLW_U0_Dbg_BREADY_14_UNCONNECTED,
Dbg_BREADY_15 => NLW_U0_Dbg_BREADY_15_UNCONNECTED,
Dbg_BREADY_16 => NLW_U0_Dbg_BREADY_16_UNCONNECTED,
Dbg_BREADY_17 => NLW_U0_Dbg_BREADY_17_UNCONNECTED,
Dbg_BREADY_18 => NLW_U0_Dbg_BREADY_18_UNCONNECTED,
Dbg_BREADY_19 => NLW_U0_Dbg_BREADY_19_UNCONNECTED,
Dbg_BREADY_2 => NLW_U0_Dbg_BREADY_2_UNCONNECTED,
Dbg_BREADY_20 => NLW_U0_Dbg_BREADY_20_UNCONNECTED,
Dbg_BREADY_21 => NLW_U0_Dbg_BREADY_21_UNCONNECTED,
Dbg_BREADY_22 => NLW_U0_Dbg_BREADY_22_UNCONNECTED,
Dbg_BREADY_23 => NLW_U0_Dbg_BREADY_23_UNCONNECTED,
Dbg_BREADY_24 => NLW_U0_Dbg_BREADY_24_UNCONNECTED,
Dbg_BREADY_25 => NLW_U0_Dbg_BREADY_25_UNCONNECTED,
Dbg_BREADY_26 => NLW_U0_Dbg_BREADY_26_UNCONNECTED,
Dbg_BREADY_27 => NLW_U0_Dbg_BREADY_27_UNCONNECTED,
Dbg_BREADY_28 => NLW_U0_Dbg_BREADY_28_UNCONNECTED,
Dbg_BREADY_29 => NLW_U0_Dbg_BREADY_29_UNCONNECTED,
Dbg_BREADY_3 => NLW_U0_Dbg_BREADY_3_UNCONNECTED,
Dbg_BREADY_30 => NLW_U0_Dbg_BREADY_30_UNCONNECTED,
Dbg_BREADY_31 => NLW_U0_Dbg_BREADY_31_UNCONNECTED,
Dbg_BREADY_4 => NLW_U0_Dbg_BREADY_4_UNCONNECTED,
Dbg_BREADY_5 => NLW_U0_Dbg_BREADY_5_UNCONNECTED,
Dbg_BREADY_6 => NLW_U0_Dbg_BREADY_6_UNCONNECTED,
Dbg_BREADY_7 => NLW_U0_Dbg_BREADY_7_UNCONNECTED,
Dbg_BREADY_8 => NLW_U0_Dbg_BREADY_8_UNCONNECTED,
Dbg_BREADY_9 => NLW_U0_Dbg_BREADY_9_UNCONNECTED,
Dbg_BRESP_0(1 downto 0) => B"00",
Dbg_BRESP_1(1 downto 0) => B"00",
Dbg_BRESP_10(1 downto 0) => B"00",
Dbg_BRESP_11(1 downto 0) => B"00",
Dbg_BRESP_12(1 downto 0) => B"00",
Dbg_BRESP_13(1 downto 0) => B"00",
Dbg_BRESP_14(1 downto 0) => B"00",
Dbg_BRESP_15(1 downto 0) => B"00",
Dbg_BRESP_16(1 downto 0) => B"00",
Dbg_BRESP_17(1 downto 0) => B"00",
Dbg_BRESP_18(1 downto 0) => B"00",
Dbg_BRESP_19(1 downto 0) => B"00",
Dbg_BRESP_2(1 downto 0) => B"00",
Dbg_BRESP_20(1 downto 0) => B"00",
Dbg_BRESP_21(1 downto 0) => B"00",
Dbg_BRESP_22(1 downto 0) => B"00",
Dbg_BRESP_23(1 downto 0) => B"00",
Dbg_BRESP_24(1 downto 0) => B"00",
Dbg_BRESP_25(1 downto 0) => B"00",
Dbg_BRESP_26(1 downto 0) => B"00",
Dbg_BRESP_27(1 downto 0) => B"00",
Dbg_BRESP_28(1 downto 0) => B"00",
Dbg_BRESP_29(1 downto 0) => B"00",
Dbg_BRESP_3(1 downto 0) => B"00",
Dbg_BRESP_30(1 downto 0) => B"00",
Dbg_BRESP_31(1 downto 0) => B"00",
Dbg_BRESP_4(1 downto 0) => B"00",
Dbg_BRESP_5(1 downto 0) => B"00",
Dbg_BRESP_6(1 downto 0) => B"00",
Dbg_BRESP_7(1 downto 0) => B"00",
Dbg_BRESP_8(1 downto 0) => B"00",
Dbg_BRESP_9(1 downto 0) => B"00",
Dbg_BVALID_0 => '0',
Dbg_BVALID_1 => '0',
Dbg_BVALID_10 => '0',
Dbg_BVALID_11 => '0',
Dbg_BVALID_12 => '0',
Dbg_BVALID_13 => '0',
Dbg_BVALID_14 => '0',
Dbg_BVALID_15 => '0',
Dbg_BVALID_16 => '0',
Dbg_BVALID_17 => '0',
Dbg_BVALID_18 => '0',
Dbg_BVALID_19 => '0',
Dbg_BVALID_2 => '0',
Dbg_BVALID_20 => '0',
Dbg_BVALID_21 => '0',
Dbg_BVALID_22 => '0',
Dbg_BVALID_23 => '0',
Dbg_BVALID_24 => '0',
Dbg_BVALID_25 => '0',
Dbg_BVALID_26 => '0',
Dbg_BVALID_27 => '0',
Dbg_BVALID_28 => '0',
Dbg_BVALID_29 => '0',
Dbg_BVALID_3 => '0',
Dbg_BVALID_30 => '0',
Dbg_BVALID_31 => '0',
Dbg_BVALID_4 => '0',
Dbg_BVALID_5 => '0',
Dbg_BVALID_6 => '0',
Dbg_BVALID_7 => '0',
Dbg_BVALID_8 => '0',
Dbg_BVALID_9 => '0',
Dbg_Capture_0 => Dbg_Capture_0,
Dbg_Capture_1 => NLW_U0_Dbg_Capture_1_UNCONNECTED,
Dbg_Capture_10 => NLW_U0_Dbg_Capture_10_UNCONNECTED,
Dbg_Capture_11 => NLW_U0_Dbg_Capture_11_UNCONNECTED,
Dbg_Capture_12 => NLW_U0_Dbg_Capture_12_UNCONNECTED,
Dbg_Capture_13 => NLW_U0_Dbg_Capture_13_UNCONNECTED,
Dbg_Capture_14 => NLW_U0_Dbg_Capture_14_UNCONNECTED,
Dbg_Capture_15 => NLW_U0_Dbg_Capture_15_UNCONNECTED,
Dbg_Capture_16 => NLW_U0_Dbg_Capture_16_UNCONNECTED,
Dbg_Capture_17 => NLW_U0_Dbg_Capture_17_UNCONNECTED,
Dbg_Capture_18 => NLW_U0_Dbg_Capture_18_UNCONNECTED,
Dbg_Capture_19 => NLW_U0_Dbg_Capture_19_UNCONNECTED,
Dbg_Capture_2 => NLW_U0_Dbg_Capture_2_UNCONNECTED,
Dbg_Capture_20 => NLW_U0_Dbg_Capture_20_UNCONNECTED,
Dbg_Capture_21 => NLW_U0_Dbg_Capture_21_UNCONNECTED,
Dbg_Capture_22 => NLW_U0_Dbg_Capture_22_UNCONNECTED,
Dbg_Capture_23 => NLW_U0_Dbg_Capture_23_UNCONNECTED,
Dbg_Capture_24 => NLW_U0_Dbg_Capture_24_UNCONNECTED,
Dbg_Capture_25 => NLW_U0_Dbg_Capture_25_UNCONNECTED,
Dbg_Capture_26 => NLW_U0_Dbg_Capture_26_UNCONNECTED,
Dbg_Capture_27 => NLW_U0_Dbg_Capture_27_UNCONNECTED,
Dbg_Capture_28 => NLW_U0_Dbg_Capture_28_UNCONNECTED,
Dbg_Capture_29 => NLW_U0_Dbg_Capture_29_UNCONNECTED,
Dbg_Capture_3 => NLW_U0_Dbg_Capture_3_UNCONNECTED,
Dbg_Capture_30 => NLW_U0_Dbg_Capture_30_UNCONNECTED,
Dbg_Capture_31 => NLW_U0_Dbg_Capture_31_UNCONNECTED,
Dbg_Capture_4 => NLW_U0_Dbg_Capture_4_UNCONNECTED,
Dbg_Capture_5 => NLW_U0_Dbg_Capture_5_UNCONNECTED,
Dbg_Capture_6 => NLW_U0_Dbg_Capture_6_UNCONNECTED,
Dbg_Capture_7 => NLW_U0_Dbg_Capture_7_UNCONNECTED,
Dbg_Capture_8 => NLW_U0_Dbg_Capture_8_UNCONNECTED,
Dbg_Capture_9 => NLW_U0_Dbg_Capture_9_UNCONNECTED,
Dbg_Clk_0 => Dbg_Clk_0,
Dbg_Clk_1 => NLW_U0_Dbg_Clk_1_UNCONNECTED,
Dbg_Clk_10 => NLW_U0_Dbg_Clk_10_UNCONNECTED,
Dbg_Clk_11 => NLW_U0_Dbg_Clk_11_UNCONNECTED,
Dbg_Clk_12 => NLW_U0_Dbg_Clk_12_UNCONNECTED,
Dbg_Clk_13 => NLW_U0_Dbg_Clk_13_UNCONNECTED,
Dbg_Clk_14 => NLW_U0_Dbg_Clk_14_UNCONNECTED,
Dbg_Clk_15 => NLW_U0_Dbg_Clk_15_UNCONNECTED,
Dbg_Clk_16 => NLW_U0_Dbg_Clk_16_UNCONNECTED,
Dbg_Clk_17 => NLW_U0_Dbg_Clk_17_UNCONNECTED,
Dbg_Clk_18 => NLW_U0_Dbg_Clk_18_UNCONNECTED,
Dbg_Clk_19 => NLW_U0_Dbg_Clk_19_UNCONNECTED,
Dbg_Clk_2 => NLW_U0_Dbg_Clk_2_UNCONNECTED,
Dbg_Clk_20 => NLW_U0_Dbg_Clk_20_UNCONNECTED,
Dbg_Clk_21 => NLW_U0_Dbg_Clk_21_UNCONNECTED,
Dbg_Clk_22 => NLW_U0_Dbg_Clk_22_UNCONNECTED,
Dbg_Clk_23 => NLW_U0_Dbg_Clk_23_UNCONNECTED,
Dbg_Clk_24 => NLW_U0_Dbg_Clk_24_UNCONNECTED,
Dbg_Clk_25 => NLW_U0_Dbg_Clk_25_UNCONNECTED,
Dbg_Clk_26 => NLW_U0_Dbg_Clk_26_UNCONNECTED,
Dbg_Clk_27 => NLW_U0_Dbg_Clk_27_UNCONNECTED,
Dbg_Clk_28 => NLW_U0_Dbg_Clk_28_UNCONNECTED,
Dbg_Clk_29 => NLW_U0_Dbg_Clk_29_UNCONNECTED,
Dbg_Clk_3 => NLW_U0_Dbg_Clk_3_UNCONNECTED,
Dbg_Clk_30 => NLW_U0_Dbg_Clk_30_UNCONNECTED,
Dbg_Clk_31 => NLW_U0_Dbg_Clk_31_UNCONNECTED,
Dbg_Clk_4 => NLW_U0_Dbg_Clk_4_UNCONNECTED,
Dbg_Clk_5 => NLW_U0_Dbg_Clk_5_UNCONNECTED,
Dbg_Clk_6 => NLW_U0_Dbg_Clk_6_UNCONNECTED,
Dbg_Clk_7 => NLW_U0_Dbg_Clk_7_UNCONNECTED,
Dbg_Clk_8 => NLW_U0_Dbg_Clk_8_UNCONNECTED,
Dbg_Clk_9 => NLW_U0_Dbg_Clk_9_UNCONNECTED,
Dbg_Disable_0 => Dbg_Disable_0,
Dbg_Disable_1 => NLW_U0_Dbg_Disable_1_UNCONNECTED,
Dbg_Disable_10 => NLW_U0_Dbg_Disable_10_UNCONNECTED,
Dbg_Disable_11 => NLW_U0_Dbg_Disable_11_UNCONNECTED,
Dbg_Disable_12 => NLW_U0_Dbg_Disable_12_UNCONNECTED,
Dbg_Disable_13 => NLW_U0_Dbg_Disable_13_UNCONNECTED,
Dbg_Disable_14 => NLW_U0_Dbg_Disable_14_UNCONNECTED,
Dbg_Disable_15 => NLW_U0_Dbg_Disable_15_UNCONNECTED,
Dbg_Disable_16 => NLW_U0_Dbg_Disable_16_UNCONNECTED,
Dbg_Disable_17 => NLW_U0_Dbg_Disable_17_UNCONNECTED,
Dbg_Disable_18 => NLW_U0_Dbg_Disable_18_UNCONNECTED,
Dbg_Disable_19 => NLW_U0_Dbg_Disable_19_UNCONNECTED,
Dbg_Disable_2 => NLW_U0_Dbg_Disable_2_UNCONNECTED,
Dbg_Disable_20 => NLW_U0_Dbg_Disable_20_UNCONNECTED,
Dbg_Disable_21 => NLW_U0_Dbg_Disable_21_UNCONNECTED,
Dbg_Disable_22 => NLW_U0_Dbg_Disable_22_UNCONNECTED,
Dbg_Disable_23 => NLW_U0_Dbg_Disable_23_UNCONNECTED,
Dbg_Disable_24 => NLW_U0_Dbg_Disable_24_UNCONNECTED,
Dbg_Disable_25 => NLW_U0_Dbg_Disable_25_UNCONNECTED,
Dbg_Disable_26 => NLW_U0_Dbg_Disable_26_UNCONNECTED,
Dbg_Disable_27 => NLW_U0_Dbg_Disable_27_UNCONNECTED,
Dbg_Disable_28 => NLW_U0_Dbg_Disable_28_UNCONNECTED,
Dbg_Disable_29 => NLW_U0_Dbg_Disable_29_UNCONNECTED,
Dbg_Disable_3 => NLW_U0_Dbg_Disable_3_UNCONNECTED,
Dbg_Disable_30 => NLW_U0_Dbg_Disable_30_UNCONNECTED,
Dbg_Disable_31 => NLW_U0_Dbg_Disable_31_UNCONNECTED,
Dbg_Disable_4 => NLW_U0_Dbg_Disable_4_UNCONNECTED,
Dbg_Disable_5 => NLW_U0_Dbg_Disable_5_UNCONNECTED,
Dbg_Disable_6 => NLW_U0_Dbg_Disable_6_UNCONNECTED,
Dbg_Disable_7 => NLW_U0_Dbg_Disable_7_UNCONNECTED,
Dbg_Disable_8 => NLW_U0_Dbg_Disable_8_UNCONNECTED,
Dbg_Disable_9 => NLW_U0_Dbg_Disable_9_UNCONNECTED,
Dbg_RDATA_0(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_1(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_10(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_11(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_12(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_13(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_14(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_15(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_16(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_17(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_18(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_19(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_2(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_20(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_21(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_22(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_23(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_24(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_25(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_26(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_27(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_28(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_29(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_3(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_30(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_31(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_4(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_5(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_6(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_7(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_8(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_9(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RREADY_0 => NLW_U0_Dbg_RREADY_0_UNCONNECTED,
Dbg_RREADY_1 => NLW_U0_Dbg_RREADY_1_UNCONNECTED,
Dbg_RREADY_10 => NLW_U0_Dbg_RREADY_10_UNCONNECTED,
Dbg_RREADY_11 => NLW_U0_Dbg_RREADY_11_UNCONNECTED,
Dbg_RREADY_12 => NLW_U0_Dbg_RREADY_12_UNCONNECTED,
Dbg_RREADY_13 => NLW_U0_Dbg_RREADY_13_UNCONNECTED,
Dbg_RREADY_14 => NLW_U0_Dbg_RREADY_14_UNCONNECTED,
Dbg_RREADY_15 => NLW_U0_Dbg_RREADY_15_UNCONNECTED,
Dbg_RREADY_16 => NLW_U0_Dbg_RREADY_16_UNCONNECTED,
Dbg_RREADY_17 => NLW_U0_Dbg_RREADY_17_UNCONNECTED,
Dbg_RREADY_18 => NLW_U0_Dbg_RREADY_18_UNCONNECTED,
Dbg_RREADY_19 => NLW_U0_Dbg_RREADY_19_UNCONNECTED,
Dbg_RREADY_2 => NLW_U0_Dbg_RREADY_2_UNCONNECTED,
Dbg_RREADY_20 => NLW_U0_Dbg_RREADY_20_UNCONNECTED,
Dbg_RREADY_21 => NLW_U0_Dbg_RREADY_21_UNCONNECTED,
Dbg_RREADY_22 => NLW_U0_Dbg_RREADY_22_UNCONNECTED,
Dbg_RREADY_23 => NLW_U0_Dbg_RREADY_23_UNCONNECTED,
Dbg_RREADY_24 => NLW_U0_Dbg_RREADY_24_UNCONNECTED,
Dbg_RREADY_25 => NLW_U0_Dbg_RREADY_25_UNCONNECTED,
Dbg_RREADY_26 => NLW_U0_Dbg_RREADY_26_UNCONNECTED,
Dbg_RREADY_27 => NLW_U0_Dbg_RREADY_27_UNCONNECTED,
Dbg_RREADY_28 => NLW_U0_Dbg_RREADY_28_UNCONNECTED,
Dbg_RREADY_29 => NLW_U0_Dbg_RREADY_29_UNCONNECTED,
Dbg_RREADY_3 => NLW_U0_Dbg_RREADY_3_UNCONNECTED,
Dbg_RREADY_30 => NLW_U0_Dbg_RREADY_30_UNCONNECTED,
Dbg_RREADY_31 => NLW_U0_Dbg_RREADY_31_UNCONNECTED,
Dbg_RREADY_4 => NLW_U0_Dbg_RREADY_4_UNCONNECTED,
Dbg_RREADY_5 => NLW_U0_Dbg_RREADY_5_UNCONNECTED,
Dbg_RREADY_6 => NLW_U0_Dbg_RREADY_6_UNCONNECTED,
Dbg_RREADY_7 => NLW_U0_Dbg_RREADY_7_UNCONNECTED,
Dbg_RREADY_8 => NLW_U0_Dbg_RREADY_8_UNCONNECTED,
Dbg_RREADY_9 => NLW_U0_Dbg_RREADY_9_UNCONNECTED,
Dbg_RRESP_0(1 downto 0) => B"00",
Dbg_RRESP_1(1 downto 0) => B"00",
Dbg_RRESP_10(1 downto 0) => B"00",
Dbg_RRESP_11(1 downto 0) => B"00",
Dbg_RRESP_12(1 downto 0) => B"00",
Dbg_RRESP_13(1 downto 0) => B"00",
Dbg_RRESP_14(1 downto 0) => B"00",
Dbg_RRESP_15(1 downto 0) => B"00",
Dbg_RRESP_16(1 downto 0) => B"00",
Dbg_RRESP_17(1 downto 0) => B"00",
Dbg_RRESP_18(1 downto 0) => B"00",
Dbg_RRESP_19(1 downto 0) => B"00",
Dbg_RRESP_2(1 downto 0) => B"00",
Dbg_RRESP_20(1 downto 0) => B"00",
Dbg_RRESP_21(1 downto 0) => B"00",
Dbg_RRESP_22(1 downto 0) => B"00",
Dbg_RRESP_23(1 downto 0) => B"00",
Dbg_RRESP_24(1 downto 0) => B"00",
Dbg_RRESP_25(1 downto 0) => B"00",
Dbg_RRESP_26(1 downto 0) => B"00",
Dbg_RRESP_27(1 downto 0) => B"00",
Dbg_RRESP_28(1 downto 0) => B"00",
Dbg_RRESP_29(1 downto 0) => B"00",
Dbg_RRESP_3(1 downto 0) => B"00",
Dbg_RRESP_30(1 downto 0) => B"00",
Dbg_RRESP_31(1 downto 0) => B"00",
Dbg_RRESP_4(1 downto 0) => B"00",
Dbg_RRESP_5(1 downto 0) => B"00",
Dbg_RRESP_6(1 downto 0) => B"00",
Dbg_RRESP_7(1 downto 0) => B"00",
Dbg_RRESP_8(1 downto 0) => B"00",
Dbg_RRESP_9(1 downto 0) => B"00",
Dbg_RVALID_0 => '0',
Dbg_RVALID_1 => '0',
Dbg_RVALID_10 => '0',
Dbg_RVALID_11 => '0',
Dbg_RVALID_12 => '0',
Dbg_RVALID_13 => '0',
Dbg_RVALID_14 => '0',
Dbg_RVALID_15 => '0',
Dbg_RVALID_16 => '0',
Dbg_RVALID_17 => '0',
Dbg_RVALID_18 => '0',
Dbg_RVALID_19 => '0',
Dbg_RVALID_2 => '0',
Dbg_RVALID_20 => '0',
Dbg_RVALID_21 => '0',
Dbg_RVALID_22 => '0',
Dbg_RVALID_23 => '0',
Dbg_RVALID_24 => '0',
Dbg_RVALID_25 => '0',
Dbg_RVALID_26 => '0',
Dbg_RVALID_27 => '0',
Dbg_RVALID_28 => '0',
Dbg_RVALID_29 => '0',
Dbg_RVALID_3 => '0',
Dbg_RVALID_30 => '0',
Dbg_RVALID_31 => '0',
Dbg_RVALID_4 => '0',
Dbg_RVALID_5 => '0',
Dbg_RVALID_6 => '0',
Dbg_RVALID_7 => '0',
Dbg_RVALID_8 => '0',
Dbg_RVALID_9 => '0',
Dbg_Reg_En_0(0 to 7) => Dbg_Reg_En_0(0 to 7),
Dbg_Reg_En_1(0 to 7) => NLW_U0_Dbg_Reg_En_1_UNCONNECTED(0 to 7),
Dbg_Reg_En_10(0 to 7) => NLW_U0_Dbg_Reg_En_10_UNCONNECTED(0 to 7),
Dbg_Reg_En_11(0 to 7) => NLW_U0_Dbg_Reg_En_11_UNCONNECTED(0 to 7),
Dbg_Reg_En_12(0 to 7) => NLW_U0_Dbg_Reg_En_12_UNCONNECTED(0 to 7),
Dbg_Reg_En_13(0 to 7) => NLW_U0_Dbg_Reg_En_13_UNCONNECTED(0 to 7),
Dbg_Reg_En_14(0 to 7) => NLW_U0_Dbg_Reg_En_14_UNCONNECTED(0 to 7),
Dbg_Reg_En_15(0 to 7) => NLW_U0_Dbg_Reg_En_15_UNCONNECTED(0 to 7),
Dbg_Reg_En_16(0 to 7) => NLW_U0_Dbg_Reg_En_16_UNCONNECTED(0 to 7),
Dbg_Reg_En_17(0 to 7) => NLW_U0_Dbg_Reg_En_17_UNCONNECTED(0 to 7),
Dbg_Reg_En_18(0 to 7) => NLW_U0_Dbg_Reg_En_18_UNCONNECTED(0 to 7),
Dbg_Reg_En_19(0 to 7) => NLW_U0_Dbg_Reg_En_19_UNCONNECTED(0 to 7),
Dbg_Reg_En_2(0 to 7) => NLW_U0_Dbg_Reg_En_2_UNCONNECTED(0 to 7),
Dbg_Reg_En_20(0 to 7) => NLW_U0_Dbg_Reg_En_20_UNCONNECTED(0 to 7),
Dbg_Reg_En_21(0 to 7) => NLW_U0_Dbg_Reg_En_21_UNCONNECTED(0 to 7),
Dbg_Reg_En_22(0 to 7) => NLW_U0_Dbg_Reg_En_22_UNCONNECTED(0 to 7),
Dbg_Reg_En_23(0 to 7) => NLW_U0_Dbg_Reg_En_23_UNCONNECTED(0 to 7),
Dbg_Reg_En_24(0 to 7) => NLW_U0_Dbg_Reg_En_24_UNCONNECTED(0 to 7),
Dbg_Reg_En_25(0 to 7) => NLW_U0_Dbg_Reg_En_25_UNCONNECTED(0 to 7),
Dbg_Reg_En_26(0 to 7) => NLW_U0_Dbg_Reg_En_26_UNCONNECTED(0 to 7),
Dbg_Reg_En_27(0 to 7) => NLW_U0_Dbg_Reg_En_27_UNCONNECTED(0 to 7),
Dbg_Reg_En_28(0 to 7) => NLW_U0_Dbg_Reg_En_28_UNCONNECTED(0 to 7),
Dbg_Reg_En_29(0 to 7) => NLW_U0_Dbg_Reg_En_29_UNCONNECTED(0 to 7),
Dbg_Reg_En_3(0 to 7) => NLW_U0_Dbg_Reg_En_3_UNCONNECTED(0 to 7),
Dbg_Reg_En_30(0 to 7) => NLW_U0_Dbg_Reg_En_30_UNCONNECTED(0 to 7),
Dbg_Reg_En_31(0 to 7) => NLW_U0_Dbg_Reg_En_31_UNCONNECTED(0 to 7),
Dbg_Reg_En_4(0 to 7) => NLW_U0_Dbg_Reg_En_4_UNCONNECTED(0 to 7),
Dbg_Reg_En_5(0 to 7) => NLW_U0_Dbg_Reg_En_5_UNCONNECTED(0 to 7),
Dbg_Reg_En_6(0 to 7) => NLW_U0_Dbg_Reg_En_6_UNCONNECTED(0 to 7),
Dbg_Reg_En_7(0 to 7) => NLW_U0_Dbg_Reg_En_7_UNCONNECTED(0 to 7),
Dbg_Reg_En_8(0 to 7) => NLW_U0_Dbg_Reg_En_8_UNCONNECTED(0 to 7),
Dbg_Reg_En_9(0 to 7) => NLW_U0_Dbg_Reg_En_9_UNCONNECTED(0 to 7),
Dbg_Rst_0 => Dbg_Rst_0,
Dbg_Rst_1 => NLW_U0_Dbg_Rst_1_UNCONNECTED,
Dbg_Rst_10 => NLW_U0_Dbg_Rst_10_UNCONNECTED,
Dbg_Rst_11 => NLW_U0_Dbg_Rst_11_UNCONNECTED,
Dbg_Rst_12 => NLW_U0_Dbg_Rst_12_UNCONNECTED,
Dbg_Rst_13 => NLW_U0_Dbg_Rst_13_UNCONNECTED,
Dbg_Rst_14 => NLW_U0_Dbg_Rst_14_UNCONNECTED,
Dbg_Rst_15 => NLW_U0_Dbg_Rst_15_UNCONNECTED,
Dbg_Rst_16 => NLW_U0_Dbg_Rst_16_UNCONNECTED,
Dbg_Rst_17 => NLW_U0_Dbg_Rst_17_UNCONNECTED,
Dbg_Rst_18 => NLW_U0_Dbg_Rst_18_UNCONNECTED,
Dbg_Rst_19 => NLW_U0_Dbg_Rst_19_UNCONNECTED,
Dbg_Rst_2 => NLW_U0_Dbg_Rst_2_UNCONNECTED,
Dbg_Rst_20 => NLW_U0_Dbg_Rst_20_UNCONNECTED,
Dbg_Rst_21 => NLW_U0_Dbg_Rst_21_UNCONNECTED,
Dbg_Rst_22 => NLW_U0_Dbg_Rst_22_UNCONNECTED,
Dbg_Rst_23 => NLW_U0_Dbg_Rst_23_UNCONNECTED,
Dbg_Rst_24 => NLW_U0_Dbg_Rst_24_UNCONNECTED,
Dbg_Rst_25 => NLW_U0_Dbg_Rst_25_UNCONNECTED,
Dbg_Rst_26 => NLW_U0_Dbg_Rst_26_UNCONNECTED,
Dbg_Rst_27 => NLW_U0_Dbg_Rst_27_UNCONNECTED,
Dbg_Rst_28 => NLW_U0_Dbg_Rst_28_UNCONNECTED,
Dbg_Rst_29 => NLW_U0_Dbg_Rst_29_UNCONNECTED,
Dbg_Rst_3 => NLW_U0_Dbg_Rst_3_UNCONNECTED,
Dbg_Rst_30 => NLW_U0_Dbg_Rst_30_UNCONNECTED,
Dbg_Rst_31 => NLW_U0_Dbg_Rst_31_UNCONNECTED,
Dbg_Rst_4 => NLW_U0_Dbg_Rst_4_UNCONNECTED,
Dbg_Rst_5 => NLW_U0_Dbg_Rst_5_UNCONNECTED,
Dbg_Rst_6 => NLW_U0_Dbg_Rst_6_UNCONNECTED,
Dbg_Rst_7 => NLW_U0_Dbg_Rst_7_UNCONNECTED,
Dbg_Rst_8 => NLW_U0_Dbg_Rst_8_UNCONNECTED,
Dbg_Rst_9 => NLW_U0_Dbg_Rst_9_UNCONNECTED,
Dbg_Shift_0 => Dbg_Shift_0,
Dbg_Shift_1 => NLW_U0_Dbg_Shift_1_UNCONNECTED,
Dbg_Shift_10 => NLW_U0_Dbg_Shift_10_UNCONNECTED,
Dbg_Shift_11 => NLW_U0_Dbg_Shift_11_UNCONNECTED,
Dbg_Shift_12 => NLW_U0_Dbg_Shift_12_UNCONNECTED,
Dbg_Shift_13 => NLW_U0_Dbg_Shift_13_UNCONNECTED,
Dbg_Shift_14 => NLW_U0_Dbg_Shift_14_UNCONNECTED,
Dbg_Shift_15 => NLW_U0_Dbg_Shift_15_UNCONNECTED,
Dbg_Shift_16 => NLW_U0_Dbg_Shift_16_UNCONNECTED,
Dbg_Shift_17 => NLW_U0_Dbg_Shift_17_UNCONNECTED,
Dbg_Shift_18 => NLW_U0_Dbg_Shift_18_UNCONNECTED,
Dbg_Shift_19 => NLW_U0_Dbg_Shift_19_UNCONNECTED,
Dbg_Shift_2 => NLW_U0_Dbg_Shift_2_UNCONNECTED,
Dbg_Shift_20 => NLW_U0_Dbg_Shift_20_UNCONNECTED,
Dbg_Shift_21 => NLW_U0_Dbg_Shift_21_UNCONNECTED,
Dbg_Shift_22 => NLW_U0_Dbg_Shift_22_UNCONNECTED,
Dbg_Shift_23 => NLW_U0_Dbg_Shift_23_UNCONNECTED,
Dbg_Shift_24 => NLW_U0_Dbg_Shift_24_UNCONNECTED,
Dbg_Shift_25 => NLW_U0_Dbg_Shift_25_UNCONNECTED,
Dbg_Shift_26 => NLW_U0_Dbg_Shift_26_UNCONNECTED,
Dbg_Shift_27 => NLW_U0_Dbg_Shift_27_UNCONNECTED,
Dbg_Shift_28 => NLW_U0_Dbg_Shift_28_UNCONNECTED,
Dbg_Shift_29 => NLW_U0_Dbg_Shift_29_UNCONNECTED,
Dbg_Shift_3 => NLW_U0_Dbg_Shift_3_UNCONNECTED,
Dbg_Shift_30 => NLW_U0_Dbg_Shift_30_UNCONNECTED,
Dbg_Shift_31 => NLW_U0_Dbg_Shift_31_UNCONNECTED,
Dbg_Shift_4 => NLW_U0_Dbg_Shift_4_UNCONNECTED,
Dbg_Shift_5 => NLW_U0_Dbg_Shift_5_UNCONNECTED,
Dbg_Shift_6 => NLW_U0_Dbg_Shift_6_UNCONNECTED,
Dbg_Shift_7 => NLW_U0_Dbg_Shift_7_UNCONNECTED,
Dbg_Shift_8 => NLW_U0_Dbg_Shift_8_UNCONNECTED,
Dbg_Shift_9 => NLW_U0_Dbg_Shift_9_UNCONNECTED,
Dbg_TDI_0 => Dbg_TDI_0,
Dbg_TDI_1 => NLW_U0_Dbg_TDI_1_UNCONNECTED,
Dbg_TDI_10 => NLW_U0_Dbg_TDI_10_UNCONNECTED,
Dbg_TDI_11 => NLW_U0_Dbg_TDI_11_UNCONNECTED,
Dbg_TDI_12 => NLW_U0_Dbg_TDI_12_UNCONNECTED,
Dbg_TDI_13 => NLW_U0_Dbg_TDI_13_UNCONNECTED,
Dbg_TDI_14 => NLW_U0_Dbg_TDI_14_UNCONNECTED,
Dbg_TDI_15 => NLW_U0_Dbg_TDI_15_UNCONNECTED,
Dbg_TDI_16 => NLW_U0_Dbg_TDI_16_UNCONNECTED,
Dbg_TDI_17 => NLW_U0_Dbg_TDI_17_UNCONNECTED,
Dbg_TDI_18 => NLW_U0_Dbg_TDI_18_UNCONNECTED,
Dbg_TDI_19 => NLW_U0_Dbg_TDI_19_UNCONNECTED,
Dbg_TDI_2 => NLW_U0_Dbg_TDI_2_UNCONNECTED,
Dbg_TDI_20 => NLW_U0_Dbg_TDI_20_UNCONNECTED,
Dbg_TDI_21 => NLW_U0_Dbg_TDI_21_UNCONNECTED,
Dbg_TDI_22 => NLW_U0_Dbg_TDI_22_UNCONNECTED,
Dbg_TDI_23 => NLW_U0_Dbg_TDI_23_UNCONNECTED,
Dbg_TDI_24 => NLW_U0_Dbg_TDI_24_UNCONNECTED,
Dbg_TDI_25 => NLW_U0_Dbg_TDI_25_UNCONNECTED,
Dbg_TDI_26 => NLW_U0_Dbg_TDI_26_UNCONNECTED,
Dbg_TDI_27 => NLW_U0_Dbg_TDI_27_UNCONNECTED,
Dbg_TDI_28 => NLW_U0_Dbg_TDI_28_UNCONNECTED,
Dbg_TDI_29 => NLW_U0_Dbg_TDI_29_UNCONNECTED,
Dbg_TDI_3 => NLW_U0_Dbg_TDI_3_UNCONNECTED,
Dbg_TDI_30 => NLW_U0_Dbg_TDI_30_UNCONNECTED,
Dbg_TDI_31 => NLW_U0_Dbg_TDI_31_UNCONNECTED,
Dbg_TDI_4 => NLW_U0_Dbg_TDI_4_UNCONNECTED,
Dbg_TDI_5 => NLW_U0_Dbg_TDI_5_UNCONNECTED,
Dbg_TDI_6 => NLW_U0_Dbg_TDI_6_UNCONNECTED,
Dbg_TDI_7 => NLW_U0_Dbg_TDI_7_UNCONNECTED,
Dbg_TDI_8 => NLW_U0_Dbg_TDI_8_UNCONNECTED,
Dbg_TDI_9 => NLW_U0_Dbg_TDI_9_UNCONNECTED,
Dbg_TDO_0 => Dbg_TDO_0,
Dbg_TDO_1 => '0',
Dbg_TDO_10 => '0',
Dbg_TDO_11 => '0',
Dbg_TDO_12 => '0',
Dbg_TDO_13 => '0',
Dbg_TDO_14 => '0',
Dbg_TDO_15 => '0',
Dbg_TDO_16 => '0',
Dbg_TDO_17 => '0',
Dbg_TDO_18 => '0',
Dbg_TDO_19 => '0',
Dbg_TDO_2 => '0',
Dbg_TDO_20 => '0',
Dbg_TDO_21 => '0',
Dbg_TDO_22 => '0',
Dbg_TDO_23 => '0',
Dbg_TDO_24 => '0',
Dbg_TDO_25 => '0',
Dbg_TDO_26 => '0',
Dbg_TDO_27 => '0',
Dbg_TDO_28 => '0',
Dbg_TDO_29 => '0',
Dbg_TDO_3 => '0',
Dbg_TDO_30 => '0',
Dbg_TDO_31 => '0',
Dbg_TDO_4 => '0',
Dbg_TDO_5 => '0',
Dbg_TDO_6 => '0',
Dbg_TDO_7 => '0',
Dbg_TDO_8 => '0',
Dbg_TDO_9 => '0',
Dbg_TrClk_0 => NLW_U0_Dbg_TrClk_0_UNCONNECTED,
Dbg_TrClk_1 => NLW_U0_Dbg_TrClk_1_UNCONNECTED,
Dbg_TrClk_10 => NLW_U0_Dbg_TrClk_10_UNCONNECTED,
Dbg_TrClk_11 => NLW_U0_Dbg_TrClk_11_UNCONNECTED,
Dbg_TrClk_12 => NLW_U0_Dbg_TrClk_12_UNCONNECTED,
Dbg_TrClk_13 => NLW_U0_Dbg_TrClk_13_UNCONNECTED,
Dbg_TrClk_14 => NLW_U0_Dbg_TrClk_14_UNCONNECTED,
Dbg_TrClk_15 => NLW_U0_Dbg_TrClk_15_UNCONNECTED,
Dbg_TrClk_16 => NLW_U0_Dbg_TrClk_16_UNCONNECTED,
Dbg_TrClk_17 => NLW_U0_Dbg_TrClk_17_UNCONNECTED,
Dbg_TrClk_18 => NLW_U0_Dbg_TrClk_18_UNCONNECTED,
Dbg_TrClk_19 => NLW_U0_Dbg_TrClk_19_UNCONNECTED,
Dbg_TrClk_2 => NLW_U0_Dbg_TrClk_2_UNCONNECTED,
Dbg_TrClk_20 => NLW_U0_Dbg_TrClk_20_UNCONNECTED,
Dbg_TrClk_21 => NLW_U0_Dbg_TrClk_21_UNCONNECTED,
Dbg_TrClk_22 => NLW_U0_Dbg_TrClk_22_UNCONNECTED,
Dbg_TrClk_23 => NLW_U0_Dbg_TrClk_23_UNCONNECTED,
Dbg_TrClk_24 => NLW_U0_Dbg_TrClk_24_UNCONNECTED,
Dbg_TrClk_25 => NLW_U0_Dbg_TrClk_25_UNCONNECTED,
Dbg_TrClk_26 => NLW_U0_Dbg_TrClk_26_UNCONNECTED,
Dbg_TrClk_27 => NLW_U0_Dbg_TrClk_27_UNCONNECTED,
Dbg_TrClk_28 => NLW_U0_Dbg_TrClk_28_UNCONNECTED,
Dbg_TrClk_29 => NLW_U0_Dbg_TrClk_29_UNCONNECTED,
Dbg_TrClk_3 => NLW_U0_Dbg_TrClk_3_UNCONNECTED,
Dbg_TrClk_30 => NLW_U0_Dbg_TrClk_30_UNCONNECTED,
Dbg_TrClk_31 => NLW_U0_Dbg_TrClk_31_UNCONNECTED,
Dbg_TrClk_4 => NLW_U0_Dbg_TrClk_4_UNCONNECTED,
Dbg_TrClk_5 => NLW_U0_Dbg_TrClk_5_UNCONNECTED,
Dbg_TrClk_6 => NLW_U0_Dbg_TrClk_6_UNCONNECTED,
Dbg_TrClk_7 => NLW_U0_Dbg_TrClk_7_UNCONNECTED,
Dbg_TrClk_8 => NLW_U0_Dbg_TrClk_8_UNCONNECTED,
Dbg_TrClk_9 => NLW_U0_Dbg_TrClk_9_UNCONNECTED,
Dbg_TrData_0(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_1(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_10(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_11(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_12(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_13(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_14(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_15(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_16(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_17(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_18(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_19(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_2(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_20(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_21(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_22(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_23(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_24(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_25(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_26(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_27(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_28(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_29(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_3(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_30(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_31(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_4(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_5(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_6(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_7(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_8(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_9(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrReady_0 => NLW_U0_Dbg_TrReady_0_UNCONNECTED,
Dbg_TrReady_1 => NLW_U0_Dbg_TrReady_1_UNCONNECTED,
Dbg_TrReady_10 => NLW_U0_Dbg_TrReady_10_UNCONNECTED,
Dbg_TrReady_11 => NLW_U0_Dbg_TrReady_11_UNCONNECTED,
Dbg_TrReady_12 => NLW_U0_Dbg_TrReady_12_UNCONNECTED,
Dbg_TrReady_13 => NLW_U0_Dbg_TrReady_13_UNCONNECTED,
Dbg_TrReady_14 => NLW_U0_Dbg_TrReady_14_UNCONNECTED,
Dbg_TrReady_15 => NLW_U0_Dbg_TrReady_15_UNCONNECTED,
Dbg_TrReady_16 => NLW_U0_Dbg_TrReady_16_UNCONNECTED,
Dbg_TrReady_17 => NLW_U0_Dbg_TrReady_17_UNCONNECTED,
Dbg_TrReady_18 => NLW_U0_Dbg_TrReady_18_UNCONNECTED,
Dbg_TrReady_19 => NLW_U0_Dbg_TrReady_19_UNCONNECTED,
Dbg_TrReady_2 => NLW_U0_Dbg_TrReady_2_UNCONNECTED,
Dbg_TrReady_20 => NLW_U0_Dbg_TrReady_20_UNCONNECTED,
Dbg_TrReady_21 => NLW_U0_Dbg_TrReady_21_UNCONNECTED,
Dbg_TrReady_22 => NLW_U0_Dbg_TrReady_22_UNCONNECTED,
Dbg_TrReady_23 => NLW_U0_Dbg_TrReady_23_UNCONNECTED,
Dbg_TrReady_24 => NLW_U0_Dbg_TrReady_24_UNCONNECTED,
Dbg_TrReady_25 => NLW_U0_Dbg_TrReady_25_UNCONNECTED,
Dbg_TrReady_26 => NLW_U0_Dbg_TrReady_26_UNCONNECTED,
Dbg_TrReady_27 => NLW_U0_Dbg_TrReady_27_UNCONNECTED,
Dbg_TrReady_28 => NLW_U0_Dbg_TrReady_28_UNCONNECTED,
Dbg_TrReady_29 => NLW_U0_Dbg_TrReady_29_UNCONNECTED,
Dbg_TrReady_3 => NLW_U0_Dbg_TrReady_3_UNCONNECTED,
Dbg_TrReady_30 => NLW_U0_Dbg_TrReady_30_UNCONNECTED,
Dbg_TrReady_31 => NLW_U0_Dbg_TrReady_31_UNCONNECTED,
Dbg_TrReady_4 => NLW_U0_Dbg_TrReady_4_UNCONNECTED,
Dbg_TrReady_5 => NLW_U0_Dbg_TrReady_5_UNCONNECTED,
Dbg_TrReady_6 => NLW_U0_Dbg_TrReady_6_UNCONNECTED,
Dbg_TrReady_7 => NLW_U0_Dbg_TrReady_7_UNCONNECTED,
Dbg_TrReady_8 => NLW_U0_Dbg_TrReady_8_UNCONNECTED,
Dbg_TrReady_9 => NLW_U0_Dbg_TrReady_9_UNCONNECTED,
Dbg_TrValid_0 => '0',
Dbg_TrValid_1 => '0',
Dbg_TrValid_10 => '0',
Dbg_TrValid_11 => '0',
Dbg_TrValid_12 => '0',
Dbg_TrValid_13 => '0',
Dbg_TrValid_14 => '0',
Dbg_TrValid_15 => '0',
Dbg_TrValid_16 => '0',
Dbg_TrValid_17 => '0',
Dbg_TrValid_18 => '0',
Dbg_TrValid_19 => '0',
Dbg_TrValid_2 => '0',
Dbg_TrValid_20 => '0',
Dbg_TrValid_21 => '0',
Dbg_TrValid_22 => '0',
Dbg_TrValid_23 => '0',
Dbg_TrValid_24 => '0',
Dbg_TrValid_25 => '0',
Dbg_TrValid_26 => '0',
Dbg_TrValid_27 => '0',
Dbg_TrValid_28 => '0',
Dbg_TrValid_29 => '0',
Dbg_TrValid_3 => '0',
Dbg_TrValid_30 => '0',
Dbg_TrValid_31 => '0',
Dbg_TrValid_4 => '0',
Dbg_TrValid_5 => '0',
Dbg_TrValid_6 => '0',
Dbg_TrValid_7 => '0',
Dbg_TrValid_8 => '0',
Dbg_TrValid_9 => '0',
Dbg_Trig_Ack_In_0(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_0_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_1(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_1_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_10(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_10_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_11(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_11_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_12(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_12_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_13(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_13_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_14(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_14_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_15(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_15_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_16(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_16_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_17(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_17_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_18(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_18_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_19(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_19_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_2(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_2_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_20(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_20_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_21(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_21_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_22(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_22_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_23(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_23_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_24(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_24_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_25(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_25_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_26(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_26_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_27(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_27_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_28(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_28_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_29(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_29_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_3(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_3_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_30(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_30_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_31(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_31_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_4(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_4_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_5(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_5_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_6(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_6_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_7(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_7_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_8(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_8_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_9(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_9_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_Out_0(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_1(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_10(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_11(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_12(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_13(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_14(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_15(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_16(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_17(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_18(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_19(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_2(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_20(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_21(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_22(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_23(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_24(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_25(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_26(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_27(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_28(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_29(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_3(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_30(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_31(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_4(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_5(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_6(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_7(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_8(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_9(0 to 7) => B"00000000",
Dbg_Trig_In_0(0 to 7) => B"00000000",
Dbg_Trig_In_1(0 to 7) => B"00000000",
Dbg_Trig_In_10(0 to 7) => B"00000000",
Dbg_Trig_In_11(0 to 7) => B"00000000",
Dbg_Trig_In_12(0 to 7) => B"00000000",
Dbg_Trig_In_13(0 to 7) => B"00000000",
Dbg_Trig_In_14(0 to 7) => B"00000000",
Dbg_Trig_In_15(0 to 7) => B"00000000",
Dbg_Trig_In_16(0 to 7) => B"00000000",
Dbg_Trig_In_17(0 to 7) => B"00000000",
Dbg_Trig_In_18(0 to 7) => B"00000000",
Dbg_Trig_In_19(0 to 7) => B"00000000",
Dbg_Trig_In_2(0 to 7) => B"00000000",
Dbg_Trig_In_20(0 to 7) => B"00000000",
Dbg_Trig_In_21(0 to 7) => B"00000000",
Dbg_Trig_In_22(0 to 7) => B"00000000",
Dbg_Trig_In_23(0 to 7) => B"00000000",
Dbg_Trig_In_24(0 to 7) => B"00000000",
Dbg_Trig_In_25(0 to 7) => B"00000000",
Dbg_Trig_In_26(0 to 7) => B"00000000",
Dbg_Trig_In_27(0 to 7) => B"00000000",
Dbg_Trig_In_28(0 to 7) => B"00000000",
Dbg_Trig_In_29(0 to 7) => B"00000000",
Dbg_Trig_In_3(0 to 7) => B"00000000",
Dbg_Trig_In_30(0 to 7) => B"00000000",
Dbg_Trig_In_31(0 to 7) => B"00000000",
Dbg_Trig_In_4(0 to 7) => B"00000000",
Dbg_Trig_In_5(0 to 7) => B"00000000",
Dbg_Trig_In_6(0 to 7) => B"00000000",
Dbg_Trig_In_7(0 to 7) => B"00000000",
Dbg_Trig_In_8(0 to 7) => B"00000000",
Dbg_Trig_In_9(0 to 7) => B"00000000",
Dbg_Trig_Out_0(0 to 7) => NLW_U0_Dbg_Trig_Out_0_UNCONNECTED(0 to 7),
Dbg_Trig_Out_1(0 to 7) => NLW_U0_Dbg_Trig_Out_1_UNCONNECTED(0 to 7),
Dbg_Trig_Out_10(0 to 7) => NLW_U0_Dbg_Trig_Out_10_UNCONNECTED(0 to 7),
Dbg_Trig_Out_11(0 to 7) => NLW_U0_Dbg_Trig_Out_11_UNCONNECTED(0 to 7),
Dbg_Trig_Out_12(0 to 7) => NLW_U0_Dbg_Trig_Out_12_UNCONNECTED(0 to 7),
Dbg_Trig_Out_13(0 to 7) => NLW_U0_Dbg_Trig_Out_13_UNCONNECTED(0 to 7),
Dbg_Trig_Out_14(0 to 7) => NLW_U0_Dbg_Trig_Out_14_UNCONNECTED(0 to 7),
Dbg_Trig_Out_15(0 to 7) => NLW_U0_Dbg_Trig_Out_15_UNCONNECTED(0 to 7),
Dbg_Trig_Out_16(0 to 7) => NLW_U0_Dbg_Trig_Out_16_UNCONNECTED(0 to 7),
Dbg_Trig_Out_17(0 to 7) => NLW_U0_Dbg_Trig_Out_17_UNCONNECTED(0 to 7),
Dbg_Trig_Out_18(0 to 7) => NLW_U0_Dbg_Trig_Out_18_UNCONNECTED(0 to 7),
Dbg_Trig_Out_19(0 to 7) => NLW_U0_Dbg_Trig_Out_19_UNCONNECTED(0 to 7),
Dbg_Trig_Out_2(0 to 7) => NLW_U0_Dbg_Trig_Out_2_UNCONNECTED(0 to 7),
Dbg_Trig_Out_20(0 to 7) => NLW_U0_Dbg_Trig_Out_20_UNCONNECTED(0 to 7),
Dbg_Trig_Out_21(0 to 7) => NLW_U0_Dbg_Trig_Out_21_UNCONNECTED(0 to 7),
Dbg_Trig_Out_22(0 to 7) => NLW_U0_Dbg_Trig_Out_22_UNCONNECTED(0 to 7),
Dbg_Trig_Out_23(0 to 7) => NLW_U0_Dbg_Trig_Out_23_UNCONNECTED(0 to 7),
Dbg_Trig_Out_24(0 to 7) => NLW_U0_Dbg_Trig_Out_24_UNCONNECTED(0 to 7),
Dbg_Trig_Out_25(0 to 7) => NLW_U0_Dbg_Trig_Out_25_UNCONNECTED(0 to 7),
Dbg_Trig_Out_26(0 to 7) => NLW_U0_Dbg_Trig_Out_26_UNCONNECTED(0 to 7),
Dbg_Trig_Out_27(0 to 7) => NLW_U0_Dbg_Trig_Out_27_UNCONNECTED(0 to 7),
Dbg_Trig_Out_28(0 to 7) => NLW_U0_Dbg_Trig_Out_28_UNCONNECTED(0 to 7),
Dbg_Trig_Out_29(0 to 7) => NLW_U0_Dbg_Trig_Out_29_UNCONNECTED(0 to 7),
Dbg_Trig_Out_3(0 to 7) => NLW_U0_Dbg_Trig_Out_3_UNCONNECTED(0 to 7),
Dbg_Trig_Out_30(0 to 7) => NLW_U0_Dbg_Trig_Out_30_UNCONNECTED(0 to 7),
Dbg_Trig_Out_31(0 to 7) => NLW_U0_Dbg_Trig_Out_31_UNCONNECTED(0 to 7),
Dbg_Trig_Out_4(0 to 7) => NLW_U0_Dbg_Trig_Out_4_UNCONNECTED(0 to 7),
Dbg_Trig_Out_5(0 to 7) => NLW_U0_Dbg_Trig_Out_5_UNCONNECTED(0 to 7),
Dbg_Trig_Out_6(0 to 7) => NLW_U0_Dbg_Trig_Out_6_UNCONNECTED(0 to 7),
Dbg_Trig_Out_7(0 to 7) => NLW_U0_Dbg_Trig_Out_7_UNCONNECTED(0 to 7),
Dbg_Trig_Out_8(0 to 7) => NLW_U0_Dbg_Trig_Out_8_UNCONNECTED(0 to 7),
Dbg_Trig_Out_9(0 to 7) => NLW_U0_Dbg_Trig_Out_9_UNCONNECTED(0 to 7),
Dbg_Update_0 => Dbg_Update_0,
Dbg_Update_1 => NLW_U0_Dbg_Update_1_UNCONNECTED,
Dbg_Update_10 => NLW_U0_Dbg_Update_10_UNCONNECTED,
Dbg_Update_11 => NLW_U0_Dbg_Update_11_UNCONNECTED,
Dbg_Update_12 => NLW_U0_Dbg_Update_12_UNCONNECTED,
Dbg_Update_13 => NLW_U0_Dbg_Update_13_UNCONNECTED,
Dbg_Update_14 => NLW_U0_Dbg_Update_14_UNCONNECTED,
Dbg_Update_15 => NLW_U0_Dbg_Update_15_UNCONNECTED,
Dbg_Update_16 => NLW_U0_Dbg_Update_16_UNCONNECTED,
Dbg_Update_17 => NLW_U0_Dbg_Update_17_UNCONNECTED,
Dbg_Update_18 => NLW_U0_Dbg_Update_18_UNCONNECTED,
Dbg_Update_19 => NLW_U0_Dbg_Update_19_UNCONNECTED,
Dbg_Update_2 => NLW_U0_Dbg_Update_2_UNCONNECTED,
Dbg_Update_20 => NLW_U0_Dbg_Update_20_UNCONNECTED,
Dbg_Update_21 => NLW_U0_Dbg_Update_21_UNCONNECTED,
Dbg_Update_22 => NLW_U0_Dbg_Update_22_UNCONNECTED,
Dbg_Update_23 => NLW_U0_Dbg_Update_23_UNCONNECTED,
Dbg_Update_24 => NLW_U0_Dbg_Update_24_UNCONNECTED,
Dbg_Update_25 => NLW_U0_Dbg_Update_25_UNCONNECTED,
Dbg_Update_26 => NLW_U0_Dbg_Update_26_UNCONNECTED,
Dbg_Update_27 => NLW_U0_Dbg_Update_27_UNCONNECTED,
Dbg_Update_28 => NLW_U0_Dbg_Update_28_UNCONNECTED,
Dbg_Update_29 => NLW_U0_Dbg_Update_29_UNCONNECTED,
Dbg_Update_3 => NLW_U0_Dbg_Update_3_UNCONNECTED,
Dbg_Update_30 => NLW_U0_Dbg_Update_30_UNCONNECTED,
Dbg_Update_31 => NLW_U0_Dbg_Update_31_UNCONNECTED,
Dbg_Update_4 => NLW_U0_Dbg_Update_4_UNCONNECTED,
Dbg_Update_5 => NLW_U0_Dbg_Update_5_UNCONNECTED,
Dbg_Update_6 => NLW_U0_Dbg_Update_6_UNCONNECTED,
Dbg_Update_7 => NLW_U0_Dbg_Update_7_UNCONNECTED,
Dbg_Update_8 => NLW_U0_Dbg_Update_8_UNCONNECTED,
Dbg_Update_9 => NLW_U0_Dbg_Update_9_UNCONNECTED,
Dbg_WDATA_0(31 downto 0) => NLW_U0_Dbg_WDATA_0_UNCONNECTED(31 downto 0),
Dbg_WDATA_1(31 downto 0) => NLW_U0_Dbg_WDATA_1_UNCONNECTED(31 downto 0),
Dbg_WDATA_10(31 downto 0) => NLW_U0_Dbg_WDATA_10_UNCONNECTED(31 downto 0),
Dbg_WDATA_11(31 downto 0) => NLW_U0_Dbg_WDATA_11_UNCONNECTED(31 downto 0),
Dbg_WDATA_12(31 downto 0) => NLW_U0_Dbg_WDATA_12_UNCONNECTED(31 downto 0),
Dbg_WDATA_13(31 downto 0) => NLW_U0_Dbg_WDATA_13_UNCONNECTED(31 downto 0),
Dbg_WDATA_14(31 downto 0) => NLW_U0_Dbg_WDATA_14_UNCONNECTED(31 downto 0),
Dbg_WDATA_15(31 downto 0) => NLW_U0_Dbg_WDATA_15_UNCONNECTED(31 downto 0),
Dbg_WDATA_16(31 downto 0) => NLW_U0_Dbg_WDATA_16_UNCONNECTED(31 downto 0),
Dbg_WDATA_17(31 downto 0) => NLW_U0_Dbg_WDATA_17_UNCONNECTED(31 downto 0),
Dbg_WDATA_18(31 downto 0) => NLW_U0_Dbg_WDATA_18_UNCONNECTED(31 downto 0),
Dbg_WDATA_19(31 downto 0) => NLW_U0_Dbg_WDATA_19_UNCONNECTED(31 downto 0),
Dbg_WDATA_2(31 downto 0) => NLW_U0_Dbg_WDATA_2_UNCONNECTED(31 downto 0),
Dbg_WDATA_20(31 downto 0) => NLW_U0_Dbg_WDATA_20_UNCONNECTED(31 downto 0),
Dbg_WDATA_21(31 downto 0) => NLW_U0_Dbg_WDATA_21_UNCONNECTED(31 downto 0),
Dbg_WDATA_22(31 downto 0) => NLW_U0_Dbg_WDATA_22_UNCONNECTED(31 downto 0),
Dbg_WDATA_23(31 downto 0) => NLW_U0_Dbg_WDATA_23_UNCONNECTED(31 downto 0),
Dbg_WDATA_24(31 downto 0) => NLW_U0_Dbg_WDATA_24_UNCONNECTED(31 downto 0),
Dbg_WDATA_25(31 downto 0) => NLW_U0_Dbg_WDATA_25_UNCONNECTED(31 downto 0),
Dbg_WDATA_26(31 downto 0) => NLW_U0_Dbg_WDATA_26_UNCONNECTED(31 downto 0),
Dbg_WDATA_27(31 downto 0) => NLW_U0_Dbg_WDATA_27_UNCONNECTED(31 downto 0),
Dbg_WDATA_28(31 downto 0) => NLW_U0_Dbg_WDATA_28_UNCONNECTED(31 downto 0),
Dbg_WDATA_29(31 downto 0) => NLW_U0_Dbg_WDATA_29_UNCONNECTED(31 downto 0),
Dbg_WDATA_3(31 downto 0) => NLW_U0_Dbg_WDATA_3_UNCONNECTED(31 downto 0),
Dbg_WDATA_30(31 downto 0) => NLW_U0_Dbg_WDATA_30_UNCONNECTED(31 downto 0),
Dbg_WDATA_31(31 downto 0) => NLW_U0_Dbg_WDATA_31_UNCONNECTED(31 downto 0),
Dbg_WDATA_4(31 downto 0) => NLW_U0_Dbg_WDATA_4_UNCONNECTED(31 downto 0),
Dbg_WDATA_5(31 downto 0) => NLW_U0_Dbg_WDATA_5_UNCONNECTED(31 downto 0),
Dbg_WDATA_6(31 downto 0) => NLW_U0_Dbg_WDATA_6_UNCONNECTED(31 downto 0),
Dbg_WDATA_7(31 downto 0) => NLW_U0_Dbg_WDATA_7_UNCONNECTED(31 downto 0),
Dbg_WDATA_8(31 downto 0) => NLW_U0_Dbg_WDATA_8_UNCONNECTED(31 downto 0),
Dbg_WDATA_9(31 downto 0) => NLW_U0_Dbg_WDATA_9_UNCONNECTED(31 downto 0),
Dbg_WREADY_0 => '0',
Dbg_WREADY_1 => '0',
Dbg_WREADY_10 => '0',
Dbg_WREADY_11 => '0',
Dbg_WREADY_12 => '0',
Dbg_WREADY_13 => '0',
Dbg_WREADY_14 => '0',
Dbg_WREADY_15 => '0',
Dbg_WREADY_16 => '0',
Dbg_WREADY_17 => '0',
Dbg_WREADY_18 => '0',
Dbg_WREADY_19 => '0',
Dbg_WREADY_2 => '0',
Dbg_WREADY_20 => '0',
Dbg_WREADY_21 => '0',
Dbg_WREADY_22 => '0',
Dbg_WREADY_23 => '0',
Dbg_WREADY_24 => '0',
Dbg_WREADY_25 => '0',
Dbg_WREADY_26 => '0',
Dbg_WREADY_27 => '0',
Dbg_WREADY_28 => '0',
Dbg_WREADY_29 => '0',
Dbg_WREADY_3 => '0',
Dbg_WREADY_30 => '0',
Dbg_WREADY_31 => '0',
Dbg_WREADY_4 => '0',
Dbg_WREADY_5 => '0',
Dbg_WREADY_6 => '0',
Dbg_WREADY_7 => '0',
Dbg_WREADY_8 => '0',
Dbg_WREADY_9 => '0',
Dbg_WVALID_0 => NLW_U0_Dbg_WVALID_0_UNCONNECTED,
Dbg_WVALID_1 => NLW_U0_Dbg_WVALID_1_UNCONNECTED,
Dbg_WVALID_10 => NLW_U0_Dbg_WVALID_10_UNCONNECTED,
Dbg_WVALID_11 => NLW_U0_Dbg_WVALID_11_UNCONNECTED,
Dbg_WVALID_12 => NLW_U0_Dbg_WVALID_12_UNCONNECTED,
Dbg_WVALID_13 => NLW_U0_Dbg_WVALID_13_UNCONNECTED,
Dbg_WVALID_14 => NLW_U0_Dbg_WVALID_14_UNCONNECTED,
Dbg_WVALID_15 => NLW_U0_Dbg_WVALID_15_UNCONNECTED,
Dbg_WVALID_16 => NLW_U0_Dbg_WVALID_16_UNCONNECTED,
Dbg_WVALID_17 => NLW_U0_Dbg_WVALID_17_UNCONNECTED,
Dbg_WVALID_18 => NLW_U0_Dbg_WVALID_18_UNCONNECTED,
Dbg_WVALID_19 => NLW_U0_Dbg_WVALID_19_UNCONNECTED,
Dbg_WVALID_2 => NLW_U0_Dbg_WVALID_2_UNCONNECTED,
Dbg_WVALID_20 => NLW_U0_Dbg_WVALID_20_UNCONNECTED,
Dbg_WVALID_21 => NLW_U0_Dbg_WVALID_21_UNCONNECTED,
Dbg_WVALID_22 => NLW_U0_Dbg_WVALID_22_UNCONNECTED,
Dbg_WVALID_23 => NLW_U0_Dbg_WVALID_23_UNCONNECTED,
Dbg_WVALID_24 => NLW_U0_Dbg_WVALID_24_UNCONNECTED,
Dbg_WVALID_25 => NLW_U0_Dbg_WVALID_25_UNCONNECTED,
Dbg_WVALID_26 => NLW_U0_Dbg_WVALID_26_UNCONNECTED,
Dbg_WVALID_27 => NLW_U0_Dbg_WVALID_27_UNCONNECTED,
Dbg_WVALID_28 => NLW_U0_Dbg_WVALID_28_UNCONNECTED,
Dbg_WVALID_29 => NLW_U0_Dbg_WVALID_29_UNCONNECTED,
Dbg_WVALID_3 => NLW_U0_Dbg_WVALID_3_UNCONNECTED,
Dbg_WVALID_30 => NLW_U0_Dbg_WVALID_30_UNCONNECTED,
Dbg_WVALID_31 => NLW_U0_Dbg_WVALID_31_UNCONNECTED,
Dbg_WVALID_4 => NLW_U0_Dbg_WVALID_4_UNCONNECTED,
Dbg_WVALID_5 => NLW_U0_Dbg_WVALID_5_UNCONNECTED,
Dbg_WVALID_6 => NLW_U0_Dbg_WVALID_6_UNCONNECTED,
Dbg_WVALID_7 => NLW_U0_Dbg_WVALID_7_UNCONNECTED,
Dbg_WVALID_8 => NLW_U0_Dbg_WVALID_8_UNCONNECTED,
Dbg_WVALID_9 => NLW_U0_Dbg_WVALID_9_UNCONNECTED,
Debug_SYS_Rst => Debug_SYS_Rst,
Ext_BRK => NLW_U0_Ext_BRK_UNCONNECTED,
Ext_JTAG_CAPTURE => NLW_U0_Ext_JTAG_CAPTURE_UNCONNECTED,
Ext_JTAG_DRCK => NLW_U0_Ext_JTAG_DRCK_UNCONNECTED,
Ext_JTAG_RESET => NLW_U0_Ext_JTAG_RESET_UNCONNECTED,
Ext_JTAG_SEL => NLW_U0_Ext_JTAG_SEL_UNCONNECTED,
Ext_JTAG_SHIFT => NLW_U0_Ext_JTAG_SHIFT_UNCONNECTED,
Ext_JTAG_TDI => NLW_U0_Ext_JTAG_TDI_UNCONNECTED,
Ext_JTAG_TDO => '0',
Ext_JTAG_UPDATE => NLW_U0_Ext_JTAG_UPDATE_UNCONNECTED,
Ext_NM_BRK => NLW_U0_Ext_NM_BRK_UNCONNECTED,
Interrupt => NLW_U0_Interrupt_UNCONNECTED,
LMB_Addr_Strobe_0 => NLW_U0_LMB_Addr_Strobe_0_UNCONNECTED,
LMB_Addr_Strobe_1 => NLW_U0_LMB_Addr_Strobe_1_UNCONNECTED,
LMB_Addr_Strobe_10 => NLW_U0_LMB_Addr_Strobe_10_UNCONNECTED,
LMB_Addr_Strobe_11 => NLW_U0_LMB_Addr_Strobe_11_UNCONNECTED,
LMB_Addr_Strobe_12 => NLW_U0_LMB_Addr_Strobe_12_UNCONNECTED,
LMB_Addr_Strobe_13 => NLW_U0_LMB_Addr_Strobe_13_UNCONNECTED,
LMB_Addr_Strobe_14 => NLW_U0_LMB_Addr_Strobe_14_UNCONNECTED,
LMB_Addr_Strobe_15 => NLW_U0_LMB_Addr_Strobe_15_UNCONNECTED,
LMB_Addr_Strobe_16 => NLW_U0_LMB_Addr_Strobe_16_UNCONNECTED,
LMB_Addr_Strobe_17 => NLW_U0_LMB_Addr_Strobe_17_UNCONNECTED,
LMB_Addr_Strobe_18 => NLW_U0_LMB_Addr_Strobe_18_UNCONNECTED,
LMB_Addr_Strobe_19 => NLW_U0_LMB_Addr_Strobe_19_UNCONNECTED,
LMB_Addr_Strobe_2 => NLW_U0_LMB_Addr_Strobe_2_UNCONNECTED,
LMB_Addr_Strobe_20 => NLW_U0_LMB_Addr_Strobe_20_UNCONNECTED,
LMB_Addr_Strobe_21 => NLW_U0_LMB_Addr_Strobe_21_UNCONNECTED,
LMB_Addr_Strobe_22 => NLW_U0_LMB_Addr_Strobe_22_UNCONNECTED,
LMB_Addr_Strobe_23 => NLW_U0_LMB_Addr_Strobe_23_UNCONNECTED,
LMB_Addr_Strobe_24 => NLW_U0_LMB_Addr_Strobe_24_UNCONNECTED,
LMB_Addr_Strobe_25 => NLW_U0_LMB_Addr_Strobe_25_UNCONNECTED,
LMB_Addr_Strobe_26 => NLW_U0_LMB_Addr_Strobe_26_UNCONNECTED,
LMB_Addr_Strobe_27 => NLW_U0_LMB_Addr_Strobe_27_UNCONNECTED,
LMB_Addr_Strobe_28 => NLW_U0_LMB_Addr_Strobe_28_UNCONNECTED,
LMB_Addr_Strobe_29 => NLW_U0_LMB_Addr_Strobe_29_UNCONNECTED,
LMB_Addr_Strobe_3 => NLW_U0_LMB_Addr_Strobe_3_UNCONNECTED,
LMB_Addr_Strobe_30 => NLW_U0_LMB_Addr_Strobe_30_UNCONNECTED,
LMB_Addr_Strobe_31 => NLW_U0_LMB_Addr_Strobe_31_UNCONNECTED,
LMB_Addr_Strobe_4 => NLW_U0_LMB_Addr_Strobe_4_UNCONNECTED,
LMB_Addr_Strobe_5 => NLW_U0_LMB_Addr_Strobe_5_UNCONNECTED,
LMB_Addr_Strobe_6 => NLW_U0_LMB_Addr_Strobe_6_UNCONNECTED,
LMB_Addr_Strobe_7 => NLW_U0_LMB_Addr_Strobe_7_UNCONNECTED,
LMB_Addr_Strobe_8 => NLW_U0_LMB_Addr_Strobe_8_UNCONNECTED,
LMB_Addr_Strobe_9 => NLW_U0_LMB_Addr_Strobe_9_UNCONNECTED,
LMB_Byte_Enable_0(0 to 3) => NLW_U0_LMB_Byte_Enable_0_UNCONNECTED(0 to 3),
LMB_Byte_Enable_1(0 to 3) => NLW_U0_LMB_Byte_Enable_1_UNCONNECTED(0 to 3),
LMB_Byte_Enable_10(0 to 3) => NLW_U0_LMB_Byte_Enable_10_UNCONNECTED(0 to 3),
LMB_Byte_Enable_11(0 to 3) => NLW_U0_LMB_Byte_Enable_11_UNCONNECTED(0 to 3),
LMB_Byte_Enable_12(0 to 3) => NLW_U0_LMB_Byte_Enable_12_UNCONNECTED(0 to 3),
LMB_Byte_Enable_13(0 to 3) => NLW_U0_LMB_Byte_Enable_13_UNCONNECTED(0 to 3),
LMB_Byte_Enable_14(0 to 3) => NLW_U0_LMB_Byte_Enable_14_UNCONNECTED(0 to 3),
LMB_Byte_Enable_15(0 to 3) => NLW_U0_LMB_Byte_Enable_15_UNCONNECTED(0 to 3),
LMB_Byte_Enable_16(0 to 3) => NLW_U0_LMB_Byte_Enable_16_UNCONNECTED(0 to 3),
LMB_Byte_Enable_17(0 to 3) => NLW_U0_LMB_Byte_Enable_17_UNCONNECTED(0 to 3),
LMB_Byte_Enable_18(0 to 3) => NLW_U0_LMB_Byte_Enable_18_UNCONNECTED(0 to 3),
LMB_Byte_Enable_19(0 to 3) => NLW_U0_LMB_Byte_Enable_19_UNCONNECTED(0 to 3),
LMB_Byte_Enable_2(0 to 3) => NLW_U0_LMB_Byte_Enable_2_UNCONNECTED(0 to 3),
LMB_Byte_Enable_20(0 to 3) => NLW_U0_LMB_Byte_Enable_20_UNCONNECTED(0 to 3),
LMB_Byte_Enable_21(0 to 3) => NLW_U0_LMB_Byte_Enable_21_UNCONNECTED(0 to 3),
LMB_Byte_Enable_22(0 to 3) => NLW_U0_LMB_Byte_Enable_22_UNCONNECTED(0 to 3),
LMB_Byte_Enable_23(0 to 3) => NLW_U0_LMB_Byte_Enable_23_UNCONNECTED(0 to 3),
LMB_Byte_Enable_24(0 to 3) => NLW_U0_LMB_Byte_Enable_24_UNCONNECTED(0 to 3),
LMB_Byte_Enable_25(0 to 3) => NLW_U0_LMB_Byte_Enable_25_UNCONNECTED(0 to 3),
LMB_Byte_Enable_26(0 to 3) => NLW_U0_LMB_Byte_Enable_26_UNCONNECTED(0 to 3),
LMB_Byte_Enable_27(0 to 3) => NLW_U0_LMB_Byte_Enable_27_UNCONNECTED(0 to 3),
LMB_Byte_Enable_28(0 to 3) => NLW_U0_LMB_Byte_Enable_28_UNCONNECTED(0 to 3),
LMB_Byte_Enable_29(0 to 3) => NLW_U0_LMB_Byte_Enable_29_UNCONNECTED(0 to 3),
LMB_Byte_Enable_3(0 to 3) => NLW_U0_LMB_Byte_Enable_3_UNCONNECTED(0 to 3),
LMB_Byte_Enable_30(0 to 3) => NLW_U0_LMB_Byte_Enable_30_UNCONNECTED(0 to 3),
LMB_Byte_Enable_31(0 to 3) => NLW_U0_LMB_Byte_Enable_31_UNCONNECTED(0 to 3),
LMB_Byte_Enable_4(0 to 3) => NLW_U0_LMB_Byte_Enable_4_UNCONNECTED(0 to 3),
LMB_Byte_Enable_5(0 to 3) => NLW_U0_LMB_Byte_Enable_5_UNCONNECTED(0 to 3),
LMB_Byte_Enable_6(0 to 3) => NLW_U0_LMB_Byte_Enable_6_UNCONNECTED(0 to 3),
LMB_Byte_Enable_7(0 to 3) => NLW_U0_LMB_Byte_Enable_7_UNCONNECTED(0 to 3),
LMB_Byte_Enable_8(0 to 3) => NLW_U0_LMB_Byte_Enable_8_UNCONNECTED(0 to 3),
LMB_Byte_Enable_9(0 to 3) => NLW_U0_LMB_Byte_Enable_9_UNCONNECTED(0 to 3),
LMB_CE_0 => '0',
LMB_CE_1 => '0',
LMB_CE_10 => '0',
LMB_CE_11 => '0',
LMB_CE_12 => '0',
LMB_CE_13 => '0',
LMB_CE_14 => '0',
LMB_CE_15 => '0',
LMB_CE_16 => '0',
LMB_CE_17 => '0',
LMB_CE_18 => '0',
LMB_CE_19 => '0',
LMB_CE_2 => '0',
LMB_CE_20 => '0',
LMB_CE_21 => '0',
LMB_CE_22 => '0',
LMB_CE_23 => '0',
LMB_CE_24 => '0',
LMB_CE_25 => '0',
LMB_CE_26 => '0',
LMB_CE_27 => '0',
LMB_CE_28 => '0',
LMB_CE_29 => '0',
LMB_CE_3 => '0',
LMB_CE_30 => '0',
LMB_CE_31 => '0',
LMB_CE_4 => '0',
LMB_CE_5 => '0',
LMB_CE_6 => '0',
LMB_CE_7 => '0',
LMB_CE_8 => '0',
LMB_CE_9 => '0',
LMB_Data_Addr_0(0 to 31) => NLW_U0_LMB_Data_Addr_0_UNCONNECTED(0 to 31),
LMB_Data_Addr_1(0 to 31) => NLW_U0_LMB_Data_Addr_1_UNCONNECTED(0 to 31),
LMB_Data_Addr_10(0 to 31) => NLW_U0_LMB_Data_Addr_10_UNCONNECTED(0 to 31),
LMB_Data_Addr_11(0 to 31) => NLW_U0_LMB_Data_Addr_11_UNCONNECTED(0 to 31),
LMB_Data_Addr_12(0 to 31) => NLW_U0_LMB_Data_Addr_12_UNCONNECTED(0 to 31),
LMB_Data_Addr_13(0 to 31) => NLW_U0_LMB_Data_Addr_13_UNCONNECTED(0 to 31),
LMB_Data_Addr_14(0 to 31) => NLW_U0_LMB_Data_Addr_14_UNCONNECTED(0 to 31),
LMB_Data_Addr_15(0 to 31) => NLW_U0_LMB_Data_Addr_15_UNCONNECTED(0 to 31),
LMB_Data_Addr_16(0 to 31) => NLW_U0_LMB_Data_Addr_16_UNCONNECTED(0 to 31),
LMB_Data_Addr_17(0 to 31) => NLW_U0_LMB_Data_Addr_17_UNCONNECTED(0 to 31),
LMB_Data_Addr_18(0 to 31) => NLW_U0_LMB_Data_Addr_18_UNCONNECTED(0 to 31),
LMB_Data_Addr_19(0 to 31) => NLW_U0_LMB_Data_Addr_19_UNCONNECTED(0 to 31),
LMB_Data_Addr_2(0 to 31) => NLW_U0_LMB_Data_Addr_2_UNCONNECTED(0 to 31),
LMB_Data_Addr_20(0 to 31) => NLW_U0_LMB_Data_Addr_20_UNCONNECTED(0 to 31),
LMB_Data_Addr_21(0 to 31) => NLW_U0_LMB_Data_Addr_21_UNCONNECTED(0 to 31),
LMB_Data_Addr_22(0 to 31) => NLW_U0_LMB_Data_Addr_22_UNCONNECTED(0 to 31),
LMB_Data_Addr_23(0 to 31) => NLW_U0_LMB_Data_Addr_23_UNCONNECTED(0 to 31),
LMB_Data_Addr_24(0 to 31) => NLW_U0_LMB_Data_Addr_24_UNCONNECTED(0 to 31),
LMB_Data_Addr_25(0 to 31) => NLW_U0_LMB_Data_Addr_25_UNCONNECTED(0 to 31),
LMB_Data_Addr_26(0 to 31) => NLW_U0_LMB_Data_Addr_26_UNCONNECTED(0 to 31),
LMB_Data_Addr_27(0 to 31) => NLW_U0_LMB_Data_Addr_27_UNCONNECTED(0 to 31),
LMB_Data_Addr_28(0 to 31) => NLW_U0_LMB_Data_Addr_28_UNCONNECTED(0 to 31),
LMB_Data_Addr_29(0 to 31) => NLW_U0_LMB_Data_Addr_29_UNCONNECTED(0 to 31),
LMB_Data_Addr_3(0 to 31) => NLW_U0_LMB_Data_Addr_3_UNCONNECTED(0 to 31),
LMB_Data_Addr_30(0 to 31) => NLW_U0_LMB_Data_Addr_30_UNCONNECTED(0 to 31),
LMB_Data_Addr_31(0 to 31) => NLW_U0_LMB_Data_Addr_31_UNCONNECTED(0 to 31),
LMB_Data_Addr_4(0 to 31) => NLW_U0_LMB_Data_Addr_4_UNCONNECTED(0 to 31),
LMB_Data_Addr_5(0 to 31) => NLW_U0_LMB_Data_Addr_5_UNCONNECTED(0 to 31),
LMB_Data_Addr_6(0 to 31) => NLW_U0_LMB_Data_Addr_6_UNCONNECTED(0 to 31),
LMB_Data_Addr_7(0 to 31) => NLW_U0_LMB_Data_Addr_7_UNCONNECTED(0 to 31),
LMB_Data_Addr_8(0 to 31) => NLW_U0_LMB_Data_Addr_8_UNCONNECTED(0 to 31),
LMB_Data_Addr_9(0 to 31) => NLW_U0_LMB_Data_Addr_9_UNCONNECTED(0 to 31),
LMB_Data_Read_0(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_1(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_10(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_11(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_12(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_13(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_14(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_15(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_16(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_17(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_18(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_19(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_2(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_20(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_21(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_22(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_23(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_24(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_25(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_26(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_27(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_28(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_29(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_3(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_30(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_31(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_4(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_5(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_6(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_7(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_8(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_9(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Write_0(0 to 31) => NLW_U0_LMB_Data_Write_0_UNCONNECTED(0 to 31),
LMB_Data_Write_1(0 to 31) => NLW_U0_LMB_Data_Write_1_UNCONNECTED(0 to 31),
LMB_Data_Write_10(0 to 31) => NLW_U0_LMB_Data_Write_10_UNCONNECTED(0 to 31),
LMB_Data_Write_11(0 to 31) => NLW_U0_LMB_Data_Write_11_UNCONNECTED(0 to 31),
LMB_Data_Write_12(0 to 31) => NLW_U0_LMB_Data_Write_12_UNCONNECTED(0 to 31),
LMB_Data_Write_13(0 to 31) => NLW_U0_LMB_Data_Write_13_UNCONNECTED(0 to 31),
LMB_Data_Write_14(0 to 31) => NLW_U0_LMB_Data_Write_14_UNCONNECTED(0 to 31),
LMB_Data_Write_15(0 to 31) => NLW_U0_LMB_Data_Write_15_UNCONNECTED(0 to 31),
LMB_Data_Write_16(0 to 31) => NLW_U0_LMB_Data_Write_16_UNCONNECTED(0 to 31),
LMB_Data_Write_17(0 to 31) => NLW_U0_LMB_Data_Write_17_UNCONNECTED(0 to 31),
LMB_Data_Write_18(0 to 31) => NLW_U0_LMB_Data_Write_18_UNCONNECTED(0 to 31),
LMB_Data_Write_19(0 to 31) => NLW_U0_LMB_Data_Write_19_UNCONNECTED(0 to 31),
LMB_Data_Write_2(0 to 31) => NLW_U0_LMB_Data_Write_2_UNCONNECTED(0 to 31),
LMB_Data_Write_20(0 to 31) => NLW_U0_LMB_Data_Write_20_UNCONNECTED(0 to 31),
LMB_Data_Write_21(0 to 31) => NLW_U0_LMB_Data_Write_21_UNCONNECTED(0 to 31),
LMB_Data_Write_22(0 to 31) => NLW_U0_LMB_Data_Write_22_UNCONNECTED(0 to 31),
LMB_Data_Write_23(0 to 31) => NLW_U0_LMB_Data_Write_23_UNCONNECTED(0 to 31),
LMB_Data_Write_24(0 to 31) => NLW_U0_LMB_Data_Write_24_UNCONNECTED(0 to 31),
LMB_Data_Write_25(0 to 31) => NLW_U0_LMB_Data_Write_25_UNCONNECTED(0 to 31),
LMB_Data_Write_26(0 to 31) => NLW_U0_LMB_Data_Write_26_UNCONNECTED(0 to 31),
LMB_Data_Write_27(0 to 31) => NLW_U0_LMB_Data_Write_27_UNCONNECTED(0 to 31),
LMB_Data_Write_28(0 to 31) => NLW_U0_LMB_Data_Write_28_UNCONNECTED(0 to 31),
LMB_Data_Write_29(0 to 31) => NLW_U0_LMB_Data_Write_29_UNCONNECTED(0 to 31),
LMB_Data_Write_3(0 to 31) => NLW_U0_LMB_Data_Write_3_UNCONNECTED(0 to 31),
LMB_Data_Write_30(0 to 31) => NLW_U0_LMB_Data_Write_30_UNCONNECTED(0 to 31),
LMB_Data_Write_31(0 to 31) => NLW_U0_LMB_Data_Write_31_UNCONNECTED(0 to 31),
LMB_Data_Write_4(0 to 31) => NLW_U0_LMB_Data_Write_4_UNCONNECTED(0 to 31),
LMB_Data_Write_5(0 to 31) => NLW_U0_LMB_Data_Write_5_UNCONNECTED(0 to 31),
LMB_Data_Write_6(0 to 31) => NLW_U0_LMB_Data_Write_6_UNCONNECTED(0 to 31),
LMB_Data_Write_7(0 to 31) => NLW_U0_LMB_Data_Write_7_UNCONNECTED(0 to 31),
LMB_Data_Write_8(0 to 31) => NLW_U0_LMB_Data_Write_8_UNCONNECTED(0 to 31),
LMB_Data_Write_9(0 to 31) => NLW_U0_LMB_Data_Write_9_UNCONNECTED(0 to 31),
LMB_Read_Strobe_0 => NLW_U0_LMB_Read_Strobe_0_UNCONNECTED,
LMB_Read_Strobe_1 => NLW_U0_LMB_Read_Strobe_1_UNCONNECTED,
LMB_Read_Strobe_10 => NLW_U0_LMB_Read_Strobe_10_UNCONNECTED,
LMB_Read_Strobe_11 => NLW_U0_LMB_Read_Strobe_11_UNCONNECTED,
LMB_Read_Strobe_12 => NLW_U0_LMB_Read_Strobe_12_UNCONNECTED,
LMB_Read_Strobe_13 => NLW_U0_LMB_Read_Strobe_13_UNCONNECTED,
LMB_Read_Strobe_14 => NLW_U0_LMB_Read_Strobe_14_UNCONNECTED,
LMB_Read_Strobe_15 => NLW_U0_LMB_Read_Strobe_15_UNCONNECTED,
LMB_Read_Strobe_16 => NLW_U0_LMB_Read_Strobe_16_UNCONNECTED,
LMB_Read_Strobe_17 => NLW_U0_LMB_Read_Strobe_17_UNCONNECTED,
LMB_Read_Strobe_18 => NLW_U0_LMB_Read_Strobe_18_UNCONNECTED,
LMB_Read_Strobe_19 => NLW_U0_LMB_Read_Strobe_19_UNCONNECTED,
LMB_Read_Strobe_2 => NLW_U0_LMB_Read_Strobe_2_UNCONNECTED,
LMB_Read_Strobe_20 => NLW_U0_LMB_Read_Strobe_20_UNCONNECTED,
LMB_Read_Strobe_21 => NLW_U0_LMB_Read_Strobe_21_UNCONNECTED,
LMB_Read_Strobe_22 => NLW_U0_LMB_Read_Strobe_22_UNCONNECTED,
LMB_Read_Strobe_23 => NLW_U0_LMB_Read_Strobe_23_UNCONNECTED,
LMB_Read_Strobe_24 => NLW_U0_LMB_Read_Strobe_24_UNCONNECTED,
LMB_Read_Strobe_25 => NLW_U0_LMB_Read_Strobe_25_UNCONNECTED,
LMB_Read_Strobe_26 => NLW_U0_LMB_Read_Strobe_26_UNCONNECTED,
LMB_Read_Strobe_27 => NLW_U0_LMB_Read_Strobe_27_UNCONNECTED,
LMB_Read_Strobe_28 => NLW_U0_LMB_Read_Strobe_28_UNCONNECTED,
LMB_Read_Strobe_29 => NLW_U0_LMB_Read_Strobe_29_UNCONNECTED,
LMB_Read_Strobe_3 => NLW_U0_LMB_Read_Strobe_3_UNCONNECTED,
LMB_Read_Strobe_30 => NLW_U0_LMB_Read_Strobe_30_UNCONNECTED,
LMB_Read_Strobe_31 => NLW_U0_LMB_Read_Strobe_31_UNCONNECTED,
LMB_Read_Strobe_4 => NLW_U0_LMB_Read_Strobe_4_UNCONNECTED,
LMB_Read_Strobe_5 => NLW_U0_LMB_Read_Strobe_5_UNCONNECTED,
LMB_Read_Strobe_6 => NLW_U0_LMB_Read_Strobe_6_UNCONNECTED,
LMB_Read_Strobe_7 => NLW_U0_LMB_Read_Strobe_7_UNCONNECTED,
LMB_Read_Strobe_8 => NLW_U0_LMB_Read_Strobe_8_UNCONNECTED,
LMB_Read_Strobe_9 => NLW_U0_LMB_Read_Strobe_9_UNCONNECTED,
LMB_Ready_0 => '0',
LMB_Ready_1 => '0',
LMB_Ready_10 => '0',
LMB_Ready_11 => '0',
LMB_Ready_12 => '0',
LMB_Ready_13 => '0',
LMB_Ready_14 => '0',
LMB_Ready_15 => '0',
LMB_Ready_16 => '0',
LMB_Ready_17 => '0',
LMB_Ready_18 => '0',
LMB_Ready_19 => '0',
LMB_Ready_2 => '0',
LMB_Ready_20 => '0',
LMB_Ready_21 => '0',
LMB_Ready_22 => '0',
LMB_Ready_23 => '0',
LMB_Ready_24 => '0',
LMB_Ready_25 => '0',
LMB_Ready_26 => '0',
LMB_Ready_27 => '0',
LMB_Ready_28 => '0',
LMB_Ready_29 => '0',
LMB_Ready_3 => '0',
LMB_Ready_30 => '0',
LMB_Ready_31 => '0',
LMB_Ready_4 => '0',
LMB_Ready_5 => '0',
LMB_Ready_6 => '0',
LMB_Ready_7 => '0',
LMB_Ready_8 => '0',
LMB_Ready_9 => '0',
LMB_UE_0 => '0',
LMB_UE_1 => '0',
LMB_UE_10 => '0',
LMB_UE_11 => '0',
LMB_UE_12 => '0',
LMB_UE_13 => '0',
LMB_UE_14 => '0',
LMB_UE_15 => '0',
LMB_UE_16 => '0',
LMB_UE_17 => '0',
LMB_UE_18 => '0',
LMB_UE_19 => '0',
LMB_UE_2 => '0',
LMB_UE_20 => '0',
LMB_UE_21 => '0',
LMB_UE_22 => '0',
LMB_UE_23 => '0',
LMB_UE_24 => '0',
LMB_UE_25 => '0',
LMB_UE_26 => '0',
LMB_UE_27 => '0',
LMB_UE_28 => '0',
LMB_UE_29 => '0',
LMB_UE_3 => '0',
LMB_UE_30 => '0',
LMB_UE_31 => '0',
LMB_UE_4 => '0',
LMB_UE_5 => '0',
LMB_UE_6 => '0',
LMB_UE_7 => '0',
LMB_UE_8 => '0',
LMB_UE_9 => '0',
LMB_Wait_0 => '0',
LMB_Wait_1 => '0',
LMB_Wait_10 => '0',
LMB_Wait_11 => '0',
LMB_Wait_12 => '0',
LMB_Wait_13 => '0',
LMB_Wait_14 => '0',
LMB_Wait_15 => '0',
LMB_Wait_16 => '0',
LMB_Wait_17 => '0',
LMB_Wait_18 => '0',
LMB_Wait_19 => '0',
LMB_Wait_2 => '0',
LMB_Wait_20 => '0',
LMB_Wait_21 => '0',
LMB_Wait_22 => '0',
LMB_Wait_23 => '0',
LMB_Wait_24 => '0',
LMB_Wait_25 => '0',
LMB_Wait_26 => '0',
LMB_Wait_27 => '0',
LMB_Wait_28 => '0',
LMB_Wait_29 => '0',
LMB_Wait_3 => '0',
LMB_Wait_30 => '0',
LMB_Wait_31 => '0',
LMB_Wait_4 => '0',
LMB_Wait_5 => '0',
LMB_Wait_6 => '0',
LMB_Wait_7 => '0',
LMB_Wait_8 => '0',
LMB_Wait_9 => '0',
LMB_Write_Strobe_0 => NLW_U0_LMB_Write_Strobe_0_UNCONNECTED,
LMB_Write_Strobe_1 => NLW_U0_LMB_Write_Strobe_1_UNCONNECTED,
LMB_Write_Strobe_10 => NLW_U0_LMB_Write_Strobe_10_UNCONNECTED,
LMB_Write_Strobe_11 => NLW_U0_LMB_Write_Strobe_11_UNCONNECTED,
LMB_Write_Strobe_12 => NLW_U0_LMB_Write_Strobe_12_UNCONNECTED,
LMB_Write_Strobe_13 => NLW_U0_LMB_Write_Strobe_13_UNCONNECTED,
LMB_Write_Strobe_14 => NLW_U0_LMB_Write_Strobe_14_UNCONNECTED,
LMB_Write_Strobe_15 => NLW_U0_LMB_Write_Strobe_15_UNCONNECTED,
LMB_Write_Strobe_16 => NLW_U0_LMB_Write_Strobe_16_UNCONNECTED,
LMB_Write_Strobe_17 => NLW_U0_LMB_Write_Strobe_17_UNCONNECTED,
LMB_Write_Strobe_18 => NLW_U0_LMB_Write_Strobe_18_UNCONNECTED,
LMB_Write_Strobe_19 => NLW_U0_LMB_Write_Strobe_19_UNCONNECTED,
LMB_Write_Strobe_2 => NLW_U0_LMB_Write_Strobe_2_UNCONNECTED,
LMB_Write_Strobe_20 => NLW_U0_LMB_Write_Strobe_20_UNCONNECTED,
LMB_Write_Strobe_21 => NLW_U0_LMB_Write_Strobe_21_UNCONNECTED,
LMB_Write_Strobe_22 => NLW_U0_LMB_Write_Strobe_22_UNCONNECTED,
LMB_Write_Strobe_23 => NLW_U0_LMB_Write_Strobe_23_UNCONNECTED,
LMB_Write_Strobe_24 => NLW_U0_LMB_Write_Strobe_24_UNCONNECTED,
LMB_Write_Strobe_25 => NLW_U0_LMB_Write_Strobe_25_UNCONNECTED,
LMB_Write_Strobe_26 => NLW_U0_LMB_Write_Strobe_26_UNCONNECTED,
LMB_Write_Strobe_27 => NLW_U0_LMB_Write_Strobe_27_UNCONNECTED,
LMB_Write_Strobe_28 => NLW_U0_LMB_Write_Strobe_28_UNCONNECTED,
LMB_Write_Strobe_29 => NLW_U0_LMB_Write_Strobe_29_UNCONNECTED,
LMB_Write_Strobe_3 => NLW_U0_LMB_Write_Strobe_3_UNCONNECTED,
LMB_Write_Strobe_30 => NLW_U0_LMB_Write_Strobe_30_UNCONNECTED,
LMB_Write_Strobe_31 => NLW_U0_LMB_Write_Strobe_31_UNCONNECTED,
LMB_Write_Strobe_4 => NLW_U0_LMB_Write_Strobe_4_UNCONNECTED,
LMB_Write_Strobe_5 => NLW_U0_LMB_Write_Strobe_5_UNCONNECTED,
LMB_Write_Strobe_6 => NLW_U0_LMB_Write_Strobe_6_UNCONNECTED,
LMB_Write_Strobe_7 => NLW_U0_LMB_Write_Strobe_7_UNCONNECTED,
LMB_Write_Strobe_8 => NLW_U0_LMB_Write_Strobe_8_UNCONNECTED,
LMB_Write_Strobe_9 => NLW_U0_LMB_Write_Strobe_9_UNCONNECTED,
M_AXIS_ACLK => '0',
M_AXIS_ARESETN => '0',
M_AXIS_TDATA(31 downto 0) => NLW_U0_M_AXIS_TDATA_UNCONNECTED(31 downto 0),
M_AXIS_TID(6 downto 0) => NLW_U0_M_AXIS_TID_UNCONNECTED(6 downto 0),
M_AXIS_TREADY => '1',
M_AXIS_TVALID => NLW_U0_M_AXIS_TVALID_UNCONNECTED,
M_AXI_ACLK => '0',
M_AXI_ARADDR(31 downto 0) => NLW_U0_M_AXI_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_ARBURST(1 downto 0) => NLW_U0_M_AXI_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_ARCACHE(3 downto 0) => NLW_U0_M_AXI_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_ARESETN => '0',
M_AXI_ARID(0) => NLW_U0_M_AXI_ARID_UNCONNECTED(0),
M_AXI_ARLEN(7 downto 0) => NLW_U0_M_AXI_ARLEN_UNCONNECTED(7 downto 0),
M_AXI_ARLOCK => NLW_U0_M_AXI_ARLOCK_UNCONNECTED,
M_AXI_ARPROT(2 downto 0) => NLW_U0_M_AXI_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_ARQOS(3 downto 0) => NLW_U0_M_AXI_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_ARREADY => '0',
M_AXI_ARSIZE(2 downto 0) => NLW_U0_M_AXI_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_ARVALID => NLW_U0_M_AXI_ARVALID_UNCONNECTED,
M_AXI_AWADDR(31 downto 0) => NLW_U0_M_AXI_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_AWBURST(1 downto 0) => NLW_U0_M_AXI_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_AWCACHE(3 downto 0) => NLW_U0_M_AXI_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_AWID(0) => NLW_U0_M_AXI_AWID_UNCONNECTED(0),
M_AXI_AWLEN(7 downto 0) => NLW_U0_M_AXI_AWLEN_UNCONNECTED(7 downto 0),
M_AXI_AWLOCK => NLW_U0_M_AXI_AWLOCK_UNCONNECTED,
M_AXI_AWPROT(2 downto 0) => NLW_U0_M_AXI_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_AWQOS(3 downto 0) => NLW_U0_M_AXI_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_AWREADY => '0',
M_AXI_AWSIZE(2 downto 0) => NLW_U0_M_AXI_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_AWVALID => NLW_U0_M_AXI_AWVALID_UNCONNECTED,
M_AXI_BID(0) => '0',
M_AXI_BREADY => NLW_U0_M_AXI_BREADY_UNCONNECTED,
M_AXI_BRESP(1 downto 0) => B"00",
M_AXI_BVALID => '0',
M_AXI_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_RID(0) => '0',
M_AXI_RLAST => '0',
M_AXI_RREADY => NLW_U0_M_AXI_RREADY_UNCONNECTED,
M_AXI_RRESP(1 downto 0) => B"00",
M_AXI_RVALID => '0',
M_AXI_WDATA(31 downto 0) => NLW_U0_M_AXI_WDATA_UNCONNECTED(31 downto 0),
M_AXI_WLAST => NLW_U0_M_AXI_WLAST_UNCONNECTED,
M_AXI_WREADY => '0',
M_AXI_WSTRB(3 downto 0) => NLW_U0_M_AXI_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_WVALID => NLW_U0_M_AXI_WVALID_UNCONNECTED,
S_AXI_ACLK => '0',
S_AXI_ARADDR(3 downto 0) => B"0000",
S_AXI_ARESETN => '0',
S_AXI_ARREADY => NLW_U0_S_AXI_ARREADY_UNCONNECTED,
S_AXI_ARVALID => '0',
S_AXI_AWADDR(3 downto 0) => B"0000",
S_AXI_AWREADY => NLW_U0_S_AXI_AWREADY_UNCONNECTED,
S_AXI_AWVALID => '0',
S_AXI_BREADY => '0',
S_AXI_BRESP(1 downto 0) => NLW_U0_S_AXI_BRESP_UNCONNECTED(1 downto 0),
S_AXI_BVALID => NLW_U0_S_AXI_BVALID_UNCONNECTED,
S_AXI_RDATA(31 downto 0) => NLW_U0_S_AXI_RDATA_UNCONNECTED(31 downto 0),
S_AXI_RREADY => '0',
S_AXI_RRESP(1 downto 0) => NLW_U0_S_AXI_RRESP_UNCONNECTED(1 downto 0),
S_AXI_RVALID => NLW_U0_S_AXI_RVALID_UNCONNECTED,
S_AXI_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_WREADY => NLW_U0_S_AXI_WREADY_UNCONNECTED,
S_AXI_WSTRB(3 downto 0) => B"0000",
S_AXI_WVALID => '0',
Scan_Reset => '0',
Scan_Reset_Sel => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_U0_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_U0_TRACE_CTL_UNCONNECTED,
TRACE_DATA(31 downto 0) => NLW_U0_TRACE_DATA_UNCONNECTED(31 downto 0),
Trig_Ack_In_0 => NLW_U0_Trig_Ack_In_0_UNCONNECTED,
Trig_Ack_In_1 => NLW_U0_Trig_Ack_In_1_UNCONNECTED,
Trig_Ack_In_2 => NLW_U0_Trig_Ack_In_2_UNCONNECTED,
Trig_Ack_In_3 => NLW_U0_Trig_Ack_In_3_UNCONNECTED,
Trig_Ack_Out_0 => '0',
Trig_Ack_Out_1 => '0',
Trig_Ack_Out_2 => '0',
Trig_Ack_Out_3 => '0',
Trig_In_0 => '0',
Trig_In_1 => '0',
Trig_In_2 => '0',
Trig_In_3 => '0',
Trig_Out_0 => NLW_U0_Trig_Out_0_UNCONNECTED,
Trig_Out_1 => NLW_U0_Trig_Out_1_UNCONNECTED,
Trig_Out_2 => NLW_U0_Trig_Out_2_UNCONNECTED,
Trig_Out_3 => NLW_U0_Trig_Out_3_UNCONNECTED,
bscan_ext_capture => '0',
bscan_ext_drck => '0',
bscan_ext_reset => '0',
bscan_ext_sel => '0',
bscan_ext_shift => '0',
bscan_ext_tdi => '0',
bscan_ext_tdo => NLW_U0_bscan_ext_tdo_UNCONNECTED,
bscan_ext_update => '0'
);
end STRUCTURE;
|
entity repro3 is
end repro3;
package repro3_pkg is
procedure inc (a : inout integer);
type prot is protected
procedure get (a : integer);
end protected prot;
end repro3_pkg;
package body repro3_pkg is
procedure inc (a : inout integer) is
begin
a := a + 1;
end inc;
procedure inc (a : inout time) is
begin
a := a + 1 ns;
end inc;
type prot is protected body
variable v : integer;
function inc (a : integer) return integer is
begin
return a + 1;
end inc;
procedure get (a : integer) is
begin
v := a;
end get;
end protected body prot;
end repro3_pkg;
use work.repro3_pkg.all;
architecture behav of repro3 is
begin -- behav
process
variable a : integer := 2;
begin
inc (a);
assert a = 3 report "bad value of a";
wait;
end process;
end behav;
|
entity repro3 is
end repro3;
package repro3_pkg is
procedure inc (a : inout integer);
type prot is protected
procedure get (a : integer);
end protected prot;
end repro3_pkg;
package body repro3_pkg is
procedure inc (a : inout integer) is
begin
a := a + 1;
end inc;
procedure inc (a : inout time) is
begin
a := a + 1 ns;
end inc;
type prot is protected body
variable v : integer;
function inc (a : integer) return integer is
begin
return a + 1;
end inc;
procedure get (a : integer) is
begin
v := a;
end get;
end protected body prot;
end repro3_pkg;
use work.repro3_pkg.all;
architecture behav of repro3 is
begin -- behav
process
variable a : integer := 2;
begin
inc (a);
assert a = 3 report "bad value of a";
wait;
end process;
end behav;
|
entity repro3 is
end repro3;
package repro3_pkg is
procedure inc (a : inout integer);
type prot is protected
procedure get (a : integer);
end protected prot;
end repro3_pkg;
package body repro3_pkg is
procedure inc (a : inout integer) is
begin
a := a + 1;
end inc;
procedure inc (a : inout time) is
begin
a := a + 1 ns;
end inc;
type prot is protected body
variable v : integer;
function inc (a : integer) return integer is
begin
return a + 1;
end inc;
procedure get (a : integer) is
begin
v := a;
end get;
end protected body prot;
end repro3_pkg;
use work.repro3_pkg.all;
architecture behav of repro3 is
begin -- behav
process
variable a : integer := 2;
begin
inc (a);
assert a = 3 report "bad value of a";
wait;
end process;
end behav;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_fg_20_07.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity top is
end entity top;
architecture top_arch of top is
signal top_sig : -- . . .; -- 1
--
bit;
--
begin
stimulus : process
is
variable var : -- . . .; -- 2
--
bit;
--
begin
-- . . .
--
report "--1: " & top'path_name;
report "--1: " & top'instance_name;
report "--1: " & top_sig'path_name;
report "--1: " & top_sig'instance_name;
report "--2: " & stimulus'path_name;
report "--2: " & stimulus'instance_name;
report "--2: " & var'path_name;
report "--2: " & var'instance_name;
wait;
--
end process stimulus;
rep_gen : for index in 0 to 7 generate
begin
end_gen : if index = 7 generate
signal end_sig : -- . . .; -- 3
--
bit;
--
begin
-- . . .
assert false report "--3: " & end_sig'path_name;
assert false report "--3: " & end_sig'instance_name;
--
end generate end_gen;
other_gen : if index /= 7 generate
signal other_sig : -- . . .; -- 4
--
bit;
--
begin
other_comp : entity work.bottom(bottom_arch)
port map ( -- . . . );
--
port_name => open );
assert false report "--4: " & other_sig'path_name;
assert false report "--4: " & other_sig'instance_name;
--
end generate other_gen;
end generate rep_gen;
end architecture top_arch;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_fg_20_07.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity top is
end entity top;
architecture top_arch of top is
signal top_sig : -- . . .; -- 1
--
bit;
--
begin
stimulus : process
is
variable var : -- . . .; -- 2
--
bit;
--
begin
-- . . .
--
report "--1: " & top'path_name;
report "--1: " & top'instance_name;
report "--1: " & top_sig'path_name;
report "--1: " & top_sig'instance_name;
report "--2: " & stimulus'path_name;
report "--2: " & stimulus'instance_name;
report "--2: " & var'path_name;
report "--2: " & var'instance_name;
wait;
--
end process stimulus;
rep_gen : for index in 0 to 7 generate
begin
end_gen : if index = 7 generate
signal end_sig : -- . . .; -- 3
--
bit;
--
begin
-- . . .
assert false report "--3: " & end_sig'path_name;
assert false report "--3: " & end_sig'instance_name;
--
end generate end_gen;
other_gen : if index /= 7 generate
signal other_sig : -- . . .; -- 4
--
bit;
--
begin
other_comp : entity work.bottom(bottom_arch)
port map ( -- . . . );
--
port_name => open );
assert false report "--4: " & other_sig'path_name;
assert false report "--4: " & other_sig'instance_name;
--
end generate other_gen;
end generate rep_gen;
end architecture top_arch;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_fg_20_07.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity top is
end entity top;
architecture top_arch of top is
signal top_sig : -- . . .; -- 1
--
bit;
--
begin
stimulus : process
is
variable var : -- . . .; -- 2
--
bit;
--
begin
-- . . .
--
report "--1: " & top'path_name;
report "--1: " & top'instance_name;
report "--1: " & top_sig'path_name;
report "--1: " & top_sig'instance_name;
report "--2: " & stimulus'path_name;
report "--2: " & stimulus'instance_name;
report "--2: " & var'path_name;
report "--2: " & var'instance_name;
wait;
--
end process stimulus;
rep_gen : for index in 0 to 7 generate
begin
end_gen : if index = 7 generate
signal end_sig : -- . . .; -- 3
--
bit;
--
begin
-- . . .
assert false report "--3: " & end_sig'path_name;
assert false report "--3: " & end_sig'instance_name;
--
end generate end_gen;
other_gen : if index /= 7 generate
signal other_sig : -- . . .; -- 4
--
bit;
--
begin
other_comp : entity work.bottom(bottom_arch)
port map ( -- . . . );
--
port_name => open );
assert false report "--4: " & other_sig'path_name;
assert false report "--4: " & other_sig'instance_name;
--
end generate other_gen;
end generate rep_gen;
end architecture top_arch;
|
--------------------------------------------------------------------------------
---- ----
---- This file is part of the yaVGA project ----
---- http://www.opencores.org/?do=project&who=yavga ----
---- ----
---- Description ----
---- Implementation of yaVGA IP core ----
---- ----
---- To Do: ----
---- ----
---- ----
---- Author(s): ----
---- Sandro Amato, [email protected] ----
---- ----
--------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2009, Sandro Amato ----
---- All rights reserved. ----
---- ----
---- Redistribution and use in source and binary forms, with or without ----
---- modification, are permitted provided that the following conditions ----
---- are met: ----
---- ----
---- * Redistributions of source code must retain the above ----
---- copyright notice, this list of conditions and the ----
---- following disclaimer. ----
---- * Redistributions in binary form must reproduce the above ----
---- copyright notice, this list of conditions and the ----
---- following disclaimer in the documentation and/or other ----
---- materials provided with the distribution. ----
---- * Neither the name of SANDRO AMATO nor the names of its ----
---- contributors may be used to endorse or promote products ----
---- derived from this software without specific prior written ----
---- permission. ----
---- ----
---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ----
---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ----
---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ----
---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ----
---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ----
---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ----
---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ----
---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ----
---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use work.yavga_pkg.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity waveform_RAM is
port (
i_DIA : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0); -- 16-bit Data Input
-- i_DIPA : in std_logic; -- 2-bit parity Input
-- i_ENA : in std_logic; -- RAM Enable Input
i_WEA : in std_logic; -- Write Enable Input
-- i_SSRA : in std_logic; -- Synchronous Set/Reset Input
i_clockA : in std_logic; -- Clock
i_ADDRA : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0); -- 10-bit Address Input
--o_DOA : out std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0); -- 16-bit Data Output
-- o_DOPA : out std_logic -- 2-bit parity Output
--
i_DIB : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0); -- 16-bit Data Input
-- i_DIPB : in std_logic; -- 2-bit parity Input
-- i_ENB : in std_logic; -- RAM Enable Input
i_WEB : in std_logic; -- Write Enable Input
-- i_SSRB : in std_logic; -- Synchronous Set/Reset Input
i_clockB : in std_logic; -- Clock
i_ADDRB : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0); -- 10-bit Address Input
o_DOB : out std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0) -- 16-bit Data Output
-- o_DOPB : out std_logic -- 2-bit parity Output
);
end waveform_RAM;
architecture Behavioral of waveform_RAM is
constant c_ram_size : natural := 2**(c_WAVFRM_ADDR_BUS_W);
type t_ram is array (c_ram_size-1 downto 0) of
std_logic_vector (c_WAVFRM_DATA_BUS_W - 1 downto 0);
shared variable v_ram : t_ram := (
0 => X"1000" or X"00BF",
1 => X"1000" or X"00BE",
2 => X"1000" or X"00BD",
3 => X"1000" or X"00BD",
4 => X"1000" or X"00BC",
5 => X"1000" or X"00BB",
6 => X"1000" or X"00BB",
7 => X"1000" or X"00BA",
8 => X"1000" or X"00B9",
9 => X"1000" or X"00B9",
10 => X"1000" or X"00B8",
11 => X"1000" or X"00B7",
12 => X"1000" or X"00B7",
13 => X"1000" or X"00B6",
14 => X"1000" or X"00B5",
15 => X"1000" or X"00B5",
16 => X"1000" or X"00B4",
17 => X"1000" or X"00B3",
18 => X"1000" or X"00B3",
19 => X"1000" or X"00B2",
20 => X"1000" or X"00B1",
21 => X"1000" or X"00B1",
22 => X"1000" or X"00B0",
23 => X"1000" or X"00B0",
24 => X"1000" or X"00AF",
25 => X"1000" or X"00AE",
26 => X"1000" or X"00AE",
27 => X"1000" or X"00AD",
28 => X"1000" or X"00AD",
29 => X"1000" or X"00AC",
30 => X"1000" or X"00AB",
31 => X"1000" or X"00AB",
32 => X"1000" or X"00AA",
33 => X"1000" or X"00AA",
34 => X"1000" or X"00A9",
35 => X"1000" or X"00A9",
36 => X"1000" or X"00A8",
37 => X"1000" or X"00A8",
38 => X"1000" or X"00A7",
39 => X"1000" or X"00A7",
40 => X"1000" or X"00A6",
41 => X"1000" or X"00A6",
42 => X"1000" or X"00A5",
43 => X"1000" or X"00A5",
44 => X"1000" or X"00A4",
45 => X"1000" or X"00A4",
46 => X"1000" or X"00A3",
47 => X"1000" or X"00A3",
48 => X"1000" or X"00A2",
49 => X"1000" or X"00A2",
50 => X"1000" or X"00A2",
51 => X"1000" or X"00A1",
52 => X"1000" or X"00A1",
53 => X"1000" or X"00A1",
54 => X"1000" or X"00A0",
55 => X"1000" or X"00A0",
56 => X"1000" or X"00A0",
57 => X"1000" or X"009F",
58 => X"1000" or X"009F",
59 => X"1000" or X"009F",
60 => X"1000" or X"009E",
61 => X"1000" or X"009E",
62 => X"1000" or X"009E",
63 => X"1000" or X"009E",
64 => X"1000" or X"009E",
65 => X"1000" or X"009D",
66 => X"1000" or X"009D",
67 => X"1000" or X"009D",
68 => X"1000" or X"009D",
69 => X"1000" or X"009D",
70 => X"1000" or X"009D",
71 => X"1000" or X"009D",
72 => X"1000" or X"009D",
73 => X"1000" or X"009D",
74 => X"1000" or X"009D",
75 => X"1000" or X"009D",
76 => X"1000" or X"009D",
77 => X"1000" or X"009D",
78 => X"1000" or X"009D",
79 => X"1000" or X"009D",
80 => X"1000" or X"009D",
81 => X"1000" or X"009D",
82 => X"1000" or X"009D",
83 => X"1000" or X"009D",
84 => X"1000" or X"009D",
85 => X"1000" or X"009D",
86 => X"1000" or X"009E",
87 => X"1000" or X"009E",
88 => X"1000" or X"009E",
89 => X"1000" or X"009E",
90 => X"1000" or X"009E",
91 => X"1000" or X"009F",
92 => X"1000" or X"009F",
93 => X"1000" or X"009F",
94 => X"1000" or X"00A0",
95 => X"1000" or X"00A0",
96 => X"1000" or X"00A0",
97 => X"1000" or X"00A1",
98 => X"1000" or X"00A1",
99 => X"1000" or X"00A2",
100 => X"1000" or X"00A2",
101 => X"1000" or X"00A3",
102 => X"1000" or X"00A3",
103 => X"1000" or X"00A4",
104 => X"1000" or X"00A4",
105 => X"1000" or X"00A5",
106 => X"1000" or X"00A5",
107 => X"1000" or X"00A6",
108 => X"1000" or X"00A7",
109 => X"1000" or X"00A7",
110 => X"1000" or X"00A8",
111 => X"1000" or X"00A8",
112 => X"1000" or X"00A9",
113 => X"1000" or X"00AA",
114 => X"1000" or X"00AB",
115 => X"1000" or X"00AB",
116 => X"1000" or X"00AC",
117 => X"1000" or X"00AD",
118 => X"1000" or X"00AE",
119 => X"1000" or X"00AF",
120 => X"1000" or X"00AF",
121 => X"1000" or X"00B0",
122 => X"1000" or X"00B1",
123 => X"1000" or X"00B2",
124 => X"1000" or X"00B3",
125 => X"1000" or X"00B4",
126 => X"1000" or X"00B5",
127 => X"1000" or X"00B6",
128 => X"1000" or X"00B7",
129 => X"1000" or X"00B8",
130 => X"1000" or X"00B9",
131 => X"1000" or X"00BA",
132 => X"1000" or X"00BB",
133 => X"1000" or X"00BC",
134 => X"1000" or X"00BD",
135 => X"1000" or X"00BE",
136 => X"1000" or X"00C0",
137 => X"1000" or X"00C1",
138 => X"1000" or X"00C2",
139 => X"1000" or X"00C3",
140 => X"1000" or X"00C4",
141 => X"1000" or X"00C6",
142 => X"1000" or X"00C7",
143 => X"1000" or X"00C8",
144 => X"1000" or X"00C9",
145 => X"1000" or X"00CB",
146 => X"1000" or X"00CC",
147 => X"1000" or X"00CD",
148 => X"1000" or X"00CF",
149 => X"1000" or X"00D0",
150 => X"1000" or X"00D1",
151 => X"1000" or X"00D3",
152 => X"1000" or X"00D4",
153 => X"1000" or X"00D6",
154 => X"1000" or X"00D7",
155 => X"1000" or X"00D8",
156 => X"1000" or X"00DA",
157 => X"1000" or X"00DB",
158 => X"1000" or X"00DD",
159 => X"1000" or X"00DE",
160 => X"1000" or X"00E0",
161 => X"1000" or X"00E1",
162 => X"1000" or X"00E3",
163 => X"1000" or X"00E5",
164 => X"1000" or X"00E6",
165 => X"1000" or X"00E8",
166 => X"1000" or X"00E9",
167 => X"1000" or X"00EB",
168 => X"1000" or X"00EC",
169 => X"1000" or X"00EE",
170 => X"1000" or X"00F0",
171 => X"1000" or X"00F1",
172 => X"1000" or X"00F3",
173 => X"1000" or X"00F5",
174 => X"1000" or X"00F6",
175 => X"1000" or X"00F8",
176 => X"1000" or X"00FA",
177 => X"1000" or X"00FB",
178 => X"1000" or X"00FD",
179 => X"1000" or X"00FF",
180 => X"1000" or X"0100",
181 => X"1000" or X"0102",
182 => X"1000" or X"0104",
183 => X"1000" or X"0105",
184 => X"1000" or X"0107",
185 => X"1000" or X"0109",
186 => X"1000" or X"010B",
187 => X"1000" or X"010C",
188 => X"1000" or X"010E",
189 => X"1000" or X"0110",
190 => X"1000" or X"0111",
191 => X"1000" or X"0113",
192 => X"1000" or X"0115",
193 => X"1000" or X"0117",
194 => X"1000" or X"0118",
195 => X"1000" or X"011A",
196 => X"1000" or X"011C",
197 => X"1000" or X"011E",
198 => X"1000" or X"011F",
199 => X"1000" or X"0121",
200 => X"1000" or X"0123",
201 => X"1000" or X"0125",
202 => X"1000" or X"0126",
203 => X"1000" or X"0128",
204 => X"1000" or X"012A",
205 => X"1000" or X"012C",
206 => X"1000" or X"012D",
207 => X"1000" or X"012F",
208 => X"1000" or X"0131",
209 => X"1000" or X"0132",
210 => X"1000" or X"0134",
211 => X"1000" or X"0136",
212 => X"1000" or X"0138",
213 => X"1000" or X"0139",
214 => X"1000" or X"013B",
215 => X"1000" or X"013D",
216 => X"1000" or X"013E",
217 => X"1000" or X"0140",
218 => X"1000" or X"0142",
219 => X"1000" or X"0143",
220 => X"1000" or X"0145",
221 => X"1000" or X"0147",
222 => X"1000" or X"0148",
223 => X"1000" or X"014A",
224 => X"1000" or X"014B",
225 => X"1000" or X"014D",
226 => X"1000" or X"014F",
227 => X"1000" or X"0150",
228 => X"1000" or X"0152",
229 => X"1000" or X"0153",
230 => X"1000" or X"0155",
231 => X"1000" or X"0156",
232 => X"1000" or X"0158",
233 => X"1000" or X"0159",
234 => X"1000" or X"015B",
235 => X"1000" or X"015C",
236 => X"1000" or X"015E",
237 => X"1000" or X"015F",
238 => X"1000" or X"0161",
239 => X"1000" or X"0162",
240 => X"1000" or X"0163",
241 => X"1000" or X"0165",
242 => X"1000" or X"0166",
243 => X"1000" or X"0167",
244 => X"1000" or X"0169",
245 => X"1000" or X"016A",
246 => X"1000" or X"016B",
247 => X"1000" or X"016D",
248 => X"1000" or X"016E",
249 => X"1000" or X"016F",
250 => X"1000" or X"0170",
251 => X"1000" or X"0171",
252 => X"1000" or X"0173",
253 => X"1000" or X"0174",
254 => X"1000" or X"0175",
255 => X"1000" or X"0176",
256 => X"1000" or X"0177",
257 => X"1000" or X"0178",
258 => X"1000" or X"0179",
259 => X"1000" or X"017A",
260 => X"1000" or X"017B",
261 => X"1000" or X"017C",
262 => X"1000" or X"017D",
263 => X"1000" or X"017E",
264 => X"1000" or X"017F",
265 => X"1000" or X"0180",
266 => X"1000" or X"0181",
267 => X"1000" or X"0182",
268 => X"1000" or X"0183",
269 => X"1000" or X"0183",
270 => X"1000" or X"0184",
271 => X"1000" or X"0185",
272 => X"1000" or X"0186",
273 => X"1000" or X"0186",
274 => X"1000" or X"0187",
275 => X"1000" or X"0188",
276 => X"1000" or X"0188",
277 => X"1000" or X"0189",
278 => X"1000" or X"018A",
279 => X"1000" or X"018A",
280 => X"1000" or X"018B",
281 => X"1000" or X"018B",
282 => X"1000" or X"018C",
283 => X"1000" or X"018C",
284 => X"1000" or X"018D",
285 => X"1000" or X"018D",
286 => X"1000" or X"018D",
287 => X"1000" or X"018E",
288 => X"1000" or X"018E",
289 => X"1000" or X"018E",
290 => X"1000" or X"018F",
291 => X"1000" or X"018F",
292 => X"1000" or X"018F",
293 => X"1000" or X"018F",
294 => X"1000" or X"0190",
295 => X"1000" or X"0190",
296 => X"1000" or X"0190",
297 => X"1000" or X"0190",
298 => X"1000" or X"0190",
299 => X"1000" or X"0190",
300 => X"1000" or X"0190",
301 => X"1000" or X"0190",
302 => X"1000" or X"0190",
303 => X"1000" or X"0190",
304 => X"1000" or X"0190",
305 => X"1000" or X"0190",
306 => X"1000" or X"0190",
307 => X"1000" or X"018F",
308 => X"1000" or X"018F",
309 => X"1000" or X"018F",
310 => X"1000" or X"018F",
311 => X"1000" or X"018E",
312 => X"1000" or X"018E",
313 => X"1000" or X"018E",
314 => X"1000" or X"018D",
315 => X"1000" or X"018D",
316 => X"1000" or X"018D",
317 => X"1000" or X"018C",
318 => X"1000" or X"018C",
319 => X"1000" or X"018B",
320 => X"1000" or X"018B",
321 => X"1000" or X"018A",
322 => X"1000" or X"018A",
323 => X"1000" or X"0189",
324 => X"1000" or X"0188",
325 => X"1000" or X"0188",
326 => X"1000" or X"0187",
327 => X"1000" or X"0186",
328 => X"1000" or X"0186",
329 => X"1000" or X"0185",
330 => X"1000" or X"0184",
331 => X"1000" or X"0183",
332 => X"1000" or X"0183",
333 => X"1000" or X"0182",
334 => X"1000" or X"0181",
335 => X"1000" or X"0180",
336 => X"1000" or X"017F",
337 => X"1000" or X"017E",
338 => X"1000" or X"017D",
339 => X"1000" or X"017C",
340 => X"1000" or X"017B",
341 => X"1000" or X"017A",
342 => X"1000" or X"0179",
343 => X"1000" or X"0178",
344 => X"1000" or X"0177",
345 => X"1000" or X"0176",
346 => X"1000" or X"0175",
347 => X"1000" or X"0174",
348 => X"1000" or X"0173",
349 => X"1000" or X"0171",
350 => X"1000" or X"0170",
351 => X"1000" or X"016F",
352 => X"1000" or X"016E",
353 => X"1000" or X"016D",
354 => X"1000" or X"016B",
355 => X"1000" or X"016A",
356 => X"1000" or X"0169",
357 => X"1000" or X"0167",
358 => X"1000" or X"0166",
359 => X"1000" or X"0165",
360 => X"1000" or X"0163",
361 => X"1000" or X"0162",
362 => X"1000" or X"0161",
363 => X"1000" or X"015F",
364 => X"1000" or X"015E",
365 => X"1000" or X"015C",
366 => X"1000" or X"015B",
367 => X"1000" or X"0159",
368 => X"1000" or X"0158",
369 => X"1000" or X"0156",
370 => X"1000" or X"0155",
371 => X"1000" or X"0153",
372 => X"1000" or X"0152",
373 => X"1000" or X"0150",
374 => X"1000" or X"014F",
375 => X"1000" or X"014D",
376 => X"1000" or X"014B",
377 => X"1000" or X"014A",
378 => X"1000" or X"0148",
379 => X"1000" or X"0147",
380 => X"1000" or X"0145",
381 => X"1000" or X"0143",
382 => X"1000" or X"0142",
383 => X"1000" or X"0140",
384 => X"1000" or X"013E",
385 => X"1000" or X"013D",
386 => X"1000" or X"013B",
387 => X"1000" or X"0139",
388 => X"1000" or X"0138",
389 => X"1000" or X"0136",
390 => X"1000" or X"0134",
391 => X"1000" or X"0132",
392 => X"1000" or X"0131",
393 => X"1000" or X"012F",
394 => X"1000" or X"012D",
395 => X"1000" or X"012C",
396 => X"1000" or X"012A",
397 => X"1000" or X"0128",
398 => X"1000" or X"0126",
399 => X"1000" or X"0125",
400 => X"1000" or X"0123",
401 => X"1000" or X"0121",
402 => X"1000" or X"011F",
403 => X"1000" or X"011E",
404 => X"1000" or X"011C",
405 => X"1000" or X"011A",
406 => X"1000" or X"0118",
407 => X"1000" or X"0117",
408 => X"1000" or X"0115",
409 => X"1000" or X"0113",
410 => X"1000" or X"0111",
411 => X"1000" or X"0110",
412 => X"1000" or X"010E",
413 => X"1000" or X"010C",
414 => X"1000" or X"010B",
415 => X"1000" or X"0109",
416 => X"1000" or X"0107",
417 => X"1000" or X"0105",
418 => X"1000" or X"0104",
419 => X"1000" or X"0102",
420 => X"1000" or X"0100",
421 => X"1000" or X"00FF",
422 => X"1000" or X"00FD",
423 => X"1000" or X"00FB",
424 => X"1000" or X"00FA",
425 => X"1000" or X"00F8",
426 => X"1000" or X"00F6",
427 => X"1000" or X"00F5",
428 => X"1000" or X"00F3",
429 => X"1000" or X"00F1",
430 => X"1000" or X"00F0",
431 => X"1000" or X"00EE",
432 => X"1000" or X"00EC",
433 => X"1000" or X"00EB",
434 => X"1000" or X"00E9",
435 => X"1000" or X"00E8",
436 => X"1000" or X"00E6",
437 => X"1000" or X"00E5",
438 => X"1000" or X"00E3",
439 => X"1000" or X"00E1",
440 => X"1000" or X"00E0",
441 => X"1000" or X"00DE",
442 => X"1000" or X"00DD",
443 => X"1000" or X"00DB",
444 => X"1000" or X"00DA",
445 => X"1000" or X"00D8",
446 => X"1000" or X"00D7",
447 => X"1000" or X"00D6",
448 => X"1000" or X"00D4",
449 => X"1000" or X"00D3",
450 => X"1000" or X"00D1",
451 => X"1000" or X"00D0",
452 => X"1000" or X"00CF",
453 => X"1000" or X"00CD",
454 => X"1000" or X"00CC",
455 => X"1000" or X"00CB",
456 => X"1000" or X"00C9",
457 => X"1000" or X"00C8",
458 => X"1000" or X"00C7",
459 => X"1000" or X"00C6",
460 => X"1000" or X"00C4",
461 => X"1000" or X"00C3",
462 => X"1000" or X"00C2",
463 => X"1000" or X"00C1",
464 => X"1000" or X"00C0",
465 => X"1000" or X"00BE",
466 => X"1000" or X"00BD",
467 => X"1000" or X"00BC",
468 => X"1000" or X"00BB",
469 => X"1000" or X"00BA",
470 => X"1000" or X"00B9",
471 => X"1000" or X"00B8",
472 => X"1000" or X"00B7",
473 => X"1000" or X"00B6",
474 => X"1000" or X"00B5",
475 => X"1000" or X"00B4",
476 => X"1000" or X"00B3",
477 => X"1000" or X"00B2",
478 => X"1000" or X"00B1",
479 => X"1000" or X"00B0",
480 => X"1000" or X"00AF",
481 => X"1000" or X"00AF",
482 => X"1000" or X"00AE",
483 => X"1000" or X"00AD",
484 => X"1000" or X"00AC",
485 => X"1000" or X"00AB",
486 => X"1000" or X"00AB",
487 => X"1000" or X"00AA",
488 => X"1000" or X"00A9",
489 => X"1000" or X"00A8",
490 => X"1000" or X"00A8",
491 => X"1000" or X"00A7",
492 => X"1000" or X"00A7",
493 => X"1000" or X"00A6",
494 => X"1000" or X"00A5",
495 => X"1000" or X"00A5",
496 => X"1000" or X"00A4",
497 => X"1000" or X"00A4",
498 => X"1000" or X"00A3",
499 => X"1000" or X"00A3",
500 => X"1000" or X"00A2",
501 => X"1000" or X"00A2",
502 => X"1000" or X"00A1",
503 => X"1000" or X"00A1",
504 => X"1000" or X"00A0",
505 => X"1000" or X"00A0",
506 => X"1000" or X"00A0",
507 => X"1000" or X"009F",
508 => X"1000" or X"009F",
509 => X"1000" or X"009F",
510 => X"1000" or X"009E",
511 => X"1000" or X"009E",
512 => X"1000" or X"009E",
513 => X"1000" or X"009E",
514 => X"1000" or X"009E",
515 => X"1000" or X"009D",
516 => X"1000" or X"009D",
517 => X"1000" or X"009D",
518 => X"1000" or X"009D",
519 => X"1000" or X"009D",
520 => X"1000" or X"009D",
521 => X"1000" or X"009D",
522 => X"1000" or X"009D",
523 => X"1000" or X"009D",
524 => X"1000" or X"009D",
525 => X"1000" or X"009D",
526 => X"1000" or X"009D",
527 => X"1000" or X"009D",
528 => X"1000" or X"009D",
529 => X"1000" or X"009D",
530 => X"1000" or X"009D",
531 => X"1000" or X"009D",
532 => X"1000" or X"009D",
533 => X"1000" or X"009D",
534 => X"1000" or X"009D",
535 => X"1000" or X"009D",
536 => X"1000" or X"009E",
537 => X"1000" or X"009E",
538 => X"1000" or X"009E",
539 => X"1000" or X"009E",
540 => X"1000" or X"009E",
541 => X"1000" or X"009F",
542 => X"1000" or X"009F",
543 => X"1000" or X"009F",
544 => X"1000" or X"00A0",
545 => X"1000" or X"00A0",
546 => X"1000" or X"00A0",
547 => X"1000" or X"00A1",
548 => X"1000" or X"00A1",
549 => X"1000" or X"00A1",
550 => X"1000" or X"00A2",
551 => X"1000" or X"00A2",
552 => X"1000" or X"00A2",
553 => X"1000" or X"00A3",
554 => X"1000" or X"00A3",
555 => X"1000" or X"00A4",
556 => X"1000" or X"00A4",
557 => X"1000" or X"00A5",
558 => X"1000" or X"00A5",
559 => X"1000" or X"00A6",
560 => X"1000" or X"00A6",
561 => X"1000" or X"00A7",
562 => X"1000" or X"00A7",
563 => X"1000" or X"00A8",
564 => X"1000" or X"00A8",
565 => X"1000" or X"00A9",
566 => X"1000" or X"00A9",
567 => X"1000" or X"00AA",
568 => X"1000" or X"00AA",
569 => X"1000" or X"00AB",
570 => X"1000" or X"00AB",
571 => X"1000" or X"00AC",
572 => X"1000" or X"00AD",
573 => X"1000" or X"00AD",
574 => X"1000" or X"00AE",
575 => X"1000" or X"00AE",
576 => X"1000" or X"00AF",
577 => X"1000" or X"00B0",
578 => X"1000" or X"00B0",
579 => X"1000" or X"00B1",
580 => X"1000" or X"00B1",
581 => X"1000" or X"00B2",
582 => X"1000" or X"00B3",
583 => X"1000" or X"00B3",
584 => X"1000" or X"00B4",
585 => X"1000" or X"00B5",
586 => X"1000" or X"00B5",
587 => X"1000" or X"00B6",
588 => X"1000" or X"00B7",
589 => X"1000" or X"00B7",
590 => X"1000" or X"00B8",
591 => X"1000" or X"00B9",
592 => X"1000" or X"00B9",
593 => X"1000" or X"00BA",
594 => X"1000" or X"00BB",
595 => X"1000" or X"00BB",
596 => X"1000" or X"00BC",
597 => X"1000" or X"00BD",
598 => X"1000" or X"00BD",
599 => X"1000" or X"00BE",
600 => X"1000" or X"00BF",
601 => X"1000" or X"00BF",
602 => X"1000" or X"00C0",
603 => X"1000" or X"00C1",
604 => X"1000" or X"00C1",
605 => X"1000" or X"00C2",
606 => X"1000" or X"00C3",
607 => X"1000" or X"00C3",
608 => X"1000" or X"00C4",
609 => X"1000" or X"00C5",
610 => X"1000" or X"00C5",
611 => X"1000" or X"00C6",
612 => X"1000" or X"00C7",
613 => X"1000" or X"00C7",
614 => X"1000" or X"00C8",
615 => X"1000" or X"00C9",
616 => X"1000" or X"00C9",
617 => X"1000" or X"00CA",
618 => X"1000" or X"00CA",
619 => X"1000" or X"00CB",
620 => X"1000" or X"00CC",
621 => X"1000" or X"00CC",
622 => X"1000" or X"00CD",
623 => X"1000" or X"00CD",
624 => X"1000" or X"00CE",
625 => X"1000" or X"00CF",
626 => X"1000" or X"00CF",
627 => X"1000" or X"00D0",
628 => X"1000" or X"00D0",
629 => X"1000" or X"00D1",
630 => X"1000" or X"00D1",
631 => X"1000" or X"00D2",
632 => X"1000" or X"00D3",
633 => X"1000" or X"00D3",
634 => X"1000" or X"00D4",
635 => X"1000" or X"00D4",
636 => X"1000" or X"00D5",
637 => X"1000" or X"00D5",
638 => X"1000" or X"00D6",
639 => X"1000" or X"00D6",
640 => X"1000" or X"00D7",
641 => X"1000" or X"00D7",
642 => X"1000" or X"00D7",
643 => X"1000" or X"00D8",
644 => X"1000" or X"00D8",
645 => X"1000" or X"00D9",
646 => X"1000" or X"00D9",
647 => X"1000" or X"00DA",
648 => X"1000" or X"00DA",
649 => X"1000" or X"00DA",
650 => X"1000" or X"00DB",
651 => X"1000" or X"00DB",
652 => X"1000" or X"00DC",
653 => X"1000" or X"00DC",
654 => X"1000" or X"00DC",
655 => X"1000" or X"00DD",
656 => X"1000" or X"00DD",
657 => X"1000" or X"00DD",
658 => X"1000" or X"00DD",
659 => X"1000" or X"00DE",
660 => X"1000" or X"00DE",
661 => X"1000" or X"00DE",
662 => X"1000" or X"00DF",
663 => X"1000" or X"00DF",
664 => X"1000" or X"00DF",
665 => X"1000" or X"00DF",
666 => X"1000" or X"00E0",
667 => X"1000" or X"00E0",
668 => X"1000" or X"00E0",
669 => X"1000" or X"00E0",
670 => X"1000" or X"00E0",
671 => X"1000" or X"00E0",
672 => X"1000" or X"00E1",
673 => X"1000" or X"00E1",
674 => X"1000" or X"00E1",
675 => X"1000" or X"00E1",
676 => X"1000" or X"00E1",
677 => X"1000" or X"00E1",
678 => X"1000" or X"00E1",
679 => X"1000" or X"00E1",
680 => X"1000" or X"00E1",
681 => X"1000" or X"00E2",
682 => X"1000" or X"00E2",
683 => X"1000" or X"00E2",
684 => X"1000" or X"00E2",
685 => X"1000" or X"00E2",
686 => X"1000" or X"00E2",
687 => X"1000" or X"00E2",
688 => X"1000" or X"00E2",
689 => X"1000" or X"00E2",
690 => X"1000" or X"00E2",
691 => X"1000" or X"00E2",
692 => X"1000" or X"00E2",
693 => X"1000" or X"00E1",
694 => X"1000" or X"00E1",
695 => X"1000" or X"00E1",
696 => X"1000" or X"00E1",
697 => X"1000" or X"00E1",
698 => X"1000" or X"00E1",
699 => X"1000" or X"00E1",
700 => X"1000" or X"00E1",
701 => X"1000" or X"00E1",
702 => X"1000" or X"00E0",
703 => X"1000" or X"00E0",
704 => X"1000" or X"00E0",
705 => X"1000" or X"00E0",
706 => X"1000" or X"00E0",
707 => X"1000" or X"00E0",
708 => X"1000" or X"00DF",
709 => X"1000" or X"00DF",
710 => X"1000" or X"00DF",
711 => X"1000" or X"00DF",
712 => X"1000" or X"00DE",
713 => X"1000" or X"00DE",
714 => X"1000" or X"00DE",
715 => X"1000" or X"00DE",
716 => X"1000" or X"00DD",
717 => X"1000" or X"00DD",
718 => X"1000" or X"00DD",
719 => X"1000" or X"00DD",
720 => X"1000" or X"00DC",
721 => X"1000" or X"00DC",
722 => X"1000" or X"00DC",
723 => X"1000" or X"00DB",
724 => X"1000" or X"00DB",
725 => X"1000" or X"00DB",
726 => X"1000" or X"00DA",
727 => X"1000" or X"00DA",
728 => X"1000" or X"00DA",
729 => X"1000" or X"00D9",
730 => X"1000" or X"00D9",
731 => X"1000" or X"00D9",
732 => X"1000" or X"00D8",
733 => X"1000" or X"00D8",
734 => X"1000" or X"00D8",
735 => X"1000" or X"00D7",
736 => X"1000" or X"00D7",
737 => X"1000" or X"00D6",
738 => X"1000" or X"00D6",
739 => X"1000" or X"00D6",
740 => X"1000" or X"00D5",
741 => X"1000" or X"00D5",
742 => X"1000" or X"00D4",
743 => X"1000" or X"00D4",
744 => X"1000" or X"00D4",
745 => X"1000" or X"00D3",
746 => X"1000" or X"00D3",
747 => X"1000" or X"00D2",
748 => X"1000" or X"00D2",
749 => X"1000" or X"00D2",
750 => X"1000" or X"00D1",
751 => X"1000" or X"00D1",
752 => X"1000" or X"00D0",
753 => X"1000" or X"00D0",
754 => X"1000" or X"00CF",
755 => X"1000" or X"00CF",
756 => X"1000" or X"00CF",
757 => X"1000" or X"00CE",
758 => X"1000" or X"00CE",
759 => X"1000" or X"00CD",
760 => X"1000" or X"00CD",
761 => X"1000" or X"00CC",
762 => X"1000" or X"00CC",
763 => X"1000" or X"00CC",
764 => X"1000" or X"00CB",
765 => X"1000" or X"00CB",
766 => X"1000" or X"00CA",
767 => X"1000" or X"00CA",
768 => X"1000" or X"00C9",
769 => X"1000" or X"00C9",
770 => X"1000" or X"00C9",
771 => X"1000" or X"00C8",
772 => X"1000" or X"00C8",
773 => X"1000" or X"00C7",
774 => X"1000" or X"00C7",
775 => X"1000" or X"00C6",
776 => X"1000" or X"00C6",
777 => X"1000" or X"00C6",
778 => X"1000" or X"00C5",
779 => X"1000" or X"00C5",
780 => X"1000" or X"00C4",
781 => X"1000" or X"00C4",
782 => X"1000" or X"00C4",
783 => X"1000" or X"00C3",
784 => X"1000" or X"00C3",
785 => X"1000" or X"00C2",
786 => X"1000" or X"00C2",
787 => X"1000" or X"00C2",
788 => X"1000" or X"00C1",
789 => X"1000" or X"00C1",
790 => X"1000" or X"00C1",
791 => X"1000" or X"00C0",
792 => X"1000" or X"00C0",
793 => X"1000" or X"00BF",
794 => X"1000" or X"00BF",
795 => X"1000" or X"00BF",
796 => X"1000" or X"00BE",
797 => X"1000" or X"00BE",
798 => X"1000" or X"00BE",
799 => X"1000" or X"00BD",
800 => X"1000" or X"00BD",
others => X"1000" or X"0064"
);
begin
-- wave form or video-line memory
-- |------| |-------------------------------------------|
-- | P P | | D D D | D D D | D D D D D D D D D D |
-- |======| |===========================================|
-- |17 16 | | 15 14 13 | 12 11 10 | 9 8 7 6 5 4 3 2 1 0 |
-- |======| |===========================================|
-- | Free | | Reserv. | R G B | vert. pos. |
-- |------| |-------------------------------------------|
--
p_rw0_port : process (i_clockA)
begin
if rising_edge(i_clockA) then
if (true) then
if (i_WEA = '1') then
v_ram(conv_integer(i_ADDRA)) := i_DIA;
end if;
--o_DOA <= v_ram(conv_integer(i_ADDRA));
end if;
end if;
end process;
p_rw1_port : process (i_clockB)
begin
if rising_edge(i_clockB) then
if (true) then
o_DOB <= v_ram(conv_integer(i_ADDRB));
if (i_WEB = '1') then
v_ram(conv_integer(i_ADDRB)) := i_DIB;
end if;
end if;
end if;
end process;
end Behavioral;
|
entity sub is
port (
i : in bit;
o : out bit );
end entity;
architecture test of sub is
begin
o <= i;
end architecture;
-------------------------------------------------------------------------------
entity source1 is
end entity;
architecture test of source1 is
signal x : bit;
signal y : bit_vector(1 to 5);
begin
x <= '1';
foo: x <= '0'; -- Error
y <= "10000";
y(2 to 3) <= "11"; -- Error
sub1_i: entity work.sub port map ( x, y(4) );
sub2_i: entity work.sub port map ( x, y(2) );
end architecture;
|
-- Descp.
--
-- entity name: g05_mastermind_game
--
-- Version 1.0
-- Author: Felix Dube; [email protected] & Auguste Lalande; [email protected]
-- Date: November 26, 2015
library ieee;
use ieee.std_logic_1164.all;
entity g05_mastermind_game is
port (
start, ready : in std_logic;
sel, increment : in std_logic;
mode : in std_logic;
clk : in std_logic;
seg_1, seg_2, seg_3, seg_4, seg_5, seg_6 : out std_logic_vector(6 downto 0)
);
end g05_mastermind_game;
architecture behavior of g05_mastermind_game is
component g05_mastermind_controller is
port (
TM_OUT : in std_logic;
SC_CMP, TC_LAST : in std_logic;
START, READY : in std_logic;
MODE : in std_logic;
CLK : in std_logic;
START_MODE : out std_logic;
DEFAULT_SCORE : out std_logic;
SR_SEL, P_SEL, GR_SEL : out std_logic;
GR_LD, SR_LD : out std_logic;
TM_IN, TM_EN, TC_EN, TC_RST : out std_logic;
SOLVED : out std_logic
);
end component;
component g05_mastermind_datapath is
port (
P_SEL, GR_SEL, SR_SEL : in std_logic;
GR_LD, SR_LD : in std_logic;
TM_IN, TM_EN, TC_RST, TC_EN : in std_logic;
EXT_PATTERN : in std_logic_vector(11 downto 0);
EXT_SCORE : in std_logic_vector(3 downto 0);
MODE : in std_logic;
START_MODE : in std_logic;
CLK : in std_logic;
TM_OUT : out std_logic;
TC_LAST : out std_logic;
SC_CMP : out std_logic;
DIS_P1, DIS_P2, DIS_P3, DIS_P4, DIS_P5, DIS_P6 : out std_logic_vector(3 downto 0)
);
end component;
signal P_SEL, GR_SEL, SR_SEL : std_logic;
signal GR_LD, SR_LD : std_logic;
signal TM_IN, TM_OUT, TM_EN, TC_RST, TC_EN : std_logic;
signal TC_LAST : std_logic;
signal SC_CMP : std_logic;
signal SOLVED : std_logic;
signal tmp_P5, tmp_P6 : std_logic_vector(3 downto 0);
signal DIS_P1, DIS_P2, DIS_P3, DIS_P4, DIS_P5, DIS_P6 : std_logic_vector(3 downto 0);
signal START_MODE, DEFAULT_SCORE : std_logic;
component g05_pattern_input is
port (
increment, sel : in std_logic;
seg_code : out std_logic_vector(2 downto 0);
segment : out std_logic_vector(1 downto 0)
);
end component;
signal seg_code : std_logic_vector(2 downto 0);
signal segment : std_logic_vector(1 downto 0);
signal ext_p1, ext_p2, ext_p3, ext_p4 : std_logic_vector(2 downto 0);
signal ext_pattern : std_logic_vector(11 downto 0);
component g05_score_input is
port (
increment, sel : in std_logic;
score : out std_logic_vector(2 downto 0);
score_part : out std_logic
);
end component;
signal score : std_logic_vector(2 downto 0);
signal exact_matches, color_matches : std_logic_vector(2 downto 0);
signal score_part : std_logic;
component g05_score_encoder is
port (
score_code : out std_logic_vector(3 downto 0);
num_exact_matches : in std_logic_vector(2 downto 0);
num_color_matches : in std_logic_vector(2 downto 0)
);
end component;
signal encoded_score : std_logic_vector(3 downto 0);
component g05_7_segment_decoder is
port (
code : in std_logic_vector(3 downto 0);
RippleBlank_In : in std_logic;
RippleBlank_Out : out std_logic;
segments : out std_logic_vector(6 downto 0)
);
end component;
begin
pattern_input : g05_pattern_input
port map (increment => increment, sel => sel,
seg_code => seg_code, segment => segment);
ext_p1 <= seg_code when segment = "00";
ext_p2 <= seg_code when segment = "01";
ext_p3 <= seg_code when segment = "10";
ext_p4 <= seg_code when segment = "11";
ext_pattern <= ext_p1 & ext_p2 & ext_p3 & ext_p4;
score_input : g05_score_input
port map (increment => increment, sel => sel,
score => score, score_part => score_part);
exact_matches <= score when score_part = '1';
color_matches <= score when score_part = '0';
encoder : g05_score_encoder
port map (num_exact_matches => exact_matches, num_color_matches => color_matches,
score_code => encoded_score);
controller : g05_mastermind_controller
port map (SC_CMP => SC_CMP, TC_LAST => TC_LAST, START => start, READY => ready,
MODE => mode, CLK => clk, SR_SEL => SR_SEL, P_SEL => P_SEL, GR_SEL => GR_SEL,
GR_LD => GR_LD, SR_LD => SR_LD, TM_IN => TM_IN, TM_EN => TM_EN, TC_EN => TC_EN,
TC_RST => TC_RST, SOLVED => SOLVED, TM_OUT => TM_OUT, START_MODE => START_MODE, DEFAULT_SCORE => DEFAULT_SCORE);
datapath : g05_mastermind_datapath
port map (P_SEL => P_SEL, GR_SEL => GR_SEL, SR_SEL => SR_SEL, GR_LD => GR_LD, SR_LD => SR_LD,
TM_IN => TM_IN, TM_OUT => TM_OUT, TM_EN => TM_EN, TC_RST => TC_RST, TC_EN => TC_EN, EXT_PATTERN => ext_pattern,
EXT_SCORE => encoded_score, MODE => mode, CLK => clk, TC_LAST => TC_LAST, SC_CMP => SC_CMP,
DIS_P1 => DIS_P1, DIS_P2 => DIS_P2, DIS_P3 => DIS_P3, DIS_P4 => DIS_P4, DIS_P5 => tmp_P5, DIS_P6 => tmp_P6, START_MODE => START_MODE);
process(clk, START_MODE)
begin
if START_MODE = '0' then
if rising_edge(clk) then
if DEFAULT_SCORE = '0' then
if MODE = '1' then
DIS_P5 <= tmp_P5;
DIS_P6 <= tmp_P6;
else
DIS_P5 <= '0' & color_matches;
DIS_P6 <= '0' & exact_matches;
end if;
else
DIS_P5 <= "0000";
DIS_P6 <= "0000";
end if;
end if;
else
DIS_P5 <= "0101"; -- S
DIS_P6 <= "0000"; --
end if;
end process;
segment1 : g05_7_segment_decoder
port map (code => DIS_P1, RippleBlank_In => '0', segments => seg_1);
segment2 : g05_7_segment_decoder
port map (code => DIS_P2, RippleBlank_In => '0', segments => seg_2);
segment3 : g05_7_segment_decoder
port map (code => DIS_P3, RippleBlank_In => '0', segments => seg_3);
segment4 : g05_7_segment_decoder
port map (code => DIS_P4, RippleBlank_In => '0', segments => seg_4);
segment5 : g05_7_segment_decoder
port map (code => DIS_P5, RippleBlank_In => '0', segments => seg_5);
segment6 : g05_7_segment_decoder
port map (code => DIS_P6, RippleBlank_In => '0', segments => seg_6);
end behavior; |
entity tb_record_test is
end tb_record_test;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_record_test is
signal clk : std_logic;
signal sl_in : std_logic;
signal slv_in : std_logic_vector(7 downto 0);
signal int_in : integer range 0 to 15;
signal usig_in : unsigned(7 downto 0);
signal sl_out : std_logic;
signal slv_out : std_logic_vector(7 downto 0);
signal int_out : integer range 0 to 15;
signal usig_out : unsigned(7 downto 0);
begin
dut: entity work.record_test
port map (
clk => clk,
sl_in => sl_in,
slv_in => slv_in,
int_in => int_in,
usig_in => usig_in,
sl_out => sl_out,
slv_out => slv_out,
int_out => int_out,
usig_out => usig_out);
process
begin
clk <= '0';
sl_in <= '1';
slv_in <= x"12";
int_in <= 13;
usig_in <= x"d5";
wait for 1 ns;
clk <= '1';
wait for 1 ns;
assert sl_out = '1' severity failure;
assert slv_out = x"12" severity failure;
assert int_out = 13 severity failure;
assert usig_out = x"d5" severity failure;
sl_in <= '0';
slv_in <= x"9b";
int_in <= 3;
usig_in <= x"72";
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
assert sl_out = '0' severity failure;
assert slv_out = x"9b" severity failure;
assert int_out = 3 severity failure;
assert usig_out = x"72" severity failure;
wait;
end process;
end behav;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DMA_Calculate is
port (
-- Downstream Registers from MWr Channel
DMA_PA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- EP (local)
DMA_HA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- Host (remote)
DMA_BDA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Length : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Control : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, for better timing
HA_is_64b : IN std_logic;
BDA_is_64b : IN std_logic;
-- Calculation in advance, for better timing
Leng_Hi19b_True : IN std_logic;
Leng_Lo7b_True : IN std_logic;
-- Parameters fed to DMA_FSM
DMA_PA_Loaded : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_PA_Var : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_HA_Var : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BDA_fsm : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
BDA_is_64b_fsm : OUT std_logic;
DMA_Snout_Length : OUT std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Body_Length : OUT std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Tail_Length : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- Only for downstream channel
DMA_PA_Snout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BAR_Number : OUT std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
-- Engine control signals
DMA_Start : IN std_logic;
DMA_Start2 : IN std_logic; -- out of consecutive dex
-- Control signals to FSM
No_More_Bodies : OUT std_logic; -- No more block(s) of Max_Size
ThereIs_Snout : OUT std_logic; -- 1st packet before Body blocks
ThereIs_Body : OUT std_logic; -- Block(s) of Max_Size
ThereIs_Tail : OUT std_logic; -- Last packet with size less than Max_Size
ThereIs_Dex : OUT std_logic; -- Not the last descriptor
HA64bit : OUT std_logic; -- Host Address is 64-bit
Addr_Inc : OUT std_logic; -- Peripheral Address increase token
-- FSM indicators
State_Is_LoadParam : IN std_logic;
State_Is_Snout : IN std_logic;
State_Is_Body : IN std_logic;
-- State_Is_Tail : IN std_logic;
-- Additional
Param_Max_Cfg : IN std_logic_vector(2 downto 0);
-- Common ports
dma_clk : IN std_logic;
dma_reset : IN std_logic
);
end entity DMA_Calculate;
architecture Behavioral of DMA_Calculate is
-- Significant bits from the MaXSiZe parameter
signal Max_TLP_Size : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal mxsz_left : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal mxsz_mid : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal mxsz_right : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
-- Signals masked by MaxSize
signal DMA_Leng_Left_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal DMA_Leng_Mid_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal DMA_Leng_Right_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
-- Alias
signal Lo_Leng_Left_Msk_is_True : std_logic;
signal Lo_Leng_Mid_Msk_is_True : std_logic;
signal Lo_Leng_Right_Msk_is_True : std_logic;
-- Masked values of HA and Length
signal DMA_HA_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal DMA_Length_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
-- Indicates whether the DMA_PA is already accepted
signal PA_is_taken : std_logic;
-- Calculation for the PA of the next DMA, if UPA bit = 0
signal DMA_PA_next : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_PA_current : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- eventual PA parameter for the current DMA transaction
signal DMA_PA_Loaded_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, only for better timing
signal Carry_PA_plus_Leng : std_logic_vector(CBIT_CARRY downto 0);
signal Carry_PAx_plus_Leng : std_logic_vector(CBIT_CARRY downto 0);
signal Leng_Hi_plus_PA_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto CBIT_CARRY);
signal Leng_Hi_plus_PAx_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto CBIT_CARRY);
-- DMA parameters from the register module
signal DMA_PA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_HA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_BDA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_Length_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- delay
signal State_Is_Snout_r1 : std_logic;
signal State_Is_Body_r1 : std_logic;
-- from control word
signal Dex_is_Last : std_logic;
signal Engine_Ends : std_logic;
-- Major FSM control signals
signal ThereIs_Snout_i : std_logic;
signal ThereIs_Body_i : std_logic;
signal ThereIs_Tail_i : std_logic;
signal Snout_Only : std_logic;
signal ThereIs_Dex_i : std_logic;
signal No_More_Bodies_i : std_logic;
-- Address/Length combination
signal ALc : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
-- Compressed ALc
-- ALc_B bit means the ALc has carry in, making an extra Body block.
signal ALc_B : std_logic;
signal ALc_B_wire : std_logic;
-- ALc_T bit means the ALc has trailer, making a final Tail block.
signal ALc_T : std_logic;
signal ALc_T_wire : std_logic;
-- Compressed Length
-- Leng_Two bit means Length >= 2 Max_Size.
signal Leng_Two : std_logic;
-- Leng_One bit means Length >= 1 Max_Size.
signal Leng_One : std_logic;
-- Leng_nint bit means Length is not integral of Max_Sizes.
signal Leng_nint : std_logic;
signal Length_analysis : std_logic_vector(2 downto 0);
signal Snout_Body_Tail : std_logic_vector(2 downto 0);
-- Byte counter
signal DMA_Byte_Counter : std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- !!! Elastic
signal Length_minus : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_BC_Carry : std_logic_vector(CBIT_CARRY downto 0);
-- Remote & Local Address variable
signal DMA_HA_Var_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_HA_Carry32 : std_logic_vector(C_DBUS_WIDTH/2 downto 0);
signal DMA_PA_Var_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- BDA parameter is buffered for FSM module
signal DMA_BDA_fsm_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal BDA_is_64b_fsm_i : std_logic;
-- Token bits out of Control word
signal HA64bit_i : std_logic;
signal Addr_Inc_i : std_logic;
signal use_PA : std_logic;
-- for better timing
signal HA_gap : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
--
signal DMA_Snout_Length_i : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal DMA_Tail_Length_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- for better timing
signal raw_Tail_Length : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
signal DMA_PA_Snout_Carry : std_logic_vector(CBIT_CARRY downto 0);
signal DMA_PA_Body_Carry : std_logic_vector(CBIT_CARRY downto 0);
signal DMA_BAR_Number_i : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
begin
-- Partition indicators
No_More_Bodies <= No_More_Bodies_i ;
ThereIs_Snout <= ThereIs_Snout_i ;
ThereIs_Body <= ThereIs_Body_i ;
ThereIs_Tail <= ThereIs_Tail_i ;
ThereIs_Dex <= ThereIs_Dex_i ;
HA64bit <= HA64bit_i ;
Addr_Inc <= Addr_Inc_i ;
--
DMA_PA_Loaded <= DMA_PA_Loaded_i ;
DMA_PA_Var <= DMA_PA_Var_i ;
DMA_HA_Var <= DMA_HA_Var_i ;
DMA_BDA_fsm <= DMA_BDA_fsm_i ;
BDA_is_64b_fsm <= BDA_is_64b_fsm_i;
-- Only for downstream channel
DMA_PA_Snout <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0);
DMA_BAR_Number <= DMA_BAR_Number_i;
-- different lengths
DMA_Snout_Length <= DMA_Snout_Length_i ;
DMA_Body_Length <= Max_TLP_Size ;
DMA_Tail_Length <= DMA_Tail_Length_i ;
-- Register stubs
DMA_PA_i <= DMA_PA;
DMA_HA_i <= DMA_HA;
DMA_BDA_i <= DMA_BDA;
DMA_Length_i <= DMA_Length;
DMA_Control_i <= DMA_Control;
-- ---------------------------------------------------------------
-- Parameters should be captured by the start/start2 and be kept
-- in case Pause command comes.
--
Syn_Param_Capture:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
Addr_Inc_i <= '0';
use_PA <= '0';
Dex_is_Last <= '0';
Engine_Ends <= '1';
DMA_BAR_Number_i <= (OTHERS=>'0');
DMA_BDA_fsm_i <= (OTHERS=>'0');
BDA_is_64b_fsm_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if DMA_Start ='1' or DMA_Start2 ='1' then
Addr_Inc_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_AINC);
use_PA <= DMA_Control_i(CINT_BIT_DMA_CTRL_UPA);
Dex_is_Last <= DMA_Control_i(CINT_BIT_DMA_CTRL_LAST);
Engine_Ends <= DMA_Control_i(CINT_BIT_DMA_CTRL_END);
DMA_BAR_Number_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_BAR_TOP downto CINT_BIT_DMA_CTRL_BAR_BOT);
DMA_BDA_fsm_i <= DMA_BDA_i ;
BDA_is_64b_fsm_i <= BDA_is_64b ;
else
Addr_Inc_i <= Addr_Inc_i ;
use_PA <= use_PA ;
Dex_is_Last <= Dex_is_Last ;
Engine_Ends <= Engine_Ends ;
DMA_BAR_Number_i <= DMA_BAR_Number_i;
DMA_BDA_fsm_i <= DMA_BDA_fsm_i ;
BDA_is_64b_fsm_i <= BDA_is_64b_fsm_i ;
end if;
end if;
end process;
-- Addr_Inc_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_AINC);
-- use_PA <= DMA_Control_i(CINT_BIT_DMA_CTRL_UPA);
-- Dex_is_Last <= DMA_Control_i(CINT_BIT_DMA_CTRL_LAST);
-- Engine_Ends <= DMA_Control_i(CINT_BIT_DMA_CTRL_END);
-- use_Irpt_Done <= not DMA_Control_i(CINT_BIT_DMA_CTRL_EDI);
-- Means there is consecutive descriptor(s)
ThereIs_Dex_i <= not Dex_is_Last and not Engine_Ends;
-- ---------------------------------------------------------------
-- PA_i selection
--
Syn_Calc_DMA_PA:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_current <= (Others=>'0');
-- DMA_BAR_Number_i <= (Others=>'0');
PA_is_taken <= '0';
elsif dma_clk'event and dma_clk = '1' then
if DMA_Start = '1' and PA_is_taken='0' then
DMA_PA_current <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00";
PA_is_taken <= '1';
elsif DMA_Start2 = '1' and PA_is_taken='0' and DMA_Control_i(CINT_BIT_DMA_CTRL_UPA) = '1' then
DMA_PA_current <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00";
PA_is_taken <= '1';
elsif DMA_Start2 = '1' and PA_is_taken='0' and DMA_Control_i(CINT_BIT_DMA_CTRL_UPA) = '0' then
DMA_PA_current(C_DBUS_WIDTH-1 downto 0) <= DMA_PA_next;
PA_is_taken <= '1';
else
DMA_PA_current <= DMA_PA_current;
if DMA_Start='0' and DMA_Start2='0' then
PA_is_taken <= '0';
else
PA_is_taken <= PA_is_taken;
end if;
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- PA_next Calculation
--
Syn_Calc_DMA_PA_next:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_next <= (Others=>'0');
elsif dma_clk'event and dma_clk = '1' then
if DMA_Start = '1' and PA_is_taken='0' then
if DMA_Control_i(CINT_BIT_DMA_CTRL_AINC) = '1' then
DMA_PA_next(CBIT_CARRY-1 downto 0) <= Carry_PA_plus_Leng(CBIT_CARRY-1 downto 0);
DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= Leng_Hi_plus_PA_Hi
+ Carry_PA_plus_Leng(CBIT_CARRY);
else
DMA_PA_next <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00";
end if;
elsif DMA_Start2 = '1' and PA_is_taken='0' then
if DMA_Control_i(CINT_BIT_DMA_CTRL_AINC) = '1' then
DMA_PA_next(CBIT_CARRY-1 downto 0) <= Carry_PAx_plus_Leng(CBIT_CARRY-1 downto 0);
DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= Leng_Hi_plus_PAx_Hi
+ Carry_PAx_plus_Leng(CBIT_CARRY);
else
DMA_PA_next <= DMA_PA_next;
end if;
else
DMA_PA_next <= DMA_PA_next;
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- Carry_PA_plus_Leng(16 downto 0)
--
Syn_Calc_Carry_PA_plus_Leng:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
Carry_PA_plus_Leng <= (Others=>'0');
elsif dma_clk'event and dma_clk = '1' then
Carry_PA_plus_Leng <= ('0'& DMA_PA_i(CBIT_CARRY-1 downto 2) &"00")
+ ('0'& DMA_Length_i(CBIT_CARRY-1 downto 2) &"00");
end if;
end process;
-- ---------------------------------------------------------------
-- Carry_PAx_plus_Leng(16 downto 0)
--
Syn_Calc_Carry_PAx_plus_Leng:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
Carry_PAx_plus_Leng <= (Others=>'0');
elsif dma_clk'event and dma_clk = '1' then
Carry_PAx_plus_Leng <= ('0'& DMA_PA_next (CBIT_CARRY-1 downto 2) &"00")
+ ('0'& DMA_Length_i(CBIT_CARRY-1 downto 2) &"00");
end if;
end process;
-- ---------------------------------------------------------------
-- Leng_Hi_plus_PA_Hi(31 downto 16)
--
Syn_Calc_Leng_Hi_plus_PA_Hi:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
Leng_Hi_plus_PA_Hi <= (Others=>'0');
elsif dma_clk'event and dma_clk = '1' then
Leng_Hi_plus_PA_Hi <= DMA_Length_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_i(C_DBUS_WIDTH-1 downto CBIT_CARRY);
end if;
end process;
-- ---------------------------------------------------------------
-- Leng_Hi_plus_PAx_Hi(31 downto 16)
--
Syn_Calc_Leng_Hi_plus_PAx_Hi:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
Leng_Hi_plus_PAx_Hi <= (Others=>'0');
elsif dma_clk'event and dma_clk = '1' then
Leng_Hi_plus_PAx_Hi <= DMA_Length_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY);
end if;
end process;
-- -----------------------------------------------------------------------------------------------------------------------------------
DMA_Leng_Left_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_left;
DMA_Leng_Mid_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid;
DMA_Leng_Right_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right;
-- -----------------------------------------------------------------------------------------------------------------------------------
DMA_HA_Msk <= (DMA_HA_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right)
& DMA_HA_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
& "00";
DMA_Length_Msk <= (DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right)
& DMA_Length_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
& "00";
-- -----------------------------------------------------------------------------------------------------------------------------------
Lo_Leng_Left_Msk_is_True <= '0' when DMA_Leng_Left_Msk =C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1';
Lo_Leng_Mid_Msk_is_True <= '0' when DMA_Leng_Mid_Msk =C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1';
Lo_Leng_Right_Msk_is_True <= '0' when DMA_Leng_Right_Msk=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1';
-- ----------------------------------------------------------
-- Synchronous Register: Leng_Info(Compressed Length Information)
---
Syn_Calc_Parameter_Leng_Info:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
Leng_Two <= '0';
Leng_One <= '0';
Leng_nint <= '0';
elsif dma_clk'event and dma_clk = '1' then
Leng_Two <= Leng_Hi19b_True or Lo_Leng_Left_Msk_is_True;
Leng_One <= Lo_Leng_Mid_Msk_is_True;
Leng_nint <= Leng_Lo7b_True or Lo_Leng_Right_Msk_is_True;
end if;
end process;
-- -----------------------------------------------------------------------------------------------------------------------------------
ALc_B_wire <= '0' when (ALc(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid)=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
else '1';
ALc_T_wire <= '0' when (ALc(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right)=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
and ALc(C_MAXSIZE_FLD_BIT_BOT-1 downto 0)=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1 downto 0)
else '1';
-- -----------------------------------------------------------------------------------------------------------------------------------
-- -------------------------------------------------------
-- Synchronous Register: ALc (Address-Length combination)
---
Syn_Calc_Parameter_ALc:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
ALc <= (Others=>'0');
ALc_B <= '0';
ALc_T <= '0';
elsif dma_clk'event and dma_clk = '1' then
ALc <= DMA_Length_Msk + DMA_HA_Msk;
ALc_B <= ALc_B_wire;
ALc_T <= ALc_T_wire;
end if;
end process;
-- concatenation of the Length information
Length_analysis <= Leng_Two & Leng_One & Leng_nint;
-- -------------------------------------------
-- Analysis on the DMA division
-- truth-table expressions
--
Comb_S_B_T:
process (
Length_analysis
, ALc_B
, ALc_T
)
begin
case Length_analysis is
-- Zero-length DMA, nothing to send
when "000" =>
Snout_Body_Tail <= "000";
-- Length < Max_Size. Always Snout and never Body, Tail depends on ALc.
when "001" =>
Snout_Body_Tail <= '1' & '0' & (ALc_B and ALc_T);
-- Length = Max_Size. Division depends only on ALc-Tail.
when "010" =>
Snout_Body_Tail <= ALc_T & not ALc_T & ALc_T;
-- Length = (k+1) Max_Size, k>=1. Always Body. Snout and Tail depend on ALc-Tail.
-- Body = Leng_Two or not ALc_T
when "100" =>
Snout_Body_Tail <= ALc_T & '1' & ALc_T;
when "110" =>
Snout_Body_Tail <= ALc_T & '1' & ALc_T;
-- Length = (1+d) Max_Size, 0<d<1. Always Snout. Body and Tail copy ALc.
when "011" =>
Snout_Body_Tail <= '1' & ALc_B & ALc_T;
-- Length = (k+1+d) Max_Size, k>=1, 0<d<1. Always Snout and Body. Tail copies ALc-Tail.
-- Body = Leng_Two or ALc_B
when "101" =>
Snout_Body_Tail <= '1' & '1' & ALc_T;
when "111" =>
Snout_Body_Tail <= '1' & '1' & ALc_T;
-- dealt as zero-length DMA
when Others =>
Snout_Body_Tail <= "000";
end case;
end process;
-- -----------------------------------------------
-- Synchronous Register:
-- ThereIs_Snout
-- ThereIs_Body
-- ThereIs_Tail
--
Syn_Calc_Parameters_SBT:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
ThereIs_Snout_i <= '0';
ThereIs_Body_i <= '0';
ThereIs_Tail_i <= '0';
Snout_Only <= '0';
elsif dma_clk'event and dma_clk = '1' then
ThereIs_Snout_i <= Snout_Body_Tail(2);
ThereIs_Body_i <= Snout_Body_Tail(1);
ThereIs_Tail_i <= Snout_Body_Tail(0);
Snout_Only <= ALc_T and not Snout_Body_Tail(0);
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- HA_gap
--
Syn_Calc_HA_gap:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
HA_gap <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
HA_gap <= Max_TLP_Size - DMA_HA_Msk;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Snout_Carry
--
FSM_Calc_DMA_PA_Snout_Carry:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Snout_Carry <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
DMA_PA_Snout_Carry <= ('0'& DMA_PA_current(CBIT_CARRY-1 downto 0)) + HA_gap;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Body_Carry
--
FSM_Calc_DMA_PA_Body_Carry:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Body_Carry <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
DMA_PA_Body_Carry <= ('0'& DMA_PA_Var_i(CBIT_CARRY-1 downto 0)) + Max_TLP_Size;
end if;
end process;
-- ------------------------------------------------------------------
-- Synchronous Register: Length_minus
--
Sync_Calc_Length_minus:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
Length_minus <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
Length_minus <= DMA_Length_i - Max_TLP_Size;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_BC_Carry
--
FSM_Calc_DMA_BC_Carry:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_BC_Carry <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
DMA_BC_Carry <= ('0'& DMA_Byte_Counter(CBIT_CARRY-1 downto 0)) - Max_TLP_Size;
end if;
end process;
-- --------------------------------------------
-- Synchronous reg: DMA_Snout_Length
-- DMA_Tail_Length
--
FSM_Calc_DMA_Snout_Tail_Lengths:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_Snout_Length_i <= (OTHERS =>'0');
DMA_Tail_Length_i <= (OTHERS =>'0');
raw_Tail_Length <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
DMA_Tail_Length_i(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0) <= (raw_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto C_MAXSIZE_FLD_BIT_BOT)
and mxsz_right(C_TLP_FLD_WIDTH_OF_LENG+1 downto C_MAXSIZE_FLD_BIT_BOT)
) & raw_Tail_Length( C_MAXSIZE_FLD_BIT_BOT-1 downto 0);
if State_Is_LoadParam ='1' then
raw_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0) <= DMA_Length_Msk(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
+ DMA_HA_Msk(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
if Snout_Only='1' then
DMA_Snout_Length_i <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto 2) &"00";
else
DMA_Snout_Length_i <= Max_TLP_Size - DMA_HA_Msk;
end if;
else
DMA_Snout_Length_i <= DMA_Snout_Length_i;
raw_Tail_Length <= raw_Tail_Length;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous Delays:
-- State_Is_Snout_r1
-- State_Is_Body_r1
--
Syn_Delay_State_is_x:
process ( dma_clk )
begin
if dma_clk'event and dma_clk = '1' then
State_Is_Snout_r1 <= State_Is_Snout;
State_Is_Body_r1 <= State_Is_Body;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_HA_Carry32
--
FSM_Calc_DMA_HA_Carry32:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_HA_Carry32 <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
DMA_HA_Carry32 <= '0' & DMA_HA_i(C_DBUS_WIDTH/2-1 downto 2) & "00"; -- temp
elsif State_Is_Snout = '1' or State_Is_Body = '1' then
DMA_HA_Carry32(C_DBUS_WIDTH/2 downto C_MAXSIZE_FLD_BIT_BOT) <= ('0'& DMA_HA_Var_i(C_DBUS_WIDTH/2-1 downto C_MAXSIZE_FLD_BIT_TOP+1) &
(DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and not mxsz_right)
) + mxsz_mid;
else
DMA_HA_Carry32 <= DMA_HA_Carry32;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_HA_Var
--
FSM_Calc_DMA_HA_Var:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_HA_Var_i <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
DMA_HA_Var_i <= DMA_HA_i(C_DBUS_WIDTH-1 downto 2) & "00"; -- temp
elsif State_Is_Snout_r1 = '1' or State_Is_Body_r1 = '1' then
-- elsif State_Is_Snout = '1' or State_Is_Body = '1' then
DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) <= DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
+ DMA_HA_Carry32(C_DBUS_WIDTH/2);
DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_BOT) <= (DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1)
& (DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and not mxsz_right))
+ mxsz_mid;
DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 0) <= (Others => '0'); -- MaxSize aligned
else
DMA_HA_Var_i <= DMA_HA_Var_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- HA64bit
--
FSM_Calc_HA64bit:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
HA64bit_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
HA64bit_i <= HA_is_64b;
elsif DMA_HA_Carry32(C_DBUS_WIDTH/2) = '1' then
HA64bit_i <= '1';
else
HA64bit_i <= HA64bit_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Var
--
FSM_Calc_DMA_PA_Var:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Var_i <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
if Addr_Inc_i='1' and ThereIs_Snout_i='1' then
DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_current(CBIT_CARRY-1 downto 0)
+ HA_gap(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_current(C_DBUS_WIDTH-1 downto CBIT_CARRY);
else
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto 0) <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0);
end if;
elsif State_Is_Snout_r1 = '1' then
---- elsif State_Is_Snout = '1' then
if Addr_Inc_i= '1' then
DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_Var_i(CBIT_CARRY-1 downto 0);
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_Snout_Carry(CBIT_CARRY);
else
DMA_PA_Var_i <= DMA_PA_Var_i;
end if;
elsif State_Is_Body_r1 = '1' then
---- elsif State_Is_Body = '1' then
if Addr_Inc_i= '1' then
DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_Body_Carry(CBIT_CARRY-1 downto 0);
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_Body_Carry(CBIT_CARRY);
else
DMA_PA_Var_i <= DMA_PA_Var_i;
end if;
else
DMA_PA_Var_i <= DMA_PA_Var_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Loaded_i
--
FSM_Calc_DMA_PA_Loaded_i:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Loaded_i <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
DMA_PA_Loaded_i <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0);
else
DMA_PA_Loaded_i <= DMA_PA_Loaded_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg: DMA_Byte_Counter
---
FSM_Calc_DMA_Byte_Counter:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_Byte_Counter <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
if ALc_B='0' and ALc_T='1' then
DMA_Byte_Counter <= Length_minus;
else
DMA_Byte_Counter <= DMA_Length_i(C_DBUS_WIDTH-1 downto 2) & "00";
end if;
-- elsif State_Is_Body_r1 = '1' then
elsif State_Is_Body = '1' then
DMA_Byte_Counter(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_Byte_Counter(C_DBUS_WIDTH-1 downto CBIT_CARRY)
- DMA_BC_Carry(CBIT_CARRY);
DMA_Byte_Counter(CBIT_CARRY-1 downto C_MAXSIZE_FLD_BIT_BOT) <= DMA_BC_Carry(CBIT_CARRY-1 downto C_MAXSIZE_FLD_BIT_BOT);
else
DMA_Byte_Counter <= DMA_Byte_Counter;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg: No_More_Bodies
---
FSM_Calc_No_More_Bodies:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
No_More_Bodies_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
No_More_Bodies_i <= not ThereIs_Body_i;
-- elsif State_Is_Body_r1 = '1' then
elsif State_Is_Body = '1' then
if DMA_Byte_Counter(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1)=C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1)
and (DMA_Byte_Counter(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_left)=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
and (DMA_Byte_Counter(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid)/=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
then
No_More_Bodies_i <= '1';
else
No_More_Bodies_i <= '0';
end if;
else
No_More_Bodies_i <= No_More_Bodies_i;
end if;
end if;
end process;
-- ------------------------------------------
-- Configuration pamameters: Param_Max_Cfg
--
Syn_Config_Param_Max_Cfg:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then -- 0x0080 Bytes
mxsz_left <= "111110"; -- 6 bits
mxsz_mid <= "000001"; -- 6 bits
mxsz_right <= "000000"; -- 6 bits
elsif dma_clk'event and dma_clk = '1' then
case Param_Max_Cfg is
when "000" => -- 0x0080 Bytes
mxsz_left <= "111110";
mxsz_mid <= "000001";
mxsz_right <= "000000";
when "001" => -- 0x0100 Bytes
mxsz_left <= "111100";
mxsz_mid <= "000010";
mxsz_right <= "000001";
when "010" => -- 0x0200 Bytes
mxsz_left <= "111000";
mxsz_mid <= "000100";
mxsz_right <= "000011";
when "011" => -- 0x0400 Bytes
mxsz_left <= "110000";
mxsz_mid <= "001000";
mxsz_right <= "000111";
when "100" => -- 0x0800 Bytes
mxsz_left <= "100000";
mxsz_mid <= "010000";
mxsz_right <= "001111";
when "101" => -- 0x1000 Bytes
mxsz_left <= "000000";
mxsz_mid <= "100000";
mxsz_right <= "011111";
when Others => -- as 0x0080 Bytes
mxsz_left <= "111110";
mxsz_mid <= "000001";
mxsz_right <= "000000";
end case;
end if;
end process;
Max_TLP_Size <= mxsz_mid & CONV_STD_LOGIC_VECTOR(0, C_MAXSIZE_FLD_BIT_BOT);
end architecture Behavioral;
|
package pkg is
type enum_t is (alpha, beta);
alias alias_t is enum_t;
end package;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decod is
port (
--wejscie BCD.
bcd : in std_logic_vector(3 downto 0);
-- wyjscie dekodera 8 bit.
segment7 : out std_logic_vector(7 downto 0)
);
end decod;
architecture Behavioral of decod is
begin
process (bcd)
BEGIN
case bcd is
when "0000"=> segment7 <="00000011"; -- '0'
when "0001"=> segment7 <="10011111"; -- '1'
when "0010"=> segment7 <="00100101"; -- '2'
when "0011"=> segment7 <="00001101"; -- '3'
when "0100"=> segment7 <="10011001"; -- '4'
when "0101"=> segment7 <="01001001"; -- '5'
when "0110"=> segment7 <="01000001"; -- '6'
when "0111"=> segment7 <="00011111"; -- '7'
when "1000"=> segment7 <="00000001"; -- '8'
when "1001"=> segment7 <="00001001"; -- '9'
-- stany wyzsze od 9 wygaczaja segement
when others=> segment7 <="11111111";
end case;
end process;
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity AddrDecM1 is
port(
addr : in vl_logic_vector(31 downto 0);
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
addrDec : out vl_logic_vector(8 downto 0)
);
end AddrDecM1;
|
library verilog;
use verilog.vl_types.all;
entity AddrDecM1 is
port(
addr : in vl_logic_vector(31 downto 0);
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
addrDec : out vl_logic_vector(8 downto 0)
);
end AddrDecM1;
|
library verilog;
use verilog.vl_types.all;
entity AddrDecM1 is
port(
addr : in vl_logic_vector(31 downto 0);
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
addrDec : out vl_logic_vector(8 downto 0)
);
end AddrDecM1;
|
-----------------------------------------------------------------------------
-- Module for transfering data from the 25MHz phy-clock nibble domain to
-- 50MHz byte clock-domain. Also strips away preamble and SFD.
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.crc.all;
entity rxsync is
Generic (reset_en:std_logic:='1');
Port ( sysclk : in STD_LOGIC;
reset : in STD_LOGIC;
rx_clk : in STD_LOGIC;
rxd : in STD_LOGIC_VECTOR (3 downto 0);
rx_dv : in STD_LOGIC;
data : out STD_LOGIC_VECTOR (7 downto 0);
data_end : out std_logic;
data_err : out std_logic;
data_dv : out STD_LOGIC;
crc_ok: out std_logic;
debug:out std_logic_vector(7 downto 0)
);
end rxsync;
architecture Behavioral of rxsync is
signal rst:std_logic;
-- rx_clk clockdomain
-- inreg latches rxd on rising rx_clk
signal inreg:std_logic_vector(3 downto 0);
signal inbytereg:std_logic_vector(8 downto 0);
signal crcreg, nextcrc:std_logic_vector(31 downto 0);
signal crcnibble:std_logic_vector(3 downto 0);
signal eod, err, crc:std_logic:='0';
signal dv_ccd:std_logic:='0';
type state_t is (Idle, Preamble, SFD, data0, data1);
signal state:state_t:=Idle;
-- sysclk clockdomain
signal dv_sync:std_logic_vector(2 downto 0);
signal dv_edge:std_logic;
begin
rst <= reset_en and reset;
nextcrc <= Crc32_4(rxd, crcreg, '1') when state = Data0 or state = Data1
else (OTHERS => '1');
fsm:process(rx_clk) is
variable eod_v, err_v, crc_v:std_logic;
begin
if rising_edge(rx_clk) then
if rst = '1' then
state <= Idle;
err <= '0';
eod <= '0';
crc <= '0';
debug(3 downto 0) <= (OTHERS => '1');
else
if err = '1' and eod = '0' then
eod_v := '1';
err_v := '1';
else
eod_v := '0';
err_v := '0';
end if;
crc_v := '0';
case state is
when Preamble =>
debug(0) <= '0';
if rx_dv = '1' then
if rxd = x"5" then
state <= SFD;
end if;
else
state <= Idle;
end if;
when SFD =>
debug(1) <= '0';
if rx_dv = '1' then
if rxd = x"d" then
state <= data0;
elsif rxd /= x"5" then
state <= Preamble;
end if;
else
state <= Idle;
end if;
when data0 =>
debug(2) <= '0';
if rx_dv = '1' then
state <= data1;
else
eod_v := '1';
if crcreg = x"12345678" then
crc_v := '1';
end if;
state <= Idle;
end if;
when data1 =>
debug(3) <= '0';
if rx_dv = '1' then
state <= data0;
else
err_v := '1';
state <= Idle;
end if;
when others => --Idle
if rx_dv = '1' then
if rxd = x"5" then
state <= SFD;
else
state <= Preamble;
end if;
end if;
end case;
err <= err_v;
eod <= eod_v;
crc <= crc_v;
end if;
end if;
end process;
process(rx_clk) is
begin
if rising_edge(rx_clk) then
if rst = '1' then
inreg <= (OTHERS => '0');
inbytereg <= (OTHERS => '0');
dv_ccd <= '0';
crcreg <= (OTHERS => '1');
else
crcreg <= nextcrc;
inreg <= rxd;
if eod = '1' then
inbytereg <= "1000000" & crc & err;
dv_ccd <= not dv_ccd;
elsif state = data1 then
inbytereg <= '0' & rxd & inreg;
dv_ccd <= not dv_ccd;
end if;
end if;
end if;
end process;
process(sysclk) is
variable data_dv_v, data_err_v, data_end_v, crc_ok_v:std_logic;
begin
if rising_edge(sysclk) then
if rst = '1' then
dv_sync <= (OTHERS => '0');
data_dv <= '0';
data_end <= '0';
data_err <= '0';
data <= (OTHERS => '0');
debug(7 downto 4) <= (OTHERS => '1');
else
dv_sync(0) <= dv_ccd;
dv_sync(1) <= dv_sync(0);
dv_sync(2) <= dv_sync(1);
data_dv_v := '0';
data_err_v := '0';
data_end_v := '0';
crc_ok_v := '0';
if dv_edge = '1' then
if inbytereg(8) = '0' then
data <= inbytereg(7 downto 0);
data_dv_v := '1';
debug(4) <= '0';
else
data_err_v := inbytereg(0);
crc_ok_v := inbytereg(1);
data_end_v := '1';
debug(5) <= '0';
end if;
end if;
data_dv <= data_dv_v;
data_err <= data_err_v;
crc_ok <= crc_ok_v;
data_end <= data_end_v;
end if;
end if;
end process;
dv_edge <= dv_sync(1) xor dv_sync(2);
end Behavioral;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll2.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll2 IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll2;
ARCHITECTURE SYN OF pll2 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
locked <= sub_wire0;
sub_wire2 <= sub_wire1(0);
c0 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 50000000,
clk0_duty_cycle => 50,
clk0_multiply_by => 33333333,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=pll2",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
areset => areset,
inclk => sub_wire4,
locked => sub_wire0,
clk => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "33.333332"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "33.33333300"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll32.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50000000"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "33333333"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity CalculateG is
generic
(
width : integer := 8
);
port
(
Difference0 : in std_logic_vector( 18 downto 0 );
Difference01 : in std_logic_vector( 18 downto 0 );
IHorizontal : in std_logic_vector( width downto 0 );
IVertical : in std_logic_vector( width downto 0 );
Difference7 : in std_logic_vector( width downto 0 );
DifferenceDver : in std_logic_vector( width + 2 downto 0 );
DifferenceDhor : in std_logic_vector( width + 2 downto 0 );
ElementG : out std_logic_vector( width downto 0 )
);
end CalculateG;
architecture Behavioral of CalculateG is
--signal PosThreshold : std_logic_vector( 10 downto 0 ) := "01111111111"; -- 1023
signal PosThreshold : std_logic_vector( 18 downto 0 ) := "0000000001111111111"; -- 1023
begin
process( Difference0, Difference01, IHorizontal, IVertical, Difference7, DifferenceDver, DifferenceDhor )
begin
if( Difference0( 18 ) /= '1' ) and ( Difference0>= PosThreshold ) then
ElementG <= IHorizontal;
elsif( Difference01( 18 ) /= '1' ) and ( Difference01 >= PosThreshold ) then
ElementG <= IVertical;
elsif DifferenceDhor < DifferenceDver then
ElementG <= IHorizontal;
elsif DifferenceDhor > DifferenceDver then
ElementG <= IVertical;
else
ElementG <= Difference7;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_host is
port (
clock : in std_logic;
reset : in std_logic;
-- Descriptor RAM interface
descr_addr : out std_logic_vector(8 downto 0);
descr_rdata : in std_logic_vector(31 downto 0);
descr_wdata : out std_logic_vector(31 downto 0);
descr_en : out std_logic;
descr_we : out std_logic;
-- Buffer RAM interface
buf_addr : out std_logic_vector(10 downto 0);
buf_rdata : in std_logic_vector(7 downto 0);
buf_wdata : out std_logic_vector(7 downto 0);
buf_en : out std_logic;
buf_we : out std_logic;
-- Transmit Path Interface
tx_busy : in std_logic;
tx_ack : in std_logic;
-- Interface to send tokens and handshakes
send_token : out std_logic;
send_handsh : out std_logic;
tx_pid : out std_logic_vector(3 downto 0);
tx_token : out std_logic_vector(10 downto 0);
-- Interface to send data packets
send_data : out std_logic;
no_data : out std_logic;
user_data : out std_logic_vector(7 downto 0);
user_last : out std_logic;
user_valid : out std_logic;
user_next : in std_logic;
-- Interface to bus initialization unit
reset_done : in std_logic;
sof_enable : in std_logic;
scan_enable : in std_logic := '1';
speed : in std_logic_vector(1 downto 0);
abort : in std_logic;
-- Receive Path Interface
rx_pid : in std_logic_vector(3 downto 0);
rx_token : in std_logic_vector(10 downto 0);
valid_token : in std_logic;
valid_handsh : in std_logic;
valid_packet : in std_logic;
data_valid : in std_logic;
data_start : in std_logic;
data_out : in std_logic_vector(7 downto 0);
rx_error : in std_logic );
end ulpi_host;
architecture functional of ulpi_host is
signal frame_div : integer range 0 to 65535;
signal frame_cnt : unsigned(13 downto 0) := (others => '0');
signal do_sof : std_logic;
constant c_max_transaction : integer := 31;
constant c_max_pipe : integer := 31;
constant c_timeout_val : integer := 7167;
constant c_transaction_offset : unsigned(8 downto 6) := "001";
signal transaction_pntr : integer range 0 to c_max_transaction;
signal descr_addr_i : unsigned(8 downto 0); -- could be temporarily pipe addr
type t_state is (startup, idle, wait4start, scan_transactions, get_pipe,
handle_trans, setup_token, bulk_token, send_data_packet, get_status,
wait_for_ack, receive_data, send_ack, update_pipe, update_trans, do_ping );
signal state : t_state;
signal substate : integer range 0 to 7;
signal trans_in : t_transaction;
signal pipe_in : t_pipe;
signal trans_cnt : unsigned(10 downto 0);
signal trans_len : unsigned(10 downto 0);
signal buf_addr_i : unsigned(10 downto 0);
-- signal speed : std_logic_vector(1 downto 0) := "11";
signal no_data_i : boolean;
signal abort_reg : std_logic;
signal tx_put : std_logic;
signal tx_last : std_logic;
signal need_ping : std_logic;
signal fifo_data_in : std_logic_vector(7 downto 0);
signal tx_almost_full : std_logic;
signal link_busy : std_logic;
signal timeout : boolean;
signal timeout_cnt : integer range 0 to c_timeout_val;
signal first_transfer : boolean;
signal terminate : std_logic;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "sequential";
-- attribute keep : string;
-- attribute keep of timeout : signal is "true";
signal debug_count : integer range 0 to 1023 := 0;
signal debug_error : std_logic := '0';
begin
descr_addr <= std_logic_vector(descr_addr_i);
buf_addr <= std_logic_vector(buf_addr_i);
no_data <= '1' when no_data_i else '0';
buf_wdata <= data_out; -- should be rx_data
buf_we <= '1' when (state = receive_data) and (data_valid = '1') else '0';
p_protocol: process(clock)
procedure next_transaction is
begin
if terminate='1' then
terminate <= '0';
state <= idle;
elsif transaction_pntr = c_max_transaction then
transaction_pntr <= 0;
state <= idle; -- wait for next sof before rescan
else
transaction_pntr <= transaction_pntr + 1;
substate <= 0;
state <= scan_transactions;
end if;
end procedure;
function min(a, b: unsigned) return unsigned is
begin
if a < b then
return a;
else
return b;
end if;
end function;
variable trans_temp : t_transaction;
variable len : unsigned(trans_temp.transfer_length'range);
begin
if rising_edge(clock) then
descr_en <= '0';
descr_we <= '0';
tx_put <= '0';
if abort='1' then
abort_reg <= '1';
end if;
-- default counter
if substate /= 3 then
substate <= substate + 1;
end if;
if timeout_cnt /= 0 then
timeout_cnt <= timeout_cnt - 1;
if timeout_cnt = 1 then
timeout <= false;--true;
end if;
end if;
case state is
when startup =>
tx_pid <= c_pid_reserved;
do_sof <= '0';
frame_div <= 7499;
if reset_done='1' then
state <= idle;
if speed = "10" then
need_ping <= '1';
end if;
end if;
when idle =>
abort_reg <= '0';
if do_sof='1' then
do_sof <= '0';
tx_token <= std_logic_vector(frame_cnt(13 downto 3));
tx_pid <= c_pid_sof;
if speed = "00" then
send_handsh <= '1';
else
send_token <= '1';
end if;
if speed(1)='1' then
frame_cnt <= frame_cnt + 1;
else
frame_cnt <= frame_cnt + 8;
end if;
state <= wait4start;
end if;
when wait4start =>
if tx_ack='1' then
send_token <= '0';
send_handsh <= '0';
send_data <= '0'; -- redundant - will not come here
substate <= 0;
if scan_enable='1' then
state <= scan_transactions;
else
state <= idle;
end if;
end if;
when scan_transactions =>
case substate is
when 0 =>
descr_addr_i <= c_transaction_offset & to_unsigned(transaction_pntr,
descr_addr_i'length-c_transaction_offset'length);
descr_en <= '1';
when 2 =>
trans_temp := data_to_t_transaction(descr_rdata);
trans_in <= trans_temp;
substate <= 0;
if trans_temp.state = busy then
state <= get_pipe;
else -- go for next, unless we are at the end of the list
next_transaction;
end if;
when others =>
null;
end case;
when get_pipe =>
case substate is
when 0 =>
descr_addr_i <= (others => '0');
descr_addr_i(trans_in.pipe_pointer'range) <= trans_in.pipe_pointer;
descr_en <= '1';
when 2 =>
pipe_in <= data_to_t_pipe(descr_rdata);
first_transfer <= true;
state <= handle_trans; ---
when others =>
null;
end case;
when handle_trans => -- both pipe and transaction records are now valid
abort_reg <= '0';
substate <= 0;
if do_sof='1' and link_busy='0' then
state <= idle;
elsif pipe_in.state /= initialized then -- can we use the pipe?
trans_in.state <= error;
state <= update_trans;
else -- yes we can
timeout <= false;
timeout_cnt <= c_timeout_val;
link_busy <= trans_in.link_to_next;
case trans_in.transaction_type is
when control =>
-- a control out sequence exists of a setup token
-- and then a data0 packet, which should be followed by
-- an ack from the device. The next phase of the transaction
-- could be either in or out, and defines whether it is a
-- control read or a control write.
-- By choice, control transfers are implemented using
-- two transactions, which are executed in guaranteed
-- sequence.
-- In this way, each stage has its own buffer.
-- Note, the first pipe should be of type OUT, although it is not
-- checked.
tx_pid <= c_pid_setup;
tx_token <= pipe_in.device_endpoint & pipe_in.device_address;
send_token <= '1';
state <= setup_token;
when bulk | interrupt =>
tx_token <= pipe_in.device_endpoint & pipe_in.device_address;
state <= bulk_token;
send_token <= '1';
timeout <= false;
timeout_cnt <= c_timeout_val;
if pipe_in.direction = dir_in then
tx_pid <= c_pid_in;
else
-- if need_ping='1' then
-- tx_pid <= c_pid_ping;
-- state <= do_ping;
-- else
tx_pid <= c_pid_out;
-- end if;
end if;
if pipe_in.control='1' and first_transfer then
pipe_in.data_toggle <= '1'; -- start with data 1
end if;
first_transfer <= false;
when others => -- not yet supported
trans_in.state <= error;
state <= update_trans;
end case;
end if;
when setup_token =>
if tx_ack='1' then
send_token <= '0';
tx_pid <= c_pid_data0; -- send setup data immediately
send_data <= '1';
buf_en <= '1';
substate <= 0;
state <= send_data_packet;
end if;
-- prepare buffer
buf_addr_i <= trans_in.buffer_address;
trans_len <= trans_in.transfer_length; -- not cut up
trans_cnt <= trans_in.transfer_length; -- not cut up
no_data_i <= (trans_in.transfer_length = 0);
when do_ping =>
if tx_ack='1' then
send_token <= '0';
end if;
-- wait for ack/nack or nyet.
if rx_error='1' then
trans_in.state <= error;
state <= update_trans;
elsif abort_reg='1' then
pipe_in.state <= aborted;
state <= update_pipe;
abort_reg <= '0';
elsif valid_handsh='1' then -- maybe an ack?
if rx_pid = c_pid_ack then
tx_pid <= c_pid_out;
send_token <= '1';
state <= bulk_token;
elsif rx_pid = c_pid_stall then
pipe_in.state <= stalled;
trans_in.state <= error;
state <= update_pipe;
elsif (rx_pid = c_pid_nak) or (rx_pid = c_pid_nyet) then
state <= handle_trans;
end if; -- all other pids are just ignored
elsif timeout then
state <= handle_trans;
end if;
when bulk_token =>
if tx_ack='1' then
send_token <= '0';
if pipe_in.direction = dir_out then
if pipe_in.data_toggle = '0' then
tx_pid <= c_pid_data0;
else
tx_pid <= c_pid_data1;
end if;
send_data <= '1';
buf_en <= '1';
substate <= 0;
state <= send_data_packet;
else -- input
timeout <= false;
timeout_cnt <= c_timeout_val;
state <= receive_data;
buf_en <= '1';
end if;
end if;
-- prepare buffer
buf_addr_i <= trans_in.buffer_address;
if pipe_in.direction = dir_out then
len := min(trans_in.transfer_length, pipe_in.max_transfer);
trans_len <= len; -- possibly cut up
trans_cnt <= len;
no_data_i <= (trans_in.transfer_length = 0);
else
trans_len <= (others => '0');
end if;
when send_data_packet =>
case substate is
when 0 =>
if tx_ack='1' then
send_data <= '0';
if no_data_i then
substate <= 2;
end if;
else
substate <= 0;
end if;
when 1 =>
substate <= 1; -- stay!
if tx_almost_full='0' then
tx_put <= '1';
buf_addr_i <= buf_addr_i + 1;
trans_cnt <= trans_cnt - 1;
if trans_cnt = 1 then
tx_last <= '1';
substate <= 2;
buf_en <= '0';
else
tx_last <= '0';
end if;
end if;
when 2 =>
if tx_busy='1' then
substate <= 2;
else
state <= wait_for_ack;
timeout <= false;
timeout_cnt <= c_timeout_val;
end if;
when others =>
null;
end case;
when wait_for_ack =>
if rx_error='1' then
trans_in.state <= error;
state <= update_trans;
elsif abort_reg='1' then
pipe_in.state <= aborted;
state <= update_pipe;
abort_reg <= '0';
elsif valid_handsh='1' then -- maybe an ack?
if (rx_pid = c_pid_ack) or (rx_pid = c_pid_nyet) then
if rx_pid = c_pid_nyet then
need_ping <= '1';
else
need_ping <= '0';
end if;
if trans_in.transfer_length = trans_len then
trans_in.state <= done;
if pipe_in.control='1' and trans_in.transaction_type = bulk then
state <= get_status;
substate <= 0;
else
state <= update_pipe;
end if;
else
trans_in.state <= busy;
state <= handle_trans;
end if;
trans_in.buffer_address <= buf_addr_i; -- store back
trans_in.transfer_length <= trans_in.transfer_length - trans_len;
pipe_in.data_toggle <= not pipe_in.data_toggle;
elsif rx_pid = c_pid_stall then
pipe_in.state <= stalled;
trans_in.state <= error;
state <= update_pipe;
elsif rx_pid = c_pid_nak then
terminate <= '0'; --link_busy; -- if control packet, then don't continue with next transaction!
state <= update_trans;
-- state <= handle_trans; -- just retry and retry, no matter what kind of packet it is, don't send SOF!
end if; -- all other pids are just ignored
-- elsif do_sof='1' then
-- state <= idle; -- test
elsif timeout then
pipe_in.timeout <= '1';
trans_in.state <= error;
state <= update_pipe;
-- state <= handle_trans; -- try again
end if;
when get_status =>
case substate is
when 0 =>
send_token <= '1';
tx_pid <= c_pid_in;
when 1 =>
if tx_ack='1' then
send_token <= '0';
timeout_cnt <= c_timeout_val;
timeout <= false;
else
substate <= 1; -- wait
end if;
when 2 =>
if valid_packet='1' or valid_handsh='1' then
state <= update_pipe; -- end transaction
elsif rx_error='1' or timeout then
trans_in.state <= error;
state <= update_pipe; -- end transaction
else
substate <= 2; -- wait
end if;
when others =>
null;
end case;
when receive_data =>
if data_valid = '1' then
timeout <= false;
timeout_cnt <= 0; -- does not occur anymore
buf_addr_i <= buf_addr_i + 1;
trans_len <= trans_len + 1;
end if;
--------------------------------------------------------------------
if rx_error = '1' or debug_error='1' then
-- go back to send the in token again
buf_en <= '0';
state <= handle_trans;
elsif abort_reg='1' then
pipe_in.state <= aborted;
state <= update_pipe;
abort_reg <= '0';
elsif valid_packet='1' then
buf_en <= '0';
trans_in.buffer_address <= buf_addr_i - 2; -- cut off CRC
trans_in.transfer_length <= trans_in.transfer_length - (trans_len - 2);
if ((trans_len - 2) >= trans_in.transfer_length) or
((trans_len - 2) < pipe_in.max_transfer) then
trans_in.state <= done;
else
trans_in.state <= busy;
end if;
state <= send_ack;
substate <= 0;
elsif valid_handsh='1' then
buf_en <= '0';
if rx_pid = c_pid_nak then
if pipe_in.control='1' then
state <= idle; -- retry on next sof, do not go to the next transaction
else
state <= update_trans; -- is not updated, but is the standard path to go to the next transact.
end if;
elsif rx_pid = c_pid_stall then
trans_in.state <= error;
pipe_in.state <= stalled;
state <= update_pipe;
end if;
elsif timeout then -- device doesn't answer, could it have missed my in token?
buf_en <= '0';
state <= handle_trans;
end if;
when send_ack =>
case substate is
when 0 =>
send_handsh <= '1';
tx_pid <= c_pid_ack;
when 1 =>
if tx_ack='0' then
substate <= 1; -- stay here.
else
send_handsh <= '0';
state <= update_trans;
-- if (pipe_in.control='0') and (trans_in.state = done) then
-- state <= update_trans;
-- elsif (pipe_in.control='1') and (trans_len = 2) then -- no data, thus status already received
-- state <= update_trans;
-- else
-- null;
-- -- substate <= 2;
-- end if;
end if;
-- when 2 => -- send status back (no data packet)
-- tx_pid <= c_pid_out;
-- tx_token <= pipe_in.device_endpoint & pipe_in.device_address;
-- send_token <= '1';
-- when 3 => -- wait until token was sent
-- if tx_ack='0' then
-- substate <= 3;
-- else
-- send_token <= '0';
-- no_data_i <= true;
-- send_data <= '1';
-- tx_pid <= c_pid_data1;
-- end if;
-- when 4 => -- wait until no data packet was processed
-- if tx_ack='0' then
-- substate <= 4;
-- else
-- send_data <= '0';
-- state <= update_trans;
-- end if;
when others =>
null;
end case;
when update_pipe =>
descr_addr_i <= (others => '0');
descr_addr_i(trans_in.pipe_pointer'range) <= trans_in.pipe_pointer;
descr_en <= '1';
descr_we <= '1';
descr_wdata <= t_pipe_to_data(pipe_in);
state <= update_trans;
when update_trans =>
descr_addr_i <= c_transaction_offset & to_unsigned(transaction_pntr,
descr_addr_i'length-c_transaction_offset'length);
descr_wdata <= t_transaction_to_data(trans_in);
descr_en <= '1';
descr_we <= '1';
next_transaction;
when others =>
null;
end case;
---------------------------------------------------
-- DEBUG
---------------------------------------------------
-- if state /= receive_data then
-- debug_count <= 0;
-- debug_error <= '0';
-- elsif debug_count = 1023 then
-- debug_error <= '1';
-- else
-- debug_count <= debug_count + 1;
-- end if;
---------------------------------------------------
if frame_div = 0 then
do_sof <= sof_enable;
if speed(1)='1' then
frame_div <= 7499; -- microframes
else
frame_div <= 59999; -- 1 ms frames
end if;
else
frame_div <= frame_div - 1;
end if;
if reset_done='0' then
state <= startup;
end if;
if speed /= "10" then -- If not high speed, then we force no ping
need_ping <= '0';
end if;
if reset = '1' then
abort_reg <= '0';
buf_en <= '0';
buf_addr_i <= (others => '0');
trans_len <= (others => '0');
trans_cnt <= (others => '0');
link_busy <= '0';
state <= startup;
do_sof <= '0';
frame_div <= 7499;
frame_cnt <= (others => '0');
send_token <= '0';
send_data <= '0';
send_handsh <= '0';
need_ping <= '0';
terminate <= '0';
end if;
end if;
end process;
-- Decoupling of ulpi tx bus and our generation of data
-- to meet timing of "next" signal
-- fifo_data_in <= reset_data when (state = startup) else buf_rdata;
fifo_data_in <= buf_rdata;
i_srl_tx: entity work.srl_fifo
generic map (
Width => 9,
Depth => 15,
Threshold => 10 )
port map (
clock => clock,
reset => reset,
GetElement => user_next,
PutElement => tx_put,
FlushFifo => '0',
DataIn(7 downto 0) => fifo_data_in,
DataIn(8) => tx_last,
DataOut(7 downto 0) => user_data,
DataOut(8) => user_last,
SpaceInFifo => open,
AlmostFull => tx_almost_full,
DataInFifo => user_valid );
end functional;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_host is
port (
clock : in std_logic;
reset : in std_logic;
-- Descriptor RAM interface
descr_addr : out std_logic_vector(8 downto 0);
descr_rdata : in std_logic_vector(31 downto 0);
descr_wdata : out std_logic_vector(31 downto 0);
descr_en : out std_logic;
descr_we : out std_logic;
-- Buffer RAM interface
buf_addr : out std_logic_vector(10 downto 0);
buf_rdata : in std_logic_vector(7 downto 0);
buf_wdata : out std_logic_vector(7 downto 0);
buf_en : out std_logic;
buf_we : out std_logic;
-- Transmit Path Interface
tx_busy : in std_logic;
tx_ack : in std_logic;
-- Interface to send tokens and handshakes
send_token : out std_logic;
send_handsh : out std_logic;
tx_pid : out std_logic_vector(3 downto 0);
tx_token : out std_logic_vector(10 downto 0);
-- Interface to send data packets
send_data : out std_logic;
no_data : out std_logic;
user_data : out std_logic_vector(7 downto 0);
user_last : out std_logic;
user_valid : out std_logic;
user_next : in std_logic;
-- Interface to bus initialization unit
reset_done : in std_logic;
sof_enable : in std_logic;
scan_enable : in std_logic := '1';
speed : in std_logic_vector(1 downto 0);
abort : in std_logic;
-- Receive Path Interface
rx_pid : in std_logic_vector(3 downto 0);
rx_token : in std_logic_vector(10 downto 0);
valid_token : in std_logic;
valid_handsh : in std_logic;
valid_packet : in std_logic;
data_valid : in std_logic;
data_start : in std_logic;
data_out : in std_logic_vector(7 downto 0);
rx_error : in std_logic );
end ulpi_host;
architecture functional of ulpi_host is
signal frame_div : integer range 0 to 65535;
signal frame_cnt : unsigned(13 downto 0) := (others => '0');
signal do_sof : std_logic;
constant c_max_transaction : integer := 31;
constant c_max_pipe : integer := 31;
constant c_timeout_val : integer := 7167;
constant c_transaction_offset : unsigned(8 downto 6) := "001";
signal transaction_pntr : integer range 0 to c_max_transaction;
signal descr_addr_i : unsigned(8 downto 0); -- could be temporarily pipe addr
type t_state is (startup, idle, wait4start, scan_transactions, get_pipe,
handle_trans, setup_token, bulk_token, send_data_packet, get_status,
wait_for_ack, receive_data, send_ack, update_pipe, update_trans, do_ping );
signal state : t_state;
signal substate : integer range 0 to 7;
signal trans_in : t_transaction;
signal pipe_in : t_pipe;
signal trans_cnt : unsigned(10 downto 0);
signal trans_len : unsigned(10 downto 0);
signal buf_addr_i : unsigned(10 downto 0);
-- signal speed : std_logic_vector(1 downto 0) := "11";
signal no_data_i : boolean;
signal abort_reg : std_logic;
signal tx_put : std_logic;
signal tx_last : std_logic;
signal need_ping : std_logic;
signal fifo_data_in : std_logic_vector(7 downto 0);
signal tx_almost_full : std_logic;
signal link_busy : std_logic;
signal timeout : boolean;
signal timeout_cnt : integer range 0 to c_timeout_val;
signal first_transfer : boolean;
signal terminate : std_logic;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "sequential";
-- attribute keep : string;
-- attribute keep of timeout : signal is "true";
signal debug_count : integer range 0 to 1023 := 0;
signal debug_error : std_logic := '0';
begin
descr_addr <= std_logic_vector(descr_addr_i);
buf_addr <= std_logic_vector(buf_addr_i);
no_data <= '1' when no_data_i else '0';
buf_wdata <= data_out; -- should be rx_data
buf_we <= '1' when (state = receive_data) and (data_valid = '1') else '0';
p_protocol: process(clock)
procedure next_transaction is
begin
if terminate='1' then
terminate <= '0';
state <= idle;
elsif transaction_pntr = c_max_transaction then
transaction_pntr <= 0;
state <= idle; -- wait for next sof before rescan
else
transaction_pntr <= transaction_pntr + 1;
substate <= 0;
state <= scan_transactions;
end if;
end procedure;
function min(a, b: unsigned) return unsigned is
begin
if a < b then
return a;
else
return b;
end if;
end function;
variable trans_temp : t_transaction;
variable len : unsigned(trans_temp.transfer_length'range);
begin
if rising_edge(clock) then
descr_en <= '0';
descr_we <= '0';
tx_put <= '0';
if abort='1' then
abort_reg <= '1';
end if;
-- default counter
if substate /= 3 then
substate <= substate + 1;
end if;
if timeout_cnt /= 0 then
timeout_cnt <= timeout_cnt - 1;
if timeout_cnt = 1 then
timeout <= false;--true;
end if;
end if;
case state is
when startup =>
tx_pid <= c_pid_reserved;
do_sof <= '0';
frame_div <= 7499;
if reset_done='1' then
state <= idle;
if speed = "10" then
need_ping <= '1';
end if;
end if;
when idle =>
abort_reg <= '0';
if do_sof='1' then
do_sof <= '0';
tx_token <= std_logic_vector(frame_cnt(13 downto 3));
tx_pid <= c_pid_sof;
if speed = "00" then
send_handsh <= '1';
else
send_token <= '1';
end if;
if speed(1)='1' then
frame_cnt <= frame_cnt + 1;
else
frame_cnt <= frame_cnt + 8;
end if;
state <= wait4start;
end if;
when wait4start =>
if tx_ack='1' then
send_token <= '0';
send_handsh <= '0';
send_data <= '0'; -- redundant - will not come here
substate <= 0;
if scan_enable='1' then
state <= scan_transactions;
else
state <= idle;
end if;
end if;
when scan_transactions =>
case substate is
when 0 =>
descr_addr_i <= c_transaction_offset & to_unsigned(transaction_pntr,
descr_addr_i'length-c_transaction_offset'length);
descr_en <= '1';
when 2 =>
trans_temp := data_to_t_transaction(descr_rdata);
trans_in <= trans_temp;
substate <= 0;
if trans_temp.state = busy then
state <= get_pipe;
else -- go for next, unless we are at the end of the list
next_transaction;
end if;
when others =>
null;
end case;
when get_pipe =>
case substate is
when 0 =>
descr_addr_i <= (others => '0');
descr_addr_i(trans_in.pipe_pointer'range) <= trans_in.pipe_pointer;
descr_en <= '1';
when 2 =>
pipe_in <= data_to_t_pipe(descr_rdata);
first_transfer <= true;
state <= handle_trans; ---
when others =>
null;
end case;
when handle_trans => -- both pipe and transaction records are now valid
abort_reg <= '0';
substate <= 0;
if do_sof='1' and link_busy='0' then
state <= idle;
elsif pipe_in.state /= initialized then -- can we use the pipe?
trans_in.state <= error;
state <= update_trans;
else -- yes we can
timeout <= false;
timeout_cnt <= c_timeout_val;
link_busy <= trans_in.link_to_next;
case trans_in.transaction_type is
when control =>
-- a control out sequence exists of a setup token
-- and then a data0 packet, which should be followed by
-- an ack from the device. The next phase of the transaction
-- could be either in or out, and defines whether it is a
-- control read or a control write.
-- By choice, control transfers are implemented using
-- two transactions, which are executed in guaranteed
-- sequence.
-- In this way, each stage has its own buffer.
-- Note, the first pipe should be of type OUT, although it is not
-- checked.
tx_pid <= c_pid_setup;
tx_token <= pipe_in.device_endpoint & pipe_in.device_address;
send_token <= '1';
state <= setup_token;
when bulk | interrupt =>
tx_token <= pipe_in.device_endpoint & pipe_in.device_address;
state <= bulk_token;
send_token <= '1';
timeout <= false;
timeout_cnt <= c_timeout_val;
if pipe_in.direction = dir_in then
tx_pid <= c_pid_in;
else
-- if need_ping='1' then
-- tx_pid <= c_pid_ping;
-- state <= do_ping;
-- else
tx_pid <= c_pid_out;
-- end if;
end if;
if pipe_in.control='1' and first_transfer then
pipe_in.data_toggle <= '1'; -- start with data 1
end if;
first_transfer <= false;
when others => -- not yet supported
trans_in.state <= error;
state <= update_trans;
end case;
end if;
when setup_token =>
if tx_ack='1' then
send_token <= '0';
tx_pid <= c_pid_data0; -- send setup data immediately
send_data <= '1';
buf_en <= '1';
substate <= 0;
state <= send_data_packet;
end if;
-- prepare buffer
buf_addr_i <= trans_in.buffer_address;
trans_len <= trans_in.transfer_length; -- not cut up
trans_cnt <= trans_in.transfer_length; -- not cut up
no_data_i <= (trans_in.transfer_length = 0);
when do_ping =>
if tx_ack='1' then
send_token <= '0';
end if;
-- wait for ack/nack or nyet.
if rx_error='1' then
trans_in.state <= error;
state <= update_trans;
elsif abort_reg='1' then
pipe_in.state <= aborted;
state <= update_pipe;
abort_reg <= '0';
elsif valid_handsh='1' then -- maybe an ack?
if rx_pid = c_pid_ack then
tx_pid <= c_pid_out;
send_token <= '1';
state <= bulk_token;
elsif rx_pid = c_pid_stall then
pipe_in.state <= stalled;
trans_in.state <= error;
state <= update_pipe;
elsif (rx_pid = c_pid_nak) or (rx_pid = c_pid_nyet) then
state <= handle_trans;
end if; -- all other pids are just ignored
elsif timeout then
state <= handle_trans;
end if;
when bulk_token =>
if tx_ack='1' then
send_token <= '0';
if pipe_in.direction = dir_out then
if pipe_in.data_toggle = '0' then
tx_pid <= c_pid_data0;
else
tx_pid <= c_pid_data1;
end if;
send_data <= '1';
buf_en <= '1';
substate <= 0;
state <= send_data_packet;
else -- input
timeout <= false;
timeout_cnt <= c_timeout_val;
state <= receive_data;
buf_en <= '1';
end if;
end if;
-- prepare buffer
buf_addr_i <= trans_in.buffer_address;
if pipe_in.direction = dir_out then
len := min(trans_in.transfer_length, pipe_in.max_transfer);
trans_len <= len; -- possibly cut up
trans_cnt <= len;
no_data_i <= (trans_in.transfer_length = 0);
else
trans_len <= (others => '0');
end if;
when send_data_packet =>
case substate is
when 0 =>
if tx_ack='1' then
send_data <= '0';
if no_data_i then
substate <= 2;
end if;
else
substate <= 0;
end if;
when 1 =>
substate <= 1; -- stay!
if tx_almost_full='0' then
tx_put <= '1';
buf_addr_i <= buf_addr_i + 1;
trans_cnt <= trans_cnt - 1;
if trans_cnt = 1 then
tx_last <= '1';
substate <= 2;
buf_en <= '0';
else
tx_last <= '0';
end if;
end if;
when 2 =>
if tx_busy='1' then
substate <= 2;
else
state <= wait_for_ack;
timeout <= false;
timeout_cnt <= c_timeout_val;
end if;
when others =>
null;
end case;
when wait_for_ack =>
if rx_error='1' then
trans_in.state <= error;
state <= update_trans;
elsif abort_reg='1' then
pipe_in.state <= aborted;
state <= update_pipe;
abort_reg <= '0';
elsif valid_handsh='1' then -- maybe an ack?
if (rx_pid = c_pid_ack) or (rx_pid = c_pid_nyet) then
if rx_pid = c_pid_nyet then
need_ping <= '1';
else
need_ping <= '0';
end if;
if trans_in.transfer_length = trans_len then
trans_in.state <= done;
if pipe_in.control='1' and trans_in.transaction_type = bulk then
state <= get_status;
substate <= 0;
else
state <= update_pipe;
end if;
else
trans_in.state <= busy;
state <= handle_trans;
end if;
trans_in.buffer_address <= buf_addr_i; -- store back
trans_in.transfer_length <= trans_in.transfer_length - trans_len;
pipe_in.data_toggle <= not pipe_in.data_toggle;
elsif rx_pid = c_pid_stall then
pipe_in.state <= stalled;
trans_in.state <= error;
state <= update_pipe;
elsif rx_pid = c_pid_nak then
terminate <= '0'; --link_busy; -- if control packet, then don't continue with next transaction!
state <= update_trans;
-- state <= handle_trans; -- just retry and retry, no matter what kind of packet it is, don't send SOF!
end if; -- all other pids are just ignored
-- elsif do_sof='1' then
-- state <= idle; -- test
elsif timeout then
pipe_in.timeout <= '1';
trans_in.state <= error;
state <= update_pipe;
-- state <= handle_trans; -- try again
end if;
when get_status =>
case substate is
when 0 =>
send_token <= '1';
tx_pid <= c_pid_in;
when 1 =>
if tx_ack='1' then
send_token <= '0';
timeout_cnt <= c_timeout_val;
timeout <= false;
else
substate <= 1; -- wait
end if;
when 2 =>
if valid_packet='1' or valid_handsh='1' then
state <= update_pipe; -- end transaction
elsif rx_error='1' or timeout then
trans_in.state <= error;
state <= update_pipe; -- end transaction
else
substate <= 2; -- wait
end if;
when others =>
null;
end case;
when receive_data =>
if data_valid = '1' then
timeout <= false;
timeout_cnt <= 0; -- does not occur anymore
buf_addr_i <= buf_addr_i + 1;
trans_len <= trans_len + 1;
end if;
--------------------------------------------------------------------
if rx_error = '1' or debug_error='1' then
-- go back to send the in token again
buf_en <= '0';
state <= handle_trans;
elsif abort_reg='1' then
pipe_in.state <= aborted;
state <= update_pipe;
abort_reg <= '0';
elsif valid_packet='1' then
buf_en <= '0';
trans_in.buffer_address <= buf_addr_i - 2; -- cut off CRC
trans_in.transfer_length <= trans_in.transfer_length - (trans_len - 2);
if ((trans_len - 2) >= trans_in.transfer_length) or
((trans_len - 2) < pipe_in.max_transfer) then
trans_in.state <= done;
else
trans_in.state <= busy;
end if;
state <= send_ack;
substate <= 0;
elsif valid_handsh='1' then
buf_en <= '0';
if rx_pid = c_pid_nak then
if pipe_in.control='1' then
state <= idle; -- retry on next sof, do not go to the next transaction
else
state <= update_trans; -- is not updated, but is the standard path to go to the next transact.
end if;
elsif rx_pid = c_pid_stall then
trans_in.state <= error;
pipe_in.state <= stalled;
state <= update_pipe;
end if;
elsif timeout then -- device doesn't answer, could it have missed my in token?
buf_en <= '0';
state <= handle_trans;
end if;
when send_ack =>
case substate is
when 0 =>
send_handsh <= '1';
tx_pid <= c_pid_ack;
when 1 =>
if tx_ack='0' then
substate <= 1; -- stay here.
else
send_handsh <= '0';
state <= update_trans;
-- if (pipe_in.control='0') and (trans_in.state = done) then
-- state <= update_trans;
-- elsif (pipe_in.control='1') and (trans_len = 2) then -- no data, thus status already received
-- state <= update_trans;
-- else
-- null;
-- -- substate <= 2;
-- end if;
end if;
-- when 2 => -- send status back (no data packet)
-- tx_pid <= c_pid_out;
-- tx_token <= pipe_in.device_endpoint & pipe_in.device_address;
-- send_token <= '1';
-- when 3 => -- wait until token was sent
-- if tx_ack='0' then
-- substate <= 3;
-- else
-- send_token <= '0';
-- no_data_i <= true;
-- send_data <= '1';
-- tx_pid <= c_pid_data1;
-- end if;
-- when 4 => -- wait until no data packet was processed
-- if tx_ack='0' then
-- substate <= 4;
-- else
-- send_data <= '0';
-- state <= update_trans;
-- end if;
when others =>
null;
end case;
when update_pipe =>
descr_addr_i <= (others => '0');
descr_addr_i(trans_in.pipe_pointer'range) <= trans_in.pipe_pointer;
descr_en <= '1';
descr_we <= '1';
descr_wdata <= t_pipe_to_data(pipe_in);
state <= update_trans;
when update_trans =>
descr_addr_i <= c_transaction_offset & to_unsigned(transaction_pntr,
descr_addr_i'length-c_transaction_offset'length);
descr_wdata <= t_transaction_to_data(trans_in);
descr_en <= '1';
descr_we <= '1';
next_transaction;
when others =>
null;
end case;
---------------------------------------------------
-- DEBUG
---------------------------------------------------
-- if state /= receive_data then
-- debug_count <= 0;
-- debug_error <= '0';
-- elsif debug_count = 1023 then
-- debug_error <= '1';
-- else
-- debug_count <= debug_count + 1;
-- end if;
---------------------------------------------------
if frame_div = 0 then
do_sof <= sof_enable;
if speed(1)='1' then
frame_div <= 7499; -- microframes
else
frame_div <= 59999; -- 1 ms frames
end if;
else
frame_div <= frame_div - 1;
end if;
if reset_done='0' then
state <= startup;
end if;
if speed /= "10" then -- If not high speed, then we force no ping
need_ping <= '0';
end if;
if reset = '1' then
abort_reg <= '0';
buf_en <= '0';
buf_addr_i <= (others => '0');
trans_len <= (others => '0');
trans_cnt <= (others => '0');
link_busy <= '0';
state <= startup;
do_sof <= '0';
frame_div <= 7499;
frame_cnt <= (others => '0');
send_token <= '0';
send_data <= '0';
send_handsh <= '0';
need_ping <= '0';
terminate <= '0';
end if;
end if;
end process;
-- Decoupling of ulpi tx bus and our generation of data
-- to meet timing of "next" signal
-- fifo_data_in <= reset_data when (state = startup) else buf_rdata;
fifo_data_in <= buf_rdata;
i_srl_tx: entity work.srl_fifo
generic map (
Width => 9,
Depth => 15,
Threshold => 10 )
port map (
clock => clock,
reset => reset,
GetElement => user_next,
PutElement => tx_put,
FlushFifo => '0',
DataIn(7 downto 0) => fifo_data_in,
DataIn(8) => tx_last,
DataOut(7 downto 0) => user_data,
DataOut(8) => user_last,
SpaceInFifo => open,
AlmostFull => tx_almost_full,
DataInFifo => user_valid );
end functional;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_host is
port (
clock : in std_logic;
reset : in std_logic;
-- Descriptor RAM interface
descr_addr : out std_logic_vector(8 downto 0);
descr_rdata : in std_logic_vector(31 downto 0);
descr_wdata : out std_logic_vector(31 downto 0);
descr_en : out std_logic;
descr_we : out std_logic;
-- Buffer RAM interface
buf_addr : out std_logic_vector(10 downto 0);
buf_rdata : in std_logic_vector(7 downto 0);
buf_wdata : out std_logic_vector(7 downto 0);
buf_en : out std_logic;
buf_we : out std_logic;
-- Transmit Path Interface
tx_busy : in std_logic;
tx_ack : in std_logic;
-- Interface to send tokens and handshakes
send_token : out std_logic;
send_handsh : out std_logic;
tx_pid : out std_logic_vector(3 downto 0);
tx_token : out std_logic_vector(10 downto 0);
-- Interface to send data packets
send_data : out std_logic;
no_data : out std_logic;
user_data : out std_logic_vector(7 downto 0);
user_last : out std_logic;
user_valid : out std_logic;
user_next : in std_logic;
-- Interface to bus initialization unit
reset_done : in std_logic;
sof_enable : in std_logic;
scan_enable : in std_logic := '1';
speed : in std_logic_vector(1 downto 0);
abort : in std_logic;
-- Receive Path Interface
rx_pid : in std_logic_vector(3 downto 0);
rx_token : in std_logic_vector(10 downto 0);
valid_token : in std_logic;
valid_handsh : in std_logic;
valid_packet : in std_logic;
data_valid : in std_logic;
data_start : in std_logic;
data_out : in std_logic_vector(7 downto 0);
rx_error : in std_logic );
end ulpi_host;
architecture functional of ulpi_host is
signal frame_div : integer range 0 to 65535;
signal frame_cnt : unsigned(13 downto 0) := (others => '0');
signal do_sof : std_logic;
constant c_max_transaction : integer := 31;
constant c_max_pipe : integer := 31;
constant c_timeout_val : integer := 7167;
constant c_transaction_offset : unsigned(8 downto 6) := "001";
signal transaction_pntr : integer range 0 to c_max_transaction;
signal descr_addr_i : unsigned(8 downto 0); -- could be temporarily pipe addr
type t_state is (startup, idle, wait4start, scan_transactions, get_pipe,
handle_trans, setup_token, bulk_token, send_data_packet, get_status,
wait_for_ack, receive_data, send_ack, update_pipe, update_trans, do_ping );
signal state : t_state;
signal substate : integer range 0 to 7;
signal trans_in : t_transaction;
signal pipe_in : t_pipe;
signal trans_cnt : unsigned(10 downto 0);
signal trans_len : unsigned(10 downto 0);
signal buf_addr_i : unsigned(10 downto 0);
-- signal speed : std_logic_vector(1 downto 0) := "11";
signal no_data_i : boolean;
signal abort_reg : std_logic;
signal tx_put : std_logic;
signal tx_last : std_logic;
signal need_ping : std_logic;
signal fifo_data_in : std_logic_vector(7 downto 0);
signal tx_almost_full : std_logic;
signal link_busy : std_logic;
signal timeout : boolean;
signal timeout_cnt : integer range 0 to c_timeout_val;
signal first_transfer : boolean;
signal terminate : std_logic;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "sequential";
-- attribute keep : string;
-- attribute keep of timeout : signal is "true";
signal debug_count : integer range 0 to 1023 := 0;
signal debug_error : std_logic := '0';
begin
descr_addr <= std_logic_vector(descr_addr_i);
buf_addr <= std_logic_vector(buf_addr_i);
no_data <= '1' when no_data_i else '0';
buf_wdata <= data_out; -- should be rx_data
buf_we <= '1' when (state = receive_data) and (data_valid = '1') else '0';
p_protocol: process(clock)
procedure next_transaction is
begin
if terminate='1' then
terminate <= '0';
state <= idle;
elsif transaction_pntr = c_max_transaction then
transaction_pntr <= 0;
state <= idle; -- wait for next sof before rescan
else
transaction_pntr <= transaction_pntr + 1;
substate <= 0;
state <= scan_transactions;
end if;
end procedure;
function min(a, b: unsigned) return unsigned is
begin
if a < b then
return a;
else
return b;
end if;
end function;
variable trans_temp : t_transaction;
variable len : unsigned(trans_temp.transfer_length'range);
begin
if rising_edge(clock) then
descr_en <= '0';
descr_we <= '0';
tx_put <= '0';
if abort='1' then
abort_reg <= '1';
end if;
-- default counter
if substate /= 3 then
substate <= substate + 1;
end if;
if timeout_cnt /= 0 then
timeout_cnt <= timeout_cnt - 1;
if timeout_cnt = 1 then
timeout <= false;--true;
end if;
end if;
case state is
when startup =>
tx_pid <= c_pid_reserved;
do_sof <= '0';
frame_div <= 7499;
if reset_done='1' then
state <= idle;
if speed = "10" then
need_ping <= '1';
end if;
end if;
when idle =>
abort_reg <= '0';
if do_sof='1' then
do_sof <= '0';
tx_token <= std_logic_vector(frame_cnt(13 downto 3));
tx_pid <= c_pid_sof;
if speed = "00" then
send_handsh <= '1';
else
send_token <= '1';
end if;
if speed(1)='1' then
frame_cnt <= frame_cnt + 1;
else
frame_cnt <= frame_cnt + 8;
end if;
state <= wait4start;
end if;
when wait4start =>
if tx_ack='1' then
send_token <= '0';
send_handsh <= '0';
send_data <= '0'; -- redundant - will not come here
substate <= 0;
if scan_enable='1' then
state <= scan_transactions;
else
state <= idle;
end if;
end if;
when scan_transactions =>
case substate is
when 0 =>
descr_addr_i <= c_transaction_offset & to_unsigned(transaction_pntr,
descr_addr_i'length-c_transaction_offset'length);
descr_en <= '1';
when 2 =>
trans_temp := data_to_t_transaction(descr_rdata);
trans_in <= trans_temp;
substate <= 0;
if trans_temp.state = busy then
state <= get_pipe;
else -- go for next, unless we are at the end of the list
next_transaction;
end if;
when others =>
null;
end case;
when get_pipe =>
case substate is
when 0 =>
descr_addr_i <= (others => '0');
descr_addr_i(trans_in.pipe_pointer'range) <= trans_in.pipe_pointer;
descr_en <= '1';
when 2 =>
pipe_in <= data_to_t_pipe(descr_rdata);
first_transfer <= true;
state <= handle_trans; ---
when others =>
null;
end case;
when handle_trans => -- both pipe and transaction records are now valid
abort_reg <= '0';
substate <= 0;
if do_sof='1' and link_busy='0' then
state <= idle;
elsif pipe_in.state /= initialized then -- can we use the pipe?
trans_in.state <= error;
state <= update_trans;
else -- yes we can
timeout <= false;
timeout_cnt <= c_timeout_val;
link_busy <= trans_in.link_to_next;
case trans_in.transaction_type is
when control =>
-- a control out sequence exists of a setup token
-- and then a data0 packet, which should be followed by
-- an ack from the device. The next phase of the transaction
-- could be either in or out, and defines whether it is a
-- control read or a control write.
-- By choice, control transfers are implemented using
-- two transactions, which are executed in guaranteed
-- sequence.
-- In this way, each stage has its own buffer.
-- Note, the first pipe should be of type OUT, although it is not
-- checked.
tx_pid <= c_pid_setup;
tx_token <= pipe_in.device_endpoint & pipe_in.device_address;
send_token <= '1';
state <= setup_token;
when bulk | interrupt =>
tx_token <= pipe_in.device_endpoint & pipe_in.device_address;
state <= bulk_token;
send_token <= '1';
timeout <= false;
timeout_cnt <= c_timeout_val;
if pipe_in.direction = dir_in then
tx_pid <= c_pid_in;
else
-- if need_ping='1' then
-- tx_pid <= c_pid_ping;
-- state <= do_ping;
-- else
tx_pid <= c_pid_out;
-- end if;
end if;
if pipe_in.control='1' and first_transfer then
pipe_in.data_toggle <= '1'; -- start with data 1
end if;
first_transfer <= false;
when others => -- not yet supported
trans_in.state <= error;
state <= update_trans;
end case;
end if;
when setup_token =>
if tx_ack='1' then
send_token <= '0';
tx_pid <= c_pid_data0; -- send setup data immediately
send_data <= '1';
buf_en <= '1';
substate <= 0;
state <= send_data_packet;
end if;
-- prepare buffer
buf_addr_i <= trans_in.buffer_address;
trans_len <= trans_in.transfer_length; -- not cut up
trans_cnt <= trans_in.transfer_length; -- not cut up
no_data_i <= (trans_in.transfer_length = 0);
when do_ping =>
if tx_ack='1' then
send_token <= '0';
end if;
-- wait for ack/nack or nyet.
if rx_error='1' then
trans_in.state <= error;
state <= update_trans;
elsif abort_reg='1' then
pipe_in.state <= aborted;
state <= update_pipe;
abort_reg <= '0';
elsif valid_handsh='1' then -- maybe an ack?
if rx_pid = c_pid_ack then
tx_pid <= c_pid_out;
send_token <= '1';
state <= bulk_token;
elsif rx_pid = c_pid_stall then
pipe_in.state <= stalled;
trans_in.state <= error;
state <= update_pipe;
elsif (rx_pid = c_pid_nak) or (rx_pid = c_pid_nyet) then
state <= handle_trans;
end if; -- all other pids are just ignored
elsif timeout then
state <= handle_trans;
end if;
when bulk_token =>
if tx_ack='1' then
send_token <= '0';
if pipe_in.direction = dir_out then
if pipe_in.data_toggle = '0' then
tx_pid <= c_pid_data0;
else
tx_pid <= c_pid_data1;
end if;
send_data <= '1';
buf_en <= '1';
substate <= 0;
state <= send_data_packet;
else -- input
timeout <= false;
timeout_cnt <= c_timeout_val;
state <= receive_data;
buf_en <= '1';
end if;
end if;
-- prepare buffer
buf_addr_i <= trans_in.buffer_address;
if pipe_in.direction = dir_out then
len := min(trans_in.transfer_length, pipe_in.max_transfer);
trans_len <= len; -- possibly cut up
trans_cnt <= len;
no_data_i <= (trans_in.transfer_length = 0);
else
trans_len <= (others => '0');
end if;
when send_data_packet =>
case substate is
when 0 =>
if tx_ack='1' then
send_data <= '0';
if no_data_i then
substate <= 2;
end if;
else
substate <= 0;
end if;
when 1 =>
substate <= 1; -- stay!
if tx_almost_full='0' then
tx_put <= '1';
buf_addr_i <= buf_addr_i + 1;
trans_cnt <= trans_cnt - 1;
if trans_cnt = 1 then
tx_last <= '1';
substate <= 2;
buf_en <= '0';
else
tx_last <= '0';
end if;
end if;
when 2 =>
if tx_busy='1' then
substate <= 2;
else
state <= wait_for_ack;
timeout <= false;
timeout_cnt <= c_timeout_val;
end if;
when others =>
null;
end case;
when wait_for_ack =>
if rx_error='1' then
trans_in.state <= error;
state <= update_trans;
elsif abort_reg='1' then
pipe_in.state <= aborted;
state <= update_pipe;
abort_reg <= '0';
elsif valid_handsh='1' then -- maybe an ack?
if (rx_pid = c_pid_ack) or (rx_pid = c_pid_nyet) then
if rx_pid = c_pid_nyet then
need_ping <= '1';
else
need_ping <= '0';
end if;
if trans_in.transfer_length = trans_len then
trans_in.state <= done;
if pipe_in.control='1' and trans_in.transaction_type = bulk then
state <= get_status;
substate <= 0;
else
state <= update_pipe;
end if;
else
trans_in.state <= busy;
state <= handle_trans;
end if;
trans_in.buffer_address <= buf_addr_i; -- store back
trans_in.transfer_length <= trans_in.transfer_length - trans_len;
pipe_in.data_toggle <= not pipe_in.data_toggle;
elsif rx_pid = c_pid_stall then
pipe_in.state <= stalled;
trans_in.state <= error;
state <= update_pipe;
elsif rx_pid = c_pid_nak then
terminate <= '0'; --link_busy; -- if control packet, then don't continue with next transaction!
state <= update_trans;
-- state <= handle_trans; -- just retry and retry, no matter what kind of packet it is, don't send SOF!
end if; -- all other pids are just ignored
-- elsif do_sof='1' then
-- state <= idle; -- test
elsif timeout then
pipe_in.timeout <= '1';
trans_in.state <= error;
state <= update_pipe;
-- state <= handle_trans; -- try again
end if;
when get_status =>
case substate is
when 0 =>
send_token <= '1';
tx_pid <= c_pid_in;
when 1 =>
if tx_ack='1' then
send_token <= '0';
timeout_cnt <= c_timeout_val;
timeout <= false;
else
substate <= 1; -- wait
end if;
when 2 =>
if valid_packet='1' or valid_handsh='1' then
state <= update_pipe; -- end transaction
elsif rx_error='1' or timeout then
trans_in.state <= error;
state <= update_pipe; -- end transaction
else
substate <= 2; -- wait
end if;
when others =>
null;
end case;
when receive_data =>
if data_valid = '1' then
timeout <= false;
timeout_cnt <= 0; -- does not occur anymore
buf_addr_i <= buf_addr_i + 1;
trans_len <= trans_len + 1;
end if;
--------------------------------------------------------------------
if rx_error = '1' or debug_error='1' then
-- go back to send the in token again
buf_en <= '0';
state <= handle_trans;
elsif abort_reg='1' then
pipe_in.state <= aborted;
state <= update_pipe;
abort_reg <= '0';
elsif valid_packet='1' then
buf_en <= '0';
trans_in.buffer_address <= buf_addr_i - 2; -- cut off CRC
trans_in.transfer_length <= trans_in.transfer_length - (trans_len - 2);
if ((trans_len - 2) >= trans_in.transfer_length) or
((trans_len - 2) < pipe_in.max_transfer) then
trans_in.state <= done;
else
trans_in.state <= busy;
end if;
state <= send_ack;
substate <= 0;
elsif valid_handsh='1' then
buf_en <= '0';
if rx_pid = c_pid_nak then
if pipe_in.control='1' then
state <= idle; -- retry on next sof, do not go to the next transaction
else
state <= update_trans; -- is not updated, but is the standard path to go to the next transact.
end if;
elsif rx_pid = c_pid_stall then
trans_in.state <= error;
pipe_in.state <= stalled;
state <= update_pipe;
end if;
elsif timeout then -- device doesn't answer, could it have missed my in token?
buf_en <= '0';
state <= handle_trans;
end if;
when send_ack =>
case substate is
when 0 =>
send_handsh <= '1';
tx_pid <= c_pid_ack;
when 1 =>
if tx_ack='0' then
substate <= 1; -- stay here.
else
send_handsh <= '0';
state <= update_trans;
-- if (pipe_in.control='0') and (trans_in.state = done) then
-- state <= update_trans;
-- elsif (pipe_in.control='1') and (trans_len = 2) then -- no data, thus status already received
-- state <= update_trans;
-- else
-- null;
-- -- substate <= 2;
-- end if;
end if;
-- when 2 => -- send status back (no data packet)
-- tx_pid <= c_pid_out;
-- tx_token <= pipe_in.device_endpoint & pipe_in.device_address;
-- send_token <= '1';
-- when 3 => -- wait until token was sent
-- if tx_ack='0' then
-- substate <= 3;
-- else
-- send_token <= '0';
-- no_data_i <= true;
-- send_data <= '1';
-- tx_pid <= c_pid_data1;
-- end if;
-- when 4 => -- wait until no data packet was processed
-- if tx_ack='0' then
-- substate <= 4;
-- else
-- send_data <= '0';
-- state <= update_trans;
-- end if;
when others =>
null;
end case;
when update_pipe =>
descr_addr_i <= (others => '0');
descr_addr_i(trans_in.pipe_pointer'range) <= trans_in.pipe_pointer;
descr_en <= '1';
descr_we <= '1';
descr_wdata <= t_pipe_to_data(pipe_in);
state <= update_trans;
when update_trans =>
descr_addr_i <= c_transaction_offset & to_unsigned(transaction_pntr,
descr_addr_i'length-c_transaction_offset'length);
descr_wdata <= t_transaction_to_data(trans_in);
descr_en <= '1';
descr_we <= '1';
next_transaction;
when others =>
null;
end case;
---------------------------------------------------
-- DEBUG
---------------------------------------------------
-- if state /= receive_data then
-- debug_count <= 0;
-- debug_error <= '0';
-- elsif debug_count = 1023 then
-- debug_error <= '1';
-- else
-- debug_count <= debug_count + 1;
-- end if;
---------------------------------------------------
if frame_div = 0 then
do_sof <= sof_enable;
if speed(1)='1' then
frame_div <= 7499; -- microframes
else
frame_div <= 59999; -- 1 ms frames
end if;
else
frame_div <= frame_div - 1;
end if;
if reset_done='0' then
state <= startup;
end if;
if speed /= "10" then -- If not high speed, then we force no ping
need_ping <= '0';
end if;
if reset = '1' then
abort_reg <= '0';
buf_en <= '0';
buf_addr_i <= (others => '0');
trans_len <= (others => '0');
trans_cnt <= (others => '0');
link_busy <= '0';
state <= startup;
do_sof <= '0';
frame_div <= 7499;
frame_cnt <= (others => '0');
send_token <= '0';
send_data <= '0';
send_handsh <= '0';
need_ping <= '0';
terminate <= '0';
end if;
end if;
end process;
-- Decoupling of ulpi tx bus and our generation of data
-- to meet timing of "next" signal
-- fifo_data_in <= reset_data when (state = startup) else buf_rdata;
fifo_data_in <= buf_rdata;
i_srl_tx: entity work.srl_fifo
generic map (
Width => 9,
Depth => 15,
Threshold => 10 )
port map (
clock => clock,
reset => reset,
GetElement => user_next,
PutElement => tx_put,
FlushFifo => '0',
DataIn(7 downto 0) => fifo_data_in,
DataIn(8) => tx_last,
DataOut(7 downto 0) => user_data,
DataOut(8) => user_last,
SpaceInFifo => open,
AlmostFull => tx_almost_full,
DataInFifo => user_valid );
end functional;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2821.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity OR is
end OR;
ENTITY c13s09b00x00p99n01i02821ent IS
END c13s09b00x00p99n01i02821ent;
ARCHITECTURE c13s09b00x00p99n01i02821arch OF c13s09b00x00p99n01i02821ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02821 - Reserved word OR can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02821arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2821.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity OR is
end OR;
ENTITY c13s09b00x00p99n01i02821ent IS
END c13s09b00x00p99n01i02821ent;
ARCHITECTURE c13s09b00x00p99n01i02821arch OF c13s09b00x00p99n01i02821ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02821 - Reserved word OR can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02821arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2821.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity OR is
end OR;
ENTITY c13s09b00x00p99n01i02821ent IS
END c13s09b00x00p99n01i02821ent;
ARCHITECTURE c13s09b00x00p99n01i02821arch OF c13s09b00x00p99n01i02821ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02821 - Reserved word OR can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02821arch;
|
------------------------------------------------------------------------------
-- C:/Users/ael10jso/Xilinx/embedded_bruteforce/brutus_system/hdl/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd
------------------------------------------------------------------------------
-- ClkGen Wrapper HDL file generated by ClkGen's TCL generator
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.vcomponents.all;
library clock_generator_v4_03_a;
use clock_generator_v4_03_a.all;
entity clock_generator is
generic (
C_FAMILY : string := "spartan6" ;
C_DEVICE : string := "6slx16";
C_PACKAGE : string := "csg324";
C_SPEEDGRADE : string := "-3";
C_CLK_GEN : string := "PASSED"
);
port (
-- clock generation
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
-- external feedback
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
-- variable phase shift
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
-- reset
RST : in std_logic;
LOCKED : out std_logic
);
end clock_generator;
architecture STRUCTURE of clock_generator is
----------------------------------------------------------------------------
-- Components ( copy from entity, exact the same in low level parameters )
----------------------------------------------------------------------------
component pll_module is
generic (
C_BANDWIDTH : string := "OPTIMIZED";
C_CLKFBOUT_MULT : integer := 1;
C_CLKFBOUT_PHASE : real := 0.0;
C_CLKIN1_PERIOD : real := 0.000;
-- C_CLKIN2_PERIOD : real := 0.000;
C_CLKOUT0_DIVIDE : integer := 1;
C_CLKOUT0_DUTY_CYCLE : real := 0.5;
C_CLKOUT0_PHASE : real := 0.0;
C_CLKOUT1_DIVIDE : integer := 1;
C_CLKOUT1_DUTY_CYCLE : real := 0.5;
C_CLKOUT1_PHASE : real := 0.0;
C_CLKOUT2_DIVIDE : integer := 1;
C_CLKOUT2_DUTY_CYCLE : real := 0.5;
C_CLKOUT2_PHASE : real := 0.0;
C_CLKOUT3_DIVIDE : integer := 1;
C_CLKOUT3_DUTY_CYCLE : real := 0.5;
C_CLKOUT3_PHASE : real := 0.0;
C_CLKOUT4_DIVIDE : integer := 1;
C_CLKOUT4_DUTY_CYCLE : real := 0.5;
C_CLKOUT4_PHASE : real := 0.0;
C_CLKOUT5_DIVIDE : integer := 1;
C_CLKOUT5_DUTY_CYCLE : real := 0.5;
C_CLKOUT5_PHASE : real := 0.0;
C_COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
C_DIVCLK_DIVIDE : integer := 1;
-- C_EN_REL : boolean := false;
-- C_PLL_PMCD_MODE : boolean := false;
C_REF_JITTER : real := 0.100;
C_RESET_ON_LOSS_OF_LOCK : boolean := false;
C_RST_DEASSERT_CLK : string := "CLKIN1";
C_CLKOUT0_DESKEW_ADJUST : string := "NONE";
C_CLKOUT1_DESKEW_ADJUST : string := "NONE";
C_CLKOUT2_DESKEW_ADJUST : string := "NONE";
C_CLKOUT3_DESKEW_ADJUST : string := "NONE";
C_CLKOUT4_DESKEW_ADJUST : string := "NONE";
C_CLKOUT5_DESKEW_ADJUST : string := "NONE";
C_CLKFBOUT_DESKEW_ADJUST : string := "NONE";
C_CLKIN1_BUF : boolean := false;
-- C_CLKIN2_BUF : boolean := false;
C_CLKFBOUT_BUF : boolean := false;
C_CLKOUT0_BUF : boolean := false;
C_CLKOUT1_BUF : boolean := false;
C_CLKOUT2_BUF : boolean := false;
C_CLKOUT3_BUF : boolean := false;
C_CLKOUT4_BUF : boolean := false;
C_CLKOUT5_BUF : boolean := false;
C_EXT_RESET_HIGH : integer := 1;
C_FAMILY : string := "spartan6"
);
port (
CLKFBDCM : out std_logic;
CLKFBOUT : out std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUTDCM0 : out std_logic;
CLKOUTDCM1 : out std_logic;
CLKOUTDCM2 : out std_logic;
CLKOUTDCM3 : out std_logic;
CLKOUTDCM4 : out std_logic;
CLKOUTDCM5 : out std_logic;
-- DO : out std_logic_vector (15 downto 0);
-- DRDY : out std_logic;
LOCKED : out std_logic;
CLKFBIN : in std_logic;
CLKIN1 : in std_logic;
-- CLKIN2 : in std_logic;
-- CLKINSEL : in std_logic;
-- DADDR : in std_logic_vector (4 downto 0);
-- DCLK : in std_logic;
-- DEN : in std_logic;
-- DI : in std_logic_vector (15 downto 0);
-- DWE : in std_logic;
-- REL : in std_logic;
RST : in std_logic
);
end component;
----------------------------------------------------------------------------
-- Functions
----------------------------------------------------------------------------
-- Note : The string functions are put here to remove dependency to other pcore level libraries
function UpperCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'a' or char > 'z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'a' => return 'A'; when 'b' => return 'B'; when 'c' => return 'C'; when 'd' => return 'D';
when 'e' => return 'E'; when 'f' => return 'F'; when 'g' => return 'G'; when 'h' => return 'H';
when 'i' => return 'I'; when 'j' => return 'J'; when 'k' => return 'K'; when 'l' => return 'L';
when 'm' => return 'M'; when 'n' => return 'N'; when 'o' => return 'O'; when 'p' => return 'P';
when 'q' => return 'Q'; when 'r' => return 'R'; when 's' => return 'S'; when 't' => return 'T';
when 'u' => return 'U'; when 'v' => return 'V'; when 'w' => return 'W'; when 'x' => return 'X';
when 'y' => return 'Y'; when 'z' => return 'Z';
when others => return char;
end case;
end UpperCase_Char;
function UpperCase_String (s : string) return string is
variable res : string(s'range);
begin -- function LoweerCase_String
for I in s'range loop
res(I) := UpperCase_Char(s(I));
end loop; -- I
return res;
end function UpperCase_String;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function equalString( str1, str2 : string ) return boolean is
constant len1 : integer := str1'length;
constant len2 : integer := str2'length;
variable equal : boolean := true;
begin
if not (len1 = len2) then
equal := false;
else
for i in str1'range loop
if not (UpperCase_Char(str1(i)) = UpperCase_Char(str2(i))) then
equal := false;
end if;
end loop;
end if;
return equal;
end equalString;
----------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------
-- signals: gnd
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd16 : std_logic_vector(0 to 15);
-- signals: vdd
signal net_vdd0 : std_logic;
-- signals : PLL0 wrapper
signal SIG_PLL0_CLKFBDCM : std_logic;
signal SIG_PLL0_CLKFBOUT : std_logic;
signal SIG_PLL0_CLKOUT0 : std_logic;
signal SIG_PLL0_CLKOUT1 : std_logic;
signal SIG_PLL0_CLKOUT2 : std_logic;
signal SIG_PLL0_CLKOUT3 : std_logic;
signal SIG_PLL0_CLKOUT4 : std_logic;
signal SIG_PLL0_CLKOUT5 : std_logic;
signal SIG_PLL0_CLKOUTDCM0 : std_logic;
signal SIG_PLL0_CLKOUTDCM1 : std_logic;
signal SIG_PLL0_CLKOUTDCM2 : std_logic;
signal SIG_PLL0_CLKOUTDCM3 : std_logic;
signal SIG_PLL0_CLKOUTDCM4 : std_logic;
signal SIG_PLL0_CLKOUTDCM5 : std_logic;
signal SIG_PLL0_LOCKED : std_logic;
signal SIG_PLL0_CLKFBIN : std_logic;
signal SIG_PLL0_CLKIN1 : std_logic;
signal SIG_PLL0_RST : std_logic;
signal SIG_PLL0_CLKFBOUT_BUF : std_logic;
signal SIG_PLL0_CLKOUT0_BUF : std_logic;
signal SIG_PLL0_CLKOUT1_BUF : std_logic;
signal SIG_PLL0_CLKOUT2_BUF : std_logic;
signal SIG_PLL0_CLKOUT3_BUF : std_logic;
signal SIG_PLL0_CLKOUT4_BUF : std_logic;
signal SIG_PLL0_CLKOUT5_BUF : std_logic;
begin
----------------------------------------------------------------------------
-- GND and VCC signals
----------------------------------------------------------------------------
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd16(0 to 15) <= B"0000000000000000";
net_vdd0 <= '1';
----------------------------------------------------------------------------
-- DCM wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLL wrappers
----------------------------------------------------------------------------
-- PLL0 wrapper
PLL0_INST : pll_module
generic map (
C_BANDWIDTH => "OPTIMIZED",
C_CLKFBOUT_MULT => 10,
C_CLKFBOUT_PHASE => 0.0,
C_CLKIN1_PERIOD => 10.000000,
C_CLKOUT0_DIVIDE => 20,
C_CLKOUT0_DUTY_CYCLE => 0.5,
C_CLKOUT0_PHASE => 0.0000,
C_CLKOUT1_DIVIDE => 1,
C_CLKOUT1_DUTY_CYCLE => 0.5,
C_CLKOUT1_PHASE => 0.0,
C_CLKOUT2_DIVIDE => 1,
C_CLKOUT2_DUTY_CYCLE => 0.5,
C_CLKOUT2_PHASE => 0.0,
C_CLKOUT3_DIVIDE => 1,
C_CLKOUT3_DUTY_CYCLE => 0.5,
C_CLKOUT3_PHASE => 0.0,
C_CLKOUT4_DIVIDE => 1,
C_CLKOUT4_DUTY_CYCLE => 0.5,
C_CLKOUT4_PHASE => 0.0,
C_CLKOUT5_DIVIDE => 1,
C_CLKOUT5_DUTY_CYCLE => 0.5,
C_CLKOUT5_PHASE => 0.0,
C_COMPENSATION => "SYSTEM_SYNCHRONOUS",
C_DIVCLK_DIVIDE => 1,
C_REF_JITTER => 0.100,
C_RESET_ON_LOSS_OF_LOCK => false,
C_RST_DEASSERT_CLK => "CLKIN1",
C_CLKOUT0_DESKEW_ADJUST => "NONE",
C_CLKOUT1_DESKEW_ADJUST => "NONE",
C_CLKOUT2_DESKEW_ADJUST => "NONE",
C_CLKOUT3_DESKEW_ADJUST => "NONE",
C_CLKOUT4_DESKEW_ADJUST => "NONE",
C_CLKOUT5_DESKEW_ADJUST => "NONE",
C_CLKFBOUT_DESKEW_ADJUST => "NONE",
C_CLKIN1_BUF => false,
C_CLKFBOUT_BUF => false,
C_CLKOUT0_BUF => false,
C_CLKOUT1_BUF => false,
C_CLKOUT2_BUF => false,
C_CLKOUT3_BUF => false,
C_CLKOUT4_BUF => false,
C_CLKOUT5_BUF => false,
C_EXT_RESET_HIGH => 1,
C_FAMILY => "spartan6"
)
port map (
CLKFBDCM => SIG_PLL0_CLKFBDCM,
CLKFBOUT => SIG_PLL0_CLKFBOUT,
CLKOUT0 => SIG_PLL0_CLKOUT0,
CLKOUT1 => SIG_PLL0_CLKOUT1,
CLKOUT2 => SIG_PLL0_CLKOUT2,
CLKOUT3 => SIG_PLL0_CLKOUT3,
CLKOUT4 => SIG_PLL0_CLKOUT4,
CLKOUT5 => SIG_PLL0_CLKOUT5,
CLKOUTDCM0 => SIG_PLL0_CLKOUTDCM0,
CLKOUTDCM1 => SIG_PLL0_CLKOUTDCM1,
CLKOUTDCM2 => SIG_PLL0_CLKOUTDCM2,
CLKOUTDCM3 => SIG_PLL0_CLKOUTDCM3,
CLKOUTDCM4 => SIG_PLL0_CLKOUTDCM4,
CLKOUTDCM5 => SIG_PLL0_CLKOUTDCM5,
-- DO
-- DRDY
LOCKED => SIG_PLL0_LOCKED,
CLKFBIN => SIG_PLL0_CLKFBIN,
CLKIN1 => SIG_PLL0_CLKIN1,
-- CLKIN2
-- CLKINSEL
-- DADDR
-- DCLK
-- DEN
-- DI
-- DWE
-- REL
RST => SIG_PLL0_RST
);
-- wrapper of clkout : CLKOUT0
PLL0_CLKOUT0_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKOUT0,
O => SIG_PLL0_CLKOUT0_BUF
);
-- wrapper of clkout : CLKOUT1
SIG_PLL0_CLKOUT1_BUF <= SIG_PLL0_CLKOUT1;
-- wrapper of clkout : CLKOUT2
SIG_PLL0_CLKOUT2_BUF <= SIG_PLL0_CLKOUT2;
-- wrapper of clkout : CLKOUT3
SIG_PLL0_CLKOUT3_BUF <= SIG_PLL0_CLKOUT3;
-- wrapper of clkout : CLKOUT4
SIG_PLL0_CLKOUT4_BUF <= SIG_PLL0_CLKOUT4;
-- wrapper of clkout : CLKOUT5
SIG_PLL0_CLKOUT5_BUF <= SIG_PLL0_CLKOUT5;
-- wrapper of clkout : CLKFBOUT
PLL0_CLKFBOUT_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKFBOUT,
O => SIG_PLL0_CLKFBOUT_BUF
);
----------------------------------------------------------------------------
-- MMCM wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLE wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- DCMs CLKIN, CLKFB and RST signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLs CLKIN1, CLKFBIN and RST signal connection
----------------------------------------------------------------------------
-- PLL0 CLKIN1
SIG_PLL0_CLKIN1 <= CLKIN;
-- PLL0 CLKFBIN
SIG_PLL0_CLKFBIN <= SIG_PLL0_CLKFBOUT;
-- PLL0 RST
SIG_PLL0_RST <= RST;
----------------------------------------------------------------------------
-- MMCMs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLEs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- CLKGEN CLKOUT, CLKFBOUT and LOCKED signal connection
----------------------------------------------------------------------------
-- CLKGEN CLKOUT
CLKOUT0 <= SIG_PLL0_CLKOUT0_BUF;
CLKOUT1 <= '0';
CLKOUT2 <= '0';
CLKOUT3 <= '0';
CLKOUT4 <= '0';
CLKOUT5 <= '0';
CLKOUT6 <= '0';
CLKOUT7 <= '0';
CLKOUT8 <= '0';
CLKOUT9 <= '0';
CLKOUT10 <= '0';
CLKOUT11 <= '0';
CLKOUT12 <= '0';
CLKOUT13 <= '0';
CLKOUT14 <= '0';
CLKOUT15 <= '0';
-- CLKGEN CLKFBOUT
-- CLKGEN LOCKED
LOCKED <= SIG_PLL0_LOCKED;
end architecture STRUCTURE;
------------------------------------------------------------------------------
-- High level parameters
------------------------------------------------------------------------------
-- C_CLK_GEN = PASSED
-- C_ELABORATE_DIR =
-- C_ELABORATE_RES = NOT_SET
-- C_FAMILY = spartan6
-- C_DEVICE = 6slx16
-- C_PACKAGE = csg324
-- C_SPEEDGRADE = -3
----------------------------------------
-- C_EXTRA_MMCM_FOR_DESKEW =
-- C_MMCMExtra_CLKIN_FREQ =
-- C_MMCMExtra_CLKOUT0 =
-- C_MMCMExtra_CLKOUT1 =
-- C_MMCMExtra_CLKOUT2 =
-- C_MMCMExtra_CLKOUT3 =
-- C_MMCMExtra_CLKOUT4 =
-- C_MMCMExtra_CLKOUT5 =
-- C_MMCMExtra_CLKOUT6 =
-- C_MMCMExtra_CLKOUT7 =
-- C_MMCMExtra_CLKOUT8 =
-- C_MMCMExtra_CLKOUT9 =
-- C_MMCMExtra_CLKOUT10 =
-- C_MMCMExtra_CLKOUT11 =
-- C_MMCMExtra_CLKOUT12 =
-- C_MMCMExtra_CLKOUT13 =
-- C_MMCMExtra_CLKOUT14 =
-- C_MMCMExtra_CLKOUT15 =
-- C_MMCMExtra_CLKFBOUT_MULT =
-- C_MMCMExtra_DIVCLK_DIVIDE =
-- C_MMCMExtra_CLKOUT0_DIVIDE =
-- C_MMCMExtra_CLKOUT1_DIVIDE =
-- C_MMCMExtra_CLKOUT2_DIVIDE =
-- C_MMCMExtra_CLKOUT3_DIVIDE =
-- C_MMCMExtra_CLKOUT4_DIVIDE =
-- C_MMCMExtra_CLKOUT5_DIVIDE =
-- C_MMCMExtra_CLKOUT6_DIVIDE =
-- C_MMCMExtra_CLKOUT0_BUF =
-- C_MMCMExtra_CLKOUT1_BUF =
-- C_MMCMExtra_CLKOUT2_BUF =
-- C_MMCMExtra_CLKOUT3_BUF =
-- C_MMCMExtra_CLKOUT4_BUF =
-- C_MMCMExtra_CLKOUT5_BUF =
-- C_MMCMExtra_CLKOUT6_BUF =
-- C_MMCMExtra_CLKFBOUT_BUF =
-- C_MMCMExtra_CLKOUT0_PHASE =
-- C_MMCMExtra_CLKOUT1_PHASE =
-- C_MMCMExtra_CLKOUT2_PHASE =
-- C_MMCMExtra_CLKOUT3_PHASE =
-- C_MMCMExtra_CLKOUT4_PHASE =
-- C_MMCMExtra_CLKOUT5_PHASE =
-- C_MMCMExtra_CLKOUT6_PHASE =
----------------------------------------
-- C_CLKIN_FREQ = 100000000
-- C_CLKOUT0_FREQ = 50000000
-- C_CLKOUT0_PHASE = 0
-- C_CLKOUT0_GROUP = NONE
-- C_CLKOUT0_BUF = TRUE
-- C_CLKOUT0_VARIABLE_PHASE = FALSE
-- C_CLKOUT1_FREQ = 0
-- C_CLKOUT1_PHASE = 0
-- C_CLKOUT1_GROUP = NONE
-- C_CLKOUT1_BUF = TRUE
-- C_CLKOUT1_VARIABLE_PHASE = FALSE
-- C_CLKOUT2_FREQ = 0
-- C_CLKOUT2_PHASE = 0
-- C_CLKOUT2_GROUP = NONE
-- C_CLKOUT2_BUF = TRUE
-- C_CLKOUT2_VARIABLE_PHASE = FALSE
-- C_CLKOUT3_FREQ = 0
-- C_CLKOUT3_PHASE = 0
-- C_CLKOUT3_GROUP = NONE
-- C_CLKOUT3_BUF = TRUE
-- C_CLKOUT3_VARIABLE_PHASE = FALSE
-- C_CLKOUT4_FREQ = 0
-- C_CLKOUT4_PHASE = 0
-- C_CLKOUT4_GROUP = NONE
-- C_CLKOUT4_BUF = TRUE
-- C_CLKOUT4_VARIABLE_PHASE = FALSE
-- C_CLKOUT5_FREQ = 0
-- C_CLKOUT5_PHASE = 0
-- C_CLKOUT5_GROUP = NONE
-- C_CLKOUT5_BUF = TRUE
-- C_CLKOUT5_VARIABLE_PHASE = FALSE
-- C_CLKOUT6_FREQ = 0
-- C_CLKOUT6_PHASE = 0
-- C_CLKOUT6_GROUP = NONE
-- C_CLKOUT6_BUF = TRUE
-- C_CLKOUT6_VARIABLE_PHASE = FALSE
-- C_CLKOUT7_FREQ = 0
-- C_CLKOUT7_PHASE = 0
-- C_CLKOUT7_GROUP = NONE
-- C_CLKOUT7_BUF = TRUE
-- C_CLKOUT7_VARIABLE_PHASE = FALSE
-- C_CLKOUT8_FREQ = 0
-- C_CLKOUT8_PHASE = 0
-- C_CLKOUT8_GROUP = NONE
-- C_CLKOUT8_BUF = TRUE
-- C_CLKOUT8_VARIABLE_PHASE = FALSE
-- C_CLKOUT9_FREQ = 0
-- C_CLKOUT9_PHASE = 0
-- C_CLKOUT9_GROUP = NONE
-- C_CLKOUT9_BUF = TRUE
-- C_CLKOUT9_VARIABLE_PHASE = FALSE
-- C_CLKOUT10_FREQ = 0
-- C_CLKOUT10_PHASE = 0
-- C_CLKOUT10_GROUP = NONE
-- C_CLKOUT10_BUF = TRUE
-- C_CLKOUT10_VARIABLE_PHASE = FALSE
-- C_CLKOUT11_FREQ = 0
-- C_CLKOUT11_PHASE = 0
-- C_CLKOUT11_GROUP = NONE
-- C_CLKOUT11_BUF = TRUE
-- C_CLKOUT11_VARIABLE_PHASE = FALSE
-- C_CLKOUT12_FREQ = 0
-- C_CLKOUT12_PHASE = 0
-- C_CLKOUT12_GROUP = NONE
-- C_CLKOUT12_BUF = TRUE
-- C_CLKOUT12_VARIABLE_PHASE = FALSE
-- C_CLKOUT13_FREQ = 0
-- C_CLKOUT13_PHASE = 0
-- C_CLKOUT13_GROUP = NONE
-- C_CLKOUT13_BUF = TRUE
-- C_CLKOUT13_VARIABLE_PHASE = FALSE
-- C_CLKOUT14_FREQ = 0
-- C_CLKOUT14_PHASE = 0
-- C_CLKOUT14_GROUP = NONE
-- C_CLKOUT14_BUF = TRUE
-- C_CLKOUT14_VARIABLE_PHASE = FALSE
-- C_CLKOUT15_FREQ = 0
-- C_CLKOUT15_PHASE = 0
-- C_CLKOUT15_GROUP = NONE
-- C_CLKOUT15_BUF = TRUE
-- C_CLKOUT15_VARIABLE_PHASE = FALSE
----------------------------------------
-- C_CLKFBIN_FREQ = 0
-- C_CLKFBIN_DESKEW = NONE
-- C_CLKFBOUT_FREQ = 0
-- C_CLKFBOUT_GROUP = NONE
-- C_CLKFBOUT_BUF = TRUE
----------------------------------------
-- C_PSDONE_GROUP = NONE
------------------------------------------------------------------------------
-- Low level parameters
------------------------------------------------------------------------------
-- C_CLKOUT0_MODULE = PLL0
-- C_CLKOUT0_PORT = CLKOUT0B
-- C_CLKOUT1_MODULE = NONE
-- C_CLKOUT1_PORT = NONE
-- C_CLKOUT2_MODULE = NONE
-- C_CLKOUT2_PORT = NONE
-- C_CLKOUT3_MODULE = NONE
-- C_CLKOUT3_PORT = NONE
-- C_CLKOUT4_MODULE = NONE
-- C_CLKOUT4_PORT = NONE
-- C_CLKOUT5_MODULE = NONE
-- C_CLKOUT5_PORT = NONE
-- C_CLKOUT6_MODULE = NONE
-- C_CLKOUT6_PORT = NONE
-- C_CLKOUT7_MODULE = NONE
-- C_CLKOUT7_PORT = NONE
-- C_CLKOUT8_MODULE = NONE
-- C_CLKOUT8_PORT = NONE
-- C_CLKOUT9_MODULE = NONE
-- C_CLKOUT9_PORT = NONE
-- C_CLKOUT10_MODULE = NONE
-- C_CLKOUT10_PORT = NONE
-- C_CLKOUT11_MODULE = NONE
-- C_CLKOUT11_PORT = NONE
-- C_CLKOUT12_MODULE = NONE
-- C_CLKOUT12_PORT = NONE
-- C_CLKOUT13_MODULE = NONE
-- C_CLKOUT13_PORT = NONE
-- C_CLKOUT14_MODULE = NONE
-- C_CLKOUT14_PORT = NONE
-- C_CLKOUT15_MODULE = NONE
-- C_CLKOUT15_PORT = NONE
----------------------------------------
-- C_CLKFBOUT_MODULE = NONE
-- C_CLKFBOUT_PORT = NONE
-- C_CLKFBOUT_get_clkgen_dcm_default_params = NONE
----------------------------------------
-- C_PSDONE_MODULE = NONE
----------------------------------------
-- C_DCM0_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM0_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM0_DUTY_CYCLE_CORRECTION = true
-- C_DCM0_CLKIN_DIVIDE_BY_2 = false
-- C_DCM0_CLK_FEEDBACK = "1X"
-- C_DCM0_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM0_DSS_MODE = "NONE"
-- C_DCM0_STARTUP_WAIT = false
-- C_DCM0_PHASE_SHIFT = 0
-- C_DCM0_CLKFX_MULTIPLY = 4
-- C_DCM0_CLKFX_DIVIDE = 1
-- C_DCM0_CLKDV_DIVIDE = 2.0
-- C_DCM0_CLKIN_PERIOD = 41.6666666
-- C_DCM0_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM0_CLKIN_BUF = false
-- C_DCM0_CLKFB_BUF = false
-- C_DCM0_CLK0_BUF = false
-- C_DCM0_CLK90_BUF = false
-- C_DCM0_CLK180_BUF = false
-- C_DCM0_CLK270_BUF = false
-- C_DCM0_CLKDV_BUF = false
-- C_DCM0_CLK2X_BUF = false
-- C_DCM0_CLK2X180_BUF = false
-- C_DCM0_CLKFX_BUF = false
-- C_DCM0_CLKFX180_BUF = false
-- C_DCM0_EXT_RESET_HIGH = 1
-- C_DCM0_FAMILY = "spartan6"
-- C_DCM0_CLKIN_MODULE = NONE
-- C_DCM0_CLKIN_PORT = NONE
-- C_DCM0_CLKFB_MODULE = NONE
-- C_DCM0_CLKFB_PORT = NONE
-- C_DCM0_RST_MODULE = NONE
-- C_DCM1_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM1_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM1_DUTY_CYCLE_CORRECTION = true
-- C_DCM1_CLKIN_DIVIDE_BY_2 = false
-- C_DCM1_CLK_FEEDBACK = "1X"
-- C_DCM1_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM1_DSS_MODE = "NONE"
-- C_DCM1_STARTUP_WAIT = false
-- C_DCM1_PHASE_SHIFT = 0
-- C_DCM1_CLKFX_MULTIPLY = 4
-- C_DCM1_CLKFX_DIVIDE = 1
-- C_DCM1_CLKDV_DIVIDE = 2.0
-- C_DCM1_CLKIN_PERIOD = 41.6666666
-- C_DCM1_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM1_CLKIN_BUF = false
-- C_DCM1_CLKFB_BUF = false
-- C_DCM1_CLK0_BUF = false
-- C_DCM1_CLK90_BUF = false
-- C_DCM1_CLK180_BUF = false
-- C_DCM1_CLK270_BUF = false
-- C_DCM1_CLKDV_BUF = false
-- C_DCM1_CLK2X_BUF = false
-- C_DCM1_CLK2X180_BUF = false
-- C_DCM1_CLKFX_BUF = false
-- C_DCM1_CLKFX180_BUF = false
-- C_DCM1_EXT_RESET_HIGH = 1
-- C_DCM1_FAMILY = "spartan6"
-- C_DCM1_CLKIN_MODULE = NONE
-- C_DCM1_CLKIN_PORT = NONE
-- C_DCM1_CLKFB_MODULE = NONE
-- C_DCM1_CLKFB_PORT = NONE
-- C_DCM1_RST_MODULE = NONE
-- C_DCM2_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM2_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM2_DUTY_CYCLE_CORRECTION = true
-- C_DCM2_CLKIN_DIVIDE_BY_2 = false
-- C_DCM2_CLK_FEEDBACK = "1X"
-- C_DCM2_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM2_DSS_MODE = "NONE"
-- C_DCM2_STARTUP_WAIT = false
-- C_DCM2_PHASE_SHIFT = 0
-- C_DCM2_CLKFX_MULTIPLY = 4
-- C_DCM2_CLKFX_DIVIDE = 1
-- C_DCM2_CLKDV_DIVIDE = 2.0
-- C_DCM2_CLKIN_PERIOD = 41.6666666
-- C_DCM2_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM2_CLKIN_BUF = false
-- C_DCM2_CLKFB_BUF = false
-- C_DCM2_CLK0_BUF = false
-- C_DCM2_CLK90_BUF = false
-- C_DCM2_CLK180_BUF = false
-- C_DCM2_CLK270_BUF = false
-- C_DCM2_CLKDV_BUF = false
-- C_DCM2_CLK2X_BUF = false
-- C_DCM2_CLK2X180_BUF = false
-- C_DCM2_CLKFX_BUF = false
-- C_DCM2_CLKFX180_BUF = false
-- C_DCM2_EXT_RESET_HIGH = 1
-- C_DCM2_FAMILY = "spartan6"
-- C_DCM2_CLKIN_MODULE = NONE
-- C_DCM2_CLKIN_PORT = NONE
-- C_DCM2_CLKFB_MODULE = NONE
-- C_DCM2_CLKFB_PORT = NONE
-- C_DCM2_RST_MODULE = NONE
-- C_DCM3_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM3_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM3_DUTY_CYCLE_CORRECTION = true
-- C_DCM3_CLKIN_DIVIDE_BY_2 = false
-- C_DCM3_CLK_FEEDBACK = "1X"
-- C_DCM3_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM3_DSS_MODE = "NONE"
-- C_DCM3_STARTUP_WAIT = false
-- C_DCM3_PHASE_SHIFT = 0
-- C_DCM3_CLKFX_MULTIPLY = 4
-- C_DCM3_CLKFX_DIVIDE = 1
-- C_DCM3_CLKDV_DIVIDE = 2.0
-- C_DCM3_CLKIN_PERIOD = 41.6666666
-- C_DCM3_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM3_CLKIN_BUF = false
-- C_DCM3_CLKFB_BUF = false
-- C_DCM3_CLK0_BUF = false
-- C_DCM3_CLK90_BUF = false
-- C_DCM3_CLK180_BUF = false
-- C_DCM3_CLK270_BUF = false
-- C_DCM3_CLKDV_BUF = false
-- C_DCM3_CLK2X_BUF = false
-- C_DCM3_CLK2X180_BUF = false
-- C_DCM3_CLKFX_BUF = false
-- C_DCM3_CLKFX180_BUF = false
-- C_DCM3_EXT_RESET_HIGH = 1
-- C_DCM3_FAMILY = "spartan6"
-- C_DCM3_CLKIN_MODULE = NONE
-- C_DCM3_CLKIN_PORT = NONE
-- C_DCM3_CLKFB_MODULE = NONE
-- C_DCM3_CLKFB_PORT = NONE
-- C_DCM3_RST_MODULE = NONE
----------------------------------------
-- C_PLL0_BANDWIDTH = "OPTIMIZED"
-- C_PLL0_CLKFBOUT_MULT = 10
-- C_PLL0_CLKFBOUT_PHASE = 0.0
-- C_PLL0_CLKIN1_PERIOD = 10.000000
-- C_PLL0_CLKOUT0_DIVIDE = 20
-- C_PLL0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT0_PHASE = 0.0000
-- C_PLL0_CLKOUT1_DIVIDE = 1
-- C_PLL0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT1_PHASE = 0.0
-- C_PLL0_CLKOUT2_DIVIDE = 1
-- C_PLL0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT2_PHASE = 0.0
-- C_PLL0_CLKOUT3_DIVIDE = 1
-- C_PLL0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT3_PHASE = 0.0
-- C_PLL0_CLKOUT4_DIVIDE = 1
-- C_PLL0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT4_PHASE = 0.0
-- C_PLL0_CLKOUT5_DIVIDE = 1
-- C_PLL0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT5_PHASE = 0.0
-- C_PLL0_COMPENSATION = "SYSTEM_SYNCHRONOUS"
-- C_PLL0_DIVCLK_DIVIDE = 1
-- C_PLL0_REF_JITTER = 0.100
-- C_PLL0_RESET_ON_LOSS_OF_LOCK = false
-- C_PLL0_RST_DEASSERT_CLK = "CLKIN1"
-- C_PLL0_CLKOUT0_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT1_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT2_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT3_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT4_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT5_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKFBOUT_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKIN1_BUF = false
-- C_PLL0_CLKFBOUT_BUF = TRUE
-- C_PLL0_CLKOUT0_BUF = TRUE
-- C_PLL0_CLKOUT1_BUF = false
-- C_PLL0_CLKOUT2_BUF = false
-- C_PLL0_CLKOUT3_BUF = false
-- C_PLL0_CLKOUT4_BUF = false
-- C_PLL0_CLKOUT5_BUF = false
-- C_PLL0_EXT_RESET_HIGH = 1
-- C_PLL0_FAMILY = "spartan6"
-- C_PLL0_CLKIN1_MODULE = CLKGEN
-- C_PLL0_CLKIN1_PORT = CLKIN
-- C_PLL0_CLKFBIN_MODULE = PLL0
-- C_PLL0_CLKFBIN_PORT = CLKFBOUT
-- C_PLL0_RST_MODULE = CLKGEN
-- C_PLL1_BANDWIDTH = "OPTIMIZED"
-- C_PLL1_CLKFBOUT_MULT = 1
-- C_PLL1_CLKFBOUT_PHASE = 0.0
-- C_PLL1_CLKIN1_PERIOD = 0.000
-- C_PLL1_CLKOUT0_DIVIDE = 1
-- C_PLL1_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT0_PHASE = 0.0
-- C_PLL1_CLKOUT1_DIVIDE = 1
-- C_PLL1_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT1_PHASE = 0.0
-- C_PLL1_CLKOUT2_DIVIDE = 1
-- C_PLL1_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT2_PHASE = 0.0
-- C_PLL1_CLKOUT3_DIVIDE = 1
-- C_PLL1_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT3_PHASE = 0.0
-- C_PLL1_CLKOUT4_DIVIDE = 1
-- C_PLL1_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT4_PHASE = 0.0
-- C_PLL1_CLKOUT5_DIVIDE = 1
-- C_PLL1_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT5_PHASE = 0.0
-- C_PLL1_COMPENSATION = "SYSTEM_SYNCHRONOUS"
-- C_PLL1_DIVCLK_DIVIDE = 1
-- C_PLL1_REF_JITTER = 0.100
-- C_PLL1_RESET_ON_LOSS_OF_LOCK = false
-- C_PLL1_RST_DEASSERT_CLK = "CLKIN1"
-- C_PLL1_CLKOUT0_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT1_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT2_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT3_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT4_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT5_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKFBOUT_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKIN1_BUF = false
-- C_PLL1_CLKFBOUT_BUF = false
-- C_PLL1_CLKOUT0_BUF = false
-- C_PLL1_CLKOUT1_BUF = false
-- C_PLL1_CLKOUT2_BUF = false
-- C_PLL1_CLKOUT3_BUF = false
-- C_PLL1_CLKOUT4_BUF = false
-- C_PLL1_CLKOUT5_BUF = false
-- C_PLL1_EXT_RESET_HIGH = 1
-- C_PLL1_FAMILY = "spartan6"
-- C_PLL1_CLKIN1_MODULE = NONE
-- C_PLL1_CLKIN1_PORT = NONE
-- C_PLL1_CLKFBIN_MODULE = NONE
-- C_PLL1_CLKFBIN_PORT = NONE
-- C_PLL1_RST_MODULE = NONE
----------------------------------------
-- C_MMCM0_BANDWIDTH = "OPTIMIZED"
-- C_MMCM0_CLKFBOUT_MULT_F = 1.0
-- C_MMCM0_CLKFBOUT_PHASE = 0.0
-- C_MMCM0_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM0_CLKIN1_PERIOD = 0.000
-- C_MMCM0_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT0_PHASE = 0.0
-- C_MMCM0_CLKOUT1_DIVIDE = 1
-- C_MMCM0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT1_PHASE = 0.0
-- C_MMCM0_CLKOUT2_DIVIDE = 1
-- C_MMCM0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT2_PHASE = 0.0
-- C_MMCM0_CLKOUT3_DIVIDE = 1
-- C_MMCM0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT3_PHASE = 0.0
-- C_MMCM0_CLKOUT4_DIVIDE = 1
-- C_MMCM0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT4_PHASE = 0.0
-- C_MMCM0_CLKOUT4_CASCADE = false
-- C_MMCM0_CLKOUT5_DIVIDE = 1
-- C_MMCM0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT5_PHASE = 0.0
-- C_MMCM0_CLKOUT6_DIVIDE = 1
-- C_MMCM0_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT6_PHASE = 0.0
-- C_MMCM0_CLKOUT0_USE_FINE_PS = false
-- C_MMCM0_CLKOUT1_USE_FINE_PS = false
-- C_MMCM0_CLKOUT2_USE_FINE_PS = false
-- C_MMCM0_CLKOUT3_USE_FINE_PS = false
-- C_MMCM0_CLKOUT4_USE_FINE_PS = false
-- C_MMCM0_CLKOUT5_USE_FINE_PS = false
-- C_MMCM0_CLKOUT6_USE_FINE_PS = false
-- C_MMCM0_COMPENSATION = "ZHOLD"
-- C_MMCM0_DIVCLK_DIVIDE = 1
-- C_MMCM0_REF_JITTER1 = 0.010
-- C_MMCM0_CLKIN1_BUF = false
-- C_MMCM0_CLKFBOUT_BUF = false
-- C_MMCM0_CLKOUT0_BUF = false
-- C_MMCM0_CLKOUT1_BUF = false
-- C_MMCM0_CLKOUT2_BUF = false
-- C_MMCM0_CLKOUT3_BUF = false
-- C_MMCM0_CLKOUT4_BUF = false
-- C_MMCM0_CLKOUT5_BUF = false
-- C_MMCM0_CLKOUT6_BUF = false
-- C_MMCM0_CLOCK_HOLD = false
-- C_MMCM0_STARTUP_WAIT = false
-- C_MMCM0_EXT_RESET_HIGH = 1
-- C_MMCM0_FAMILY = "spartan6"
-- C_MMCM0_CLKIN1_MODULE = NONE
-- C_MMCM0_CLKIN1_PORT = NONE
-- C_MMCM0_CLKFBIN_MODULE = NONE
-- C_MMCM0_CLKFBIN_PORT = NONE
-- C_MMCM0_RST_MODULE = NONE
-- C_MMCM1_BANDWIDTH = "OPTIMIZED"
-- C_MMCM1_CLKFBOUT_MULT_F = 1.0
-- C_MMCM1_CLKFBOUT_PHASE = 0.0
-- C_MMCM1_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM1_CLKIN1_PERIOD = 0.000
-- C_MMCM1_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM1_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT0_PHASE = 0.0
-- C_MMCM1_CLKOUT1_DIVIDE = 1
-- C_MMCM1_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT1_PHASE = 0.0
-- C_MMCM1_CLKOUT2_DIVIDE = 1
-- C_MMCM1_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT2_PHASE = 0.0
-- C_MMCM1_CLKOUT3_DIVIDE = 1
-- C_MMCM1_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT3_PHASE = 0.0
-- C_MMCM1_CLKOUT4_DIVIDE = 1
-- C_MMCM1_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT4_PHASE = 0.0
-- C_MMCM1_CLKOUT4_CASCADE = false
-- C_MMCM1_CLKOUT5_DIVIDE = 1
-- C_MMCM1_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT5_PHASE = 0.0
-- C_MMCM1_CLKOUT6_DIVIDE = 1
-- C_MMCM1_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT6_PHASE = 0.0
-- C_MMCM1_CLKOUT0_USE_FINE_PS = false
-- C_MMCM1_CLKOUT1_USE_FINE_PS = false
-- C_MMCM1_CLKOUT2_USE_FINE_PS = false
-- C_MMCM1_CLKOUT3_USE_FINE_PS = false
-- C_MMCM1_CLKOUT4_USE_FINE_PS = false
-- C_MMCM1_CLKOUT5_USE_FINE_PS = false
-- C_MMCM1_CLKOUT6_USE_FINE_PS = false
-- C_MMCM1_COMPENSATION = "ZHOLD"
-- C_MMCM1_DIVCLK_DIVIDE = 1
-- C_MMCM1_REF_JITTER1 = 0.010
-- C_MMCM1_CLKIN1_BUF = false
-- C_MMCM1_CLKFBOUT_BUF = false
-- C_MMCM1_CLKOUT0_BUF = false
-- C_MMCM1_CLKOUT1_BUF = false
-- C_MMCM1_CLKOUT2_BUF = false
-- C_MMCM1_CLKOUT3_BUF = false
-- C_MMCM1_CLKOUT4_BUF = false
-- C_MMCM1_CLKOUT5_BUF = false
-- C_MMCM1_CLKOUT6_BUF = false
-- C_MMCM1_CLOCK_HOLD = false
-- C_MMCM1_STARTUP_WAIT = false
-- C_MMCM1_EXT_RESET_HIGH = 1
-- C_MMCM1_FAMILY = "spartan6"
-- C_MMCM1_CLKIN1_MODULE = NONE
-- C_MMCM1_CLKIN1_PORT = NONE
-- C_MMCM1_CLKFBIN_MODULE = NONE
-- C_MMCM1_CLKFBIN_PORT = NONE
-- C_MMCM1_RST_MODULE = NONE
-- C_MMCM2_BANDWIDTH = "OPTIMIZED"
-- C_MMCM2_CLKFBOUT_MULT_F = 1.0
-- C_MMCM2_CLKFBOUT_PHASE = 0.0
-- C_MMCM2_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM2_CLKIN1_PERIOD = 0.000
-- C_MMCM2_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM2_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT0_PHASE = 0.0
-- C_MMCM2_CLKOUT1_DIVIDE = 1
-- C_MMCM2_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT1_PHASE = 0.0
-- C_MMCM2_CLKOUT2_DIVIDE = 1
-- C_MMCM2_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT2_PHASE = 0.0
-- C_MMCM2_CLKOUT3_DIVIDE = 1
-- C_MMCM2_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT3_PHASE = 0.0
-- C_MMCM2_CLKOUT4_DIVIDE = 1
-- C_MMCM2_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT4_PHASE = 0.0
-- C_MMCM2_CLKOUT4_CASCADE = false
-- C_MMCM2_CLKOUT5_DIVIDE = 1
-- C_MMCM2_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT5_PHASE = 0.0
-- C_MMCM2_CLKOUT6_DIVIDE = 1
-- C_MMCM2_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT6_PHASE = 0.0
-- C_MMCM2_CLKOUT0_USE_FINE_PS = false
-- C_MMCM2_CLKOUT1_USE_FINE_PS = false
-- C_MMCM2_CLKOUT2_USE_FINE_PS = false
-- C_MMCM2_CLKOUT3_USE_FINE_PS = false
-- C_MMCM2_CLKOUT4_USE_FINE_PS = false
-- C_MMCM2_CLKOUT5_USE_FINE_PS = false
-- C_MMCM2_CLKOUT6_USE_FINE_PS = false
-- C_MMCM2_COMPENSATION = "ZHOLD"
-- C_MMCM2_DIVCLK_DIVIDE = 1
-- C_MMCM2_REF_JITTER1 = 0.010
-- C_MMCM2_CLKIN1_BUF = false
-- C_MMCM2_CLKFBOUT_BUF = false
-- C_MMCM2_CLKOUT0_BUF = false
-- C_MMCM2_CLKOUT1_BUF = false
-- C_MMCM2_CLKOUT2_BUF = false
-- C_MMCM2_CLKOUT3_BUF = false
-- C_MMCM2_CLKOUT4_BUF = false
-- C_MMCM2_CLKOUT5_BUF = false
-- C_MMCM2_CLKOUT6_BUF = false
-- C_MMCM2_CLOCK_HOLD = false
-- C_MMCM2_STARTUP_WAIT = false
-- C_MMCM2_EXT_RESET_HIGH = 1
-- C_MMCM2_FAMILY = "spartan6"
-- C_MMCM2_CLKIN1_MODULE = NONE
-- C_MMCM2_CLKIN1_PORT = NONE
-- C_MMCM2_CLKFBIN_MODULE = NONE
-- C_MMCM2_CLKFBIN_PORT = NONE
-- C_MMCM2_RST_MODULE = NONE
-- C_MMCM3_BANDWIDTH = "OPTIMIZED"
-- C_MMCM3_CLKFBOUT_MULT_F = 1.0
-- C_MMCM3_CLKFBOUT_PHASE = 0.0
-- C_MMCM3_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM3_CLKIN1_PERIOD = 0.000
-- C_MMCM3_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM3_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT0_PHASE = 0.0
-- C_MMCM3_CLKOUT1_DIVIDE = 1
-- C_MMCM3_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT1_PHASE = 0.0
-- C_MMCM3_CLKOUT2_DIVIDE = 1
-- C_MMCM3_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT2_PHASE = 0.0
-- C_MMCM3_CLKOUT3_DIVIDE = 1
-- C_MMCM3_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT3_PHASE = 0.0
-- C_MMCM3_CLKOUT4_DIVIDE = 1
-- C_MMCM3_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT4_PHASE = 0.0
-- C_MMCM3_CLKOUT4_CASCADE = false
-- C_MMCM3_CLKOUT5_DIVIDE = 1
-- C_MMCM3_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT5_PHASE = 0.0
-- C_MMCM3_CLKOUT6_DIVIDE = 1
-- C_MMCM3_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT6_PHASE = 0.0
-- C_MMCM3_CLKOUT0_USE_FINE_PS = false
-- C_MMCM3_CLKOUT1_USE_FINE_PS = false
-- C_MMCM3_CLKOUT2_USE_FINE_PS = false
-- C_MMCM3_CLKOUT3_USE_FINE_PS = false
-- C_MMCM3_CLKOUT4_USE_FINE_PS = false
-- C_MMCM3_CLKOUT5_USE_FINE_PS = false
-- C_MMCM3_CLKOUT6_USE_FINE_PS = false
-- C_MMCM3_COMPENSATION = "ZHOLD"
-- C_MMCM3_DIVCLK_DIVIDE = 1
-- C_MMCM3_REF_JITTER1 = 0.010
-- C_MMCM3_CLKIN1_BUF = false
-- C_MMCM3_CLKFBOUT_BUF = false
-- C_MMCM3_CLKOUT0_BUF = false
-- C_MMCM3_CLKOUT1_BUF = false
-- C_MMCM3_CLKOUT2_BUF = false
-- C_MMCM3_CLKOUT3_BUF = false
-- C_MMCM3_CLKOUT4_BUF = false
-- C_MMCM3_CLKOUT5_BUF = false
-- C_MMCM3_CLKOUT6_BUF = false
-- C_MMCM3_CLOCK_HOLD = false
-- C_MMCM3_STARTUP_WAIT = false
-- C_MMCM3_EXT_RESET_HIGH = 1
-- C_MMCM3_FAMILY = "spartan6"
-- C_MMCM3_CLKIN1_MODULE = NONE
-- C_MMCM3_CLKIN1_PORT = NONE
-- C_MMCM3_CLKFBIN_MODULE = NONE
-- C_MMCM3_CLKFBIN_PORT = NONE
-- C_MMCM3_RST_MODULE = NONE
----------------------------------------
-- C_PLLE0_BANDWIDTH = "OPTIMIZED"
-- C_PLLE0_CLKFBOUT_MULT = 1
-- C_PLLE0_CLKFBOUT_PHASE = 0.0
-- C_PLLE0_CLKIN1_PERIOD = 0.000
-- C_PLLE0_CLKOUT0_DIVIDE = 1
-- C_PLLE0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT0_PHASE = 0.0
-- C_PLLE0_CLKOUT1_DIVIDE = 1
-- C_PLLE0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT1_PHASE = 0.0
-- C_PLLE0_CLKOUT2_DIVIDE = 1
-- C_PLLE0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT2_PHASE = 0.0
-- C_PLLE0_CLKOUT3_DIVIDE = 1
-- C_PLLE0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT3_PHASE = 0.0
-- C_PLLE0_CLKOUT4_DIVIDE = 1
-- C_PLLE0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT4_PHASE = 0.0
-- C_PLLE0_CLKOUT5_DIVIDE = 1
-- C_PLLE0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT5_PHASE = 0.0
-- C_PLLE0_COMPENSATION = "ZHOLD"
-- C_PLLE0_DIVCLK_DIVIDE = 1
-- C_PLLE0_REF_JITTER1 = 0.010
-- C_PLLE0_CLKIN1_BUF = false
-- C_PLLE0_CLKFBOUT_BUF = false
-- C_PLLE0_CLKOUT0_BUF = false
-- C_PLLE0_CLKOUT1_BUF = false
-- C_PLLE0_CLKOUT2_BUF = false
-- C_PLLE0_CLKOUT3_BUF = false
-- C_PLLE0_CLKOUT4_BUF = false
-- C_PLLE0_CLKOUT5_BUF = false
-- C_PLLE0_STARTUP_WAIT = "false"
-- C_PLLE0_EXT_RESET_HIGH = 1
-- C_PLLE0_FAMILY = "virtex7"
-- C_PLLE0_CLKIN1_MODULE = NONE
-- C_PLLE0_CLKIN1_PORT = NONE
-- C_PLLE0_CLKFBIN_MODULE = NONE
-- C_PLLE0_CLKFBIN_PORT = NONE
-- C_PLLE0_RST_MODULE = NONE
----------------------------------------
|
-------------------------------------------------------------------------------
-- system_ilmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_10_c;
use lmb_bram_if_cntlr_v3_10_c.all;
entity system_ilmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to 31);
LMB1_WriteDBus : in std_logic_vector(0 to 31);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to 3);
Sl1_DBus : out std_logic_vector(0 to 31);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to 31);
LMB2_WriteDBus : in std_logic_vector(0 to 31);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to 3);
Sl2_DBus : out std_logic_vector(0 to 31);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to 31);
LMB3_WriteDBus : in std_logic_vector(0 to 31);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to 3);
Sl3_DBus : out std_logic_vector(0 to 31);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_ilmb_cntlr_wrapper : entity is "lmb_bram_if_cntlr_v3_10_c";
end system_ilmb_cntlr_wrapper;
architecture STRUCTURE of system_ilmb_cntlr_wrapper is
component lmb_bram_if_cntlr is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_FAMILY : string;
C_MASK : std_logic_vector(0 to 31);
C_MASK1 : std_logic_vector(0 to 31);
C_MASK2 : std_logic_vector(0 to 31);
C_MASK3 : std_logic_vector(0 to 31);
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_ECC : integer;
C_INTERCONNECT : integer;
C_FAULT_INJECT : integer;
C_CE_FAILING_REGISTERS : integer;
C_UE_FAILING_REGISTERS : integer;
C_ECC_STATUS_REGISTERS : integer;
C_ECC_ONOFF_REGISTER : integer;
C_ECC_ONOFF_RESET_VALUE : integer;
C_CE_COUNTER_WIDTH : integer;
C_WRITE_ACCESS : integer;
C_NUM_LMB : integer;
C_SPLB_CTRL_BASEADDR : std_logic_vector;
C_SPLB_CTRL_HIGHADDR : std_logic_vector;
C_SPLB_CTRL_AWIDTH : INTEGER;
C_SPLB_CTRL_DWIDTH : INTEGER;
C_SPLB_CTRL_P2P : INTEGER;
C_SPLB_CTRL_MID_WIDTH : INTEGER;
C_SPLB_CTRL_NUM_MASTERS : INTEGER;
C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER;
C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER;
C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1);
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1));
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1));
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
begin
ilmb_cntlr : lmb_bram_if_cntlr
generic map (
C_BASEADDR => X"00000000",
C_HIGHADDR => X"00000fff",
C_FAMILY => "virtex5",
C_MASK => X"80000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_NUM_LMB => 1,
C_SPLB_CTRL_BASEADDR => X"FFFFFFFF",
C_SPLB_CTRL_HIGHADDR => X"00000000",
C_SPLB_CTRL_AWIDTH => 32,
C_SPLB_CTRL_DWIDTH => 32,
C_SPLB_CTRL_P2P => 0,
C_SPLB_CTRL_MID_WIDTH => 1,
C_SPLB_CTRL_NUM_MASTERS => 1,
C_SPLB_CTRL_SUPPORT_BURSTS => 0,
C_SPLB_CTRL_NATIVE_DWIDTH => 32,
C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF",
C_S_AXI_CTRL_HIGHADDR => X"00000000",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
Interrupt => Interrupt,
UE => UE,
CE => CE,
SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus,
SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid,
SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID,
SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW,
SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE,
SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size,
SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type,
SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus,
SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck,
SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize,
SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait,
SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate,
SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck,
SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp,
SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus,
SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck,
SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp,
SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy,
SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr,
SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr,
SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus,
SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid,
SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim,
SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim,
SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort,
SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock,
SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize,
SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr,
SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst,
SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst,
SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq,
SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq,
SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri,
SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri,
SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri,
SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute,
SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm,
SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr,
SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm,
SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ,
S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK,
S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA,
S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY
);
end architecture STRUCTURE;
|
entity case3 is
end entity;
architecture test of case3 is
signal s : bit_vector(1 to 3);
signal t : bit;
begin
p1: process (s) is
begin
case s is
when "100" =>
t <= '1';
when "101" =>
t <= '0';
when "100" => -- Error
t <= '1';
when others =>
null;
end case;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity SymbolMultiplier is
port( uncoded_a, uncoded_b:
in std_logic_vector(2 downto 0);
uncoded_multab: out std_logic_vector(2 downto 0)
);
end SymbolMultiplier;
architecture Behavioral of SymbolMultiplier is
component BinaryAdderSubtractor is
port( a,b: in std_logic_vector(3 downto 0);
fnc: in std_logic;
s_or_d: out std_logic_vector(3 downto 0)
);
end component;
component Mux6x3 is
Port ( a : in std_logic_vector(2 downto 0) ;
b : in std_logic_vector(2 downto 0) ;
s : in std_logic ;
f : out std_logic_vector(2 downto 0));
end component ;
component SymbolPowerDecoder is
Port ( n1 : in std_logic_vector(2 downto 0);
n1c : out std_logic_vector(2 downto 0));
end component;
component SymbolPowerEncoder is
Port ( n1 : in std_logic_vector(2 downto 0);
n1c : out std_logic_vector(2 downto 0));
end component;
signal iszero: std_logic;
signal zerov: std_logic_vector(2 downto 0);
signal s_or_d: std_logic_vector(3 downto 0);
signal a: std_logic_vector(2 downto 0);
signal b: std_logic_vector(2 downto 0);
signal uncoded_multab_poly: std_logic_vector(2 downto 0);
signal multab: std_logic_vector(2 downto 0);
signal sa: std_logic_vector(3 downto 0);
signal sb: std_logic_vector(3 downto 0);
signal tt: std_logic;
signal t7: std_logic_vector(3 downto 0);
signal tres: std_logic_vector(3 downto 0);
signal sa2: std_logic_vector(2 downto 0);
signal sb2: std_logic_vector(2 downto 0);
begin
iszero <= (uncoded_a(0) or uncoded_a(1) or uncoded_a(2))
and (uncoded_b(0) or uncoded_b(1) or uncoded_b(2));
encode1: SymbolPowerEncoder port map(uncoded_a, a);
encode2: SymbolPowerEncoder port map(uncoded_b, b);
sa(0) <= a(0);
sa(1) <= a(1);
sa(2) <= a(2);
sa(3) <= '0';
sb(0) <= b(0);
sb(1) <= b(1);
sb(2) <= b(2);
sb(3) <= '0';
fa0: BinaryAdderSubtractor port map(sa, sb, '0', s_or_d);
tt <= s_or_d(3) or (s_or_d(0) and s_or_d(1) and s_or_d(2));
t7(0) <= '1';
t7(1) <= '1';
t7(2) <= '1';
t7(3) <= '0';
fa1: BinaryAdderSubtractor port map(s_or_d, t7,'1',tres);
sa2(0) <= tres(0);
sa2(1) <= tres(1);
sa2(2) <= tres(2);
sb2(0) <= s_or_d(0);
sb2(1) <= s_or_d(1);
sb2(2) <= s_or_d(2);
mux1: Mux6x3 port map(sa2, sb2, tt, multab);
decode1: SymbolPowerDecoder port map(multab, uncoded_multab_poly);
zerov(0) <= '0';
zerov(1) <= '0';
zerov(2) <= '0';
mux2: Mux6x3 port map(uncoded_multab_poly, zerov, iszero, uncoded_multab);
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc249.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00249ent IS
END c03s01b02x00p04n01i00249ent;
ARCHITECTURE c03s01b02x00p04n01i00249arch OF c03s01b02x00p04n01i00249ent IS
type I5 is range B"000" to B"111"; -- Failure_here
-- SEMANTIC ERROR: RANGE CONSTRAINT IN INTEGER TYPE DEFINITION
-- MUST BE OF INTEGER TYPE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p04n01i00249 - Range constraint must be an integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00249arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc249.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00249ent IS
END c03s01b02x00p04n01i00249ent;
ARCHITECTURE c03s01b02x00p04n01i00249arch OF c03s01b02x00p04n01i00249ent IS
type I5 is range B"000" to B"111"; -- Failure_here
-- SEMANTIC ERROR: RANGE CONSTRAINT IN INTEGER TYPE DEFINITION
-- MUST BE OF INTEGER TYPE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p04n01i00249 - Range constraint must be an integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00249arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc249.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00249ent IS
END c03s01b02x00p04n01i00249ent;
ARCHITECTURE c03s01b02x00p04n01i00249arch OF c03s01b02x00p04n01i00249ent IS
type I5 is range B"000" to B"111"; -- Failure_here
-- SEMANTIC ERROR: RANGE CONSTRAINT IN INTEGER TYPE DEFINITION
-- MUST BE OF INTEGER TYPE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p04n01i00249 - Range constraint must be an integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00249arch;
|
-- $Id: sys_w11a_br_arty.vhd 1211 2021-08-28 11:20:34Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_br_arty - syn
-- Description: w11a test design for arty
--
-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce
-- bplib/bpgen/bp_rs232_2line_iob
-- vlib/rlink/rlink_sp2c
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- w11a/pdp11_bram_memctl
-- vlib/rlink/ioleds_sp1c
-- pdp11_hio70_arty
-- bplib/bpgen/bp_swibtnled
-- bplib/bpgen/rgbdrv_3x4mux
-- bplib/sysmon/sysmonx_rbus_arty
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_3
--
-- Test bench: tb/tb_sys_w11a_br_arty
--
-- Target Devices: generic
-- Tool versions: viv 2015.4-2018.3; ghdl 0.33-0.35
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2019-05-19 1150 2017.2 xc7a35t-1 2829 6226 273 48.0 8150 +dz11
-- 2019-02-02 1108 2018.3 xc7a35t-1 2571 5781 170 47.5 1780
-- 2019-02-02 1108 2017.2 xc7a35t-1 2560 5496 170 47.5 1722
-- 2018-10-13 1055 2017.2 xc7a35t-1 2560 5499 170 47.5 1699 +dmpcnt
-- 2018-09-15 1045 2017.2 xc7a35t-1 2337 5188 138 47.5 1611 +KW11P
-- 2018-08-11 1038 2018.2 xc7a35t-1 2283 5190 138 47.5 1602
-- 2018-08-11 1038 2018.1 xc7a35t-1 2283 5193 138 47.5 1616
-- 2018-08-11 1038 2017.4 xc7a35t-1 2278 5130 138 47.5 1541
-- 2018-08-11 1038 2017.2 xc7a35t-1 2275 5104 138 47.5 1581
-- 2018-08-11 1038 2017.1 xc7a35t-1 2275 5104 138 47.5 1581
-- 2017-04-16 881 2016.4 xc7a35t-1 2275 5104 138 47.5 1611 +DEUNA
-- 2017-01-29 846 2016.4 xc7a35t-1 2225 5100 138 47.5 1555 +int24
-- 2016-05-26 768 2016.1 xc7a35t-1 2226 5080 138 47.5 1569 fsm+dsm=0
-- 2016-03-29 756 2015.4 xc7a35t-1 2106 4428 138 48.5 1397 serport2
-- 2016-03-27 753 2015.4 xc7a35t-1 1995 4298 138 48.5 1349 meminf
-- 2016-03-13 742 2015.4 xc7a35t-1 1996 4309 162 48.5 1333 +XADC
-- 2016-02-27 737 2015.4 xc7a35t-1 1952 4246 162 48.5 1316
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1086 1.4 use s7_cmt_1ce1ce
-- 2018-10-13 1055 1.3 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2016-04-02 758 1.2.1 add rbd_usracc (bitfile+jtag timestamp access)
-- 2016-03-28 755 1.2 use serport_2clock2
-- 2016-03-19 748 1.1.2 define rlink SYSID
-- 2016-03-13 742 1.1.1 add sysmon_rbus
-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config
-- 2016-02-27 736 1.0 Initial version (derived from sys_w11a_b3)
------------------------------------------------------------------------------
--
-- w11a test design for arty (using BRAM as memory)
-- w11a + rlink + serport
--
-- Usage of Arty switches, Buttons, LEDs
--
-- SWI(3:0): determine what is displayed in the LEDs and RGBLEDs
-- 00xy LED shows IO
-- y=1 enables CPU activities on RGB_G,RGB_R
-- x=1 enables MEM activities on RGB_B
-- 0100 LED+RGB give DR emulation 'light show'
-- 1xyy LED+RGB show low (x=0) or high (x=1) byte of
-- yy = 00: abclkdiv & abclkdiv_f
-- 01: PC
-- 10: DISPREG
-- 11: DR emulation
-- LED shows upper, RGB low nibble of the byte selected by x
--
-- LED and RGB assignment for SWI=00xy
-- LED IO activity
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
-- RGB_G CPU busy (active cpugo=1, enabled with SWI(0))
-- (3) kernel mode, non-wait, pri>0
-- (2) kernel mode, non-wait, pri=0
-- (1) supervisor mode
-- (0) user mode
-- RGB_R CPU rust (active cpugo=0, enabled with SWI(0))
-- (3:0) cpurust code
-- RGB_B MEM/cmd busy (enabled with SWI(1))
-- (3) MEM_ACT_W
-- (2) MEM_ACT_R
-- (1) cmdbusy (all rlink access, mostly rdma)
-- (0) not cpugo
--
-- LED and RGB assignment for SWI=0100 (DR emulation)
-- LED DR(15:12)
-- RGB_B DR(11:08)
-- RGB_G DR( 7:04)
-- RGB_R DR( 3:00)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.sysmonrbuslib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_br_arty is -- top level
-- implements arty_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- arty switches
I_BTN : in slv4; -- arty buttons
O_LED : out slv4; -- arty leds
O_RGBLED0 : out slv3; -- arty rgb-led 0
O_RGBLED1 : out slv3; -- arty rgb-led 1
O_RGBLED2 : out slv3; -- arty rgb-led 2
O_RGBLED3 : out slv3; -- arty rgb-led 3
A_VPWRN : in slv4; -- arty pwrmon (neg)
A_VPWRP : in slv4 -- arty pwrmon (pos)
);
end sys_w11a_br_arty;
architecture syn of sys_w11a_br_arty is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
signal IOLEDS : slv4 := (others=>'0');
signal SWI : slv4 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv4 := (others=>'0');
signal RGB_R : slv4 := (others=>'0');
signal RGB_G : slv4 := (others=>'0');
signal RGB_B : slv4 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"07"; -- arty
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000)
port map (
CLKIN => I_CLK100,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
LOCKED => open
);
IOB_RS232 : bp_rs232_2line_iob -- serport iob ----------------------
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp2c -- rlink for serport -----------------
generic map (
BTOWIDTH => 7, -- 128 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '1', -- XON statically enabled !
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
BRAM_CTL: pdp11_bram_memctl -- memory controller -----------------
generic map (
MAWIDTH => sys_conf_memctl_mawidth,
NBLOCK => sys_conf_memctl_nblock)
port map (
CLK => CLK,
RESET => GRESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO
);
LED_IO : ioleds_sp1c -- hio leds from serport -------------
port map (
SER_MONI => SER_MONI,
IOLEDS => IOLEDS
);
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : entity work.pdp11_hio70_arty -- hio from sys70 --------------------
port map (
CLK => CLK,
MODE => SWI,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
DISPREG => DISPREG,
IOLEDS => IOLEDS,
ABCLKDIV => ABCLKDIV,
LED => LED,
RGB_R => RGB_R,
RGB_G => RGB_G,
RGB_B => RGB_B
);
HIO : bp_swibtnled
generic map (
SWIDTH => I_SWI'length,
BWIDTH => I_BTN'length,
LWIDTH => O_LED'length,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
HIORGB : rgbdrv_3x4mux
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
DATR => RGB_R,
DATG => RGB_G,
DATB => RGB_B,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_RGBLED2 => O_RGBLED2,
O_RGBLED3 => O_RGBLED3
);
SMRB : if sys_conf_rbd_sysmon generate
I0: sysmonx_rbus_arty
generic map ( -- use default INIT_ (LP: Vccint=0.95)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open,
VPWRN => A_VPWRN,
VPWRP => A_VPWRP
);
end generate SMRB;
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_SYSMON,
RB_SRES_3 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
end syn;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1405.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p07n01i01405ent IS
END c08s05b00x00p07n01i01405ent;
ARCHITECTURE c08s05b00x00p07n01i01405arch OF c08s05b00x00p07n01i01405ent IS
BEGIN
TESTING: PROCESS
variable S1 : BIT;
variable T1 : BIT;
variable T2 : BIT;
variable B2 : BIT_VECTOR(0 to 2) := B"111";
BEGIN
(S1, T1, T2) := B2;
assert NOT( (S1='1') and (T1='1') and (T2='1') )
report "***PASSED TEST: c08s05b00x00p07n01i01405"
severity NOTE;
assert ( (S1='1') and (T1='1') and (T2='1') )
report "***FAILED TEST: c08s05b00x00p07n01i01405 - Subtypes of the subelements of the right-hand side and that of the names in the aggregate should match"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p07n01i01405arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1405.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p07n01i01405ent IS
END c08s05b00x00p07n01i01405ent;
ARCHITECTURE c08s05b00x00p07n01i01405arch OF c08s05b00x00p07n01i01405ent IS
BEGIN
TESTING: PROCESS
variable S1 : BIT;
variable T1 : BIT;
variable T2 : BIT;
variable B2 : BIT_VECTOR(0 to 2) := B"111";
BEGIN
(S1, T1, T2) := B2;
assert NOT( (S1='1') and (T1='1') and (T2='1') )
report "***PASSED TEST: c08s05b00x00p07n01i01405"
severity NOTE;
assert ( (S1='1') and (T1='1') and (T2='1') )
report "***FAILED TEST: c08s05b00x00p07n01i01405 - Subtypes of the subelements of the right-hand side and that of the names in the aggregate should match"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p07n01i01405arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1405.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p07n01i01405ent IS
END c08s05b00x00p07n01i01405ent;
ARCHITECTURE c08s05b00x00p07n01i01405arch OF c08s05b00x00p07n01i01405ent IS
BEGIN
TESTING: PROCESS
variable S1 : BIT;
variable T1 : BIT;
variable T2 : BIT;
variable B2 : BIT_VECTOR(0 to 2) := B"111";
BEGIN
(S1, T1, T2) := B2;
assert NOT( (S1='1') and (T1='1') and (T2='1') )
report "***PASSED TEST: c08s05b00x00p07n01i01405"
severity NOTE;
assert ( (S1='1') and (T1='1') and (T2='1') )
report "***FAILED TEST: c08s05b00x00p07n01i01405 - Subtypes of the subelements of the right-hand side and that of the names in the aggregate should match"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p07n01i01405arch;
|
library verilog;
use verilog.vl_types.all;
entity sample_iterator_get_offset is
generic(
ap_const_logic_1: vl_logic := Hi1;
ap_const_logic_0: vl_logic := Hi0;
ap_ST_pp0_stg0_fsm_0: vl_logic := Hi0;
ap_const_lv32_1 : integer := 1;
ap_const_lv32_30: integer := 48;
ap_const_lv32_37: integer := 55;
ap_const_lv56_0 : vl_logic_vector(0 to 55) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
ap_true : vl_logic := Hi1
);
port(
ap_clk : in vl_logic;
ap_rst : in vl_logic;
ap_start : in vl_logic;
ap_done : out vl_logic;
ap_idle : out vl_logic;
ap_ready : out vl_logic;
indices_req_din : out vl_logic;
indices_req_full_n: in vl_logic;
indices_req_write: out vl_logic;
indices_rsp_empty_n: in vl_logic;
indices_rsp_read: out vl_logic;
indices_address : out vl_logic_vector(31 downto 0);
indices_datain : in vl_logic_vector(55 downto 0);
indices_dataout : out vl_logic_vector(55 downto 0);
indices_size : out vl_logic_vector(31 downto 0);
ap_ce : in vl_logic;
i_index : in vl_logic_vector(15 downto 0);
i_sample : in vl_logic_vector(15 downto 0);
sample_buffer_size: in vl_logic_vector(31 downto 0);
sample_length : in vl_logic_vector(15 downto 0);
ap_return : out vl_logic_vector(31 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of ap_const_logic_1 : constant is 1;
attribute mti_svvh_generic_type of ap_const_logic_0 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_pp0_stg0_fsm_0 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv32_1 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv32_30 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv32_37 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv56_0 : constant is 1;
attribute mti_svvh_generic_type of ap_true : constant is 1;
end sample_iterator_get_offset;
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of a real_const_mult an its content. It exists
/ to circumvent the impossibility of reading the attributes of an unconstrained port signal inside
/ the port declaration of an entity. (so as to declare the output's size, which depends on the
/ input's size).
/ Additionally, the generics' consistency and correctness is checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity real_const_mult_u is
generic(
SPEED_opt : T_speed := t_exc; --exception: value not set
ROUND_STYLE_opt : T_round_style := fixed_truncate; --default
ROUND_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
MAX_ERROR_PCT_opt : real_exc := real'low; --exception: value not set
MULTIPLICANDS : real_v --compulsory
);
port(
input : in u_ufixed;
clk : in std_ulogic;
valid_input : in std_ulogic;
output : out u_ufixed_v;
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture real_const_mult_u_1 of real_const_mult_u is
constant CHECKS : integer := real_const_mult_CHECKS(input'high,
input'low,
true, --UNSIGNED_2COMP_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
MULTIPLICANDS);
constant MULTIPLICANDS_adjusted : real_v(1 to MULTIPLICANDS'length) := MULTIPLICANDS;
/*================================================================================================*/
/*================================================================================================*/
begin
real_const_mult_core_u_1:
entity work.real_const_mult_core_u
generic map(
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
CONSTANTS => MULTIPLICANDS_adjusted,
input_high => input'high,
input_low => input'low
)
port map(
input => input,
clk => clk,
valid_input => valid_input,
output => output,
valid_output => valid_output
);
end architecture; |
-------------------------------------------------------------------------------
-- Title : Testbench for design "bldc_motor_module"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.motor_control_pkg.all;
-------------------------------------------------------------------------------
entity bldc_motor_module_tb is
end bldc_motor_module_tb;
-------------------------------------------------------------------------------
architecture tb of bldc_motor_module_tb is
-- component generics
constant BASE_ADDRESS : positive := 16#0100#;
constant WIDTH : positive := 8;
constant PRESCALER : positive := 2;
-- component ports
signal driver_stage : bldc_driver_stage_type;
signal hall : hall_sensor_type := ('0', '0', '0');
signal break : std_logic := '0';
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal clk : std_logic := '0';
begin
-- component instantiation
DUT : bldc_motor_module
generic map (
BASE_ADDRESS => BASE_ADDRESS,
WIDTH => WIDTH,
PRESCALER => PRESCALER)
port map (
driver_stage_p => driver_stage,
hall_p => hall,
break_p => break,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
bus_waveform : process
begin
wait for 100 ns;
-- wrong address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0020", bus_i.addr'length)));
bus_i.data <= x"0123";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 30 US;
-- correct address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"00f0";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 30 US;
-- wrong address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0110", bus_i.addr'length)));
bus_i.data <= x"0123";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 630 US;
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"000f";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 100 US;
-- Disable PWM via Shutdown
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"800f";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
end process;
hall_sensor_waveform : process
begin
wait for 50 US;
hall <= ('1', '0', '1');
wait for 100 US;
hall <= ('1', '0', '0');
wait for 100 US;
hall <= ('1', '1', '0');
wait for 100 US;
hall <= ('0', '1', '0');
wait for 100 US;
hall <= ('0', '1', '1');
wait for 100 US;
hall <= ('0', '0', '1');
wait for 100 US;
hall <= ('1', '0', '1');
wait for 100 US;
hall <= ('1', '0', '0');
wait for 100 US;
hall <= ('1', '1', '0');
wait for 100 US;
hall <= ('0', '1', '0');
wait for 100 US;
hall <= ('0', '1', '1');
wait for 100 US;
hall <= ('0', '0', '1');
end process;
-- Test break signal
process
begin
wait for 220 US;
break <= '1';
wait for 50 US;
break <= '0';
end process;
end tb;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "bldc_motor_module"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.motor_control_pkg.all;
-------------------------------------------------------------------------------
entity bldc_motor_module_tb is
end bldc_motor_module_tb;
-------------------------------------------------------------------------------
architecture tb of bldc_motor_module_tb is
-- component generics
constant BASE_ADDRESS : positive := 16#0100#;
constant WIDTH : positive := 8;
constant PRESCALER : positive := 2;
-- component ports
signal driver_stage : bldc_driver_stage_type;
signal hall : hall_sensor_type := ('0', '0', '0');
signal break : std_logic := '0';
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal clk : std_logic := '0';
begin
-- component instantiation
DUT : bldc_motor_module
generic map (
BASE_ADDRESS => BASE_ADDRESS,
WIDTH => WIDTH,
PRESCALER => PRESCALER)
port map (
driver_stage_p => driver_stage,
hall_p => hall,
break_p => break,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
bus_waveform : process
begin
wait for 100 ns;
-- wrong address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0020", bus_i.addr'length)));
bus_i.data <= x"0123";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 30 US;
-- correct address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"00f0";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 30 US;
-- wrong address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0110", bus_i.addr'length)));
bus_i.data <= x"0123";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 630 US;
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"000f";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 100 US;
-- Disable PWM via Shutdown
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"800f";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
end process;
hall_sensor_waveform : process
begin
wait for 50 US;
hall <= ('1', '0', '1');
wait for 100 US;
hall <= ('1', '0', '0');
wait for 100 US;
hall <= ('1', '1', '0');
wait for 100 US;
hall <= ('0', '1', '0');
wait for 100 US;
hall <= ('0', '1', '1');
wait for 100 US;
hall <= ('0', '0', '1');
wait for 100 US;
hall <= ('1', '0', '1');
wait for 100 US;
hall <= ('1', '0', '0');
wait for 100 US;
hall <= ('1', '1', '0');
wait for 100 US;
hall <= ('0', '1', '0');
wait for 100 US;
hall <= ('0', '1', '1');
wait for 100 US;
hall <= ('0', '0', '1');
end process;
-- Test break signal
process
begin
wait for 220 US;
break <= '1';
wait for 50 US;
break <= '0';
end process;
end tb;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF1_3_block.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block
-- Source Path: hdl_ofdm_tx/ifft/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY RADIX22FFT_SDNF1_3_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_2_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_2_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_6_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_6_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_3_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_4_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_4_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_3_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block IS
-- Signals
SIGNAL twdlXdin_2_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL twdlXdin_2_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL twdlXdin_6_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL twdlXdin_6_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_3_re_tmp : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_3_im_tmp : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_4_re_tmp : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_4_im_tmp : signed(18 DOWNTO 0); -- sfix19_En13
BEGIN
twdlXdin_2_re_signed <= signed(twdlXdin_2_re);
twdlXdin_2_im_signed <= signed(twdlXdin_2_im);
twdlXdin_6_re_signed <= signed(twdlXdin_6_re);
twdlXdin_6_im_signed <= signed(twdlXdin_6_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_2_re_signed,
twdlXdin_2_im_signed, twdlXdin_6_re_signed, twdlXdin_6_im_signed,
twdlXdin_1_vld)
VARIABLE add_cast : signed(19 DOWNTO 0);
VARIABLE add_cast_0 : signed(19 DOWNTO 0);
VARIABLE sub_cast : signed(19 DOWNTO 0);
VARIABLE sub_cast_0 : signed(19 DOWNTO 0);
VARIABLE add_cast_1 : signed(19 DOWNTO 0);
VARIABLE add_cast_2 : signed(19 DOWNTO 0);
VARIABLE sub_cast_1 : signed(19 DOWNTO 0);
VARIABLE sub_cast_2 : signed(19 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
add_cast := resize(twdlXdin_2_re_signed, 20);
add_cast_0 := resize(twdlXdin_6_re_signed, 20);
Radix22ButterflyG1_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(twdlXdin_2_re_signed, 20);
sub_cast_0 := resize(twdlXdin_6_re_signed, 20);
Radix22ButterflyG1_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_1 := resize(twdlXdin_2_im_signed, 20);
add_cast_2 := resize(twdlXdin_6_im_signed, 20);
Radix22ButterflyG1_NF_btf1_im_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(twdlXdin_2_im_signed, 20);
sub_cast_2 := resize(twdlXdin_6_im_signed, 20);
Radix22ButterflyG1_NF_btf2_im_reg_next <= sub_cast_1 - sub_cast_2;
END IF;
dout_3_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(18 DOWNTO 0);
dout_3_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(18 DOWNTO 0);
dout_4_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(18 DOWNTO 0);
dout_4_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(18 DOWNTO 0);
dout_3_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_3_re <= std_logic_vector(dout_3_re_tmp);
dout_3_im <= std_logic_vector(dout_3_im_tmp);
dout_4_re <= std_logic_vector(dout_4_re_tmp);
dout_4_im <= std_logic_vector(dout_4_im_tmp);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Prueba_tb IS
END Prueba_tb;
ARCHITECTURE behavior OF Prueba_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Prueba
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
op : IN std_logic;
s : OUT std_logic_vector(3 downto 0);
cout : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
signal op : std_logic := '0';
--Outputs
signal s : std_logic_vector(3 downto 0);
signal cout : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Prueba PORT MAP (
a => a,
b => b,
op => op,
s => s,
cout => cout
);
-- estimulos de simulación
process
begin
a <= "0011";
b <= "0001";
wait for 10 ns;
a <= "0111";
b <= "0010";
--op <= '1';
wait for 10 ns;
--op <= '0';
--wait for 40 ns;
end process;
process
begin
wait for 10 ns;
op <= not op;
end process;
END;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Prueba_tb IS
END Prueba_tb;
ARCHITECTURE behavior OF Prueba_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Prueba
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
op : IN std_logic;
s : OUT std_logic_vector(3 downto 0);
cout : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
signal op : std_logic := '0';
--Outputs
signal s : std_logic_vector(3 downto 0);
signal cout : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Prueba PORT MAP (
a => a,
b => b,
op => op,
s => s,
cout => cout
);
-- estimulos de simulación
process
begin
a <= "0011";
b <= "0001";
wait for 10 ns;
a <= "0111";
b <= "0010";
--op <= '1';
wait for 10 ns;
--op <= '0';
--wait for 40 ns;
end process;
process
begin
wait for 10 ns;
op <= not op;
end process;
END;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normusgn3236;
ARCHITECTURE rtl OF hcc_normusgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntusgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntusgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntusgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normusgn3236;
ARCHITECTURE rtl OF hcc_normusgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntusgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntusgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntusgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normusgn3236;
ARCHITECTURE rtl OF hcc_normusgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntusgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntusgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntusgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normusgn3236;
ARCHITECTURE rtl OF hcc_normusgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntusgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntusgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntusgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normusgn3236;
ARCHITECTURE rtl OF hcc_normusgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntusgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntusgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntusgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normusgn3236;
ARCHITECTURE rtl OF hcc_normusgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntusgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntusgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntusgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normusgn3236;
ARCHITECTURE rtl OF hcc_normusgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntusgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntusgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntusgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normusgn3236;
ARCHITECTURE rtl OF hcc_normusgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntusgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntusgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntusgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normusgn3236;
ARCHITECTURE rtl OF hcc_normusgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntusgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntusgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntusgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normusgn3236;
ARCHITECTURE rtl OF hcc_normusgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntusgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntusgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntusgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_feature_transform:1.0
-- IP Revision: 74
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_feature_transform_0_0 IS
PORT (
clk : IN STD_LOGIC;
clk_x2 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : IN STD_LOGIC;
vsync : IN STD_LOGIC;
x_addr_0 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_0 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_addr_1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
rot_m00 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m01 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
t_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
t_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END system_vga_feature_transform_0_0;
ARCHITECTURE system_vga_feature_transform_0_0_arch OF system_vga_feature_transform_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_feature_transform_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_feature_transform IS
GENERIC (
NUM_FEATURES : INTEGER
);
PORT (
clk : IN STD_LOGIC;
clk_x2 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : IN STD_LOGIC;
vsync : IN STD_LOGIC;
x_addr_0 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_0 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_addr_1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
rot_m00 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m01 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
t_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
t_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT vga_feature_transform;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_feature_transform_0_0_arch: ARCHITECTURE IS "vga_feature_transform,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_feature_transform_0_0_arch : ARCHITECTURE IS "system_vga_feature_transform_0_0,vga_feature_transform,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_feature_transform_0_0_arch: ARCHITECTURE IS "system_vga_feature_transform_0_0,vga_feature_transform,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_feature_transform,x_ipVersion=1.0,x_ipCoreRevision=74,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,NUM_FEATURES=64}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_feature_transform
GENERIC MAP (
NUM_FEATURES => 64
)
PORT MAP (
clk => clk,
clk_x2 => clk_x2,
rst => rst,
active => active,
vsync => vsync,
x_addr_0 => x_addr_0,
y_addr_0 => y_addr_0,
hessian_0 => hessian_0,
x_addr_1 => x_addr_1,
y_addr_1 => y_addr_1,
hessian_1 => hessian_1,
rot_m00 => rot_m00,
rot_m01 => rot_m01,
rot_m10 => rot_m10,
rot_m11 => rot_m11,
t_x => t_x,
t_y => t_y,
state => state
);
END system_vga_feature_transform_0_0_arch;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_ae
--
-- Generated
-- by: wig
-- on: Sat Mar 3 18:34:27 2007
-- cmd: /home/wig/work/MIX/mix_0.pl ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ae-rtl-conf-c.vhd,v 1.1 2007/03/05 13:35:50 wig Exp $
-- $Date: 2007/03/05 13:35:50 $
-- $Log: ent_ae-rtl-conf-c.vhd,v $
-- Revision 1.1 2007/03/05 13:35:50 wig
-- Reworked testcase sigport (changed case of generated files).
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_ae_RTL_CONF / ent_ae
--
configuration ent_ae_RTL_CONF of ent_ae is
for rtl
-- Generated Configuration
end for;
end ent_ae_RTL_CONF;
--
-- End of Generated Configuration ent_ae_RTL_CONF
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
--!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library ambalib;
use ambalib.types_amba4.all;
package types_gnss is
component gnss_ss is
generic (
async_reset : boolean := false;
tech : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#FFFFF#;
xirq : integer := 0
);
port (
i_nrst : in std_logic;
i_clk_bus : in std_logic;
i_clk_adc : in std_logic; -- GNSS ADC clock (4..40 MHz)
-- ADC samples (2 complex channels)
i_gps_I : in std_logic_vector(1 downto 0); -- Channel 0 sampled I value
i_gps_Q : in std_logic_vector(1 downto 0); -- Channel 0 sampled Q value
i_glo_I : in std_logic_vector(1 downto 0); -- Channel 1 sampled I value
i_glo_Q : in std_logic_vector(1 downto 0); -- Channel 1 sampled I value
o_pps : out std_logic; -- Pulse Per Second signal
-- MAX2769 SPIs and antenna controls signals:
i_gps_ld : in std_logic; -- Channel 0 RF front-end Lock detect
i_glo_ld : in std_logic; -- Channel 1 RF front-end Lock detect
o_max_sclk : out std_logic; -- RF synthesizer SPI clock
o_max_sdata : out std_logic; -- RF synthesizer SPI data
o_max_ncs : out std_logic_vector(1 downto 0); -- RF synthesizer channel 0/1 selector
i_antext_stat : in std_logic; -- Antenna powered status
i_antext_detect : in std_logic; -- Antenna connected status
o_antext_ena : out std_logic; -- Enabling/disabling antenna
o_antint_contr : out std_logic; -- Antenna Internal/External selector
-- AXI4 interface
o_cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_irq : out std_logic
);
end component;
end;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pkg.ALL;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND FULL = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_dma_0_wrapper_fifo_generator_v9_3_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_dma_0_wrapper_fifo_generator_v9_3_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity gcd_gcd_bus_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
a :out STD_LOGIC_VECTOR(15 downto 0);
b :out STD_LOGIC_VECTOR(15 downto 0);
pResult :in STD_LOGIC_VECTOR(15 downto 0);
pResult_ap_vld :in STD_LOGIC
);
end entity gcd_gcd_bus_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of a
-- bit 15~0 - a[15:0] (Read/Write)
-- others - reserved
-- 0x14 : reserved
-- 0x18 : Data signal of b
-- bit 15~0 - b[15:0] (Read/Write)
-- others - reserved
-- 0x1c : reserved
-- 0x20 : Data signal of pResult
-- bit 15~0 - pResult[15:0] (Read)
-- others - reserved
-- 0x24 : Control signal of pResult
-- bit 0 - pResult_ap_vld (Read/COR)
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of gcd_gcd_bus_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_A_DATA_0 : INTEGER := 16#10#;
constant ADDR_A_CTRL : INTEGER := 16#14#;
constant ADDR_B_DATA_0 : INTEGER := 16#18#;
constant ADDR_B_CTRL : INTEGER := 16#1c#;
constant ADDR_PRESULT_DATA_0 : INTEGER := 16#20#;
constant ADDR_PRESULT_CTRL : INTEGER := 16#24#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
signal int_a : UNSIGNED(15 downto 0) := (others => '0');
signal int_b : UNSIGNED(15 downto 0) := (others => '0');
signal int_pResult : UNSIGNED(15 downto 0) := (others => '0');
signal int_pResult_ap_vld : STD_LOGIC;
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_A_DATA_0 =>
rdata_data <= RESIZE(int_a(15 downto 0), 32);
when ADDR_B_DATA_0 =>
rdata_data <= RESIZE(int_b(15 downto 0), 32);
when ADDR_PRESULT_DATA_0 =>
rdata_data <= RESIZE(int_pResult(15 downto 0), 32);
when ADDR_PRESULT_CTRL =>
rdata_data <= (0 => int_pResult_ap_vld, others => '0');
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
a <= STD_LOGIC_VECTOR(int_a);
b <= STD_LOGIC_VECTOR(int_b);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_idle <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_idle <= ap_idle;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_ready <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_ready <= ap_ready;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_A_DATA_0) then
int_a(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_a(15 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_B_DATA_0) then
int_b(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_b(15 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_pResult <= (others => '0');
elsif (ACLK_EN = '1') then
if (pResult_ap_vld = '1') then
int_pResult <= UNSIGNED(pResult); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_pResult_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (pResult_ap_vld = '1') then
int_pResult_ap_vld <= '1';
elsif (ar_hs = '1' and raddr = ADDR_PRESULT_CTRL) then
int_pResult_ap_vld <= '0'; -- clear on read
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity gcd_gcd_bus_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
a :out STD_LOGIC_VECTOR(15 downto 0);
b :out STD_LOGIC_VECTOR(15 downto 0);
pResult :in STD_LOGIC_VECTOR(15 downto 0);
pResult_ap_vld :in STD_LOGIC
);
end entity gcd_gcd_bus_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of a
-- bit 15~0 - a[15:0] (Read/Write)
-- others - reserved
-- 0x14 : reserved
-- 0x18 : Data signal of b
-- bit 15~0 - b[15:0] (Read/Write)
-- others - reserved
-- 0x1c : reserved
-- 0x20 : Data signal of pResult
-- bit 15~0 - pResult[15:0] (Read)
-- others - reserved
-- 0x24 : Control signal of pResult
-- bit 0 - pResult_ap_vld (Read/COR)
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of gcd_gcd_bus_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_A_DATA_0 : INTEGER := 16#10#;
constant ADDR_A_CTRL : INTEGER := 16#14#;
constant ADDR_B_DATA_0 : INTEGER := 16#18#;
constant ADDR_B_CTRL : INTEGER := 16#1c#;
constant ADDR_PRESULT_DATA_0 : INTEGER := 16#20#;
constant ADDR_PRESULT_CTRL : INTEGER := 16#24#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
signal int_a : UNSIGNED(15 downto 0) := (others => '0');
signal int_b : UNSIGNED(15 downto 0) := (others => '0');
signal int_pResult : UNSIGNED(15 downto 0) := (others => '0');
signal int_pResult_ap_vld : STD_LOGIC;
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_A_DATA_0 =>
rdata_data <= RESIZE(int_a(15 downto 0), 32);
when ADDR_B_DATA_0 =>
rdata_data <= RESIZE(int_b(15 downto 0), 32);
when ADDR_PRESULT_DATA_0 =>
rdata_data <= RESIZE(int_pResult(15 downto 0), 32);
when ADDR_PRESULT_CTRL =>
rdata_data <= (0 => int_pResult_ap_vld, others => '0');
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
a <= STD_LOGIC_VECTOR(int_a);
b <= STD_LOGIC_VECTOR(int_b);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_idle <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_idle <= ap_idle;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_ready <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_ready <= ap_ready;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_A_DATA_0) then
int_a(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_a(15 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_B_DATA_0) then
int_b(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_b(15 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_pResult <= (others => '0');
elsif (ACLK_EN = '1') then
if (pResult_ap_vld = '1') then
int_pResult <= UNSIGNED(pResult); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_pResult_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (pResult_ap_vld = '1') then
int_pResult_ap_vld <= '1';
elsif (ar_hs = '1' and raddr = ADDR_PRESULT_CTRL) then
int_pResult_ap_vld <= '0'; -- clear on read
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity gcd_gcd_bus_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
a :out STD_LOGIC_VECTOR(15 downto 0);
b :out STD_LOGIC_VECTOR(15 downto 0);
pResult :in STD_LOGIC_VECTOR(15 downto 0);
pResult_ap_vld :in STD_LOGIC
);
end entity gcd_gcd_bus_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of a
-- bit 15~0 - a[15:0] (Read/Write)
-- others - reserved
-- 0x14 : reserved
-- 0x18 : Data signal of b
-- bit 15~0 - b[15:0] (Read/Write)
-- others - reserved
-- 0x1c : reserved
-- 0x20 : Data signal of pResult
-- bit 15~0 - pResult[15:0] (Read)
-- others - reserved
-- 0x24 : Control signal of pResult
-- bit 0 - pResult_ap_vld (Read/COR)
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of gcd_gcd_bus_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_A_DATA_0 : INTEGER := 16#10#;
constant ADDR_A_CTRL : INTEGER := 16#14#;
constant ADDR_B_DATA_0 : INTEGER := 16#18#;
constant ADDR_B_CTRL : INTEGER := 16#1c#;
constant ADDR_PRESULT_DATA_0 : INTEGER := 16#20#;
constant ADDR_PRESULT_CTRL : INTEGER := 16#24#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
signal int_a : UNSIGNED(15 downto 0) := (others => '0');
signal int_b : UNSIGNED(15 downto 0) := (others => '0');
signal int_pResult : UNSIGNED(15 downto 0) := (others => '0');
signal int_pResult_ap_vld : STD_LOGIC;
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_A_DATA_0 =>
rdata_data <= RESIZE(int_a(15 downto 0), 32);
when ADDR_B_DATA_0 =>
rdata_data <= RESIZE(int_b(15 downto 0), 32);
when ADDR_PRESULT_DATA_0 =>
rdata_data <= RESIZE(int_pResult(15 downto 0), 32);
when ADDR_PRESULT_CTRL =>
rdata_data <= (0 => int_pResult_ap_vld, others => '0');
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
a <= STD_LOGIC_VECTOR(int_a);
b <= STD_LOGIC_VECTOR(int_b);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_idle <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_idle <= ap_idle;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_ready <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_ready <= ap_ready;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_A_DATA_0) then
int_a(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_a(15 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_B_DATA_0) then
int_b(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_b(15 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_pResult <= (others => '0');
elsif (ACLK_EN = '1') then
if (pResult_ap_vld = '1') then
int_pResult <= UNSIGNED(pResult); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_pResult_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (pResult_ap_vld = '1') then
int_pResult_ap_vld <= '1';
elsif (ar_hs = '1' and raddr = ADDR_PRESULT_CTRL) then
int_pResult_ap_vld <= '0'; -- clear on read
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
-- cb20_info_device_0_avalon_slave_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.05.28.12:22:46
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_info_device_0_avalon_slave_translator is
generic (
AV_ADDRESS_W : integer := 5;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 17;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(16 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(4 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity cb20_info_device_0_avalon_slave_translator;
architecture rtl of cb20_info_device_0_avalon_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(4 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
info_device_0_avalon_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_waitrequest => av_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of cb20_info_device_0_avalon_slave_translator
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_counter is
end entity tb_counter;
use work.counter_types.all;
architecture test of tb_counter is
signal clk, clr : bit := '0';
signal q0, q1 : digit;
begin
dut : entity work.counter(registered)
port map ( clk => clk, clr => clr,
q0 => q0, q1 => q1 );
clk_gen : clk <= not clk after 20 ns;
clr_gen : clr <= '1' after 95 ns,
'0' after 135 ns;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_counter is
end entity tb_counter;
use work.counter_types.all;
architecture test of tb_counter is
signal clk, clr : bit := '0';
signal q0, q1 : digit;
begin
dut : entity work.counter(registered)
port map ( clk => clk, clr => clr,
q0 => q0, q1 => q1 );
clk_gen : clk <= not clk after 20 ns;
clr_gen : clr <= '1' after 95 ns,
'0' after 135 ns;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_counter is
end entity tb_counter;
use work.counter_types.all;
architecture test of tb_counter is
signal clk, clr : bit := '0';
signal q0, q1 : digit;
begin
dut : entity work.counter(registered)
port map ( clk => clk, clr => clr,
q0 => q0, q1 => q1 );
clk_gen : clk <= not clk after 20 ns;
clr_gen : clr <= '1' after 95 ns,
'0' after 135 ns;
end architecture test;
|
library IEEE;
use IEEE.std_logic_1164.all;
package pkg1_lib1 is
component com1_pkg1_lib1 is
generic (
WITH_GENERIC: boolean:=TRUE
);
port (
data_i : in std_logic;
data_o : out std_logic
);
end component com1_pkg1_lib1;
component com2_pkg1_lib1 is
port (
data_i : in std_logic;
data_o : out std_logic
);
end component com2_pkg1_lib1;
component com3_pkg1_lib1 is
generic (
WITH_GENERIC: boolean:=TRUE
);
port (
data_i : in std_logic;
data_o : out std_logic
);
end component com3_pkg1_lib1;
end package pkg1_lib1;
|
architecture RTL of FIFO is
procedure proc1 is begin END procedure proc1;
PROCEDURE PROC1 IS BEGIN END PROCEDURE PROC1;
function func1 return integer is begin End function func1;
begin
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_100 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_100;
architecture BEHAVIORAL of dcm_32_100 is
signal CLKFX_BUF : std_logic;
signal CLK2X_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
CLK2X_BUFG_INST : BUFG
port map (I => CLK2X_BUF, O => CLK2X_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 100.00 = 32.000 * 25/8
CLKFX_MULTIPLY => 25,
CLKFX_DIVIDE => 8,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_BUF,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
-- Don't use this.
-- GHDL doesn't put signals of enumerated type into the .vcd signal trace
-- So we'd have to settle for constants when we want to display them.
-- If you find yourself in that position, comment out alu_op_t in arch_defs.vhdl
-- and use this one here instead.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package alu_defs is
subtype alu_op_t is std_logic_vector(4 downto 0);
constant ALU_ADD : alu_op_t := B"0_0000";
constant ALU_ADDU : alu_op_t := B"0_0001";
constant ALU_SUB : alu_op_t := B"0_0010";
constant ALU_SUBU : alu_op_t := B"0_0011";
constant ALU_AND : alu_op_t := B"0_0100";
constant ALU_OR : alu_op_t := B"0_0101";
constant ALU_NOR : alu_op_t := B"0_0110";
constant ALU_XOR : alu_op_t := B"0_0111";
constant ALU_LU : alu_op_t := B"0_1000";
constant ALU_SLL : alu_op_t := B"0_1001";
constant ALU_SRL : alu_op_t := B"0_1010";
constant ALU_SRA : alu_op_t := B"0_1011";
constant ALU_MULT : alu_op_t := B"0_1100";
constant ALU_MULTU : alu_op_t := B"0_1101";
constant ALU_DIV : alu_op_t := B"0_1110";
constant ALU_DIVU : alu_op_t := B"0_1111";
constant ALU_MFHI : alu_op_t := B"1_0000";
constant ALU_MFLO : alu_op_t := B"1_0001";
constant ALU_MTHI : alu_op_t := B"1_0010";
constant ALU_MTLO : alu_op_t := B"1_0011";
constant ALU_SLT : alu_op_t := B"1_0100";
constant ALU_SLTU : alu_op_t := B"1_0101";
constant ALU_EQ : alu_op_t := B"1_0110";
constant ALU_NE : alu_op_t := B"1_0111";
constant ALU_LEZ : alu_op_t := B"1_1000";
constant ALU_LTZ : alu_op_t := B"1_1001";
constant ALU_GTZ : alu_op_t := B"1_1010";
constant ALU_GEZ : alu_op_t := B"1_1011";
end package;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_b_e
--
-- Generated
-- by: wig
-- on: Wed Apr 5 12:50:28 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-rtl-conf-c.vhd,v 1.1 2006/04/10 15:42:11 wig Exp $
-- $Date: 2006/04/10 15:42:11 $
-- $Log: inst_b_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2006/04/10 15:42:11 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_b_e_rtl_conf / inst_b_e
--
configuration inst_b_e_rtl_conf of inst_b_e is
for rtl
-- Generated Configuration
for inst_ba_i : inst_xa_e
use configuration work.inst_xa_e_rtl_conf;
end for;
for inst_bb_i : inst_bb_e
use configuration work.inst_bb_e_rtl_conf;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_bc_i : inst_vb_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_vb_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_bd_i : inst_vb_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_vb_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_be_i : inst_be_i
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_be_i_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_b_e_rtl_conf;
--
-- End of Generated Configuration inst_b_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(138-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(138-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(138-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(138-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
rst_s_wr3 <= '0';
rst_s_rd <= '0';
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 138,
C_DOUT_WIDTH => 138,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 138,
C_DIN_WIDTH => 138,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 138,
C_DIN_WIDTH => 138,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_138x16_shift_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Global configuration settings.
--
-- Description:
-- ------------------------------------
-- This file evaluates the settings declared in the project specific package my_config.
-- See also template file my_config.vhdl.template.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.my_config.all;
use PoC.my_project.all;
use PoC.utils.all;
package config is
constant PROJECT_DIR : string := MY_PROJECT_DIR;
constant OPERATING_SYSTEM : string := MY_OPERATING_SYSTEM;
-- TODO:
-- ===========================================================================
subtype T_BOARD_STRING is STRING(1 to 8);
subtype T_BOARD_CONFIG_STRING8 is STRING(1 to 8);
subtype T_BOARD_CONFIG_STRING16 is STRING(1 to 16);
subtype T_BOARD_CONFIG_STRING32 is STRING(1 to 32);
-- subtype T_BOARD_CONFIG_STRING64 is STRING(1 to 64);
subtype T_DEVICE_STRING is STRING(1 to 32);
constant C_BOARD_STRING_EMPTY : T_BOARD_STRING;
constant C_BOARD_CONFIG_STRING8_EMPTY : T_BOARD_CONFIG_STRING8;
constant C_BOARD_CONFIG_STRING16_EMPTY : T_BOARD_CONFIG_STRING16;
constant C_BOARD_CONFIG_STRING32_EMPTY : T_BOARD_CONFIG_STRING32;
-- constant C_BOARD_CONFIG_STRING64_EMPTY : T_BOARD_CONFIG_STRING64;
constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING;
-- List of known boards
-- ---------------------------------------------------------------------------
type T_BOARD is (
BOARD_CUSTOM,
-- Spartan-3 boards
BOARD_S3SK200, BOARD_S3SK1000,
BOARD_S3ESK500, BOARD_S3ESK1600,
-- Spartan-6 boards
BOARD_ATLYS,
-- Kintex-7 boards
BOARD_KC705,
-- Virtex-5 boards
BOARD_ML505,
BOARD_ML506,
BOARD_ML507,
BOARD_XUPV5,
-- Virtex-6 boards
BOARD_ML605,
-- Virtex-7 boards
BOARD_VC707,
BOARD_VC709,
-- Zynq-7000 boards
BOARD_ZEDBOARD,
-- Cyclon III boards
BOARD_DE0,
-- Stratix II boards
BOARD_S2GXAV,
-- Stratix IV boards
BOARD_DE4,
-- Stratix V boards
BOARD_DE5
);
-- List of known FPGA / Chip vendors
-- ---------------------------------------------------------------------------
type T_VENDOR is (
VENDOR_ALTERA,
VENDOR_LATTICE,
VENDOR_XILINX
);
subtype vendor_t is T_VENDOR;
-- List of known synthesis tool chains
-- ---------------------------------------------------------------------------
type T_SYNTHESIS_TOOL is (
SYNTHESIS_TOOL_ALTERA_QUARTUS2,
SYNTHESIS_TOOL_SYNOPSIS,
SYNTHESIS_TOOL_XILINX_XST,
SYNTHESIS_TOOL_XILINX_VIVADO
);
-- List of known devices
-- ---------------------------------------------------------------------------
type T_DEVICE is (
DEVICE_SPARTAN3, DEVICE_SPARTAN6, -- Xilinx.Spartan
DEVICE_ZYNQ7, -- Xilinx.Zynq
DEVICE_ARTIX7, -- Xilinx.Artix
DEVICE_KINTEX7, -- Xilinx.Kintex
DEVICE_VIRTEX5, DEVICE_VIRTEX6, DEVICE_VIRTEX7, -- Xilinx.Virtex
DEVICE_CYCLONE1, DEVICE_CYCLONE2, DEVICE_CYCLONE3, -- Altera.Cyclone
DEVICE_STRATIX1, DEVICE_STRATIX2, DEVICE_STRATIX4, DEVICE_STRATIX5 -- Altera.Stratix
);
subtype device_t is T_DEVICE;
-- List of known device families
-- ---------------------------------------------------------------------------
type T_DEVICE_FAMILY is (
-- Xilinx
DEVICE_FAMILY_SPARTAN,
DEVICE_FAMILY_ZYNQ,
DEVICE_FAMILY_ARTIX,
DEVICE_FAMILY_KINTEX,
DEVICE_FAMILY_VIRTEX,
DEVICE_FAMILY_CYCLONE,
DEVICE_FAMILY_STRATIX
);
-- List of known device subtypes
-- ---------------------------------------------------------------------------
type T_DEVICE_SUBTYPE is (
DEVICE_SUBTYPE_NONE,
-- Xilinx
DEVICE_SUBTYPE_X,
DEVICE_SUBTYPE_T,
DEVICE_SUBTYPE_XT,
DEVICE_SUBTYPE_HT,
DEVICE_SUBTYPE_LX,
DEVICE_SUBTYPE_SXT,
DEVICE_SUBTYPE_LXT,
DEVICE_SUBTYPE_TXT,
DEVICE_SUBTYPE_FXT,
DEVICE_SUBTYPE_CXT,
DEVICE_SUBTYPE_HXT,
-- Altera
DEVICE_SUBTYPE_E,
DEVICE_SUBTYPE_GS,
DEVICE_SUBTYPE_GX,
DEVICE_SUBTYPE_GT
);
-- List of known transceiver (sub-)types
-- ---------------------------------------------------------------------------
type T_TRANSCEIVER is (
TRANSCEIVER_GTP_DUAL, TRANSCEIVER_GTPE1, TRANSCEIVER_GTPE2, -- Xilinx GTP transceivers
TRANSCEIVER_GTX, TRANSCEIVER_GTXE1, TRANSCEIVER_GTXE2, -- Xilinx GTX transceivers
TRANSCEIVER_GTH, TRANSCEIVER_GTHE1, TRANSCEIVER_GTHE2, -- Xilinx GTH transceivers
TRANSCEIVER_GTZ, -- Xilinx GTZ transceivers
-- TODO: add Altera transceivers
TRANSCEIVER_GXB, -- Altera GXB transceiver
TRANSCEIVER_NONE
);
-- Properties of an FPGA architecture
-- ===========================================================================
type T_DEVICE_INFO is record
Vendor : T_VENDOR;
Device : T_DEVICE;
DevFamily : T_DEVICE_FAMILY;
DevNumber : natural;
DevSubType : T_DEVICE_SUBTYPE;
DevSeries : natural;
TransceiverType : T_TRANSCEIVER;
LUT_FanIn : positive;
end record;
-- Data structures to describe UART / RS232
type T_BOARD_UART_DESC is record
IsDTE : BOOLEAN; -- Data terminal Equipment (e.g. PC, Printer)
FlowControl : T_BOARD_CONFIG_STRING16; -- (NONE, SW, HW_CTS_RTS, HW_RTR_RTS)
BaudRate : T_BOARD_CONFIG_STRING16; -- e.g. "115.2 kBd"
BaudRate_Max : T_BOARD_CONFIG_STRING16;
end record;
-- Data structures to describe Ethernet
type T_BOARD_ETHERNET_DESC is record
IPStyle : T_BOARD_CONFIG_STRING8;
RS_DataInterface : T_BOARD_CONFIG_STRING8;
PHY_Device : T_BOARD_CONFIG_STRING16;
PHY_DeviceAddress : STD_LOGIC_VECTOR(7 downto 0);
PHY_DataInterface : T_BOARD_CONFIG_STRING8;
PHY_ManagementInterface : T_BOARD_CONFIG_STRING16;
end record;
subtype T_BOARD_ETHERNET_DESC_INDEX is NATURAL range 0 to 7;
type T_BOARD_ETHERNET_DESC_VECTOR is array(NATURAL range <>) of T_BOARD_ETHERNET_DESC;
-- Data structures to describe a board layout
type T_BOARD_INFO is record
FPGADevice : T_DEVICE_STRING;
UART : T_BOARD_UART_DESC;
Ethernet : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX);
EthernetCount : T_BOARD_ETHERNET_DESC_INDEX;
end record;
type T_BOARD_INFO_VECTOR is array (T_BOARD) of T_BOARD_INFO;
-- QUESTION: replace archprops with DEVICE_INFO ?
type archprops_t is record
LUT_K : positive; -- LUT Fanin
end record;
-- Functions extracting board and PCB properties from "MY_BOARD"
-- which is declared in package "my_config".
-- ===========================================================================
function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return T_BOARD;
function BOARD_INFO(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return T_BOARD_INFO;
function BOARD_DEVICE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING;
function BOARD_UART_BAUDRATE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING;
-- Functions extracting device and architecture properties from "MY_DEVICE"
-- which is declared in package "my_config".
-- ===========================================================================
function VENDOR(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_VENDOR;
function SYNTHESIS_TOOL(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_SYNTHESIS_TOOL;
function DEVICE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE;
function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY;
function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural;
function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SUBTYPE;
function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural;
function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER;
function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive;
function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO;
function ARCH_PROPS return archprops_t;
-- force FSM to predefined encoding in debug mode
function getFSMEncoding_gray(debug : BOOLEAN) return STRING;
end package;
package body config is
-- default fill and string termination character for fixed size strings
-- ===========================================================================
constant C_POC_NUL : CHARACTER := '`';
-- deferred constant
-- ===========================================================================
constant C_BOARD_STRING_EMPTY : T_BOARD_STRING := (others => C_POC_NUL);
constant C_BOARD_CONFIG_STRING8_EMPTY : T_BOARD_CONFIG_STRING8 := (others => C_POC_NUL);
constant C_BOARD_CONFIG_STRING16_EMPTY : T_BOARD_CONFIG_STRING16 := (others => C_POC_NUL);
constant C_BOARD_CONFIG_STRING32_EMPTY : T_BOARD_CONFIG_STRING32 := (others => C_POC_NUL);
constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING := (others => C_POC_NUL);
-- private functions required by board description
-- ModelSim requires that this functions is defined before it is used below.
-- ===========================================================================
-- chr_is* function
function chr_isDigit(chr : CHARACTER) return boolean is
begin
return ((CHARACTER'pos('0') <= CHARACTER'pos(chr)) and (CHARACTER'pos(chr) <= CHARACTER'pos('9')));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return (((CHARACTER'pos('a') <= CHARACTER'pos(chr)) and (CHARACTER'pos(chr) <= CHARACTER'pos('z'))) or
((CHARACTER'pos('A') <= CHARACTER'pos(chr)) and (CHARACTER'pos(chr) <= CHARACTER'pos('Z'))));
end function;
function str_length(str : STRING) return NATURAL is
begin
for i in str'range loop
if (str(i) = C_POC_NUL) then
return i - str'low;
end if;
end loop;
return str'length;
end function;
function str_trim(str : STRING) return STRING is
begin
return str(str'low to str'low + str_length(str) - 1);
end function;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is
constant len : NATURAL := imin(str1'length, str2'length);
variable chr1 : CHARACTER;
variable chr2 : CHARACTER;
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in str1'low to str1'low + len - 1 loop
chr1 := str1(i);
chr2 := str2(str2'low + (i - str1'low ));
if (CHARACTER'pos('A') <= CHARACTER'pos(chr1)) and (CHARACTER'pos(chr1) <= CHARACTER'pos('Z')) then
chr1 := CHARACTER'val(CHARACTER'pos(chr1) - CHARACTER'pos('A') + CHARACTER'pos('a'));
end if;
if (CHARACTER'pos('A') <= CHARACTER'pos(chr2)) and (CHARACTER'pos(chr2) <= CHARACTER'pos('Z')) then
chr2 := CHARACTER'val(CHARACTER'pos(chr2) - CHARACTER'pos('A') + CHARACTER'pos('a'));
end if;
if (chr1 /= chr2) then
return FALSE;
elsif ((chr1 = C_POC_NUL) xor (chr2 = C_POC_NUL)) then
return FALSE;
elsif ((chr1 = C_POC_NUL) and (chr2 = C_POC_NUL)) then
return TRUE;
end if;
end loop;
-- check special cases,
return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal
((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len
((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len
end function;
function str_find(str : STRING; pattern : STRING; start : NATURAL := 0) return BOOLEAN is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return TRUE;
end if;
end loop;
return FALSE;
end function;
-- helper function to create configuration strings
-- ===========================================================================
function getLocalDeviceString(DeviceString : STRING) return STRING is
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is begin
if cond then return value1; else return value2; end if;
end function;
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
constant MY_DEVICE_STR : STRING := BOARD_DEVICE;
variable Result : STRING(1 to T_DEVICE_STRING'length);
begin
Result := (others => C_POC_NUL);
-- report DeviceString for debugging
if (POC_VERBOSE = TRUE) then
report "getLocalDeviceString: DeviceString='" & str_trim(DeviceString) & "' MY_DEVICE='" & str_trim(MY_DEVICE) & "' MY_DEVICE_STR='" & str_trim(MY_DEVICE_STR) & "'" severity NOTE;
end if;
-- if DeviceString is populated
if ((str_length(DeviceString) /= 0) and (str_imatch(DeviceString, "None") = FALSE)) then
Result(1 to imin(T_DEVICE_STRING'length, imax(1, DeviceString'length))) := ite((DeviceString'length > 0), DeviceString(1 to imin(T_DEVICE_STRING'length, DeviceString'length)), ConstNUL);
-- if MY_DEVICE is set, prefer it
elsif ((str_length(MY_DEVICE) /= 0) and (str_imatch(MY_DEVICE, "None") = FALSE)) then
Result(1 to imin(T_DEVICE_STRING'length, imax(1, MY_DEVICE'length))) := ite((MY_DEVICE'length > 0), MY_DEVICE(1 to imin(T_DEVICE_STRING'length, MY_DEVICE'length)), ConstNUL);
-- otherwise use MY_BOARD
else
Result(1 to imin(T_DEVICE_STRING'length, imax(1, MY_DEVICE_STR'length))) := ite((MY_DEVICE_STR'length > 0), MY_DEVICE_STR(1 to imin(T_DEVICE_STRING'length, MY_DEVICE_STR'length)), ConstNUL);
end if;
return Result;
end function;
-- helper function to create configuration strings
-- ===========================================================================
function conf(str : string; Size : POSITIVE) return STRING is
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
variable Result : STRING(1 to Size);
-- inlined function from PoC.utils, to break dependency
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is begin
if cond then return value1; else return value2; end if;
end function;
function imin(arg1 : integer; arg2 : integer) return integer is begin
if arg1 < arg2 then return arg1; else return arg2; end if;
end function;
function imax(arg1 : integer; arg2 : integer) return integer is begin
if arg1 > arg2 then return arg1; else return arg2; end if;
end function;
begin
Result := (others => C_POC_NUL);
if (str'length > 0) then
Result(1 to imin(Size, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(Size, str'length)), ConstNUL);
end if;
return Result;
end function;
function conf8(str : string) return T_BOARD_CONFIG_STRING8 is
begin
return conf(str, 8);
end function;
function conf16(str : string) return T_BOARD_CONFIG_STRING16 is
begin
return conf(str, 16);
end function;
function conf32(str : string) return T_BOARD_CONFIG_STRING32 is
begin
return conf(str, 32);
end function;
-- function conf64(str : string) return T_BOARD_CONFIG_STRING64 is
-- begin
-- return conf(str, 64);
-- end function;
function extractFirstNumber(str : STRING) return NATURAL is
variable low : integer;
variable high : integer;
variable Result : NATURAL;
variable Digit : INTEGER;
begin
low := -1;
high := -1;
for i in str'low to str'high loop
if chr_isDigit(str(i)) then
low := i;
exit;
end if;
end loop;
-- abort if no digit can be found
if (low = -1) then return 0; end if;
for i in (low + 1) to str'high loop
if chr_isAlpha(str(i)) then
high := i - 1;
exit;
end if;
end loop;
if (high = -1) then return 0; end if;
-- return INTEGER'value(str(low to high)); -- 'value(...) is not supported by Vivado Synth 2014.1
-- convert substring to a number
for i in low to high loop
if (chr_isDigit(str(i)) = FALSE) then
return -1;
end if;
Result := (Result * 10) + (character'pos(str(i)) - character'pos('0'));
end loop;
return Result;
end function;
-- predefined UART descriptions
function brd_CreateUART(IsDTE : BOOLEAN; FlowControl : STRING; BaudRate : STRING; BaudRate_Max : STRING := "") return T_BOARD_UART_DESC is
variable Result : T_BOARD_UART_DESC;
begin
Result.IsDTE := IsDTE;
Result.FlowControl := conf16(FlowControl);
Result.BaudRate := conf16(BaudRate);
Result.BaudRate_Max := conf16(BaudRate_Max);
return Result;
end function;
constant C_BOARD_UART_EMPTY : T_BOARD_UART_DESC := brd_CreateUART(TRUE, "NONE", "0 Bd");
constant C_BOARD_UART_DTE_115200_NONE : T_BOARD_UART_DESC := brd_CreateUART(TRUE, "NONE", "115.2 kBd");
constant C_BOARD_UART_DCE_115200_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "115.2 kBd");
constant C_BOARD_UART_DCE_115200_HWCTS : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "HW_CTS_RTS", "115.2 kBd");
constant C_BOARD_UART_DTE_460800_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "460.8 kBd");
constant C_BOARD_UART_DTE_921600_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "921.6 kBd");
function brd_CreateEthernet(IPStyle : STRING; RS_DataInt : STRING; PHY_Device : STRING; PHY_DevAddress : STD_LOGIC_VECTOR(7 downto 0); PHY_DataInt : STRING; PHY_MgntInt : STRING) return T_BOARD_ETHERNET_DESC is
variable Result : T_BOARD_ETHERNET_DESC;
begin
Result.IPStyle := conf8(IPStyle);
Result.RS_DataInterface := conf8(RS_DataInt);
Result.PHY_Device := conf16(PHY_Device);
Result.PHY_DeviceAddress := PHY_DevAddress;
Result.PHY_DataInterface := conf8(PHY_DataInt);
Result.PHY_ManagementInterface := conf16(PHY_MgntInt);
return Result;
end function;
constant C_BOARD_ETH_EMPTY : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("", "", "", x"00", "", "");
constant C_BOARD_ETH_SOFT_GMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"07", "GMII", "MDIO");
constant C_BOARD_ETH_HARD_GMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("HARD", "GMII", "MARVEL_88E1111", x"07", "GMII", "MDIO");
constant C_BOARD_ETH_SOFT_SGMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"07", "SGMII", "MDIO_OVER_IIC");
constant C_BOARD_ETH_NONE : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX) := (others => C_BOARD_ETH_EMPTY);
-- board description
-- ===========================================================================
CONSTANT C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR := (
-- Xilinx boards
-- =========================================================================
BOARD_S3SK200 => (
FPGADevice => conf32("XC3S200FT256"), -- XC2S200FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_S3SK1000 => (
FPGADevice => conf32("XC3S1000FT256"), -- XC2S200FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_S3ESK500 => (
FPGADevice => conf32("XC3S500EFT256"), -- XC2S200FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_S3ESK1600 => (
FPGADevice => conf32("XC3S1600EFT256"), -- XC2S200FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_ATLYS => (
FPGADevice => conf32("XC6SLX45-3CSG324"), -- XC6SLX45-3CSG324
UART => C_BOARD_UART_DTE_460800_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_KC705 => (
FPGADevice => conf32("XC7K325T-2FFG900C"), -- XC7K325T-2FFG900C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => (
0 => C_BOARD_ETH_SOFT_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_ML505 => (
FPGADevice => conf32("XC5VLX50T-1FF1136"), -- XC5VLX50T-1FF1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_ML506 => (
FPGADevice => conf32("XC5VSX50T-1FFG1136"), -- XC5VSX50T-1FFG1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_ML507 => (
FPGADevice => conf32("XC5VFX70T-1FFG1136"), -- XC5VFX70T-1FFG1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_XUPV5 => (
FPGADevice => conf32("XC5VLX110T-1FF1136"), -- XC5VLX110T-1FF1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_ML605 => (
FPGADevice => conf32("XC6VLX240T-1FF1156"), -- XC6VLX240T-1FF1156
UART => C_BOARD_UART_EMPTY,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_VC707 => (
FPGADevice => conf32("XC7VX485T-2FFG1761C"), -- XC7VX485T-2FFG1761C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => (
0 => C_BOARD_ETH_SOFT_SGMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),
BOARD_VC709 => (
FPGADevice => conf32("XC7VX690T-2FFG1761C"), -- XC7VX690T-2FFG1761C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_ZEDBOARD => (
FPGADevice => conf32("XC7Z020-1CLG484"), -- XC7Z020-1CLG484
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
-- Altera boards
-- =========================================================================
BOARD_DE0 => (
FPGADevice => conf32("EP3C16F484"), -- EP3C16F484
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_S2GXAV => (
FPGADevice => conf32("EP2SGX90FF1508C3"), -- EP2SGX90FF1508C3
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
BOARD_DE4 => (
FPGADevice => conf32("EP4SGX230KF40C2"), -- EP4SGX230KF40C2
UART => C_BOARD_UART_DTE_460800_NONE,
Ethernet => (
0 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"00", "RGMII", "MDIO"),
1 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"01", "RGMII", "MDIO"),
2 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"02", "RGMII", "MDIO"),
3 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"03", "RGMII", "MDIO"),
others => C_BOARD_ETH_EMPTY
),
EthernetCount => 4
),
BOARD_DE5 => (
FPGADevice => conf32("EP5SGXEA7N2F45C2"), -- EP5SGXEA7N2F45C2
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
-- custom board / dummy entry
BOARD_CUSTOM => (
FPGADevice => conf32("Device is unknown for a custom board"),
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
)
);
-- Public functions
-- ===========================================================================
-- TODO: comment
function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return T_BOARD is
-- inlined function from PoC.utils, to break dependency
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is begin
if cond then return value1; else return value2; end if;
end function;
constant MY_BRD : T_BOARD_STRING := ite((BoardConfig /= C_BOARD_STRING_EMPTY), conf(BoardConfig, T_BOARD_STRING'length), conf(MY_BOARD, T_BOARD_STRING'length));
begin
if (POC_VERBOSE = TRUE) then
report "PoC configuration: Used board is '" & str_trim(MY_BRD) & "'" severity NOTE;
end if;
for i in T_BOARD loop
if str_imatch(T_BOARD'image(i), "BOARD_" & str_trim(MY_BRD)) then
return i;
end if;
end loop;
report "Unknown board name in MY_BOARD = " & MY_BRD & "." severity failure;
return BOARD_CUSTOM;
end function;
function BOARD_INFO(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return T_BOARD_INFO is
constant BRD : T_BOARD := BOARD(BoardConfig);
begin
return C_BOARD_INFO_LIST(BRD);
end function;
-- TODO: comment
function BOARD_DEVICE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING is
constant BRD : T_BOARD := BOARD(BoardConfig);
begin
return str_trim(C_BOARD_INFO_LIST(BRD).FPGADevice);
end function;
function BOARD_UART_BAUDRATE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING is
constant BRD : T_BOARD := BOARD(BoardConfig);
begin
return str_trim(C_BOARD_INFO_LIST(BRD).UART.BaudRate);
end function;
-- purpose: extract vendor from MY_DEVICE
function VENDOR(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_VENDOR is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN_STR : string(1 to 2) := MY_DEV(1 to 2);
begin
case VEN_STR is
when "XC" => return VENDOR_XILINX;
when "EP" => return VENDOR_ALTERA;
when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function SYNTHESIS_TOOL(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_SYNTHESIS_TOOL is
constant VEN : T_VENDOR := VENDOR(DeviceString);
begin
case VEN is
when VENDOR_ALTERA =>
return SYNTHESIS_TOOL_ALTERA_QUARTUS2;
when VENDOR_LATTICE =>
return SYNTHESIS_TOOL_SYNOPSIS;
when VENDOR_XILINX =>
if (1 fs /= 1 us) then
return SYNTHESIS_TOOL_XILINX_XST;
else
return SYNTHESIS_TOOL_XILINX_VIVADO;
end if;
end case;
end function;
-- purpose: extract device from MY_DEVICE
function DEVICE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN : T_VENDOR := VENDOR(DeviceString);
constant DEV_STR : string(3 to 4) := MY_DEV(3 to 4);
begin
case VEN is
when VENDOR_ALTERA =>
case DEV_STR is
when "1C" => return DEVICE_CYCLONE1;
when "2C" => return DEVICE_CYCLONE2;
when "3C" => return DEVICE_CYCLONE3;
when "1S" => return DEVICE_STRATIX1;
when "2S" => return DEVICE_STRATIX2;
when "4S" => return DEVICE_STRATIX4;
when "5S" => return DEVICE_STRATIX5;
when others => report "Unknown Altera device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when VENDOR_XILINX =>
case DEV_STR is
when "7A" => return DEVICE_ARTIX7;
when "7K" => return DEVICE_KINTEX7;
when "3S" => return DEVICE_SPARTAN3;
when "6S" => return DEVICE_SPARTAN6;
when "5V" => return DEVICE_VIRTEX5;
when "6V" => return DEVICE_VIRTEX6;
when "7V" => return DEVICE_VIRTEX7;
when "7Z" => return DEVICE_ZYNQ7;
when others => report "Unknown Xilinx device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when others => report "Unknown vendor in MY_DEVICE = " & MY_DEV & "." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
-- purpose: extract device from MY_DEVICE
function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN : T_VENDOR := VENDOR(DeviceString);
constant FAM_CHAR : character := MY_DEV(4);
begin
case VEN is
when VENDOR_ALTERA =>
case FAM_CHAR is
when 'C' => return DEVICE_FAMILY_CYCLONE;
when 'S' => return DEVICE_FAMILY_STRATIX;
when others => report "Unknown Altera device family in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when VENDOR_XILINX =>
case FAM_CHAR is
when 'A' => return DEVICE_FAMILY_ARTIX;
when 'K' => return DEVICE_FAMILY_KINTEX;
when 'S' => return DEVICE_FAMILY_SPARTAN;
when 'V' => return DEVICE_FAMILY_VIRTEX;
when 'Z' => return DEVICE_FAMILY_ZYNQ;
when others => report "Unknown Xilinx device family in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(DeviceString);
begin
case DEV is
when DEVICE_ARTIX7 | DEVICE_KINTEX7 | DEVICE_VIRTEX7 | DEVICE_ZYNQ7 => return 7; -- all Xilinx ****7 devices share some common features: e.g. XADC
when others => return 0;
end case;
end function;
function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN : T_VENDOR := VENDOR(DeviceString);
begin
case VEN is
when VENDOR_ALTERA => return extractFirstNumber(MY_DEV(5 to MY_DEV'high));
when VENDOR_XILINX => return extractFirstNumber(MY_DEV(5 to MY_DEV'high));
when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return t_device_subtype is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(MY_DEV);
constant DEV_SUB_STR : string(1 to 2) := MY_DEV(5 to 6); -- work around for GHDL
begin
case DEV is
when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return DEVICE_SUBTYPE_NONE; -- Altera Cyclon I, II, III devices have no subtype
when DEVICE_STRATIX2 =>
if chr_isDigit(DEV_SUB_STR(1)) then return DEVICE_SUBTYPE_NONE;
elsif (DEV_SUB_STR = "GX") then return DEVICE_SUBTYPE_GX;
else report "Unknown Stratix II subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_STRATIX4 =>
if (DEV_SUB_STR(1) = 'E') then return DEVICE_SUBTYPE_E;
elsif (DEV_SUB_STR = "GX") then return DEVICE_SUBTYPE_GX;
-- elsif (DEV_SUB_STR = "GT") then return DEVICE_SUBTYPE_GT;
else report "Unknown Stratix II subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_SPARTAN3 => report "TODO: parse Spartan3 / Spartan3E / Spartan3AN device subtype." severity failure;
when DEVICE_SPARTAN6 =>
if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_VIRTEX5 =>
if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT;
elsif ((DEV_SUB_STR = "TX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_TXT;
elsif ((DEV_SUB_STR = "FX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_FXT;
else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_VIRTEX6 =>
if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT;
elsif ((DEV_SUB_STR = "CX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_CXT;
elsif ((DEV_SUB_STR = "HX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HXT;
else report "Unknown Virtex-6 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_ARTIX7 =>
if ( ( str_find(MY_DEV(5 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
else report "Unknown Artix-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_KINTEX7 =>
if ( ( str_find(MY_DEV(5 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
else report "Unknown Kintex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_VIRTEX7 =>
if ( ( str_find(MY_DEV(5 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
elsif ((DEV_SUB_STR(1) = 'X') and ( str_find(MY_DEV(6 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_XT;
elsif ((DEV_SUB_STR(1) = 'H') and ( str_find(MY_DEV(6 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HT;
else report "Unknown Virtex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when others => report "Transceiver type is unknown for the given device." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(DeviceString);
begin
case DEV is
when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return 4;
when DEVICE_STRATIX1 | DEVICE_STRATIX2 => return 4;
when DEVICE_STRATIX4 | DEVICE_STRATIX5 => return 6;
when DEVICE_SPARTAN3 => return 4;
when DEVICE_SPARTAN6 => return 6;
when DEVICE_ARTIX7 => return 6;
when DEVICE_KINTEX7 => return 6;
when DEVICE_VIRTEX5 | DEVICE_VIRTEX6 | DEVICE_VIRTEX7 => return 6;
when DEVICE_ZYNQ7 => return 6;
when others => report "LUT fan-in is unknown for the given device." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(DeviceString);
constant DEV_NUM : natural := DEVICE_NUMBER(DeviceString);
constant DEV_SUB : t_device_subtype := DEVICE_SUBTYPE(DeviceString);
begin
case DEV is
when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return TRANSCEIVER_NONE; -- Altera Cyclon I, II, III devices have no transceivers
when DEVICE_SPARTAN3 => return TRANSCEIVER_NONE; -- Xilinx Spartan3 devices have no transceivers
when DEVICE_SPARTAN6 =>
case DEV_SUB is
when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTPE1;
when others => report "Unknown Spartan-6 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
end case;
when DEVICE_VIRTEX5 =>
case DEV_SUB is
when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
when DEVICE_SUBTYPE_SXT => return TRANSCEIVER_GTP_DUAL;
when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTP_DUAL;
when DEVICE_SUBTYPE_TXT => return TRANSCEIVER_GTX;
when DEVICE_SUBTYPE_FXT => return TRANSCEIVER_GTX;
when others => report "Unknown Virtex-5 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
end case;
when DEVICE_VIRTEX6 =>
case DEV_SUB is
when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
when DEVICE_SUBTYPE_SXT => return TRANSCEIVER_GTXE1;
when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTXE1;
when DEVICE_SUBTYPE_HXT => return TRANSCEIVER_GTXE1;
when others => report "Unknown Virtex-6 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
end case;
when DEVICE_ARTIX7 => return TRANSCEIVER_GTPE2;
when DEVICE_KINTEX7 => return TRANSCEIVER_GTXE2;
when DEVICE_VIRTEX7 =>
case DEV_SUB is
when DEVICE_SUBTYPE_T => return TRANSCEIVER_GTXE2;
when DEVICE_SUBTYPE_XT =>
if (DEV_NUM = 485) then return TRANSCEIVER_GTXE2;
else return TRANSCEIVER_GTHE2;
end if;
when DEVICE_SUBTYPE_HT => return TRANSCEIVER_GTHE2;
when others => report "Unknown Virtex-7 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
end case;
when DEVICE_STRATIX2 => return TRANSCEIVER_GXB;
when DEVICE_STRATIX4 => return TRANSCEIVER_GXB;
when others => report "Unknown device." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
-- purpose: extract architecture properties from DEVICE
function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO is
variable Result : T_DEVICE_INFO;
begin
Result.Vendor := VENDOR(DeviceString);
Result.Device := DEVICE(DeviceString);
Result.DevFamily := DEVICE_FAMILY(DeviceString);
Result.DevNumber := DEVICE_NUMBER(DeviceString);
Result.DevSubType := DEVICE_SUBTYPE(DeviceString);
Result.DevSeries := DEVICE_SERIES(DeviceString);
Result.TransceiverType := TRANSCEIVER_TYPE(DeviceString);
Result.LUT_FanIn := LUT_FANIN(DeviceString);
return Result;
end function;
function ARCH_PROPS return archprops_t is
variable result : archprops_t;
begin
result.LUT_K := LUT_FANIN;
return result;
end function;
-- force FSM to predefined encoding in debug mode
function getFSMEncoding_gray(debug : BOOLEAN) return STRING is
begin
if (debug = true) then
return "gray";
else
case VENDOR is
when VENDOR_XILINX => return "auto";
when VENDOR_ALTERA => return "default";
when others => report "Unknown vendor." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end if;
end function;
end package body;
|
library IEEE;
use IEEE.std_logic_1164.all;
use work.fsm_pkg.all;
architecture behavior of fsm is
signal internal_state,internal_state_next : fsm_state;
signal internal_output,internal_output_next: std_logic_vector(1 downto 0);
begin
--Next State Logic and Next Output Logic----
nextState_nextOutput : process(internal_state, INPUT)
begin
internal_state_next<= internal_state;
internal_output_next<=internal_output;
case internal_state is
when START =>
if INPUT = "00" then
internal_state_next <= S3;
internal_output_next <= "01";
end if;
when S0 =>
if INPUT = "01" then
internal_state_next <= S1;
internal_output_next <= "01";
end if;
when S1 =>
if INPUT = "10" then
internal_state_next <= S2;
internal_output_next <= "10";
end if;
if INPUT = "01" then
internal_state_next <= S1;
internal_output_next <= "01";
end if;
if INPUT = "00" then
internal_state_next <= S3;
internal_output_next <= "01";
end if;
if INPUT = "11" then
internal_state_next <= S0;
internal_output_next <= "10" ;
end if;
when S2 =>
if INPUT = "01" then
internal_state_next <= S1;
internal_output_next <= "01" ;
end if;
if INPUT = "11" then
internal_state_next <= S3;
internal_output_next <= "11" ;
end if;
when S3 =>
if INPUT = "11" then
internal_state_next <= S1;
internal_output_next <= "01" ;
end if;
if INPUT = "10" then
internal_state_next <= S2;
internal_output_next <= "01" ;
end if;
when others=>
null;
end case;
end process nextState_nextOutput;
--Sync and Reset Logic--
sync_proc : process(clk, rst)
begin
if(rising_edge(CLK)) then
if RST = '1' then
internal_state <= START;
internal_output <= "00";
else
internal_state <= internal_state_next;
internal_output <= internal_output_next;
end if;
end if;
end process sync_proc;
OUTPUT <= internal_output;
STATE <= internal_state;
end behavior;
|
library IEEE;
use IEEE.std_logic_1164.all;
use work.fsm_pkg.all;
architecture behavior of fsm is
signal internal_state,internal_state_next : fsm_state;
signal internal_output,internal_output_next: std_logic_vector(1 downto 0);
begin
--Next State Logic and Next Output Logic----
nextState_nextOutput : process(internal_state, INPUT)
begin
internal_state_next<= internal_state;
internal_output_next<=internal_output;
case internal_state is
when START =>
if INPUT = "00" then
internal_state_next <= S3;
internal_output_next <= "01";
end if;
when S0 =>
if INPUT = "01" then
internal_state_next <= S1;
internal_output_next <= "01";
end if;
when S1 =>
if INPUT = "10" then
internal_state_next <= S2;
internal_output_next <= "10";
end if;
if INPUT = "01" then
internal_state_next <= S1;
internal_output_next <= "01";
end if;
if INPUT = "00" then
internal_state_next <= S3;
internal_output_next <= "01";
end if;
if INPUT = "11" then
internal_state_next <= S0;
internal_output_next <= "10" ;
end if;
when S2 =>
if INPUT = "01" then
internal_state_next <= S1;
internal_output_next <= "01" ;
end if;
if INPUT = "11" then
internal_state_next <= S3;
internal_output_next <= "11" ;
end if;
when S3 =>
if INPUT = "11" then
internal_state_next <= S1;
internal_output_next <= "01" ;
end if;
if INPUT = "10" then
internal_state_next <= S2;
internal_output_next <= "01" ;
end if;
when others=>
null;
end case;
end process nextState_nextOutput;
--Sync and Reset Logic--
sync_proc : process(clk, rst)
begin
if(rising_edge(CLK)) then
if RST = '1' then
internal_state <= START;
internal_output <= "00";
else
internal_state <= internal_state_next;
internal_output <= internal_output_next;
end if;
end if;
end process sync_proc;
OUTPUT <= internal_output;
STATE <= internal_state;
end behavior;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity uart is
generic(
clk_freq: integer := 50000000;
baud_rate: integer := 115200
);
port(
uart_tx: out std_logic;
data_in: in std_logic_vector(7 downto 0);
ready: out std_logic;
send_data: in std_logic;
rst: in std_logic;
clk: in std_logic
);
end uart;
architecture behavioral of uart is
type uart_state is (reset,waiting,sending);
signal curr_state: uart_state;
signal clock_divide: integer range 0 to 5208 := 0;
signal slow_clock: std_logic := '0';
signal uart_tx_sig: std_logic;
signal current_bit: integer range 0 to 9;
begin
slower_clock: process(clk,rst)
begin
if(rst = '1') then
clock_divide <= 0;
slow_clock <= '0';
elsif(rising_edge(clk)) then
clock_divide <= clock_divide + 1;
if(clock_divide = 215) then -- 651->38400 baud
clock_divide <= 0;
slow_clock <= not slow_clock;
end if;
end if;
end process;
main_uart: process(slow_clock,rst)
begin
if(rst = '1') then
curr_state <= reset;
elsif(rising_edge(slow_clock)) then
case curr_state is
when reset =>
uart_tx_sig <= '1';
curr_state <= waiting;
when waiting =>
ready <= '1';
current_bit <= 0;
uart_tx_sig <= '1';
if(send_data = '1') then
curr_state <= sending;
end if;
when sending =>
ready <= '0';
current_bit <= current_bit + 1;
if(current_bit = 9) then
current_bit <= 0;
uart_tx_sig <= '1';
curr_state <= waiting;
elsif(current_bit = 0) then
uart_tx_sig <= '0';
else
uart_tx_sig <= data_in(current_bit - 1);
end if;
end case;
end if;
end process;
uart_tx <= uart_tx_sig;
end behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity uart is
generic(
clk_freq: integer := 50000000;
baud_rate: integer := 115200
);
port(
uart_tx: out std_logic;
data_in: in std_logic_vector(7 downto 0);
ready: out std_logic;
send_data: in std_logic;
rst: in std_logic;
clk: in std_logic
);
end uart;
architecture behavioral of uart is
type uart_state is (reset,waiting,sending);
signal curr_state: uart_state;
signal clock_divide: integer range 0 to 5208 := 0;
signal slow_clock: std_logic := '0';
signal uart_tx_sig: std_logic;
signal current_bit: integer range 0 to 9;
begin
slower_clock: process(clk,rst)
begin
if(rst = '1') then
clock_divide <= 0;
slow_clock <= '0';
elsif(rising_edge(clk)) then
clock_divide <= clock_divide + 1;
if(clock_divide = 215) then -- 651->38400 baud
clock_divide <= 0;
slow_clock <= not slow_clock;
end if;
end if;
end process;
main_uart: process(slow_clock,rst)
begin
if(rst = '1') then
curr_state <= reset;
elsif(rising_edge(slow_clock)) then
case curr_state is
when reset =>
uart_tx_sig <= '1';
curr_state <= waiting;
when waiting =>
ready <= '1';
current_bit <= 0;
uart_tx_sig <= '1';
if(send_data = '1') then
curr_state <= sending;
end if;
when sending =>
ready <= '0';
current_bit <= current_bit + 1;
if(current_bit = 9) then
current_bit <= 0;
uart_tx_sig <= '1';
curr_state <= waiting;
elsif(current_bit = 0) then
uart_tx_sig <= '0';
else
uart_tx_sig <= data_in(current_bit - 1);
end if;
end case;
end if;
end process;
uart_tx <= uart_tx_sig;
end behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo, mulo, divo, dummy, rp)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
if r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else
xc_vectt := "00" & r.x.ctrl.tt;
end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0';
v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
else
xc_result := r.x.result;
end if;
xc_df_result := xc_result;
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then
v.x.debug := '0';
end if;
pwrd := '0';
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt;
vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find(r);
vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1';
xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r);
xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
else
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
when dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if dbgi.reset = '1' then
vp.pwd := '0';
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then
v.x.debug := '1';
end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address, vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
if r.x.ipend = '1' then
vp.pwd := '0';
end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
if (r.x.rstate = dsu2) then
v.w.except := '0';
end if;
v.w.wa := xc_waddr(7 downto 0);
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.w.s.ef := '0';-- needed for AX
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1;
v.x.debug := '1';
end if;
end if;
if not FPEN then
v.w.s.ef := '0';
end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush, me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify, v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap, v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
v.x.data(0) := dco.data(0);
v.x.data(1) := dco.data(1);
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if (r.x.rstate = dsu2) then
me_nullify2 := '0';
v.x.set := dco.set(0 downto 0);
end if;
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0);
ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2;
ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then
v.m.nalign := '0';
else
v.m.nalign := '1';
end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load);
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res, ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then
v.m.ctrl.ld := '1';
end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt, v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000", r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm, r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2, v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft, v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
de_inst := r.d.inst(conv_integer(r.d.set));
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000";
de_raddr2 := "0000000000";
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst, fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock, v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst), de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch, v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv, de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1, false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2, imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
end if;
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2);
de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000";
v.f.branch := '0';
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
elsif xc_exception = '1' then -- exception
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc);
v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1;-- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
v.d.inst(0) := ico.data(0);-- latch instruction
v.d.inst(1) := ico.data(1);-- latch instruction
v.d.set := ico.set(0 downto 0);-- latch instruction
v.d.mexc := ico.mexc;-- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
muli.acc(39 downto 32) <= r.x.y(7 downto 0);
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else
dsign := r.e.ctrl.inst(19);
end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all;
vfpi.exack := xc_fpexack;
vfpi.a_rs1 := r.a.rs1;
vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or r.d.annul;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0');
vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0');
vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst;
vfpi.a.cnt := r.a.ctrl.cnt;
vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0');
vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst;
vfpi.e.cnt := r.e.ctrl.cnt;
vfpi.e.trap := r.e.ctrl.trap;
vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0');
vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst;
vfpi.m.cnt := r.m.ctrl.cnt;
vfpi.m.trap := r.m.ctrl.trap;
vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0');
vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst;
vfpi.x.cnt := r.x.ctrl.cnt;
vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul;
vfpi.x.pv := r.x.ctrl.pv;
vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then
vfpi.dbg.enable := dbgi.denable;
else
vfpi.dbg.enable := '0';
end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22);-- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi;-- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= '0';
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst;
r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data;
r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1';
r.w.s.ps <= '1';
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then
ir <= irin;
end if;
end if;
end process;
dummy <= '1';
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo, mulo, divo, dummy, rp)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
if r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else
xc_vectt := "00" & r.x.ctrl.tt;
end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0';
v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
else
xc_result := r.x.result;
end if;
xc_df_result := xc_result;
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then
v.x.debug := '0';
end if;
pwrd := '0';
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt;
vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find(r);
vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1';
xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r);
xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
else
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
when dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if dbgi.reset = '1' then
vp.pwd := '0';
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then
v.x.debug := '1';
end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address, vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
if r.x.ipend = '1' then
vp.pwd := '0';
end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
if (r.x.rstate = dsu2) then
v.w.except := '0';
end if;
v.w.wa := xc_waddr(7 downto 0);
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.w.s.ef := '0';-- needed for AX
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1;
v.x.debug := '1';
end if;
end if;
if not FPEN then
v.w.s.ef := '0';
end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush, me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify, v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap, v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
v.x.data(0) := dco.data(0);
v.x.data(1) := dco.data(1);
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if (r.x.rstate = dsu2) then
me_nullify2 := '0';
v.x.set := dco.set(0 downto 0);
end if;
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0);
ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2;
ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then
v.m.nalign := '0';
else
v.m.nalign := '1';
end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load);
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res, ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then
v.m.ctrl.ld := '1';
end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt, v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000", r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm, r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2, v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft, v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
de_inst := r.d.inst(conv_integer(r.d.set));
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000";
de_raddr2 := "0000000000";
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst, fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock, v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst), de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch, v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv, de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1, false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2, imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
end if;
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2);
de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000";
v.f.branch := '0';
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
elsif xc_exception = '1' then -- exception
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc);
v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1;-- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
v.d.inst(0) := ico.data(0);-- latch instruction
v.d.inst(1) := ico.data(1);-- latch instruction
v.d.set := ico.set(0 downto 0);-- latch instruction
v.d.mexc := ico.mexc;-- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
muli.acc(39 downto 32) <= r.x.y(7 downto 0);
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else
dsign := r.e.ctrl.inst(19);
end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all;
vfpi.exack := xc_fpexack;
vfpi.a_rs1 := r.a.rs1;
vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or r.d.annul;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0');
vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0');
vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst;
vfpi.a.cnt := r.a.ctrl.cnt;
vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0');
vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst;
vfpi.e.cnt := r.e.ctrl.cnt;
vfpi.e.trap := r.e.ctrl.trap;
vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0');
vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst;
vfpi.m.cnt := r.m.ctrl.cnt;
vfpi.m.trap := r.m.ctrl.trap;
vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0');
vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst;
vfpi.x.cnt := r.x.ctrl.cnt;
vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul;
vfpi.x.pv := r.x.ctrl.pv;
vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then
vfpi.dbg.enable := dbgi.denable;
else
vfpi.dbg.enable := '0';
end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22);-- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi;-- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= '0';
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst;
r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data;
r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1';
r.w.s.ps <= '1';
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then
ir <= irin;
end if;
end if;
end process;
dummy <= '1';
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Yuan Mei
--
-- Create Date: 23:56:58 10/26/2013
-- Design Name: Convert byte stream into command
-- Module Name: byte2cmd - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY byte2cmd IS
PORT (
CLK : IN std_logic;
RESET : IN std_logic;
-- byte in
RX_DATA : IN std_logic_vector(7 DOWNTO 0);
RX_RDY : IN std_logic;
-- cmd out
CMD_FIFO_Q : OUT std_logic_vector(35 DOWNTO 0); -- command fifo data out port
CMD_FIFO_EMPTY : OUT std_logic; -- command fifo "emtpy" SIGNAL
CMD_FIFO_RDCLK : IN std_logic;
CMD_FIFO_RDREQ : IN std_logic -- command fifo read request
);
END byte2cmd;
ARCHITECTURE Behavioral OF byte2cmd IS
COMPONENT fifo36x512
PORT (
rst : IN std_logic;
wr_clk : IN std_logic;
rd_clk : IN std_logic;
din : IN std_logic_vector(35 DOWNTO 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(35 DOWNTO 0);
full : OUT std_logic;
empty : OUT std_logic
);
END COMPONENT;
SIGNAL sCmdFifoWrClk : std_logic;
SIGNAL sCmdFifoD : std_logic_vector(39 DOWNTO 0);
SIGNAL sCmdFifoWrreq : std_logic;
SIGNAL sCmdFifoFull : std_logic;
SIGNAL sInByte : std_logic_vector(7 DOWNTO 0);
TYPE cmdState_t IS (S0, S1);
SIGNAL cmdState : cmdState_t;
BEGIN
-- cmd FIFO
sCmdFifoWrClk <= CLK;
cmd_fifo : fifo36x512
PORT MAP (
rst => RESET,
wr_clk => sCmdFifoWrClk,
rd_clk => CMD_FIFO_RDCLK,
din => sCmdFifoD(35 DOWNTO 0),
wr_en => sCmdFifoWrreq,
rd_en => CMD_FIFO_RDREQ,
dout => CMD_FIFO_Q,
full => sCmdFifoFull,
empty => CMD_FIFO_EMPTY
);
PROCESS (CLK, RESET) IS
VARIABLE addri : integer RANGE 0 TO 7 :=0;
BEGIN
IF RESET = '1' THEN
addri := 0;
sCmdFifoD <= (OTHERS => '0');
sCmdFifoWrreq <= '0';
sInByte <= x"ff";
cmdState <= S0;
ELSIF falling_edge(CLK) THEN
CASE cmdState IS
WHEN S0 =>
sCmdFifoWrreq <= '0';
IF RX_RDY = '1' THEN
sInByte <= RX_DATA;
addri := to_integer(unsigned(sInByte(7 DOWNTO 5)));
sCmdFifoD((addri+1)*5-1 DOWNTO addri*5) <= sInByte(4 DOWNTO 0);
IF addri = 0 THEN
cmdState <= S1;
END IF;
END IF;
WHEN S1 =>
sCmdFifoWrreq <= '1';
cmdState <= S0;
WHEN OTHERS =>
cmdState <= S0;
END CASE;
END IF;
END PROCESS;
END Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Yuan Mei
--
-- Create Date: 23:56:58 10/26/2013
-- Design Name: Convert byte stream into command
-- Module Name: byte2cmd - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY byte2cmd IS
PORT (
CLK : IN std_logic;
RESET : IN std_logic;
-- byte in
RX_DATA : IN std_logic_vector(7 DOWNTO 0);
RX_RDY : IN std_logic;
-- cmd out
CMD_FIFO_Q : OUT std_logic_vector(35 DOWNTO 0); -- command fifo data out port
CMD_FIFO_EMPTY : OUT std_logic; -- command fifo "emtpy" SIGNAL
CMD_FIFO_RDCLK : IN std_logic;
CMD_FIFO_RDREQ : IN std_logic -- command fifo read request
);
END byte2cmd;
ARCHITECTURE Behavioral OF byte2cmd IS
COMPONENT fifo36x512
PORT (
rst : IN std_logic;
wr_clk : IN std_logic;
rd_clk : IN std_logic;
din : IN std_logic_vector(35 DOWNTO 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(35 DOWNTO 0);
full : OUT std_logic;
empty : OUT std_logic
);
END COMPONENT;
SIGNAL sCmdFifoWrClk : std_logic;
SIGNAL sCmdFifoD : std_logic_vector(39 DOWNTO 0);
SIGNAL sCmdFifoWrreq : std_logic;
SIGNAL sCmdFifoFull : std_logic;
SIGNAL sInByte : std_logic_vector(7 DOWNTO 0);
TYPE cmdState_t IS (S0, S1);
SIGNAL cmdState : cmdState_t;
BEGIN
-- cmd FIFO
sCmdFifoWrClk <= CLK;
cmd_fifo : fifo36x512
PORT MAP (
rst => RESET,
wr_clk => sCmdFifoWrClk,
rd_clk => CMD_FIFO_RDCLK,
din => sCmdFifoD(35 DOWNTO 0),
wr_en => sCmdFifoWrreq,
rd_en => CMD_FIFO_RDREQ,
dout => CMD_FIFO_Q,
full => sCmdFifoFull,
empty => CMD_FIFO_EMPTY
);
PROCESS (CLK, RESET) IS
VARIABLE addri : integer RANGE 0 TO 7 :=0;
BEGIN
IF RESET = '1' THEN
addri := 0;
sCmdFifoD <= (OTHERS => '0');
sCmdFifoWrreq <= '0';
sInByte <= x"ff";
cmdState <= S0;
ELSIF falling_edge(CLK) THEN
CASE cmdState IS
WHEN S0 =>
sCmdFifoWrreq <= '0';
IF RX_RDY = '1' THEN
sInByte <= RX_DATA;
addri := to_integer(unsigned(sInByte(7 DOWNTO 5)));
sCmdFifoD((addri+1)*5-1 DOWNTO addri*5) <= sInByte(4 DOWNTO 0);
IF addri = 0 THEN
cmdState <= S1;
END IF;
END IF;
WHEN S1 =>
sCmdFifoWrreq <= '1';
cmdState <= S0;
WHEN OTHERS =>
cmdState <= S0;
END CASE;
END IF;
END PROCESS;
END Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb_apb
-- File: i2c2ahb_apb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple I2C-slave providing a bridge to AMBA AHB
-- This entity provides an APB interface for setting defining the
-- AHB address window that can be accessed from I2C.
-- See i2c2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.i2c.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.conv_std_logic;
use grlib.stdlib.conv_std_logic_vector;
entity i2c2ahb_apb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2c2ahb_apb;
architecture rtl of i2c2ahb_apb is
-- Register offsets
constant CTRL_OFF : std_logic_vector(4 downto 2) := "000";
constant STS_OFF : std_logic_vector(4 downto 2) := "001";
constant ADDR_OFF : std_logic_vector(4 downto 2) := "010";
constant MASK_OFF : std_logic_vector(4 downto 2) := "011";
constant SLVA_OFF : std_logic_vector(4 downto 2) := "100";
constant SLVC_OFF : std_logic_vector(4 downto 2) := "101";
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2C2AHB, 0, 0, pirq),
1 => apb_iobar(paddr, pmask));
type apb_reg_type is record
i2c2ahbi : i2c2ahb_in_type;
irq : std_ulogic;
irqen : std_ulogic;
prot : std_ulogic;
protx : std_ulogic;
wr : std_ulogic;
dma : std_ulogic;
dmax : std_ulogic;
end record;
signal r, rin : apb_reg_type;
signal i2c2ahbo : i2c2ahb_out_type;
begin
bridge : i2c2ahbx
generic map (hindex => hindex, oepol => oepol, filter => filter)
port map (rstn => rstn, clk => clk, ahbi => ahbi, ahbo => ahbo,
i2ci => i2ci, i2co => i2co, i2c2ahbi => r.i2c2ahbi,
i2c2ahbo => i2c2ahbo);
comb: process (r, rstn, apbi, i2c2ahbo)
variable v : apb_reg_type;
variable apbaddr : std_logic_vector(4 downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable irqout : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; apbaddr := apbi.paddr(apbaddr'range); apbout := (others => '0');
v.irq := '0'; irqout := (others => '0'); irqout(pirq) := r.irq;
v.protx := i2c2ahbo.prot; v.dmax := i2c2ahbo.dma;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when CTRL_OFF => apbout(1 downto 0) := r.irqen & r.i2c2ahbi.en;
when STS_OFF => apbout(2 downto 0) := r.prot & r.wr & r.dma;
when ADDR_OFF => apbout := r.i2c2ahbi.haddr;
when MASK_OFF => apbout := r.i2c2ahbi.hmask;
when SLVA_OFF => apbout(6 downto 0) := r.i2c2ahbi.slvaddr;
when SLVC_OFF => apbout(6 downto 0) := r.i2c2ahbi.cfgaddr;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when CTRL_OFF => v.irqen := apbi.pwdata(1); v.i2c2ahbi.en := apbi.pwdata(0);
when STS_OFF => v.dma := r.dma and not apbi.pwdata(0);
v.prot := r.prot and not apbi.pwdata(2);
when ADDR_OFF => v.i2c2ahbi.haddr := apbi.pwdata;
when MASK_OFF => v.i2c2ahbi.hmask := apbi.pwdata;
when SLVA_OFF => v.i2c2ahbi.slvaddr := apbi.pwdata(6 downto 0);
when SLVC_OFF => v.i2c2ahbi.cfgaddr := apbi.pwdata(6 downto 0);
when others => null;
end case;
end if;
-- interrupt and status register handling
if ((i2c2ahbo.dma and not r.dmax) or
(i2c2ahbo.prot and not r.protx)) = '1' then
v.dma := '1'; v.prot := r.prot or i2c2ahbo.prot; v.wr := i2c2ahbo.wr;
if (r.irqen and not r.dma) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- reset
---------------------------------------------------------------------------
if rstn = '0' then
v.i2c2ahbi.en := conv_std_logic(resen = 1);
v.i2c2ahbi.haddr := conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
v.i2c2ahbi.hmask := conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
v.i2c2ahbi.slvaddr := conv_std_logic_vector(i2cslvaddr, 7);
v.i2c2ahbi.cfgaddr := conv_std_logic_vector(i2ccfgaddr, 7);
v.irqen := '0'; v.prot := '0'; v.wr := '0'; v.dma := '0';
end if;
---------------------------------------------------------------------------
-- signal assignments
---------------------------------------------------------------------------
-- update registers
rin <= v;
-- update outputs
apbo.prdata <= apbout;
apbo.pirq <= irqout;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
end process comb;
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message provided in i2c2ahbx...
end architecture rtl;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity array_io is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
d_o_0_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_0_full_n : IN STD_LOGIC;
d_o_0_write : OUT STD_LOGIC;
d_o_1_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_1_full_n : IN STD_LOGIC;
d_o_1_write : OUT STD_LOGIC;
d_o_2_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_2_full_n : IN STD_LOGIC;
d_o_2_write : OUT STD_LOGIC;
d_o_3_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_3_full_n : IN STD_LOGIC;
d_o_3_write : OUT STD_LOGIC;
d_o_4_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_4_full_n : IN STD_LOGIC;
d_o_4_write : OUT STD_LOGIC;
d_o_5_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_5_full_n : IN STD_LOGIC;
d_o_5_write : OUT STD_LOGIC;
d_o_6_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_6_full_n : IN STD_LOGIC;
d_o_6_write : OUT STD_LOGIC;
d_o_7_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_7_full_n : IN STD_LOGIC;
d_o_7_write : OUT STD_LOGIC;
d_o_8_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_8_full_n : IN STD_LOGIC;
d_o_8_write : OUT STD_LOGIC;
d_o_9_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_9_full_n : IN STD_LOGIC;
d_o_9_write : OUT STD_LOGIC;
d_o_10_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_10_full_n : IN STD_LOGIC;
d_o_10_write : OUT STD_LOGIC;
d_o_11_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_11_full_n : IN STD_LOGIC;
d_o_11_write : OUT STD_LOGIC;
d_o_12_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_12_full_n : IN STD_LOGIC;
d_o_12_write : OUT STD_LOGIC;
d_o_13_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_13_full_n : IN STD_LOGIC;
d_o_13_write : OUT STD_LOGIC;
d_o_14_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_14_full_n : IN STD_LOGIC;
d_o_14_write : OUT STD_LOGIC;
d_o_15_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_15_full_n : IN STD_LOGIC;
d_o_15_write : OUT STD_LOGIC;
d_o_16_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_16_full_n : IN STD_LOGIC;
d_o_16_write : OUT STD_LOGIC;
d_o_17_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_17_full_n : IN STD_LOGIC;
d_o_17_write : OUT STD_LOGIC;
d_o_18_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_18_full_n : IN STD_LOGIC;
d_o_18_write : OUT STD_LOGIC;
d_o_19_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_19_full_n : IN STD_LOGIC;
d_o_19_write : OUT STD_LOGIC;
d_o_20_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_20_full_n : IN STD_LOGIC;
d_o_20_write : OUT STD_LOGIC;
d_o_21_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_21_full_n : IN STD_LOGIC;
d_o_21_write : OUT STD_LOGIC;
d_o_22_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_22_full_n : IN STD_LOGIC;
d_o_22_write : OUT STD_LOGIC;
d_o_23_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_23_full_n : IN STD_LOGIC;
d_o_23_write : OUT STD_LOGIC;
d_o_24_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_24_full_n : IN STD_LOGIC;
d_o_24_write : OUT STD_LOGIC;
d_o_25_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_25_full_n : IN STD_LOGIC;
d_o_25_write : OUT STD_LOGIC;
d_o_26_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_26_full_n : IN STD_LOGIC;
d_o_26_write : OUT STD_LOGIC;
d_o_27_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_27_full_n : IN STD_LOGIC;
d_o_27_write : OUT STD_LOGIC;
d_o_28_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_28_full_n : IN STD_LOGIC;
d_o_28_write : OUT STD_LOGIC;
d_o_29_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_29_full_n : IN STD_LOGIC;
d_o_29_write : OUT STD_LOGIC;
d_o_30_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_30_full_n : IN STD_LOGIC;
d_o_30_write : OUT STD_LOGIC;
d_o_31_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_31_full_n : IN STD_LOGIC;
d_o_31_write : OUT STD_LOGIC;
d_i_0 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_1 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_2 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_3 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_4 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_5 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_6 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_7 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_8 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_9 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_10 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_11 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_12 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_13 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_14 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_15 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_16 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_17 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_18 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_19 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_20 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_21 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_22 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_23 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_24 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_25 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_26 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_27 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_28 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_29 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_30 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_31 : IN STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of array_io is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"array_io,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.359333,HLS_SYN_LAT=2,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=3395,HLS_SYN_LUT=1855}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (2 downto 0) := "010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (2 downto 0) := "100";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (2 downto 0) := "001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal acc_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal d_o_0_blk_n : STD_LOGIC;
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal d_o_1_blk_n : STD_LOGIC;
signal d_o_2_blk_n : STD_LOGIC;
signal d_o_3_blk_n : STD_LOGIC;
signal d_o_4_blk_n : STD_LOGIC;
signal d_o_5_blk_n : STD_LOGIC;
signal d_o_6_blk_n : STD_LOGIC;
signal d_o_7_blk_n : STD_LOGIC;
signal d_o_8_blk_n : STD_LOGIC;
signal d_o_9_blk_n : STD_LOGIC;
signal d_o_10_blk_n : STD_LOGIC;
signal d_o_11_blk_n : STD_LOGIC;
signal d_o_12_blk_n : STD_LOGIC;
signal d_o_13_blk_n : STD_LOGIC;
signal d_o_14_blk_n : STD_LOGIC;
signal d_o_15_blk_n : STD_LOGIC;
signal d_o_16_blk_n : STD_LOGIC;
signal d_o_17_blk_n : STD_LOGIC;
signal d_o_18_blk_n : STD_LOGIC;
signal d_o_19_blk_n : STD_LOGIC;
signal d_o_20_blk_n : STD_LOGIC;
signal d_o_21_blk_n : STD_LOGIC;
signal d_o_22_blk_n : STD_LOGIC;
signal d_o_23_blk_n : STD_LOGIC;
signal d_o_24_blk_n : STD_LOGIC;
signal d_o_25_blk_n : STD_LOGIC;
signal d_o_26_blk_n : STD_LOGIC;
signal d_o_27_blk_n : STD_LOGIC;
signal d_o_28_blk_n : STD_LOGIC;
signal d_o_29_blk_n : STD_LOGIC;
signal d_o_30_blk_n : STD_LOGIC;
signal d_o_31_blk_n : STD_LOGIC;
signal tmp_8_fu_586_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_reg_1228 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_1_fu_600_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_1_reg_1244 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_2_fu_614_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_2_reg_1260 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_3_fu_628_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_3_reg_1276 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_4_fu_642_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_4_reg_1292 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_5_fu_656_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_5_reg_1308 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_6_fu_670_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_6_reg_1324 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_7_fu_684_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_7_reg_1340 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp3_fu_726_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp3_reg_1391 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp6_fu_736_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp6_reg_1401 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp9_fu_746_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp9_reg_1411 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp12_fu_756_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp12_reg_1421 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp15_fu_766_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp15_reg_1431 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp18_fu_776_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp18_reg_1441 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp21_fu_786_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp21_reg_1451 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp24_fu_796_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp24_reg_1461 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_8_fu_830_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_8_reg_1466 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal tmp_1_9_fu_839_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_9_reg_1471 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_s_fu_848_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_s_reg_1476 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_10_fu_857_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_10_reg_1481 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_11_fu_866_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_11_reg_1486 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_12_fu_875_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_12_reg_1491 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_13_fu_884_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_13_reg_1496 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_14_fu_893_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_14_reg_1501 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_15_fu_898_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_15_reg_1506 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_16_fu_903_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_16_reg_1512 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_17_fu_908_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_17_reg_1518 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_18_fu_913_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_18_reg_1524 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_19_fu_918_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_19_reg_1530 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_20_fu_923_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_20_reg_1536 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_21_fu_928_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_21_reg_1542 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_22_fu_933_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_22_reg_1548 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_block_state3 : BOOLEAN;
signal temp_s_fu_956_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_1_fu_986_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_fu_1016_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_3_fu_1046_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_4_fu_1076_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_5_fu_1106_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_6_fu_1136_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_7_fu_1166_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_582_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_9_fu_596_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_10_fu_610_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_11_fu_624_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_12_fu_638_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_13_fu_652_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_14_fu_666_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_15_fu_680_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_16_cast_fu_690_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_24_cast_fu_722_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_17_cast_fu_694_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_25_cast_fu_732_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_18_cast_fu_698_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_26_cast_fu_742_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_19_cast_fu_702_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_27_cast_fu_752_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_20_cast_fu_706_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_28_cast_fu_762_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_21_cast_fu_710_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_29_cast_fu_772_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_22_cast_fu_714_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_30_cast_fu_782_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_23_cast_fu_718_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_31_cast_fu_792_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_fu_802_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp3_cast_fu_943_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_8_cast_fu_826_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp2_fu_946_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp2_cast_fu_952_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp1_fu_938_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_s_fu_805_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp6_cast_fu_973_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_9_cast_fu_835_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp5_fu_976_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp5_cast_fu_982_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp4_fu_968_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_808_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp9_cast_fu_1003_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_10_cast_fu_844_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp8_fu_1006_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp8_cast_fu_1012_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp7_fu_998_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_fu_811_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp12_cast_fu_1033_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_11_cast_fu_853_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp11_fu_1036_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp11_cast_fu_1042_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp10_fu_1028_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_fu_814_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp15_cast_fu_1063_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_12_cast_fu_862_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp14_fu_1066_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp14_cast_fu_1072_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp13_fu_1058_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_fu_817_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp18_cast_fu_1093_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_13_cast_fu_871_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp17_fu_1096_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp17_cast_fu_1102_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp16_fu_1088_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_fu_820_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp21_cast_fu_1123_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_14_cast_fu_880_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp20_fu_1126_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp20_cast_fu_1132_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp19_fu_1118_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_fu_823_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp24_cast_fu_1153_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_15_cast_fu_889_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp23_fu_1156_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp23_cast_fu_1162_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp22_fu_1148_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (2 downto 0);
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
acc_0 <= temp_s_fu_956_p2;
acc_1 <= temp_1_fu_986_p2;
acc_2 <= temp_2_fu_1016_p2;
acc_3 <= temp_3_fu_1046_p2;
acc_4 <= temp_4_fu_1076_p2;
acc_5 <= temp_5_fu_1106_p2;
acc_6 <= temp_6_fu_1136_p2;
acc_7 <= temp_7_fu_1166_p2;
tmp_1_10_reg_1481 <= tmp_1_10_fu_857_p2;
tmp_1_11_reg_1486 <= tmp_1_11_fu_866_p2;
tmp_1_12_reg_1491 <= tmp_1_12_fu_875_p2;
tmp_1_13_reg_1496 <= tmp_1_13_fu_884_p2;
tmp_1_14_reg_1501 <= tmp_1_14_fu_893_p2;
tmp_1_15_reg_1506 <= tmp_1_15_fu_898_p2;
tmp_1_16_reg_1512 <= tmp_1_16_fu_903_p2;
tmp_1_17_reg_1518 <= tmp_1_17_fu_908_p2;
tmp_1_18_reg_1524 <= tmp_1_18_fu_913_p2;
tmp_1_19_reg_1530 <= tmp_1_19_fu_918_p2;
tmp_1_20_reg_1536 <= tmp_1_20_fu_923_p2;
tmp_1_21_reg_1542 <= tmp_1_21_fu_928_p2;
tmp_1_22_reg_1548 <= tmp_1_22_fu_933_p2;
tmp_1_8_reg_1466 <= tmp_1_8_fu_830_p2;
tmp_1_9_reg_1471 <= tmp_1_9_fu_839_p2;
tmp_1_s_reg_1476 <= tmp_1_s_fu_848_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
tmp12_reg_1421 <= tmp12_fu_756_p2;
tmp15_reg_1431 <= tmp15_fu_766_p2;
tmp18_reg_1441 <= tmp18_fu_776_p2;
tmp21_reg_1451 <= tmp21_fu_786_p2;
tmp24_reg_1461 <= tmp24_fu_796_p2;
tmp3_reg_1391 <= tmp3_fu_726_p2;
tmp6_reg_1401 <= tmp6_fu_736_p2;
tmp9_reg_1411 <= tmp9_fu_746_p2;
tmp_1_1_reg_1244 <= tmp_1_1_fu_600_p2;
tmp_1_2_reg_1260 <= tmp_1_2_fu_614_p2;
tmp_1_3_reg_1276 <= tmp_1_3_fu_628_p2;
tmp_1_4_reg_1292 <= tmp_1_4_fu_642_p2;
tmp_1_5_reg_1308 <= tmp_1_5_fu_656_p2;
tmp_1_6_reg_1324 <= tmp_1_6_fu_670_p2;
tmp_1_7_reg_1340 <= tmp_1_7_fu_684_p2;
tmp_8_reg_1228 <= tmp_8_fu_586_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when others =>
ap_NS_fsm <= "XXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_block_state3_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n)
begin
ap_block_state3 <= ((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n));
end process;
ap_done_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
d_o_0_blk_n_assign_proc : process(d_o_0_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_0_blk_n <= d_o_0_full_n;
else
d_o_0_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_0_din <= tmp_8_reg_1228;
d_o_0_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_0_write <= ap_const_logic_1;
else
d_o_0_write <= ap_const_logic_0;
end if;
end process;
d_o_10_blk_n_assign_proc : process(d_o_10_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_10_blk_n <= d_o_10_full_n;
else
d_o_10_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_10_din <= tmp_1_s_reg_1476;
d_o_10_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_10_write <= ap_const_logic_1;
else
d_o_10_write <= ap_const_logic_0;
end if;
end process;
d_o_11_blk_n_assign_proc : process(d_o_11_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_11_blk_n <= d_o_11_full_n;
else
d_o_11_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_11_din <= tmp_1_10_reg_1481;
d_o_11_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_11_write <= ap_const_logic_1;
else
d_o_11_write <= ap_const_logic_0;
end if;
end process;
d_o_12_blk_n_assign_proc : process(d_o_12_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_12_blk_n <= d_o_12_full_n;
else
d_o_12_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_12_din <= tmp_1_11_reg_1486;
d_o_12_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_12_write <= ap_const_logic_1;
else
d_o_12_write <= ap_const_logic_0;
end if;
end process;
d_o_13_blk_n_assign_proc : process(d_o_13_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_13_blk_n <= d_o_13_full_n;
else
d_o_13_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_13_din <= tmp_1_12_reg_1491;
d_o_13_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_13_write <= ap_const_logic_1;
else
d_o_13_write <= ap_const_logic_0;
end if;
end process;
d_o_14_blk_n_assign_proc : process(d_o_14_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_14_blk_n <= d_o_14_full_n;
else
d_o_14_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_14_din <= tmp_1_13_reg_1496;
d_o_14_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_14_write <= ap_const_logic_1;
else
d_o_14_write <= ap_const_logic_0;
end if;
end process;
d_o_15_blk_n_assign_proc : process(d_o_15_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_15_blk_n <= d_o_15_full_n;
else
d_o_15_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_15_din <= tmp_1_14_reg_1501;
d_o_15_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_15_write <= ap_const_logic_1;
else
d_o_15_write <= ap_const_logic_0;
end if;
end process;
d_o_16_blk_n_assign_proc : process(d_o_16_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_16_blk_n <= d_o_16_full_n;
else
d_o_16_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_16_din <= tmp_1_15_reg_1506;
d_o_16_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_16_write <= ap_const_logic_1;
else
d_o_16_write <= ap_const_logic_0;
end if;
end process;
d_o_17_blk_n_assign_proc : process(d_o_17_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_17_blk_n <= d_o_17_full_n;
else
d_o_17_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_17_din <= tmp_1_16_reg_1512;
d_o_17_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_17_write <= ap_const_logic_1;
else
d_o_17_write <= ap_const_logic_0;
end if;
end process;
d_o_18_blk_n_assign_proc : process(d_o_18_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_18_blk_n <= d_o_18_full_n;
else
d_o_18_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_18_din <= tmp_1_17_reg_1518;
d_o_18_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_18_write <= ap_const_logic_1;
else
d_o_18_write <= ap_const_logic_0;
end if;
end process;
d_o_19_blk_n_assign_proc : process(d_o_19_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_19_blk_n <= d_o_19_full_n;
else
d_o_19_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_19_din <= tmp_1_18_reg_1524;
d_o_19_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_19_write <= ap_const_logic_1;
else
d_o_19_write <= ap_const_logic_0;
end if;
end process;
d_o_1_blk_n_assign_proc : process(d_o_1_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_1_blk_n <= d_o_1_full_n;
else
d_o_1_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_1_din <= tmp_1_1_reg_1244;
d_o_1_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_1_write <= ap_const_logic_1;
else
d_o_1_write <= ap_const_logic_0;
end if;
end process;
d_o_20_blk_n_assign_proc : process(d_o_20_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_20_blk_n <= d_o_20_full_n;
else
d_o_20_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_20_din <= tmp_1_19_reg_1530;
d_o_20_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_20_write <= ap_const_logic_1;
else
d_o_20_write <= ap_const_logic_0;
end if;
end process;
d_o_21_blk_n_assign_proc : process(d_o_21_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_21_blk_n <= d_o_21_full_n;
else
d_o_21_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_21_din <= tmp_1_20_reg_1536;
d_o_21_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_21_write <= ap_const_logic_1;
else
d_o_21_write <= ap_const_logic_0;
end if;
end process;
d_o_22_blk_n_assign_proc : process(d_o_22_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_22_blk_n <= d_o_22_full_n;
else
d_o_22_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_22_din <= tmp_1_21_reg_1542;
d_o_22_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_22_write <= ap_const_logic_1;
else
d_o_22_write <= ap_const_logic_0;
end if;
end process;
d_o_23_blk_n_assign_proc : process(d_o_23_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_23_blk_n <= d_o_23_full_n;
else
d_o_23_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_23_din <= tmp_1_22_reg_1548;
d_o_23_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_23_write <= ap_const_logic_1;
else
d_o_23_write <= ap_const_logic_0;
end if;
end process;
d_o_24_blk_n_assign_proc : process(d_o_24_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_24_blk_n <= d_o_24_full_n;
else
d_o_24_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_24_din <= std_logic_vector(unsigned(d_i_24) + unsigned(tmp_1_15_reg_1506));
d_o_24_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_24_write <= ap_const_logic_1;
else
d_o_24_write <= ap_const_logic_0;
end if;
end process;
d_o_25_blk_n_assign_proc : process(d_o_25_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_25_blk_n <= d_o_25_full_n;
else
d_o_25_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_25_din <= std_logic_vector(unsigned(d_i_25) + unsigned(tmp_1_16_reg_1512));
d_o_25_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_25_write <= ap_const_logic_1;
else
d_o_25_write <= ap_const_logic_0;
end if;
end process;
d_o_26_blk_n_assign_proc : process(d_o_26_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_26_blk_n <= d_o_26_full_n;
else
d_o_26_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_26_din <= std_logic_vector(unsigned(d_i_26) + unsigned(tmp_1_17_reg_1518));
d_o_26_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_26_write <= ap_const_logic_1;
else
d_o_26_write <= ap_const_logic_0;
end if;
end process;
d_o_27_blk_n_assign_proc : process(d_o_27_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_27_blk_n <= d_o_27_full_n;
else
d_o_27_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_27_din <= std_logic_vector(unsigned(d_i_27) + unsigned(tmp_1_18_reg_1524));
d_o_27_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_27_write <= ap_const_logic_1;
else
d_o_27_write <= ap_const_logic_0;
end if;
end process;
d_o_28_blk_n_assign_proc : process(d_o_28_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_28_blk_n <= d_o_28_full_n;
else
d_o_28_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_28_din <= std_logic_vector(unsigned(d_i_28) + unsigned(tmp_1_19_reg_1530));
d_o_28_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_28_write <= ap_const_logic_1;
else
d_o_28_write <= ap_const_logic_0;
end if;
end process;
d_o_29_blk_n_assign_proc : process(d_o_29_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_29_blk_n <= d_o_29_full_n;
else
d_o_29_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_29_din <= std_logic_vector(unsigned(d_i_29) + unsigned(tmp_1_20_reg_1536));
d_o_29_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_29_write <= ap_const_logic_1;
else
d_o_29_write <= ap_const_logic_0;
end if;
end process;
d_o_2_blk_n_assign_proc : process(d_o_2_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_2_blk_n <= d_o_2_full_n;
else
d_o_2_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_2_din <= tmp_1_2_reg_1260;
d_o_2_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_2_write <= ap_const_logic_1;
else
d_o_2_write <= ap_const_logic_0;
end if;
end process;
d_o_30_blk_n_assign_proc : process(d_o_30_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_30_blk_n <= d_o_30_full_n;
else
d_o_30_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_30_din <= std_logic_vector(unsigned(d_i_30) + unsigned(tmp_1_21_reg_1542));
d_o_30_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_30_write <= ap_const_logic_1;
else
d_o_30_write <= ap_const_logic_0;
end if;
end process;
d_o_31_blk_n_assign_proc : process(d_o_31_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_31_blk_n <= d_o_31_full_n;
else
d_o_31_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_31_din <= std_logic_vector(unsigned(d_i_31) + unsigned(tmp_1_22_reg_1548));
d_o_31_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_31_write <= ap_const_logic_1;
else
d_o_31_write <= ap_const_logic_0;
end if;
end process;
d_o_3_blk_n_assign_proc : process(d_o_3_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_3_blk_n <= d_o_3_full_n;
else
d_o_3_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_3_din <= tmp_1_3_reg_1276;
d_o_3_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_3_write <= ap_const_logic_1;
else
d_o_3_write <= ap_const_logic_0;
end if;
end process;
d_o_4_blk_n_assign_proc : process(d_o_4_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_4_blk_n <= d_o_4_full_n;
else
d_o_4_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_4_din <= tmp_1_4_reg_1292;
d_o_4_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_4_write <= ap_const_logic_1;
else
d_o_4_write <= ap_const_logic_0;
end if;
end process;
d_o_5_blk_n_assign_proc : process(d_o_5_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_5_blk_n <= d_o_5_full_n;
else
d_o_5_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_5_din <= tmp_1_5_reg_1308;
d_o_5_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_5_write <= ap_const_logic_1;
else
d_o_5_write <= ap_const_logic_0;
end if;
end process;
d_o_6_blk_n_assign_proc : process(d_o_6_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_6_blk_n <= d_o_6_full_n;
else
d_o_6_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_6_din <= tmp_1_6_reg_1324;
d_o_6_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_6_write <= ap_const_logic_1;
else
d_o_6_write <= ap_const_logic_0;
end if;
end process;
d_o_7_blk_n_assign_proc : process(d_o_7_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_7_blk_n <= d_o_7_full_n;
else
d_o_7_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_7_din <= tmp_1_7_reg_1340;
d_o_7_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_7_write <= ap_const_logic_1;
else
d_o_7_write <= ap_const_logic_0;
end if;
end process;
d_o_8_blk_n_assign_proc : process(d_o_8_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_8_blk_n <= d_o_8_full_n;
else
d_o_8_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_8_din <= tmp_1_8_reg_1466;
d_o_8_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_8_write <= ap_const_logic_1;
else
d_o_8_write <= ap_const_logic_0;
end if;
end process;
d_o_9_blk_n_assign_proc : process(d_o_9_full_n, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_9_blk_n <= d_o_9_full_n;
else
d_o_9_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_9_din <= tmp_1_9_reg_1471;
d_o_9_write_assign_proc : process(d_o_0_full_n, d_o_1_full_n, d_o_2_full_n, d_o_3_full_n, d_o_4_full_n, d_o_5_full_n, d_o_6_full_n, d_o_7_full_n, d_o_8_full_n, d_o_9_full_n, d_o_10_full_n, d_o_11_full_n, d_o_12_full_n, d_o_13_full_n, d_o_14_full_n, d_o_15_full_n, d_o_16_full_n, d_o_17_full_n, d_o_18_full_n, d_o_19_full_n, d_o_20_full_n, d_o_21_full_n, d_o_22_full_n, d_o_23_full_n, d_o_24_full_n, d_o_25_full_n, d_o_26_full_n, d_o_27_full_n, d_o_28_full_n, d_o_29_full_n, d_o_30_full_n, d_o_31_full_n, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and not(((ap_const_logic_0 = d_o_0_full_n) or (ap_const_logic_0 = d_o_1_full_n) or (ap_const_logic_0 = d_o_2_full_n) or (ap_const_logic_0 = d_o_3_full_n) or (ap_const_logic_0 = d_o_4_full_n) or (ap_const_logic_0 = d_o_5_full_n) or (ap_const_logic_0 = d_o_6_full_n) or (ap_const_logic_0 = d_o_7_full_n) or (ap_const_logic_0 = d_o_8_full_n) or (ap_const_logic_0 = d_o_9_full_n) or (ap_const_logic_0 = d_o_10_full_n) or (ap_const_logic_0 = d_o_11_full_n) or (ap_const_logic_0 = d_o_12_full_n) or (ap_const_logic_0 = d_o_13_full_n) or (ap_const_logic_0 = d_o_14_full_n) or (ap_const_logic_0 = d_o_15_full_n) or (ap_const_logic_0 = d_o_16_full_n) or (ap_const_logic_0 = d_o_17_full_n) or (ap_const_logic_0 = d_o_18_full_n) or (ap_const_logic_0 = d_o_19_full_n) or (ap_const_logic_0 = d_o_20_full_n) or (ap_const_logic_0 = d_o_21_full_n) or (ap_const_logic_0 = d_o_22_full_n) or (ap_const_logic_0 = d_o_23_full_n) or (ap_const_logic_0 = d_o_24_full_n) or (ap_const_logic_0 = d_o_25_full_n) or (ap_const_logic_0 = d_o_26_full_n) or (ap_const_logic_0 = d_o_27_full_n) or (ap_const_logic_0 = d_o_28_full_n) or (ap_const_logic_0 = d_o_29_full_n) or (ap_const_logic_0 = d_o_30_full_n) or (ap_const_logic_0 = d_o_31_full_n))))) then
d_o_9_write <= ap_const_logic_1;
else
d_o_9_write <= ap_const_logic_0;
end if;
end process;
temp_1_fu_986_p2 <= std_logic_vector(signed(tmp5_cast_fu_982_p1) + signed(tmp4_fu_968_p2));
temp_2_fu_1016_p2 <= std_logic_vector(signed(tmp8_cast_fu_1012_p1) + signed(tmp7_fu_998_p2));
temp_3_fu_1046_p2 <= std_logic_vector(signed(tmp11_cast_fu_1042_p1) + signed(tmp10_fu_1028_p2));
temp_4_fu_1076_p2 <= std_logic_vector(signed(tmp14_cast_fu_1072_p1) + signed(tmp13_fu_1058_p2));
temp_5_fu_1106_p2 <= std_logic_vector(signed(tmp17_cast_fu_1102_p1) + signed(tmp16_fu_1088_p2));
temp_6_fu_1136_p2 <= std_logic_vector(signed(tmp20_cast_fu_1132_p1) + signed(tmp19_fu_1118_p2));
temp_7_fu_1166_p2 <= std_logic_vector(signed(tmp23_cast_fu_1162_p1) + signed(tmp22_fu_1148_p2));
temp_s_fu_956_p2 <= std_logic_vector(signed(tmp2_cast_fu_952_p1) + signed(tmp1_fu_938_p2));
tmp10_fu_1028_p2 <= std_logic_vector(unsigned(acc_3) + unsigned(tmp_3_fu_811_p1));
tmp11_cast_fu_1042_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp11_fu_1036_p2),32));
tmp11_fu_1036_p2 <= std_logic_vector(signed(tmp12_cast_fu_1033_p1) + signed(tmp_11_cast_fu_853_p1));
tmp12_cast_fu_1033_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp12_reg_1421),18));
tmp12_fu_756_p2 <= std_logic_vector(signed(tmp_19_cast_fu_702_p1) + signed(tmp_27_cast_fu_752_p1));
tmp13_fu_1058_p2 <= std_logic_vector(unsigned(acc_4) + unsigned(tmp_4_fu_814_p1));
tmp14_cast_fu_1072_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp14_fu_1066_p2),32));
tmp14_fu_1066_p2 <= std_logic_vector(signed(tmp15_cast_fu_1063_p1) + signed(tmp_12_cast_fu_862_p1));
tmp15_cast_fu_1063_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp15_reg_1431),18));
tmp15_fu_766_p2 <= std_logic_vector(signed(tmp_20_cast_fu_706_p1) + signed(tmp_28_cast_fu_762_p1));
tmp16_fu_1088_p2 <= std_logic_vector(unsigned(acc_5) + unsigned(tmp_5_fu_817_p1));
tmp17_cast_fu_1102_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp17_fu_1096_p2),32));
tmp17_fu_1096_p2 <= std_logic_vector(signed(tmp18_cast_fu_1093_p1) + signed(tmp_13_cast_fu_871_p1));
tmp18_cast_fu_1093_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp18_reg_1441),18));
tmp18_fu_776_p2 <= std_logic_vector(signed(tmp_21_cast_fu_710_p1) + signed(tmp_29_cast_fu_772_p1));
tmp19_fu_1118_p2 <= std_logic_vector(unsigned(acc_6) + unsigned(tmp_6_fu_820_p1));
tmp1_fu_938_p2 <= std_logic_vector(unsigned(acc_0) + unsigned(tmp_fu_802_p1));
tmp20_cast_fu_1132_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp20_fu_1126_p2),32));
tmp20_fu_1126_p2 <= std_logic_vector(signed(tmp21_cast_fu_1123_p1) + signed(tmp_14_cast_fu_880_p1));
tmp21_cast_fu_1123_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp21_reg_1451),18));
tmp21_fu_786_p2 <= std_logic_vector(signed(tmp_22_cast_fu_714_p1) + signed(tmp_30_cast_fu_782_p1));
tmp22_fu_1148_p2 <= std_logic_vector(unsigned(acc_7) + unsigned(tmp_7_fu_823_p1));
tmp23_cast_fu_1162_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp23_fu_1156_p2),32));
tmp23_fu_1156_p2 <= std_logic_vector(signed(tmp24_cast_fu_1153_p1) + signed(tmp_15_cast_fu_889_p1));
tmp24_cast_fu_1153_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp24_reg_1461),18));
tmp24_fu_796_p2 <= std_logic_vector(signed(tmp_23_cast_fu_718_p1) + signed(tmp_31_cast_fu_792_p1));
tmp2_cast_fu_952_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp2_fu_946_p2),32));
tmp2_fu_946_p2 <= std_logic_vector(signed(tmp3_cast_fu_943_p1) + signed(tmp_8_cast_fu_826_p1));
tmp3_cast_fu_943_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp3_reg_1391),18));
tmp3_fu_726_p2 <= std_logic_vector(signed(tmp_16_cast_fu_690_p1) + signed(tmp_24_cast_fu_722_p1));
tmp4_fu_968_p2 <= std_logic_vector(unsigned(acc_1) + unsigned(tmp_s_fu_805_p1));
tmp5_cast_fu_982_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp5_fu_976_p2),32));
tmp5_fu_976_p2 <= std_logic_vector(signed(tmp6_cast_fu_973_p1) + signed(tmp_9_cast_fu_835_p1));
tmp6_cast_fu_973_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp6_reg_1401),18));
tmp6_fu_736_p2 <= std_logic_vector(signed(tmp_17_cast_fu_694_p1) + signed(tmp_25_cast_fu_732_p1));
tmp7_fu_998_p2 <= std_logic_vector(unsigned(acc_2) + unsigned(tmp_2_fu_808_p1));
tmp8_cast_fu_1012_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp8_fu_1006_p2),32));
tmp8_fu_1006_p2 <= std_logic_vector(signed(tmp9_cast_fu_1003_p1) + signed(tmp_10_cast_fu_844_p1));
tmp9_cast_fu_1003_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp9_reg_1411),18));
tmp9_fu_746_p2 <= std_logic_vector(signed(tmp_18_cast_fu_698_p1) + signed(tmp_26_cast_fu_742_p1));
tmp_10_cast_fu_844_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_10),18));
tmp_10_fu_610_p1 <= acc_2(16 - 1 downto 0);
tmp_11_cast_fu_853_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_11),18));
tmp_11_fu_624_p1 <= acc_3(16 - 1 downto 0);
tmp_12_cast_fu_862_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_12),18));
tmp_12_fu_638_p1 <= acc_4(16 - 1 downto 0);
tmp_13_cast_fu_871_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_13),18));
tmp_13_fu_652_p1 <= acc_5(16 - 1 downto 0);
tmp_14_cast_fu_880_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_14),18));
tmp_14_fu_666_p1 <= acc_6(16 - 1 downto 0);
tmp_15_cast_fu_889_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_15),18));
tmp_15_fu_680_p1 <= acc_7(16 - 1 downto 0);
tmp_16_cast_fu_690_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_16),17));
tmp_17_cast_fu_694_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_17),17));
tmp_18_cast_fu_698_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_18),17));
tmp_19_cast_fu_702_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_19),17));
tmp_1_10_fu_857_p2 <= std_logic_vector(unsigned(d_i_11) + unsigned(tmp_1_3_reg_1276));
tmp_1_11_fu_866_p2 <= std_logic_vector(unsigned(d_i_12) + unsigned(tmp_1_4_reg_1292));
tmp_1_12_fu_875_p2 <= std_logic_vector(unsigned(d_i_13) + unsigned(tmp_1_5_reg_1308));
tmp_1_13_fu_884_p2 <= std_logic_vector(unsigned(d_i_14) + unsigned(tmp_1_6_reg_1324));
tmp_1_14_fu_893_p2 <= std_logic_vector(unsigned(d_i_15) + unsigned(tmp_1_7_reg_1340));
tmp_1_15_fu_898_p2 <= std_logic_vector(unsigned(d_i_16) + unsigned(tmp_1_8_fu_830_p2));
tmp_1_16_fu_903_p2 <= std_logic_vector(unsigned(d_i_17) + unsigned(tmp_1_9_fu_839_p2));
tmp_1_17_fu_908_p2 <= std_logic_vector(unsigned(d_i_18) + unsigned(tmp_1_s_fu_848_p2));
tmp_1_18_fu_913_p2 <= std_logic_vector(unsigned(d_i_19) + unsigned(tmp_1_10_fu_857_p2));
tmp_1_19_fu_918_p2 <= std_logic_vector(unsigned(d_i_20) + unsigned(tmp_1_11_fu_866_p2));
tmp_1_1_fu_600_p2 <= std_logic_vector(unsigned(d_i_1) + unsigned(tmp_9_fu_596_p1));
tmp_1_20_fu_923_p2 <= std_logic_vector(unsigned(d_i_21) + unsigned(tmp_1_12_fu_875_p2));
tmp_1_21_fu_928_p2 <= std_logic_vector(unsigned(d_i_22) + unsigned(tmp_1_13_fu_884_p2));
tmp_1_22_fu_933_p2 <= std_logic_vector(unsigned(d_i_23) + unsigned(tmp_1_14_fu_893_p2));
tmp_1_2_fu_614_p2 <= std_logic_vector(unsigned(d_i_2) + unsigned(tmp_10_fu_610_p1));
tmp_1_3_fu_628_p2 <= std_logic_vector(unsigned(d_i_3) + unsigned(tmp_11_fu_624_p1));
tmp_1_4_fu_642_p2 <= std_logic_vector(unsigned(d_i_4) + unsigned(tmp_12_fu_638_p1));
tmp_1_5_fu_656_p2 <= std_logic_vector(unsigned(d_i_5) + unsigned(tmp_13_fu_652_p1));
tmp_1_6_fu_670_p2 <= std_logic_vector(unsigned(d_i_6) + unsigned(tmp_14_fu_666_p1));
tmp_1_7_fu_684_p2 <= std_logic_vector(unsigned(d_i_7) + unsigned(tmp_15_fu_680_p1));
tmp_1_8_fu_830_p2 <= std_logic_vector(unsigned(d_i_8) + unsigned(tmp_8_reg_1228));
tmp_1_9_fu_839_p2 <= std_logic_vector(unsigned(d_i_9) + unsigned(tmp_1_1_reg_1244));
tmp_1_fu_582_p1 <= acc_0(16 - 1 downto 0);
tmp_1_s_fu_848_p2 <= std_logic_vector(unsigned(d_i_10) + unsigned(tmp_1_2_reg_1260));
tmp_20_cast_fu_706_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_20),17));
tmp_21_cast_fu_710_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_21),17));
tmp_22_cast_fu_714_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_22),17));
tmp_23_cast_fu_718_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_23),17));
tmp_24_cast_fu_722_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_24),17));
tmp_25_cast_fu_732_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_25),17));
tmp_26_cast_fu_742_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_26),17));
tmp_27_cast_fu_752_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_27),17));
tmp_28_cast_fu_762_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_28),17));
tmp_29_cast_fu_772_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_29),17));
tmp_2_fu_808_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_2),32));
tmp_30_cast_fu_782_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_30),17));
tmp_31_cast_fu_792_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_31),17));
tmp_3_fu_811_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_3),32));
tmp_4_fu_814_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_4),32));
tmp_5_fu_817_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_5),32));
tmp_6_fu_820_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_6),32));
tmp_7_fu_823_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_7),32));
tmp_8_cast_fu_826_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_8),18));
tmp_8_fu_586_p2 <= std_logic_vector(unsigned(d_i_0) + unsigned(tmp_1_fu_582_p1));
tmp_9_cast_fu_835_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_9),18));
tmp_9_fu_596_p1 <= acc_1(16 - 1 downto 0);
tmp_fu_802_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_0),32));
tmp_s_fu_805_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_1),32));
end behav;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RegisterN is
generic(N : positive := 4);
port( dataIn : in std_logic_vector(N-1 downto 0);
wrEn : in std_logic;
clk : in std_logic;
dataOut : out std_logic_vector(N-1 downto 0));
end RegisterN;
architecture Behavioral of RegisterN is
begin
process(clk)
begin
if(rising_edge(clk)) then
if(wrEn='1') then
dataOut <= dataIn;
end if;
end if;
end process;
end Behavioral; |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY scfifo_32in_32out_1kb IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END scfifo_32in_32out_1kb;
ARCHITECTURE scfifo_32in_32out_1kb_arch OF scfifo_32in_32out_1kb IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF scfifo_32in_32out_1kb_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF scfifo_32in_32out_1kb_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF scfifo_32in_32out_1kb_arch : ARCHITECTURE IS "scfifo_32in_32out_1kb,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF scfifo_32in_32out_1kb_arch: ARCHITECTURE IS "scfifo_32in_32out_1kb,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=31,C_PROG_FULL_THRESH_NEGATE_VAL=30,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=32,C_RD_FREQ=1,C_RD_PNTR_WIDTH=5,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=32,C_WR_FREQ=1,C_WR_PNTR_WIDTH=5,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 6,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "artix7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 31,
C_PROG_FULL_THRESH_NEGATE_VAL => 30,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 6,
C_RD_DEPTH => 32,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 5,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 6,
C_WR_DEPTH => 32,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 5,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => rst,
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END scfifo_32in_32out_1kb_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY scfifo_32in_32out_1kb IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END scfifo_32in_32out_1kb;
ARCHITECTURE scfifo_32in_32out_1kb_arch OF scfifo_32in_32out_1kb IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF scfifo_32in_32out_1kb_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF scfifo_32in_32out_1kb_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF scfifo_32in_32out_1kb_arch : ARCHITECTURE IS "scfifo_32in_32out_1kb,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF scfifo_32in_32out_1kb_arch: ARCHITECTURE IS "scfifo_32in_32out_1kb,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=31,C_PROG_FULL_THRESH_NEGATE_VAL=30,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=32,C_RD_FREQ=1,C_RD_PNTR_WIDTH=5,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=32,C_WR_FREQ=1,C_WR_PNTR_WIDTH=5,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 6,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "artix7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 31,
C_PROG_FULL_THRESH_NEGATE_VAL => 30,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 6,
C_RD_DEPTH => 32,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 5,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 6,
C_WR_DEPTH => 32,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 5,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => rst,
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END scfifo_32in_32out_1kb_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY scfifo_32in_32out_1kb IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END scfifo_32in_32out_1kb;
ARCHITECTURE scfifo_32in_32out_1kb_arch OF scfifo_32in_32out_1kb IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF scfifo_32in_32out_1kb_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF scfifo_32in_32out_1kb_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF scfifo_32in_32out_1kb_arch : ARCHITECTURE IS "scfifo_32in_32out_1kb,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF scfifo_32in_32out_1kb_arch: ARCHITECTURE IS "scfifo_32in_32out_1kb,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=31,C_PROG_FULL_THRESH_NEGATE_VAL=30,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=32,C_RD_FREQ=1,C_RD_PNTR_WIDTH=5,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=32,C_WR_FREQ=1,C_WR_PNTR_WIDTH=5,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 6,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "artix7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 31,
C_PROG_FULL_THRESH_NEGATE_VAL => 30,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 6,
C_RD_DEPTH => 32,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 5,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 6,
C_WR_DEPTH => 32,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 5,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => rst,
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END scfifo_32in_32out_1kb_arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY memory_tb IS
END memory_tb;
ARCHITECTURE behavior OF memory_tb IS
-- Component Declaration for the Unit Under Test (UUT)
component memory
generic (
width: integer := 8; -- ilosc bitow adresów
size: integer := 256 -- rozmiar pamieci w bajtach
);
port (
SET: in STD_LOGIC; -- tryb pracy
CLK: in STD_LOGIC; -- zegar
INDEX: in STD_LOGIC_VECTOR ((width - 1) downto 0); -- indeks elementu tablicy
INVALUE: in STD_LOGIC_VECTOR ((width - 1) downto 0); -- wartoæ wejciowa
OUTVALUE: out STD_LOGIC_VECTOR ((width - 1) downto 0) -- wartoæ wyjciowa
);
end component;
--Inputs
signal SET : std_logic := '0';
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal INDEX : std_logic_vector(7 downto 0) := (others => '0');
signal INVALUE : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal OUTVALUE : std_logic_vector(7 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: memory PORT MAP (
SET => SET,
CLK => CLK,
RST => RST,
INDEX => INDEX,
INVALUE => INVALUE,
OUTVALUE => OUTVALUE
);
-- Clock process definitions
CLK_process : process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc : process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- ustawianie wartoci tablicy
set <= '1';
for i in 0 to 255 loop
index <= conv_std_logic_vector(i, 8);
invalue <= conv_std_logic_vector(i, 8);
wait for clk_period;
end loop;
invalue <= (others => '0');
-- odczytywanie wartoci tablicy
set <= '0';
for i in 0 to 255 loop
index <= conv_std_logic_vector(i, 8);
wait for clk_period;
assert (outvalue = conv_std_logic_vector(i, 8))
report "Oczekiwana inna wartosc"
severity failure;
end loop;
wait;
end process;
END;
|
/***************************************************************************************************
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ 3 space tabs are used throughout the document
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This design of a parameterized real constant multiplier implements the multiplierless multiple
/ constants multiplier by Voronenko-Püschel.
/ The input signal is multiplied by the multiplicands and the result is sent to the output on
/ each clk cycle.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.fixed_float_types.all;
use work.fixed_generic_pkg.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity real_const_mult_core_u is
generic(
SPEED_opt : T_speed := t_exc; --exception: value not set
ROUND_STYLE_opt : T_round_style := fixed_truncate; --default
ROUND_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
MAX_ERROR_PCT_opt : real_exc := real'low; --exception: value not set
CONSTANTS : real_v; --compulsory
input_high : integer;
input_low : integer
);
port(
input : in u_ufixed;
clk : in std_ulogic;
valid_input : in std_ulogic;
output : out u_ufixed_v(1 to CONSTANTS'length)
(real_const_mult_OH(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
CONSTANTS,
input_high,
input_low,
is_signed => false)
downto
real_const_mult_OL(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
CONSTANTS,
input_low,
is_signed => false)
);
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture real_const_mult_core_u_1 of real_const_mult_core_u is
/* corrected generics and internal/external ports' signals */
/***********************************************************************************************/
constant CHECKS : integer := real_const_mult_CHECKS(input_high,
input_low,
false, --unsigned_2comp_opt
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
CONSTANTS);
/* constants for the calculation of port sizes */
/***********************************************************************************************/
--the common output size
constant OUT_HIGH : integer := real_const_mult_OH(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
CONSTANTS,
input_high,
input_low,
is_signed => false);
constant OUT_LOW : integer := real_const_mult_OL(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
CONSTANTS,
input_low,
is_signed => false);
/* constants related to the multiplicands */
/***********************************************************************************************/
--vector to preserve the sign of each constant
constant MULT_SIGN_POSITIVE : boolean_v := is_positive_vector_from_constants(CONSTANTS);
--vector with the values of the constants in fixed point (applying parameters of error percentage,
--round style and bit to which to round)
constant NO_NEGATIONS : boolean := all_positive(MULT_SIGN_POSITIVE);
constant MULT_FIXED : u_ufixed_v := fixed_from_real_constants(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
abs(CONSTANTS),
input_high,
input_low,
is_signed => false);
--vector with the left shift needed(possibly negative) to transform the constants to odd natural values
constant PRE_VP_SHIFT : integer_v := calculate_pre_vp_shift(MULT_FIXED);
--maximum left shift needed
constant MAX_PRE_VP_SHIFT : integer := maximum(PRE_VP_SHIFT);
--vector with the constants in positive odd form, ready for the Voronenko-Püschel algorithm
constant MULT_FUNDAMENTAL : positive_v := calculate_mult_fundamental(MULT_FIXED, PRE_VP_SHIFT);
constant INTER_LOW : integer := input_low - MAX_PRE_VP_SHIFT;
/* file constants */
/***********************************************************************************************/
constant FILE_NAME : string := generate_file_name(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
MULT_FUNDAMENTAL);
constant FILE_PATH : string := DATA_FILE_DIRECTORY & "\" /*"*/ & FILE_NAME; --comment inserted to prevent nonsense syntax highlighting on sublime text 3
file solution_input : text;
/* constants obtained from files */
/***********************************************************************************************/
--carries out the Voronenko_Püschel algorithm and saves the solution to a file
procedure generate_solutions_file
is
--pragma translate off
--synthesis translate_off
package mmcm is new work.mmcm_pkg
generic map(
MAX_TARGET => maximum(MULT_FUNDAMENTAL),
FILE_PATH => FILE_PATH
);
--pragma translate on
--synthesis translate_on
begin
--pragma translate off
--synthesis translate_off
mmcm.VorPus(MULT_FUNDAMENTAL);
--pragma translate on
--synthesis translate_on
end procedure;
--reads the number of vertexes in the solution that is in the file. Additionally, as it is the first
--function that is called in the module, the file with the solutions is also generated, or produces
--an error if the file doesn't exist and we are in synthesis trying to read it
impure function read_number_of_vertexes
return natural is
variable currentline : line;
variable currentchar : character;
variable solution : natural := 0;
variable exists : file_open_status;
begin
--pragma translate off
--synthesis translate_off
file_open(solution_input, FILE_PATH, WRITE_MODE);
file_close(solution_input);
generate_solutions_file;
--pragma translate on
--synthesis translate_on
file_open(solution_input, FILE_PATH, READ_MODE);
if endfile(solution_input) then
assert false
report "The values needed to generate multiplication/divisions have not yet been " &
"generated. It is first required to launch the simulation in order to achieve this"
severity error;
end if;
if not endfile(solution_input) then
readline(solution_input, currentline);
for i in 1 to currentline'length loop
read(currentline, currentchar);
solution := 10*solution + (character'pos(currentchar)-character'pos('0'));
end loop;
end if;
file_close(solution_input);
return solution;
end function;
constant NUMBER_OF_VERTEXES : natural := read_number_of_vertexes;
type T_solutions is record
fundamental : positive;
u : positive;
l1 : natural;
v : positive;
l2 : natural;
s : boolean; --true: v is positive, false: v is negative
is_target : boolean;
flevel : natural;
max_child_flevel : natural;
high : integer;
end record;
type T_solutions_v is array(natural range <>) of T_solutions;
procedure insert(
vector : inout T_solutions_v;
index : in positive;
member : in natural;
value : in natural)
is
begin
case member is
when 0 => vector(index).fundamental := value;
when 1 => vector(index).u := value;
when 2 => vector(index).l1 := value;
when 3 => vector(index).v := value;
when 4 => vector(index).l2 := value;
when others => vector(index).s := ite(value=1, true, false);
end case;
end procedure;
function contains(
vector : positive_v;
number : positive)
return boolean is
begin
for i in vector'range loop
if vector(i) = number then
return true;
end if;
end loop;
return false;
end function;
function index_from_fund(
vertexes : T_solutions_v;
fund : positive)
return natural is
variable result : natural := 0;
begin
for1:
for i in 1 to NUMBER_OF_VERTEXES loop
if vertexes(i).fundamental = fund then
return i;
end if;
end loop;
return result;
end function;
function calculate_max_flevel(
vertexes : T_solutions_v)
return natural is
variable vertex : T_solutions_v(vertexes'range) := vertexes;
variable max_f : natural := 0;
variable aux : natural;
begin
--calculate max_flevel
if NUMBER_OF_VERTEXES > 0 then
vertex(1).flevel := 0;
end if;
if NUMBER_OF_VERTEXES > 1 then
for i in 2 to NUMBER_OF_VERTEXES loop
aux := 1 + maximum(vertex(index_from_fund(vertexes, vertexes(i).u)).flevel,
vertex(index_from_fund(vertexes, vertexes(i).v)).flevel);
vertex(i).flevel := aux;
max_f := maximum(max_f, aux);
end loop;
end if;
return max_f;
end function;
procedure populate_vertexes(
vertexes : inout T_solutions_v;
max_flevel : in natural)
is
variable aux : natural;
variable lowest_child_flevel : natural_v(1 to NUMBER_OF_VERTEXES) := (others => natural'high);
begin
if NUMBER_OF_VERTEXES>0 then
vertexes(1).flevel := 0;
vertexes(1).high := OUT_LOW + input_high - input_low;
end if;
if NUMBER_OF_VERTEXES>1 then
--generate high values for all fundamentals but the first
for i in 2 to NUMBER_OF_VERTEXES loop
vertexes(i).high := calculate_high(vertexes(i).fundamental,
vertexes(1).high,
is_signed => false);
end loop;
--assign values of flevel for all fundamentals' parents but the first
for i in 2 to NUMBER_OF_VERTEXES loop
aux := 1 + maximum(vertexes(index_from_fund(vertexes, vertexes(i).u)).flevel,
vertexes(index_from_fund(vertexes, vertexes(i).v)).flevel);
vertexes(i).flevel := aux;
end loop;
--increase the flevel value of each fundamental to the highest possible(so as to delay the
--operations the most and reduce the registers used in the pipelining)
for j in 1 to NUMBER_OF_VERTEXES loop
--update the lowest flevel of the children for each vertex
for i in 2 to NUMBER_OF_VERTEXES loop
aux := index_from_fund(vertexes, vertexes(i).u);
lowest_child_flevel(aux) := minimum(lowest_child_flevel(aux), vertexes(i).flevel);
aux := index_from_fund(vertexes, vertexes(i).v);
lowest_child_flevel(aux) := minimum(lowest_child_flevel(aux), vertexes(i).flevel);
end loop;
--then increase the flevel when possible
for i in NUMBER_OF_VERTEXES downto 2 loop
if lowest_child_flevel(i) = natural'high then
vertexes(i).flevel := max_flevel;
else
vertexes(i).flevel := lowest_child_flevel(i) - 1;
end if;
end loop;
end loop;
--assign values to max_child_flevel for all fundamentals
for i in 2 to NUMBER_OF_VERTEXES loop
aux := index_from_fund(vertexes, vertexes(i).u);
vertexes(aux).max_child_flevel := maximum(vertexes(aux).max_child_flevel, vertexes(i).flevel);
aux := index_from_fund(vertexes, vertexes(i).v);
vertexes(aux).max_child_flevel := maximum(vertexes(aux).max_child_flevel, vertexes(i).flevel);
end loop;
--if the fundamental is a target increase the max_child_flevel to max_flevel
for i in 1 to NUMBER_OF_VERTEXES loop
if vertexes(i).is_target then
vertexes(i).max_child_flevel := max_flevel + 1;
end if;
end loop;
end if;
end procedure;
--reads the solution vertexes and returns a static structure with the data
impure function read_vertexes
return T_solutions_v is
variable result : T_solutions_v(1 to NUMBER_OF_VERTEXES);
variable currentline : line;
variable currentchar : character;
variable aux : natural := 0;
variable member : natural := 0;
variable max_f : natural;
begin
file_open(solution_input, FILE_PATH, READ_MODE);
if not endfile(solution_input) then
readline(solution_input, currentline);--discard first line
if not endfile(solution_input) then
for i in 1 to NUMBER_OF_VERTEXES loop
readline(solution_input, currentline);
member := 0;
for j in 1 to currentline'length loop
read(currentline, currentchar);
if currentchar = ' ' then
insert(result, i, member, aux);
aux := 0;
member := member + 1;
else
aux := 10*aux + (character'pos(currentchar)-character'pos('0'));
end if;
end loop;
--add the last read member
insert(result, i, member, aux);
--add whether the actual fundamental is a target (which is not read from the file)
result(i).is_target := contains(MULT_FUNDAMENTAL, result(i).fundamental);
aux := 0;
end loop;
end if;
end if;
file_close(solution_input);
max_f := calculate_max_flevel(result);
populate_vertexes(result, max_f);
return result;
end function;
constant VERTEXES : T_solutions_v(1 to NUMBER_OF_VERTEXES) := read_vertexes;
--same as before but referred directly to the constant VERTEXES
function index_from_fund(
fund : positive)
return natural is
begin
for1:
for i in 1 to NUMBER_OF_VERTEXES loop
if VERTEXES(i).fundamental = fund then
return i;
end if;
end loop;
return 0; --when not found return 0
end function;
constant MAX_FLEVEL : natural := calculate_max_flevel(VERTEXES);
/* constants related to pipelines */
/***********************************************************************************************/
--number of possible positions to place pipelines
constant PIPELINE_POSITIONS : natural := MAX_FLEVEL + 1;
--boolean vector which indicates whether a pipeline is placed or not on each possible position
constant IS_PIPELINED : boolean_v(0 to PIPELINE_POSITIONS-1) := generate_pipelines(PIPELINE_POSITIONS,
SPEED_opt);
--number of pipelines
constant PIPELINES : natural := number_of_pipelines(PIPELINE_POSITIONS,
SPEED_opt);
/* signals */
/***********************************************************************************************/
signal fundamental_signals : u_ufixed_vv(1 to NUMBER_OF_VERTEXES)(0 to MAX_FLEVEL)(OUT_HIGH downto INTER_LOW);
signal valid_input_sh : std_ulogic_vector(1 to PIPELINES);
signal pre_output : u_ufixed_v(1 to MULT_FUNDAMENTAL'length)(OUT_HIGH downto OUT_LOW);
/*================================================================================================*/
/*================================================================================================*/
begin
generate_valid_output:
if PIPELINES > 0 generate
begin
valid_output <= valid_input_sh(PIPELINES);
process(clk) is
begin
if rising_edge(clk) then
valid_input_sh <= valid_input_sh srl 1;
valid_input_sh(1) <= valid_input;
end if;
end process;
end;
else generate
begin
valid_output <= valid_input;
end;
end generate;
msg_debug("real_const_mult_core_u FILE_PATH: " & string'(FILE_PATH));
msg_debug("real_const_mult_core_u NUMBER_OF_VERTEXES: " & image(NUMBER_OF_VERTEXES));
msg_debug("real_const_mult_core_u OUT_HIGH: " & image(OUT_HIGH));
msg_debug("real_const_mult_core_u OUT_LOW: " & image(OUT_LOW));
generate_each_constant:
for i in 1 to CONSTANTS'length generate
begin
msg_debug("real_const_mult_core_u CONSTANTS(" & image(i) & "): " & image(CONSTANTS(i)));
msg_debug("real_const_mult_core_u MULT_FUNDAMENTAL(" & image(i) & "): " & image(MULT_FUNDAMENTAL(i)));
msg_debug("real_const_mult_core_u PRE_VP_SHIFT(" & image(i) & "): " & image(PRE_VP_SHIFT(i)));
end generate;
pipeline_or_connection_of_input:
if IS_PIPELINED(0) generate
begin
process(clk) is
begin
if rising_edge(clk) then
fundamental_signals(1)(0)(VERTEXES(1).high downto OUT_LOW) <= input;
end if;
end process;
end;
else generate
fundamental_signals(1)(0)(VERTEXES(1).high downto OUT_LOW) <= input;
end generate;
if_max_child_of_input_is_higher_than_1:
if VERTEXES(1).max_child_flevel > 1 generate
generate_pipelines_fundamental_for_1_for_each_flevel:
for j in 1 to VERTEXES(1).max_child_flevel - 1 generate
constant high : integer := VERTEXES(1).high;
begin
pipeline_or_connection:
if IS_PIPELINED(j) generate
begin
process(clk) is
begin
if rising_edge(clk) then
fundamental_signals(1)(j)(high downto OUT_LOW)
<= fundamental_signals(1)(j-1)(high downto OUT_LOW);
end if;
end process;
end;
else generate
fundamental_signals(1)(j)(high downto OUT_LOW)
<= fundamental_signals(1)(j-1)(high downto OUT_LOW);
end generate;
end;
end generate;
end generate;
generate_pipelines_for_other_fundamentals:
for i in 2 to NUMBER_OF_VERTEXES generate
constant first : natural := VERTEXES(i).flevel;
constant last : natural := VERTEXES(i).max_child_flevel - 1;
constant high : integer := vertexes(i).high;
begin
if_last_greater_than_first:
if last > first generate
for_each_flevel:
for j in first+1 to last generate
pipeline_or_connection:
if IS_PIPELINED(j) generate
begin
process(clk) is
begin
if rising_edge(clk) then
fundamental_signals(i)(j)(high downto OUT_LOW)
<= fundamental_signals(i)(j-1)(high downto OUT_LOW);
end if;
end process;
end;
else generate
fundamental_signals(i)(j)(high downto OUT_LOW)
<= fundamental_signals(i)(j-1)(high downto OUT_LOW);
end generate;
end generate;
end generate;
end;
end generate;
generate_fundamental_signals:
for i in 2 to NUMBER_OF_VERTEXES generate
constant current : T_solutions := VERTEXES(i);
constant u : positive := current.u;
constant l1 : natural := current.l1;
constant v : positive := current.v;
constant l2 : natural := current.l2;
constant s : boolean := current.s;
constant flevel : natural := current.flevel;
constant high : integer := current.high;
constant u_high : integer := vertexes(index_from_fund(u)).high;
constant v_high : integer := vertexes(index_from_fund(v)).high;
signal signal1 : u_ufixed(u_high downto OUT_LOW);
signal signal2 : u_ufixed(v_high downto OUT_LOW);
signal signal3 : u_ufixed(u_high+1 downto OUT_LOW);
signal aux1 : u_ufixed(high downto OUT_LOW);
signal aux2 : u_ufixed(high downto OUT_LOW);
signal aux3 : u_ufixed(high+1 downto OUT_LOW);
signal result1 : u_ufixed(high downto OUT_LOW);
signal result2 : u_ufixed(high+1 downto OUT_LOW);
begin
signal1 <= fundamental_signals(index_from_fund(u))(flevel-1)(u_high downto OUT_LOW);
signal2 <= fundamental_signals(index_from_fund(v))(flevel-1)(v_high downto OUT_LOW);
signal3 <= resize(fundamental_signals(index_from_fund(u))(flevel-1)(u_high downto OUT_LOW), signal3);
aux1 <= resize(signal1, aux1) sll l1;
aux2 <= resize(signal2, aux2) sll l2;
aux3 <= resize(signal3, aux3) sll l1;
result1 <= resize(aux1 + aux2, result1);
result2 <= resize(aux3 - resize(aux2, aux3), result2);
pipeline_or_connection:
if IS_PIPELINED(flevel) generate
begin
process(clk) is
begin
if rising_edge(clk) then
fundamental_signals(i)(flevel)(high downto OUT_LOW)
<= result1(high downto OUT_LOW) when s else
result2(high downto OUT_LOW);
end if;
end process;
end;
else generate
begin
positive_or_negative:
if s generate
fundamental_signals(i)(flevel)(high downto OUT_LOW)
<= result1(high downto OUT_LOW);
else generate
fundamental_signals(i)(flevel)(high downto OUT_LOW)
<= result2(high downto OUT_LOW);
end generate;
end;
end generate;
end;
end generate;
invert_output:
for i in 1 to CONSTANTS'length generate
constant index : integer := index_from_fund(MULT_FUNDAMENTAL(i));
constant high : integer := VERTEXES(index).high;
signal aux : u_ufixed(high downto OUT_LOW);
signal result1 : u_ufixed(high downto OUT_LOW);
begin
aux <= fundamental_signals(index)(MAX_FLEVEL)(high downto OUT_LOW);
result1 <= resize(aux, result1);
pre_output(i)(result1'range) <= result1;
end;
end generate;
generate_output_shifts:
for i in 1 to CONSTANTS'length generate
constant index : integer := index_from_fund(MULT_FUNDAMENTAL(i));
constant high : integer := VERTEXES(index).high;
constant adjustment : integer := -PRE_VP_SHIFT(i) - (OUT_LOW - input_low);
begin
depending_on_adjustment_value:
if adjustment > 0 generate
output(i) <= resize(pre_output(i)(high downto OUT_LOW),
output(i))
sll
adjustment;
else generate
output(i) <= resize(pre_output(i)(high downto OUT_LOW),
output(i))
sra
abs(adjustment); --to introduce the leftmost bit when shifting to the right
end generate;
end;
end generate;
end architecture; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: inpad
-- File: inpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: input pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity inpad is
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; filter : integer := 0;
strength : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of inpad is
begin
gen0 : if has_pads(tech) = 0 generate
o <= transport to_X01(pad)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_inpad generic map (level, voltage) port map (pad, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_inpad generic map (level, voltage) port map (pad, o);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_inpad generic map (level, voltage) port map (pad, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_inpad generic map (level, voltage) port map (pad, o);
end generate;
um : if (tech = umc) generate
x0 : umc_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
saed : if (tech = saed32) generate
x0 : saed32_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
dar : if (tech = dare) generate
x0 : dare_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_inpad generic map(level, voltage) port map(pad, o);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_inpad generic map(level, voltage) port map(pad, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_inpad generic map (voltage, filter) port map(pad, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_inpad generic map (level, voltage, filter) port map(pad, o);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_inpad generic map (level, voltage, filter) port map(pad, o);
end generate;
pereg : if (tech = peregrine) generate
x0 : peregrine_inpad generic map (level, voltage, filter, strength) port map(pad, o);
end generate;
eas : if (tech = easic90) generate
x0 : nextreme_inpad generic map (level, voltage) port map (pad, o);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_inpad generic map (level, voltage) port map (pad, o);
end generate;
ut90nhbd : if (tech = ut90) generate
x0 : ut90nhbd_inpad generic map (level, voltage, filter) port map(pad, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity inpadv is
generic (tech : integer := 0; level : integer := 0;
voltage : integer := 0; width : integer := 1;
filter : integer := 0; strength : integer := 0);
port (
pad : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of inpadv is
begin
v : for i in width-1 downto 0 generate
x0 : inpad generic map (tech, level, voltage, filter, strength) port map (pad(i), o(i));
end generate;
end;
|
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--library SYNOPSYS;
--use SYNOPSYS.attributes.all;
package std_logic_misc is
-- output-strength types
type STRENGTH is (strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1,
strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1);
--synopsys synthesis_off
type MINOMAX is array (1 to 3) of TIME;
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC;
---------------------------------------------------------------------
--
-- conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
--synopsys synthesis_off
--attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
--synopsys synthesis_on
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_(U)LOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT;
--------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01;
function fun_WiredX(Input0, Input1: std_ulogic) return STD_LOGIC;
--synopsys synthesis_on
end;
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
package body std_logic_misc is
--synopsys synthesis_off
type STRN_STD_ULOGIC_TABLE is array (STD_ULOGIC,STRENGTH) of STD_ULOGIC;
--------------------------------------------------------------------
--
-- Truth tables for output strength --> STD_ULOGIC lookup
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
--------------------------------------------------------------------
--
-- Truth tables for strength --> STD_ULOGIC mapping ('Z' pass through)
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC_Z: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 387
begin
return tbl_STRN_STD_ULOGIC(input, strn);
end strength_map;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 388
begin
return tbl_STRN_STD_ULOGIC_Z(input, strn);
end strength_map_z;
---------------------------------------------------------------------
--
-- conversion functions for STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 389
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_ULOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 390
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_LOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
--synopsys synthesis_off
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
--
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC is
-- pragma subpgm_id 391
begin
if V = 'Z' then
return vZ;
elsif V = 'U' then
return vU;
elsif V = '-' then
return vDC;
else
return V;
end if;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 392
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 393
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 394
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 395
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
--synopsys synthesis_on
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 396
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_LOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_ULOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 397
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_ULOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_ULOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 398
variable Result: BIT;
begin
--synopsys synthesis_off
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result := vZ;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result := vU;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result := vDC;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: - --> 0"
severity WARNING;
end if;
end case;
return Result;
--synopsys synthesis_on
end STD_ULOGICtoBIT;
--------------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 399
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 400
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 401
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 402
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 404
begin
return not XOR_REDUCE(ARG);
end;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 405
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 406
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 407
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 408
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 409
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 410
begin
return not XOR_REDUCE(ARG);
end;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 411
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3S: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('Z', 'Z', 'Z', 'Z'), --| 0 X01 |
('U', 'X', '0', '1')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('Z', 'Z', 'Z', 'Z'), --| 0 X0H |
('U', 'X', '0', 'H')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XL1 |
('U', 'X', 'L', '1')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('Z', 'Z', 'Z', 'Z'), --| 0 X0Z |
('U', 'X', '0', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XZ1 |
('U', 'X', 'Z', '1')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('Z', 'Z', 'Z', 'Z'), --| 0 WLH |
('U', 'W', 'L', 'H')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('Z', 'Z', 'Z', 'Z'), --| 0 WLZ |
('U', 'W', 'L', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('Z', 'Z', 'Z', 'Z'), --| 0 WZH |
('U', 'W', 'Z', 'H')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('Z', 'Z', 'Z', 'Z'), --| 0 W0H |
('U', 'W', '0', 'H')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 WL1 |
('U', 'W', 'L', '1')));--| 1 WL1 |
begin
return tbl_BUF3S(Strn, Enable, Input);
end fun_BUF3S;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 412
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3SL: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('U', 'X', '0', '1'), --| 0 X01 |
('Z', 'Z', 'Z', 'Z')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('U', 'X', '0', 'H'), --| 0 X0H |
('Z', 'Z', 'Z', 'Z')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('U', 'X', 'L', '1'), --| 0 XL1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('U', 'X', '0', 'Z'), --| 0 X0Z |
('Z', 'Z', 'Z', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('U', 'X', 'Z', '1'), --| 0 XZ1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('U', 'W', 'L', 'H'), --| 0 WLH |
('Z', 'Z', 'Z', 'Z')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('U', 'W', 'L', 'Z'), --| 0 WLZ |
('Z', 'Z', 'Z', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('U', 'W', 'Z', 'H'), --| 0 WZH |
('Z', 'Z', 'Z', 'Z')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('U', 'W', '0', 'H'), --| 0 W0H |
('Z', 'Z', 'Z', 'Z')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('U', 'W', 'L', '1'), --| 0 WL1 |
('Z', 'Z', 'Z', 'Z')));--| 1 WL1 |
begin
return tbl_BUF3SL(Strn, Enable, Input);
end fun_BUF3SL;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01 is
-- pragma subpgm_id 413
type MUX_TABLE is array (UX01, UX01, UX01) of UX01;
-- truth table for "MUX2x1" function
constant tbl_MUX2x1: MUX_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | Sel In1 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'X', '0', '1'), --| '0' 'U' |
('U', 'U', 'U', 'U')), --| '1' 'U' |
(('U', 'X', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', '1'), --| '0' 'X' |
('X', 'X', 'X', 'X')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('U', 'X', '0', '1'), --| '0' '0' |
('0', '0', '0', '0')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MUX2x1(Input1, Sel, Input0);
end fun_MUX2x1;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01 is
-- pragma subpgm_id 414
type MAJ23_TABLE is array (UX01, UX01, UX01) of UX01;
----------------------------------------------------------------------------
-- The "tbl_MAJ23" truth table return 1 if the majority of three
-- inputs is 1, a 0 if the majority is 0, a X if unknown, and a U if
-- uninitialized.
----------------------------------------------------------------------------
constant tbl_MAJ23: MAJ23_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | In1 In2 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'U', '0', 'U'), --| '0' 'U' |
('U', 'U', 'U', '1')), --| '1' 'U' |
(('U', 'U', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', 'X'), --| '0' 'X' |
('U', 'X', 'X', '1')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('0', '0', '0', '0'), --| '0' '0' |
('U', 'X', '0', '1')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MAJ23(Input0, Input1, Input2);
end fun_MAJ23;
function fun_WiredX(Input0, Input1: STD_ULOGIC) return STD_LOGIC is
-- pragma subpgm_id 415
TYPE stdlogic_table IS ARRAY(STD_ULOGIC, STD_ULOGIC) OF STD_LOGIC;
-- truth table for "WiredX" function
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ));-- | - |
begin
return resolution_table(Input0, Input1);
end fun_WiredX;
--synopsys synthesis_on
end;
|
-- File: inc_comb.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:39 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity inc_comb is
port (
nextCount: out unsigned(7 downto 0);
count: in unsigned(7 downto 0)
);
end entity inc_comb;
architecture MyHDL of inc_comb is
begin
nextCount <= (count + 1) mod 256;
end architecture MyHDL;
|
-- File: inc_comb.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:39 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity inc_comb is
port (
nextCount: out unsigned(7 downto 0);
count: in unsigned(7 downto 0)
);
end entity inc_comb;
architecture MyHDL of inc_comb is
begin
nextCount <= (count + 1) mod 256;
end architecture MyHDL;
|
-- File: inc_comb.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:39 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity inc_comb is
port (
nextCount: out unsigned(7 downto 0);
count: in unsigned(7 downto 0)
);
end entity inc_comb;
architecture MyHDL of inc_comb is
begin
nextCount <= (count + 1) mod 256;
end architecture MyHDL;
|
-- File: inc_comb.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:39 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity inc_comb is
port (
nextCount: out unsigned(7 downto 0);
count: in unsigned(7 downto 0)
);
end entity inc_comb;
architecture MyHDL of inc_comb is
begin
nextCount <= (count + 1) mod 256;
end architecture MyHDL;
|
-- File: inc_comb.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:39 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity inc_comb is
port (
nextCount: out unsigned(7 downto 0);
count: in unsigned(7 downto 0)
);
end entity inc_comb;
architecture MyHDL of inc_comb is
begin
nextCount <= (count + 1) mod 256;
end architecture MyHDL;
|
-- File: inc_comb.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:39 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity inc_comb is
port (
nextCount: out unsigned(7 downto 0);
count: in unsigned(7 downto 0)
);
end entity inc_comb;
architecture MyHDL of inc_comb is
begin
nextCount <= (count + 1) mod 256;
end architecture MyHDL;
|
-- File: inc_comb.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:39 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity inc_comb is
port (
nextCount: out unsigned(7 downto 0);
count: in unsigned(7 downto 0)
);
end entity inc_comb;
architecture MyHDL of inc_comb is
begin
nextCount <= (count + 1) mod 256;
end architecture MyHDL;
|
-- File: inc_comb.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:39 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity inc_comb is
port (
nextCount: out unsigned(7 downto 0);
count: in unsigned(7 downto 0)
);
end entity inc_comb;
architecture MyHDL of inc_comb is
begin
nextCount <= (count + 1) mod 256;
end architecture MyHDL;
|
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