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--
--
-- ZPUINO implementation on Gadget Factory 'Papilio Pro' Board
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- Vanilla Variant
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
use work.zpuinopkg.all;
use work.zpuino_config.all;
use work.zpu_config.all;
use work.pad.all;
use work.wishbonepkg.all;
use Work.I2C_Master.all;
entity miniSpartan6_plus_top is
port (
CLK: in std_logic;
CLK50: in std_logic;
-- Connection to the main SPI flash
SPI_SCK: out std_logic;
SPI_MISO: in std_logic;
SPI_MOSI: out std_logic;
SPI_CS: out std_logic;
-- PORT connections
PORTA: inout std_logic_vector(7 downto 0);
PORTB: inout std_logic_vector(7 downto 0);
PORTC: inout std_logic_vector(7 downto 0);
PORTE: inout std_logic_vector(7 downto 0);
PORTF: inout std_logic_vector(7 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
DRAM_ADDR : OUT STD_LOGIC_VECTOR (12 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
-- I2C
SCL: inout std_logic;
SDA: inout std_logic;
-- ADC
AD_CS : out std_logic;
AD_SCLK : out std_logic;
AD_DIN : out std_logic;
AD_OUT : in std_logic;
-- UART1 Bluetooth
TXD1 : out std_logic;
RXD1 : in std_logic;
SPI2_CS : out std_logic;
-- OV7670 Camera
OV7670_VSYNC : in std_logic;
OV7670_HREF : in std_logic;
OV7670_PCLK : in std_logic;
OV7670_XCLK : out std_logic;
OV7670_D : in std_logic_vector( 7 downto 0 );
-- ENCODER
ENCODER_A_A : in std_logic;
ENCODER_A_B : in std_logic;
ENCODER_B_A : in std_logic;
ENCODER_B_B : in std_logic;
-- The LED
LEDS: inout std_logic_vector(7 downto 0)
);
end entity miniSpartan6_plus_top;
architecture behave of miniSpartan6_plus_top is
component zpuino_debug_jtag_spartan6 is
port (
jtag_data_chain_in: in std_logic_vector(98 downto 0);
jtag_ctrl_chain_out: out std_logic_vector(11 downto 0)
);
end component;
signal jtag_data_chain_in: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_out: std_logic_vector(11 downto 0);
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout1: out std_logic;
clkout2: out std_logic;
clk_1Mhz_out: out std_logic;
rstout: out std_logic
);
end component;
component wb_bootloader is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(11 downto 2);
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
wb2_dat_o: out std_logic_vector(31 downto 0);
wb2_adr_i: in std_logic_vector(11 downto 2);
wb2_cyc_i: in std_logic;
wb2_stb_i: in std_logic;
wb2_ack_o: out std_logic;
wb2_stall_o: out std_logic
);
end component;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal clkgen_rst: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"00" & -- SPI CS
"1111111111111111" & -- PORT E PORTF
"1111111111111111" & -- PORT C PORTB
"1111111111111111"; -- PORT A LEDS
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"00" & -- SPI CS
"1111111111111111" & -- PORT E PORTF
"1111111111111111" & -- PORT C PORTB
"1111111111111111"; -- PORT A LEDS
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address:slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
-- 2nd SPI signals
signal spi2_mosi: std_logic;
signal spi2_miso: std_logic;
signal spi2_sck: std_logic;
-- GPIO Periperal Pin Select
signal gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- Timer connections
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm_a: std_logic_vector(1 downto 0);
signal timers_pwm_b: std_logic_vector(1 downto 0);
-- Sigmadelta output
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- main SPI signals
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
-- UART signals
signal rx: std_logic;
signal tx: std_logic;
signal sysclk_sram_we, sysclk_sram_wen: std_ulogic;
signal rx1: std_logic;
signal tx1: std_logic;
signal ram_wb_ack_o: std_logic;
signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal ram_wb_cyc_i: std_logic;
signal ram_wb_stb_i: std_logic;
signal ram_wb_sel_i: std_logic_vector(3 downto 0);
signal ram_wb_we_i: std_logic;
signal ram_wb_stall_o: std_logic;
signal np_ram_wb_ack_o: std_logic;
signal np_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal np_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal np_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal np_ram_wb_cyc_i: std_logic;
signal np_ram_wb_stb_i: std_logic;
signal np_ram_wb_sel_i: std_logic_vector(3 downto 0);
signal np_ram_wb_we_i: std_logic;
signal sram_wb_ack_o: std_logic;
signal sram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal sram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal sram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal sram_wb_cyc_i: std_logic;
signal sram_wb_stb_i: std_logic;
signal sram_wb_we_i: std_logic;
signal sram_wb_sel_i: std_logic_vector(3 downto 0);
signal sram_wb_stall_o: std_logic;
signal rom_wb_ack_o: std_logic;
signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal rom_wb_cyc_i: std_logic;
signal rom_wb_stb_i: std_logic;
signal rom_wb_cti_i: std_logic_vector(2 downto 0);
signal rom_wb_stall_o: std_logic;
signal sram_rom_wb_ack_o: std_logic;
signal sram_rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal sram_rom_wb_adr_i: std_logic_vector(maxAddrBit downto 2);
signal sram_rom_wb_cyc_i: std_logic;
signal sram_rom_wb_stb_i: std_logic;
signal sram_rom_wb_cti_i: std_logic_vector(2 downto 0);
signal sram_rom_wb_stall_o: std_logic;
signal prom_rom_wb_ack_o: std_logic;
signal prom_rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal prom_rom_wb_adr_i: std_logic_vector(maxAddrBit downto 2);
signal prom_rom_wb_cyc_i: std_logic;
signal prom_rom_wb_stb_i: std_logic;
signal prom_rom_wb_cti_i: std_logic_vector(2 downto 0);
signal prom_rom_wb_stall_o: std_logic;
signal memory_enable: std_logic;
signal adc_enabled: std_logic;
signal spi2_enabled: std_logic;
component sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end component sdram_ctrl;
component wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master signals
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave signals
s_wb_dat_i: in std_logic_vector(31 downto 0);
s_wb_dat_o: out std_logic_vector(31 downto 0);
s_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s_wb_sel_o: out std_logic_vector(3 downto 0);
s_wb_cti_o: out std_logic_vector(2 downto 0);
s_wb_we_o: out std_logic;
s_wb_cyc_o: out std_logic;
s_wb_stb_o: out std_logic;
s_wb_ack_i: in std_logic;
s_wb_stall_i: in std_logic
);
end component;
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sysclk_1mhz: std_logic;
-- Papilio Note: Place your signal statements here. #Signal
signal scl_padi : std_logic; -- i2c clock line input
signal scl_pado : std_logic; -- i2c clock line output
signal scl_padoen : std_logic; -- i2c clock line output enable, active low
signal sda_padi : std_logic; -- i2c data line input
signal sda_pado : std_logic; -- i2c data line output
signal sda_padoen : std_logic; -- i2c data line output enable, active low
signal sdar : std_logic; -- i2c data line
signal sclr : std_logic; -- i2c data line
begin
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => '0' ,
clkout => sysclk,
clkout1 => sysclk_sram_we,
clkout2 => sysclk_sram_wen,
clk_1Mhz_out => sysclk_1mhz,
rstout => clkgen_rst
);
pin00: IOPAD port map(I => gpio_o(0),O => gpio_i(0),T => gpio_t(0),C => sysclk,PAD => LEDS(0) );
pin01: IOPAD port map(I => gpio_o(1),O => gpio_i(1),T => gpio_t(1),C => sysclk,PAD => LEDS(1) );
pin02: IOPAD port map(I => gpio_o(2),O => gpio_i(2),T => gpio_t(2),C => sysclk,PAD => LEDS(2) );
pin03: IOPAD port map(I => gpio_o(3),O => gpio_i(3),T => gpio_t(3),C => sysclk,PAD => LEDS(3) );
pin04: IOPAD port map(I => gpio_o(4),O => gpio_i(4),T => gpio_t(4),C => sysclk,PAD => LEDS(4) );
pin05: IOPAD port map(I => gpio_o(5),O => gpio_i(5),T => gpio_t(5),C => sysclk,PAD => LEDS(5) );
pin06: IOPAD port map(I => gpio_o(6),O => gpio_i(6),T => gpio_t(6),C => sysclk,PAD => LEDS(6) );
pin07: IOPAD port map(I => gpio_o(7),O => gpio_i(7),T => gpio_t(7),C => sysclk,PAD => LEDS(7) );
pin08: IOPAD port map(I => gpio_o(8),O => gpio_i(8),T => gpio_t(8),C => sysclk,PAD => PORTA(0) );
pin09: IOPAD port map(I => gpio_o(9),O => gpio_i(9),T => gpio_t(9),C => sysclk,PAD => PORTA(1) );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => PORTA(2) );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => PORTA(3) );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => PORTA(4) );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => PORTA(5) );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => PORTA(6) );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => PORTA(7) );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => PORTB(0) );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => PORTB(1) );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => PORTB(2) );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => PORTB(3) );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => PORTB(4) );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => PORTB(5) );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => PORTB(6) );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => PORTB(7) );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => PORTC(0) );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => PORTC(1) );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => PORTC(2) );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => PORTC(3) );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => PORTC(4) );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => PORTC(5) );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => PORTC(6) );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => PORTC(7) );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => PORTE(0) );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => PORTE(1) );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => PORTE(2) );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => PORTE(3) );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => PORTE(4) );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => PORTE(5) );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => PORTE(6) );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => PORTE(7) );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => PORTF(0) );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => PORTF(1) );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => PORTF(2) );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => PORTF(3) );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => PORTF(4) );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => PORTF(5) );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => PORTF(6) );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => PORTF(7) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_SCK );
ospics: OPAD port map ( I => gpio_o(48), PAD => SPI_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_MOSI );
--oled: OPAD port map ( I => gpio_o(49), PAD => LED );
ibufrx1: IPAD port map ( PAD => RXD1, O => rx1, C => sysclk );
obuftx1: OPAD port map ( I => tx1, PAD => TXD1 );
zpuino:zpuino_top_icache
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
m_wb_dat_o => open,
m_wb_dat_i => (others => 'X'),
m_wb_adr_i => (others => 'X'),
m_wb_we_i => '0',
m_wb_cyc_i => '0',
m_wb_stb_i => '0',
m_wb_ack_o => open,
memory_enable => memory_enable,
ram_wb_ack_i => np_ram_wb_ack_o,
ram_wb_stall_i => '0',--np_ram_wb_stall_o,
ram_wb_dat_o => np_ram_wb_dat_i,
ram_wb_dat_i => np_ram_wb_dat_o,
ram_wb_adr_o => np_ram_wb_adr_i(maxAddrBit downto 0),
ram_wb_cyc_o => np_ram_wb_cyc_i,
ram_wb_stb_o => np_ram_wb_stb_i,
ram_wb_sel_o => np_ram_wb_sel_i,
ram_wb_we_o => np_ram_wb_we_i,
rom_wb_ack_i => rom_wb_ack_o,
rom_wb_stall_i => rom_wb_stall_o,
rom_wb_dat_i => rom_wb_dat_o,
rom_wb_adr_o => rom_wb_adr_i(maxAddrBit downto 0),
rom_wb_cyc_o => rom_wb_cyc_i,
rom_wb_stb_o => rom_wb_stb_i,
-- No debug unit connected
dbg_reset => open,
jtag_data_chain_out => open, --jtag_data_chain_in,
jtag_ctrl_chain_in => (others => '0') --jtag_ctrl_chain_out
);
--dbg: zpuino_debug_jtag_spartan6
-- port map (
-- jtag_data_chain_in => jtag_data_chain_in,
-- jtag_ctrl_chain_out => jtag_ctrl_chain_out
-- );
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBit,
ADDRESS_LOW => 2
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
m0_wb_dat_o => ram_wb_dat_o,
m0_wb_dat_i => ram_wb_dat_i,
m0_wb_adr_i => ram_wb_adr_i(maxAddrBit downto 2),
m0_wb_sel_i => ram_wb_sel_i,
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => ram_wb_we_i,
m0_wb_cyc_i => ram_wb_cyc_i,
m0_wb_stb_i => ram_wb_stb_i,
m0_wb_ack_o => ram_wb_ack_o,
m0_wb_stall_o => ram_wb_stall_o,
m1_wb_dat_o => sram_rom_wb_dat_o,
m1_wb_dat_i => (others => DontCareValue),
m1_wb_adr_i => sram_rom_wb_adr_i(maxAddrBit downto 2),
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => '0',--rom_wb_we_i,
m1_wb_cyc_i => sram_rom_wb_cyc_i,
m1_wb_stb_i => sram_rom_wb_stb_i,
m1_wb_ack_o => sram_rom_wb_ack_o,
m1_wb_stall_o => sram_rom_wb_stall_o,
s0_wb_dat_i => sram_wb_dat_o,
s0_wb_dat_o => sram_wb_dat_i,
s0_wb_adr_o => sram_wb_adr_i(maxAddrBit downto 2),
s0_wb_sel_o => sram_wb_sel_i,
s0_wb_cti_o => open,
s0_wb_we_o => sram_wb_we_i,
s0_wb_cyc_o => sram_wb_cyc_i,
s0_wb_stb_o => sram_wb_stb_i,
s0_wb_ack_i => sram_wb_ack_o,
s0_wb_stall_i => sram_wb_stall_o
);
bootmux: wbbootloadermux
generic map (
address_high => maxAddrBit
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
sel => memory_enable,
-- Master
m_wb_dat_o => rom_wb_dat_o,
m_wb_dat_i => (others => DontCareValue),
m_wb_adr_i => rom_wb_adr_i(maxAddrBit downto 2),
m_wb_sel_i => (others => '1'),
m_wb_cti_i => CTI_CYCLE_CLASSIC,
m_wb_we_i => '0',
m_wb_cyc_i => rom_wb_cyc_i,
m_wb_stb_i => rom_wb_stb_i,
m_wb_ack_o => rom_wb_ack_o,
m_wb_stall_o => rom_wb_stall_o,
-- Slave 0 signals
s0_wb_dat_i => sram_rom_wb_dat_o,
s0_wb_dat_o => open,
s0_wb_adr_o => sram_rom_wb_adr_i,
s0_wb_sel_o => open,
s0_wb_cti_o => open,
s0_wb_we_o => open,
s0_wb_cyc_o => sram_rom_wb_cyc_i,
s0_wb_stb_o => sram_rom_wb_stb_i,
s0_wb_ack_i => sram_rom_wb_ack_o,
s0_wb_stall_i => sram_rom_wb_stall_o,
-- Slave 1 signals
s1_wb_dat_i => prom_rom_wb_dat_o,
s1_wb_dat_o => open,
s1_wb_adr_o => prom_rom_wb_adr_i(11 downto 2),
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => open,
s1_wb_cyc_o => prom_rom_wb_cyc_i,
s1_wb_stb_o => prom_rom_wb_stb_i,
s1_wb_ack_i => prom_rom_wb_ack_o,
s1_wb_stall_i => prom_rom_wb_stall_o
);
npnadapt: wb_master_np_to_slave_p
generic map (
ADDRESS_HIGH => maxAddrBitIncIO,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
-- Master signals
m_wb_dat_o => np_ram_wb_dat_o,
m_wb_dat_i => np_ram_wb_dat_i,
m_wb_adr_i => np_ram_wb_adr_i,
m_wb_sel_i => np_ram_wb_sel_i,
m_wb_cti_i => CTI_CYCLE_CLASSIC,
m_wb_we_i => np_ram_wb_we_i,
m_wb_cyc_i => np_ram_wb_cyc_i,
m_wb_stb_i => np_ram_wb_stb_i,
m_wb_ack_o => np_ram_wb_ack_o,
-- Slave signals
s_wb_dat_i => ram_wb_dat_o,
s_wb_dat_o => ram_wb_dat_i,
s_wb_adr_o => ram_wb_adr_i,
s_wb_sel_o => ram_wb_sel_i,
s_wb_cti_o => open,
s_wb_we_o => ram_wb_we_i,
s_wb_cyc_o => ram_wb_cyc_i,
s_wb_stb_o => ram_wb_stb_i,
s_wb_ack_i => ram_wb_ack_o,
s_wb_stall_i => ram_wb_stall_o
);
-- PROM
prom: wb_bootloader
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => prom_rom_wb_dat_o,
wb_adr_i => prom_rom_wb_adr_i(11 downto 2),
wb_cyc_i => prom_rom_wb_cyc_i,
wb_stb_i => prom_rom_wb_stb_i,
wb_ack_o => prom_rom_wb_ack_o,
wb_stall_o => prom_rom_wb_stall_o,
wb2_dat_o => slot_read(15),
wb2_adr_i => slot_address(15)(11 downto 2),
wb2_cyc_i => slot_cyc(15),
wb2_stb_i => slot_stb(15),
wb2_ack_o => slot_ack(15),
wb2_stall_o => open
);
--
-- IO SLOT 0
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => open
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => open,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_spp_data,
spp_read => gpio_spp_read,
gpio_i => gpio_i,
gpio_t => gpio_t,
gpio_o => gpio_o,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 2,
B_WIDTH => 8, -- 24,
B_PRESCALER_ENABLED => true, -- false
B_BUFFERS => true -- false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm_a(0 downto 0),
pwm_b_out => timers_pwm_b(1 downto 0)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
sigmadelta_inst: zpuino_sigmadelta
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(5),
wb_dat_i => slot_write(5),
wb_adr_i => slot_address(5),
wb_we_i => slot_we(5),
wb_cyc_i => slot_cyc(5),
wb_stb_i => slot_stb(5),
wb_ack_o => slot_ack(5),
wb_inta_o => slot_interrupt(5),
spp_data => sigmadelta_spp_data,
spp_en => open,
sync_in => '1'
);
--
-- IO SLOT 6
--
slot1: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(6),
wb_dat_i => slot_write(6),
wb_adr_i => slot_address(6),
wb_we_i => slot_we(6),
wb_cyc_i => slot_cyc(6),
wb_stb_i => slot_stb(6),
wb_ack_o => slot_ack(6),
wb_inta_o => slot_interrupt(6),
mosi => spi2_mosi,
miso => spi2_miso,
sck => spi2_sck,
enabled => spi2_enabled
);
SPI2_CS <= not spi2_enabled;
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
sram_inst: sdram_ctrl
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => sram_wb_dat_o,
wb_dat_i => sram_wb_dat_i,
wb_adr_i => sram_wb_adr_i(maxIObit downto minIObit),
wb_we_i => sram_wb_we_i,
wb_cyc_i => sram_wb_cyc_i,
wb_stb_i => sram_wb_stb_i,
wb_sel_i => sram_wb_sel_i,
--wb_cti_i => CTI_CYCLE_CLASSIC,
wb_ack_o => sram_wb_ack_o,
wb_stall_o => sram_wb_stall_o,
clk_off_3ns => sysclk_sram_we,
DRAM_ADDR => DRAM_ADDR(11 downto 0),
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N
);
DRAM_ADDR(12) <= '0';
-- Papilio Note: Place your Wishbone components here. #Wishbone
-- Look at the ZPUino User Guide for what Wishbone components are available:
-- http://www.papilio.cc/index.php?n=Papilio.ZPUinoUserGuide#Reference
--
-- IO SLOT 8
--
slot8 : I2C_MasterTop
--generic map(DEBUG => false,
-- FULL_SYNC => false,
-- FIXED_PRER => 96)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(8)( 7 downto 0 ),
wb_dat_i => slot_write(8)( 7 downto 0 ),
wb_adr_i => unsigned(slot_address(8)( 4 downto 2 )),
wb_we_i => slot_we(8),
wb_cyc_i => slot_cyc(8),
wb_stb_i => slot_stb(8),
wb_ack_o => slot_ack(8),
wb_inta_o => slot_interrupt(8),
-- i2c lines
scl_pad_i => scl_padi,
scl_pad_o => scl_pado,
scl_padoen_o => scl_padoen,
sda_pad_i => sda_padi,
sda_pad_o => sda_pado,
sda_padoen_o => sda_padoen
);
-- SCL/SDA pads
SCL <= 'Z' when scl_padoen='1' else scl_pado;-- after 600 ns;
scl_padi <= sclr;
SDA <= 'Z' when sda_padoen='1' else sda_pado;-- after 600 ns;
sda_padi <= sdar;
-- SCL/SDA values converted to X/0/1/Z
-- The I2C module can't handle 'H'
sdar <= to_x01z(SDA);
sclr <= to_x01z(SCL);
--
-- IO SLOT 9
--
slot9: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(9),
wb_dat_i => slot_write(9),
wb_adr_i => slot_address(9),
wb_we_i => slot_we(9),
wb_cyc_i => slot_cyc(9),
wb_stb_i => slot_stb(9),
wb_ack_o => slot_ack(9),
wb_inta_o => slot_interrupt(9),
mosi => AD_DIN,
miso => AD_OUT,
sck => AD_SCLK,
enabled => adc_enabled
);
AD_CS <= not adc_enabled;
--
-- IO SLOT 10
--
slot10: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(10),
wb_dat_i => slot_write(10),
wb_adr_i => slot_address(10),
wb_we_i => slot_we(10),
wb_cyc_i => slot_cyc(10),
wb_stb_i => slot_stb(10),
wb_ack_o => slot_ack(10),
wb_inta_o => slot_interrupt(10),
enabled => open,
tx => tx1,
rx => rx1
);
--
-- IO SLOT 11
--
slot11: zpuino_encoder
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(11),
wb_dat_i => slot_write(11),
wb_adr_i => slot_address(11),
wb_we_i => slot_we(11),
wb_cyc_i => slot_cyc(11),
wb_stb_i => slot_stb(11),
wb_ack_o => slot_ack(11),
wb_inta_o => slot_interrupt(11),
ENCODER_A(0) => ENCODER_A_A,
ENCODER_A(1) => ENCODER_B_A,
ENCODER_B(0) => ENCODER_A_B,
ENCODER_B(1) => ENCODER_B_B
);
--
-- IO SLOT 12
--
slot12: zpuino_ov7670
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(12),
wb_dat_i => slot_write(12),
wb_adr_i => slot_address(12),
wb_we_i => slot_we(12),
wb_cyc_i => slot_cyc(12),
wb_stb_i => slot_stb(12),
wb_ack_o => slot_ack(12),
wb_inta_o => slot_interrupt(12),
CLK50 => CLK50,
OV7670_VSYNC => OV7670_VSYNC,
OV7670_HREF => OV7670_HREF,
OV7670_PCLK => OV7670_PCLK,
OV7670_XCLK => OV7670_XCLK,
OV7670_D => OV7670_D
);
--
-- IO SLOT 13
--
slot13: zpuino_empty_device
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(13),
wb_dat_i => slot_write(13),
wb_adr_i => slot_address(13),
wb_we_i => slot_we(13),
wb_cyc_i => slot_cyc(13),
wb_stb_i => slot_stb(13),
wb_ack_o => slot_ack(13),
wb_inta_o => slot_interrupt(13)
);
--
-- IO SLOT 14
--
slot14: zpuino_empty_device
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(14),
wb_dat_i => slot_write(14),
wb_adr_i => slot_address(14),
wb_we_i => slot_we(14),
wb_cyc_i => slot_cyc(14),
wb_stb_i => slot_stb(14),
wb_ack_o => slot_ack(14),
wb_inta_o => slot_interrupt(14)
);
--
-- IO SLOT 15 - do not use
--
process(gpio_spp_read, spi_pf_mosi, spi_pf_sck,
sigmadelta_spp_data,timers_pwm_a,timers_pwm_b,
spi2_mosi,spi2_sck)
begin
gpio_spp_data <= (others => DontCareValue);
-- PPS Outputs
gpio_spp_data(0) <= sigmadelta_spp_data(0); -- PPS0 : SIGMADELTA DATA
gpio_spp_data(1) <= timers_pwm_b(0); -- PPS1 : TIMER1_0
gpio_spp_data(2) <= timers_pwm_b(1); -- PPS2 : TIMER1_1
gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
gpio_spp_data(5) <= sigmadelta_spp_data(1); -- PPS5 : SIGMADELTA1 DATA
-- PPS inputs
spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
end process;
end behave;
|
entity tb is
end;
architecture behav of tb is
begin
b : block
generic (c : natural);
generic map (c => c);
begin
assert true;
end block b;
end behav;
|
entity tb is
end;
architecture behav of tb is
begin
b : block
generic (c : natural);
generic map (c => c);
begin
assert true;
end block b;
end behav;
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S500E
-- Description: REGISTER BANK TO BE USED IN PIPELINE DEVICE THAT USES GENERAL PURPOSE REGISTERS FOR PIPELINE USE
--
-- Dependencies: IEEE.STD_LOGIC_1164
--
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity RegisterBank is
Port ( RAddr : in STD_LOGIC_VECTOR (3 downto 0); --
RBddr : in STD_LOGIC_VECTOR (3 downto 0); --
RWddr : in STD_LOGIC_VECTOR (3 downto 0);
DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
R : in STD_LOGIC;
W : in STD_LOGIC;
RAout : out STD_LOGIC_VECTOR (15 downto 0); --
RBout : out STD_LOGIC_VECTOR (15 downto 0)); --
end RegisterBank;
architecture Behavioral of RegisterBank is
signal R0dat, R1dat, R2dat, R3dat, R4dat, R5dat, R6dat, R7dat, R8dat, R9dat,
R10dat, R11dat, R12dat, R13dat, R14dat, R15dat : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');
begin
process(clk) -- Synchronous register bank
begin
if(rising_edge(clk) and R = '1') then -- Synchronous data read when read line enabled on rising edge (before write back)
case RAddr is
when x"0" => RAout <= R0dat;
when x"1" => RAout <= R1dat;
when x"2" => RAout <= R2dat;
when x"3" => RAout <= R3dat;
when x"4" => RAout <= R4dat;
when x"5" => RAout <= R5dat;
when x"6" => RAout <= R6dat;
when x"7" => RAout <= R7dat;
when x"8" => RAout <= R8dat;
when x"9" => RAout <= R9dat;
when x"A" => RAout <= R10dat;
when x"B" => RAout <= R11dat;
when x"C" => RAout <= R12dat;
when x"D" => RAout <= R13dat;
when x"E" => RAout <= R14dat;
when x"F" => RAout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
case RBddr is
when x"0" => RBout <= R0dat;
when x"1" => RBout <= R1dat;
when x"2" => RBout <= R2dat;
when x"3" => RBout <= R3dat;
when x"4" => RBout <= R4dat;
when x"5" => RBout <= R5dat;
when x"6" => RBout <= R6dat;
when x"7" => RBout <= R7dat;
when x"8" => RBout <= R8dat;
when x"9" => RBout <= R9dat;
when x"A" => RBout <= R10dat;
when x"B" => RBout <= R11dat;
when x"C" => RBout <= R12dat;
when x"D" => RBout <= R13dat;
when x"E" => RBout <= R14dat;
when x"F" => RBout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
if(falling_edge(clk) and W = '1') then -- Synchronous data latching when write line enabled (after data read)
case RWddr is
when x"0" => R0dat <= DATAIN;
when x"1" => R1dat <= DATAIN;
when x"2" => R2dat <= DATAIN;
when x"3" => R3dat <= DATAIN;
when x"4" => R4dat <= DATAIN;
when x"5" => R5dat <= DATAIN;
when x"6" => R6dat <= DATAIN;
when x"7" => R7dat <= DATAIN;
when x"8" => R8dat <= DATAIN;
when x"9" => R9dat <= DATAIN;
when x"A" => R10dat <= DATAIN;
when x"B" => R11dat <= DATAIN;
when x"C" => R12dat <= DATAIN;
when x"D" => R13dat <= DATAIN;
when x"E" => R14dat <= DATAIN;
when x"F" => R15dat <= DATAIN;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S500E
-- Description: REGISTER BANK TO BE USED IN PIPELINE DEVICE THAT USES GENERAL PURPOSE REGISTERS FOR PIPELINE USE
--
-- Dependencies: IEEE.STD_LOGIC_1164
--
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity RegisterBank is
Port ( RAddr : in STD_LOGIC_VECTOR (3 downto 0); --
RBddr : in STD_LOGIC_VECTOR (3 downto 0); --
RWddr : in STD_LOGIC_VECTOR (3 downto 0);
DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
R : in STD_LOGIC;
W : in STD_LOGIC;
RAout : out STD_LOGIC_VECTOR (15 downto 0); --
RBout : out STD_LOGIC_VECTOR (15 downto 0)); --
end RegisterBank;
architecture Behavioral of RegisterBank is
signal R0dat, R1dat, R2dat, R3dat, R4dat, R5dat, R6dat, R7dat, R8dat, R9dat,
R10dat, R11dat, R12dat, R13dat, R14dat, R15dat : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');
begin
process(clk) -- Synchronous register bank
begin
if(rising_edge(clk) and R = '1') then -- Synchronous data read when read line enabled on rising edge (before write back)
case RAddr is
when x"0" => RAout <= R0dat;
when x"1" => RAout <= R1dat;
when x"2" => RAout <= R2dat;
when x"3" => RAout <= R3dat;
when x"4" => RAout <= R4dat;
when x"5" => RAout <= R5dat;
when x"6" => RAout <= R6dat;
when x"7" => RAout <= R7dat;
when x"8" => RAout <= R8dat;
when x"9" => RAout <= R9dat;
when x"A" => RAout <= R10dat;
when x"B" => RAout <= R11dat;
when x"C" => RAout <= R12dat;
when x"D" => RAout <= R13dat;
when x"E" => RAout <= R14dat;
when x"F" => RAout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
case RBddr is
when x"0" => RBout <= R0dat;
when x"1" => RBout <= R1dat;
when x"2" => RBout <= R2dat;
when x"3" => RBout <= R3dat;
when x"4" => RBout <= R4dat;
when x"5" => RBout <= R5dat;
when x"6" => RBout <= R6dat;
when x"7" => RBout <= R7dat;
when x"8" => RBout <= R8dat;
when x"9" => RBout <= R9dat;
when x"A" => RBout <= R10dat;
when x"B" => RBout <= R11dat;
when x"C" => RBout <= R12dat;
when x"D" => RBout <= R13dat;
when x"E" => RBout <= R14dat;
when x"F" => RBout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
if(falling_edge(clk) and W = '1') then -- Synchronous data latching when write line enabled (after data read)
case RWddr is
when x"0" => R0dat <= DATAIN;
when x"1" => R1dat <= DATAIN;
when x"2" => R2dat <= DATAIN;
when x"3" => R3dat <= DATAIN;
when x"4" => R4dat <= DATAIN;
when x"5" => R5dat <= DATAIN;
when x"6" => R6dat <= DATAIN;
when x"7" => R7dat <= DATAIN;
when x"8" => R8dat <= DATAIN;
when x"9" => R9dat <= DATAIN;
when x"A" => R10dat <= DATAIN;
when x"B" => R11dat <= DATAIN;
when x"C" => R12dat <= DATAIN;
when x"D" => R13dat <= DATAIN;
when x"E" => R14dat <= DATAIN;
when x"F" => R15dat <= DATAIN;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S500E
-- Description: REGISTER BANK TO BE USED IN PIPELINE DEVICE THAT USES GENERAL PURPOSE REGISTERS FOR PIPELINE USE
--
-- Dependencies: IEEE.STD_LOGIC_1164
--
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity RegisterBank is
Port ( RAddr : in STD_LOGIC_VECTOR (3 downto 0); --
RBddr : in STD_LOGIC_VECTOR (3 downto 0); --
RWddr : in STD_LOGIC_VECTOR (3 downto 0);
DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
R : in STD_LOGIC;
W : in STD_LOGIC;
RAout : out STD_LOGIC_VECTOR (15 downto 0); --
RBout : out STD_LOGIC_VECTOR (15 downto 0)); --
end RegisterBank;
architecture Behavioral of RegisterBank is
signal R0dat, R1dat, R2dat, R3dat, R4dat, R5dat, R6dat, R7dat, R8dat, R9dat,
R10dat, R11dat, R12dat, R13dat, R14dat, R15dat : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');
begin
process(clk) -- Synchronous register bank
begin
if(rising_edge(clk) and R = '1') then -- Synchronous data read when read line enabled on rising edge (before write back)
case RAddr is
when x"0" => RAout <= R0dat;
when x"1" => RAout <= R1dat;
when x"2" => RAout <= R2dat;
when x"3" => RAout <= R3dat;
when x"4" => RAout <= R4dat;
when x"5" => RAout <= R5dat;
when x"6" => RAout <= R6dat;
when x"7" => RAout <= R7dat;
when x"8" => RAout <= R8dat;
when x"9" => RAout <= R9dat;
when x"A" => RAout <= R10dat;
when x"B" => RAout <= R11dat;
when x"C" => RAout <= R12dat;
when x"D" => RAout <= R13dat;
when x"E" => RAout <= R14dat;
when x"F" => RAout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
case RBddr is
when x"0" => RBout <= R0dat;
when x"1" => RBout <= R1dat;
when x"2" => RBout <= R2dat;
when x"3" => RBout <= R3dat;
when x"4" => RBout <= R4dat;
when x"5" => RBout <= R5dat;
when x"6" => RBout <= R6dat;
when x"7" => RBout <= R7dat;
when x"8" => RBout <= R8dat;
when x"9" => RBout <= R9dat;
when x"A" => RBout <= R10dat;
when x"B" => RBout <= R11dat;
when x"C" => RBout <= R12dat;
when x"D" => RBout <= R13dat;
when x"E" => RBout <= R14dat;
when x"F" => RBout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
if(falling_edge(clk) and W = '1') then -- Synchronous data latching when write line enabled (after data read)
case RWddr is
when x"0" => R0dat <= DATAIN;
when x"1" => R1dat <= DATAIN;
when x"2" => R2dat <= DATAIN;
when x"3" => R3dat <= DATAIN;
when x"4" => R4dat <= DATAIN;
when x"5" => R5dat <= DATAIN;
when x"6" => R6dat <= DATAIN;
when x"7" => R7dat <= DATAIN;
when x"8" => R8dat <= DATAIN;
when x"9" => R9dat <= DATAIN;
when x"A" => R10dat <= DATAIN;
when x"B" => R11dat <= DATAIN;
when x"C" => R12dat <= DATAIN;
when x"D" => R13dat <= DATAIN;
when x"E" => R14dat <= DATAIN;
when x"F" => R15dat <= DATAIN;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S500E
-- Description: REGISTER BANK TO BE USED IN PIPELINE DEVICE THAT USES GENERAL PURPOSE REGISTERS FOR PIPELINE USE
--
-- Dependencies: IEEE.STD_LOGIC_1164
--
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity RegisterBank is
Port ( RAddr : in STD_LOGIC_VECTOR (3 downto 0); --
RBddr : in STD_LOGIC_VECTOR (3 downto 0); --
RWddr : in STD_LOGIC_VECTOR (3 downto 0);
DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
R : in STD_LOGIC;
W : in STD_LOGIC;
RAout : out STD_LOGIC_VECTOR (15 downto 0); --
RBout : out STD_LOGIC_VECTOR (15 downto 0)); --
end RegisterBank;
architecture Behavioral of RegisterBank is
signal R0dat, R1dat, R2dat, R3dat, R4dat, R5dat, R6dat, R7dat, R8dat, R9dat,
R10dat, R11dat, R12dat, R13dat, R14dat, R15dat : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');
begin
process(clk) -- Synchronous register bank
begin
if(rising_edge(clk) and R = '1') then -- Synchronous data read when read line enabled on rising edge (before write back)
case RAddr is
when x"0" => RAout <= R0dat;
when x"1" => RAout <= R1dat;
when x"2" => RAout <= R2dat;
when x"3" => RAout <= R3dat;
when x"4" => RAout <= R4dat;
when x"5" => RAout <= R5dat;
when x"6" => RAout <= R6dat;
when x"7" => RAout <= R7dat;
when x"8" => RAout <= R8dat;
when x"9" => RAout <= R9dat;
when x"A" => RAout <= R10dat;
when x"B" => RAout <= R11dat;
when x"C" => RAout <= R12dat;
when x"D" => RAout <= R13dat;
when x"E" => RAout <= R14dat;
when x"F" => RAout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
case RBddr is
when x"0" => RBout <= R0dat;
when x"1" => RBout <= R1dat;
when x"2" => RBout <= R2dat;
when x"3" => RBout <= R3dat;
when x"4" => RBout <= R4dat;
when x"5" => RBout <= R5dat;
when x"6" => RBout <= R6dat;
when x"7" => RBout <= R7dat;
when x"8" => RBout <= R8dat;
when x"9" => RBout <= R9dat;
when x"A" => RBout <= R10dat;
when x"B" => RBout <= R11dat;
when x"C" => RBout <= R12dat;
when x"D" => RBout <= R13dat;
when x"E" => RBout <= R14dat;
when x"F" => RBout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
if(falling_edge(clk) and W = '1') then -- Synchronous data latching when write line enabled (after data read)
case RWddr is
when x"0" => R0dat <= DATAIN;
when x"1" => R1dat <= DATAIN;
when x"2" => R2dat <= DATAIN;
when x"3" => R3dat <= DATAIN;
when x"4" => R4dat <= DATAIN;
when x"5" => R5dat <= DATAIN;
when x"6" => R6dat <= DATAIN;
when x"7" => R7dat <= DATAIN;
when x"8" => R8dat <= DATAIN;
when x"9" => R9dat <= DATAIN;
when x"A" => R10dat <= DATAIN;
when x"B" => R11dat <= DATAIN;
when x"C" => R12dat <= DATAIN;
when x"D" => R13dat <= DATAIN;
when x"E" => R14dat <= DATAIN;
when x"F" => R15dat <= DATAIN;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S500E
-- Description: REGISTER BANK TO BE USED IN PIPELINE DEVICE THAT USES GENERAL PURPOSE REGISTERS FOR PIPELINE USE
--
-- Dependencies: IEEE.STD_LOGIC_1164
--
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity RegisterBank is
Port ( RAddr : in STD_LOGIC_VECTOR (3 downto 0); --
RBddr : in STD_LOGIC_VECTOR (3 downto 0); --
RWddr : in STD_LOGIC_VECTOR (3 downto 0);
DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
R : in STD_LOGIC;
W : in STD_LOGIC;
RAout : out STD_LOGIC_VECTOR (15 downto 0); --
RBout : out STD_LOGIC_VECTOR (15 downto 0)); --
end RegisterBank;
architecture Behavioral of RegisterBank is
signal R0dat, R1dat, R2dat, R3dat, R4dat, R5dat, R6dat, R7dat, R8dat, R9dat,
R10dat, R11dat, R12dat, R13dat, R14dat, R15dat : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');
begin
process(clk) -- Synchronous register bank
begin
if(rising_edge(clk) and R = '1') then -- Synchronous data read when read line enabled on rising edge (before write back)
case RAddr is
when x"0" => RAout <= R0dat;
when x"1" => RAout <= R1dat;
when x"2" => RAout <= R2dat;
when x"3" => RAout <= R3dat;
when x"4" => RAout <= R4dat;
when x"5" => RAout <= R5dat;
when x"6" => RAout <= R6dat;
when x"7" => RAout <= R7dat;
when x"8" => RAout <= R8dat;
when x"9" => RAout <= R9dat;
when x"A" => RAout <= R10dat;
when x"B" => RAout <= R11dat;
when x"C" => RAout <= R12dat;
when x"D" => RAout <= R13dat;
when x"E" => RAout <= R14dat;
when x"F" => RAout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
case RBddr is
when x"0" => RBout <= R0dat;
when x"1" => RBout <= R1dat;
when x"2" => RBout <= R2dat;
when x"3" => RBout <= R3dat;
when x"4" => RBout <= R4dat;
when x"5" => RBout <= R5dat;
when x"6" => RBout <= R6dat;
when x"7" => RBout <= R7dat;
when x"8" => RBout <= R8dat;
when x"9" => RBout <= R9dat;
when x"A" => RBout <= R10dat;
when x"B" => RBout <= R11dat;
when x"C" => RBout <= R12dat;
when x"D" => RBout <= R13dat;
when x"E" => RBout <= R14dat;
when x"F" => RBout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
if(falling_edge(clk) and W = '1') then -- Synchronous data latching when write line enabled (after data read)
case RWddr is
when x"0" => R0dat <= DATAIN;
when x"1" => R1dat <= DATAIN;
when x"2" => R2dat <= DATAIN;
when x"3" => R3dat <= DATAIN;
when x"4" => R4dat <= DATAIN;
when x"5" => R5dat <= DATAIN;
when x"6" => R6dat <= DATAIN;
when x"7" => R7dat <= DATAIN;
when x"8" => R8dat <= DATAIN;
when x"9" => R9dat <= DATAIN;
when x"A" => R10dat <= DATAIN;
when x"B" => R11dat <= DATAIN;
when x"C" => R12dat <= DATAIN;
when x"D" => R13dat <= DATAIN;
when x"E" => R14dat <= DATAIN;
when x"F" => R15dat <= DATAIN;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S500E
-- Description: REGISTER BANK TO BE USED IN PIPELINE DEVICE THAT USES GENERAL PURPOSE REGISTERS FOR PIPELINE USE
--
-- Dependencies: IEEE.STD_LOGIC_1164
--
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity RegisterBank is
Port ( RAddr : in STD_LOGIC_VECTOR (3 downto 0); --
RBddr : in STD_LOGIC_VECTOR (3 downto 0); --
RWddr : in STD_LOGIC_VECTOR (3 downto 0);
DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
R : in STD_LOGIC;
W : in STD_LOGIC;
RAout : out STD_LOGIC_VECTOR (15 downto 0); --
RBout : out STD_LOGIC_VECTOR (15 downto 0)); --
end RegisterBank;
architecture Behavioral of RegisterBank is
signal R0dat, R1dat, R2dat, R3dat, R4dat, R5dat, R6dat, R7dat, R8dat, R9dat,
R10dat, R11dat, R12dat, R13dat, R14dat, R15dat : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');
begin
process(clk) -- Synchronous register bank
begin
if(rising_edge(clk) and R = '1') then -- Synchronous data read when read line enabled on rising edge (before write back)
case RAddr is
when x"0" => RAout <= R0dat;
when x"1" => RAout <= R1dat;
when x"2" => RAout <= R2dat;
when x"3" => RAout <= R3dat;
when x"4" => RAout <= R4dat;
when x"5" => RAout <= R5dat;
when x"6" => RAout <= R6dat;
when x"7" => RAout <= R7dat;
when x"8" => RAout <= R8dat;
when x"9" => RAout <= R9dat;
when x"A" => RAout <= R10dat;
when x"B" => RAout <= R11dat;
when x"C" => RAout <= R12dat;
when x"D" => RAout <= R13dat;
when x"E" => RAout <= R14dat;
when x"F" => RAout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
case RBddr is
when x"0" => RBout <= R0dat;
when x"1" => RBout <= R1dat;
when x"2" => RBout <= R2dat;
when x"3" => RBout <= R3dat;
when x"4" => RBout <= R4dat;
when x"5" => RBout <= R5dat;
when x"6" => RBout <= R6dat;
when x"7" => RBout <= R7dat;
when x"8" => RBout <= R8dat;
when x"9" => RBout <= R9dat;
when x"A" => RBout <= R10dat;
when x"B" => RBout <= R11dat;
when x"C" => RBout <= R12dat;
when x"D" => RBout <= R13dat;
when x"E" => RBout <= R14dat;
when x"F" => RBout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
if(falling_edge(clk) and W = '1') then -- Synchronous data latching when write line enabled (after data read)
case RWddr is
when x"0" => R0dat <= DATAIN;
when x"1" => R1dat <= DATAIN;
when x"2" => R2dat <= DATAIN;
when x"3" => R3dat <= DATAIN;
when x"4" => R4dat <= DATAIN;
when x"5" => R5dat <= DATAIN;
when x"6" => R6dat <= DATAIN;
when x"7" => R7dat <= DATAIN;
when x"8" => R8dat <= DATAIN;
when x"9" => R9dat <= DATAIN;
when x"A" => R10dat <= DATAIN;
when x"B" => R11dat <= DATAIN;
when x"C" => R12dat <= DATAIN;
when x"D" => R13dat <= DATAIN;
when x"E" => R14dat <= DATAIN;
when x"F" => R15dat <= DATAIN;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S500E
-- Description: REGISTER BANK TO BE USED IN PIPELINE DEVICE THAT USES GENERAL PURPOSE REGISTERS FOR PIPELINE USE
--
-- Dependencies: IEEE.STD_LOGIC_1164
--
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity RegisterBank is
Port ( RAddr : in STD_LOGIC_VECTOR (3 downto 0); --
RBddr : in STD_LOGIC_VECTOR (3 downto 0); --
RWddr : in STD_LOGIC_VECTOR (3 downto 0);
DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
R : in STD_LOGIC;
W : in STD_LOGIC;
RAout : out STD_LOGIC_VECTOR (15 downto 0); --
RBout : out STD_LOGIC_VECTOR (15 downto 0)); --
end RegisterBank;
architecture Behavioral of RegisterBank is
signal R0dat, R1dat, R2dat, R3dat, R4dat, R5dat, R6dat, R7dat, R8dat, R9dat,
R10dat, R11dat, R12dat, R13dat, R14dat, R15dat : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');
begin
process(clk) -- Synchronous register bank
begin
if(rising_edge(clk) and R = '1') then -- Synchronous data read when read line enabled on rising edge (before write back)
case RAddr is
when x"0" => RAout <= R0dat;
when x"1" => RAout <= R1dat;
when x"2" => RAout <= R2dat;
when x"3" => RAout <= R3dat;
when x"4" => RAout <= R4dat;
when x"5" => RAout <= R5dat;
when x"6" => RAout <= R6dat;
when x"7" => RAout <= R7dat;
when x"8" => RAout <= R8dat;
when x"9" => RAout <= R9dat;
when x"A" => RAout <= R10dat;
when x"B" => RAout <= R11dat;
when x"C" => RAout <= R12dat;
when x"D" => RAout <= R13dat;
when x"E" => RAout <= R14dat;
when x"F" => RAout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
case RBddr is
when x"0" => RBout <= R0dat;
when x"1" => RBout <= R1dat;
when x"2" => RBout <= R2dat;
when x"3" => RBout <= R3dat;
when x"4" => RBout <= R4dat;
when x"5" => RBout <= R5dat;
when x"6" => RBout <= R6dat;
when x"7" => RBout <= R7dat;
when x"8" => RBout <= R8dat;
when x"9" => RBout <= R9dat;
when x"A" => RBout <= R10dat;
when x"B" => RBout <= R11dat;
when x"C" => RBout <= R12dat;
when x"D" => RBout <= R13dat;
when x"E" => RBout <= R14dat;
when x"F" => RBout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
if(falling_edge(clk) and W = '1') then -- Synchronous data latching when write line enabled (after data read)
case RWddr is
when x"0" => R0dat <= DATAIN;
when x"1" => R1dat <= DATAIN;
when x"2" => R2dat <= DATAIN;
when x"3" => R3dat <= DATAIN;
when x"4" => R4dat <= DATAIN;
when x"5" => R5dat <= DATAIN;
when x"6" => R6dat <= DATAIN;
when x"7" => R7dat <= DATAIN;
when x"8" => R8dat <= DATAIN;
when x"9" => R9dat <= DATAIN;
when x"A" => R10dat <= DATAIN;
when x"B" => R11dat <= DATAIN;
when x"C" => R12dat <= DATAIN;
when x"D" => R13dat <= DATAIN;
when x"E" => R14dat <= DATAIN;
when x"F" => R15dat <= DATAIN;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
end process;
end Behavioral;
|
--! @file dpRamSplx-rtl-a.vhd
--
--! @brief Simplex Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the Simplex DPRAM intended for synthesis on Altera
--! platforms only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use altera_mf library
library altera_mf;
use altera_mf.altera_mf_components.all;
architecture rtl of dpRamSplx is
begin
altsyncram_component : altsyncram
generic map (
operation_mode => "DUAL_PORT",
intended_device_family => "Cyclone IV",
init_file => gInitFile,
numwords_a => gNumberOfWordsA,
numwords_b => gNumberOfWordsB,
widthad_a => logDualis(gNumberOfWordsA),
widthad_b => logDualis(gNumberOfWordsB),
width_a => gWordWidthA,
width_b => gWordWidthB,
width_byteena_a => gByteenableWidthA,
width_byteena_b => gByteenableWidthA
)
port map (
clock0 => iClk_A,
clocken0 => iEnable_A,
wren_a => iWriteEnable_A,
address_a => iAddress_A,
byteena_a => iByteenable_A,
data_a => iWritedata_A,
clock1 => iClk_B,
clocken1 => iEnable_B,
address_b => iAddress_B,
q_b => oReaddata_B
);
end architecture rtl;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect end_protected
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_gaussian_blur:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_gaussian_blur_2_0 IS
PORT (
en : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
active_in : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
xaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
active_out : OUT STD_LOGIC;
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
xaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_gaussian_blur_2_0;
ARCHITECTURE system_vga_gaussian_blur_2_0_arch OF system_vga_gaussian_blur_2_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_gaussian_blur_2_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_gaussian_blur IS
GENERIC (
H_SIZE : INTEGER;
H_DELAY : INTEGER;
KERNEL : INTEGER
);
PORT (
en : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
active_in : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
xaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
active_out : OUT STD_LOGIC;
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
xaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_gaussian_blur;
BEGIN
U0 : vga_gaussian_blur
GENERIC MAP (
H_SIZE => 640,
H_DELAY => 160,
KERNEL => 3
)
PORT MAP (
en => en,
clk_25 => clk_25,
active_in => active_in,
hsync_in => hsync_in,
vsync_in => vsync_in,
xaddr_in => xaddr_in,
yaddr_in => yaddr_in,
rgb_in => rgb_in,
active_out => active_out,
hsync_out => hsync_out,
vsync_out => vsync_out,
xaddr_out => xaddr_out,
yaddr_out => yaddr_out,
rgb_out => rgb_out
);
END system_vga_gaussian_blur_2_0_arch;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: dist_mem_gen_v7_2_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY dist_mem_gen_v7_2_tb IS
END ENTITY;
ARCHITECTURE dist_mem_gen_v7_2_tb_ARCH OF dist_mem_gen_v7_2_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
dist_mem_gen_v7_2_tb_synth_inst:ENTITY work.dist_mem_gen_v7_2_tb_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
architecture RTL of FIFO is
begin
process is
begin
end process;
process
begin
end process;
-- Violations below
process is begin
end process;
a <= b;
process begin
end process;
b <= z;
end architecture RTL;
|
-- megafunction wizard: %LPM_DECODE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_decode
-- ============================================================
-- File Name: lpm_decode0.vhd
-- Megafunction Name(s):
-- lpm_decode
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_decode0 IS
PORT
(
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
eq0 : OUT STD_LOGIC ;
eq1 : OUT STD_LOGIC ;
eq2 : OUT STD_LOGIC ;
eq3 : OUT STD_LOGIC ;
eq4 : OUT STD_LOGIC ;
eq5 : OUT STD_LOGIC ;
eq6 : OUT STD_LOGIC ;
eq7 : OUT STD_LOGIC
);
END lpm_decode0;
ARCHITECTURE SYN OF lpm_decode0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC ;
COMPONENT lpm_decode
GENERIC (
lpm_decodes : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
eq : OUT STD_LOGIC_VECTOR (lpm_decodes-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire8 <= sub_wire0(7);
sub_wire7 <= sub_wire0(6);
sub_wire6 <= sub_wire0(5);
sub_wire5 <= sub_wire0(4);
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
eq0 <= sub_wire1;
eq1 <= sub_wire2;
eq2 <= sub_wire3;
eq3 <= sub_wire4;
eq4 <= sub_wire5;
eq5 <= sub_wire6;
eq6 <= sub_wire7;
eq7 <= sub_wire8;
lpm_decode_component : lpm_decode
GENERIC MAP (
lpm_decodes => 8,
lpm_type => "LPM_DECODE",
lpm_width => 3
)
PORT MAP (
data => data,
eq => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BaseDec NUMERIC "1"
-- Retrieval info: PRIVATE: EnableInput NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: eq0 NUMERIC "1"
-- Retrieval info: PRIVATE: eq1 NUMERIC "1"
-- Retrieval info: PRIVATE: eq2 NUMERIC "1"
-- Retrieval info: PRIVATE: eq3 NUMERIC "1"
-- Retrieval info: PRIVATE: eq4 NUMERIC "1"
-- Retrieval info: PRIVATE: eq5 NUMERIC "1"
-- Retrieval info: PRIVATE: eq6 NUMERIC "1"
-- Retrieval info: PRIVATE: eq7 NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "3"
-- Retrieval info: CONSTANT: LPM_DECODES NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DECODE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "3"
-- Retrieval info: USED_PORT: @eq 0 0 LPM_DECODES 0 OUTPUT NODEFVAL @eq[LPM_DECODES-1..0]
-- Retrieval info: USED_PORT: data 0 0 3 0 INPUT NODEFVAL data[2..0]
-- Retrieval info: USED_PORT: eq0 0 0 0 0 OUTPUT NODEFVAL eq0
-- Retrieval info: USED_PORT: eq1 0 0 0 0 OUTPUT NODEFVAL eq1
-- Retrieval info: USED_PORT: eq2 0 0 0 0 OUTPUT NODEFVAL eq2
-- Retrieval info: USED_PORT: eq3 0 0 0 0 OUTPUT NODEFVAL eq3
-- Retrieval info: USED_PORT: eq4 0 0 0 0 OUTPUT NODEFVAL eq4
-- Retrieval info: USED_PORT: eq5 0 0 0 0 OUTPUT NODEFVAL eq5
-- Retrieval info: USED_PORT: eq6 0 0 0 0 OUTPUT NODEFVAL eq6
-- Retrieval info: USED_PORT: eq7 0 0 0 0 OUTPUT NODEFVAL eq7
-- Retrieval info: CONNECT: @data 0 0 3 0 data 0 0 3 0
-- Retrieval info: CONNECT: eq0 0 0 0 0 @eq 0 0 1 0
-- Retrieval info: CONNECT: eq1 0 0 0 0 @eq 0 0 1 1
-- Retrieval info: CONNECT: eq2 0 0 0 0 @eq 0 0 1 2
-- Retrieval info: CONNECT: eq3 0 0 0 0 @eq 0 0 1 3
-- Retrieval info: CONNECT: eq4 0 0 0 0 @eq 0 0 1 4
-- Retrieval info: CONNECT: eq5 0 0 0 0 @eq 0 0 1 5
-- Retrieval info: CONNECT: eq6 0 0 0 0 @eq 0 0 1 6
-- Retrieval info: CONNECT: eq7 0 0 0 0 @eq 0 0 1 7
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
architecture rtl of fifo is
alias designator IS name;
alias designator IS name;
begin
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity mux4x4 is
port(s : in std_logic_vector(1 downto 0);
d0, d1, d2, d3: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0)
);
end mux4x4;
architecture logic of mux4x4 is
begin
with s select output <= d0 when "00",
d1 when "01",
d2 when "10",
d3 when "11";
end logic; |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity mux4x4 is
port(s : in std_logic_vector(1 downto 0);
d0, d1, d2, d3: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0)
);
end mux4x4;
architecture logic of mux4x4 is
begin
with s select output <= d0 when "00",
d1 when "01",
d2 when "10",
d3 when "11";
end logic; |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity mux4x4 is
port(s : in std_logic_vector(1 downto 0);
d0, d1, d2, d3: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0)
);
end mux4x4;
architecture logic of mux4x4 is
begin
with s select output <= d0 when "00",
d1 when "01",
d2 when "10",
d3 when "11";
end logic; |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity mux4x4 is
port(s : in std_logic_vector(1 downto 0);
d0, d1, d2, d3: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0)
);
end mux4x4;
architecture logic of mux4x4 is
begin
with s select output <= d0 when "00",
d1 when "01",
d2 when "10",
d3 when "11";
end logic; |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Sat Oct 31 15:04:15 2015
-- Host : cascade.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.1 (Maipo)
-- Command : write_vhdl -force -mode funcsim
-- /afs/ece.cmu.edu/usr/rmrobert/Private/18545/Atari7800/Atari7800/Atari7800.srcs/sources_1/ip/BIOS_ROM/BIOS_ROM_funcsim.vhdl
-- Design : BIOS_ROM
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity BIOS_ROM_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of BIOS_ROM_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end BIOS_ROM_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of BIOS_ROM_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00F46C48",
INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"FFFD2DFFFCADF410CA88EAD0FD80D9FE00BD7FA2FFA0018516A926C24C26C24C",
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INIT_2A => X"EDB890FA94A38734FC17A98473FBD1383108C8AF45063DE6B7592078BE81C5DC",
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INIT_6A => X"1FFEFF07807F00F8FF1FE07F807F80FF01FC837FF00F7EF8871F808F7F7C808F",
INIT_6B => X"00FFC03F00FCC3FF00F03F00C03FFF0000FF0300FCF30F00FE0300807F0000F0",
INIT_6C => X"03C0FFF03F00FC03F00F00FF03C03F00FF00FC03FC3FF03F00F00FFC0300FF03",
INIT_6D => X"F8871F808F7F7C808F7F7C00FC03F03FF03F00FFFFFF3F00FF03F0FFFFFF03FC",
INIT_6E => X"0FFE0F00807F0000FC1FFEFF0F807F00FCFF1FC0FF807FC0FF00F8837FF0077E",
INIT_6F => X"3FF03F0000FF03FF03FF0300F03FFC03FC0FF03FC0FFFFFFFF00FF03FCFFFFFF",
INIT_70 => X"8F7F7C808F7F7C00FCC3FF00F03FFC0F0000FC0FFFC3FF0000C0FFFC03FF03F0",
INIT_71 => X"807F0000FF1FFEFF1F807F00FEFF1F80FF807FC07F00F8837FF0077CF8870F80",
INIT_72 => X"808F7F7C808F7F7C005555555555555555555555555555555555555555FE3F00",
INIT_73 => X"00807F00C0FF1FE0FF1F807F00FEFF0100FF817FE03F00F0837FF003FCF8C70F",
INIT_74 => X"0F808F7F7C808F7F7C00AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAFEFF",
INIT_75 => X"FF01807F00E0FF1F00FE3F807F00FF1F0000FE817FE01F00F0877FF803FCF8C7",
INIT_76 => X"8158601B0812B4C6C9CA095555555555555555555555555555555555555555FE",
INIT_77 => X"9306CD8A2DAFECC53B000A8DFAE2E22FBC7C3B847932DC7BA025D9BFD801864B",
INIT_78 => X"C855510C4723EF20B5066DF7E873D37168A20CCE8CEF3653B26AC4774614A56A",
INIT_79 => X"BD870A801D8F71B388CC222D3B583CF86305D8C4E276B03867A7203FC458F4FE",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEA3942806846ECD3E270E92359A1",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"F933F884F000F72D34383931294328434347FFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity BIOS_ROM_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of BIOS_ROM_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end BIOS_ROM_blk_mem_gen_prim_width;
architecture STRUCTURE of BIOS_ROM_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.BIOS_ROM_blk_mem_gen_prim_wrapper_init
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity BIOS_ROM_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of BIOS_ROM_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end BIOS_ROM_blk_mem_gen_generic_cstr;
architecture STRUCTURE of BIOS_ROM_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.BIOS_ROM_blk_mem_gen_prim_width
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity BIOS_ROM_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of BIOS_ROM_blk_mem_gen_top : entity is "blk_mem_gen_top";
end BIOS_ROM_blk_mem_gen_top;
architecture STRUCTURE of BIOS_ROM_blk_mem_gen_top is
begin
\valid.cstr\: entity work.BIOS_ROM_blk_mem_gen_generic_cstr
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity BIOS_ROM_blk_mem_gen_v8_2_synth is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of BIOS_ROM_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end BIOS_ROM_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of BIOS_ROM_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.BIOS_ROM_blk_mem_gen_top
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity BIOS_ROM_blk_mem_gen_v8_2 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of BIOS_ROM_blk_mem_gen_v8_2 : entity is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of BIOS_ROM_blk_mem_gen_v8_2 : entity is 12;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of BIOS_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of BIOS_ROM_blk_mem_gen_v8_2 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of BIOS_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of BIOS_ROM_blk_mem_gen_v8_2 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of BIOS_ROM_blk_mem_gen_v8_2 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of BIOS_ROM_blk_mem_gen_v8_2 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of BIOS_ROM_blk_mem_gen_v8_2 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of BIOS_ROM_blk_mem_gen_v8_2 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of BIOS_ROM_blk_mem_gen_v8_2 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of BIOS_ROM_blk_mem_gen_v8_2 : entity is "Estimated Power for IP : 2.535699 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of BIOS_ROM_blk_mem_gen_v8_2 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of BIOS_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of BIOS_ROM_blk_mem_gen_v8_2 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of BIOS_ROM_blk_mem_gen_v8_2 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of BIOS_ROM_blk_mem_gen_v8_2 : entity is "BIOS_ROM.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of BIOS_ROM_blk_mem_gen_v8_2 : entity is "BIOS_ROM.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of BIOS_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of BIOS_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is 4096;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is 4096;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of BIOS_ROM_blk_mem_gen_v8_2 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of BIOS_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of BIOS_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is 4096;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is 4096;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of BIOS_ROM_blk_mem_gen_v8_2 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of BIOS_ROM_blk_mem_gen_v8_2 : entity is "blk_mem_gen_v8_2";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of BIOS_ROM_blk_mem_gen_v8_2 : entity is "yes";
end BIOS_ROM_blk_mem_gen_v8_2;
architecture STRUCTURE of BIOS_ROM_blk_mem_gen_v8_2 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.BIOS_ROM_blk_mem_gen_v8_2_synth
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity BIOS_ROM is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of BIOS_ROM : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of BIOS_ROM : entity is "BIOS_ROM,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of BIOS_ROM : entity is "BIOS_ROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=BIOS_ROM.mif,C_INIT_FILE=BIOS_ROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=4096,C_READ_DEPTH_B=4096,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.535699 mW}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of BIOS_ROM : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of BIOS_ROM : entity is "blk_mem_gen_v8_2,Vivado 2015.2";
end BIOS_ROM;
architecture STRUCTURE of BIOS_ROM is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 12;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.535699 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "BIOS_ROM.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "BIOS_ROM.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 4096;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 4096;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 4096;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 4096;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.BIOS_ROM_blk_mem_gen_v8_2
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11) => '0',
addrb(10) => '0',
addrb(9) => '0',
addrb(8) => '0',
addrb(7) => '0',
addrb(6) => '0',
addrb(5) => '0',
addrb(4) => '0',
addrb(3) => '0',
addrb(2) => '0',
addrb(1) => '0',
addrb(0) => '0',
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(7 downto 0) => dina(7 downto 0),
dinb(7) => '0',
dinb(6) => '0',
dinb(5) => '0',
dinb(4) => '0',
dinb(3) => '0',
dinb(2) => '0',
dinb(1) => '0',
dinb(0) => '0',
douta(7 downto 0) => douta(7 downto 0),
doutb(7 downto 0) => NLW_U0_doutb_UNCONNECTED(7 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(11 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(11 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rstb => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arid(3) => '0',
s_axi_arid(2) => '0',
s_axi_arid(1) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awid(3) => '0',
s_axi_awid(2) => '0',
s_axi_awid(1) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(11 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(11 downto 0),
s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
library verilog;
use verilog.vl_types.all;
entity control_vlg_sample_tst is
port(
d7 : in vl_logic;
d711 : in vl_logic;
d2312 : in vl_logic;
eq : in vl_logic;
rb : in vl_logic;
reset : in vl_logic;
sampler_tx : out vl_logic
);
end control_vlg_sample_tst;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Ram_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY Ram_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE Ram_synth_ARCH OF Ram_synth IS
COMPONENT Ram_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 32,
READ_WIDTH => 32 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: Ram_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
------------------------------------------------------------------------------
--
-- File: AXI_S_to_DPTI_converter.vhd
-- Author: Sergiu Arpadi
-- Original Project: AXI DPTI
-- Date: 8 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module reads data from the AXI STREAM interface and sends it to the DPTI
-- interface. It will require a 32 bit TDATA bus, 4 bit TKEEP, TVALID and TLAST
-- as inputs and it will output the TREADY signal. It uses the DPTI clock of 60 MHz
-- to perform all the operations and it will use the maximum bandwidth of the DPTI
-- interface which is 480 mbps as long as valid data is received from the AXI STREAM
-- interface. In order to achieve this, FOR loops have been used which will generate
-- combinational logic that allows the simultaneous verification of all of the 4 TKEEP
-- bits received. Along with the DPTI clock, the module also reads the PROG_TXEN
-- signal and it will generate the PROG_D bus and PROG_WRN signal. In order to control
-- the module, two AXI Lite registers are used, one for direction/control and one for
-- the lenght of the transfer, which are synchronized in the top module.
-- The module also uses a reset signal aResetTx which is generated in the top module.
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_arith.all;
entity AXI_S_to_DPTI_converter is
Port (
-- clock, reset and DPTI signals
pResetnTx : in std_logic;
PROG_CLK : in std_logic;
pTxe : in std_logic;
pWr : out std_logic;
pDataOut : out std_logic_vector (7 downto 0);
-- AXI Stream signals
pOutTready : out std_logic;
pInTdata : in std_logic_vector (31 downto 0);
pInTvalid : in std_logic;
pInTlast : in std_logic;
pInTkeep : in std_logic_vector (3 downto 0);
-- AXI Lite registers
pAXI_L_Length : in std_logic_vector (31 downto 0);
pOvalidLength : in std_logic;
pAXI_L_Control : in std_logic_vector (31 downto 0);
pOvalidControl : in std_logic;
pTxLengthEmpty : out std_logic
);
end AXI_S_to_DPTI_converter;
architecture Behavioral of AXI_S_to_DPTI_converter is
--------------------------------------------------------------------------------------------------------------------------
signal pTxEnDir : std_logic := '0';
signal pLengthTxCnt : std_logic_vector (22 downto 0) := (others => '0');
signal Index : integer range 0 to 3;
signal pCtlOutTready : std_logic := '0';
signal pCtlWr : std_logic := '1';
signal pTransferInvalidFlag : std_logic := '1';
signal pAuxTdata : std_logic_vector(31 downto 0);
signal pAuxTkeep : std_logic_vector(3 downto 0) := (others => '0');
--------------------------------------------------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------------------------------------------------
pWr <= pCtlWr;
pOutTready <= pCtlOutTready;
--------------------------------------------------------------------------------------------------------------------------
pTxLengthEmpty <= '1' when pLengthTxCnt = 0 else '0'; -- we check to see if we are currently doing a tranfer. this will be a part of the AXI Lite status register
-- Generating TREADY signal which will request data from the AXI STREAM interface
pCtlOutTready <= '1' when (pAuxTkeep = "0001" or pAuxTkeep = "0010" or pAuxTkeep = "0100" or pAuxTkeep = "1000" or (pAuxTkeep = "0000" )) and pTxe = '0' and pLengthTxCnt > 0 else '0';
-- new data will be requested when we have at most one valid data byte in the current TDATA bus. other conditions are that a transfer must be in progress and the DPTI interface can accept more data
pTransferInvalidFlag <= '1' when pTxe = '1' and pCtlWr = '0' else '0'; -- detecting if a transfer has failed because the FT_TXE signal from FTDI was '1'
--------------------------------------------------------------------------------------------------------------------------
generate_WR: process (PROG_CLK, pLengthTxCnt, pResetnTx) -- PROG_WRN is generated
begin
if pResetnTx = '0' then
pCtlWr <= '1';
else if rising_edge (PROG_CLK) then
if pAuxTkeep /= 0 and pLengthTxCnt > 0 then -- check if the transfer is not finnished and there is at least one valid data byte
pCtlWr <= '0'; -- when the signal is 0 then the byte currently on the PROG_D bus is valid
else -- if valid data is not available or the transfer is completed
pCtlWr <= '1'; -- PROG_WRN is '1'
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
read_Tkeep_and_Tdata: process (PROG_CLK, pResetnTx)
variable aux_tkindex : integer;
begin
if pResetnTx = '0' then
aux_tkindex := 0;
pAuxTkeep <= (others => '0');
pAuxTdata <= (others => '0');
else if rising_edge(PROG_CLK)then
if pLengthTxCnt > 0 and pTxe = '0' and pTxEnDir = '1' then -- check to see if a transfer is in progress
if (pAuxTkeep = 0 or pAuxTkeep = 1 or pAuxTkeep = 2 or pAuxTkeep = 4 or pAuxTkeep = 8) and pInTvalid = '1' then -- check if the current set of TDATA and TKEEP contains at most one valid byte of data
pAuxTkeep <= pInTkeep; --new tkeep is read
pAuxTdata <= pInTdata; --new data is read
-- TDATA and TKEEP are used in the "generate_pDataOut" process below
else -- if more than one valid bytes exist
for Index in 3 downto 0 loop -- we use a FOR loop to check all of the bytes simultaneously
if pAuxTkeep (Index) = '1' then -- each valid byte is identified by checking TKEEP
aux_tkindex := Index;
end if;
end loop;
pAuxTkeep(aux_tkindex) <= '0'; --reset one bit at a time after sending the corresponding valid byte to the DPTI interface
end if;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
generate_pDataOut: process (PROG_CLK, pResetnTx)
begin
if pResetnTx = '0' then
pDataOut <= (others => '0');
pLengthTxCnt <= (others=>'0');
else if rising_edge(PROG_CLK) then
if pOvalidControl = '1' and pLengthTxCnt = 0 then -- the control bit (and the direction) can only be changed when the module is idle
pTxEnDir <= pAXI_L_Control(0); -- Reading control byte from AXI LITE register. Bit (0) sets the transfer's direction.
end if;
if pOvalidLength = '1' and pTxEnDir = '1' then -- checking if the module was enabled and if valid value is present in register
pLengthTxCnt (22 downto 0) <= pAXI_L_Length(22 downto 0); -- LENGTH register is read
end if;
if pLengthTxCnt > 0 and pTxe = '0' and pTxEnDir = '1' then -- conditions for starting transfer
for Index in 3 downto 0 loop -- the FOR loop allows us to check all of the bytes simultaneously
if pAuxTkeep (Index) = '1' then -- we identify the valid byte's position
pDataOut(7 downto 0) <= pAuxTdata((8 * (Index + 1)) -1 downto (8 * (Index))); -- the valid byte is extracted and sent to the DPTI interface
pLengthTxCnt <= pLengthTxCnt - '1'; -- since one valid byte was transferred, length is decremented
end if;
end loop;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_aa
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_aa-e.vhd,v 1.1 2006/04/10 15:42:08 wig Exp $
-- $Date: 2006/04/10 15:42:08 $
-- $Log: ent_aa-e.vhd,v $
-- Revision 1.1 2006/04/10 15:42:08 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_aa
--
entity ent_aa is
-- Generics:
-- No Generated Generics for Entity ent_aa
-- Generated Port Declaration:
-- No Generated Port for Entity ent_aa
end ent_aa;
--
-- End of Generated Entity ent_aa
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.common_types.all;
use work.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.common_types.all;
use work.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.common_types.all;
use work.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc238.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00238ent IS
END c03s01b02x00p04n01i00238ent;
ARCHITECTURE c03s01b02x00p04n01i00238arch OF c03s01b02x00p04n01i00238ent IS
type t3 is range (ns/fs) downto (fs/fs);
BEGIN
TESTING: PROCESS
variable k : integer := 6;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b02x00p04n01i00238"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b02x00p04n01i00238 - Each each bound of a range constraint that is used in an integer type definition is a locally static expression [of some integer type, but the two bounds need not have the same integer type.]"
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00238arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc238.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00238ent IS
END c03s01b02x00p04n01i00238ent;
ARCHITECTURE c03s01b02x00p04n01i00238arch OF c03s01b02x00p04n01i00238ent IS
type t3 is range (ns/fs) downto (fs/fs);
BEGIN
TESTING: PROCESS
variable k : integer := 6;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b02x00p04n01i00238"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b02x00p04n01i00238 - Each each bound of a range constraint that is used in an integer type definition is a locally static expression [of some integer type, but the two bounds need not have the same integer type.]"
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00238arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc238.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00238ent IS
END c03s01b02x00p04n01i00238ent;
ARCHITECTURE c03s01b02x00p04n01i00238arch OF c03s01b02x00p04n01i00238ent IS
type t3 is range (ns/fs) downto (fs/fs);
BEGIN
TESTING: PROCESS
variable k : integer := 6;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b02x00p04n01i00238"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b02x00p04n01i00238 - Each each bound of a range constraint that is used in an integer type definition is a locally static expression [of some integer type, but the two bounds need not have the same integer type.]"
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00238arch;
|
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
entity rcon is port (
next_value : in T_ENABLE; -- to be connected to next_rcon from controller
ctrl_dec : in T_ENCDEC;
reset, clock : in std_logic;
rcon_byte : out std_logic_vector (7 downto 0);
reset_key : in T_ENABLE;
last_key : in T_ENABLE);
end rcon;
architecture a_rcon of rcon is
signal rc_reg, s_next_rc, s_last_rcon : std_logic_vector( 7 downto 0 );
begin
SAVE_RCON_PROC : process( clock, reset )
begin
if ( reset=RESET_ACTIVE ) then
s_last_rcon <= "00000001";
elsif ( clock'event and clock='1' ) then
if (last_key = C_ENABLE) then
s_last_rcon <= rc_reg;
end if; -- nextval
end if;
end process SAVE_RCON_PROC;
process( clock, reset, reset_key, last_key )
begin
if ( reset=RESET_ACTIVE ) then
rc_reg <= "00000001";
elsif ( clock'event and clock='1' ) then
if ( next_value/=C_DISABLE ) then -- v. 1.2
rc_reg <= s_next_rc;
elsif ( reset_key = C_ENABLE ) then
rc_reg <= s_last_rcon;
end if; -- nextval
end if; -- reset, clock
end process;
idec : if ( C_INCLUDE_DECODING_LOGIC ) generate
s_next_rc <= ( rc_reg(6 downto 0) & '0' ) xor ( "000" & rc_reg(7) & rc_reg(7) & '0' & rc_reg(7) & rc_reg(7) )
when ( ctrl_dec = C_ENC )
else ( '0' & rc_reg(7 downto 1) ) xor ( rc_reg(0) & "000" & rc_reg(0) & rc_reg(0) & '0' & rc_reg(0) );
end generate; -- C_INCLUDE_DECODING_LOGIC
ienc : if ( not C_INCLUDE_DECODING_LOGIC ) generate
s_next_rc(7 downto 5) <= rc_reg(6 downto 4);
s_next_rc(4 downto 3) <= rc_reg(3 downto 2) xor ( rc_reg(7) & rc_reg(7) );
s_next_rc(2) <= rc_reg(1);
s_next_rc(1) <= rc_reg(0) xor rc_reg(7);
s_next_rc(0) <= rc_reg(7);
end generate; -- not C_INCLUDE_DECODING_LOGIC
rcon_byte <= rc_reg;
end a_rcon;
|
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
entity rcon is port (
next_value : in T_ENABLE; -- to be connected to next_rcon from controller
ctrl_dec : in T_ENCDEC;
reset, clock : in std_logic;
rcon_byte : out std_logic_vector (7 downto 0);
reset_key : in T_ENABLE;
last_key : in T_ENABLE);
end rcon;
architecture a_rcon of rcon is
signal rc_reg, s_next_rc, s_last_rcon : std_logic_vector( 7 downto 0 );
begin
SAVE_RCON_PROC : process( clock, reset )
begin
if ( reset=RESET_ACTIVE ) then
s_last_rcon <= "00000001";
elsif ( clock'event and clock='1' ) then
if (last_key = C_ENABLE) then
s_last_rcon <= rc_reg;
end if; -- nextval
end if;
end process SAVE_RCON_PROC;
process( clock, reset, reset_key, last_key )
begin
if ( reset=RESET_ACTIVE ) then
rc_reg <= "00000001";
elsif ( clock'event and clock='1' ) then
if ( next_value/=C_DISABLE ) then -- v. 1.2
rc_reg <= s_next_rc;
elsif ( reset_key = C_ENABLE ) then
rc_reg <= s_last_rcon;
end if; -- nextval
end if; -- reset, clock
end process;
idec : if ( C_INCLUDE_DECODING_LOGIC ) generate
s_next_rc <= ( rc_reg(6 downto 0) & '0' ) xor ( "000" & rc_reg(7) & rc_reg(7) & '0' & rc_reg(7) & rc_reg(7) )
when ( ctrl_dec = C_ENC )
else ( '0' & rc_reg(7 downto 1) ) xor ( rc_reg(0) & "000" & rc_reg(0) & rc_reg(0) & '0' & rc_reg(0) );
end generate; -- C_INCLUDE_DECODING_LOGIC
ienc : if ( not C_INCLUDE_DECODING_LOGIC ) generate
s_next_rc(7 downto 5) <= rc_reg(6 downto 4);
s_next_rc(4 downto 3) <= rc_reg(3 downto 2) xor ( rc_reg(7) & rc_reg(7) );
s_next_rc(2) <= rc_reg(1);
s_next_rc(1) <= rc_reg(0) xor rc_reg(7);
s_next_rc(0) <= rc_reg(7);
end generate; -- not C_INCLUDE_DECODING_LOGIC
rcon_byte <= rc_reg;
end a_rcon;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: image_selector_fifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.image_selector_fifo_pkg.ALL;
ENTITY image_selector_fifo_tb IS
END ENTITY;
ARCHITECTURE image_selector_fifo_arch OF image_selector_fifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from image_selector_fifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of image_selector_fifo_synth
image_selector_fifo_synth_inst:image_selector_fifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 28
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: image_selector_fifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.image_selector_fifo_pkg.ALL;
ENTITY image_selector_fifo_tb IS
END ENTITY;
ARCHITECTURE image_selector_fifo_arch OF image_selector_fifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from image_selector_fifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of image_selector_fifo_synth
image_selector_fifo_synth_inst:image_selector_fifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 28
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: image_selector_fifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.image_selector_fifo_pkg.ALL;
ENTITY image_selector_fifo_tb IS
END ENTITY;
ARCHITECTURE image_selector_fifo_arch OF image_selector_fifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from image_selector_fifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of image_selector_fifo_synth
image_selector_fifo_synth_inst:image_selector_fifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 28
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
-- author: Madhav P. Desai
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.Utility_Package.all;
package Vhpi_Foreign is
-----------------------------------------------------------------------------
-- foreign Vhpi function
-----------------------------------------------------------------------------
procedure Vhpi_Initialize(sock_port : in integer);
attribute foreign of Vhpi_Initialize : procedure is "VHPIDIRECT Vhpi_Initialize";
procedure Vhpi_Close; -- close .
attribute foreign of Vhpi_Close : procedure is "VHPIDIRECT Vhpi_Close";
procedure Vhpi_Listen;
attribute foreign of Vhpi_Listen : procedure is "VHPIDIRECT Vhpi_Listen";
procedure Vhpi_Send;
attribute foreign of Vhpi_Send : procedure is "VHPIDIRECT Vhpi_Send";
procedure Vhpi_Set_Port_Value(port_name: in VhpiString; port_value: in VhpiString; port_width: in integer);
attribute foreign of Vhpi_Set_Port_Value: procedure is "VHPIDIRECT Vhpi_Set_Port_Value";
procedure Vhpi_Get_Port_Value(port_name: in VhpiString; port_value : out VhpiString; port_width: in integer);
attribute foreign of Vhpi_Get_Port_Value : procedure is "VHPIDIRECT Vhpi_Get_Port_Value";
procedure Vhpi_Log(message_string: in VhpiString);
attribute foreign of Vhpi_Log : procedure is "VHPIDIRECT Vhpi_Log";
end Vhpi_Foreign;
package body Vhpi_Foreign is
-----------------------------------------------------------------------------
-- subprogram bodies for foreign vhpi routines. will never be called
-----------------------------------------------------------------------------
procedure Vhpi_Initialize(sock_port: in integer) is
begin
assert false report "fatal: this should never be called" severity failure;
end Vhpi_Initialize;
procedure Vhpi_Close is
begin
assert false report "fatal: this should never be called" severity failure;
end Vhpi_Close;
procedure Vhpi_Listen is
begin
assert false report "fatal: this should never be called" severity failure;
end Vhpi_Listen;
procedure Vhpi_Send is
begin
assert false report "fatal: this should never be called" severity failure;
end Vhpi_Send;
procedure Vhpi_Set_Port_Value(port_name: in VhpiString; port_value: in VhpiString; port_width: in integer) is
begin
assert false report "fatal: this should never be called" severity failure;
end Vhpi_Set_Port_Value;
procedure Vhpi_Get_Port_Value(port_name : in VhpiString; port_value: out VhpiString; port_width: in integer)is
begin
assert false report "fatal: this should never be called" severity failure;
end Vhpi_Get_Port_Value;
procedure Vhpi_Log(message_string: in VhpiString) is
begin
assert false report "fatal: this should never be called" severity failure;
end Vhpi_Log;
end Vhpi_Foreign;
|
-----------------------------------------------------------------------------------------------------------
--
-- INTERNAL RESULTS PACKING (AND ROUNDING) LOGIC
--
-- Created by Claudio Brunelli, 2004
--
-----------------------------------------------------------------------------------------------------------
--Copyright (c) 2004, Tampere University of Technology.
--All rights reserved.
--Redistribution and use in source and binary forms, with or without modification,
--are permitted provided that the following conditions are met:
--* Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--* Neither the name of Tampere University of Technology nor the names of its
-- contributors may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--THIS HARDWARE DESCRIPTION OR SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
--CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND NONINFRINGEMENT AND
--FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
--OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
--EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
--PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
--BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--ARISING IN ANY WAY OUT OF THE USE OF THIS HARDWARE DESCRIPTION OR SOFTWARE, EVEN
--IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
use work.cop_components.all;
entity add_packer is
port( internal_exponent : in std_logic_vector(8 downto 0);
internal_mantissa : in std_logic_vector(47 downto 0);
packed_exponent : out std_logic_vector(7 downto 0);
packed_fractional_part : out std_logic_vector(22 downto 0);
exc_overflow : out std_logic;
exc_underflow : out std_logic;
exc_inexact : out std_logic
);
end add_packer;
-------------------------------------------------------------------------------
architecture rtl of add_packer is
signal internal_e : std_logic_vector(8 downto 0);
signal internal_m : std_logic_vector(47 downto 0);
signal exp : std_logic_vector(8 downto 0);
signal m : std_logic_vector(23 downto 0);
signal rounded_add : std_logic_vector(24 downto 0);
signal x : std_logic_vector(7 downto 0);
signal f : std_logic_vector(22 downto 0);
signal sgl_exc_overflow : std_logic;
signal sgl_exc_underflow : std_logic;
signal result_inexact : std_logic;
signal rounding_inexact : std_logic;
signal sgl_inexact_addiction : std_logic;
begin
internal_e <= internal_exponent;
internal_m <= internal_mantissa;
packed_exponent <= x;
packed_fractional_part <= f;
exc_overflow <= sgl_exc_overflow;
exc_underflow <= sgl_exc_underflow;
exc_inexact <= sgl_inexact_addiction;
-- special result detection and result packing into single precision floating-point format:
SUM_RESULT_GEN: process(internal_e, internal_m, rounded_add, exp, m)
variable c : integer RANGE 0 to 16777215;
variable d : integer RANGE 0 to 8388607;
begin
----------------------------------------------------------------------------
-- special cases:
if ( conv_integer(unsigned(internal_e)) > 127 + 255) then
-- overflow
x <= (others => '1'); -- Infinity
f <= (others => '0');
sgl_exc_overflow <= '1'; sgl_exc_underflow <= '0'; result_inexact <= '1'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (conv_integer(unsigned(internal_e)) = 127 + 255) and ( internal_m(47 downto 23) = "1111111111111111111111111") ) then
-- normalized --> overflow limit zone
x <= (others => '1'); -- Infinity
f <= (others => '0');
sgl_exc_overflow <= '1'; sgl_exc_underflow <= '0'; result_inexact <= '1'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( conv_integer(unsigned(internal_e)) = -127 + 255) then
-- normalized/denormalized limit zone
if ( internal_m(47 downto 24) = "111111111111111111111111" ) then
-- round to min normalized number: 2^(-126)
x <= "00000001";
f <= conv_std_logic_vector(0,23);
result_inexact <= '1';
else
-- trunc to denormalized number (exp = -126)
d := conv_integer(unsigned(internal_m(47 downto 25)));
x <= (others => '0');
if ( internal_m(24 downto 0) = conv_std_logic_vector(0,25) ) then
f <= conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(24)='0') or ((internal_m(25)='0') and (internal_m(24)='1') and (internal_m(23 downto 0)=conv_std_logic_vector(0,24))) ) then
f <= conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (conv_integer(unsigned(internal_e)) = -150 + 255 ) ) then
-- denormalized --> underflow limit zone
x <= (others => '0');
if ( internal_m(46 downto 0)=conv_std_logic_vector(0,47) )then
-- underflow
f <= (others => '0'); -- ZERO
sgl_exc_underflow <= '1'; result_inexact <= '1';
else
-- round to min denormalized
f <= "00000000000000000000001";
sgl_exc_underflow <= '0'; result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( Conv_integer(unsigned(internal_e)) < -150 + 255 ) then
-- underflow
x <= (others => '0');
f <= (others => '0'); -- ZERO
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '1'; result_inexact <= '1'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
----------------------------------------------------------------------------
-- result is always converted into a single precision denormalized number:
elsif ( (Conv_integer(unsigned(internal_e))= -128 + 255) )then
d := Conv_integer( unsigned(internal_m(47 downto 26)) );
x <= (others => '0');
if ( internal_m(25 downto 0) = conv_std_logic_vector(0,26) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(25)='0') or ((internal_m(26)='0') and (internal_m(25)='1') and (internal_m(24 downto 0)=conv_std_logic_vector(0,25))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -129 + 255) )then
d := Conv_integer( unsigned(internal_m(47 downto 27)) );
x <= (others => '0');
if ( internal_m(26 downto 0) = conv_std_logic_vector(0,27) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(26)='0') or ((internal_m(27)='0') and (internal_m(26)='1') and (internal_m(25 downto 0)=conv_std_logic_vector(0,26))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -130 + 255) )then
d := Conv_integer( unsigned(internal_m(47 downto 28)) );
x <= (others => '0');
if ( internal_m(27 downto 0) = conv_std_logic_vector(0,28) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(27)='0') or ((internal_m(28)='0') and (internal_m(27)='1') and (internal_m(26 downto 0)=conv_std_logic_vector(0,27))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -131 + 255) ) then
d := Conv_integer( unsigned(internal_m(47 downto 29)) );
x <= (others => '0');
if ( internal_m(28 downto 0) = conv_std_logic_vector(0,29) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(28)='0') or ((internal_m(29)='0') and (internal_m(28)='1') and (internal_m(27 downto 0)=conv_std_logic_vector(0,28))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -132 + 255) ) then
d := Conv_integer( unsigned(internal_m(47 downto 30)) );
x <= (others => '0');
if ( internal_m(29 downto 0) = conv_std_logic_vector(0,30) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(29)='0') or ((internal_m(30)='0') and (internal_m(29)='1') and (internal_m(28 downto 0)=conv_std_logic_vector(0,29))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -133 + 255) ) then
d := Conv_integer( unsigned(internal_m(47 downto 31)) );
x <= (others => '0');
if ( internal_m(30 downto 0) = conv_std_logic_vector(0,31) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(30)='0') or ((internal_m(31)='0') and (internal_m(30)='1') and (internal_m(29 downto 0)=conv_std_logic_vector(0,30))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -134 + 255) ) then
d := Conv_integer( unsigned(internal_m(47 downto 32)) );
x <= (others => '0');
if ( internal_m(31 downto 0) = conv_std_logic_vector(0,32) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(31)='0') or ((internal_m(32)='0') and (internal_m(31)='1') and (internal_m(30 downto 0)=conv_std_logic_vector(0,31))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -135 + 255) ) then
d := Conv_integer( unsigned(internal_m(47 downto 33)) );
x <= (others => '0');
if ( internal_m(32 downto 0) = conv_std_logic_vector(0,33) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(32)='0') or ((internal_m(33)='0') and (internal_m(32)='1') and (internal_m(31 downto 0)=conv_std_logic_vector(0,32))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -136 + 255) ) then
d := Conv_integer( unsigned(internal_m(47 downto 34)) );
x <= (others => '0');
if ( internal_m(33 downto 0) = conv_std_logic_vector(0,34) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(33)='0') or ((internal_m(34)='0') and (internal_m(33)='1') and (internal_m(32 downto 0)=conv_std_logic_vector(0,33))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -137 + 255) ) then
d := Conv_integer( unsigned(internal_m(47 downto 35)) );
x <= (others => '0');
if ( internal_m(34 downto 0) = conv_std_logic_vector(0,35) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(34)='0') or ((internal_m(35)='0') and (internal_m(34)='1') and (internal_m(33 downto 0)=conv_std_logic_vector(0,34))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -138 + 255) ) then
d := Conv_integer( unsigned(internal_m(47 downto 36)) );
x <= (others => '0');
if ( internal_m(35 downto 0) = conv_std_logic_vector(0,36) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(35)='0') or ((internal_m(36)='0') and (internal_m(35)='1') and (internal_m(34 downto 0)=conv_std_logic_vector(0,35))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -139 + 255) ) then
d := Conv_integer( unsigned(internal_m(47 downto 37)) );
x <= (others => '0');
if ( internal_m(36 downto 0) = conv_std_logic_vector(0,37) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(36)='0') or ((internal_m(37)='0') and (internal_m(36)='1') and (internal_m(35 downto 0)=conv_std_logic_vector(0,36))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -140 + 255) ) then
d := Conv_integer( unsigned(internal_m(47 downto 38)) );
x <= (others => '0');
if ( internal_m(37 downto 0) = conv_std_logic_vector(0,38) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(37)='0') or ((internal_m(38)='0') and (internal_m(37)='1') and (internal_m(36 downto 0)=conv_std_logic_vector(0,37))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -141 + 255) ) then
d := Conv_integer( unsigned(internal_m(47 downto 39)) );
x <= (others => '0');
if ( internal_m(38 downto 0) = conv_std_logic_vector(0,39) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(38)='0') or ((internal_m(39)='0') and (internal_m(38)='1') and (internal_m(37 downto 0)=conv_std_logic_vector(0,38))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -142 + 255) ) then
d := Conv_integer( unsigned(internal_m(47 downto 40)) );
x <= (others => '0');
if ( internal_m(39 downto 0) = conv_std_logic_vector(0,40) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(39)='0') or ((internal_m(40)='0') and (internal_m(39)='1') and (internal_m(38 downto 0)=conv_std_logic_vector(0,39))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -143 + 255) ) then
d := Conv_integer( unsigned(internal_m(47 downto 41)) );
x <= (others => '0');
if ( internal_m(40 downto 0) = conv_std_logic_vector(0,41) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(40)='0') or ((internal_m(41)='0') and (internal_m(40)='1') and (internal_m(39 downto 0)=conv_std_logic_vector(0,40))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -144 + 255) ) then
d := Conv_integer( unsigned(internal_m(47 downto 42)) );
x <= (others => '0');
if ( internal_m(41 downto 0) = conv_std_logic_vector(0,42) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(41)='0') or ((internal_m(42)='0') and (internal_m(41)='1') and (internal_m(40 downto 0)=conv_std_logic_vector(0,41))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -145 + 255) ) then
d := Conv_integer( unsigned(internal_m(47 downto 43)) );
x <= (others => '0');
if ( internal_m(42 downto 0) = conv_std_logic_vector(0,43) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(42)='0') or ((internal_m(43)='0') and (internal_m(42)='1') and (internal_m(41 downto 0)=conv_std_logic_vector(0,42))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -146 + 255) ) then
d := Conv_integer( unsigned(internal_m(47 downto 44)) );
x <= (others => '0');
if ( internal_m(43 downto 0) = conv_std_logic_vector(0,44) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(43)='0') or ((internal_m(44)='0') and (internal_m(43)='1') and (internal_m(42 downto 0)=conv_std_logic_vector(0,43))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -147 + 255) ) then
d := Conv_integer( unsigned(internal_m(47 downto 45)) );
x <= (others => '0');
if ( internal_m(44 downto 0) = conv_std_logic_vector(0,45) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(44)='0') or ((internal_m(45)='0') and (internal_m(44)='1') and (internal_m(43 downto 0)=conv_std_logic_vector(0,44))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -148 + 255) ) then
d := Conv_integer( unsigned(internal_m(47 downto 46)) );
x <= (others => '0');
if ( internal_m(45 downto 0) = conv_std_logic_vector(0,46) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( (internal_m(45)='0') or ((internal_m(46)='0') and (internal_m(45)='1') and (internal_m(44 downto 0)=conv_std_logic_vector(0,45))) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
elsif ( (Conv_integer(unsigned(internal_e))= -149 + 255) ) then
d := Conv_integer(internal_m(47));
x <= (others => '0');
if ( internal_m(46 downto 0) = conv_std_logic_vector(0,47) ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '0';
----------------------------------------------------------
-- ROUND TO NEAREST
elsif ( internal_m(46)='0' ) then
f <= Conv_std_logic_vector(d,23);
result_inexact <= '1';
else
f <= Conv_std_logic_vector(d+1,23);
result_inexact <= '1';
end if;
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; rounding_inexact <= '0';
rounded_add <= (others => '0'); exp <= (others => '0'); m <= (others => '0');
----------------------------------------------------------------------------
-- result is always converted into a single precision normalized numbers:
-- rounding
elsif ( (conv_integer(unsigned(internal_e)) < 128 + 255) and (conv_integer(unsigned(internal_e)) > -127 + 255) ) then
c := Conv_integer( unsigned(internal_m(47 downto 24)) );
if internal_m(23 downto 0) = Conv_std_logic_vector(0,24) then
-- only one exact case!
rounded_add <= Conv_std_logic_vector(c,25);
rounding_inexact <= '0';
elsif ( (internal_m(23) = '0') or ( internal_m(24) = '0' and internal_m(23) = '1' and internal_m(22 downto 0) = Conv_std_logic_vector(0,23) ) ) then
rounded_add <= Conv_std_logic_vector(c,25);
rounding_inexact <= '1';
else
rounded_add <= Conv_std_logic_vector(c+1,25);
rounding_inexact <= '1';
end if;
----------------------------------------------------------
-- If the rounding makes the mantissa to overflow, then result has to be re-adjusted
if rounded_add(24) = '1' then
-- overflow => SHR(rounded_add), exp <- (exp + 1)
m <= rounded_add(24 downto 1); -- note: LSB is lost, but there's no information loss in doing this, since the lost bit is zero
exp <= ( unsigned(internal_e) + 1 );
else
-- no overflow
m <= rounded_add(23 downto 0);
exp <= internal_e;
end if;
----------------------------------------------------------
-- normalized result packing
x <= conv_std_logic_vector( unsigned(exp) -255 + 127, 8 );
f <= m(22 downto 0);
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; result_inexact <= '0';
----------------------------------------------------------
else
-- invalid operand; NaN is generated
rounded_add <= (others => '0');
exp <= (others => '0');
m <= (others => '0');
x <= "11111111";
f <= "00000000000000000000001";
sgl_exc_overflow <= '0'; sgl_exc_underflow <= '0'; result_inexact <= '0'; rounding_inexact <= '0';
end if;
end process;
-- All "inexact result warning" internal signals are put in logical OR:
sgl_inexact_addiction <= ( result_inexact or rounding_inexact);
end rtl;
|
--!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library techmap;
use techmap.gencomp.all;
package config_target is
-- Technology and synthesis options
constant CFG_FABTECH : integer := inferred;
constant CFG_MEMTECH : integer := inferred;
constant CFG_PADTECH : integer := inferred;
constant CFG_JTAGTECH : integer := inferred;
constant CFG_ASYNC_RESET : boolean := false;
constant CFG_TOPDIR : string := "../../../";
--! @brief Number of processors in a system
--! @details This value may be in a range 1 to CFG_TOTAL_CPU_MAX-1
constant CFG_CPU_NUM : integer := 1;
--! @brief HEX-image for the initialization of the Boot ROM.
--! @details This file is used by \e inferred ROM implementation.
constant CFG_SIM_BOOTROM_HEX : string :=
CFG_TOPDIR & "examples/boot/linuxbuild/bin/bootimage.hex";
-- CFG_TOPDIR & "examples/bootrom_tests/linuxbuild/bin/bootrom_tests.hex";
--! @brief HEX-image for the initialization of the FwImage ROM.
--! @details This file is used by \e inferred ROM implementation.
constant CFG_SIM_FWIMAGE_HEX : string :=
-- CFG_TOPDIR & "examples/zephyr/gcc711/zephyr.hex";
CFG_TOPDIR & "examples/gnss_fw/makefiles/bin/gnssfw.hex";
--! @brief Hardware SoC Identificator.
--!
--! @details Read Only unique platform identificator that could be
--! read by firmware from the Plug'n'Play support module.
constant CFG_HW_ID : std_logic_vector(31 downto 0) := X"20190524";
--! @brief Enabling Ethernet MAC interface.
--! @details By default MAC module enables support of the debug feature EDCL.
constant CFG_ETHERNET_ENABLE : boolean := true;
--! @brief Enable/Disable Debug Unit
constant CFG_DSU_ENABLE : boolean := true;
--! External Flash IC connected via SPI
constant CFG_EXT_FLASH_ENA : boolean := true;
--! GNSS sub-system
constant CFG_GNSS_SS_ENA : boolean := true;
--! OTP 8 KB memory bank
constant CFG_OTP8KB_ENA : boolean := true;
--! Coherent bridge with L2-cache
constant CFG_L2CACHE_ENA : boolean := false;
end;
|
-----------------------------------------------------------------------------------
-- File : Mips (Data) Memory
-- Author : Wolfgang Brandt / Fabian May
-- Company : Technical University Hamburg Harburg Institute of Computer Technology
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
entity BRAM is
generic(
MEM_ADDR_WIDTH : integer := 8;
MEM_DATA_WIDTH : integer := 32;
EDGE_TYPE : boolean := true; -- true = rising edge, false = falling edge
MEM_NAME : string := "ram.mem"
);
port (
Clock : in std_logic;
WriteEnable : in std_logic;
Address : in std_logic_vector (MEM_ADDR_WIDTH-1 downto 0);
WriteData : in std_logic_vector (MEM_DATA_WIDTH-1 downto 0);
ReadData : out std_logic_vector (MEM_DATA_WIDTH-1 downto 0)
);
end BRAM;
architecture behavior of BRAM is
type MemType is array (0 to 2**MEM_ADDR_WIDTH-1) of bit_vector (MEM_DATA_WIDTH-1 downto 0);
impure function InitRamFromFile (RamFileName : in string) return MemType is
file RamFile : text is in RamFileName;
variable RamFileLine : line;
variable RAM : MemType;
begin
for I in MemType'range loop
readline (RamFile, RamFileLine);
read (RamFileLine, RAM(I));
end loop;
return RAM;
end function;
signal Ram : MemType := InitRamFromFile(MEM_NAME);
begin
process (Clock)
begin
if EDGE_TYPE then
if rising_edge(Clock) then --todo
if (WriteEnable = '1') then
Ram(conv_integer(Address)) <= to_bitvector(WriteData);
end if;
ReadData <= to_stdlogicvector(Ram(conv_integer(Address)));
end if;
else
if falling_edge(Clock) then --todo
if (WriteEnable = '1') then
Ram(conv_integer(Address)) <= to_bitvector(WriteData);
end if;
ReadData <= to_stdlogicvector(Ram(conv_integer(Address)));
end if;
end if;
end process;
end behavior;
|
library IEEE;
use IEEE.std_logic_1164.all;
use Std.Textio.all;
use IEEE.std_logic_textio.all;
entity test_ram is
end test_ram;
architecture test_ram of test_ram is
component Ram
generic (width : INTEGER := 16;
ram_select : INTEGER := 4);
port (input1 : in std_logic_Vector((width - 1) downto 0);
input2 : in std_logic_Vector((ram_select - 1) downto 0);
Wr, Rd, CLOCK : in std_logic;
output : out std_logic_Vector(width - 1 downto 0)) ;
end component;
for all : Ram use entity WORK.Ram(behavior);
signal input1 : std_logic_Vector(3 downto 0);
signal input2 : std_logic_Vector(3 downto 0);
signal Wr, Rd, Clk : std_logic;
signal output : std_logic_Vector(3 downto 0);
begin
UUT : Ram
generic map(4,4)
port map(input1, input2, Wr, rd, Clk, output);
test_process : process
begin
Clk <= '1';
wr <= '1';
rd <= '0';
input1 <= "1111";
input2 <= "0000";
wait for 100 ns;
Clk <= '0';
wait for 100 ns;
Clk <= '1';
wr <= '1';
rd <= '0';
input1 <= "1110";
input2 <= "0001";
wait for 100 ns;
Clk <= '0';
wait for 100 ns;
Clk <= '1';
wr <= '1';
rd <= '0';
input1 <= "1101";
input2 <= "0010";
wait for 100 ns;
Clk <= '0';
wait for 100 ns;
Clk <= '1';
wr <= '0';
rd <= '1';
input2 <= "0000";
wait for 100 ns;
Clk <= '0';
wait for 100 ns;
Clk <= '1';
wr <= '0';
rd <= '1';
input2 <= "0001";
wait for 100 ns;
Clk <= '0';
wait for 100 ns;
Clk <= '1';
wr <= '0';
rd <= '1';
input2 <= "0010";
wait for 100 ns;
Clk <= '0';
wait for 100 ns;
wait;
end process;
monitor_process : process
variable outline : line;
file outfile : text is out "ram.out";
begin
write(outline, input1);
write(outline, string'(" : "));
write(outline, input2);
write(outline, string'(" : "));
write(outline, rd);
write(outline, string'(" : "));
write(outline, wr);
write(outline, string'(" : "));
write(outline, output);
writeline(outfile, outline);
wait until not rd'quiet;
end process;
end test_ram;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (7);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 4;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#010a#;
constant CFG_ETH_ENM : integer := 16#020060#;
constant CFG_ETH_ENL : integer := 16#000015#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 0;
constant CFG_DDRSP_INIT : integer := 0;
constant CFG_DDRSP_FREQ : integer := 100;
constant CFG_DDRSP_COL : integer := 9;
constant CFG_DDRSP_SIZE : integer := 8;
constant CFG_DDRSP_RSKEW : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#FE0#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
COMPONENT sram_control
GENERIC(data_width : positive);
PORT(
CLK, RESET : IN std_logic;
C_WRITE, C_READ : IN std_logic;
DATA_IN : IN std_logic_vector(data_width-1 DOWNTO 0);
TO_DATA_IN : OUT std_logic_vector(data_width-1 DOWNTO 0);
CS, WE : OUT std_logic;
SELECT_ALL : OUT std_logic
);
END COMPONENT;
FOR ALL : sram_control USE ENTITY WORK.sram_control(primitive);
|
COMPONENT sram_control
GENERIC(data_width : positive);
PORT(
CLK, RESET : IN std_logic;
C_WRITE, C_READ : IN std_logic;
DATA_IN : IN std_logic_vector(data_width-1 DOWNTO 0);
TO_DATA_IN : OUT std_logic_vector(data_width-1 DOWNTO 0);
CS, WE : OUT std_logic;
SELECT_ALL : OUT std_logic
);
END COMPONENT;
FOR ALL : sram_control USE ENTITY WORK.sram_control(primitive);
|
COMPONENT sram_control
GENERIC(data_width : positive);
PORT(
CLK, RESET : IN std_logic;
C_WRITE, C_READ : IN std_logic;
DATA_IN : IN std_logic_vector(data_width-1 DOWNTO 0);
TO_DATA_IN : OUT std_logic_vector(data_width-1 DOWNTO 0);
CS, WE : OUT std_logic;
SELECT_ALL : OUT std_logic
);
END COMPONENT;
FOR ALL : sram_control USE ENTITY WORK.sram_control(primitive);
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 128,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : pcie_command_rec_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
-- Author: Elahe Jalalpour ([email protected])
--
-- Create Date: 27-08-2015
-- Module Name: hea.vhd
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity hea is
port(a, b : in std_logic_vector(3 downto 0);
s : out std_logic_vector(7 downto 0));
end hea;
architecture rtl of hea is
component ha
port(a, b : in std_logic;
s, c : out std_logic);
end component;
begin
L0: ha port map(b(3),a(0),s(0),s(1));
L1: ha port map(b(2),a(1),s(2),s(3));
L2: ha port map(b(1),a(2),s(4),s(5));
L3: ha port map(b(0),a(3),s(6),s(7));
end rtl;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr.kth.se:user:axi_spi_master:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_axi_spi_master_1_0 IS
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_axi_spi_master_1_0;
ARCHITECTURE DemoInterconnect_axi_spi_master_1_0_arch OF DemoInterconnect_axi_spi_master_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_axi_spi_master_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_spi_master_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
SPI_DATA_WIDTH : INTEGER;
SPI_CLK_DIV : INTEGER
);
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT axi_spi_master_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST, xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_sclk: SIGNAL IS "XIL_INTERFACENAME m_spi_sclk, ASSOCIATED_CLKEN m_spi_ss, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN DemoInterconnect_axi_spi_master_1_0_m_spi_sclk";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_sclk: SIGNAL IS "xilinx.com:signal:clock:1.0 m_spi_sclk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_ss: SIGNAL IS "XIL_INTERFACENAME m_spi_ss, FREQ_HZ 100000000, PHASE 0, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_ss: SIGNAL IS "xilinx.com:signal:clockenable:1.0 m_spi_ss CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_miso: SIGNAL IS "XIL_INTERFACENAME m_spi_miso, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_miso: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_miso DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_mosi: SIGNAL IS "XIL_INTERFACENAME m_spi_mosi, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_mosi: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_mosi DATA";
BEGIN
U0 : axi_spi_master_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
SPI_DATA_WIDTH => 8,
SPI_CLK_DIV => 6
)
PORT MAP (
m_spi_mosi => m_spi_mosi,
m_spi_miso => m_spi_miso,
m_spi_ss => m_spi_ss,
m_spi_sclk => m_spi_sclk,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END DemoInterconnect_axi_spi_master_1_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr.kth.se:user:axi_spi_master:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_axi_spi_master_1_0 IS
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_axi_spi_master_1_0;
ARCHITECTURE DemoInterconnect_axi_spi_master_1_0_arch OF DemoInterconnect_axi_spi_master_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_axi_spi_master_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_spi_master_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
SPI_DATA_WIDTH : INTEGER;
SPI_CLK_DIV : INTEGER
);
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT axi_spi_master_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST, xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_sclk: SIGNAL IS "XIL_INTERFACENAME m_spi_sclk, ASSOCIATED_CLKEN m_spi_ss, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN DemoInterconnect_axi_spi_master_1_0_m_spi_sclk";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_sclk: SIGNAL IS "xilinx.com:signal:clock:1.0 m_spi_sclk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_ss: SIGNAL IS "XIL_INTERFACENAME m_spi_ss, FREQ_HZ 100000000, PHASE 0, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_ss: SIGNAL IS "xilinx.com:signal:clockenable:1.0 m_spi_ss CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_miso: SIGNAL IS "XIL_INTERFACENAME m_spi_miso, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_miso: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_miso DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_mosi: SIGNAL IS "XIL_INTERFACENAME m_spi_mosi, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_mosi: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_mosi DATA";
BEGIN
U0 : axi_spi_master_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
SPI_DATA_WIDTH => 8,
SPI_CLK_DIV => 6
)
PORT MAP (
m_spi_mosi => m_spi_mosi,
m_spi_miso => m_spi_miso,
m_spi_ss => m_spi_ss,
m_spi_sclk => m_spi_sclk,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END DemoInterconnect_axi_spi_master_1_0_arch;
|
-------------------------------------------------------------------------------
--
-- $Id: clock_ctrl-c.vhd,v 1.2 2005-06-11 10:08:43 arniml Exp $
--
-- The clock control unit.
--
-------------------------------------------------------------------------------
configuration t48_clock_ctrl_rtl_c0 of t48_clock_ctrl is
for rtl
end for;
end t48_clock_ctrl_rtl_c0;
|
package FIFO_PKG is
procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES (constant a : in integer := 0; signal b : in std_logic := 'X'; variable c : in std_logic := 'X');
procedure AVERAGE_SAMPLES (
constant a : in integer := 0;
signal b : in std_logic := 'X';
variable c : in std_logic := 'X';
some_sig : inout t_some_type := '0');
-- Violations below this line
procedure AVERAGE_SAMPLES (
constant a : in integer := 0;
signal b : in std_logic := 'X';
variable ccc : in std_logic := 'X';
some_sig : inout t_some_type := '0');
end package FIFO_PKG;
package body FIFO_PKG is
procedure AVERAGE_SAMPLES (
constant a : in integer := 0;
signal b : in std_logic := 'X';
variable c : in std_logic := 'X') is
begin
end procedure AVERAGE_SAMPLES;
-- Violations below this line
procedure AVERAGE_SAMPLES (
constant a : in integer := 0;
signal b : in std_logic := 'X';
variable ccc : in std_logic := 'X') is
begin
end procedure AVERAGE_SAMPLES;
end package body FIFO_PKG;
architecture RTL of ENT is
procedure AVERAGE_SAMPLES (
constant a : in integer := 0;
signal b : in std_logic := 'X';
variable c : in std_logic := 'X') is
begin
end procedure AVERAGE_SAMPLES;
-- Violations below this line
procedure AVERAGE_SAMPLES (
constant a : in integer := 0;
signal b : in std_logic := 'X';
variable ccc : in std_logic := 'X') is
begin
end procedure AVERAGE_SAMPLES;
begin
TEST_PROCESS : process
procedure AVERAGE_SAMPLES (
constant a : in integer := 0;
signal b : in std_logic := 'X';
variable c : in std_logic := 'X') is
begin
end procedure AVERAGE_SAMPLES;
-- Violations below this line
procedure AVERAGE_SAMPLES (
constant a : in integer := 0;
signal b : in std_logic := 'X';
variable ccc : in std_logic := 'X') is
begin
end procedure AVERAGE_SAMPLES;
begin
end process TEST_PROCESS;
end architecture RTL;
|
-- Test generic clause
package PACK1 is
generic (
-- Test function
pure function funct1 parameter (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is <>;
pure function funct1 parameter (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is func1;
impure function funct1 parameter (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is <>;
impure function funct1 parameter (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is func1;
-- Remove Parameter
pure function funct1 (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is <>;
pure function funct1 (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is func1;
impure function funct1 (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is <>;
impure function funct1 (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is func1;
-- Remove formal_parameter_list
pure function funct1 return boolean is <>;
pure function funct1 return boolean is func1;
impure function funct1 return boolean is <>;
impure function funct1 return boolean is func1;
-- Remove interface_subprogram_default
pure function funct1 return boolean;
pure function funct1 return boolean;
impure function funct1 return boolean;
impure function funct1 return boolean;
-- Remove pure/impure
function funct1 return boolean;
function funct1 return boolean;
function funct1 return boolean;
function funct1 return boolean
);
end package PACK1;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2126.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02126ent IS
END c07s02b04x00p20n01i02126ent;
ARCHITECTURE c07s02b04x00p20n01i02126arch OF c07s02b04x00p20n01i02126ent IS
TYPE integer_v is array (integer range <>) of integer;
SUBTYPE integer_4 is integer_v (1 to 4);
SUBTYPE integer_8 is integer_v (1 to 8);
SUBTYPE integer_8_dwn is integer_v (8 downto 1);
BEGIN
TESTING: PROCESS
variable r_operand : integer_4 := ( 5,6,7,8 );
variable l_operand1: integer := 1;
variable l_operand2: integer := 2;
variable l_operand3: integer := 3;
variable l_operand4: integer := 4;
variable result : integer_8;
variable result_dwn: integer_8_dwn;
BEGIN
result_dwn := l_operand1 &
l_operand2 &
l_operand3 &
l_operand4 &
l_operand2 &
l_operand3 &
l_operand2 &
l_operand3;
assert (result_dwn = (1,2,3,4,2,3,2,3))
report "integer implicit array concatenation failed"
severity FAILURE;
assert NOT(result_dwn = (1,2,3,4,2,3,2,3))
report "***PASSED TEST: c07s02b04x00p20n01i02126"
severity NOTE;
assert (result_dwn = (1,2,3,4,2,3,2,3))
report "***FAILED TEST: c07s02b04x00p20n01i02126 - The left bound of this implicit array is the left bound of the index subtype of the array and its direction is ascending if the index subtype is ascending."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02126arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2126.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02126ent IS
END c07s02b04x00p20n01i02126ent;
ARCHITECTURE c07s02b04x00p20n01i02126arch OF c07s02b04x00p20n01i02126ent IS
TYPE integer_v is array (integer range <>) of integer;
SUBTYPE integer_4 is integer_v (1 to 4);
SUBTYPE integer_8 is integer_v (1 to 8);
SUBTYPE integer_8_dwn is integer_v (8 downto 1);
BEGIN
TESTING: PROCESS
variable r_operand : integer_4 := ( 5,6,7,8 );
variable l_operand1: integer := 1;
variable l_operand2: integer := 2;
variable l_operand3: integer := 3;
variable l_operand4: integer := 4;
variable result : integer_8;
variable result_dwn: integer_8_dwn;
BEGIN
result_dwn := l_operand1 &
l_operand2 &
l_operand3 &
l_operand4 &
l_operand2 &
l_operand3 &
l_operand2 &
l_operand3;
assert (result_dwn = (1,2,3,4,2,3,2,3))
report "integer implicit array concatenation failed"
severity FAILURE;
assert NOT(result_dwn = (1,2,3,4,2,3,2,3))
report "***PASSED TEST: c07s02b04x00p20n01i02126"
severity NOTE;
assert (result_dwn = (1,2,3,4,2,3,2,3))
report "***FAILED TEST: c07s02b04x00p20n01i02126 - The left bound of this implicit array is the left bound of the index subtype of the array and its direction is ascending if the index subtype is ascending."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02126arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2126.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02126ent IS
END c07s02b04x00p20n01i02126ent;
ARCHITECTURE c07s02b04x00p20n01i02126arch OF c07s02b04x00p20n01i02126ent IS
TYPE integer_v is array (integer range <>) of integer;
SUBTYPE integer_4 is integer_v (1 to 4);
SUBTYPE integer_8 is integer_v (1 to 8);
SUBTYPE integer_8_dwn is integer_v (8 downto 1);
BEGIN
TESTING: PROCESS
variable r_operand : integer_4 := ( 5,6,7,8 );
variable l_operand1: integer := 1;
variable l_operand2: integer := 2;
variable l_operand3: integer := 3;
variable l_operand4: integer := 4;
variable result : integer_8;
variable result_dwn: integer_8_dwn;
BEGIN
result_dwn := l_operand1 &
l_operand2 &
l_operand3 &
l_operand4 &
l_operand2 &
l_operand3 &
l_operand2 &
l_operand3;
assert (result_dwn = (1,2,3,4,2,3,2,3))
report "integer implicit array concatenation failed"
severity FAILURE;
assert NOT(result_dwn = (1,2,3,4,2,3,2,3))
report "***PASSED TEST: c07s02b04x00p20n01i02126"
severity NOTE;
assert (result_dwn = (1,2,3,4,2,3,2,3))
report "***FAILED TEST: c07s02b04x00p20n01i02126 - The left bound of this implicit array is the left bound of the index subtype of the array and its direction is ascending if the index subtype is ascending."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02126arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc204.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p07n02i00204ent IS
END c03s01b00x00p07n02i00204ent;
ARCHITECTURE c03s01b00x00p07n02i00204arch OF c03s01b00x00p07n02i00204ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for I in 5 downto 50 loop
k := k + 1;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c03s01b00x00p07n02i00204"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c03s01b00x00p07n02i00204 - In the case of L downto R, if L < R then the range is a null range."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p07n02i00204arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc204.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p07n02i00204ent IS
END c03s01b00x00p07n02i00204ent;
ARCHITECTURE c03s01b00x00p07n02i00204arch OF c03s01b00x00p07n02i00204ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for I in 5 downto 50 loop
k := k + 1;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c03s01b00x00p07n02i00204"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c03s01b00x00p07n02i00204 - In the case of L downto R, if L < R then the range is a null range."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p07n02i00204arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc204.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p07n02i00204ent IS
END c03s01b00x00p07n02i00204ent;
ARCHITECTURE c03s01b00x00p07n02i00204arch OF c03s01b00x00p07n02i00204ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for I in 5 downto 50 loop
k := k + 1;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c03s01b00x00p07n02i00204"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c03s01b00x00p07n02i00204 - In the case of L downto R, if L < R then the range is a null range."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p07n02i00204arch;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_random-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library math;
package body random is
use math.math_real;
constant sample_seeds : seed_array(0 to 50)
:= ( 0 => (1, 1),
1 => (1919456777, 2006618587),
2 => (928906921, 476680813),
3 => (715788085, 762347824),
4 => (366002668, 1804336679),
5 => (1866585254, 247488051),
6 => (1342990589, 1539624735),
7 => (677313287, 1675609237),
8 => (644816519, 2026475269),
9 => (1654953611, 564421524),
10 => (1020104619, 712556314),
11 => (609798541, 1592526288),
12 => (1106087470, 1468242308),
13 => (1378844312, 646793513),
14 => (966261604, 481733031),
15 => (1407842093, 1316990206),
16 => (1705378215, 1930221363),
17 => (206887499, 1810320799),
18 => (1681633030, 2114795480),
19 => (71194926, 1642522201),
20 => (663275331, 1947299255),
21 => (224432387, 944962866),
22 => (1156075861, 1866435087),
23 => (1670357576, 1247152991),
24 => (846934138, 1673364736),
25 => (1972636955, 1404522710),
26 => (533484185, 592078395),
27 => (1989468008, 1409246301),
28 => (697086615, 1975145057),
29 => (111393259, 1673620688),
30 => (1352201163, 872947497),
31 => (1342844190, 877696585),
32 => (938770066, 1222894811),
33 => (1144599578, 661919919),
34 => (1750521407, 269946538),
35 => (457892500, 1256953520),
36 => (1678589945, 356027520),
37 => (1484458924, 2103068828),
38 => (1296978761, 2124096638),
39 => (1702642440, 1161000593),
40 => (1244690090, 2016422304),
41 => (1858682943, 1053836731),
42 => (1496964676, 701079294),
43 => (432696952, 602526767),
44 => (2097684438, 1264032473),
45 => (2115456834, 298917738),
46 => (432301768, 232430346),
47 => (1929812456, 758157910),
48 => (1655564027, 1062345086),
49 => (1116121051, 538424126),
50 => (844396720, 821616997) );
procedure init_fixed ( random_info : out random_info_record;
mean : in real ) is
begin
random_info.distribution := fixed;
random_info.mean := mean;
end procedure init_fixed;
procedure init_uniform ( random_info : out random_info_record;
lower_bound, upper_bound : in real;
seed : in seed_type ) is
begin
assert lower_bound <= upper_bound
report "init_uniform: lower_bound > upper_bound" severity failure;
random_info.distribution := uniform;
random_info.lower_bound := lower_bound;
random_info.upper_bound := upper_bound;
random_info.seed := seed;
end procedure init_uniform;
procedure init_exponential ( random_info : out random_info_record;
mean : in real;
seed : in seed_type ) is
begin
assert mean > 0.0
report "init_exponential: mean not positive" severity failure;
random_info.distribution := exponential;
random_info.mean := mean;
random_info.seed := seed;
end procedure init_exponential;
procedure generate_uniform ( random_info : inout random_info_record;
random_number : out real ) is
variable tmp : real;
begin
math_real.uniform(random_info.seed.seed1, random_info.seed.seed2, tmp);
random_number := random_info.lower_bound
+ tmp * (random_info.upper_bound - random_info.lower_bound);
end procedure generate_uniform;
procedure generate_exponential ( random_info : inout random_info_record;
random_number : out real ) is
variable tmp : real;
begin
loop
math_real.uniform(random_info.seed.seed1, random_info.seed.seed2, tmp);
exit when tmp /= 0.0;
end loop;
random_number := - random_info.mean * math_real.log(tmp);
end procedure generate_exponential;
procedure generate_random ( random_info : inout random_info_record;
random_number : out real ) is
begin
case random_info.distribution is
when fixed =>
random_number := random_info.mean;
when uniform =>
generate_uniform(random_info, random_number);
when exponential =>
generate_exponential(random_info, random_number);
end case;
end procedure generate_random;
end package body random;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_random-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library math;
package body random is
use math.math_real;
constant sample_seeds : seed_array(0 to 50)
:= ( 0 => (1, 1),
1 => (1919456777, 2006618587),
2 => (928906921, 476680813),
3 => (715788085, 762347824),
4 => (366002668, 1804336679),
5 => (1866585254, 247488051),
6 => (1342990589, 1539624735),
7 => (677313287, 1675609237),
8 => (644816519, 2026475269),
9 => (1654953611, 564421524),
10 => (1020104619, 712556314),
11 => (609798541, 1592526288),
12 => (1106087470, 1468242308),
13 => (1378844312, 646793513),
14 => (966261604, 481733031),
15 => (1407842093, 1316990206),
16 => (1705378215, 1930221363),
17 => (206887499, 1810320799),
18 => (1681633030, 2114795480),
19 => (71194926, 1642522201),
20 => (663275331, 1947299255),
21 => (224432387, 944962866),
22 => (1156075861, 1866435087),
23 => (1670357576, 1247152991),
24 => (846934138, 1673364736),
25 => (1972636955, 1404522710),
26 => (533484185, 592078395),
27 => (1989468008, 1409246301),
28 => (697086615, 1975145057),
29 => (111393259, 1673620688),
30 => (1352201163, 872947497),
31 => (1342844190, 877696585),
32 => (938770066, 1222894811),
33 => (1144599578, 661919919),
34 => (1750521407, 269946538),
35 => (457892500, 1256953520),
36 => (1678589945, 356027520),
37 => (1484458924, 2103068828),
38 => (1296978761, 2124096638),
39 => (1702642440, 1161000593),
40 => (1244690090, 2016422304),
41 => (1858682943, 1053836731),
42 => (1496964676, 701079294),
43 => (432696952, 602526767),
44 => (2097684438, 1264032473),
45 => (2115456834, 298917738),
46 => (432301768, 232430346),
47 => (1929812456, 758157910),
48 => (1655564027, 1062345086),
49 => (1116121051, 538424126),
50 => (844396720, 821616997) );
procedure init_fixed ( random_info : out random_info_record;
mean : in real ) is
begin
random_info.distribution := fixed;
random_info.mean := mean;
end procedure init_fixed;
procedure init_uniform ( random_info : out random_info_record;
lower_bound, upper_bound : in real;
seed : in seed_type ) is
begin
assert lower_bound <= upper_bound
report "init_uniform: lower_bound > upper_bound" severity failure;
random_info.distribution := uniform;
random_info.lower_bound := lower_bound;
random_info.upper_bound := upper_bound;
random_info.seed := seed;
end procedure init_uniform;
procedure init_exponential ( random_info : out random_info_record;
mean : in real;
seed : in seed_type ) is
begin
assert mean > 0.0
report "init_exponential: mean not positive" severity failure;
random_info.distribution := exponential;
random_info.mean := mean;
random_info.seed := seed;
end procedure init_exponential;
procedure generate_uniform ( random_info : inout random_info_record;
random_number : out real ) is
variable tmp : real;
begin
math_real.uniform(random_info.seed.seed1, random_info.seed.seed2, tmp);
random_number := random_info.lower_bound
+ tmp * (random_info.upper_bound - random_info.lower_bound);
end procedure generate_uniform;
procedure generate_exponential ( random_info : inout random_info_record;
random_number : out real ) is
variable tmp : real;
begin
loop
math_real.uniform(random_info.seed.seed1, random_info.seed.seed2, tmp);
exit when tmp /= 0.0;
end loop;
random_number := - random_info.mean * math_real.log(tmp);
end procedure generate_exponential;
procedure generate_random ( random_info : inout random_info_record;
random_number : out real ) is
begin
case random_info.distribution is
when fixed =>
random_number := random_info.mean;
when uniform =>
generate_uniform(random_info, random_number);
when exponential =>
generate_exponential(random_info, random_number);
end case;
end procedure generate_random;
end package body random;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_random-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library math;
package body random is
use math.math_real;
constant sample_seeds : seed_array(0 to 50)
:= ( 0 => (1, 1),
1 => (1919456777, 2006618587),
2 => (928906921, 476680813),
3 => (715788085, 762347824),
4 => (366002668, 1804336679),
5 => (1866585254, 247488051),
6 => (1342990589, 1539624735),
7 => (677313287, 1675609237),
8 => (644816519, 2026475269),
9 => (1654953611, 564421524),
10 => (1020104619, 712556314),
11 => (609798541, 1592526288),
12 => (1106087470, 1468242308),
13 => (1378844312, 646793513),
14 => (966261604, 481733031),
15 => (1407842093, 1316990206),
16 => (1705378215, 1930221363),
17 => (206887499, 1810320799),
18 => (1681633030, 2114795480),
19 => (71194926, 1642522201),
20 => (663275331, 1947299255),
21 => (224432387, 944962866),
22 => (1156075861, 1866435087),
23 => (1670357576, 1247152991),
24 => (846934138, 1673364736),
25 => (1972636955, 1404522710),
26 => (533484185, 592078395),
27 => (1989468008, 1409246301),
28 => (697086615, 1975145057),
29 => (111393259, 1673620688),
30 => (1352201163, 872947497),
31 => (1342844190, 877696585),
32 => (938770066, 1222894811),
33 => (1144599578, 661919919),
34 => (1750521407, 269946538),
35 => (457892500, 1256953520),
36 => (1678589945, 356027520),
37 => (1484458924, 2103068828),
38 => (1296978761, 2124096638),
39 => (1702642440, 1161000593),
40 => (1244690090, 2016422304),
41 => (1858682943, 1053836731),
42 => (1496964676, 701079294),
43 => (432696952, 602526767),
44 => (2097684438, 1264032473),
45 => (2115456834, 298917738),
46 => (432301768, 232430346),
47 => (1929812456, 758157910),
48 => (1655564027, 1062345086),
49 => (1116121051, 538424126),
50 => (844396720, 821616997) );
procedure init_fixed ( random_info : out random_info_record;
mean : in real ) is
begin
random_info.distribution := fixed;
random_info.mean := mean;
end procedure init_fixed;
procedure init_uniform ( random_info : out random_info_record;
lower_bound, upper_bound : in real;
seed : in seed_type ) is
begin
assert lower_bound <= upper_bound
report "init_uniform: lower_bound > upper_bound" severity failure;
random_info.distribution := uniform;
random_info.lower_bound := lower_bound;
random_info.upper_bound := upper_bound;
random_info.seed := seed;
end procedure init_uniform;
procedure init_exponential ( random_info : out random_info_record;
mean : in real;
seed : in seed_type ) is
begin
assert mean > 0.0
report "init_exponential: mean not positive" severity failure;
random_info.distribution := exponential;
random_info.mean := mean;
random_info.seed := seed;
end procedure init_exponential;
procedure generate_uniform ( random_info : inout random_info_record;
random_number : out real ) is
variable tmp : real;
begin
math_real.uniform(random_info.seed.seed1, random_info.seed.seed2, tmp);
random_number := random_info.lower_bound
+ tmp * (random_info.upper_bound - random_info.lower_bound);
end procedure generate_uniform;
procedure generate_exponential ( random_info : inout random_info_record;
random_number : out real ) is
variable tmp : real;
begin
loop
math_real.uniform(random_info.seed.seed1, random_info.seed.seed2, tmp);
exit when tmp /= 0.0;
end loop;
random_number := - random_info.mean * math_real.log(tmp);
end procedure generate_exponential;
procedure generate_random ( random_info : inout random_info_record;
random_number : out real ) is
begin
case random_info.distribution is
when fixed =>
random_number := random_info.mean;
when uniform =>
generate_uniform(random_info, random_number);
when exponential =>
generate_exponential(random_info, random_number);
end case;
end procedure generate_random;
end package body random;
|
library ieee;
use ieee.std_logic_1164.all;
package PROTOCOL is
-- Design Subtypes
subtype ulogic_QuadWord is std_ulogic_vector (63 downto 0);
subtype ulogic_DoubleWord is std_ulogic_vector (31 downto 0);
subtype ulogic_Word is std_ulogic_vector (15 downto 0);
subtype ulogic_Byte is std_ulogic_vector (7 downto 0);
subtype ulogic_Nibble is std_ulogic_vector (3 downto 0);
subtype ulogic_Bit is std_ulogic;
subtype BV_QuadWord is bit_vector (63 downto 0);
subtype BV_DoubleWord is bit_vector (31 downto 0);
subtype BV_Word is bit_vector (15 downto 0);
subtype BV_Byte is bit_vector (7 downto 0);
subtype BV_Nibble is bit_vector (3 downto 0);
subtype BV_Bit is bit;
subtype BV_Config_Ad is bit_vector (5 downto 0);
subtype BV_Mem_Ad is bit_vector (11 downto 0);
-- Design Constants
constant c_CBE_Interrupt_Ack : std_ulogic_vector (3 downto 0) := "0000";
constant c_CBE_Special_Cycle : std_ulogic_vector (3 downto 0) := "0001";
constant c_CBE_IO_Read : std_ulogic_vector (3 downto 0) := "0010";
constant c_CBE_IO_Write : std_ulogic_vector (3 downto 0) := "0011";
constant c_CBE_Mem_Read : std_ulogic_vector (3 downto 0) := "0110";
constant c_CBE_Mem_Write : std_ulogic_vector (3 downto 0) := "0111";
constant c_CBE_Config_Read : std_ulogic_vector (3 downto 0) := "1010";
constant c_CBE_Config_Write : std_ulogic_vector (3 downto 0) := "1011";
constant c_CBE_Mem_Read_Mul : std_ulogic_vector (3 downto 0) := "1100";
constant c_CBE_Dual_Add_Cycle : std_ulogic_vector (3 downto 0) := "1101";
constant c_CBE_Mem_Read_line : std_ulogic_vector (3 downto 0) := "1110";
constant c_CBE_Mem_Write_Inv : std_ulogic_vector (3 downto 0) := "1111";
constant c_BV_CBE_Interrupt_Ack : bit_vector (3 downto 0) := "0000";
constant c_BV_CBE_Special_Cycle : bit_vector (3 downto 0) := "0001";
constant c_BV_CBE_IO_Read : bit_vector (3 downto 0) := "0010";
constant c_BV_CBE_IO_Write : bit_vector (3 downto 0) := "0011";
constant c_BV_CBE_Mem_Read : bit_vector (3 downto 0) := "0110";
constant c_BV_CBE_Mem_Write : bit_vector (3 downto 0) := "0111";
constant c_BV_CBE_Config_Read : bit_vector (3 downto 0) := "1010";
constant c_BV_CBE_Config_Write : bit_vector (3 downto 0) := "1011";
constant c_BV_CBE_Mem_Read_Mul : bit_vector (3 downto 0) := "1100";
constant c_BV_CBE_Dual_Add_Cycle : bit_vector (3 downto 0) := "1101";
constant c_BV_CBE_Mem_Read_line : bit_vector (3 downto 0) := "1110";
constant c_BV_CBE_Mem_Write_Inv : bit_vector (3 downto 0) := "1111";
constant Disable : bit := '0';
constant Enable : bit := '1';
constant NotSet : bit := '0';
constant Set : bit := '1';
constant PCI : bit := '0';
constant INT : bit := '1';
constant Mem : bit := '0';
constant IO : bit := '1';
constant No : bit := '0';
constant Yes : bit := '1';
constant Read : bit := '0';
constant Write : bit := '1';
constant Reset_Counter : integer := 0;
constant c_ulogic_DWord_Z : std_ulogic_vector (31 downto 0) := (others => 'Z');
constant c_ulogic_Word_Z : std_ulogic_vector (15 downto 0) := (others => 'Z');
constant c_ulogic_Byte_Z : std_ulogic_vector (7 downto 0) := (others => 'Z');
constant c_ulogic_Nibble_Z : std_ulogic_vector (3 downto 0) := (others => 'Z');
constant c_BV_QWord_0 : bit_vector (63 downto 0) := (others => '0');
constant c_BV_DWord_0 : bit_vector (31 downto 0) := (others => '0');
constant c_BV_Word_0 : bit_vector (15 downto 0) := (others => '0');
constant c_BV_Byte_0 : bit_vector (7 downto 0) := (others => '0');
constant c_BV_Nibble_0 : bit_vector (3 downto 0) := (others => '0');
constant c_ulogic_DWord_0 : std_ulogic_vector (31 downto 0) := (others => '0');
constant c_ulogic_Word_0 : std_ulogic_vector (15 downto 0) := (others => '0');
constant c_ulogic_Byte_0 : std_ulogic_vector (7 downto 0) := (others => '0');
constant c_ulogic_Nibble_0 : std_ulogic_vector (3 downto 0) := (others => '0');
-- Type Definitions
type Base_Addr_Reg is array (0 to 5) of std_ulogic_vector (31 downto 0);
type Base_Addr_Range is array (0 to 5) of std_ulogic_vector (31 downto 12);
type Base_Addr_Type is array (0 to 5) of bit;
type Base_Addr_Reg_BV is array (0 to 5) of bit_vector (31 downto 0);
type Data_Buffer_Array is array (0 to 15) of bit_vector (31 downto 0);
type Data_BE is array (0 to 15) of bit_vector (3 downto 0);
type CONFIGURATION_SPACE is record
Device_ID : bit_vector (15 downto 0);
Vendor_ID : bit_vector (15 downto 0);
Status : bit_vector (15 downto 0);
Command : bit_vector (15 downto 0);
Class_Code : bit_vector (23 downto 0);
Revision_ID : bit_vector (7 downto 0);
BIST : bit_vector (7 downto 0);
Header_Type : bit_vector (7 downto 0);
Latency_Timer : bit_vector (7 downto 0);
Cacheline_Size : bit_vector (7 downto 0);
Base_Address_Registers : Base_Addr_Reg_BV;
Cardbus_CIS_Pointer : bit_vector (31 downto 0);
Subsystem_ID : bit_vector (15 downto 0);
Subsystem_Vendor_ID : bit_vector (15 downto 0);
Expansion_ROM_Base_Address : bit_vector (31 downto 0);
Capabilities_Pointer : bit_vector (7 downto 0);
Max_Lat : bit_vector (7 downto 0);
Min_Gnt : bit_vector (7 downto 0);
Interrupt_Pin : bit_vector (7 downto 0);
Interrupt_line : bit_vector (7 downto 0);
end record CONFIGURATION_SPACE;
type CONFIGURATION_COMMAND is record
Address : bit_vector (31 downto 0);
Data : bit_vector (31 downto 0);
end record CONFIGURATION_COMMAND;
type Master_State is
(cs_Idle, cs_Addr, cs_S_Tar, cs_Dr_Bus, cs_Turn_Ar,
cs_M_Data);
type Lock_State is
(cs_Free, cs_Busy);
type Target_State is
(cs_Idle, cs_B_Busy, cs_S_Data, cs_Backoff, cs_Turn_ar);
type DATA_BUFFER is record
Data : Data_Buffer_Array;
BE : Data_BE;
Valid_Data : integer range 0 to 15;
end record DATA_BUFFER;
end PROTOCOL;
|
-- NICSim-vhd: A VHDL-based modelling and simulation of NIC's buffers
-- Copyright (C) 2013 Godofredo R. Garay <godofredo.garay (-at-) gmail.com>
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
use std.textio.all;
library ieee;
use ieee.math_real.all; -- for uniform
use ieee.std_logic_1164.all;
entity othermaster is
port (
frame : inout std_logic := 'Z';
pciclk : in bit
);
end othermaster;
architecture V1 of othermaster is
--------------- Random number generator configuration ---------------
--Baseline
constant othermaster_seed1_value : positive := 6;
constant othermaster_seed2_value : positive := 31;
--Run 1
--constant othermaster_seed1_value : positive := 680;
--constant othermaster_seed2_value : positive := 613;
--Run 2
--constant othermaster_seed1_value : positive := 700;
--constant othermaster_seed2_value : positive := 88;
--Run 3
--constant othermaster_seed1_value : positive := 47;
--constant othermaster_seed2_value : positive := 92;
--Run 4
--constant othermaster_seed1_value : positive := 72;
--constant othermaster_seed2_value : positive := 1;
--Run 5
--constant othermaster_seed1_value : positive := 37;
--constant othermaster_seed2_value : positive := 41;
--Run 6
--constant othermaster_seed1_value : positive := 1;
--constant othermaster_seed2_value : positive := 500;
--Run 7
--constant othermaster_seed1_value : positive := 2000;
--constant othermaster_seed2_value : positive := 2001;
--constant othermaster_seed1_value : positive := 2030;
--constant othermaster_seed2_value : positive := 2101;
--constant othermaster_seed1_value : positive := 2011;
--constant othermaster_seed2_value : positive := 1970;
--constant othermaster_seed1_value : positive := 1933;
--constant othermaster_seed2_value : positive := 1937;
--constant othermaster_seed1_value : positive := 73;
--constant othermaster_seed2_value : positive := 194;
--constant othermaster_seed1_value : positive := 3;
--constant othermaster_seed2_value : positive := 101;
--constant othermaster_seed1_value : positive := 1356;
--constant othermaster_seed2_value : positive := 4;
--constant othermaster_seed1_value : positive := 9;
--constant othermaster_seed2_value : positive := 884;
--------------- Bus arbitration latency configuration ---------------
constant min_transaction_in_progress_latency : positive := 1;
constant max_transaction_in_progress_latency : positive := 80;
--------------- Variables Declarations ---------------
shared variable trdy_value : bit := '1';
shared variable random_cycles_count : integer := 0;
shared variable latency_cycles_count : integer := 0;
shared variable total_acquisition_cycles : integer := 0;
shared variable total_bus_transfer_cycles : integer := 0;
shared variable current_transaction_cycles_count : integer := 0;
--shared variable acquisition_cycles_count : integer := 0;
-- Variables needed for Memsub FSM
type othermaster_fsm_state is (watching_bus_state,
bus_acquired,
bus_idle);
shared variable state : othermaster_fsm_state := watching_bus_state; --Initial state = watching_bus_state
shared variable next_state : othermaster_fsm_state := watching_bus_state;
-- These signals are used to handle frame bidirectional port
signal dir : std_logic := '0'; -- '0' reading, '1' driving
signal frame_out : std_logic := 'Z';
-- ****** In the future, constant pcilck_period should be removed a function based on the pciclk signal should be implemented
--constant pciclk_period : time := 0.03030303 us; -- PCI 33
--constant pciclk_period : time := 0.015151515 us; -- PCI-X 66
constant pciclk_period : time := 0.007518797 us; -- PCI-X 133
--constant pciclk_period : time := 0.003759398 us; -- PCI-X 266
--constant pciclk_period : time := 0.001876173 us; -- PCI-X 533
--constant tpd : time := 1 ns; ****** To be removed
begin
frame <= frame_out when (dir = '1') else 'Z';
othermaster_fsm: process
begin
wait until pciclk'event and pciclk = '1';
case state is
when watching_bus_state =>
--gnt_value := '1';
--bus_transfer_cycles_counter := 0;
--latency_cycles_count := 0;
--This wait cycle allows us avoiding bus contention among the NIC and othermaster
wait for pciclk_period;
dir <= '0';
if frame = '0'
then --dir <= '0' ;
next_state := watching_bus_state;
elsif frame = 'Z'
then dir <= '1';
frame_out <= '0';
current_transaction_cycles_count := random_cycles_count;
--latency_cycles_count := generate_random_latency_in_cycles;
--acquisition_cycles_count := random_cycles_count;
--total_acquisition_cycles := total_acquisition_cycles + acquisition_cycles_count;
--bus_transfer_cycles_counter := dma_burst_size_in_cycles;
--total_bus_transfer_cycles = total_bus_transfer_cycles + bus_transfer_cycles_counter;
assert false
report "othermaster_fsm: bus_acquired"
severity note;
next_state := bus_acquired;
elsif frame = '1'
then dir <= '0';
assert false
report "othermaster_fsm: bus_acquired"
severity note;
next_state := bus_acquired;
end if;
when bus_acquired =>
dir <= '1';
frame_out <= '0';
if current_transaction_cycles_count > 0
then current_transaction_cycles_count := current_transaction_cycles_count - 1;
next_state := bus_acquired;
elsif current_transaction_cycles_count = 0
then dir <= '1';
frame_out <= '1';
assert false
report "othermaster_fsm: bus_idle"
severity note;
next_state := bus_idle;
end if;
when bus_idle =>
dir <= '0';
assert false
report "othermaster_fsm: watching_bus_state"
severity note;
next_state := watching_bus_state;
end case;
state := next_state;
end process othermaster_fsm;
random_number_generator_fsm: process
type generator_state is (generating_random_number, waiting);
variable state : generator_state := generating_random_number;
variable next_state : generator_state := generating_random_number;
variable random_number : integer := 1;
variable seed1 : positive := othermaster_seed1_value;
variable seed2 : positive := othermaster_seed2_value;
variable rand : real;
file random_current_transaction_cycles_count_file : text open write_mode is "random_current_transaction_cycles_count.out";
variable output_line : line;
begin
case state is
when generating_random_number =>
-- Since rand values are in the interval 0..1, the values are multiplicated by 1000 and rounded.
-- This way, an integer random value in the interval 1..1000 is obtained
uniform(seed1, seed2, rand);
random_number := integer(round(rand*1000.0));
--random_number := 5;
if random_number >= min_transaction_in_progress_latency
and random_number <= max_transaction_in_progress_latency
then random_cycles_count := random_number;
write(output_line, random_cycles_count);
writeline(random_current_transaction_cycles_count_file, output_line);
assert false
report "random_number_generator_fsm: waiting"
severity note;
next_state := waiting;
else next_state := generating_random_number;
end if;
when waiting =>
wait until frame_out'event and frame_out = '0';
assert false
report "random_number_generator_fsm: generating random acquisition latency"
severity note;
next_state := generating_random_number;
end case;
state := next_state;
end process random_number_generator_fsm;
-- output_signals_driver: process
-- begin
-- wait until pciclk'event and pciclk = '1';
-- frame <= frame_value;
-- end process output_signals_driver;
end V1;
|
-- $Id: $
-- File name: tb_XmitSR.vhd
-- Created: 3/2/2012
-- Author: David Kauer
-- Lab Section: 2
-- Version: 1.0 Initial Test Bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_SpiXmitSR is
generic
(
srWidth : integer := 8;
CLK_PERIOD : Time := 10 ns
);
end tb_SpiXmitSR;
architecture TEST of tb_SpiXmitSR is
function UINT_TO_STD_LOGIC( X: INTEGER; NumBits: INTEGER )
return STD_LOGIC_VECTOR is
begin
return std_logic_vector(to_unsigned(X, NumBits));
end;
function STD_LOGIC_TO_UINT( X: std_logic_vector)
return integer is
begin
return to_integer(unsigned(x));
end;
component SpiXmitSR
PORT(
clk : in std_logic;
resetN : in std_logic;
tsrEnable : in std_logic;
shiftCtrl : in std_logic;
tsrLoad : in std_logic;
tsrData : in std_logic_vector(srWidth-1 downto 0);
mosi : out std_logic
);
end component;
signal clk : std_logic;
signal resetN : std_logic;
signal tsrEnable : std_logic;
signal shiftCtrl : std_logic;
signal tsrLoad : std_logic;
signal tsrData : std_logic_vector(srWidth-1 downto 0);
signal mosi : std_logic;
begin
process
begin
clk <= '1';
wait for CLK_PERIOD/2;
clk <= '0';
wait for CLK_PERIOD/2;
end process;
DUT: SpiXmitSR port map(
clk => clk,
resetN => resetN,
tsrEnable => tsrEnable,
shiftCtrl => shiftCtrl,
tsrLoad => tsrLoad,
tsrData => tsrData,
mosi => mosi
);
process
begin
-- run for 400 ns
tsrEnable <= '0';
shiftCtrl <= '0';
tsrLoad <= '0';
tsrData <= "00000000";
-- Reset System
resetN <= '0';
wait for 10 ns;
resetN <= '1';
-- Load data into SR
tsrLoad <= '1';
tsrData <= "10101010";
wait for 10 ns;
tsrLoad <= '0';
-- Shift data out
shiftCtrl <= '1';
for i in 0 to 7 loop
tsrEnable <= '1';
wait for 10 ns;
tsrEnable <= '0';
wait for 40 ns;
end loop;
shiftCtrl <= '0';
wait for 10 ns;
-- Load data into SR
tsrLoad <= '1';
tsrData <= "11001100";
wait for 10 ns;
tsrLoad <= '0';
wait;
end process;
end TEST;
|
---------------------------------------------------------------------------------------------
-- VIDEO DELAY - TOP FILE
--
-- Part of the Synkie Project: www.synkie.net
--
-- © 2013 Michael Egger, Licensed under GNU GPLv3
--
--------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Top is
port
(
Clk : in std_logic;
ResetN : in std_logic;
Display_C : out std_logic_vector(6 downto 0);
Display_A : out std_logic_vector(2 downto 0);
Encoder_A : in std_logic;
Encoder_B : in std_logic;
Encoder_C : in std_logic;
Led1 : out std_logic;
Led2 : out std_logic;
Led3 : out std_logic;
AD_Clk : out std_logic;
AD_Data : in std_logic_vector (7 downto 0);
DA_Clk : out std_logic;
DA_Data : out std_logic_vector (7 downto 0);
Switch1 : in std_logic;
Ram_Address : out std_logic_vector(13 downto 0); -- 12 bits Address / 2 bits BANK
Ram_RAS : out std_logic;
Ram_CAS : out std_logic;
Ram_WE : out std_logic;
Ram_Data : inout std_logic_vector(7 downto 0);
Ram_Clk : out std_logic;
Ram_DQM : out std_logic
);
end entity;
--------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------
architecture Top_Arch of Top is
------------------------------------------------------------------------------- Analog Converters
component AD_DA is
port (
Clk : in std_logic;
ResetN : in std_logic;
Loopthru : in std_logic;
Data_from_AD : out std_logic_vector (7 downto 0);
Data_to_DA : in std_logic_vector (7 downto 0);
AD_Clk : out std_logic;
AD_Input : in std_logic_vector (7 downto 0);
DA_Clk : out std_logic;
DA_Out : out std_logic_vector (7 downto 0)
);
end component;
------------------------------------------------------------------------------- SDRAM
component Ram_Controller is
port(
Clk : in std_logic;
ResetN : in std_logic;
Overflow : out std_logic;
Oszi_Trig : out std_logic;
--Loopthru : in std_logic;
Write_Data : in std_logic_vector (7 downto 0);
Read_Data : out std_logic_vector (7 downto 0);
Reset_Counter : in std_logic;
Ram_Address : out std_logic_vector(13 downto 0); -- 12 bits Address / 2 bits BANK
Ram_RAS : out std_logic;
Ram_CAS : out std_logic;
Ram_WE : out std_logic;
Ram_Data : inout std_logic_vector(7 downto 0);
Ram_Clk : out std_logic;
Ram_DQM : out std_logic
);
end component;
--------------------------------------------------------------------------------------------
-- Implementation
--------------------------------------------------------------------------------------------
signal ad_buf,da_buf : std_logic_vector(7 downto 0);
signal counter_int: std_logic_vector(7 downto 0);
signal enc_step,enc_dir : std_logic;
begin
------------------------------------------------------------------------------- AD-DA
AD_DA_Inst : AD_DA
port map
(
Clk => Clk, --156.25 MHz
ResetN => ResetN,
Loopthru => Switch1,
Data_from_AD => ad_buf,
Data_to_DA => da_buf,
AD_Clk => AD_Clk,
AD_Input => AD_Data,
DA_Clk => DA_Clk,
DA_Out => DA_Data
);
------------------------------------------------------------------------------- SDRAM
Ram_Controller_Inst : Ram_Controller
port map(
Clk => Clk,
ResetN => ResetN,
Overflow => LED2,
Oszi_Trig => LED1,
Reset_Counter => Encoder_C,
-- Loopthru => Switch1,
Write_Data => ad_buf,
Read_Data => da_buf,
Ram_Address => Ram_Address,
Ram_RAS => Ram_RAS,
Ram_CAS => Ram_CAS,
Ram_WE => Ram_WE,
Ram_Data => Ram_Data,
Ram_Clk => Ram_Clk,
Ram_DQM => Ram_DQM
);
------------------------------------------------------------------------------- LEDs
--LED3 <= '1';--very_slow_clk_int;
Display_C <= "1111111";
LED3 <= Encoder_C;
end Top_Arch;
|
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_clk_ddr_s8_se.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: 1-bit generic 1:n DDR clock receiver module for serdes factors from 2 to 8 with differential inputs
-- Instantiates necessary BUFIO2 clock buffers
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_1_to_n_clk_ddr_s8_se is generic (
S : integer := 8) ; -- Parameter to set the serdes factor 1..8
port (
clkin1 : in std_logic ; -- Input from se receiver pin
clkin2 : in std_logic ; -- Input from se receiver pin
rxioclkp : out std_logic ; -- IO Clock network
rxioclkn : out std_logic ; -- IO Clock network
rx_serdesstrobe : out std_logic ; -- Parallel data capture strobe
rx_bufg_x1 : out std_logic) ; -- Global clock
end serdes_1_to_n_clk_ddr_s8_se ;
architecture arch_serdes_1_to_n_clk_ddr_s8_se of serdes_1_to_n_clk_ddr_s8_se is
signal ddly_m : std_logic; -- Master output from IODELAY1
signal ddly_s : std_logic; -- Slave output from IODELAY1
signal rx_clk_in : std_logic; --
signal iob_data_in_p : std_logic; --
signal iob_data_in_n : std_logic; --
signal rx_clk_in_p : std_logic; --
signal rx_clk_in_n : std_logic; --
signal rx_bufio2_x1 : std_logic; --
constant RX_SWAP_CLK : std_logic := '0' ; -- pinswap mask for input clock (0 = no swap (default), 1 = swap). Allows input to be connected the wrong way round to ease PCB routing.
begin
iob_clk_in1 : IBUFG port map (
I => clkin1,
O => rx_clk_in_p) ;
iob_clk_in2 : IBUFG port map (
I => clkin2,
O => rx_clk_in_n) ;
iob_data_in_p <= rx_clk_in_p xor RX_SWAP_CLK ; -- Invert clock as required
iob_data_in_n <= not rx_clk_in_n xor RX_SWAP_CLK ; -- Invert clock as required, remembering the 2nd parallle clock input needs to be inverted
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 49, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "FIXED", -- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in_p, -- data from master IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => '0', -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => '0', -- Fabric clock (GCLK) for control signals
CAL => '0', -- Calibrate enable signal
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => '0', -- Reset delay line to 1/2 max in this case
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 49, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "FIXED", -- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in_n, -- data from slave IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => '0', -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => '0', -- Fabric clock (GCLK) for control signals
CAL => '0', -- Calibrate control signal, never needed as the slave supplies the clock input to the PLL
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => '0', -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
bufg_pll_x1 : BUFG port map (I => rx_bufio2_x1, O => rx_bufg_x1) ;
bufio2_2clk_inst : BUFIO2_2CLK generic map(
DIVIDE => S) -- The DIVCLK divider divide-by value; default 1
port map (
I => ddly_m, -- Input source clock 0 degrees
IB => ddly_s, -- Input source clock 0 degrees
IOCLK => rxioclkp, -- Output Clock for IO
DIVCLK => rx_bufio2_x1, -- Output Divided Clock
SERDESSTROBE => rx_serdesstrobe) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst : BUFIO2 generic map(
I_INVERT => FALSE, --
DIVIDE_BYPASS => FALSE, --
USE_DOUBLER => FALSE) --
port map (
I => ddly_s, -- N_clk input from IDELAY
IOCLK => rxioclkn, -- Output Clock
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
end arch_serdes_1_to_n_clk_ddr_s8_se ;
|
-- $Id: sys_conf_sim.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_n3 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-25 432 1.0 Initial version (cloned from _n3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1; -- no dcm in sim...
-- constant sys_conf_clkfx_divide : positive := 5;
-- constant sys_conf_clkfx_multiply : positive := 4; -- ==> 80 MHz
constant sys_conf_memctl_read0delay : positive := 6; -- for 100 MHz
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 7;
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_bram : integer := 0; -- no bram, use cache
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
-- constant sys_conf_bram : integer := 1; -- bram only
-- constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB)
-- constant sys_conf_mem_losize : integer := 8#001777#; -- 64 kByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
-- derived constants
constant sys_conf_clksys : integer :=
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
-- 2 211 111 111 110 000 000 000
-- 1 098 765 432 109 876 543 210
--
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
-- upper 256 kB excluded for 11/70 UB
|
--
-- GPIOs on DE0-Nano
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
entity Top is
port (
dips_i : in std_logic_vector(3 downto 0);
pbs_i : in std_logic_vector(1 downto 0);
leds_o : out std_logic_vector(7 downto 0)
);
end entity Top;
architecture RTL of Top is
begin
leds_o <= not(pbs_i) & pbs_i & dips_i;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmos_sensor_input_avalon_st_source is
generic(
DATA_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
-- Avalon-ST Source
ready : in std_logic;
valid : out std_logic;
data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
-- fifo
fifo_read : out std_logic;
fifo_empty : in std_logic;
fifo_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
fifo_end_of_frame : in std_logic;
fifo_overflow : in std_logic;
-- sampler
end_of_frame_out : out std_logic;
end_of_frame_out_ack : in std_logic
);
end entity cmos_sensor_input_avalon_st_source;
architecture rtl of cmos_sensor_input_avalon_st_source is
type state_type is (STATE_IDLE, STATE_READY_CYCLE, STATE_WAIT_END_OF_FRAME_ACK);
signal reg_state, next_reg_state : state_type;
signal data_little_endian : std_logic_vector(data'range);
signal data_big_endian : std_logic_vector(data'range);
begin
STATE_LOGIC : process(clk, reset)
begin
if reset = '1' then
reg_state <= STATE_IDLE;
elsif rising_edge(clk) then
if stop_and_reset = '1' then
reg_state <= STATE_IDLE;
else
reg_state <= next_reg_state;
end if;
end if;
end process;
NEXT_STATE_LOGIC : process(data_big_endian, end_of_frame_out_ack, fifo_empty, fifo_end_of_frame, fifo_overflow, ready, reg_state)
begin
fifo_read <= '0';
valid <= '0';
data <= (others => '0');
end_of_frame_out <= '0';
next_reg_state <= reg_state;
case reg_state is
when STATE_IDLE =>
if ready = '1' then
next_reg_state <= STATE_READY_CYCLE;
end if;
when STATE_READY_CYCLE =>
if ready = '0' then
next_reg_state <= STATE_IDLE;
end if;
if fifo_empty = '0' and fifo_overflow = '0' then
fifo_read <= '1';
valid <= '1';
data <= data_big_endian;
if fifo_end_of_frame = '1' then
next_reg_state <= STATE_WAIT_END_OF_FRAME_ACK;
end if;
end if;
when STATE_WAIT_END_OF_FRAME_ACK =>
end_of_frame_out <= '1';
if end_of_frame_out_ack = '1' then
next_reg_state <= STATE_IDLE;
end if;
end case;
end process;
data_little_endian <= fifo_data;
NETWORK_ORDER : process(data_little_endian)
begin
-- data is an Avalon-ST interface, so it needs to arrange data in
-- network order (a.k.a big-endian).
-- This component is specified to support 8 bits per symbol for its
-- Avalon-ST interface, so data is flipped on 8-bit boundaries.
for i in 0 to (DATA_WIDTH / 8) - 1 loop
data_big_endian(8 * (i + 1) - 1 downto 8 * i) <= data_little_endian(data_little_endian'length - 8 * i - 1 downto data_little_endian'length - 8 * (i + 1));
end loop;
end process;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmos_sensor_input_avalon_st_source is
generic(
DATA_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
-- Avalon-ST Source
ready : in std_logic;
valid : out std_logic;
data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
-- fifo
fifo_read : out std_logic;
fifo_empty : in std_logic;
fifo_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
fifo_end_of_frame : in std_logic;
fifo_overflow : in std_logic;
-- sampler
end_of_frame_out : out std_logic;
end_of_frame_out_ack : in std_logic
);
end entity cmos_sensor_input_avalon_st_source;
architecture rtl of cmos_sensor_input_avalon_st_source is
type state_type is (STATE_IDLE, STATE_READY_CYCLE, STATE_WAIT_END_OF_FRAME_ACK);
signal reg_state, next_reg_state : state_type;
signal data_little_endian : std_logic_vector(data'range);
signal data_big_endian : std_logic_vector(data'range);
begin
STATE_LOGIC : process(clk, reset)
begin
if reset = '1' then
reg_state <= STATE_IDLE;
elsif rising_edge(clk) then
if stop_and_reset = '1' then
reg_state <= STATE_IDLE;
else
reg_state <= next_reg_state;
end if;
end if;
end process;
NEXT_STATE_LOGIC : process(data_big_endian, end_of_frame_out_ack, fifo_empty, fifo_end_of_frame, fifo_overflow, ready, reg_state)
begin
fifo_read <= '0';
valid <= '0';
data <= (others => '0');
end_of_frame_out <= '0';
next_reg_state <= reg_state;
case reg_state is
when STATE_IDLE =>
if ready = '1' then
next_reg_state <= STATE_READY_CYCLE;
end if;
when STATE_READY_CYCLE =>
if ready = '0' then
next_reg_state <= STATE_IDLE;
end if;
if fifo_empty = '0' and fifo_overflow = '0' then
fifo_read <= '1';
valid <= '1';
data <= data_big_endian;
if fifo_end_of_frame = '1' then
next_reg_state <= STATE_WAIT_END_OF_FRAME_ACK;
end if;
end if;
when STATE_WAIT_END_OF_FRAME_ACK =>
end_of_frame_out <= '1';
if end_of_frame_out_ack = '1' then
next_reg_state <= STATE_IDLE;
end if;
end case;
end process;
data_little_endian <= fifo_data;
NETWORK_ORDER : process(data_little_endian)
begin
-- data is an Avalon-ST interface, so it needs to arrange data in
-- network order (a.k.a big-endian).
-- This component is specified to support 8 bits per symbol for its
-- Avalon-ST interface, so data is flipped on 8-bit boundaries.
for i in 0 to (DATA_WIDTH / 8) - 1 loop
data_big_endian(8 * (i + 1) - 1 downto 8 * i) <= data_little_endian(data_little_endian'length - 8 * i - 1 downto data_little_endian'length - 8 * (i + 1));
end loop;
end process;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmos_sensor_input_avalon_st_source is
generic(
DATA_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
-- Avalon-ST Source
ready : in std_logic;
valid : out std_logic;
data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
-- fifo
fifo_read : out std_logic;
fifo_empty : in std_logic;
fifo_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
fifo_end_of_frame : in std_logic;
fifo_overflow : in std_logic;
-- sampler
end_of_frame_out : out std_logic;
end_of_frame_out_ack : in std_logic
);
end entity cmos_sensor_input_avalon_st_source;
architecture rtl of cmos_sensor_input_avalon_st_source is
type state_type is (STATE_IDLE, STATE_READY_CYCLE, STATE_WAIT_END_OF_FRAME_ACK);
signal reg_state, next_reg_state : state_type;
signal data_little_endian : std_logic_vector(data'range);
signal data_big_endian : std_logic_vector(data'range);
begin
STATE_LOGIC : process(clk, reset)
begin
if reset = '1' then
reg_state <= STATE_IDLE;
elsif rising_edge(clk) then
if stop_and_reset = '1' then
reg_state <= STATE_IDLE;
else
reg_state <= next_reg_state;
end if;
end if;
end process;
NEXT_STATE_LOGIC : process(data_big_endian, end_of_frame_out_ack, fifo_empty, fifo_end_of_frame, fifo_overflow, ready, reg_state)
begin
fifo_read <= '0';
valid <= '0';
data <= (others => '0');
end_of_frame_out <= '0';
next_reg_state <= reg_state;
case reg_state is
when STATE_IDLE =>
if ready = '1' then
next_reg_state <= STATE_READY_CYCLE;
end if;
when STATE_READY_CYCLE =>
if ready = '0' then
next_reg_state <= STATE_IDLE;
end if;
if fifo_empty = '0' and fifo_overflow = '0' then
fifo_read <= '1';
valid <= '1';
data <= data_big_endian;
if fifo_end_of_frame = '1' then
next_reg_state <= STATE_WAIT_END_OF_FRAME_ACK;
end if;
end if;
when STATE_WAIT_END_OF_FRAME_ACK =>
end_of_frame_out <= '1';
if end_of_frame_out_ack = '1' then
next_reg_state <= STATE_IDLE;
end if;
end case;
end process;
data_little_endian <= fifo_data;
NETWORK_ORDER : process(data_little_endian)
begin
-- data is an Avalon-ST interface, so it needs to arrange data in
-- network order (a.k.a big-endian).
-- This component is specified to support 8 bits per symbol for its
-- Avalon-ST interface, so data is flipped on 8-bit boundaries.
for i in 0 to (DATA_WIDTH / 8) - 1 loop
data_big_endian(8 * (i + 1) - 1 downto 8 * i) <= data_little_endian(data_little_endian'length - 8 * i - 1 downto data_little_endian'length - 8 * (i + 1));
end loop;
end process;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmos_sensor_input_avalon_st_source is
generic(
DATA_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
-- Avalon-ST Source
ready : in std_logic;
valid : out std_logic;
data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
-- fifo
fifo_read : out std_logic;
fifo_empty : in std_logic;
fifo_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
fifo_end_of_frame : in std_logic;
fifo_overflow : in std_logic;
-- sampler
end_of_frame_out : out std_logic;
end_of_frame_out_ack : in std_logic
);
end entity cmos_sensor_input_avalon_st_source;
architecture rtl of cmos_sensor_input_avalon_st_source is
type state_type is (STATE_IDLE, STATE_READY_CYCLE, STATE_WAIT_END_OF_FRAME_ACK);
signal reg_state, next_reg_state : state_type;
signal data_little_endian : std_logic_vector(data'range);
signal data_big_endian : std_logic_vector(data'range);
begin
STATE_LOGIC : process(clk, reset)
begin
if reset = '1' then
reg_state <= STATE_IDLE;
elsif rising_edge(clk) then
if stop_and_reset = '1' then
reg_state <= STATE_IDLE;
else
reg_state <= next_reg_state;
end if;
end if;
end process;
NEXT_STATE_LOGIC : process(data_big_endian, end_of_frame_out_ack, fifo_empty, fifo_end_of_frame, fifo_overflow, ready, reg_state)
begin
fifo_read <= '0';
valid <= '0';
data <= (others => '0');
end_of_frame_out <= '0';
next_reg_state <= reg_state;
case reg_state is
when STATE_IDLE =>
if ready = '1' then
next_reg_state <= STATE_READY_CYCLE;
end if;
when STATE_READY_CYCLE =>
if ready = '0' then
next_reg_state <= STATE_IDLE;
end if;
if fifo_empty = '0' and fifo_overflow = '0' then
fifo_read <= '1';
valid <= '1';
data <= data_big_endian;
if fifo_end_of_frame = '1' then
next_reg_state <= STATE_WAIT_END_OF_FRAME_ACK;
end if;
end if;
when STATE_WAIT_END_OF_FRAME_ACK =>
end_of_frame_out <= '1';
if end_of_frame_out_ack = '1' then
next_reg_state <= STATE_IDLE;
end if;
end case;
end process;
data_little_endian <= fifo_data;
NETWORK_ORDER : process(data_little_endian)
begin
-- data is an Avalon-ST interface, so it needs to arrange data in
-- network order (a.k.a big-endian).
-- This component is specified to support 8 bits per symbol for its
-- Avalon-ST interface, so data is flipped on 8-bit boundaries.
for i in 0 to (DATA_WIDTH / 8) - 1 loop
data_big_endian(8 * (i + 1) - 1 downto 8 * i) <= data_little_endian(data_little_endian'length - 8 * i - 1 downto data_little_endian'length - 8 * (i + 1));
end loop;
end process;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmos_sensor_input_avalon_st_source is
generic(
DATA_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
-- Avalon-ST Source
ready : in std_logic;
valid : out std_logic;
data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
-- fifo
fifo_read : out std_logic;
fifo_empty : in std_logic;
fifo_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
fifo_end_of_frame : in std_logic;
fifo_overflow : in std_logic;
-- sampler
end_of_frame_out : out std_logic;
end_of_frame_out_ack : in std_logic
);
end entity cmos_sensor_input_avalon_st_source;
architecture rtl of cmos_sensor_input_avalon_st_source is
type state_type is (STATE_IDLE, STATE_READY_CYCLE, STATE_WAIT_END_OF_FRAME_ACK);
signal reg_state, next_reg_state : state_type;
signal data_little_endian : std_logic_vector(data'range);
signal data_big_endian : std_logic_vector(data'range);
begin
STATE_LOGIC : process(clk, reset)
begin
if reset = '1' then
reg_state <= STATE_IDLE;
elsif rising_edge(clk) then
if stop_and_reset = '1' then
reg_state <= STATE_IDLE;
else
reg_state <= next_reg_state;
end if;
end if;
end process;
NEXT_STATE_LOGIC : process(data_big_endian, end_of_frame_out_ack, fifo_empty, fifo_end_of_frame, fifo_overflow, ready, reg_state)
begin
fifo_read <= '0';
valid <= '0';
data <= (others => '0');
end_of_frame_out <= '0';
next_reg_state <= reg_state;
case reg_state is
when STATE_IDLE =>
if ready = '1' then
next_reg_state <= STATE_READY_CYCLE;
end if;
when STATE_READY_CYCLE =>
if ready = '0' then
next_reg_state <= STATE_IDLE;
end if;
if fifo_empty = '0' and fifo_overflow = '0' then
fifo_read <= '1';
valid <= '1';
data <= data_big_endian;
if fifo_end_of_frame = '1' then
next_reg_state <= STATE_WAIT_END_OF_FRAME_ACK;
end if;
end if;
when STATE_WAIT_END_OF_FRAME_ACK =>
end_of_frame_out <= '1';
if end_of_frame_out_ack = '1' then
next_reg_state <= STATE_IDLE;
end if;
end case;
end process;
data_little_endian <= fifo_data;
NETWORK_ORDER : process(data_little_endian)
begin
-- data is an Avalon-ST interface, so it needs to arrange data in
-- network order (a.k.a big-endian).
-- This component is specified to support 8 bits per symbol for its
-- Avalon-ST interface, so data is flipped on 8-bit boundaries.
for i in 0 to (DATA_WIDTH / 8) - 1 loop
data_big_endian(8 * (i + 1) - 1 downto 8 * i) <= data_little_endian(data_little_endian'length - 8 * i - 1 downto data_little_endian'length - 8 * (i + 1));
end loop;
end process;
end architecture rtl;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 10:20:39 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux4x1_8_0_1/RAT_Mux4x1_8_0_1_sim_netlist.vhdl
-- Design : RAT_Mux4x1_8_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_Mux4x1_8_0_1_Mux4x1_8 is
port (
X : out STD_LOGIC_VECTOR ( 7 downto 0 );
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
C : in STD_LOGIC_VECTOR ( 7 downto 0 );
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
A : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of RAT_Mux4x1_8_0_1_Mux4x1_8 : entity is "Mux4x1_8";
end RAT_Mux4x1_8_0_1_Mux4x1_8;
architecture STRUCTURE of RAT_Mux4x1_8_0_1_Mux4x1_8 is
begin
\X[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(0),
I1 => B(0),
I2 => C(0),
I3 => SEL(1),
I4 => A(0),
I5 => SEL(0),
O => X(0)
);
\X[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(1),
I1 => B(1),
I2 => C(1),
I3 => SEL(1),
I4 => A(1),
I5 => SEL(0),
O => X(1)
);
\X[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(2),
I1 => B(2),
I2 => C(2),
I3 => SEL(1),
I4 => A(2),
I5 => SEL(0),
O => X(2)
);
\X[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(3),
I1 => B(3),
I2 => C(3),
I3 => SEL(1),
I4 => A(3),
I5 => SEL(0),
O => X(3)
);
\X[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(4),
I1 => B(4),
I2 => C(4),
I3 => SEL(1),
I4 => A(4),
I5 => SEL(0),
O => X(4)
);
\X[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(5),
I1 => B(5),
I2 => C(5),
I3 => SEL(1),
I4 => A(5),
I5 => SEL(0),
O => X(5)
);
\X[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(6),
I1 => B(6),
I2 => C(6),
I3 => SEL(1),
I4 => A(6),
I5 => SEL(0),
O => X(6)
);
\X[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(7),
I1 => B(7),
I2 => C(7),
I3 => SEL(1),
I4 => A(7),
I5 => SEL(0),
O => X(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_Mux4x1_8_0_1 is
port (
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
C : in STD_LOGIC_VECTOR ( 7 downto 0 );
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
X : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_Mux4x1_8_0_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_Mux4x1_8_0_1 : entity is "RAT_Mux4x1_8_0_1,Mux4x1_8,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_Mux4x1_8_0_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_Mux4x1_8_0_1 : entity is "Mux4x1_8,Vivado 2016.4";
end RAT_Mux4x1_8_0_1;
architecture STRUCTURE of RAT_Mux4x1_8_0_1 is
begin
U0: entity work.RAT_Mux4x1_8_0_1_Mux4x1_8
port map (
A(7 downto 0) => A(7 downto 0),
B(7 downto 0) => B(7 downto 0),
C(7 downto 0) => C(7 downto 0),
D(7 downto 0) => D(7 downto 0),
SEL(1 downto 0) => SEL(1 downto 0),
X(7 downto 0) => X(7 downto 0)
);
end STRUCTURE;
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL Package - soundgates_common_pkg
--
-- project: PG-Soundgates
-- author: Lukas Funke, University of Paderborn
--
-- description: Common functions, declaration, constants for sound
-- processing components
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
package soundgates_common_pkg is
-- Constant declarations
constant SOUNDGATE_FIX_PT_SCALING : real := 28.0;
constant MAX_NCO_FREQUNCY : integer := 16000;
constant SAMPLE_WIDTH : integer := 32;
-- Type declarations
type Phase_Increment_Array is array(0 to MAX_NCO_FREQUNCY) of signed(31 downto 0);
type WAVEFORM_TYPE is ( SIN, SQU, SAW, TRI);
type NOISE_TYPE is ( WHITE, PINK, GREY );
type ARITHMETIC_TYPE is ( ADD, SUB, MUL );
type mem16 is array (natural range <>) of signed(15 downto 0);
type mem24 is array (natural range <>) of signed(23 downto 0);
type mem32 is array (natural range <>) of signed(31 downto 0);
type mem64 is array (natural range <>) of signed(63 downto 0);
------------------------------------------------------------
-- Functions and Procedure declarations
------------------------------------------------------------
------------------------------------------------------------
function Precalculate_Phase_Increments (FPGA_FREQUENCY : integer) return Phase_Increment_Array;
function Precalculate_Cordic_Phase_Increments (FPGA_FREQUENCY : integer) return Phase_Increment_Array;
function Get_Cordic_Phase_Increment (FPGA_FREQUENCY, SIN_FREQUENCY : integer) return signed;
------------------------------------------------------------
end package soundgates_common_pkg;
package body soundgates_common_pkg is
function Get_Cordic_Phase_Increment (FPGA_FREQUENCY, SIN_FREQUENCY : integer) return signed is
variable stepsize : integer;
variable phi_incr_real : real;
variable phi_incr_signed : signed(31 downto 0);
begin
if SIN_FREQUENCY > 0 then
--stepsize := FPGA_FREQUENCY / SIN_FREQUENCY;
--phi_incr_real := MATH_PI * 2.0 / real(stepsize);
--phi_incr_signed := to_signed(integer(real(phi_incr_real) * 2**SOUNDGATE_FIX_PT_SCALING), 32);
phi_incr_real := (MATH_PI * 2.0 * real(SIN_FREQUENCY) / 44100.0) * 2**SOUNDGATE_FIX_PT_SCALING;
phi_incr_signed := to_signed(integer(phi_incr_real), 32);
else
phi_incr_signed := to_signed(0, 32);
end if;
return phi_incr_signed;
end Get_Cordic_Phase_Increment;
function Precalculate_Cordic_Phase_Increments (FPGA_FREQUENCY : integer) return Phase_Increment_Array is
variable tmp : phase_increment_array;
variable stepsize : integer;
variable phi_offset : real;
begin
for i in 0 to MAX_NCO_FREQUNCY loop
if i > 0 then
stepsize := FPGA_FREQUENCY / i;
phi_offset := MATH_PI * 2.0 / real(stepsize);
tmp(i) := to_signed(integer(real(phi_offset) * 2**SOUNDGATE_FIX_PT_SCALING), 32);
else
tmp(i) := to_signed(0, 32);
end if;
end loop;
return tmp;
end Precalculate_Cordic_Phase_Increments;
function Precalculate_Phase_Increments (FPGA_FREQUENCY : integer) return Phase_Increment_Array is
variable tmp : phase_increment_array;
begin
for i in 0 to MAX_NCO_FREQUNCY loop
if i > 0 then
tmp(i) := to_signed(FPGA_FREQUENCY / i, 32);
else
tmp(i) := to_signed(0, 32);
end if;
end loop;
return tmp;
end Precalculate_Phase_Increments;
end package body soundgates_common_pkg;
|
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_axi_pat_gen.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is a very simple pattern generator which will generate packets
-- with the supplied dest_addr and src_addr and incrementing data. The packet size
-- increments between the min and max size (which can be set to the same value if a
-- specific size is required
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity tri_mode_ethernet_mac_0_axi_pat_gen is
generic (
DEST_ADDR : bit_vector(47 downto 0) := X"da0102030405";
SRC_ADDR : bit_vector(47 downto 0) := X"5a0102030405";
MAX_SIZE : unsigned(11 downto 0) := X"1f4";
MIN_SIZE : unsigned(11 downto 0) := X"040";
ENABLE_VLAN : boolean := false;
VLAN_ID : bit_vector(11 downto 0) := X"002";
VLAN_PRIORITY : bit_vector(2 downto 0) := "010"
);
port (
axi_tclk : in std_logic;
axi_tresetn : in std_logic;
enable_pat_gen : in std_logic;
speed : in std_logic_vector(1 downto 0);
tdata : out std_logic_vector(7 downto 0);
tvalid : out std_logic;
tlast : out std_logic;
tready : in std_logic
);
end tri_mode_ethernet_mac_0_axi_pat_gen;
architecture rtl of tri_mode_ethernet_mac_0_axi_pat_gen is
-- State machine
type state_typ is (IDLE,
HEADER,
SIZE,
SET_DATA,
OVERHEAD);
function Sel (Cond : boolean; A,B : integer) return integer is
begin
if Cond then
return A;
else
return B;
end if;
end function Sel;
-- work out the adjustment required to get the right packet size.
constant PKT_ADJUST : integer := Sel(ENABLE_VLAN,22,18);
-- generate the vlan fields
constant VLAN_HEADER : bit_vector(31 downto 0) := X"8100" & VLAN_PRIORITY & '0' & VLAN_ID;
-- generate the require header count compare
constant HEADER_LENGTH : integer := Sel(ENABLE_VLAN,15,11);
-- generate the required bandwidth controls based on speed
-- we want to use less than 100% bandwidth to avoid loopback overflow
constant BW_1G : integer := 230;
constant BW_100M : integer := 23;
constant BW_10M : integer := 2;
signal next_gen_state : state_typ;
signal gen_state : state_typ;
signal byte_count : unsigned(11 downto 0);
signal header_count : unsigned(3 downto 0);
signal overhead_count : unsigned(4 downto 0);
signal pkt_size : unsigned(11 downto 0);
signal lut_data : std_logic_vector(7 downto 0);
signal tvalid_int : std_logic;
-- rate control signals
signal basic_rc_counter : unsigned(7 downto 0);
signal add_credit : std_logic;
signal credit_count : unsigned(12 downto 0);
signal axi_treset : std_logic;
constant dummy : bit_vector(47 downto 0) := (others => '0');
begin
axi_treset <= not axi_tresetn;
-- need a packet counter - max size limited to 11 bits
byte_count_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
byte_count <= (others => '0');
elsif gen_state = SET_DATA and byte_count /= X"000" and tready = '1' then
byte_count <= byte_count - X"001";
elsif gen_state = HEADER then
byte_count <= pkt_size;
end if;
end if;
end process byte_count_p;
-- need a smaller count to manage the header insertion
header_count_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
header_count <= (others => '0');
elsif gen_state = HEADER and header_count /= X"F" and (tready = '1' or tvalid_int = '0') then
header_count <= header_count + X"1";
elsif gen_state = SIZE and tready = '1' then
header_count <= (others => '0');
end if;
end if;
end process header_count_p;
-- need a smaller count to manage the overhead
overhead_count_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
overhead_count <= (others => '0');
elsif gen_state = OVERHEAD and overhead_count /= "00000" and tready = '1' then
overhead_count <= overhead_count - "00001";
elsif gen_state = IDLE then
overhead_count <= "11000"; -- 24 in decimal
end if;
end if;
end process overhead_count_p;
-- need a smaller count to manage the header insertion
-- adjust parameter values by 18 to allow for header and crc
-- so the pkt_size can be sued directly in the size field
pkt_size_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
pkt_size <= MIN_SIZE - PKT_ADJUST;
elsif gen_state = SET_DATA and next_gen_state /= SET_DATA then
if pkt_size = MAX_SIZE - PKT_ADJUST then
pkt_size <= MIN_SIZE - PKT_ADJUST;
else
pkt_size <= pkt_size + "001";
end if;
end if;
end if;
end process pkt_size_p;
-- store the parametised values in a lut (64 deep)
-- this should mean the values could be adjusted in fpga_editor etc..
LUT6_gen : for I in 0 to 7 generate
begin
LUT6_inst : LUT6
generic map (
INIT => dummy &
VLAN_HEADER(I) &
VLAN_HEADER(I+8) &
VLAN_HEADER(I+16) &
VLAN_HEADER(I+24) &
SRC_ADDR(I) &
SRC_ADDR(I+8) &
SRC_ADDR(I+16) &
SRC_ADDR(I+24) &
SRC_ADDR(I+32) &
SRC_ADDR(I+40) &
DEST_ADDR(I) &
DEST_ADDR(I+8) &
DEST_ADDR(I+16) &
DEST_ADDR(I+24) &
DEST_ADDR(I+32) &
DEST_ADDR(I+40)
)
port map (
O => lut_data(I),
I0 => header_count(0),
I1 => header_count(1),
I2 => header_count(2),
I3 => header_count(3),
I4 => '0',
I5 => '0'
);
end generate;
-- rate control logic
-- first we need an always active counter to provide the credit control
basic_count_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' or enable_pat_gen = '0' then
basic_rc_counter <= (others => '1');
else
basic_rc_counter <= basic_rc_counter + X"01";
end if;
end if;
end process basic_count_p;
-- now we need to set the compare level depending upon the selected speed
-- the credits are applied using a simple less-than check
gen_inc_control_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if speed(1) = '1' then
if basic_rc_counter < X"E6" then -- decimal 230
add_credit <= '1';
else
add_credit <= '0';
end if;
elsif speed(0) = '1' then
if basic_rc_counter < X"17" then -- decimal 23
add_credit <= '1';
else
add_credit <= '0';
end if;
else
if basic_rc_counter < X"02" then
add_credit <= '1';
else
add_credit <= '0';
end if;
end if;
end if;
end process gen_inc_control_p;
-- basic credit counter - -ve value means do not send a frame
credit_count_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
credit_count <= (others => '0');
else
-- if we are in frame
if gen_state /= IDLE then
if add_credit = '0' and credit_count(12 downto 10) /= "110" then -- stop decrementing at -2048
credit_count <= credit_count - "0000000000001";
end if;
else
if add_credit = '1' and credit_count(12 downto 11) /= "01" then -- stop incrementing at 2048
credit_count <= credit_count + 1;
end if;
end if;
end if;
end if;
end process credit_count_p;
-- simple state machine to control the data
-- on the transition from IDLE we reset the counters and increment the packet size
next_s : process(gen_state, enable_pat_gen, header_count, tready, byte_count, tvalid_int, overhead_count, credit_count)
begin
next_gen_state <= gen_state;
case gen_state is
when IDLE =>
if enable_pat_gen = '1' and tvalid_int = '0' and credit_count(12) = '0' then
next_gen_state <= HEADER;
end if;
when HEADER =>
if header_count = HEADER_LENGTH and tready = '1' then
next_gen_state <= SIZE;
end if;
when SIZE =>
if header_count = X"0" and tready = '1' then
next_gen_state <= SET_DATA;
end if;
when SET_DATA =>
if byte_count = X"001" and tready = '1' then -- may need to be 1
next_gen_state <= OVERHEAD;
end if;
when OVERHEAD =>
if overhead_count = "00001" and tready = '1' then
next_gen_state <= IDLE;
end if;
end case;
end process;
state_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
gen_state <= IDLE;
else
gen_state <= next_gen_state;
end if;
end if;
end process state_p;
-- now generate the TVALID output
valid_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
tvalid_int <= '0';
elsif gen_state /= IDLE and gen_state /= OVERHEAD then
tvalid_int <= '1';
elsif tready = '1' then
tvalid_int <= '0';
end if;
end if;
end process valid_p;
-- now generate the TDATA output
data_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if gen_state = HEADER and (tready = '1' or tvalid_int = '0') then
tdata <= lut_data;
elsif gen_state = SIZE and tready = '1' then
if header_count(3) = '1' then
tdata <= "00000" & std_logic_vector(pkt_size(10 downto 8));
else
tdata <= std_logic_vector(pkt_size(7 downto 0));
end if;
elsif tready = '1' then
tdata <= std_logic_vector(byte_count(7 downto 0));
end if;
end if;
end process data_p;
-- now generate the TLAST output
last_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
tlast <= '0';
elsif byte_count = "001" and tready = '1' then
tlast <= '1';
elsif tready = '1' then
tlast <= '0';
end if;
end if;
end process last_p;
tvalid <= tvalid_int;
end rtl;
|
architecture test of test2 is
constant foo : bar := 32sO"12345";
begin end;
|
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------------------
entity DECODER is
port(OP1,OP2,OP3,OP4: in integer range 0 to 255;
CLOCK: std_logic;
OUTS: out integer range 0 to 1024);
end DECODER;
------------------------------------------
architecture behv of DECODER is
signal NEXT_OUTS: integer;
begin
process(CLOCK)
begin
if(rising_edge(CLOCK)) then
OUTS <= NEXT_OUTS;
end if;
end process;
process(OP1,OP2,OP3,OP4)
begin
case OP1 is
when 0 => NEXT_OUTS <= 503; -- addb_Eb_Gb SANITY
when 1 =>
case OP2 is
when 0 => NEXT_OUTS <= 12; -- addl_Ed_Gd SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 2 => NEXT_OUTS <= 313; -- addb_Gb_Eb SANITY
when 3 => NEXT_OUTS <= 336; -- addl_Gd_Ed SANITY
when 4 => NEXT_OUTS <= 457; -- addb_AL_Ib SANITY
when 5 => NEXT_OUTS <= 558; -- addl_EAX_Id SANITY
when 6 => NEXT_OUTS <= 201; -- pushl_ES SANITY
when 7 => NEXT_OUTS <= 238; -- popl_ES SANITY
when 8 => NEXT_OUTS <= 489; -- orb_Eb_Gb SANITY
when 9 => NEXT_OUTS <= 618; -- orl_Ed_Gd SANITY
when 10 => NEXT_OUTS <= 624; -- orb_Gb_Eb SANITY
when 11 => NEXT_OUTS <= 733; -- orl_Gd_Ed SANITY
when 12 => NEXT_OUTS <= 139; -- orb_AL_Ib SANITY
when 13 => NEXT_OUTS <= 163; -- orl_EAX_Id SANITY
when 14 => NEXT_OUTS <= 178; -- pushl_CS SANITY
when 15 =>
case OP2 is
when 0 =>
case OP3 is
when 0 => NEXT_OUTS <= 225; -- sldt SANITY
when 8 => NEXT_OUTS <= 147; -- str SANITY
when 16 => NEXT_OUTS <= 729; -- lldt SANITY
when 24 => NEXT_OUTS <= 415; -- ltr SANITY
when 32 => NEXT_OUTS <= 182; -- verr SANITY
when 40 => NEXT_OUTS <= 220; -- verw SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 1 =>
case OP3 is
when 0 => NEXT_OUTS <= 318; -- sgdt SANITY
when 8 => NEXT_OUTS <= 207; -- sidt SANITY
when 16 => NEXT_OUTS <= 477; -- lgdt SANITY
when 24 => NEXT_OUTS <= 389; -- lidt SANITY
when 32 => NEXT_OUTS <= 356; -- smsw_Ew SANITY
when 48 => NEXT_OUTS <= 404; -- lmsw_Ew SANITY
when 56 => NEXT_OUTS <= 573; -- invlpg SANITY
when 248 => NEXT_OUTS <= 456; -- swapgs SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 2 =>
case OP3 is
when 0 => NEXT_OUTS <= 365; -- larl_Gd_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 3 =>
case OP3 is
when 0 => NEXT_OUTS <= 156; -- lsll_Gd_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 8 => NEXT_OUTS <= 21; -- invd SANITY
when 9 => NEXT_OUTS <= 448; -- wbinvd SANITY
when 11 => NEXT_OUTS <= 41; -- ud2a SANITY
when 32 =>
case OP3 is
when 0 => NEXT_OUTS <= 295; -- movl_Rd_Cd SANITY
when 1 => NEXT_OUTS <= 583; -- movq_Rq_Cq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 33 =>
case OP3 is
when 0 => NEXT_OUTS <= 452; -- movl_Rd_Dd SANITY
when 1 => NEXT_OUTS <= 513; -- movq_Rq_Dq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 34 =>
case OP3 is
when 0 => NEXT_OUTS <= 743; -- movl_Cd_Rd SANITY
when 1 => NEXT_OUTS <= 433; -- movq_Cq_Rq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 35 =>
case OP3 is
when 0 => NEXT_OUTS <= 168; -- movl_Dd_Rd SANITY
when 1 => NEXT_OUTS <= 561; -- movq_Dq_Rq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 36 =>
case OP3 is
when 0 => NEXT_OUTS <= 283; -- movl_Rd_Td SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 38 => NEXT_OUTS <= 143; -- movl_Td_Rd SANITY
when 110 => NEXT_OUTS <= 568; -- movd_Pq_Ed SANITY
when 128 => NEXT_OUTS <= 202; -- jo_Jd SANITY
when 129 => NEXT_OUTS <= 159; -- jno_Jd SANITY
when 130 => NEXT_OUTS <= 782; -- jb_Jd SANITY
when 131 => NEXT_OUTS <= 312; -- jnb_Jd SANITY
when 132 => NEXT_OUTS <= 3; -- jz_Jd SANITY
when 133 => NEXT_OUTS <= 161; -- jnz_Jd SANITY
when 134 => NEXT_OUTS <= 284; -- jbe_Jd SANITY
when 135 => NEXT_OUTS <= 154; -- jnbe_Jd SANITY
when 136 => NEXT_OUTS <= 20; -- js_Jd SANITY
when 137 => NEXT_OUTS <= 108; -- jns_Jd SANITY
when 138 => NEXT_OUTS <= 184; -- jp_Jd SANITY
when 139 => NEXT_OUTS <= 74; -- jnp_Jd SANITY
when 140 => NEXT_OUTS <= 409; -- jl_Jd SANITY
when 141 => NEXT_OUTS <= 100; -- jnl_Jd SANITY
when 142 => NEXT_OUTS <= 497; -- jle_Jd SANITY
when 143 => NEXT_OUTS <= 322; -- jnle_Jd SANITY
when 144 => NEXT_OUTS <= 14; -- seto_Eb SANITY
when 145 => NEXT_OUTS <= 62; -- setno_Eb SANITY
when 146 => NEXT_OUTS <= 227; -- setb_Eb SANITY
when 147 => NEXT_OUTS <= 67; -- setnb_Eb SANITY
when 148 => NEXT_OUTS <= 237; -- setz_Eb SANITY
when 149 => NEXT_OUTS <= 374; -- setnz_Eb SANITY
when 150 => NEXT_OUTS <= 39; -- setbe_Eb SANITY
when 151 => NEXT_OUTS <= 212; -- setnbe_Eb SANITY
when 152 => NEXT_OUTS <= 459; -- sets_Eb SANITY
when 153 => NEXT_OUTS <= 424; -- setns_Eb SANITY
when 154 => NEXT_OUTS <= 304; -- setp_Eb SANITY
when 155 => NEXT_OUTS <= 718; -- setnp_Eb SANITY
when 156 => NEXT_OUTS <= 24; -- setl_Eb SANITY
when 157 => NEXT_OUTS <= 385; -- setnl_Eb SANITY
when 158 => NEXT_OUTS <= 429; -- setle_Eb SANITY
when 159 => NEXT_OUTS <= 590; -- setnle_Eb SANITY
when 160 =>
case OP3 is
when 0 => NEXT_OUTS <= 103; -- pushl_FS SANITY
when 1 => NEXT_OUTS <= 770; -- pushq_FS SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 161 =>
case OP3 is
when 0 => NEXT_OUTS <= 607; -- popl_FS SANITY
when 1 => NEXT_OUTS <= 571; -- popq_FS SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 162 => NEXT_OUTS <= 616; -- cpuid SANITY
when 163 => NEXT_OUTS <= 382; -- btl_Ed_Gd SANITY
when 164 => NEXT_OUTS <= 556; -- shldl_Ed_Gd_Ib SANITY
when 165 => NEXT_OUTS <= 617; -- shldl_Ed_Gd_CL SANITY
when 168 =>
case OP3 is
when 0 => NEXT_OUTS <= 442; -- pushl_GS SANITY
when 1 => NEXT_OUTS <= 160; -- pushq_GS SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 169 =>
case OP3 is
when 0 => NEXT_OUTS <= 543; -- popl_GS SANITY
when 1 => NEXT_OUTS <= 737; -- popq_GS SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 170 => NEXT_OUTS <= 65; -- rsm SANITY
when 171 => NEXT_OUTS <= 328; -- btsl_Ed_Gd SANITY
when 172 => NEXT_OUTS <= 341; -- shrdl_Ed_Gd_Ib SANITY
when 173 => NEXT_OUTS <= 253; -- shrdl_Ed_Gd_CL SANITY
when 175 => NEXT_OUTS <= 453; -- imull_Gd_Ed SANITY
when 176 => NEXT_OUTS <= 311; -- cmpxchgb_Eb_Gb SANITY
when 177 => NEXT_OUTS <= 769; -- cmpxchgl_Ed_Gd SANITY
when 178 => NEXT_OUTS <= 366; -- lssl_Gd_Mp SANITY
when 179 => NEXT_OUTS <= 189; -- btrl_Ed_Gd SANITY
when 180 => NEXT_OUTS <= 130; -- lfsl_Gd_Mp SANITY
when 181 => NEXT_OUTS <= 544; -- lgsl_Gd_Mp SANITY
when 182 => NEXT_OUTS <= 331; -- movzbl_Gd_Eb SANITY
when 183 => NEXT_OUTS <= 753; -- movzwl_Gd_Ew SANITY
when 185 =>
case OP3 is
when 0 => NEXT_OUTS <= 247; -- ud2b SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 186 =>
case OP3 is
when 32 => NEXT_OUTS <= 581; -- btl_Ed_Ib SANITY
when 40 => NEXT_OUTS <= 661; -- btsl_Ed_Ib SANITY
when 48 => NEXT_OUTS <= 761; -- btrl_Ed_Ib SANITY
when 56 => NEXT_OUTS <= 194; -- btcl_Ed_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 187 => NEXT_OUTS <= 745; -- btcl_Ed_Gd SANITY
when 190 => NEXT_OUTS <= 471; -- movsbl_Gd_Eb SANITY
when 191 => NEXT_OUTS <= 257; -- movswl_Gd_Ew SANITY
when 192 => NEXT_OUTS <= 303; -- xaddb_Eb_Gb SANITY
when 193 => NEXT_OUTS <= 727; -- xaddl_Ed_Gd SANITY
when 199 =>
case OP3 is
when 48 => NEXT_OUTS <= 344; -- vmptrld_Mq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 200 => NEXT_OUTS <= 142; -- bswapl_ERX SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 16 => NEXT_OUTS <= 174; -- adcb_Eb_Gb SANITY
when 17 => NEXT_OUTS <= 111; -- adcl_Ed_Gd SANITY
when 18 => NEXT_OUTS <= 13; -- adcb_Gb_Eb SANITY
when 19 => NEXT_OUTS <= 711; -- adcl_Gd_Ed SANITY
when 20 => NEXT_OUTS <= 292; -- adcb_AL_Ib SANITY
when 21 => NEXT_OUTS <= 512; -- adcl_EAX_Id SANITY
when 22 => NEXT_OUTS <= 70; -- pushl_SS SANITY
when 23 => NEXT_OUTS <= 504; -- popl_SS SANITY
when 24 => NEXT_OUTS <= 766; -- sbbb_Eb_Gb SANITY
when 25 => NEXT_OUTS <= 191; -- sbbl_Ed_Gd SANITY
when 26 => NEXT_OUTS <= 83; -- sbbb_Gb_Eb SANITY
when 27 => NEXT_OUTS <= 596; -- sbbl_Gd_Ed SANITY
when 28 => NEXT_OUTS <= 514; -- sbbb_AL_Ib SANITY
when 29 => NEXT_OUTS <= 95; -- sbbl_EAX_Id SANITY
when 30 => NEXT_OUTS <= 343; -- pushl_DS SANITY
when 31 => NEXT_OUTS <= 234; -- popl_DS SANITY
when 32 => NEXT_OUTS <= 261; -- andb_Eb_Gb SANITY
when 33 => NEXT_OUTS <= 340; -- andl_Ed_Gd SANITY
when 34 => NEXT_OUTS <= 251; -- andb_Gb_Eb SANITY
when 35 => NEXT_OUTS <= 699; -- andl_Gd_Ed SANITY
when 36 => NEXT_OUTS <= 300; -- andb_AL_Ib SANITY
when 37 => NEXT_OUTS <= 144; -- andl_EAX_Id SANITY
when 39 => NEXT_OUTS <= 491; -- daa SANITY
when 40 => NEXT_OUTS <= 176; -- subb_Eb_Gb SANITY
when 41 => NEXT_OUTS <= 478; -- subl_Ed_Gd SANITY
when 42 => NEXT_OUTS <= 428; -- subb_Gb_Eb SANITY
when 43 => NEXT_OUTS <= 204; -- subl_Gd_Ed SANITY
when 44 => NEXT_OUTS <= 738; -- subb_AL_Ib SANITY
when 45 => NEXT_OUTS <= 192; -- subl_EAX_Id SANITY
when 47 => NEXT_OUTS <= 115; -- das SANITY
when 48 => NEXT_OUTS <= 315; -- xorb_Eb_Gb SANITY
when 49 => NEXT_OUTS <= 511; -- xorl_Ed_Gd SANITY
when 50 => NEXT_OUTS <= 755; -- xorb_Gb_Eb SANITY
when 51 => NEXT_OUTS <= 488; -- xorl_Gd_Ed SANITY
when 52 => NEXT_OUTS <= 364; -- xorb_AL_Ib SANITY
when 53 => NEXT_OUTS <= 468; -- xorl_EAX_Id SANITY
when 55 => NEXT_OUTS <= 670; -- aaa SANITY
when 56 => NEXT_OUTS <= 725; -- cmpb_Eb_Gb SANITY
when 57 => NEXT_OUTS <= 410; -- cmpl_Ed_Gd SANITY
when 58 => NEXT_OUTS <= 23; -- cmpb_Gb_Eb SANITY
when 59 => NEXT_OUTS <= 461; -- cmpl_Gd_Ed SANITY
when 60 => NEXT_OUTS <= 262; -- cmpb_AL_Ib SANITY
when 61 => NEXT_OUTS <= 399; -- cmpl_EAX_Id SANITY
when 63 => NEXT_OUTS <= 615; -- aas SANITY
when 64 => NEXT_OUTS <= 499; -- incl_ERX SANITY
when 72 =>
case OP2 is
when 1 => NEXT_OUTS <= 730; -- addq_Eq_Gq SANITY
when 3 => NEXT_OUTS <= 258; -- addq_Gq_Eq SANITY
when 5 => NEXT_OUTS <= 179; -- addq_RAX_sId SANITY
when 9 => NEXT_OUTS <= 564; -- orq_Eq_Gq SANITY
when 11 => NEXT_OUTS <= 391; -- orq_Gq_Eq SANITY
when 13 => NEXT_OUTS <= 26; -- orq_RAX_sId SANITY
when 15 =>
case OP3 is
when 2 =>
case OP4 is
when 0 => NEXT_OUTS <= 712; -- larq_Gq_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 3 =>
case OP4 is
when 0 => NEXT_OUTS <= 362; -- lslq_Gq_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 110 => NEXT_OUTS <= 672; -- movq_Pq_Eq SANITY
when 163 => NEXT_OUTS <= 450; -- btq_Eq_Gq SANITY
when 164 => NEXT_OUTS <= 639; -- shldq_Eq_Gq_Ib SANITY
when 165 => NEXT_OUTS <= 609; -- shldq_Eq_Gq_CL SANITY
when 171 => NEXT_OUTS <= 305; -- btsq_Eq_Gq SANITY
when 172 => NEXT_OUTS <= 660; -- shrdq_Eq_Gq_Ib SANITY
when 173 => NEXT_OUTS <= 229; -- shrdq_Eq_Gq_CL SANITY
when 175 => NEXT_OUTS <= 69; -- imulq_Gq_Eq SANITY
when 177 => NEXT_OUTS <= 706; -- cmpxchgq_Eq_Gq SANITY
when 178 => NEXT_OUTS <= 625; -- lssq_Gq_Mp SANITY
when 179 => NEXT_OUTS <= 565; -- btrq_Eq_Gq SANITY
when 180 => NEXT_OUTS <= 688; -- lfsq_Gq_Mp SANITY
when 181 => NEXT_OUTS <= 197; -- lgsq_Gq_Mp SANITY
when 182 => NEXT_OUTS <= 689; -- movzbq_Gq_Eb SANITY
when 183 => NEXT_OUTS <= 566; -- movzwq_Gq_Ew SANITY
when 186 =>
case OP4 is
when 32 => NEXT_OUTS <= 259; -- btq_Eq_Ib SANITY
when 40 => NEXT_OUTS <= 697; -- btsq_Eq_Ib SANITY
when 48 => NEXT_OUTS <= 647; -- btrq_Eq_Ib SANITY
when 56 => NEXT_OUTS <= 190; -- btcq_Eq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 187 => NEXT_OUTS <= 441; -- btcq_Eq_Gq SANITY
when 190 => NEXT_OUTS <= 104; -- movsbq_Gq_Eb SANITY
when 191 => NEXT_OUTS <= 383; -- movswq_Gq_Ew SANITY
when 193 => NEXT_OUTS <= 9; -- xaddq_Eq_Gq SANITY
when 200 => NEXT_OUTS <= 120; -- bswapq_RRX SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 17 => NEXT_OUTS <= 551; -- adcq_Eq_Gq SANITY
when 19 => NEXT_OUTS <= 446; -- adcq_Gq_Eq SANITY
when 21 => NEXT_OUTS <= 535; -- adcq_RAX_sId SANITY
when 25 => NEXT_OUTS <= 506; -- sbbq_Eq_Gq SANITY
when 27 => NEXT_OUTS <= 765; -- sbbq_Gq_Eq SANITY
when 29 => NEXT_OUTS <= 181; -- sbbq_RAX_sId SANITY
when 33 => NEXT_OUTS <= 92; -- andq_Eq_Gq SANITY
when 35 => NEXT_OUTS <= 498; -- andq_Gq_Eq SANITY
when 37 => NEXT_OUTS <= 633; -- andq_RAX_sId SANITY
when 41 => NEXT_OUTS <= 323; -- subq_Eq_Gq SANITY
when 43 => NEXT_OUTS <= 734; -- subq_Gq_Eq SANITY
when 45 => NEXT_OUTS <= 696; -- subq_RAX_sId SANITY
when 49 => NEXT_OUTS <= 321; -- xorq_Eq_Gq SANITY
when 51 => NEXT_OUTS <= 508; -- xorq_Gq_Eq SANITY
when 53 => NEXT_OUTS <= 346; -- xorq_RAX_sId SANITY
when 57 => NEXT_OUTS <= 540; -- cmpq_Eq_Gq SANITY
when 59 => NEXT_OUTS <= 634; -- cmpq_Gq_Eq SANITY
when 61 => NEXT_OUTS <= 210; -- cmpq_RAX_sId SANITY
when 99 => NEXT_OUTS <= 7; -- movslq_Gq_Ed SANITY
when 105 => NEXT_OUTS <= 620; -- imulq_Gq_Eq_sId SANITY
when 107 => NEXT_OUTS <= 279; -- imulq_Gq_Eq_sIb SANITY
when 129 =>
case OP3 is
when 0 => NEXT_OUTS <= 49; -- addq_Eq_sId SANITY
when 8 => NEXT_OUTS <= 567; -- orq_Eq_sId SANITY
when 16 => NEXT_OUTS <= 357; -- adcq_Eq_sId SANITY
when 24 => NEXT_OUTS <= 173; -- sbbq_Eq_sId SANITY
when 32 => NEXT_OUTS <= 167; -- andq_Eq_sId SANITY
when 40 => NEXT_OUTS <= 427; -- subq_Eq_sId SANITY
when 48 => NEXT_OUTS <= 501; -- xorq_Eq_sId SANITY
when 56 => NEXT_OUTS <= 604; -- cmpq_Eq_sId SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 131 =>
case OP3 is
when 0 => NEXT_OUTS <= 99; -- addq_Eq_sIb SANITY
when 8 => NEXT_OUTS <= 22; -- orq_Eq_sIb SANITY
when 16 => NEXT_OUTS <= 637; -- adcq_Eq_sIb SANITY
when 24 => NEXT_OUTS <= 137; -- sbbq_Eq_sIb SANITY
when 32 => NEXT_OUTS <= 695; -- andq_Eq_sIb SANITY
when 40 => NEXT_OUTS <= 273; -- subq_Eq_sIb SANITY
when 48 => NEXT_OUTS <= 744; -- xorq_Eq_sIb SANITY
when 56 => NEXT_OUTS <= 339; -- cmpq_Eq_sIb SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 133 => NEXT_OUTS <= 153; -- testq_Eq_Gq SANITY
when 135 => NEXT_OUTS <= 559; -- xchgq_Eq_Gq SANITY
when 137 => NEXT_OUTS <= 208; -- movq_Eq_Gq SANITY
when 139 => NEXT_OUTS <= 81; -- movq_Gq_Eq SANITY
when 141 => NEXT_OUTS <= 610; -- leaq_Gq_Mq SANITY
when 145 => NEXT_OUTS <= 702; -- xchgq_RRX_RAX SANITY
when 152 => NEXT_OUTS <= 240; -- cdqe SANITY
when 153 => NEXT_OUTS <= 278; -- cqo SANITY
when 161 => NEXT_OUTS <= 175; -- movq_RAX_Oq SANITY
when 163 => NEXT_OUTS <= 437; -- movq_Oq_RAX SANITY
when 165 => NEXT_OUTS <= 55; -- movsq_Yq_Xq SANITY
when 167 => NEXT_OUTS <= 28; -- cmpsq_Yq_Xq SANITY
when 169 => NEXT_OUTS <= 578; -- testq_RAX_sId SANITY
when 171 => NEXT_OUTS <= 612; -- stosq_Yq_RAX SANITY
when 173 => NEXT_OUTS <= 282; -- lodsq_RAX_Xq SANITY
when 175 => NEXT_OUTS <= 576; -- scasq_Yq_RAX SANITY
when 184 => NEXT_OUTS <= 416; -- movq_RRX_Iq SANITY
when 193 =>
case OP3 is
when 0 => NEXT_OUTS <= 146; -- rolq_Eq_Ib SANITY
when 8 => NEXT_OUTS <= 613; -- rorq_Eq_Ib SANITY
when 16 => NEXT_OUTS <= 117; -- rclq_Eq_Ib SANITY
when 24 => NEXT_OUTS <= 611; -- rcrq_Eq_Ib SANITY
when 32 => NEXT_OUTS <= 631; -- shlq_Eq_Ib SANITY
when 40 => NEXT_OUTS <= 722; -- shrq_Eq_Ib SANITY
when 56 => NEXT_OUTS <= 242; -- sarq_Eq_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 199 =>
case OP3 is
when 0 => NEXT_OUTS <= 548; -- movq_Eq_sId SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 207 => NEXT_OUTS <= 557; -- iretq SANITY
when 209 =>
case OP3 is
when 0 => NEXT_OUTS <= 379; -- rolq_Eq_I1 SANITY
when 8 => NEXT_OUTS <= 538; -- rorq_Eq_I1 SANITY
when 16 => NEXT_OUTS <= 75; -- rclq_Eq_I1 SANITY
when 24 => NEXT_OUTS <= 763; -- rcrq_Eq_I1 SANITY
when 32 => NEXT_OUTS <= 721; -- shlq_Eq_I1 SANITY
when 40 => NEXT_OUTS <= 188; -- shrq_Eq_I1 SANITY
when 56 => NEXT_OUTS <= 58; -- sarq_Eq_I1 SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 211 =>
case OP3 is
when 0 => NEXT_OUTS <= 395; -- rolq_Eq_CL SANITY
when 8 => NEXT_OUTS <= 307; -- rorq_Eq_CL SANITY
when 16 => NEXT_OUTS <= 493; -- rclq_Eq_CL SANITY
when 24 => NEXT_OUTS <= 35; -- rcrq_Eq_CL SANITY
when 32 => NEXT_OUTS <= 11; -- shlq_Eq_CL SANITY
when 40 => NEXT_OUTS <= 363; -- shrq_Eq_CL SANITY
when 56 => NEXT_OUTS <= 627; -- sarq_Eq_CL SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 247 =>
case OP3 is
when 0 => NEXT_OUTS <= 32; -- testq_Eq_sId SANITY
when 16 => NEXT_OUTS <= 472; -- notq_Eq SANITY
when 24 => NEXT_OUTS <= 186; -- negq_Eq SANITY
when 32 => NEXT_OUTS <= 297; -- mulq_RAX_Eq SANITY
when 40 => NEXT_OUTS <= 196; -- imulq_RAX_Eq SANITY
when 48 => NEXT_OUTS <= 677; -- divq_RAX_Eq SANITY
when 56 => NEXT_OUTS <= 371; -- idivq_RAX_Eq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 255 =>
case OP3 is
when 0 => NEXT_OUTS <= 350; -- incq_Eq SANITY
when 8 => NEXT_OUTS <= 48; -- decq_Eq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 80 =>
case OP2 is
when 0 => NEXT_OUTS <= 445; -- pushl_ERX SANITY
when 1 => NEXT_OUTS <= 520; -- pushq_RRX SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 88 =>
case OP2 is
when 0 => NEXT_OUTS <= 47; -- popl_ERX SANITY
when 1 => NEXT_OUTS <= 529; -- popq_RRX SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 96 => NEXT_OUTS <= 271; -- pushal SANITY
when 97 => NEXT_OUTS <= 479; -- popal SANITY
when 98 => NEXT_OUTS <= 569; -- boundl_Gd_Ma SANITY
when 99 => NEXT_OUTS <= 89; -- arpl_Ew_Gw SANITY
when 102 =>
case OP2 is
when 1 =>
case OP3 is
when 0 => NEXT_OUTS <= 57; -- addw_Ew_Gw SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 3 => NEXT_OUTS <= 325; -- addw_Gw_Ew SANITY
when 5 => NEXT_OUTS <= 361; -- addw_AX_Iw SANITY
when 6 => NEXT_OUTS <= 30; -- pushw_ES SANITY
when 7 => NEXT_OUTS <= 330; -- popw_ES SANITY
when 9 => NEXT_OUTS <= 8; -- orw_Ew_Gw SANITY
when 11 => NEXT_OUTS <= 349; -- orw_Gw_Ew SANITY
when 13 => NEXT_OUTS <= 494; -- orw_AX_Iw SANITY
when 14 => NEXT_OUTS <= 484; -- pushw_CS SANITY
when 15 =>
case OP3 is
when 2 =>
case OP4 is
when 0 => NEXT_OUTS <= 674; -- larw_Gw_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 3 =>
case OP4 is
when 0 => NEXT_OUTS <= 380; -- lslw_Gw_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 110 => NEXT_OUTS <= 61; -- movd_Vdq_Ed SANITY
when 128 => NEXT_OUTS <= 648; -- jo_Jw SANITY
when 129 => NEXT_OUTS <= 754; -- jno_Jw SANITY
when 130 => NEXT_OUTS <= 79; -- jb_Jw SANITY
when 131 => NEXT_OUTS <= 155; -- jnb_Jw SANITY
when 132 => NEXT_OUTS <= 77; -- jz_Jw SANITY
when 133 => NEXT_OUTS <= 345; -- jnz_Jw SANITY
when 134 => NEXT_OUTS <= 768; -- jbe_Jw SANITY
when 135 => NEXT_OUTS <= 96; -- jnbe_Jw SANITY
when 136 => NEXT_OUTS <= 263; -- js_Jw SANITY
when 137 => NEXT_OUTS <= 642; -- jns_Jw SANITY
when 138 => NEXT_OUTS <= 2; -- jp_Jw SANITY
when 139 => NEXT_OUTS <= 662; -- jnp_Jw SANITY
when 140 => NEXT_OUTS <= 394; -- jl_Jw SANITY
when 141 => NEXT_OUTS <= 274; -- jnl_Jw SANITY
when 142 => NEXT_OUTS <= 653; -- jle_Jw SANITY
when 143 => NEXT_OUTS <= 38; -- jnle_Jw SANITY
when 160 => NEXT_OUTS <= 470; -- pushw_FS SANITY
when 161 => NEXT_OUTS <= 751; -- popw_FS SANITY
when 163 => NEXT_OUTS <= 421; -- btw_Ew_Gw SANITY
when 164 => NEXT_OUTS <= 46; -- shldw_Ew_Gw_Ib SANITY
when 165 => NEXT_OUTS <= 778; -- shldw_Ew_Gw_CL SANITY
when 168 => NEXT_OUTS <= 693; -- pushw_GS SANITY
when 169 => NEXT_OUTS <= 570; -- popw_GS SANITY
when 171 => NEXT_OUTS <= 657; -- btsw_Ew_Gw SANITY
when 172 => NEXT_OUTS <= 458; -- shrdw_Ew_Gw_Ib SANITY
when 173 => NEXT_OUTS <= 376; -- shrdw_Ew_Gw_CL SANITY
when 175 => NEXT_OUTS <= 684; -- imulw_Gw_Ew SANITY
when 177 => NEXT_OUTS <= 54; -- cmpxchgw_Ew_Gw SANITY
when 178 => NEXT_OUTS <= 64; -- lssw_Gw_Mp SANITY
when 179 => NEXT_OUTS <= 332; -- btrw_Ew_Gw SANITY
when 180 => NEXT_OUTS <= 17; -- lfsw_Gw_Mp SANITY
when 181 => NEXT_OUTS <= 308; -- lgsw_Gw_Mp SANITY
when 182 => NEXT_OUTS <= 589; -- movzbw_Gw_Eb SANITY
when 186 =>
case OP4 is
when 32 => NEXT_OUTS <= 418; -- btw_Ew_Ib SANITY
when 40 => NEXT_OUTS <= 533; -- btsw_Ew_Ib SANITY
when 48 => NEXT_OUTS <= 269; -- btrw_Ew_Ib SANITY
when 56 => NEXT_OUTS <= 438; -- btcw_Ew_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 187 => NEXT_OUTS <= 80; -- btcw_Ew_Gw SANITY
when 190 => NEXT_OUTS <= 106; -- movsbw_Gw_Eb SANITY
when 193 => NEXT_OUTS <= 526; -- xaddw_Ew_Gw SANITY
when 199 =>
case OP4 is
when 48 => NEXT_OUTS <= 420; -- vmclear_Mq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 17 => NEXT_OUTS <= 43; -- adcw_Ew_Gw SANITY
when 19 => NEXT_OUTS <= 469; -- adcw_Gw_Ew SANITY
when 21 => NEXT_OUTS <= 593; -- adcw_AX_Iw SANITY
when 22 => NEXT_OUTS <= 370; -- pushw_SS SANITY
when 23 => NEXT_OUTS <= 294; -- popw_SS SANITY
when 25 => NEXT_OUTS <= 715; -- sbbw_Ew_Gw SANITY
when 27 => NEXT_OUTS <= 217; -- sbbw_Gw_Ew SANITY
when 29 => NEXT_OUTS <= 655; -- sbbw_AX_Iw SANITY
when 30 => NEXT_OUTS <= 646; -- pushw_DS SANITY
when 31 => NEXT_OUTS <= 123; -- popw_DS SANITY
when 33 => NEXT_OUTS <= 496; -- andw_Ew_Gw SANITY
when 35 => NEXT_OUTS <= 203; -- andw_Gw_Ew SANITY
when 37 => NEXT_OUTS <= 523; -- andw_AX_Iw SANITY
when 41 => NEXT_OUTS <= 118; -- subw_Ew_Gw SANITY
when 43 => NEXT_OUTS <= 760; -- subw_Gw_Ew SANITY
when 45 => NEXT_OUTS <= 87; -- subw_AX_Iw SANITY
when 49 => NEXT_OUTS <= 280; -- xorw_Ew_Gw SANITY
when 51 => NEXT_OUTS <= 337; -- xorw_Gw_Ew SANITY
when 53 => NEXT_OUTS <= 654; -- xorw_AX_Iw SANITY
when 57 => NEXT_OUTS <= 705; -- cmpw_Ew_Gw SANITY
when 59 => NEXT_OUTS <= 31; -- cmpw_Gw_Ew SANITY
when 61 => NEXT_OUTS <= 86; -- cmpw_AX_Iw SANITY
when 64 => NEXT_OUTS <= 460; -- incw_RX SANITY
when 72 =>
case OP3 is
when 15 =>
case OP4 is
when 110 => NEXT_OUTS <= 177; -- movq_Vdq_Eq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 80 => NEXT_OUTS <= 172; -- pushw_RX SANITY
when 88 => NEXT_OUTS <= 510; -- popw_RX SANITY
when 96 => NEXT_OUTS <= 390; -- pushaw SANITY
when 97 => NEXT_OUTS <= 632; -- popaw SANITY
when 98 => NEXT_OUTS <= 386; -- boundw_Gw_Ma SANITY
when 104 => NEXT_OUTS <= 162; -- pushw_Iw SANITY
when 105 => NEXT_OUTS <= 541; -- imulw_Gw_Ew_Iw SANITY
when 106 => NEXT_OUTS <= 481; -- pushw_sIb SANITY
when 107 => NEXT_OUTS <= 411; -- imulw_Gw_Ew_sIb SANITY
when 109 => NEXT_OUTS <= 597; -- insw_Yw_DX SANITY
when 111 => NEXT_OUTS <= 214; -- outsw_DX_Xw SANITY
when 129 =>
case OP3 is
when 0 => NEXT_OUTS <= 550; -- addw_Ew_Iw SANITY
when 8 => NEXT_OUTS <= 641; -- orw_Ew_Iw SANITY
when 16 => NEXT_OUTS <= 246; -- adcw_Ew_Iw SANITY
when 24 => NEXT_OUTS <= 101; -- sbbw_Ew_Iw SANITY
when 32 => NEXT_OUTS <= 110; -- andw_Ew_Iw SANITY
when 40 => NEXT_OUTS <= 423; -- subw_Ew_Iw SANITY
when 48 => NEXT_OUTS <= 663; -- xorw_Ew_Iw SANITY
when 56 => NEXT_OUTS <= 772; -- cmpw_Ew_Iw SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 131 =>
case OP3 is
when 0 => NEXT_OUTS <= 327; -- addw_Ew_sIb SANITY
when 8 => NEXT_OUTS <= 476; -- orw_Ew_sIb SANITY
when 16 => NEXT_OUTS <= 93; -- adcw_Ew_sIb SANITY
when 24 => NEXT_OUTS <= 129; -- sbbw_Ew_sIb SANITY
when 32 => NEXT_OUTS <= 694; -- andw_Ew_sIb SANITY
when 40 => NEXT_OUTS <= 127; -- subw_Ew_sIb SANITY
when 48 => NEXT_OUTS <= 717; -- xorw_Ew_sIb SANITY
when 56 => NEXT_OUTS <= 141; -- cmpw_Ew_sIb SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 133 => NEXT_OUTS <= 206; -- testw_Ew_Gw SANITY
when 135 => NEXT_OUTS <= 726; -- xchgw_Ew_Gw SANITY
when 137 => NEXT_OUTS <= 773; -- movw_Ew_Gw SANITY
when 139 => NEXT_OUTS <= 582; -- movw_Gw_Ew SANITY
when 141 => NEXT_OUTS <= 723; -- leaw_Gw_Mw SANITY
when 143 =>
case OP3 is
when 0 => NEXT_OUTS <= 762; -- popw_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 145 => NEXT_OUTS <= 682; -- xchgw_RX_AX SANITY
when 152 => NEXT_OUTS <= 298; -- cbw SANITY
when 153 => NEXT_OUTS <= 482; -- cwd SANITY
when 154 => NEXT_OUTS <= 434; -- lcall_Apw SANITY
when 156 => NEXT_OUTS <= 329; -- pushfw SANITY
when 157 => NEXT_OUTS <= 758; -- popfw SANITY
when 161 => NEXT_OUTS <= 125; -- movw_AX_Ow SANITY
when 163 => NEXT_OUTS <= 309; -- movw_Ow_AX SANITY
when 165 => NEXT_OUTS <= 352; -- movsw_Yw_Xw SANITY
when 167 => NEXT_OUTS <= 629; -- cmpsw_Yw_Xw SANITY
when 169 => NEXT_OUTS <= 749; -- testw_AX_Iw SANITY
when 171 => NEXT_OUTS <= 287; -- stosw_Yw_AX SANITY
when 173 => NEXT_OUTS <= 320; -- lodsw_AX_Xw SANITY
when 175 => NEXT_OUTS <= 739; -- scasw_Yw_AX SANITY
when 184 => NEXT_OUTS <= 690; -- movw_RX_Iw SANITY
when 193 =>
case OP3 is
when 0 => NEXT_OUTS <= 105; -- rolw_Ew_Ib SANITY
when 8 => NEXT_OUTS <= 741; -- rorw_Ew_Ib SANITY
when 16 => NEXT_OUTS <= 248; -- rclw_Ew_Ib SANITY
when 24 => NEXT_OUTS <= 603; -- rcrw_Ew_Ib SANITY
when 32 => NEXT_OUTS <= 626; -- shlw_Ew_Ib SANITY
when 40 => NEXT_OUTS <= 554; -- shrw_Ew_Ib SANITY
when 56 => NEXT_OUTS <= 668; -- sarw_Ew_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 196 => NEXT_OUTS <= 467; -- lesw_Gw_Mp SANITY
when 199 =>
case OP3 is
when 0 => NEXT_OUTS <= 353; -- movw_Ew_Iw SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 207 => NEXT_OUTS <= 720; -- iretw SANITY
when 209 =>
case OP3 is
when 0 => NEXT_OUTS <= 584; -- rolw_Ew_I1 SANITY
when 8 => NEXT_OUTS <= 740; -- rorw_Ew_I1 SANITY
when 16 => NEXT_OUTS <= 360; -- rclw_Ew_I1 SANITY
when 24 => NEXT_OUTS <= 628; -- rcrw_Ew_I1 SANITY
when 32 => NEXT_OUTS <= 195; -- shlw_Ew_I1 SANITY
when 40 => NEXT_OUTS <= 169; -- shrw_Ew_I1 SANITY
when 56 => NEXT_OUTS <= 226; -- sarw_Ew_I1 SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 211 =>
case OP3 is
when 0 => NEXT_OUTS <= 579; -- rolw_Ew_CL SANITY
when 8 => NEXT_OUTS <= 709; -- rorw_Ew_CL SANITY
when 16 => NEXT_OUTS <= 387; -- rclw_Ew_CL SANITY
when 24 => NEXT_OUTS <= 396; -- rcrw_Ew_CL SANITY
when 32 => NEXT_OUTS <= 97; -- shlw_Ew_CL SANITY
when 40 => NEXT_OUTS <= 686; -- shrw_Ew_CL SANITY
when 56 => NEXT_OUTS <= 29; -- sarw_Ew_CL SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 229 => NEXT_OUTS <= 466; -- inw_AX_Ib SANITY
when 231 => NEXT_OUTS <= 780; -- outw_Ib_AX SANITY
when 232 => NEXT_OUTS <= 473; -- call_Jw SANITY
when 233 => NEXT_OUTS <= 746; -- jmp_Jw SANITY
when 234 => NEXT_OUTS <= 384; -- ljmp_Apw SANITY
when 237 => NEXT_OUTS <= 724; -- inw_AX_DX SANITY
when 239 => NEXT_OUTS <= 200; -- outw_DX_AX SANITY
when 247 =>
case OP3 is
when 0 => NEXT_OUTS <= 542; -- testw_Ew_Iw SANITY
when 16 => NEXT_OUTS <= 265; -- notw_Ew SANITY
when 24 => NEXT_OUTS <= 122; -- negw_Ew SANITY
when 32 => NEXT_OUTS <= 651; -- mulw_AX_Ew SANITY
when 40 => NEXT_OUTS <= 767; -- imulw_AX_Ew SANITY
when 48 => NEXT_OUTS <= 281; -- divw_AX_Ew SANITY
when 56 => NEXT_OUTS <= 245; -- idivw_AX_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 255 =>
case OP3 is
when 0 => NEXT_OUTS <= 776; -- incw_Ew SANITY
when 8 => NEXT_OUTS <= 656; -- decw_Ew SANITY
when 16 => NEXT_OUTS <= 398; -- call_Ew SANITY
when 32 => NEXT_OUTS <= 193; -- jmp_Ew SANITY
when 48 => NEXT_OUTS <= 52; -- pushw_Ew SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 103 =>
case OP2 is
when 227 => NEXT_OUTS <= 748; -- jcxz_Jb SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 104 =>
case OP2 is
when 0 => NEXT_OUTS <= 464; -- pushl_Id SANITY
when 1 => NEXT_OUTS <= 277; -- pushq_sId SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 105 => NEXT_OUTS <= 701; -- imull_Gd_Ed_Id SANITY
when 106 =>
case OP2 is
when 0 => NEXT_OUTS <= 536; -- pushl_sIb SANITY
when 1 => NEXT_OUTS <= 562; -- pushq_sIb SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 107 => NEXT_OUTS <= 719; -- imull_Gd_Ed_sIb SANITY
when 108 => NEXT_OUTS <= 310; -- insb_Yb_DX SANITY
when 109 => NEXT_OUTS <= 205; -- insl_Yd_DX SANITY
when 110 => NEXT_OUTS <= 6; -- outsb_DX_Xb SANITY
when 111 => NEXT_OUTS <= 594; -- outsl_DX_Xd SANITY
when 112 => NEXT_OUTS <= 665; -- jo_Jb SANITY
when 113 => NEXT_OUTS <= 354; -- jno_Jb SANITY
when 114 => NEXT_OUTS <= 185; -- jb_Jb SANITY
when 115 => NEXT_OUTS <= 643; -- jnb_Jb SANITY
when 116 => NEXT_OUTS <= 157; -- jz_Jb SANITY
when 117 => NEXT_OUTS <= 591; -- jnz_Jb SANITY
when 118 => NEXT_OUTS <= 165; -- jbe_Jb SANITY
when 119 => NEXT_OUTS <= 314; -- jnbe_Jb SANITY
when 120 => NEXT_OUTS <= 232; -- js_Jb SANITY
when 121 => NEXT_OUTS <= 102; -- jns_Jb SANITY
when 122 => NEXT_OUTS <= 462; -- jp_Jb SANITY
when 123 => NEXT_OUTS <= 88; -- jnp_Jb SANITY
when 124 => NEXT_OUTS <= 517; -- jl_Jb SANITY
when 125 => NEXT_OUTS <= 490; -- jnl_Jb SANITY
when 126 => NEXT_OUTS <= 522; -- jle_Jb SANITY
when 127 => NEXT_OUTS <= 72; -- jnle_Jb SANITY
when 128 =>
case OP2 is
when 0 => NEXT_OUTS <= 351; -- addb_Eb_Ib SANITY
when 8 => NEXT_OUTS <= 116; -- orb_Eb_Ib SANITY
when 16 => NEXT_OUTS <= 691; -- adcb_Eb_Ib SANITY
when 24 => NEXT_OUTS <= 507; -- sbbb_Eb_Ib SANITY
when 32 => NEXT_OUTS <= 704; -- andb_Eb_Ib SANITY
when 40 => NEXT_OUTS <= 150; -- subb_Eb_Ib SANITY
when 48 => NEXT_OUTS <= 521; -- xorb_Eb_Ib SANITY
when 56 => NEXT_OUTS <= 219; -- cmpb_Eb_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 129 =>
case OP2 is
when 0 => NEXT_OUTS <= 454; -- addl_Ed_Id SANITY
when 8 => NEXT_OUTS <= 243; -- orl_Ed_Id SANITY
when 16 => NEXT_OUTS <= 728; -- adcl_Ed_Id SANITY
when 24 => NEXT_OUTS <= 199; -- sbbl_Ed_Id SANITY
when 32 => NEXT_OUTS <= 223; -- andl_Ed_Id SANITY
when 40 => NEXT_OUTS <= 714; -- subl_Ed_Id SANITY
when 48 => NEXT_OUTS <= 42; -- xorl_Ed_Id SANITY
when 56 => NEXT_OUTS <= 285; -- cmpl_Ed_Id SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 131 =>
case OP2 is
when 0 => NEXT_OUTS <= 45; -- addl_Ed_sIb SANITY
when 8 => NEXT_OUTS <= 266; -- orl_Ed_sIb SANITY
when 16 => NEXT_OUTS <= 334; -- adcl_Ed_sIb SANITY
when 24 => NEXT_OUTS <= 401; -- sbbl_Ed_sIb SANITY
when 32 => NEXT_OUTS <= 59; -- andl_Ed_sIb SANITY
when 40 => NEXT_OUTS <= 549; -- subl_Ed_sIb SANITY
when 48 => NEXT_OUTS <= 422; -- xorl_Ed_sIb SANITY
when 56 => NEXT_OUTS <= 109; -- cmpl_Ed_sIb SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 132 => NEXT_OUTS <= 614; -- testb_Eb_Gb SANITY
when 133 => NEXT_OUTS <= 700; -- testl_Ed_Gd SANITY
when 134 => NEXT_OUTS <= 623; -- xchgb_Eb_Gb SANITY
when 135 => NEXT_OUTS <= 553; -- xchgl_Ed_Gd SANITY
when 136 => NEXT_OUTS <= 255; -- movb_Eb_Gb SANITY
when 137 => NEXT_OUTS <= 166; -- movl_Ed_Gd SANITY
when 138 => NEXT_OUTS <= 598; -- movb_Gb_Eb SANITY
when 139 => NEXT_OUTS <= 752; -- movl_Gd_Ed SANITY
when 140 => NEXT_OUTS <= 348; -- movw_Ew_Sw SANITY
when 141 => NEXT_OUTS <= 326; -- leal_Gd_Md SANITY
when 142 => NEXT_OUTS <= 231; -- movw_Sw_Ew SANITY
when 143 =>
case OP2 is
when 0 =>
case OP3 is
when 0 => NEXT_OUTS <= 707; -- popl_Ed SANITY
when 1 => NEXT_OUTS <= 635; -- popq_Eq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 144 => NEXT_OUTS <= 601; -- nop SANITY
when 145 => NEXT_OUTS <= 640; -- xchgl_ERX_EAX SANITY
when 152 => NEXT_OUTS <= 750; -- cwde SANITY
when 153 => NEXT_OUTS <= 666; -- cdq SANITY
when 154 => NEXT_OUTS <= 413; -- lcall_Apd SANITY
when 155 => NEXT_OUTS <= 85; -- fwait SANITY
when 156 =>
case OP2 is
when 0 => NEXT_OUTS <= 685; -- pushfl SANITY
when 1 => NEXT_OUTS <= 392; -- pushfq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 157 =>
case OP2 is
when 0 => NEXT_OUTS <= 44; -- popfl SANITY
when 1 => NEXT_OUTS <= 393; -- popfq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 158 => NEXT_OUTS <= 183; -- sahf SANITY
when 159 => NEXT_OUTS <= 151; -- lahf SANITY
when 160 => NEXT_OUTS <= 244; -- movb_AL_Ob SANITY
when 161 => NEXT_OUTS <= 537; -- movl_EAX_Od SANITY
when 162 => NEXT_OUTS <= 531; -- movb_Ob_AL SANITY
when 163 => NEXT_OUTS <= 764; -- movl_Od_EAX SANITY
when 164 => NEXT_OUTS <= 149; -- movsb_Yb_Xb SANITY
when 165 => NEXT_OUTS <= 5; -- movsl_Yd_Xd SANITY
when 166 => NEXT_OUTS <= 703; -- cmpsb_Yb_Xb SANITY
when 167 => NEXT_OUTS <= 126; -- cmpsl_Yd_Xd SANITY
when 168 => NEXT_OUTS <= 187; -- testb_AL_Ib SANITY
when 169 => NEXT_OUTS <= 534; -- testl_EAX_Id SANITY
when 170 => NEXT_OUTS <= 687; -- stosb_Yb_AL SANITY
when 171 => NEXT_OUTS <= 249; -- stosl_Yd_EAX SANITY
when 172 => NEXT_OUTS <= 291; -- lodsb_AL_Xb SANITY
when 173 => NEXT_OUTS <= 622; -- lodsl_EAX_Xd SANITY
when 174 => NEXT_OUTS <= 546; -- scasb_Yb_AL SANITY
when 175 => NEXT_OUTS <= 775; -- scasl_Yd_EAX SANITY
when 176 => NEXT_OUTS <= 213; -- movb_R8_Ib SANITY
when 184 => NEXT_OUTS <= 107; -- movl_ERX_Id SANITY
when 192 =>
case OP2 is
when 0 => NEXT_OUTS <= 736; -- rolb_Eb_Ib SANITY
when 8 => NEXT_OUTS <= 756; -- rorb_Eb_Ib SANITY
when 16 => NEXT_OUTS <= 216; -- rclb_Eb_Ib SANITY
when 24 => NEXT_OUTS <= 302; -- rcrb_Eb_Ib SANITY
when 32 => NEXT_OUTS <= 532; -- shlb_Eb_Ib SANITY
when 40 => NEXT_OUTS <= 286; -- shrb_Eb_Ib SANITY
when 56 => NEXT_OUTS <= 73; -- sarb_Eb_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 193 =>
case OP2 is
when 0 => NEXT_OUTS <= 164; -- roll_Ed_Ib SANITY
when 8 => NEXT_OUTS <= 527; -- rorl_Ed_Ib SANITY
when 16 => NEXT_OUTS <= 449; -- rcll_Ed_Ib SANITY
when 24 => NEXT_OUTS <= 742; -- rcrl_Ed_Ib SANITY
when 32 => NEXT_OUTS <= 435; -- shll_Ed_Ib SANITY
when 40 => NEXT_OUTS <= 680; -- shrl_Ed_Ib SANITY
when 56 => NEXT_OUTS <= 36; -- sarl_Ed_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 194 => NEXT_OUTS <= 563; -- ret_Iw SANITY
when 195 => NEXT_OUTS <= 552; -- ret SANITY
when 196 =>
case OP2 is
when 0 => NEXT_OUTS <= 228; -- lesl_Gd_Mp SANITY
when 225 =>
case OP3 is
when 249 =>
case OP4 is
when 110 => NEXT_OUTS <= 338; -- vmovq_Vdq_Eq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 226 =>
case OP3 is
when 121 =>
case OP4 is
when 19 => NEXT_OUTS <= 595; -- vcvtph2ps_Vps_Wq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 227 =>
case OP3 is
when 121 =>
case OP4 is
when 29 => NEXT_OUTS <= 94; -- vcvtps2ph_Wq_Vps_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 197 =>
case OP2 is
when 249 =>
case OP3 is
when 110 => NEXT_OUTS <= 367; -- vmovd_Vdq_Ed SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 198 =>
case OP2 is
when 0 => NEXT_OUTS <= 140; -- movb_Eb_Ib SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 199 =>
case OP2 is
when 0 => NEXT_OUTS <= 649; -- movl_Ed_Id SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 200 => NEXT_OUTS <= 66; -- enter SANITY
when 201 => NEXT_OUTS <= 779; -- leave SANITY
when 202 => NEXT_OUTS <= 136; -- lret_Iw SANITY
when 203 => NEXT_OUTS <= 252; -- lret SANITY
when 204 => NEXT_OUTS <= 447; -- int3 SANITY
when 205 => NEXT_OUTS <= 56; -- int_Ib SANITY
when 206 => NEXT_OUTS <= 128; -- into SANITY
when 207 => NEXT_OUTS <= 268; -- iretl SANITY
when 208 =>
case OP2 is
when 0 => NEXT_OUTS <= 19; -- rolb_Eb_I1 SANITY
when 8 => NEXT_OUTS <= 152; -- rorb_Eb_I1 SANITY
when 16 => NEXT_OUTS <= 90; -- rclb_Eb_I1 SANITY
when 24 => NEXT_OUTS <= 605; -- rcrb_Eb_I1 SANITY
when 32 => NEXT_OUTS <= 774; -- shlb_Eb_I1 SANITY
when 40 => NEXT_OUTS <= 606; -- shrb_Eb_I1 SANITY
when 56 => NEXT_OUTS <= 516; -- sarb_Eb_I1 SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 209 =>
case OP2 is
when 0 => NEXT_OUTS <= 290; -- roll_Ed_I1 SANITY
when 8 => NEXT_OUTS <= 209; -- rorl_Ed_I1 SANITY
when 16 => NEXT_OUTS <= 414; -- rcll_Ed_I1 SANITY
when 24 => NEXT_OUTS <= 524; -- rcrl_Ed_I1 SANITY
when 32 => NEXT_OUTS <= 530; -- shll_Ed_I1 SANITY
when 40 => NEXT_OUTS <= 436; -- shrl_Ed_I1 SANITY
when 56 => NEXT_OUTS <= 440; -- sarl_Ed_I1 SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 210 =>
case OP2 is
when 0 => NEXT_OUTS <= 236; -- rolb_Eb_CL SANITY
when 8 => NEXT_OUTS <= 221; -- rorb_Eb_CL SANITY
when 16 => NEXT_OUTS <= 4; -- rclb_Eb_CL SANITY
when 24 => NEXT_OUTS <= 132; -- rcrb_Eb_CL SANITY
when 32 => NEXT_OUTS <= 406; -- shlb_Eb_CL SANITY
when 40 => NEXT_OUTS <= 198; -- shrb_Eb_CL SANITY
when 56 => NEXT_OUTS <= 519; -- sarb_Eb_CL SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 211 =>
case OP2 is
when 0 => NEXT_OUTS <= 51; -- roll_Ed_CL SANITY
when 8 => NEXT_OUTS <= 509; -- rorl_Ed_CL SANITY
when 16 => NEXT_OUTS <= 76; -- rcll_Ed_CL SANITY
when 24 => NEXT_OUTS <= 608; -- rcrl_Ed_CL SANITY
when 32 => NEXT_OUTS <= 785; -- shll_Ed_CL SANITY
when 40 => NEXT_OUTS <= 18; -- shrl_Ed_CL SANITY
when 56 => NEXT_OUTS <= 33; -- sarl_Ed_CL SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 212 => NEXT_OUTS <= 135; -- aam SANITY
when 213 => NEXT_OUTS <= 572; -- aad SANITY
when 214 => NEXT_OUTS <= 777; -- salc SANITY
when 215 => NEXT_OUTS <= 368; -- xlat SANITY
when 216 =>
case OP2 is
when 0 => NEXT_OUTS <= 372; -- fadds_Md SANITY
when 8 => NEXT_OUTS <= 645; -- fmuls_Md SANITY
when 16 => NEXT_OUTS <= 515; -- fcoms_Md SANITY
when 24 => NEXT_OUTS <= 716; -- fcomps_Md SANITY
when 32 => NEXT_OUTS <= 342; -- fsubs_Md SANITY
when 40 => NEXT_OUTS <= 430; -- fsubrs_Md SANITY
when 48 => NEXT_OUTS <= 419; -- fdivs_Md SANITY
when 56 => NEXT_OUTS <= 335; -- fdivrs_Md SANITY
when 192 => NEXT_OUTS <= 483; -- fadd_ST0_STi SANITY
when 200 => NEXT_OUTS <= 264; -- fmul_ST0_STi SANITY
when 208 => NEXT_OUTS <= 698; -- fcom_STi SANITY
when 216 => NEXT_OUTS <= 784; -- fcomp_STi SANITY
when 224 => NEXT_OUTS <= 316; -- fsub_ST0_STi SANITY
when 232 => NEXT_OUTS <= 375; -- fsubr_ST0_STi SANITY
when 240 => NEXT_OUTS <= 131; -- fdiv_ST0_STi SANITY
when 248 => NEXT_OUTS <= 60; -- fdivr_ST0_STi SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 217 =>
case OP2 is
when 0 => NEXT_OUTS <= 735; -- flds_Md SANITY
when 16 => NEXT_OUTS <= 658; -- fsts_Md SANITY
when 24 => NEXT_OUTS <= 588; -- fstps_Md SANITY
when 32 => NEXT_OUTS <= 417; -- fldenv SANITY
when 40 => NEXT_OUTS <= 545; -- fldcw SANITY
when 48 => NEXT_OUTS <= 602; -- fnstenv SANITY
when 56 => NEXT_OUTS <= 254; -- fnstcw SANITY
when 192 => NEXT_OUTS <= 91; -- fld_STi SANITY
when 200 => NEXT_OUTS <= 27; -- fxch SANITY
when 208 => NEXT_OUTS <= 53; -- fnop SANITY
when 224 => NEXT_OUTS <= 134; -- fchs SANITY
when 225 => NEXT_OUTS <= 783; -- fabs SANITY
when 228 => NEXT_OUTS <= 539; -- ftst SANITY
when 229 => NEXT_OUTS <= 426; -- fxam SANITY
when 232 => NEXT_OUTS <= 299; -- fld1 SANITY
when 233 => NEXT_OUTS <= 16; -- fldl2t SANITY
when 234 => NEXT_OUTS <= 678; -- fldl2e SANITY
when 235 => NEXT_OUTS <= 650; -- fldpi SANITY
when 236 => NEXT_OUTS <= 431; -- fldlg2 SANITY
when 237 => NEXT_OUTS <= 585; -- fldln2 SANITY
when 238 => NEXT_OUTS <= 25; -- fldz SANITY
when 240 => NEXT_OUTS <= 170; -- f2xm1 SANITY
when 241 => NEXT_OUTS <= 211; -- fyl2x SANITY
when 242 => NEXT_OUTS <= 397; -- fptan SANITY
when 243 => NEXT_OUTS <= 288; -- fpatan SANITY
when 244 => NEXT_OUTS <= 621; -- fxtract SANITY
when 245 => NEXT_OUTS <= 306; -- fprem1 SANITY
when 246 => NEXT_OUTS <= 486; -- fdecstp SANITY
when 247 => NEXT_OUTS <= 525; -- fincstp SANITY
when 248 => NEXT_OUTS <= 586; -- fprem SANITY
when 249 => NEXT_OUTS <= 68; -- fyl2xp1 SANITY
when 250 => NEXT_OUTS <= 71; -- fsqrt SANITY
when 251 => NEXT_OUTS <= 402; -- fsincos SANITY
when 252 => NEXT_OUTS <= 224; -- frndint SANITY
when 253 => NEXT_OUTS <= 373; -- fscale SANITY
when 254 => NEXT_OUTS <= 439; -- fsin SANITY
when 255 => NEXT_OUTS <= 272; -- fcos SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 218 =>
case OP2 is
when 0 => NEXT_OUTS <= 276; -- fiaddl_Md SANITY
when 8 => NEXT_OUTS <= 444; -- fimull_Md SANITY
when 16 => NEXT_OUTS <= 673; -- ficoml_Md SANITY
when 24 => NEXT_OUTS <= 82; -- ficompl_Md SANITY
when 32 => NEXT_OUTS <= 747; -- fisubl_Md SANITY
when 40 => NEXT_OUTS <= 270; -- fisubrl_Md SANITY
when 48 => NEXT_OUTS <= 577; -- fidivl_Md SANITY
when 56 => NEXT_OUTS <= 359; -- fidivrl_Md SANITY
when 233 => NEXT_OUTS <= 34; -- fucompp SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 219 =>
case OP2 is
when 0 => NEXT_OUTS <= 492; -- fildl_Md SANITY
when 16 => NEXT_OUTS <= 112; -- fistl_Md SANITY
when 24 => NEXT_OUTS <= 40; -- fistpl_Md SANITY
when 40 => NEXT_OUTS <= 400; -- fldt_Mt SANITY
when 56 => NEXT_OUTS <= 407; -- fstpt_Mt SANITY
when 226 => NEXT_OUTS <= 388; -- fnclex SANITY
when 227 => NEXT_OUTS <= 681; -- fninit SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 220 =>
case OP2 is
when 0 => NEXT_OUTS <= 138; -- faddl_Mq SANITY
when 8 => NEXT_OUTS <= 369; -- fmull_Mq SANITY
when 16 => NEXT_OUTS <= 463; -- fcoml_Mq SANITY
when 24 => NEXT_OUTS <= 600; -- fcompl_Mq SANITY
when 32 => NEXT_OUTS <= 574; -- fsubl_Mq SANITY
when 40 => NEXT_OUTS <= 256; -- fsubrl_Mq SANITY
when 48 => NEXT_OUTS <= 587; -- fdivl_Mq SANITY
when 56 => NEXT_OUTS <= 241; -- fdivrl_Mq SANITY
when 192 => NEXT_OUTS <= 487; -- fadd_STi_ST0 SANITY
when 200 => NEXT_OUTS <= 355; -- fmul_STi_ST0 SANITY
when 224 => NEXT_OUTS <= 636; -- fsubr_STi_ST0 SANITY
when 232 => NEXT_OUTS <= 78; -- fsub_STi_ST0 SANITY
when 240 => NEXT_OUTS <= 669; -- fdivr_STi_ST0 SANITY
when 248 => NEXT_OUTS <= 580; -- fdiv_STi_ST0 SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 221 =>
case OP2 is
when 0 => NEXT_OUTS <= 500; -- fldl_Mq SANITY
when 16 => NEXT_OUTS <= 505; -- fstl_Mq SANITY
when 24 => NEXT_OUTS <= 63; -- fstpl_Mq SANITY
when 32 => NEXT_OUTS <= 771; -- frstor SANITY
when 48 => NEXT_OUTS <= 121; -- fnsave SANITY
when 56 => NEXT_OUTS <= 759; -- fnstsw SANITY
when 192 => NEXT_OUTS <= 713; -- ffree_STi SANITY
when 208 => NEXT_OUTS <= 235; -- fst_STi SANITY
when 216 => NEXT_OUTS <= 50; -- fstp_STi SANITY
when 224 => NEXT_OUTS <= 289; -- fucom_STi SANITY
when 232 => NEXT_OUTS <= 451; -- fucomp_STi SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 222 =>
case OP2 is
when 0 => NEXT_OUTS <= 502; -- fiadds_Mw SANITY
when 8 => NEXT_OUTS <= 485; -- fimuls_Mw SANITY
when 16 => NEXT_OUTS <= 781; -- ficoms_Mw SANITY
when 24 => NEXT_OUTS <= 324; -- ficomps_Mw SANITY
when 32 => NEXT_OUTS <= 333; -- fisubs_Mw SANITY
when 40 => NEXT_OUTS <= 233; -- fisubrs_Mw SANITY
when 48 => NEXT_OUTS <= 659; -- fidivs_Mw SANITY
when 56 => NEXT_OUTS <= 98; -- fidivrs_Mw SANITY
when 192 => NEXT_OUTS <= 84; -- faddp_STi_ST0 SANITY
when 200 => NEXT_OUTS <= 171; -- fmulp_STi_ST0 SANITY
when 217 => NEXT_OUTS <= 15; -- fcompp SANITY
when 224 => NEXT_OUTS <= 644; -- fsubrp_STi_ST0 SANITY
when 232 => NEXT_OUTS <= 403; -- fsubp_STi_ST0 SANITY
when 240 => NEXT_OUTS <= 443; -- fdivrp_STi_ST0 SANITY
when 248 => NEXT_OUTS <= 215; -- fdivp_STi_ST0 SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 223 =>
case OP2 is
when 0 => NEXT_OUTS <= 377; -- filds_Mw SANITY
when 16 => NEXT_OUTS <= 619; -- fists_Mw SANITY
when 24 => NEXT_OUTS <= 37; -- fistps_Mw SANITY
when 32 => NEXT_OUTS <= 425; -- fbldt_Mt SANITY
when 40 => NEXT_OUTS <= 528; -- fildq_Mq SANITY
when 48 => NEXT_OUTS <= 495; -- fbstpt_Mt SANITY
when 56 => NEXT_OUTS <= 675; -- fistpq_Mq SANITY
when 224 => NEXT_OUTS <= 260; -- fnstsw_AX SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 224 => NEXT_OUTS <= 679; -- loopne_Jb SANITY
when 225 => NEXT_OUTS <= 381; -- loope_Jb SANITY
when 226 => NEXT_OUTS <= 692; -- loop_Jb SANITY
when 227 =>
case OP2 is
when 0 => NEXT_OUTS <= 432; -- jecxz_Jb SANITY
when 1 => NEXT_OUTS <= 408; -- jrcxz_Jb SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 228 => NEXT_OUTS <= 358; -- inb_AL_Ib SANITY
when 229 => NEXT_OUTS <= 412; -- inl_EAX_Ib SANITY
when 230 => NEXT_OUTS <= 10; -- outb_Ib_AL SANITY
when 231 => NEXT_OUTS <= 671; -- outl_Ib_EAX SANITY
when 232 => NEXT_OUTS <= 148; -- call_Jd SANITY
when 233 => NEXT_OUTS <= 592; -- jmp_Jd SANITY
when 234 => NEXT_OUTS <= 158; -- ljmp_Apd SANITY
when 235 => NEXT_OUTS <= 124; -- jmp_Jb SANITY
when 236 => NEXT_OUTS <= 455; -- inb_AL_DX SANITY
when 237 => NEXT_OUTS <= 480; -- inl_EAX_DX SANITY
when 238 => NEXT_OUTS <= 301; -- outb_DX_AL SANITY
when 239 => NEXT_OUTS <= 317; -- outl_DX_EAX SANITY
when 241 => NEXT_OUTS <= 296; -- int1 SANITY
when 243 =>
case OP2 is
when 15 =>
case OP3 is
when 174 =>
case OP4 is
when 192 => NEXT_OUTS <= 708; -- rdfsbase_Ry SANITY
when 200 => NEXT_OUTS <= 664; -- rdgsbase_Ry SANITY
when 208 => NEXT_OUTS <= 547; -- wrfsbase_Ry SANITY
when 216 => NEXT_OUTS <= 683; -- wrgsbase_Ry SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 144 => NEXT_OUTS <= 114; -- pause SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 244 => NEXT_OUTS <= 676; -- hlt SANITY
when 245 => NEXT_OUTS <= 145; -- cmc SANITY
when 246 =>
case OP2 is
when 0 => NEXT_OUTS <= 475; -- testb_Eb_Ib SANITY
when 16 => NEXT_OUTS <= 133; -- notb_Eb SANITY
when 24 => NEXT_OUTS <= 560; -- negb_Eb SANITY
when 32 => NEXT_OUTS <= 638; -- mulb_AL_Eb SANITY
when 40 => NEXT_OUTS <= 465; -- imulb_AL_Eb SANITY
when 48 => NEXT_OUTS <= 230; -- divb_AL_Eb SANITY
when 56 => NEXT_OUTS <= 555; -- idivb_AL_Eb SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 247 =>
case OP2 is
when 0 => NEXT_OUTS <= 518; -- testl_Ed_Id SANITY
when 16 => NEXT_OUTS <= 474; -- notl_Ed SANITY
when 24 => NEXT_OUTS <= 275; -- negl_Ed SANITY
when 32 => NEXT_OUTS <= 347; -- mull_EAX_Ed SANITY
when 40 => NEXT_OUTS <= 667; -- imull_EAX_Ed SANITY
when 48 => NEXT_OUTS <= 319; -- divl_EAX_Ed SANITY
when 56 => NEXT_OUTS <= 731; -- idivl_EAX_Ed SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 248 => NEXT_OUTS <= 710; -- clc SANITY
when 249 => NEXT_OUTS <= 630; -- stc SANITY
when 250 => NEXT_OUTS <= 599; -- cli SANITY
when 251 => NEXT_OUTS <= 222; -- sti SANITY
when 252 => NEXT_OUTS <= 652; -- cld SANITY
when 253 => NEXT_OUTS <= 405; -- std SANITY
when 254 =>
case OP2 is
when 0 => NEXT_OUTS <= 218; -- incb_Eb SANITY
when 8 => NEXT_OUTS <= 119; -- decb_Eb SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 255 =>
case OP2 is
when 0 => NEXT_OUTS <= 267; -- incl_Ed SANITY
when 8 => NEXT_OUTS <= 378; -- decl_Ed SANITY
when 16 =>
case OP3 is
when 0 => NEXT_OUTS <= 239; -- call_Ed SANITY
when 1 => NEXT_OUTS <= 113; -- call_Eq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 24 => NEXT_OUTS <= 732; -- lcall_Mp SANITY
when 32 =>
case OP3 is
when 0 => NEXT_OUTS <= 250; -- jmp_Ed SANITY
when 1 => NEXT_OUTS <= 575; -- jmp_Eq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when 40 => NEXT_OUTS <= 293; -- ljmp_Mp SANITY
when 48 =>
case OP3 is
when 0 => NEXT_OUTS <= 757; -- pushl_Ed SANITY
when 1 => NEXT_OUTS <= 180; -- pushq_Eq SANITY
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
when others => NEXT_OUTS <= 0; -- invalid
end case;
end process;
end behv;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0238
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80sed is
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80sed;
architecture rtl of T80sed is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => 0,
IOWait => 1)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if ((TState = "001") or (TState = "010")) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;
|
package pkg is
subtype s is integer (0 to 10); -- error
subtype ss is string range 2 to 5; -- error
end package pkg;
|
package pkg is
subtype s is integer (0 to 10); -- error
subtype ss is string range 2 to 5; -- error
end package pkg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2939.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p07n03i02939ent IS
procedure proc1 (i,l:integer; res: boolean);
EEND c02s02b00x00p07n03i02939ent;
ARCHITECTURE c02s02b00x00p07n03i02939arch OF c02s02b00x00p07n03i02939ent IS
-- ERROR: non-existent body for procedure proc1
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n03i02939 - Every subprogram declaration has to have a corresponding body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n03i02939arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2939.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p07n03i02939ent IS
procedure proc1 (i,l:integer; res: boolean);
EEND c02s02b00x00p07n03i02939ent;
ARCHITECTURE c02s02b00x00p07n03i02939arch OF c02s02b00x00p07n03i02939ent IS
-- ERROR: non-existent body for procedure proc1
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n03i02939 - Every subprogram declaration has to have a corresponding body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n03i02939arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2939.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p07n03i02939ent IS
procedure proc1 (i,l:integer; res: boolean);
EEND c02s02b00x00p07n03i02939ent;
ARCHITECTURE c02s02b00x00p07n03i02939arch OF c02s02b00x00p07n03i02939ent IS
-- ERROR: non-existent body for procedure proc1
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n03i02939 - Every subprogram declaration has to have a corresponding body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n03i02939arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity extimg is
generic(
Ha: integer := 96; -- Hpulse
Hb: integer := 144; -- Hpulse+HBP
Hc: integer := 784; -- Hpulse+HBP+Hactive
Hd: integer := 800; -- Hpulse+HBP+Hactive+HFP
Va: integer := 2; -- Vpulse
Vb: integer := 35; -- Vpulse+VBP
Vc: integer := 515; -- Vpulse+VBP+Vactive
Vd: integer := 525); -- Vpulse+VBP+Vactive+VFP
port(
clk: in std_logic; -- 50 MHz
pixel_clk: buffer std_logic; -- 25 MHz
Hsync,Vsync: buffer std_logic;
R,G,B: out std_logic_vector(9 downto 0);
nblank,nsync: out std_logic;
nWE,nCE,nOE,nLB,nUB: out std_logic;
address: out integer range 0 to 262143;
data: in std_logic_vector(15 downto 0));
end extimg;
architecture ei of extimg is
signal Hactive,Vactive,dena: std_logic;
signal registered_data: std_logic_vector(15 downto 0);
signal flag: std_logic;
begin
-- control generator
-----------------------------------------------------------------
nblank <= '1';
nsync <= '0';
process (clk)
begin
if (clk'event and clk='1') then
pixel_clk <= not pixel_clk;
end if;
end process;
process (pixel_clk)
variable Hcount: integer range 0 to Hd;
begin
if (pixel_clk'event and pixel_clk='1') then
Hcount := Hcount + 1;
if (Hcount=Ha) then
Hsync <= '1';
elsif (Hcount=Hb) then
Hactive <= '1';
elsif (Hcount=Hc) then
Hactive <= '0';
elsif (Hcount=Hd) then
Hsync <= '0';
Hcount := 0;
end if;
end if;
end process;
process (Hsync)
variable Vcount: integer range 0 to Vd;
begin
if (Hsync'event and Hsync='0') then
Vcount := Vcount + 1;
if (Vcount=Va) then
Vsync <= '1';
elsif (Vcount=Vb) then
Vactive <= '1';
elsif (Vcount=Vc) then
Vactive <= '0';
elsif (Vcount=Vd) then
Vsync <= '0';
Vcount := 0;
end if;
end if;
end process;
dena <= (Hactive and Vactive);
---------------------------------------------------------------------------
-- image generator
---------------------------------------------------------------------------
nWE <= '1';
nCE <= '0';
nOE <= '0';
nLB <= '0';
nUB <= '0';
process (pixel_clk, Vsync)
variable pixel_counter: integer range 0 to 262143;
begin
if (Vsync='0') then
pixel_counter := 0;
flag <= '0';
elsif (pixel_clk'event and pixel_clk='1') then
if (dena='1' and flag='1') then
registered_data <= data;
pixel_counter := pixel_counter + 1;
end if;
flag <= not flag;
end if;
address <= pixel_counter;
end process;
process (dena, flag, registered_data)
begin
if (dena='1') then
if (flag='1') then
R <= (registered_data(15 downto 8) & "00");
G <= (registered_data(15 downto 8) & "00");
B <= (registered_data(15 downto 8) & "00");
else
R <= (registered_data(7 downto 0) & "00");
G <= (registered_data(7 downto 0) & "00");
B <= (registered_data(7 downto 0) & "00");
end if;
else
R <= (others => '0');
G <= (others => '0');
B <= (others => '0');
end if;
end process;
end ei;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity blink_10m04 is
Port (
c1_1 : inout std_logic;
c1_2 : inout std_logic;
c1_3 : inout std_logic;
c1_5 : inout std_logic;
c1_6 : inout std_logic;
c1_7 : inout std_logic;
c1_9 : inout std_logic;
c1_10 : inout std_logic;
c1_11 : inout std_logic;
c1_12 : inout std_logic;
c1_13 : inout std_logic;
c1_14 : inout std_logic;
c1_16 : inout std_logic;
c1_17 : inout std_logic;
c1_18 : inout std_logic;
c1_19 : inout std_logic;
c1_20 : inout std_logic;
c1_22 : inout std_logic;
c1_23 : inout std_logic;
c1_24 : inout std_logic;
c1_25 : inout std_logic;
c1_26 : inout std_logic;
c1_27 : inout std_logic;
c1_28 : inout std_logic;
c1_29 : inout std_logic;
c1_30 : inout std_logic;
c1_31 : inout std_logic;
c1_33 : inout std_logic;
c1_34 : inout std_logic;
c1_36 : inout std_logic;
c1_37 : inout std_logic;
c1_38 : inout std_logic;
c2_1 : inout std_logic;
c2_3 : inout std_logic;
c2_4 : inout std_logic;
c2_5 : inout std_logic;
c2_8 : inout std_logic;
c2_12 : inout std_logic;
c3_1 : inout std_logic;
c3_2_CLK3n : inout std_logic;
c3_3 : inout std_logic;
c3_4 : inout std_logic;
c3_5_CLK3p : inout std_logic;
c3_6 : inout std_logic;
c3_7 : inout std_logic;
c3_8 : inout std_logic;
c3_9 : inout std_logic;
c3_10 : inout std_logic;
c3_11 : inout std_logic;
c3_12 : inout std_logic;
c4_3_VREFB2N0 : inout std_logic;
c4_4 : inout std_logic;
c4_6 : inout std_logic;
c4_7 : inout std_logic;
c4_8 : inout std_logic;
c4_10 : inout std_logic;
c4_11 : inout std_logic;
c4_12 : inout std_logic;
c4_13 : inout std_logic;
c4_14 : inout std_logic;
c4_15_DPCLK1 : inout std_logic;
c4_16_DPCLK0 : inout std_logic;
c4_17 : inout std_logic;
c4_18 : inout std_logic;
c4_19 : inout std_logic;
c4_20 : inout std_logic;
c4_21 : inout std_logic;
c4_22 : inout std_logic;
c4_23 : inout std_logic;
c4_24 : inout std_logic;
c4_25 : inout std_logic;
c4_26 : inout std_logic;
c4_27 : inout std_logic;
c4_28 : inout std_logic;
c4_30 : inout std_logic;
c4_31 : inout std_logic;
c4_32 : inout std_logic;
c4_33 : inout std_logic;
c4_34 : inout std_logic;
c4_35 : inout std_logic;
c4_36 : inout std_logic;
c4_37 : inout std_logic;
c4_38 : inout std_logic;
c4_39 : inout std_logic;
c4_40 : inout std_logic
);
end blink_10m04;
architecture rtl of blink_10m04 is
component internal_osc is
port (
oscena : in std_logic := 'X'; -- oscena
clkout : out std_logic -- clk
);
end component internal_osc;
signal clk : std_logic; -- 55-115MHz clock from internal oscillator
signal clk_div_count : std_logic_vector(26 downto 0) := (others => '0');
signal slow_clk : std_logic; -- clk/(128*1024*1024), 0.4-0.85 Hz
begin
osc0 : component internal_osc
port map (
oscena => '1',
clkout => clk
);
process (clk)
begin
if rising_edge(clk) then
clk_div_count <= std_logic_vector(unsigned(clk_div_count) + 1);
if unsigned(clk_div_count) = 0 then
slow_clk <= not slow_clk;
end if;
end if;
end process;
c1_1 <= slow_clk;
c1_2 <= 'Z'; -- poor solder connection, tristate so we can patch
c1_3 <= slow_clk;
c1_5 <= slow_clk;
c1_6 <= slow_clk;
c1_7 <= slow_clk;
c1_9 <= slow_clk;
c1_10 <= slow_clk;
c1_11 <= slow_clk;
c1_12 <= slow_clk;
c1_13 <= slow_clk;
c1_14 <= slow_clk;
c1_16 <= slow_clk;
c1_17 <= slow_clk;
c1_18 <= slow_clk;
c1_19 <= 'Z'; -- poor solder connection, tristate so we can patch
c1_20 <= slow_clk;
c1_22 <= slow_clk;
c1_23 <= slow_clk;
c1_24 <= slow_clk;
c1_25 <= slow_clk;
c1_26 <= slow_clk;
c1_27 <= slow_clk;
c1_28 <= slow_clk;
c1_29 <= slow_clk;
c1_30 <= slow_clk;
c1_31 <= slow_clk;
c1_33 <= slow_clk;
c1_34 <= slow_clk;
c1_36 <= slow_clk;
c1_37 <= slow_clk;
c1_38 <= slow_clk;
c2_1 <= slow_clk;
c2_3 <= slow_clk;
c2_4 <= slow_clk;
c2_5 <= slow_clk;
c2_8 <= slow_clk;
c2_12 <= slow_clk;
c3_1 <= slow_clk;
c3_2_CLK3n <= slow_clk;
c3_3 <= slow_clk;
c3_4 <= slow_clk;
c3_5_CLK3p <= slow_clk;
c3_6 <= slow_clk;
c3_7 <= slow_clk;
c3_8 <= slow_clk;
c3_9 <= slow_clk;
c3_10 <= slow_clk;
c3_11 <= slow_clk;
c3_12 <= slow_clk;
c4_3_VREFB2N0 <= slow_clk;
c4_4 <= slow_clk;
c4_6 <= slow_clk;
c4_7 <= slow_clk;
c4_8 <= slow_clk;
c4_10 <= slow_clk;
c4_11 <= slow_clk;
c4_12 <= slow_clk;
c4_13 <= slow_clk;
c4_14 <= slow_clk;
c4_15_DPCLK1 <= slow_clk;
c4_16_DPCLK0 <= slow_clk;
c4_17 <= 'Z'; -- poor solder connection, tristate so we can patch
c4_18 <= slow_clk;
c4_19 <= slow_clk;
c4_20 <= slow_clk;
c4_21 <= slow_clk;
c4_22 <= slow_clk;
c4_23 <= 'Z'; -- poor solder connection, tristate so we can patch
c4_24 <= slow_clk;
c4_25 <= slow_clk;
c4_26 <= slow_clk;
c4_27 <= slow_clk;
c4_28 <= 'Z'; -- poor solder connection, tristate so we can patch
c4_30 <= slow_clk;
c4_31 <= slow_clk;
c4_32 <= slow_clk;
c4_33 <= slow_clk;
c4_34 <= slow_clk;
c4_35 <= slow_clk;
c4_36 <= slow_clk;
c4_37 <= slow_clk;
c4_38 <= slow_clk;
c4_39 <= 'Z'; -- poor solder connection, tristate so we can patch
c4_40 <= slow_clk;
end rtl;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
ROM_form.vhd
Production template for a 2K program for KCPSM6 in a 7-Series device using a
RAMB36E1 primitive with a content verifying CRC-16 circuit.
PLEASE READ THE DESCRIPTIONS AND ADVICE LATER IN THIS TEMPLATE OR CONTAINED IN THE
ASSEMBLED FILE.
Ken Chapman (Xilinx Ltd)
9th August 2012 - Initial Release
8th October 2012 - Optimised implementation.
14th March 2013 - Unused address inputs on BRAMs connected High to reflect
descriptions UG473.
This is a VHDL template file for the KCPSM6 assembler.
This VHDL file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.vhd' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Production definition of a 2K program for KCPSM6 in a 7-Series device using a
-- RAMB36E1 primitive with a content verifying CRC-16 error detection circuit.
--
-- NOTE - Compared with any of the normal program memory definitions for KCPSM6 this
-- module has additional inputs and outputs associated with the error detection
-- feature. Only use this module if there is a clear requirement to perform
-- error detection and do consider all the factors described below when
-- incorporating it in a design.
--
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: {timestamp}.
--
-- Assembler used ROM_form template: ROM_form_7S_2K_with_error_detection_14March13.vhd
--
--
-- Error Detection Feature
-- -----------------------
--
-- In this application the BRAM is being used as a ROM and therefore the contents should
-- not change during normal operation. If for any reason the contents of the memory should
-- change then there is the potential for KCPSM6 to execute an instruction that is either
-- different to that expected or even an invalid op-code neither of which would be
-- desirable. Obviously this should not happen and in majority of cases it will be more
-- than acceptable to assume that it never will. However, designs in which extreme levels
-- of reliability or design security are required may consider that the special error
-- detection feature provided in this memory definition is useful.
--
-- This memory definition provides KCPSM6 with access to the program in the conventional
-- way using the first port of the BRAM. Then the second port of the BRAM is used to
-- continuously scan the whole memory and compute the CRC-16 of the entire contents. At
-- the end of each scan the result of each CRC calculation is compared with the expected
-- value (which was computed by the KCPSM6 assembler). If the value does not match then
-- the 'scan_error' output is forced High to inform the system of a potential corruption
-- somewhere within the memory.
--
--
-- SEU Mitigation
-- --------------
--
-- One concern for the very highest reliability systems are Single Event Upsets (SEU)
-- caused by radiation. FIT rates for BRAM are published and updated quarterly in UG116
-- and these should be used to evaluate the potential failure rates prior to using this
-- memory with its error detection circuit. It is vital to remember that everything in a
-- system contributes to the overall reliability. As such, the thoughtless addition of
-- features such as BRAM content error detection could in fact lower the overall
-- reliability of the system which obviously wouldn't be the intention! Two of the factors
-- to consider are as follows:-
--
-- a) Configuration memory is also susceptible to SEU and may impact the operation of
-- a design. Again the FIT rates are published in UG116 and the failure rates need
-- to be estimated. PicoBlaze itself, the error detection circuit defined in this
-- file and whatever you monitor and control the error detection circuit with are
-- all associated with configuration memory and therefore the potential exists for
-- a 'false alarm'. For example, and SEU could flip a configuration memory cell that
-- altered the logic of the error detection circuit resulting in a 'scan_error' even
-- though the BRAM contents are good.
--
-- b) If one bit within the BRAM is flipped by an SEU (the typical effect), it could
-- take up to ~73,740 'scan_clk' cycles for the error to be detected and reported.
-- This worst case detection time is equivalent two complete scans of the memory
-- and would only occur if the SEU flips a bit very close to the start of the
-- memory (address zero) just after the scan has just passed that location. Hence,
-- the average detection time will be one complete scan (36,873 'scan_clk' cycles).
-- During the time taken to detect and report the error, and any time leading up to
-- your decision to take some suitable action, KCPSM6 may execute the instruction
-- that has been corrupted. The impact of executing that corrupted instruction is
-- anyone's guess! However, in terms of estimating the failure rate it is important
-- to recognise that KCPSM6 must actually read and execute the corrupted instruction
-- for anything unexpected to occur. So whilst the error detection circuit will
-- report when an error is present in the memory it definitely does not mean that
-- KCPSM6 has or will definitely go wrong. KCPSM6 programs rarely occupy all the
-- memory locations so the failure rate estimate should be scaled accordingly.
-- Likewise, most programs consist of some code that is used frequently and other
-- code which is only used occasionally (e.g. some code is only used during
-- initialisation). So once again the failure rate can often be scaled appropriately
-- to reflect the actual code. Due to these scaling factors there is quite a high
-- probability that a real upset will be detected and reported but for there to be
-- no effect on the program execution. Whilst this is not a 'false alarm' is may
-- appear to be. Detection of any error is valuable in a fail-safe system but it can
-- adversely impact the overall availability of systems if every alarm results in
-- an interruption to service. Therefore, deciding what action to take when an error
-- is detected is critical before opting to us this memory module with KCPSM6.
--
--
-- Design Security
-- ---------------
--
-- Devices of the 7-Series which this memory definition is intended to service provide
-- Bitstream Security in the form of AES encryption so obviously this should be of
-- high relevance for anyone concerned with design security. However, there may be
-- reasons not to use that feature or a desire to further enhance security in other ways.
-- Whilst it would be a significant challenge to reverse engineer a bitstream (assuming it
-- wasn't encrypted or was somehow decrypted), it is feasible to alter or tamper with the
-- bits in what is often referred to as 'side attacks'.
--
-- On a scale of difficulty it should be recognised that BRAM contents are one of the
-- easier targets for such attacks. Note that the DATA2MEM tool (see UG658) intended to
-- help accelerate design development would also be a useful tool for an attacker!
-- Obviously the ability to tamper with BRAM contents means that the program for a KCPSM6
-- processor could be altered or replaced. Depending on the purpose of that code it could
-- definitely compromise security.
--
-- Since the error detection circuit will report any changes to the memory contents this
-- scheme can also be used to detect attacks and somehow disable the design to prevent the
-- attacker making progress. For example, the 'scan_error' signal could be used to
-- permanently reset KCPSM6 or be used to disable something else in the design such as
-- putting critical output pins of the device into a high impedance state.
--
--
-- Using the Error Detection Feature in a Design
-- ---------------------------------------------
--
-- Whether this feature is used for SEU mitigation or design security it is highly
-- recommended that signals and logic associated with the error detection feature remain
-- isolated from the KCPSM6 processor; i.e. it certainly wouldn't be a good idea to
-- monitor the error signal with the same KCPSM6 given that any change to the
-- program may prevent KCPSM6 from reacting as intended in the first place. However,
-- it would be a valid arrangement for two or more KCPSM6 processors to monitor the
-- health of each other's memory providing they too had a reasonable degree of
-- independence(e.g. avoiding a common point such as using the same clock).
--
-- As with most digital circuits the clock is critical for reliable operation. In terms
-- failure rates then SEU are so rare that things like an irregular clock cycle or glitch
-- possibly caused by power surge could be as likely to impact the integrity of the
-- CRC-16 calculation and result in a false alarm. So always give consideration to the
-- source of your clock including any use of clock division or multiplication schemes
-- implemented within the FPGA before it is applied to the 'scan_clk' input of this module.
--
-- In most applications the 'scan_reset' control can be driven or tied Low. The report of
-- any error would be a rare event but would generally be considered a permanent error
-- until the device is reconfigured. However, there is the small possibility that an SEU
-- or clock glitch could impact the logical operation of the error detection circuit
-- resulting in a 'false alarm'. In these situations, the device level SEU mitigation
-- measures would detect and subsequently correct the configuration memory error or the
-- clock source would recover. Applying a synchronous pulse to 'scan_reset' would then
-- clear the false alarm and allow the memory checking to continue. Ultimately, design
-- for reliability must consider the interaction between all elements of the system and
-- can not simply focus on one issue like the BRAM contents.
--
-- In situations where the clock may take time to settle following device configuration
-- the error detection circuit should be held in reset until the integrity of the clock
-- can be assured.
--
-- Note that the 'scan_error' signal has be deliberately designed to 'latch' any error
-- that is detected (i.e. false alarms are not cleared automatically by a subsequent good
-- scan of the memory). This scheme ensures that no error reports can be missed by a
-- monitor which only checks occasionally. It is always the responsibility of the system
-- to decide what action to take when an error is reported. Some systems may initially
-- reset the error detection circuit in order to confirm the error is permanent before
-- taking more significant actions.
--
-- The 'scan_complete' signal is a single clock cycle pulse generated at the end of each
-- CRC-16 calculation. This signal could be ignored but for both reliability and security
-- purposes it is extremely useful to know that the error detection circuit is actually
-- working and these pulses will confirm that it is (one pulse every 36,873 'scan_clk'
-- cycles). For example, these pulses confirm that the clock is being supplied and has not
-- been disabled by an SEU, oscillator failure, board defect or a malicious attacker.
--
--
-------------------------------------------------------------------------------------------
--
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
clk : in std_logic;
scan_error : out std_logic;
scan_complete : out std_logic;
scan_reset : in std_logic;
scan_clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
signal address_a : std_logic_vector(15 downto 0);
signal data_in_a : std_logic_vector(35 downto 0);
signal data_out_a : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in_b : std_logic_vector(35 downto 0);
signal data_out_b : std_logic_vector(35 downto 0);
--
signal previous_scan_address : std_logic_vector(11 downto 0);
signal sa_carry_primer : std_logic_vector(11 downto 0);
signal scan_address_carry : std_logic_vector(11 downto 0);
signal scan_address_value : std_logic_vector(11 downto 0);
signal scan_address : std_logic_vector(11 downto 0);
signal scan_address_ce_value : std_logic;
signal scan_address_ce : std_logic;
signal scan_data : std_logic_vector(8 downto 0);
signal scan_bit_value : std_logic_vector(3 downto 0);
signal scan_bit : std_logic_vector(3 downto 0);
signal scan_mid : std_logic;
signal scan_high : std_logic;
signal scan_byte : std_logic;
signal crc_reset_value : std_logic;
signal crc_reset : std_logic;
signal crc : std_logic_vector(16 downto 1);
signal crc1_value : std_logic;
signal crc2_value : std_logic;
signal crc3_value : std_logic;
signal crc16_value : std_logic;
signal serial_data_value : std_logic;
signal serial_data : std_logic;
signal last_address_value : std_logic;
signal last_address : std_logic;
signal last_bit : std_logic;
signal end_of_scan : std_logic;
signal crc_test : std_logic;
signal crc_check_value : std_logic;
signal crc_check : std_logic;
--
attribute hblknm : string;
attribute hblknm of crc16_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc1_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc2_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc3_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc4_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc5_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc6_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc7_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc1_lut : label is "kcpsm6_program_crc1";
attribute hblknm of crc3_lut : label is "kcpsm6_program_crc1";
--
attribute hblknm of crc8_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc9_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc10_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc11_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc12_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc13_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc14_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc15_flop : label is "kcpsm6_program_crc2";
--
attribute hblknm of scan_bit0_flop : label is "kcpsm6_program_crc3";
attribute hblknm of scan_bit1_flop : label is "kcpsm6_program_crc3";
attribute hblknm of scan_bit2_flop : label is "kcpsm6_program_crc3";
attribute hblknm of scan_bit3_flop : label is "kcpsm6_program_crc3";
attribute hblknm of crc_reset_flop : label is "kcpsm6_program_crc3";
attribute hblknm of scan_address_ce_flop : label is "kcpsm6_program_crc3";
attribute hblknm of crc_check_flop : label is "kcpsm6_program_crc3";
attribute hblknm of last_address_flop : label is "kcpsm6_program_crc3";
attribute hblknm of scan_bit01_lut : label is "kcpsm6_program_crc3";
attribute hblknm of scan_bit23_lut : label is "kcpsm6_program_crc3";
attribute hblknm of crc_reset_lut : label is "kcpsm6_program_crc3";
attribute hblknm of crc_check_lut : label is "kcpsm6_program_crc3";
--
attribute hblknm of serial_data_flop : label is "kcpsm6_program_crc4";
attribute hblknm of last_bit_flop : label is "kcpsm6_program_crc4";
attribute hblknm of end_of_scan_flop : label is "kcpsm6_program_crc4";
attribute hblknm of scan_complete_flop : label is "kcpsm6_program_crc4";
attribute hblknm of serial_data_lut : label is "kcpsm6_program_crc4";
attribute hblknm of scan_mid_lut : label is "kcpsm6_program_crc4";
attribute hblknm of scan_high_lut : label is "kcpsm6_program_crc4";
attribute hblknm of scan_byte_muxf7 : label is "kcpsm6_program_crc4";
--
attribute hblknm of scan_address0_flop : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address0_lut : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address0_xorcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address0_muxcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address1_flop : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address1_lut : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address1_xorcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address1_muxcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address2_flop : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address2_lut : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address2_xorcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address2_muxcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address3_flop : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address3_lut : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address3_xorcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address3_muxcy : label is "kcpsm6_program_crc5";
--
attribute hblknm of scan_address4_flop : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address4_lut : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address4_xorcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address4_muxcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address5_flop : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address5_lut : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address5_xorcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address5_muxcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address6_flop : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address6_lut : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address6_xorcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address6_muxcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address7_flop : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address7_lut : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address7_xorcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address7_muxcy : label is "kcpsm6_program_crc6";
--
attribute hblknm of scan_address8_flop : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address8_lut : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address8_xorcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address8_muxcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address9_flop : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address9_lut : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address9_xorcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address9_muxcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address10_flop : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address10_lut : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address10_xorcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address10_muxcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address11_flop : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address11_lut : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address11_xorcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address11_muxcy : label is "kcpsm6_program_crc7";
--
begin
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
--
address_b <= '1' & scan_address(11 downto 0) & "111";
data_in_b <= "000000000000000000000000000000000000";
scan_data <= data_out_b(32) & data_out_b(7 downto 0);
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INIT_40 => X"{INIT_40}",
INIT_41 => X"{INIT_41}",
INIT_42 => X"{INIT_42}",
INIT_43 => X"{INIT_43}",
INIT_44 => X"{INIT_44}",
INIT_45 => X"{INIT_45}",
INIT_46 => X"{INIT_46}",
INIT_47 => X"{INIT_47}",
INIT_48 => X"{INIT_48}",
INIT_49 => X"{INIT_49}",
INIT_4A => X"{INIT_4A}",
INIT_4B => X"{INIT_4B}",
INIT_4C => X"{INIT_4C}",
INIT_4D => X"{INIT_4D}",
INIT_4E => X"{INIT_4E}",
INIT_4F => X"{INIT_4F}",
INIT_50 => X"{INIT_50}",
INIT_51 => X"{INIT_51}",
INIT_52 => X"{INIT_52}",
INIT_53 => X"{INIT_53}",
INIT_54 => X"{INIT_54}",
INIT_55 => X"{INIT_55}",
INIT_56 => X"{INIT_56}",
INIT_57 => X"{INIT_57}",
INIT_58 => X"{INIT_58}",
INIT_59 => X"{INIT_59}",
INIT_5A => X"{INIT_5A}",
INIT_5B => X"{INIT_5B}",
INIT_5C => X"{INIT_5C}",
INIT_5D => X"{INIT_5D}",
INIT_5E => X"{INIT_5E}",
INIT_5F => X"{INIT_5F}",
INIT_60 => X"{INIT_60}",
INIT_61 => X"{INIT_61}",
INIT_62 => X"{INIT_62}",
INIT_63 => X"{INIT_63}",
INIT_64 => X"{INIT_64}",
INIT_65 => X"{INIT_65}",
INIT_66 => X"{INIT_66}",
INIT_67 => X"{INIT_67}",
INIT_68 => X"{INIT_68}",
INIT_69 => X"{INIT_69}",
INIT_6A => X"{INIT_6A}",
INIT_6B => X"{INIT_6B}",
INIT_6C => X"{INIT_6C}",
INIT_6D => X"{INIT_6D}",
INIT_6E => X"{INIT_6E}",
INIT_6F => X"{INIT_6F}",
INIT_70 => X"{INIT_70}",
INIT_71 => X"{INIT_71}",
INIT_72 => X"{INIT_72}",
INIT_73 => X"{INIT_73}",
INIT_74 => X"{INIT_74}",
INIT_75 => X"{INIT_75}",
INIT_76 => X"{INIT_76}",
INIT_77 => X"{INIT_77}",
INIT_78 => X"{INIT_78}",
INIT_79 => X"{INIT_79}",
INIT_7A => X"{INIT_7A}",
INIT_7B => X"{INIT_7B}",
INIT_7C => X"{INIT_7C}",
INIT_7D => X"{INIT_7D}",
INIT_7E => X"{INIT_7E}",
INIT_7F => X"{INIT_7F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}",
INITP_08 => X"{INITP_08}",
INITP_09 => X"{INITP_09}",
INITP_0A => X"{INITP_0A}",
INITP_0B => X"{INITP_0B}",
INITP_0C => X"{INITP_0C}",
INITP_0D => X"{INITP_0D}",
INITP_0E => X"{INITP_0E}",
INITP_0F => X"{INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => '1',
CLKBWRCLK => scan_clk,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => "00000000",
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
-- Error Detection Circuit
--
scan_mid_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => scan_data(1),
I1 => scan_data(2),
I2 => scan_data(3),
I3 => scan_data(4),
I4 => scan_bit(0),
I5 => scan_bit(1),
O => scan_mid);
--
scan_high_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => scan_data(5),
I1 => scan_data(6),
I2 => scan_data(7),
I3 => scan_data(8),
I4 => scan_bit(0),
I5 => scan_bit(1),
O => scan_high);
--
scan_byte_muxf7: MUXF7
port map( I0 => scan_mid,
I1 => scan_high,
S => scan_bit(2),
O => scan_byte);
--
crc1_lut: LUT6_2
generic map (INIT => X"F0F0F0F066666666")
port map( I0 => serial_data,
I1 => crc(16),
I2 => crc(1),
I3 => '1',
I4 => '1',
I5 => '1',
O5 => crc1_value,
O6 => crc2_value);
--
crc3_lut: LUT6_2
generic map (INIT => X"C33C0000A55A0000")
port map( I0 => crc(2),
I1 => crc(15),
I2 => crc(16),
I3 => serial_data,
I4 => '1',
I5 => '1',
O5 => crc3_value,
O6 => crc16_value);
--
crc1_flop: FDR
port map ( D => crc1_value,
Q => crc(1),
R => crc_reset,
C => scan_clk);
--
crc2_flop: FDR
port map ( D => crc2_value,
Q => crc(2),
R => crc_reset,
C => scan_clk);
--
crc3_flop: FDR
port map ( D => crc3_value,
Q => crc(3),
R => crc_reset,
C => scan_clk);
--
crc4_flop: FDR
port map ( D => crc(3),
Q => crc(4),
R => crc_reset,
C => scan_clk);
--
crc5_flop: FDR
port map ( D => crc(4),
Q => crc(5),
R => crc_reset,
C => scan_clk);
--
crc6_flop: FDR
port map ( D => crc(5),
Q => crc(6),
R => crc_reset,
C => scan_clk);
--
crc7_flop: FDR
port map ( D => crc(6),
Q => crc(7),
R => crc_reset,
C => scan_clk);
--
crc8_flop: FDR
port map ( D => crc(7),
Q => crc(8),
R => crc_reset,
C => scan_clk);
--
crc9_flop: FDR
port map ( D => crc(8),
Q => crc(9),
R => crc_reset,
C => scan_clk);
--
crc10_flop: FDR
port map ( D => crc(9),
Q => crc(10),
R => crc_reset,
C => scan_clk);
--
crc11_flop: FDR
port map ( D => crc(10),
Q => crc(11),
R => crc_reset,
C => scan_clk);
--
crc12_flop: FDR
port map ( D => crc(11),
Q => crc(12),
R => crc_reset,
C => scan_clk);
--
crc13_flop: FDR
port map ( D => crc(12),
Q => crc(13),
R => crc_reset,
C => scan_clk);
--
crc14_flop: FDR
port map ( D => crc(13),
Q => crc(14),
R => crc_reset,
C => scan_clk);
--
crc15_flop: FDR
port map ( D => crc(14),
Q => crc(15),
R => crc_reset,
C => scan_clk);
--
crc16_flop: FDR
port map ( D => crc16_value,
Q => crc(16),
R => crc_reset,
C => scan_clk);
--
scan_bit01_lut: LUT6_2
generic map (INIT => X"0000E6660000D555")
port map( I0 => scan_bit(0),
I1 => scan_bit(1),
I2 => scan_bit(2),
I3 => scan_bit(3),
I4 => end_of_scan,
I5 => '1',
O5 => scan_bit_value(0),
O6 => scan_bit_value(1));
--
scan_bit23_lut: LUT6_2
generic map (INIT => X"00007F800000F878")
port map( I0 => scan_bit(0),
I1 => scan_bit(1),
I2 => scan_bit(2),
I3 => scan_bit(3),
I4 => end_of_scan,
I5 => '1',
O5 => scan_bit_value(2),
O6 => scan_bit_value(3));
--
scan_bit0_flop: FDR
port map ( D => scan_bit_value(0),
Q => scan_bit(0),
R => scan_reset,
C => scan_clk);
--
scan_bit1_flop: FDR
port map ( D => scan_bit_value(1),
Q => scan_bit(1),
R => scan_reset,
C => scan_clk);
--
scan_bit2_flop: FDR
port map ( D => scan_bit_value(2),
Q => scan_bit(2),
R => scan_reset,
C => scan_clk);
--
scan_bit3_flop: FDR
port map ( D => scan_bit_value(3),
Q => scan_bit(3),
R => scan_reset,
C => scan_clk);
--
crc_reset_lut: LUT6_2
generic map (INIT => X"007F000020000000")
port map( I0 => scan_bit(0),
I1 => scan_bit(1),
I2 => scan_bit(2),
I3 => scan_bit(3),
I4 => '1',
I5 => '1',
O5 => scan_address_ce_value,
O6 => crc_reset_value);
--
scan_address_ce_flop: FDR
port map ( D => scan_address_ce_value,
Q => scan_address_ce,
R => scan_reset,
C => scan_clk);
--
crc_reset_flop: FDR
port map ( D => crc_reset_value,
Q => crc_reset,
R => scan_reset,
C => scan_clk);
--
crc_check_lut: LUT6_2
generic map (INIT => X"FF00F0F088888888")
port map( I0 => scan_address_carry(11),
I1 => scan_address_ce,
I2 => crc_check,
I3 => crc_test,
I4 => end_of_scan,
I5 => '1',
O5 => last_address_value,
O6 => crc_check_value);
--
crc_check_flop: FDR
port map ( D => crc_check_value,
Q => crc_check,
R => scan_reset,
C => scan_clk);
--
last_address_flop: FDR
port map ( D => last_address_value,
Q => last_address,
R => scan_reset,
C => scan_clk);
--
scan_address0_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(0),
I5 => '1',
O5 => sa_carry_primer(0),
O6 => previous_scan_address(0));
--
scan_address0_xorcy: XORCY
port map( LI => previous_scan_address(0),
CI => '1',
O => scan_address_value(0));
--
scan_address0_muxcy: MUXCY
port map( DI => sa_carry_primer(0),
CI => '1',
S => previous_scan_address(0),
O => scan_address_carry(0));
--
scan_address0_flop: FDRE
port map ( D => scan_address_value(0),
Q => scan_address(0),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address1_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(1),
I5 => '1',
O5 => sa_carry_primer(1),
O6 => previous_scan_address(1));
--
scan_address1_xorcy: XORCY
port map( LI => previous_scan_address(1),
CI => scan_address_carry(0),
O => scan_address_value(1));
--
scan_address1_muxcy: MUXCY
port map( DI => sa_carry_primer(1),
CI => scan_address_carry(0),
S => previous_scan_address(1),
O => scan_address_carry(1));
--
scan_address1_flop: FDRE
port map ( D => scan_address_value(1),
Q => scan_address(1),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address2_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(2),
I5 => '1',
O5 => sa_carry_primer(2),
O6 => previous_scan_address(2));
--
scan_address2_xorcy: XORCY
port map( LI => previous_scan_address(2),
CI => scan_address_carry(1),
O => scan_address_value(2));
--
scan_address2_muxcy: MUXCY
port map( DI => sa_carry_primer(2),
CI => scan_address_carry(1),
S => previous_scan_address(2),
O => scan_address_carry(2));
--
scan_address2_flop: FDRE
port map ( D => scan_address_value(2),
Q => scan_address(2),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address3_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(3),
I5 => '1',
O5 => sa_carry_primer(3),
O6 => previous_scan_address(3));
--
scan_address3_xorcy: XORCY
port map( LI => previous_scan_address(3),
CI => scan_address_carry(2),
O => scan_address_value(3));
--
scan_address3_muxcy: MUXCY
port map( DI => sa_carry_primer(3),
CI => scan_address_carry(2),
S => previous_scan_address(3),
O => scan_address_carry(3));
--
scan_address3_flop: FDRE
port map ( D => scan_address_value(3),
Q => scan_address(3),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address4_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(4),
I5 => '1',
O5 => sa_carry_primer(4),
O6 => previous_scan_address(4));
--
scan_address4_xorcy: XORCY
port map( LI => previous_scan_address(4),
CI => scan_address_carry(3),
O => scan_address_value(4));
--
scan_address4_muxcy: MUXCY
port map( DI => sa_carry_primer(4),
CI => scan_address_carry(3),
S => previous_scan_address(4),
O => scan_address_carry(4));
--
scan_address4_flop: FDRE
port map ( D => scan_address_value(4),
Q => scan_address(4),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address5_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(5),
I5 => '1',
O5 => sa_carry_primer(5),
O6 => previous_scan_address(5));
--
scan_address5_xorcy: XORCY
port map( LI => previous_scan_address(5),
CI => scan_address_carry(4),
O => scan_address_value(5));
--
scan_address5_muxcy: MUXCY
port map( DI => sa_carry_primer(5),
CI => scan_address_carry(4),
S => previous_scan_address(5),
O => scan_address_carry(5));
--
scan_address5_flop: FDRE
port map ( D => scan_address_value(5),
Q => scan_address(5),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address6_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(6),
I5 => '1',
O5 => sa_carry_primer(6),
O6 => previous_scan_address(6));
--
scan_address6_xorcy: XORCY
port map( LI => previous_scan_address(6),
CI => scan_address_carry(5),
O => scan_address_value(6));
--
scan_address6_muxcy: MUXCY
port map( DI => sa_carry_primer(6),
CI => scan_address_carry(5),
S => previous_scan_address(6),
O => scan_address_carry(6));
--
scan_address6_flop: FDRE
port map ( D => scan_address_value(6),
Q => scan_address(6),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address7_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(7),
I5 => '1',
O5 => sa_carry_primer(7),
O6 => previous_scan_address(7));
--
scan_address7_xorcy: XORCY
port map( LI => previous_scan_address(7),
CI => scan_address_carry(6),
O => scan_address_value(7));
--
scan_address7_muxcy: MUXCY
port map( DI => sa_carry_primer(7),
CI => scan_address_carry(6),
S => previous_scan_address(7),
O => scan_address_carry(7));
--
scan_address7_flop: FDRE
port map ( D => scan_address_value(7),
Q => scan_address(7),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address8_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(8),
I5 => '1',
O5 => sa_carry_primer(8),
O6 => previous_scan_address(8));
--
scan_address8_xorcy: XORCY
port map( LI => previous_scan_address(8),
CI => scan_address_carry(7),
O => scan_address_value(8));
--
scan_address8_muxcy: MUXCY
port map( DI => sa_carry_primer(8),
CI => scan_address_carry(7),
S => previous_scan_address(8),
O => scan_address_carry(8));
--
scan_address8_flop: FDRE
port map ( D => scan_address_value(8),
Q => scan_address(8),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address9_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(9),
I5 => '1',
O5 => sa_carry_primer(9),
O6 => previous_scan_address(9));
--
scan_address9_xorcy: XORCY
port map( LI => previous_scan_address(9),
CI => scan_address_carry(8),
O => scan_address_value(9));
--
scan_address9_muxcy: MUXCY
port map( DI => sa_carry_primer(9),
CI => scan_address_carry(8),
S => previous_scan_address(9),
O => scan_address_carry(9));
--
scan_address9_flop: FDRE
port map ( D => scan_address_value(9),
Q => scan_address(9),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address10_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(10),
I5 => '1',
O5 => sa_carry_primer(10),
O6 => previous_scan_address(10));
--
scan_address10_xorcy: XORCY
port map( LI => previous_scan_address(10),
CI => scan_address_carry(9),
O => scan_address_value(10));
--
scan_address10_muxcy: MUXCY
port map( DI => sa_carry_primer(10),
CI => scan_address_carry(9),
S => previous_scan_address(10),
O => scan_address_carry(10));
--
scan_address10_flop: FDRE
port map ( D => scan_address_value(10),
Q => scan_address(10),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address11_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(11),
I5 => '1',
O5 => sa_carry_primer(11),
O6 => previous_scan_address(11));
--
scan_address11_xorcy: XORCY
port map( LI => previous_scan_address(11),
CI => scan_address_carry(10),
O => scan_address_value(11));
--
scan_address11_muxcy: MUXCY
port map( DI => sa_carry_primer(11),
CI => scan_address_carry(10),
S => previous_scan_address(11),
O => scan_address_carry(11));
--
scan_address11_flop: FDRE
port map ( D => scan_address_value(11),
Q => scan_address(11),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
serial_data_lut: LUT6
generic map (INIT => X"CACACACACACACACA")
port map( I0 => scan_data(0),
I1 => scan_byte,
I2 => scan_bit(3),
I3 => '1',
I4 => '1',
I5 => '1',
O => serial_data_value);
--
serial_data_flop: FD
port map ( D => serial_data_value,
Q => serial_data,
C => scan_clk);
--
last_bit_flop: FD
port map ( D => last_address,
Q => last_bit,
C => scan_clk);
--
end_of_scan_flop: FD
port map ( D => last_bit,
Q => end_of_scan,
C => scan_clk);
--
scan_complete_flop: FD
port map ( D => end_of_scan,
Q => scan_complete,
C => scan_clk);
--
crc_test <= '0' when (crc = "{CRC_2K}") else '1';
--
scan_error <= crc_check;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
library verilog;
use verilog.vl_types.all;
entity MF_cycloneiiigl_scale_cntr is
port(
clk : in vl_logic;
reset : in vl_logic;
cout : out vl_logic;
high : in vl_logic_vector(31 downto 0);
low : in vl_logic_vector(31 downto 0);
initial_value : in vl_logic_vector(31 downto 0);
mode : in vl_logic_vector(48 downto 1);
ph_tap : in vl_logic_vector(31 downto 0)
);
end MF_cycloneiiigl_scale_cntr;
|
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: instruction.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.0 Build 178 05/31/2012 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY instruction IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END instruction;
ARCHITECTURE SYN OF instruction IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "instruction.mif",
intended_device_family => "Cyclone IV GX",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 8,
width_a => 32,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "instruction.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "instruction.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL instruction.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL instruction.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL instruction.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL instruction.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL instruction_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dcom_uart
-- File: dcom_uart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Asynchronous UART with baud-rate detection.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity dcom_uart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ui : in uart_in_type;
uo : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in dcom_uart_in_type;
uarto : out dcom_uart_out_type
);
end;
architecture rtl of dcom_uart is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBUART, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type rxfsmtype is (idle, startbit, data, stopbit);
type txfsmtype is (idle, data, stopbit);
type uartregs is record
rxen : std_ulogic; -- receiver enabled
dready : std_ulogic; -- data ready
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
thempty : std_ulogic; -- transmitter hold register empty
break : std_ulogic; -- break detected
ovf : std_ulogic; -- receiver overflow
frame : std_ulogic; -- framing error
rhold : std_logic_vector(7 downto 0);
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(10 downto 0);
thold : std_logic_vector(7 downto 0);
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_ulogic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_logic_vector(1 downto 0); -- rx data filtering buffer
rxtick : std_ulogic; -- rx clock (internal)
tick : std_ulogic; -- rx clock (internal)
scaler : std_logic_vector(17 downto 0);
brate : std_logic_vector(17 downto 0);
tcnt : std_logic_vector(1 downto 0); -- autobaud counter
rxf : std_logic_vector(4 downto 0); -- rx data filtering buffer
fedge : std_ulogic; -- rx falling edge
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : uartregs := (
rxen => '0', dready => '0', rsempty => '1', tsempty => '1', thempty => '1',
break => '0', ovf => '0', frame => '0', rhold => (others => '0'),
rshift => (others => '0'), tshift => (others => '1'), thold => (others => '0'),
txstate => idle, txclk => (others => '0'), txtick => '0', rxstate => idle,
rxclk => (others => '0'), rxdb => (others => '0'), rxtick => '0', tick => '0',
scaler => "111111111111111011", brate => (others => '1'), tcnt => (others => '0'),
rxf => (others => '0'), fedge => '0');
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti, ui )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(17 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable irxd : std_ulogic;
variable v : uartregs;
begin
v := r;
v.txtick := '0'; v.rxtick := '0'; v.tick := '0'; rdata := (others => '0');
v.rxdb(1) := r.rxdb(0);
-- scaler
if r.tcnt = "11" then scaler := r.scaler - 1;
else scaler := r.scaler + 1; end if;
if r.tcnt /= "11" then
if (r.rxdb(1) and not r.rxdb(0)) = '1' then v.fedge := '1'; end if;
if (r.fedge) = '1' then
v.scaler := scaler;
if (v.scaler(17) and not r.scaler(16)) = '1' then
v.scaler := "111111111111111011";
v.fedge := '0'; v.tcnt := "00";
end if;
end if;
if (r.rxdb(1) and r.fedge and not r.rxdb(0)) = '1' then
if (r.brate(17 downto 4)> r.scaler(17 downto 4)) then
v.brate := r.scaler; v.tcnt := "00";
end if;
v.scaler := "111111111111111011";
if (r.brate(17 downto 4) = r.scaler(17 downto 4)) then
v.tcnt := r.tcnt + 1;
if r.tcnt = "10" then
v.brate := "0000" & r.scaler(17 downto 4);
v.scaler := v.brate; v.rxen := '1';
end if;
end if;
end if;
else
if (r.break and r.rxdb(1)) = '1' then
v.scaler := "111111111111111011";
v.brate := (others => '1'); v.tcnt := "00";
v.break := '0'; v.rxen := '0';
end if;
end if;
if r.rxen = '1' then
v.scaler := scaler;
v.tick := scaler(15) and not r.scaler(15);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- read/write registers
if uarti.read = '1' then v.dready := '0'; end if;
case apbi.paddr(3 downto 2) is
when "01" =>
rdata(9 downto 0) := r.tcnt & r.rxdb(0) & r.frame & '0' & r.ovf &
r.break & r.thempty & r.tsempty & r.dready;
when "10" =>
rdata(1 downto 0) := (r.tcnt(1) or r.tcnt(0)) & r.rxen;
when others =>
rdata(17 downto 0) := r.brate;
end case;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
v.frame := apbi.pwdata(6);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "10" =>
v.tcnt := apbi.pwdata(1) & apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "11" =>
v.brate := apbi.pwdata(17 downto 0);
v.scaler := apbi.pwdata(17 downto 0);
when others =>
end case;
end if;
-- tx clock
txclk := r.txclk + 1;
if r.tick = '1' then
v.txclk := txclk; v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
rxclk := r.rxclk + 1;
if r.tick = '1' then
v.rxclk := rxclk; v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
-- filter rx data
v.rxf(1 downto 0) := r.rxf(0) & ui.rxd; -- meta-stability filter
if ((r.tcnt /= "11") and (r.scaler(0 downto 0) = "1")) or
((r.tcnt = "11") and (r.tick = '1'))
then v.rxf(4 downto 2) := r.rxf(3 downto 1); end if;
v.rxdb(0) := (r.rxf(4) and r.rxf(3)) or (r.rxf(4) and r.rxf(2)) or
(r.rxf(3) and r.rxf(2));
irxd := r.rxdb(0);
-- transmitter operation
case r.txstate is
when idle => -- idle state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if (r.rxen and (not r.thempty) and r.txtick) = '1' then
v.tshift := "10" & r.thold & '0'; v.txstate := data;
v.thempty := '1';
v.tsempty := '0'; v.txclk := "00" & r.tick; v.txtick := '0';
end if;
when data => -- transmitt data frame
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1);
if r.tshift(10 downto 1) = "1111111110" then
v.tshift(0) := '1'; v.txstate := stopbit;
end if;
end if;
when stopbit => -- transmitt stop bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1); v.txstate := idle;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if uarti.write = '1' then
v.thold := uarti.data(7 downto 0); v.thempty := '0';
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((not r.rsempty) and not r.dready) = '1' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
if (r.rxen and r.rxdb(1) and (not irxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if irxd = '0' then
v.rshift := irxd & r.rshift(7 downto 1); v.rxstate := data;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.rshift := irxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
v.rxstate := stopbit;
end if;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
if irxd = '1' then
v.rsempty := '0';
if v.dready = '0' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
else
if r.rshift = "00000000" then
v.break := '1'; -- break
else
v.frame := '1'; -- framing error
end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
end case;
-- reset operation
if not RESET_ALL and rst = '0' then
v.frame := RES.frame; v.rsempty := RES.rsempty;
v.ovf := RES.ovf; v.break := RES.break; v.thempty := RES.thempty;
v.tsempty := RES.tsempty; v.dready := RES.dready; v.fedge := RES.fedge;
v.txstate := RES.txstate; v.rxstate := RES.rxstate; v.tshift(0) := RES.tshift(0);
v.scaler := RES.scaler; v.brate := RES.brate;
v.rxen := RES.rxen; v.tcnt := RES.tcnt;
v.txclk := RES.txclk; v.rxclk := RES.rxclk;
end if;
-- update registers
rin <= v;
-- drive outputs
uo.txd <= r.tshift(0);
uo.scaler(31 downto 18) <= (others => '0');
uo.scaler(17 downto 0) <= r.brate;
uo.rtsn <= '0';
uo.rxen <= andv(r.tcnt);
uarto.dready <= r.dready;
uarto.tsempty <= r.tsempty;
uarto.thempty <= r.thempty;
uarto.lock <= r.tcnt(1) and r.tcnt(0);
uarto.enable <= r.rxen;
uarto.data <= r.rhold;
uo.txen <= '1'; uo.flow <= '0';
apbo.prdata <= rdata;
end process;
apbo.pirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
-- Sync. registers not reset
r.rxf <= rin.rxf;
end if;
end if;
end process;
end;
|
-- Pegelgetaktetes D-FF mit Reset
-- Automatenebene, 2-Prozess-Variante
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PDFF_R_RK is
Port ( c : in bit;
D: in bit;
R: in bit; -- Reset
y: out bit;
ny : out bit
);
end PDFF_R_RK;
--
-- Reset via RK ------------------------------------------------------------
--
architecture Automatenspek of PDFF_R_RK is
type Zustaende is (Za, Zb); -- Aufzhlungstyp
signal Z, Z_folge : Zustaende;
signal X : bit_vector (1 downto 0);
signal yInt : bit;
begin
-- Zustandsberfhrungs- und Ausgabefunktion
X <= (c,D);
Delta: process (X,Z)
begin
case Z is
when Za => yInt <= '0';
if X = "11" then Z_folge <= Zb;
else Z_folge <= Za;
end if;
when Zb => yInt <= '1';
if X = "10" then Z_folge <= Za;
else Z_folge <= Zb;
end if;
end case;
end process Delta;
-- RK (direkte Rckfhrung):
RK: process (Z_folge, R)
begin
if R = '1' then Z <= Za ;
else Z <= Z_folge;
end if;
end process RK;
y <= yInt;
-- inv. Ausgang:
ny <= not yInt;
end Automatenspek; |
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_bitcoin_miner
-- expander_tb.vhd is part of DS_bitcoin_miner.
-- DS_bitcoin_miner is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- DS_bitcoin_miner is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all; -- std_logic
use ieee.std_logic_arith.all; -- signed/unsigned, conv_integer(), conv_std_logic_vector(signal, no. bit)
use ieee.numeric_std.all; -- to_integer()
entity expander_tb is
end entity expander_tb;
architecture behav of expander_tb is
signal s_clk : std_ulogic;
signal s_rstn : std_ulogic;
signal s_exp_sel1 : std_ulogic;
signal s_M_i_j : std_ulogic_vector(31 downto 0);
signal s_W_i_j : std_ulogic_vector(31 downto 0);
component expander is
port (
clk : in std_ulogic; -- clock
rstn : in std_ulogic; -- asynchronous active low reset
exp_sel1 : in std_ulogic; -- select signal for exp_mux1
M_i_j : in std_ulogic_vector(31 downto 0); -- 32-bit word of the i-th message block
W_i_j : out std_ulogic_vector(31 downto 0) -- 32-bit W_i_j
);
end component expander;
begin
-- Instantiate the Unit Under Test (UUT)
UUT : expander
port map (
clk => s_clk,
rstn => s_rstn,
exp_sel1 => s_exp_sel1,
M_i_j => s_M_i_j,
W_i_j => s_W_i_j
);
-- s_clk signal generation
s_clk_proc : process
begin
s_clk <= '1',
'0' after 10 ns; --50MHz
wait for 20 ns;
end process;
-- rstn signal generation
s_rstn_proc : process
begin
s_rstn <= '0',
'1' after 25 ns;
wait;
end process;
s_exp_sel1_proc : process
begin
s_exp_sel1 <= '0',
'1' after 361 ns;
wait;
end process;
s_M_i_j_proc : process
begin
s_M_i_j <= (others => 'Z'),
x"666f6f62" after 41 ns,
x"61726161" after 61 ns,
x"61616161" after 81 ns;
wait;
end process;
end architecture behav;
|
library verilog;
use verilog.vl_types.all;
entity div_pipelined_latch is
generic(
N : integer := 4
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREMOVE : in vl_logic;
iPREVIOUS_VALID : in vl_logic;
oPREVIOUS_BUSY : out vl_logic;
iPREVIOUS_SIGN : in vl_logic;
iPREVIOUS_DIVISOR: in vl_logic_vector(31 downto 0);
iPREVIOUS_DIVIDEND: in vl_logic_vector(31 downto 0);
iPREVIOUS_Q : in vl_logic_vector;
iPREVIOUS_R : in vl_logic_vector(30 downto 0);
oNEXT_VALID : out vl_logic;
iNEXT_BUSY : in vl_logic;
oNEXT_SIGN : out vl_logic;
oNEXT_DIVISOR : out vl_logic_vector(31 downto 0);
oNEXT_DIVIDEND : out vl_logic_vector(31 downto 0);
oNEXT_Q : out vl_logic_vector;
oNEXT_R : out vl_logic_vector(30 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of N : constant is 1;
end div_pipelined_latch;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
SIGNAL wr_d_sel : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_4_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
gen_fifo_stim: IF(C_CH_TYPE /= 2) GENERATE
-- DIN_WIDTH < DOUT_WIDTH
gen_din_lt_dout: IF(C_DIN_WIDTH < C_DOUT_WIDTH) GENERATE
BEGIN
pr_w_en <= (AND_REDUCE(wr_d_sel)) AND PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DOUT_WIDTH-C_DIN_WIDTH*conv_integer(wr_d_sel)-1 DOWNTO C_DOUT_WIDTH-C_DIN_WIDTH*(conv_integer(wr_d_sel)+1));
PROCESS(WR_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
wr_d_sel <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK = '1') THEN
IF(FULL = '0' AND PRC_WR_EN = '1') THEN
wr_d_sel <= wr_d_sel + "1";
END IF;
END IF;
END PROCESS;
END GENERATE gen_din_lt_dout;
-- DIN_WIDTH >= DOUT_WIDTH
gen_din_gteq_dout:IF(C_DIN_WIDTH >= C_DOUT_WIDTH) GENERATE
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END GENERATE gen_din_gteq_dout;
END GENERATE gen_fifo_stim;
----------------------------------------------
-- Wiring logic stimulus generation
----------------------------------------------
gen_wiring_stim: IF (C_CH_TYPE = 2) GENERATE
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
pr_w_en <= PRC_WR_EN;
END GENERATE gen_wiring_stim;
END ARCHITECTURE;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
pb <= pb_buf;
dpUCECHO: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
if ( pd >= 97 ) and ( pd <= 122)
then
pb_buf <= pd - 32;
else
pb_buf <= pd;
end if;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
pb <= pb_buf;
dpUCECHO: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
if ( pd >= 97 ) and ( pd <= 122)
then
pb_buf <= pd - 32;
else
pb_buf <= pd;
end if;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
pb <= pb_buf;
dpUCECHO: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
if ( pd >= 97 ) and ( pd <= 122)
then
pb_buf <= pd - 32;
else
pb_buf <= pd;
end if;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
pb <= pb_buf;
dpUCECHO: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
if ( pd >= 97 ) and ( pd <= 122)
then
pb_buf <= pd - 32;
else
pb_buf <= pd;
end if;
end if;
end process dpUCECHO;
end RTL;
|
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