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library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
pb <= pb_buf;
dpUCECHO: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
if ( pd >= 97 ) and ( pd <= 122)
then
pb_buf <= pd - 32;
else
pb_buf <= pd;
end if;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
pb <= pb_buf;
dpUCECHO: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
if ( pd >= 97 ) and ( pd <= 122)
then
pb_buf <= pd - 32;
else
pb_buf <= pd;
end if;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
pb <= pb_buf;
dpUCECHO: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
if ( pd >= 97 ) and ( pd <= 122)
then
pb_buf <= pd - 32;
else
pb_buf <= pd;
end if;
end if;
end process dpUCECHO;
end RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DEL is port(
D : in std_logic;
E : in std_logic;
Q : out std_logic
);
end DEL;
architecture behavior of DEL is
signal S : std_logic;
begin
Main : process (D, E)
begin
if(E='1') then
S <= D;
end if;
end process;
Q <= S;
end behavior;
|
----
-- This file is part of etip-ss11-g07.
--
-- Copyright (C) 2011 Lukas Märdian <[email protected]>
-- Copyright (C) 2011 M. S.
-- Copyright (C) 2011 Orest Tarasiuk <[email protected]>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
----
LIBRARY ieee;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
ENTITY BINBCD IS
PORT(
clk : IN std_logic;
bin_input : IN std_logic_vector (16 DOWNTO 0);
einer, zehner, hunderter, tausender, zehntausender : OUT std_logic_vector (3 DOWNTO 0);
overflow : OUT std_logic
);
END BINBCD;
ARCHITECTURE DoubleDabbleV3 OF BINBCD IS
SIGNAL int_input : integer := 0;
BEGIN
int_input <= to_integer(unsigned(bin_input));
IF (int_input <= 99999) THEN
overflow := '0';
ELSE
overflow := '1';
einer := "0000";
zehner := "0000";
hunderter := "0000";
tausender := "0000";
zehntausender := "0000";
END IF;
PROCESS(clk)
VARIABLE vector: std_logic_vector(36 DOWNTO 0) := "00000000000000000000" & bin_input;
VARIABLE int_bcd_seg : integer := 0;
BEGIN
IF (rising_edge(clk)) AND (overflow = '0') THEN
FOR i IN 0 TO 17 LOOP
-- Prüfen, ob größergleich 5; falls ja, dann 3 addieren für:
-- Zehntausender
int_bcd_seg <= to_integer(unsigned(vector(3 DOWNTO 0)));
IF (int_bcd_seg >= 5) THEN
vector(3 DOWNTO 0) <= std_logic_vector(to_unsigned(int_bcd_seg + 3));
END IF;
-- Tausender
int_bcd_seg <= to_integer(unsigned(vector(7 DOWNTO 4)));
IF (int_bcd_seg >= 5) THEN
vector(7 DOWNTO 4) <= std_logic_vector(to_unsigned(int_bcd_seg + 3));
END IF;
-- Hunderter
int_bcd_seg <= to_integer(unsigned(vector(11 DOWNTO 8)));
IF (int_bcd_seg >= 5) THEN
vector(11 DOWNTO 8) <= std_logic_vector(to_unsigned(int_bcd_seg + 3));
END IF;
-- Zehner
int_bcd_seg <= to_integer(unsigned(vector(15 DOWNTO 12)));
IF (int_bcd_seg >= 5) THEN
vector(15 DOWNTO 12) <= std_logic_vector(to_unsigned(int_bcd_seg + 3));
END IF;
-- Einer
int_bcd_seg <= to_integer(unsigned(vector(19 DOWNTO 16)));
IF (int_bcd_seg >= 5) THEN
vector(19 DOWNTO 16) <= std_logic_vector(to_unsigned(int_bcd_seg + 3));
END IF;
-- Shiften:
vector := vector(35 DOWNTO 0) & '0';
END LOOP;
-- Ergebnisse in die jeweiligen Stellen schreiben
zehntausender <= vector(3 DOWNTO 0);
tausender <= vector(7 DOWNTO 4);
hunderter <= vector(11 DOWNTO 8);
zehner <= vector(15 DOWNTO 12);
einer <= vector(19 DOWNTO 16);
END IF;
END PROCESS;
END DoubleDabbleV3;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc946.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n01i00946ent IS
END c06s01b00x00p10n01i00946ent;
ARCHITECTURE c06s01b00x00p10n01i00946arch OF c06s01b00x00p10n01i00946ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
variable V1: BOOLEAN;
BEGIN
V1 := (RE1=>TRUE).RE1;
-- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s01b00x00p10n01i00946 - Prefix of a selected name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n01i00946arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc946.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n01i00946ent IS
END c06s01b00x00p10n01i00946ent;
ARCHITECTURE c06s01b00x00p10n01i00946arch OF c06s01b00x00p10n01i00946ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
variable V1: BOOLEAN;
BEGIN
V1 := (RE1=>TRUE).RE1;
-- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s01b00x00p10n01i00946 - Prefix of a selected name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n01i00946arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc946.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n01i00946ent IS
END c06s01b00x00p10n01i00946ent;
ARCHITECTURE c06s01b00x00p10n01i00946arch OF c06s01b00x00p10n01i00946ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
variable V1: BOOLEAN;
BEGIN
V1 := (RE1=>TRUE).RE1;
-- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s01b00x00p10n01i00946 - Prefix of a selected name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n01i00946arch;
|
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is begin
a <= b;
end block;
-- Violations below
BLOCK_LABEL : block is begin
a <= b; end block;
end architecture RTL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:16:12 03/17/2014
-- Design Name:
-- Module Name: ram - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ram is
end ram;
architecture Behavioral of ram is
begin
end Behavioral;
|
-------------------------------------------------------------------------------
-- Title : D Flip-Flop with synchronous Reset, Set and Clock Enable
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Platform : Xilinx Spartan 3
-------------------------------------------------------------------------------
-- Description:
--
-- D Flip-Flop with Synchronous Reset, Set and Clock Enable.
-- Priority (high to low): reset_p, set_p, ce_p
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dff is
port(
dout_p : out std_logic; -- Data output
din_p : in std_logic; -- Data input
set_p : in std_logic; -- Synchronous set input
reset_p : in std_logic; -- Synchronous reset input
ce_p : in std_logic; -- Clock enable input
clk : in std_logic -- Clock input
);
end dff;
-------------------------------------------------------------------------------
architecture behavioral of dff is
begin
process (clk)
begin
if rising_edge(clk) then
if reset_p = '1' then
dout_p <= '0';
elsif set_p = '1' then
dout_p <= '1';
elsif ce_p = '1' then
dout_p <= din_p;
end if;
end if;
end process;
end behavioral;
|
-------------------------------------------------------------------------------
-- Title : D Flip-Flop with synchronous Reset, Set and Clock Enable
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Platform : Xilinx Spartan 3
-------------------------------------------------------------------------------
-- Description:
--
-- D Flip-Flop with Synchronous Reset, Set and Clock Enable.
-- Priority (high to low): reset_p, set_p, ce_p
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dff is
port(
dout_p : out std_logic; -- Data output
din_p : in std_logic; -- Data input
set_p : in std_logic; -- Synchronous set input
reset_p : in std_logic; -- Synchronous reset input
ce_p : in std_logic; -- Clock enable input
clk : in std_logic -- Clock input
);
end dff;
-------------------------------------------------------------------------------
architecture behavioral of dff is
begin
process (clk)
begin
if rising_edge(clk) then
if reset_p = '1' then
dout_p <= '0';
elsif set_p = '1' then
dout_p <= '1';
elsif ce_p = '1' then
dout_p <= din_p;
end if;
end if;
end process;
end behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tope_rof512_uart is --Entidad
Port ( --17/05/08 cambio I tx_female : out std_logic; --Entidad
LED : out std_logic_vector(7 downto 0);
rx_female : in std_logic; --Entidad
RSTn : in std_logic; --Entidad
clk : in std_logic); --Entidad
end tope_rof512_uart; --Entidad
architecture Comportamiento of tope_rof512_uart is-----------------Arquitectura
--17/05/08 cambio I component uart_tx_plus --comp uart_tx_plus
--17/05/08 cambio I Port ( data_in : in std_logic_vector(7 downto 0);--comp uart_tx_plus
--17/05/08 cambio I write_buffer : in std_logic; --comp uart_tx_plus
--17/05/08 cambio I reset_buffer : in std_logic; --comp uart_tx_plus
--17/05/08 cambio I en_16_x_baud : in std_logic; --comp uart_tx_plus
--17/05/08 cambio I serial_out : out std_logic; --comp uart_tx_plus
--17/05/08 cambio I buffer_data_present : out std_logic; --comp uart_tx_plus
--17/05/08 cambio I buffer_full : out std_logic; --comp uart_tx_plus
--17/05/08 cambio I buffer_half_full : out std_logic; --comp uart_tx_plus
--17/05/08 cambio I clk : in std_logic); --comp uart_tx_plus
--17/05/08 cambio I end component;
component uart_rx --comp uart_rx
Port ( serial_in : in std_logic; --comp uart_rx
data_out : out std_logic_vector(7 downto 0); --comp uart_rx
read_buffer : in std_logic; --comp uart_rx
reset_buffer : in std_logic; --comp uart_rx
en_16_x_baud : in std_logic; --comp uart_rx
buffer_data_present : out std_logic; --comp uart_rx
buffer_full : out std_logic; --comp uart_rx
buffer_half_full : out std_logic; --comp uart_rx
clk : in std_logic); --comp uart_rx
end component; --comp uart_rx
signal cambio : std_logic :='0';
signal Dfilt : std_logic_vector(7 downto 0);
signal interrupt : std_logic :='0'; --señales
signal interrupt_ack : std_logic; --señales
--señales
--señales
signal baud_count : integer range 0 to 26 :=0; --señales
signal en_16_x_baud : std_logic; --señales
signal write_to_uart : std_logic; --señales
signal tx_data_present : std_logic; --señales
signal tx_full : std_logic; --señales
signal tx_half_full : std_logic; --señales
signal read_from_uart : std_logic :='0'; --señales
signal rx_data : std_logic_vector(7 downto 0); --señales
signal rx_data_present : std_logic; --señales
signal rx_full : std_logic; --señales
signal rx_half_full : std_logic; --señales
--señales
signal previous_rx_half_full : std_logic; --señales
signal rx_half_full_event : std_logic; --señales
begin --------------------------------------------- Comienzo de procesos y portmaps
interrupt_control: process(clk) --Control de transmisión
begin --Control de transmisión
if clk'event and clk='1' then --Control de transmisión
--Control de transmisión
-- detect change in state of the 'rx_half_full' flag. --Control de transmisión
previous_rx_half_full <= rx_half_full; --Control de transmisión
rx_half_full_event <= previous_rx_half_full xor rx_half_full;--Control de transmisión
--Control de transmisión
-- processor interrupt waits for an acknowledgement --Control de transmisión
if interrupt_ack='1' then --Control de transmisión
interrupt <= '0'; --Control de transmisión
elsif rx_half_full_event='1' then --Control de transmisión
interrupt <= '1'; --Control de transmisión
else --Control de transmisión
interrupt <= interrupt; --Control de transmisión
end if; --Control de transmisión
--Control de transmisión
end if; --Control de transmisión
end process interrupt_control; --Control de transmisión
--17/05/08 cambio I transmit: uart_tx_plus
--17/05/08 cambio I port map ( data_in => rx_data,
--17/05/08 cambio I write_buffer => rx_data_present,
--17/05/08 cambio I reset_buffer => '0',
--17/05/08 cambio I en_16_x_baud => en_16_x_baud,
--17/05/08 cambio I serial_out => tx_female,
--17/05/08 cambio I buffer_data_present => tx_data_present,--Pruebo: desconectado
--17/05/08 cambio I buffer_full => tx_full, --Pruebo: desconectado
--17/05/08 cambio I buffer_half_full => tx_half_full, --Pruebo: desconectado
--17/05/08 cambio I clk => clk );
--17/05/08 cambio I
receive: uart_rx
port map ( serial_in => rx_female,
data_out => rx_data,
read_buffer => read_from_uart, -- Atención:fijar read_from_uart (indica lectura en el macro)
reset_buffer => '0',
en_16_x_baud => en_16_x_baud,
buffer_data_present => rx_data_present,--Pruebo: desconectado
buffer_full => rx_full, --Pruebo: desconectado
buffer_half_full => rx_half_full, --Pruebo: desconectado
clk => clk );
LED(7) <= cambio;
LED(6) <= rx_data(6);
LED(5) <= rx_data(5);
LED(4) <= rx_data(4);
LED(3) <= rx_data(3);
LED(2) <= rx_data(2);
LED(1) <= rx_data(1);
LED(0) <= rx_data(0);
toggle: process(rx_data_present)
begin
if rx_data_present'event and rx_data_present='1' then
if cambio='0' then
cambio <= '1';
else
cambio <= '0';
end if;
else
end if;
end process toggle;
baud_timer: process(clk) --Generación de en_16_x_baud
begin --Generación de en_16_x_baud
if clk'event and clk='1' then --Generación de en_16_x_baud
if baud_count=26 then --Generación de en_16_x_baud
baud_count <= 0; --Generación de en_16_x_baud
en_16_x_baud <= '1'; --Generación de en_16_x_baud
else --Generación de en_16_x_baud
baud_count <= baud_count + 1; --Generación de en_16_x_baud
en_16_x_baud <= '0'; --Generación de en_16_x_baud
end if; --Generación de en_16_x_baud
end if; --Generación de en_16_x_baud
end process baud_timer; --Generación de en_16_x_baud
inicio: process(rx_female)
begin
if rx_female'event and rx_female='0' then
read_from_uart <= '1';
else
end if;
end process inicio;
end Comportamiento;
|
--!
--! @file: pkg_my_data_types.vhd
--! @brief:
--! @author: Antonio Gutierrez
--! @date: 2013-10-24
--!
--!
--------------------------------------
package my_data_types is
type matrix is array of (natural range<>, natural range<>) of std_logic;
end package my_data_types;
------------------------------
package body my_data_types is
--functionsdefinitions
end package body my_data_types;
--------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity PHPE_MOD is
generic (
-- IO-REQ: 15 DWORD
WB_CONF_OFFSET: std_logic_vector(15 downto 2) := "00000000000000";
WB_CONF_DATA: std_logic_vector(15 downto 0) := "0000000000000110";
WB_ADDR_OFFSET: std_logic_vector(15 downto 2) := "00000000000000"
);
port (
CLK100: in std_logic;
WB_CLK: in std_logic;
WB_RST: in std_logic;
WB_ADDR: in std_logic_vector(15 downto 2);
WB_DATA_OUT: out std_logic_vector(31 downto 0);
WB_DATA_IN: in std_logic_vector(31 downto 0);
WB_STB_RD: in std_logic;
WB_STB_WR: in std_logic;
SV : inout std_logic_vector(10 downto 3)
);
end;
architecture rtl of PHPE_MOD is
signal wb_data_mux : std_logic_vector(31 downto 0);
signal pe_reg_top : std_logic_vector(15 downto 0);
signal pe_reg_scan : std_logic_vector(15 downto 0);
signal pe_reg_disch : std_logic_vector(15 downto 0);
signal pe_reg_take : std_logic_vector(15 downto 0);
signal pe_pos_capt_a : std_logic;
signal pe_pos_cnt_a : std_logic_vector(31 downto 0);
signal pe_pos_sin_a : std_logic_vector(31 downto 0);
signal pe_pos_cos_a : std_logic_vector(31 downto 0);
signal pe_area_cnt_a : std_logic_vector(31 downto 0);
signal pe_area_sin_a : std_logic_vector(31 downto 0);
signal pe_area_cos_a : std_logic_vector(31 downto 0);
signal pe_area_pol_a : std_logic;
signal pe_area_flag_a : std_logic;
signal pe_area_state_a : std_logic;
signal pe_pos_capt_b : std_logic;
signal pe_pos_cnt_b : std_logic_vector(31 downto 0);
signal pe_pos_sin_b : std_logic_vector(31 downto 0);
signal pe_pos_cos_b : std_logic_vector(31 downto 0);
signal pe_area_cnt_b : std_logic_vector(31 downto 0);
signal pe_area_sin_b : std_logic_vector(31 downto 0);
signal pe_area_cos_b : std_logic_vector(31 downto 0);
signal pe_area_pol_b : std_logic;
signal pe_area_flag_b : std_logic;
signal pe_area_state_b : std_logic;
signal pe_scan_cnt : std_logic_vector(15 downto 0);
signal pe_scan_cnt_ena : std_logic;
signal pe_scan_cnt_top : std_logic;
signal pe_scan_cnt_disch : std_logic;
signal pe_scan_cnt_take : std_logic;
signal pe_scan_cnt_scan : std_logic;
signal pe_scan_ovs_top : std_logic;
signal pe_scan_ovs : std_logic;
signal pe_trars_cnt : std_logic_vector(4 downto 0);
signal pe_trars_cnt_bot : std_logic;
signal pe_trars_cnt_top : std_logic;
signal pe_scan : std_logic;
signal pe_disch : std_logic;
signal pe_disch_sync : std_logic_vector(2 downto 0);
signal pe_disch_int : std_logic;
signal pe_disch_ack : std_logic;
signal pe_disch_ack_sync : std_logic_vector(1 downto 0);
signal pe_disch_ack_int : std_logic;
signal pe_take : std_logic;
signal pe_take_sync : std_logic_vector(2 downto 0);
signal pe_take_int : std_logic;
signal pe_take_ack : std_logic;
signal pe_take_ack_sync : std_logic_vector(1 downto 0);
signal pe_take_ack_int : std_logic;
signal pe_trars : std_logic;
signal pe_sin : signed(15 downto 0);
signal pe_cos : signed(15 downto 0);
begin
----------------------------------------------------------
--- bus logic
----------------------------------------------------------
P_WB_RD : process(WB_ADDR, WB_STB_RD, pe_reg_top, pe_reg_scan, pe_reg_disch, pe_reg_take,
pe_pos_cnt_a, pe_pos_sin_a, pe_pos_cos_a, pe_area_cnt_a, pe_area_sin_a, pe_area_cos_a, pe_area_pol_a, pe_area_flag_a, pe_area_state_a,
pe_pos_cnt_b, pe_pos_sin_b, pe_pos_cos_b, pe_area_cnt_b, pe_area_sin_b, pe_area_cos_b, pe_area_pol_b, pe_area_flag_b, pe_area_state_b)
begin
pe_pos_capt_a <= '0';
pe_pos_capt_b <= '0';
case WB_ADDR is
when WB_CONF_OFFSET =>
wb_data_mux(15 downto 0) <= WB_CONF_DATA;
wb_data_mux(31 downto 16) <= WB_ADDR_OFFSET & "00";
when WB_ADDR_OFFSET =>
wb_data_mux <= (others => '0');
wb_data_mux(0) <= pe_area_pol_a;
wb_data_mux(1) <= pe_area_state_a;
wb_data_mux(2) <= pe_area_flag_a;
wb_data_mux(8) <= pe_area_pol_b;
wb_data_mux(9) <= pe_area_state_b;
wb_data_mux(10) <= pe_area_flag_b;
when WB_ADDR_OFFSET + 1 =>
wb_data_mux(15 downto 0) <= pe_reg_top;
wb_data_mux(31 downto 16) <= pe_reg_scan;
when WB_ADDR_OFFSET + 2 =>
wb_data_mux(15 downto 0) <= pe_reg_disch;
wb_data_mux(31 downto 16) <= pe_reg_take;
when WB_ADDR_OFFSET + 3 =>
pe_pos_capt_a <= WB_STB_RD;
wb_data_mux <= pe_pos_cnt_a;
when WB_ADDR_OFFSET + 4 =>
wb_data_mux <= pe_pos_sin_a;
when WB_ADDR_OFFSET + 5 =>
wb_data_mux <= pe_pos_cos_a;
when WB_ADDR_OFFSET + 6 =>
wb_data_mux <= pe_area_cnt_a;
when WB_ADDR_OFFSET + 7 =>
wb_data_mux <= pe_area_sin_a;
when WB_ADDR_OFFSET + 8 =>
wb_data_mux <= pe_area_cos_a;
when WB_ADDR_OFFSET + 9 =>
pe_pos_capt_b <= WB_STB_RD;
wb_data_mux <= pe_pos_cnt_b;
when WB_ADDR_OFFSET + 10 =>
wb_data_mux <= pe_pos_sin_b;
when WB_ADDR_OFFSET + 11 =>
wb_data_mux <= pe_pos_cos_b;
when WB_ADDR_OFFSET + 12 =>
wb_data_mux <= pe_area_cnt_b;
when WB_ADDR_OFFSET + 13 =>
wb_data_mux <= pe_area_sin_b;
when WB_ADDR_OFFSET + 14 =>
wb_data_mux <= pe_area_cos_b;
when others =>
wb_data_mux <= (others => '0');
end case;
end process;
P_WB_RD_REG : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
WB_DATA_OUT <= (others => '0');
elsif rising_edge(WB_CLK) then
if WB_STB_RD = '1' then
WB_DATA_OUT <= wb_data_mux;
end if;
end if;
end process;
P_PE_REG_WR : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
pe_reg_top <= (others => '0');
pe_reg_scan <= (others => '0');
pe_reg_disch <= (others => '0');
pe_reg_take <= (others => '0');
pe_area_pol_a <= '0';
pe_area_pol_b <= '0';
elsif rising_edge(WB_CLK) then
if WB_STB_WR = '1' then
case WB_ADDR is
when WB_ADDR_OFFSET =>
pe_area_pol_a <= WB_DATA_IN(0);
pe_area_pol_b <= WB_DATA_IN(8);
when WB_ADDR_OFFSET + 1 =>
pe_reg_top <= WB_DATA_IN(15 downto 0);
pe_reg_scan <= WB_DATA_IN(31 downto 16);
when WB_ADDR_OFFSET + 2 =>
pe_reg_disch <= WB_DATA_IN(15 downto 0);
pe_reg_take <= WB_DATA_IN(31 downto 16);
when others =>
end case;
end if;
end if;
end process;
----------------------------------------------------------
--- cycle counter
----------------------------------------------------------
P_PE_SCAN_CNT : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
pe_scan_cnt <= (others => '0');
elsif rising_edge(wb_clk) then
if pe_scan_cnt_top = '1' then
pe_scan_cnt <= (others => '0');
else
pe_scan_cnt <= pe_scan_cnt + 1;
end if;
end if;
end process;
pe_scan_cnt_ena <= '1' when pe_reg_top /= 0 else '0';
pe_scan_cnt_top <= '1' when pe_scan_cnt = pe_reg_top else '0';
pe_scan_cnt_disch <= '1' when pe_scan_cnt = pe_reg_disch else '0';
pe_scan_cnt_take <= '1' when pe_scan_cnt = pe_reg_take else '0';
pe_scan_cnt_scan <= '1' when pe_scan_cnt = pe_reg_scan else '0';
pe_scan_ovs_top <= '1' when pe_scan_cnt = ("0" & pe_reg_top(15 downto 1)) else '0';
pe_scan_ovs <= pe_scan_cnt_top or pe_scan_ovs_top;
P_PE_TRARS_CNT : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
pe_trars_cnt <= (others => '0');
elsif rising_edge(wb_clk) then
if pe_scan_cnt_ena = '0' then
pe_trars_cnt <= (others => '0');
elsif pe_scan_ovs = '1' then
if pe_trars_cnt_top = '1' then
if pe_scan_cnt_top = '1' then
pe_trars_cnt <= (others => '0');
end if;
else
pe_trars_cnt <= pe_trars_cnt + 1;
end if;
end if;
end if;
end process;
pe_trars_cnt_bot <= '1' when pe_trars_cnt = "00000" else '0';
pe_trars_cnt_top <= '1' when pe_trars_cnt = "10011" else '0';
pe_trars <= pe_trars_cnt(4);
----------------------------------------------------------
--- pulse generator
----------------------------------------------------------
P_PE_DISCH : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
pe_disch <= '0';
elsif rising_edge(wb_clk) then
if pe_scan_cnt_disch = '1' then
pe_disch <= '1';
elsif pe_disch_ack = '1' then
pe_disch <= '0';
end if;
end if;
end process;
P_PE_TAKE : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
pe_take <= '0';
elsif rising_edge(wb_clk) then
if pe_scan_cnt_take = '1' then
pe_take <= '1';
elsif pe_take_ack = '1' then
pe_take <= '0';
end if;
end if;
end process;
P_PE_SCAN : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
pe_scan <= '0';
elsif rising_edge(wb_clk) then
if pe_scan_cnt_scan = '1' then
pe_scan <= '1';
end if;
if pe_scan_cnt_top = '1' then
pe_scan <= '0';
end if;
end if;
end process;
----------------------------------------------------------
--- whichbone <-> pulse with count syncer
----------------------------------------------------------
P_PE_SYNC_WB : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
pe_disch_ack_sync <= (others => '0');
pe_take_ack_sync <= (others => '0');
elsif rising_edge(wb_clk) then
pe_disch_ack_sync <= pe_disch_ack_int & pe_disch_ack_sync(1);
pe_take_ack_sync <= pe_take_ack_int & pe_take_ack_sync(1);
end if;
end process;
pe_disch_ack <= pe_disch_ack_sync(0);
pe_take_ack <= pe_take_ack_sync(0);
P_PE_SYNC_INT : process(wb_rst, clk100)
begin
if wb_rst = '1' then
pe_disch_sync <= (others => '0');
pe_take_sync <= (others => '0');
elsif rising_edge(clk100) then
pe_disch_sync <= pe_disch & pe_disch_sync(2 downto 1);
pe_take_sync <= pe_take & pe_take_sync(2 downto 1);
end if;
end process;
pe_disch_int <= '1' when pe_disch_sync(1 downto 0) = "10" else '0';
pe_disch_ack_int <= pe_disch_sync(0);
pe_take_int <= '1' when pe_take_sync(1 downto 0) = "10" else '0';
pe_take_ack_int <= pe_take_sync(0);
----------------------------------------------------------
--- sincos generator
----------------------------------------------------------
P_PE_SIN_COS : process(pe_trars_cnt)
begin
case pe_trars_cnt is
when "00000" =>
pe_sin <= conv_signed( 0, pe_sin'length);
pe_cos <= conv_signed( 32767, pe_cos'length);
when "00001" =>
pe_sin <= conv_signed( 10126, pe_sin'length);
pe_cos <= conv_signed( 31163, pe_cos'length);
when "00010" =>
pe_sin <= conv_signed( 19260, pe_sin'length);
pe_cos <= conv_signed( 26509, pe_cos'length);
when "00011" =>
pe_sin <= conv_signed( 26509, pe_sin'length);
pe_cos <= conv_signed( 19260, pe_cos'length);
when "00100" =>
pe_sin <= conv_signed( 31163, pe_sin'length);
pe_cos <= conv_signed( 10126, pe_cos'length);
when "00101" =>
pe_sin <= conv_signed( 32767, pe_sin'length);
pe_cos <= conv_signed( 0, pe_cos'length);
when "00110" =>
pe_sin <= conv_signed( 31163, pe_sin'length);
pe_cos <= conv_signed(-10126, pe_cos'length);
when "00111" =>
pe_sin <= conv_signed( 26509, pe_sin'length);
pe_cos <= conv_signed(-19260, pe_cos'length);
when "01000" =>
pe_sin <= conv_signed( 19260, pe_sin'length);
pe_cos <= conv_signed(-26509, pe_cos'length);
when "01001" =>
pe_sin <= conv_signed( 10126, pe_sin'length);
pe_cos <= conv_signed(-31163, pe_cos'length);
when "01010" =>
pe_sin <= conv_signed( 0, pe_sin'length);
pe_cos <= conv_signed(-32767, pe_cos'length);
when "01011" =>
pe_sin <= conv_signed(-10126, pe_sin'length);
pe_cos <= conv_signed(-31163, pe_cos'length);
when "01100" =>
pe_sin <= conv_signed(-19260, pe_sin'length);
pe_cos <= conv_signed(-26509, pe_cos'length);
when "01101" =>
pe_sin <= conv_signed(-26509, pe_sin'length);
pe_cos <= conv_signed(-19260, pe_cos'length);
when "01110" =>
pe_sin <= conv_signed(-31163, pe_sin'length);
pe_cos <= conv_signed(-10126, pe_cos'length);
when "01111" =>
pe_sin <= conv_signed(-32767, pe_sin'length);
pe_cos <= conv_signed( 0, pe_cos'length);
when "10000" =>
pe_sin <= conv_signed(-31163, pe_sin'length);
pe_cos <= conv_signed( 10126, pe_cos'length);
when "10001" =>
pe_sin <= conv_signed(-26509, pe_sin'length);
pe_cos <= conv_signed( 19260, pe_cos'length);
when "10010" =>
pe_sin <= conv_signed(-19260, pe_sin'length);
pe_cos <= conv_signed( 26509, pe_cos'length);
when others =>
pe_sin <= conv_signed(-10126, pe_sin'length);
pe_cos <= conv_signed( 31163, pe_cos'length);
end case;
end process;
----------------------------------------------------------
--- channel instances
----------------------------------------------------------
U_PECHAN_A: entity work.PHPE_CHAN
port map (
RESET => WB_RST,
CLK100 => CLK100,
WB_CLK => WB_CLK,
TRAMS => not SV(8),
AREA => not SV(10),
pe_scan_cnt_top => pe_scan_cnt_top,
pe_scan_ovs_top => pe_scan_ovs_top,
pe_scan_ovs => pe_scan_ovs,
pe_trars_cnt_bot => pe_trars_cnt_bot,
pe_disch_int => pe_disch_int,
pe_take_int => pe_take_int,
pe_sin => pe_sin,
pe_cos => pe_cos,
pe_pos_capt => pe_pos_capt_a,
pe_pos_cnt => pe_pos_cnt_a,
pe_pos_sin => pe_pos_sin_a,
pe_pos_cos => pe_pos_cos_a,
pe_area_pol => pe_area_pol_a,
pe_area_flag => pe_area_flag_a,
pe_area_state => pe_area_state_a,
pe_area_cnt => pe_area_cnt_a,
pe_area_sin => pe_area_sin_a,
pe_area_cos => pe_area_cos_a
);
U_PECHAN_B: entity work.PHPE_CHAN
port map (
RESET => WB_RST,
CLK100 => CLK100,
WB_CLK => WB_CLK,
TRAMS => not SV(7),
AREA => not SV(9),
pe_scan_cnt_top => pe_scan_cnt_top,
pe_scan_ovs_top => pe_scan_ovs_top,
pe_scan_ovs => pe_scan_ovs,
pe_trars_cnt_bot => pe_trars_cnt_bot,
pe_disch_int => pe_disch_int,
pe_take_int => pe_take_int,
pe_sin => pe_sin,
pe_cos => pe_cos,
pe_pos_capt => pe_pos_capt_b,
pe_pos_cnt => pe_pos_cnt_b,
pe_pos_sin => pe_pos_sin_b,
pe_pos_cos => pe_pos_cos_b,
pe_area_pol => pe_area_pol_b,
pe_area_flag => pe_area_flag_b,
pe_area_state => pe_area_state_b,
pe_area_cnt => pe_area_cnt_b,
pe_area_sin => pe_area_sin_b,
pe_area_cos => pe_area_cos_b
);
----------------------------------------------------------
--- output mapping
----------------------------------------------------------
SV(3) <= '0';
SV(4) <= '0';
SV(5) <= pe_scan_cnt_ena and (not pe_scan);
SV(6) <= pe_scan_cnt_ena and (not pe_trars);
end;
|
ENTITY xorer IS
PORT(inSig0 : in BIT;
inSig1 : in BIT;
inSig2 : in BIT;
inSig3 : in BIT;
inSig4 : in BIT;
inSig5 : in BIT;
inSig6 : in BIT;
inSig7 : in BIT;
outSig0 : out BIT;
outSig1 : out BIT;
outSig2 : out BIT;
outSig3 : out BIT);
BEGIN
END ENTITY xorer;
ARCHITECTURE arch OF xorer IS
BEGIN
outSig0 <= (inSig0 xor inSig1);
outSig1 <= (inSig2 xor inSig3);
outSig2 <= (inSig4 xor inSig5);
outSig3 <= (inSig6 xor inSig7);
END ARCHITECTURE arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity INTERPOLATION is
generic
(
width : integer := 8
);
port
(
Clock : in std_logic;
----------------------------------------------------
B31 : in std_logic_vector( width downto 0 );
B33 : in std_logic_vector( width downto 0 );
B35 : in std_logic_vector( width downto 0 );
G32 : in std_logic_vector( width downto 0 );
G34 : in std_logic_vector( width downto 0 );
------------------------------------------------------
B13 : in std_logic_vector( width downto 0 );
B53 : in std_logic_vector( width downto 0 );
G23 : in std_logic_vector( width downto 0 );
G43 : in std_logic_vector( width downto 0 );
----------------------------------------------------
EdgeHorizontal : in std_logic_vector( width downto 0 );
EdgeVertical : in std_logic_vector( width downto 0 );
mytest : out std_logic_vector( width downto 0 );
-------------------------------------------------------------
G : out std_logic_vector( width downto 0 )
);
end INTERPOLATION;
architecture TABLE of INTERPOLATION is
type Column is array( 0 to 6 ) of std_logic_vector( width downto 0 );
type Matrix is array ( 0 to 6 ) of Column;
constant TestMatrix : Matrix :=
(
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" ),
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" ),
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" ),
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" ),
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" ),
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" ),
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" )
);
signal BayerPattern : Matrix;
component CSAFullAdder is
generic
(
width : integer := 8
);
port
(
x_1 : in std_logic_vector( width downto 0 );
x_2 : in std_logic_vector( width downto 0 );
x_3 : in std_logic_vector( width downto 0 );
Sum : out std_logic_vector( width downto 0 );
Carry : out std_logic_vector( width downto 0 )
);
end component;
component CSAHalfAdder is
generic
(
width : integer := 8
);
port
(
x_1 : in std_logic_vector( width downto 0 );
x_2 : in std_logic_vector( width downto 0 );
Sum : out std_logic_vector( width downto 0 );
Carry : out std_logic_vector( width downto 0 )
);
end component;
component absolute
generic
(
width : integer := 8
);
Port
(
x : in std_logic_vector( width downto 0 );
y : out std_logic_vector( width downto 0)
);
end component;
component CalculateG
generic
(
width : integer := 8
);
port
(
-- Difference0 : in std_logic_vector( width + 3 downto 0 );
-- Difference01 : in std_logic_vector( width + 3 downto 0 );
Difference0 : in std_logic_vector( width downto 0 );
Difference01 : in std_logic_vector( width downto 0 );
IHorizontal : in std_logic_vector( width downto 0 );
IVertical : in std_logic_vector( width downto 0 );
Difference7 : in std_logic_vector( width downto 0 );
DifferenceDver : in std_logic_vector( width + 2 downto 0 );
DifferenceDhor : in std_logic_vector( width + 2 downto 0 );
ElementG : out std_logic_vector( width downto 0 )
);
end component;
-----------------------------------------------------------------------------------------------------------------
-- Ehor - Ever
signal Neg0 : std_logic_vector( width downto 0 );
signal Sum0 : std_logic_vector( width downto 0 );
signal Carry0: std_logic_vector( width downto 0 );
signal DifferenceSum0 : std_logic_vector( width + 1 downto 0 );
signal Difference0 : std_logic_vector( width downto 0 );
-- Ever - Ehor
signal Difference01 : std_logic_vector( width downto 0 );
-----------------------------------------------------------------------------------------------
signal NegB33 : std_logic_vector( width downto 0 );
-- | B31 - B33 |
signal Sum1 : std_logic_vector( width downto 0 );
signal Carry1: std_logic_vector( width downto 0 );
signal DifferenceSum1 : std_logic_vector( width + 1 downto 0 );
signal Difference1 : std_logic_vector( width downto 0 );
signal Value1 : std_logic_vector( width downto 0 );
-- | B35 - B33 |
signal Sum2 : std_logic_vector( width downto 0 );
signal Carry2: std_logic_vector( width downto 0 );
signal DifferenceSum2 : std_logic_vector( width + 1 downto 0 );
signal Difference2 : std_logic_vector( width downto 0 );
signal Value2 : std_logic_vector( width downto 0 );
-- | G32 - G34 |
signal Neg3 : std_logic_vector( width downto 0 );
signal Sum3 : std_logic_vector( width downto 0 );
signal Carry3: std_logic_vector( width downto 0 );
signal DifferenceSum3 : std_logic_vector( width + 1 downto 0 );
signal Difference3 : std_logic_vector( width downto 0 );
signal Value3 : std_logic_vector( width downto 0 );
signal SumDhor : std_logic_vector( width downto 0 );
signal CarryDhor : std_logic_vector( width downto 0 );
signal DifferenceSumDhor : std_logic_vector( width + 1 downto 0 );
signal DifferenceDhor : std_logic_vector( width + 2 downto 0 );
---------------------------------------------------------------------------------------------------
-- | B13 - B33 |
signal Sum4 : std_logic_vector( width downto 0 );
signal Carry4: std_logic_vector( width downto 0 );
signal DifferenceSum4 : std_logic_vector( width + 1 downto 0 );
signal Difference4 : std_logic_vector( width downto 0 );
signal Value4 : std_logic_vector( width downto 0 );
-- | B53 - B33 |
signal Sum5 : std_logic_vector( width downto 0 );
signal Carry5: std_logic_vector( width downto 0 );
signal DifferenceSum5 : std_logic_vector( width + 1 downto 0 );
signal Difference5 : std_logic_vector( width downto 0 );
signal Value5 : std_logic_vector( width downto 0 );
-- | G23 - G43 |
signal Neg6 : std_logic_vector( width downto 0 );
signal Sum6 : std_logic_vector( width downto 0 );
signal Carry6: std_logic_vector( width downto 0 );
signal DifferenceSum6 : std_logic_vector( width + 1 downto 0 );
signal Difference6 : std_logic_vector( width downto 0 );
signal Value6 : std_logic_vector( width downto 0 );
signal SumDver : std_logic_vector( width downto 0 );
signal CarryDver : std_logic_vector( width downto 0 );
signal DifferenceSumDver : std_logic_vector( width + 1 downto 0 );
signal DifferenceDver : std_logic_vector( width + 2 downto 0 );
------------------------------------------------------------------------------------------------------
-- calculate IHorizontal
-- ( G32 + G34 ) / 2
signal SumIhor1 : std_logic_vector( width downto 0 );
signal CarryIhor1 : std_logic_vector( width downto 0 );
signal IhorSum1 : std_logic_vector( width + 1 downto 0 );
signal IHorizontal1 : std_logic_vector( width downto 0 );
-- B33 / 4
signal IHorizontal2 : std_logic_vector( width downto 0 );
-- ( B31 + B35 ) / 8
signal SumIhor3 : std_logic_vector( width downto 0 );
signal CarryIhor3 : std_logic_vector( width downto 0 );
signal IhorSum30 : std_logic_vector( width + 1 downto 0 );
signal IhorSum31 : std_logic_vector( width downto 0 );
signal IHorizontal3 : std_logic_vector( width downto 0 );
-- ( G32 + G34 ) / 2 + B33 / 4 + ( B31 + B35 ) / 8
signal SumIhor : std_logic_vector( width downto 0 );
signal CarryIhor : std_logic_vector( width downto 0 );
signal IhorSum : std_logic_vector( width + 1 downto 0 );
signal IHorizontal : std_logic_vector( width downto 0 );
-- calculate IVertical
-- ( G23 + G43 ) / 2
signal SumIver1 : std_logic_vector( width downto 0 );
signal CarryIver1 : std_logic_vector( width downto 0 );
signal IverSum1 : std_logic_vector( width + 1 downto 0 );
signal IVertical1 : std_logic_vector( width downto 0 );
-- B33 / 4
signal IVertical2 : std_logic_vector( width downto 0 );
-- ( B13 + B53 ) / 8
signal SumIver3 : std_logic_vector( width downto 0 );
signal CarryIver3 : std_logic_vector( width downto 0 );
signal IverSum30 : std_logic_vector( width + 1 downto 0 );
signal IverSum31 : std_logic_vector( width downto 0 );
signal IVertical3 : std_logic_vector( width downto 0 );
-- ( G32 + G34 ) / 2 + B33 / 4 + ( B31 + B35 ) / 8
signal SumIver : std_logic_vector( width downto 0 );
signal CarryIver : std_logic_vector( width downto 0 );
signal IverSum : std_logic_vector( width + 1 downto 0 );
signal IVertical : std_logic_vector( width downto 0 );
----------------------------------------------------------------------------------------
-- ( Ihor + Iver ) / 2
signal Sum7 : std_logic_vector( width downto 0 );
signal Carry7: std_logic_vector( width downto 0 );
signal DifferenceSum7 : std_logic_vector( width + 1 downto 0 );
signal Difference7 : std_logic_vector( width downto 0 );
signal ElementG : std_logic_vector( width downto 0 );
begin
BayerPattern( 6 )( 6 ) <= "000000011";
mytest <= BayerPattern( 6 )( 6 );
-- Ehor - Ever
Neg0 <= not EdgeVertical + '1';
Diff0 : CSAHalfAdder port map( EdgeHorizontal, Neg0, Sum0, Carry0 );
DifferenceSum0 <= ( Carry0 & '0' ) + Sum0;
Difference0 <= DifferenceSum0( width downto 0 );
-- Ever - Ehor
Difference01 <= not Difference0 + '1';
---------------------------------------------------------------------------------------------------------------------
NegB33 <= not B33 + '1';
-- | B31 - B33 |
Diff1 : CSAHalfAdder port map( B31, NegB33, Sum1, Carry1 );
DifferenceSum1 <= ( Carry1 & '0' ) + Sum1;
Difference1 <= DifferenceSum1( width downto 0 );
absoulte1 : absolute port map( Difference1, Value1 );
-- | B35 - B33 |
Diff2 : CSAHalfAdder port map( B35, NegB33, Sum2, Carry2 );
DifferenceSum2 <= ( Carry2 & '0' ) + Sum2;
Difference2 <= DifferenceSum2( width downto 0 );
absoulte2 : absolute port map( Difference2, Value2 );
-- | G32 - G34 |
Neg3 <= not G34 + '1';
Diff3 : CSAHalfAdder port map( G32, Neg3, Sum3, Carry3 );
DifferenceSum3 <= ( Carry3 & '0' ) + Sum3;
Difference3 <= DifferenceSum3( width downto 0 );
absoulte3 : absolute port map( Difference3, Value3 );
-- Dver = | B31 - B33 | + | B35 - B33 | + | G32 - G34 |
Dhor : CSAFullAdder port map( Value1, Value2, Value3, SumDhor, CarryDhor );
DifferenceSumDhor <= ( CarryDhor & '0' ) + SumDhor;
DifferenceDhor <= "00" & DifferenceSumDhor( width downto 0 );
---------------------------------------------------------------------------------------------------------------------
-- | B13 - B33 |
Diff4 : CSAHalfAdder port map( B13, NegB33, Sum4, Carry4 );
DifferenceSum4 <= ( Carry4 & '0' ) + Sum4;
Difference4 <= DifferenceSum4( width downto 0 );
absoulte4 : absolute port map( Difference4, Value4 );
-- | B53 - B33 |
Diff5 : CSAHalfAdder port map( B53, NegB33, Sum5, Carry5 );
DifferenceSum5 <= ( Carry5 & '0' ) + Sum5;
Difference5 <= DifferenceSum5( width downto 0 );
absoulte5 : absolute port map( Difference5, Value5 );
-- | G23 - G43 |
Neg6 <= not G43 + '1';
Diff6 : CSAHalfAdder port map( G23, Neg6, Sum6, Carry6 );
DifferenceSum6 <= ( Carry6 & '0' ) + Sum6;
Difference6 <= DifferenceSum6( width downto 0 );
absoulte6 : absolute port map( Difference6, Value6 );
-- Dver = | B13 - B33 | + | B53 - B33 | + | G23 - G43 |
Dver : CSAFullAdder port map( Value4, Value5, Value6, SumDver, CarryDver );
DifferenceSumDver <= ( CarryDver & '0' ) + SumDver;
DifferenceDver <= "00" & DifferenceSumDver( width downto 0 );
-------------------------------------------------------------------------------------------------------------------
-- calculate IHorizontal value
-- ( G32 + G34 ) / 2
Ihor1 : CSAHalfAdder port map( G32, G34, SumIhor1, CarryIhor1 );
IhorSum1 <= ( CarryIhor1 & '0' ) + SumIhor1;
IHorizontal1 <= IhorSum1( width + 1 downto 1 );
-- B33 / 4
IHorizontal2 <= "00" & B33( width downto 2 );
-- ( B31 + B35 ) / 8
Ihor3 : CSAHalfAdder port map( B31, B35, SumIhor3, CarryIhor3 );
IhorSum30 <= ( CarryIhor3 & '0' ) + SumIhor3;
IhorSum31 <= "00" & IhorSum30( width + 1 downto 3 );
IHorizontal3 <= not IhorSum31 + '1';
-- ( G32 + G34 ) / 2 + B33 / 4 + ( B31 + B35 ) / 8
Ihor : CSAFullAdder port map( IHorizontal1, IHorizontal2, IHorizontal3, SumIhor, CarryIhor );
IhorSum <= ( CarryIhor & '0' ) + SumIhor;
IHorizontal <= IhorSum( width downto 0 );
---------------------------------------------------------------------------------------------------------------------
-- calculate IVertical value
-- ( G23 + G43 ) / 2
Iver1 : CSAHalfAdder port map( G23, G43, SumIver1, CarryIver1 );
IverSum1 <= ( CarryIver1 & '0' ) + SumIver1;
IVertical1 <= IverSum1( width + 1 downto 1 );
-- B33 / 4
IVertical2 <= IHorizontal2;
-- ( B13 + B53 ) / 8
Iver3 : CSAHalfAdder port map( B13, B53, SumIver3, CarryIver3 );
IverSum30 <= ( CarryIver3 & '0' ) + SumIver3;
IverSum31 <= "00" & IverSum30( width + 1 downto 3 );
IVertical3 <= not IverSum31 + '1';
-- ( G23 + G43 ) / 2 + B33 / 4 + ( B13 + B53 ) / 8
Iver : CSAFullAdder port map( IVertical1, IVertical2, IVertical3, SumIver, CarryIver );
IverSum <= ( CarryIver & '0' ) + SumIver;
IVertical <= IverSum( width downto 0 );
----------------------------------------------------------------------------------------------------------------
-- ( Ihor + Iver ) / 2
Diff7 : CSAHalfAdder port map( IHorizontal, IVertical, Sum7, Carry7 );
DifferenceSum7 <= ( Carry7 & '0' ) + Sum7;
Difference7 <= DifferenceSum7( width + 1 downto 1 );
PartG : CalculateG port map( Difference0, Difference01, IHorizontal, IVertical, Difference7, DifferenceDver, DifferenceDhor, ElementG );
G <= ElementG;
end TABLE;
|
-- test_ng.vhd
entity TEST_REGS is
generic (
REGS_BITS : integer := 32
);
port (
CLK : in bit;
RST : in bit;
REGS_WEN : in bit_vector(REGS_BITS-1 downto 0);
REGS_WDATA : in bit_vector(REGS_BITS-1 downto 0);
REGS_RDATA : out bit_vector(REGS_BITS-1 downto 0)
);
end TEST_REGS;
architecture RTL of TEST_REGS is
type UNSIGNED is array (NATURAL range <> ) of BIT;
constant NAU: UNSIGNED(0 downto 1) := (others => '0');
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is
begin
return ARG;
end RESIZE;
signal curr_value : unsigned(REGS_BITS-1 downto 0);
signal x : boolean;
begin
REGS_RDATA <= bit_vector(RESIZE(curr_value, REGS_RDATA'length));
x <= regs_rdata'event;
end RTL;
|
-- test_ng.vhd
entity TEST_REGS is
generic (
REGS_BITS : integer := 32
);
port (
CLK : in bit;
RST : in bit;
REGS_WEN : in bit_vector(REGS_BITS-1 downto 0);
REGS_WDATA : in bit_vector(REGS_BITS-1 downto 0);
REGS_RDATA : out bit_vector(REGS_BITS-1 downto 0)
);
end TEST_REGS;
architecture RTL of TEST_REGS is
type UNSIGNED is array (NATURAL range <> ) of BIT;
constant NAU: UNSIGNED(0 downto 1) := (others => '0');
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is
begin
return ARG;
end RESIZE;
signal curr_value : unsigned(REGS_BITS-1 downto 0);
signal x : boolean;
begin
REGS_RDATA <= bit_vector(RESIZE(curr_value, REGS_RDATA'length));
x <= regs_rdata'event;
end RTL;
|
-- VHDL de um contador_transmissao de modulo 16
-- OBS: Para esse experimento so eh utilizada a contagem ate 11
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity contador_transmissao is
port(clock : in std_logic;
enable : in std_logic;
zera : in std_logic;
conta : in std_logic;
contagem : out std_logic_vector(3 downto 0);
fim : out std_logic);
end contador_transmissao;
architecture exemplo of contador_transmissao is
signal IQ: unsigned(3 downto 0);
begin
process (clock, conta, IQ, zera)
begin
if zera = '1' then
IQ <= (others => '0');
elsif clock'event and clock = '1' then
if conta = '1' and enable = '1' then
IQ <= IQ + 1;
end if;
end if;
if IQ = 11 then
fim <= '1';
else
fim <= '0';
end if;
contagem <= std_logic_vector(IQ);
end process;
end exemplo;
|
library ieee;
use ieee.std_logic_1164.all;
library alib;
use alib.acomp;
entity tb2 is
end;
architecture arch of tb2 is
signal a, b : std_logic := '0';
begin
ainst: alib.apkg.acomp
port map (a, b);
process is
begin
a <= '0';
wait for 1 ns;
assert b = '0' report "component is missing" severity failure;
a <= '1';
wait for 1 ns;
assert b = '1' report "component is missing" severity failure;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library alib;
use alib.acomp;
entity tb2 is
end;
architecture arch of tb2 is
signal a, b : std_logic := '0';
begin
ainst: alib.apkg.acomp
port map (a, b);
process is
begin
a <= '0';
wait for 1 ns;
assert b = '0' report "component is missing" severity failure;
a <= '1';
wait for 1 ns;
assert b = '1' report "component is missing" severity failure;
wait;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity apatb_doHist_top is
generic (
AUTOTB_CLOCK_PERIOD_DIV2 : TIME := 5.00 ns;
AUTOTB_TVIN_inStream_V_data_V : STRING := "../tv/cdatafile/c.doHist.autotvin_inStream_V_data_V.dat";
AUTOTB_TVIN_inStream_V_keep_V : STRING := "../tv/cdatafile/c.doHist.autotvin_inStream_V_keep_V.dat";
AUTOTB_TVIN_inStream_V_strb_V : STRING := "../tv/cdatafile/c.doHist.autotvin_inStream_V_strb_V.dat";
AUTOTB_TVIN_inStream_V_user_V : STRING := "../tv/cdatafile/c.doHist.autotvin_inStream_V_user_V.dat";
AUTOTB_TVIN_inStream_V_last_V : STRING := "../tv/cdatafile/c.doHist.autotvin_inStream_V_last_V.dat";
AUTOTB_TVIN_inStream_V_id_V : STRING := "../tv/cdatafile/c.doHist.autotvin_inStream_V_id_V.dat";
AUTOTB_TVIN_inStream_V_dest_V : STRING := "../tv/cdatafile/c.doHist.autotvin_inStream_V_dest_V.dat";
AUTOTB_TVIN_histo : STRING := "../tv/cdatafile/c.doHist.autotvin_histo.dat";
AUTOTB_TVIN_inStream_V_data_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHist.autotvin_inStream_V_data_V.dat";
AUTOTB_TVIN_inStream_V_keep_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHist.autotvin_inStream_V_keep_V.dat";
AUTOTB_TVIN_inStream_V_strb_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHist.autotvin_inStream_V_strb_V.dat";
AUTOTB_TVIN_inStream_V_user_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHist.autotvin_inStream_V_user_V.dat";
AUTOTB_TVIN_inStream_V_last_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHist.autotvin_inStream_V_last_V.dat";
AUTOTB_TVIN_inStream_V_id_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHist.autotvin_inStream_V_id_V.dat";
AUTOTB_TVIN_inStream_V_dest_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHist.autotvin_inStream_V_dest_V.dat";
AUTOTB_TVIN_histo_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHist.autotvin_histo.dat";
AUTOTB_TVOUT_histo : STRING := "../tv/cdatafile/c.doHist.autotvout_histo.dat";
AUTOTB_TVOUT_histo_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHist.autotvout_histo.dat";
AUTOTB_LAT_RESULT_FILE : STRING := "doHist.result.lat.rb";
AUTOTB_PER_RESULT_TRANS_FILE : STRING := "doHist.performance.result.transaction.xml";
LENGTH_inStream_V_data_V : INTEGER := 76800;
LENGTH_inStream_V_keep_V : INTEGER := 76800;
LENGTH_inStream_V_strb_V : INTEGER := 76800;
LENGTH_inStream_V_user_V : INTEGER := 76800;
LENGTH_inStream_V_last_V : INTEGER := 76800;
LENGTH_inStream_V_id_V : INTEGER := 76800;
LENGTH_inStream_V_dest_V : INTEGER := 76800;
LENGTH_histo : INTEGER := 256;
AUTOTB_TRANSACTION_NUM : INTEGER := 1
);
end apatb_doHist_top;
architecture behav of apatb_doHist_top is
signal AESL_clock : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal start : STD_LOGIC := '0';
signal ce : STD_LOGIC;
signal continue : STD_LOGIC := '0';
signal AESL_reset : STD_LOGIC := '0';
signal AESL_start : STD_LOGIC := '0';
signal AESL_ce : STD_LOGIC := '0';
signal AESL_continue : STD_LOGIC := '0';
signal AESL_ready : STD_LOGIC := '0';
signal AESL_idle : STD_LOGIC := '0';
signal AESL_done : STD_LOGIC := '0';
signal AESL_done_delay : STD_LOGIC := '0';
signal AESL_done_delay2 : STD_LOGIC := '0';
signal AESL_ready_delay : STD_LOGIC := '0';
signal ready : STD_LOGIC := '0';
signal ready_wire : STD_LOGIC := '0';
signal CTRL_BUS_AWADDR: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal CTRL_BUS_AWVALID: STD_LOGIC;
signal CTRL_BUS_AWREADY: STD_LOGIC;
signal CTRL_BUS_WVALID: STD_LOGIC;
signal CTRL_BUS_WREADY: STD_LOGIC;
signal CTRL_BUS_WDATA: STD_LOGIC_VECTOR (31 DOWNTO 0);
signal CTRL_BUS_WSTRB: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal CTRL_BUS_ARADDR: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal CTRL_BUS_ARVALID: STD_LOGIC;
signal CTRL_BUS_ARREADY: STD_LOGIC;
signal CTRL_BUS_RVALID: STD_LOGIC;
signal CTRL_BUS_RREADY: STD_LOGIC;
signal CTRL_BUS_RDATA: STD_LOGIC_VECTOR (31 DOWNTO 0);
signal CTRL_BUS_RRESP: STD_LOGIC_VECTOR (1 DOWNTO 0);
signal CTRL_BUS_BVALID: STD_LOGIC;
signal CTRL_BUS_BREADY: STD_LOGIC;
signal CTRL_BUS_BRESP: STD_LOGIC_VECTOR (1 DOWNTO 0);
signal CTRL_BUS_INTERRUPT: STD_LOGIC;
signal ap_clk : STD_LOGIC;
signal ap_rst_n : STD_LOGIC;
signal inStream_TDATA: STD_LOGIC_VECTOR (7 DOWNTO 0);
signal inStream_TVALID: STD_LOGIC;
signal inStream_TREADY: STD_LOGIC;
signal inStream_TKEEP: STD_LOGIC_VECTOR (0 DOWNTO 0);
signal inStream_TSTRB: STD_LOGIC_VECTOR (0 DOWNTO 0);
signal inStream_TUSER: STD_LOGIC_VECTOR (1 DOWNTO 0);
signal inStream_TLAST: STD_LOGIC_VECTOR (0 DOWNTO 0);
signal inStream_TID: STD_LOGIC_VECTOR (4 DOWNTO 0);
signal inStream_TDEST: STD_LOGIC_VECTOR (5 DOWNTO 0);
signal histo_ADDR_A: STD_LOGIC_VECTOR (31 DOWNTO 0);
signal histo_EN_A: STD_LOGIC;
signal histo_WEN_A: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal histo_DIN_A: STD_LOGIC_VECTOR (31 DOWNTO 0);
signal histo_DOUT_A: STD_LOGIC_VECTOR (31 DOWNTO 0);
signal histo_CLK_A: STD_LOGIC;
signal histo_RST_A: STD_LOGIC;
signal ready_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal done_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal ready_initial : STD_LOGIC;
signal ready_initial_n : STD_LOGIC;
signal ready_last_n : STD_LOGIC;
signal ready_delay_last_n : STD_LOGIC;
signal done_delay_last_n : STD_LOGIC;
signal interface_done : STD_LOGIC := '0';
-- Subtype for random state number, to prevent confusing it with true integers
-- Top of range should be (2**31)-1 but this literal calculation causes overflow on 32-bit machines
subtype T_RANDINT is integer range 1 to integer'high;
type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER;
shared variable AESL_mLatCnterIn : latency_record;
shared variable AESL_mLatCnterOut : latency_record;
shared variable AESL_mLatCnterIn_addr : INTEGER;
shared variable AESL_mLatCnterOut_addr : INTEGER;
shared variable AESL_clk_counter : INTEGER;
signal reported_stuck : STD_LOGIC := '0';
shared variable reported_stuck_cnt : INTEGER := 0;
component doHist is
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TKEEP : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
histo_Addr_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
histo_EN_A : OUT STD_LOGIC;
histo_WEN_A : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
histo_Din_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
histo_Dout_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
histo_Clk_A : OUT STD_LOGIC;
histo_Rst_A : OUT STD_LOGIC;
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
interrupt : OUT STD_LOGIC);
end component;
signal bramhisto_Clk_A, bramhisto_Clk_B : STD_LOGIC;
signal bramhisto_Rst_A, bramhisto_Rst_B : STD_LOGIC;
signal bramhisto_EN_A, bramhisto_EN_B : STD_LOGIC;
signal bramhisto_WEN_A, bramhisto_WEN_B : STD_LOGIC_VECTOR(4 - 1 downto 0);
signal bramhisto_Addr_A, bramhisto_Addr_B : STD_LOGIC_VECTOR(31 downto 0);
signal bramhisto_Din_A, bramhisto_Din_B : STD_LOGIC_VECTOR(31 downto 0);
signal bramhisto_Dout_A, bramhisto_Dout_B : STD_LOGIC_VECTOR(31 downto 0);
signal bramhisto_ready : STD_LOGIC;
signal bramhisto_done : STD_LOGIC;
component AESL_autobram_histo is
port(
Clk_A : IN STD_LOGIC;
Rst_A : IN STD_LOGIC;
EN_A : IN STD_LOGIC;
WEN_A : IN STD_LOGIC_VECTOR;
Addr_A : IN STD_LOGIC_VECTOR;
Din_A : IN STD_LOGIC_VECTOR;
Dout_A : OUT STD_LOGIC_VECTOR;
Clk_B : IN STD_LOGIC;
Rst_B : IN STD_LOGIC;
EN_B : IN STD_LOGIC;
WEN_B : IN STD_LOGIC_VECTOR;
Addr_B : IN STD_LOGIC_VECTOR;
Din_B : IN STD_LOGIC_VECTOR;
Dout_B : OUT STD_LOGIC_VECTOR;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
signal inStream_ready : STD_LOGIC := '0';
signal inStream_done : STD_LOGIC := '0';
signal axi_s_inStream_TVALID : STD_LOGIC := '0';
signal axi_s_inStream_TREADY : STD_LOGIC := '0';
signal reg_inStream_TVALID : STD_LOGIC := '0';
signal reg_inStream_TREADY : STD_LOGIC := '0';
signal ap_c_n_tvin_trans_num_inStream_V_data_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32);
signal ap_c_n_tvin_trans_num_inStream_V_keep_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32);
signal ap_c_n_tvin_trans_num_inStream_V_strb_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32);
signal ap_c_n_tvin_trans_num_inStream_V_user_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32);
signal ap_c_n_tvin_trans_num_inStream_V_last_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32);
signal ap_c_n_tvin_trans_num_inStream_V_id_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32);
signal ap_c_n_tvin_trans_num_inStream_V_dest_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32);
signal inStream_ready_reg : STD_LOGIC := '0';
component AESL_axi_s_inStream is
port(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
TRAN_inStream_TDATA : OUT STD_LOGIC_VECTOR;
inStream_TDATA_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TKEEP : OUT STD_LOGIC_VECTOR;
inStream_TKEEP_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TSTRB : OUT STD_LOGIC_VECTOR;
inStream_TSTRB_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TUSER : OUT STD_LOGIC_VECTOR;
inStream_TUSER_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TLAST : OUT STD_LOGIC_VECTOR;
inStream_TLAST_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TID : OUT STD_LOGIC_VECTOR;
inStream_TID_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TDEST : OUT STD_LOGIC_VECTOR;
inStream_TDEST_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TVALID : OUT STD_LOGIC;
TRAN_inStream_TREADY : IN STD_LOGIC;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
signal AESL_slave_output_done : STD_LOGIC;
signal AESL_slave_start : STD_LOGIC;
signal AESL_slave_write_start_in : STD_LOGIC;
signal AESL_slave_write_start_finish : STD_LOGIC;
signal AESL_slave_ready : STD_LOGIC;
signal slave_start_status : STD_LOGIC := '0';
signal start_rise : STD_LOGIC := '0';
signal ready_rise : STD_LOGIC := '0';
signal slave_done_status : STD_LOGIC := '0';
component AESL_AXI_SLAVE_CTRL_BUS is
port(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_AWADDR : OUT STD_LOGIC_VECTOR;
TRAN_s_axi_CTRL_BUS_AWVALID : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_AWREADY : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_WVALID : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_WREADY : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_WDATA : OUT STD_LOGIC_VECTOR;
TRAN_s_axi_CTRL_BUS_WSTRB : OUT STD_LOGIC_VECTOR;
TRAN_s_axi_CTRL_BUS_ARADDR : OUT STD_LOGIC_VECTOR;
TRAN_s_axi_CTRL_BUS_ARVALID : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_ARREADY : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_RVALID : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_RREADY : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_RDATA : IN STD_LOGIC_VECTOR;
TRAN_s_axi_CTRL_BUS_RRESP : IN STD_LOGIC_VECTOR;
TRAN_s_axi_CTRL_BUS_BVALID : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_BREADY : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_BRESP : IN STD_LOGIC_VECTOR;
TRAN_CTRL_BUS_interrupt : IN STD_LOGIC;
TRAN_CTRL_BUS_ready_out : OUT STD_LOGIC;
TRAN_CTRL_BUS_ready_in : IN STD_LOGIC;
TRAN_CTRL_BUS_done_out : OUT STD_LOGIC;
TRAN_CTRL_BUS_idle_out : OUT STD_LOGIC;
TRAN_CTRL_BUS_write_start_in : IN STD_LOGIC;
TRAN_CTRL_BUS_write_start_finish : OUT STD_LOGIC;
TRAN_CTRL_BUS_transaction_done_in : IN STD_LOGIC;
TRAN_CTRL_BUS_start_in : IN STD_LOGIC
);
end component;
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when 'x' | 'X' => ret := ret(data_width - 5 downto 0) & "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when 'x' | 'X' => ret := "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when 'x' | 'X' => ret := "XXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when 'x' | 'X' => ret := "XX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when 'x' | 'X' => ret := "X";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_str_dec2int (RHS : STRING) return INTEGER is
variable ret : integer;
variable idx : integer := 1;
begin
ret := 0;
while true loop
case RHS(idx) is
when '0' => ret := ret * 10 + 0;
when '1' => ret := ret * 10 + 1;
when '2' => ret := ret * 10 + 2;
when '3' => ret := ret * 10 + 3;
when '4' => ret := ret * 10 + 4;
when '5' => ret := ret * 10 + 5;
when '6' => ret := ret * 10 + 6;
when '7' => ret := ret * 10 + 7;
when '8' => ret := ret * 10 + 8;
when '9' => ret := ret * 10 + 9;
when ' ' => return ret;
when others => report "Wrong dec char " & RHS(idx); return ret;
end case;
idx := idx + 1;
end loop;
return ret;
end esl_str_dec2int;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
end loop;
return ret;
end function;
-- purpose: initialise the random state variable based on an integer seed
function init_rand(seed : integer) return T_RANDINT is
variable result : T_RANDINT;
begin
-- If the seed is smaller than the minimum value of the random state variable, use the minimum value
if seed < T_RANDINT'low then
result := T_RANDINT'low;
-- If the seed is larger than the maximum value of the random state variable, use the maximum value
elsif seed > T_RANDINT'high then
result := T_RANDINT'high;
-- If the seed is within the range of the random state variable, just use the seed
else
result := seed;
end if;
-- Return the result
return result;
end init_rand;
-- purpose: generate a random integer between min and max limits
procedure rand_int(variable rand : inout T_RANDINT;
constant minval : in integer;
constant maxval : in integer;
variable result : out integer
) is
variable k, q : integer;
variable real_rand : real;
variable res : integer;
begin
-- Create a new random integer in the range 1 to 2**31-1 and put it back into rand VARIABLE
-- Based on an example from Numerical Recipes in C, 2nd Edition, page 279
k := rand/127773;
q := 16807*(rand-k*127773)-2836*k;
if q < 0 then
q := q + 2147483647;
end if;
rand := init_rand(q);
-- Convert this integer to a real number in the range 0 to 1
real_rand := (real(rand - T_RANDINT'low)) / real(T_RANDINT'high - T_RANDINT'low);
-- Convert this real number to an integer in the range minval to maxval
-- The +1 and -0.5 are to get equal probability of minval and maxval as other values
res := integer((real_rand * real(maxval+1-minval)) - 0.5) + minval;
-- VHDL real to integer conversion doesn't define what happens for x.5 so deal with this
if res < minval then
res := minval;
elsif res > maxval then
res := maxval;
end if;
-- assign output
result := res;
end rand_int;
begin
AESL_inst_doHist : doHist port map (
s_axi_CTRL_BUS_AWADDR => CTRL_BUS_AWADDR,
s_axi_CTRL_BUS_AWVALID => CTRL_BUS_AWVALID,
s_axi_CTRL_BUS_AWREADY => CTRL_BUS_AWREADY,
s_axi_CTRL_BUS_WVALID => CTRL_BUS_WVALID,
s_axi_CTRL_BUS_WREADY => CTRL_BUS_WREADY,
s_axi_CTRL_BUS_WDATA => CTRL_BUS_WDATA,
s_axi_CTRL_BUS_WSTRB => CTRL_BUS_WSTRB,
s_axi_CTRL_BUS_ARADDR => CTRL_BUS_ARADDR,
s_axi_CTRL_BUS_ARVALID => CTRL_BUS_ARVALID,
s_axi_CTRL_BUS_ARREADY => CTRL_BUS_ARREADY,
s_axi_CTRL_BUS_RVALID => CTRL_BUS_RVALID,
s_axi_CTRL_BUS_RREADY => CTRL_BUS_RREADY,
s_axi_CTRL_BUS_RDATA => CTRL_BUS_RDATA,
s_axi_CTRL_BUS_RRESP => CTRL_BUS_RRESP,
s_axi_CTRL_BUS_BVALID => CTRL_BUS_BVALID,
s_axi_CTRL_BUS_BREADY => CTRL_BUS_BREADY,
s_axi_CTRL_BUS_BRESP => CTRL_BUS_BRESP,
interrupt => CTRL_BUS_INTERRUPT,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
inStream_TDATA => inStream_TDATA,
inStream_TVALID => inStream_TVALID,
inStream_TREADY => inStream_TREADY,
inStream_TKEEP => inStream_TKEEP,
inStream_TSTRB => inStream_TSTRB,
inStream_TUSER => inStream_TUSER,
inStream_TLAST => inStream_TLAST,
inStream_TID => inStream_TID,
inStream_TDEST => inStream_TDEST,
histo_Addr_A => histo_ADDR_A,
histo_EN_A => histo_EN_A,
histo_WEN_A => histo_WEN_A,
histo_Din_A => histo_DIN_A,
histo_Dout_A => histo_DOUT_A,
histo_Clk_A => histo_CLK_A,
histo_Rst_A => histo_RST_A
);
-- Assignment for control signal
ap_clk <= AESL_clock;
ap_rst_n <= AESL_reset;
AESL_reset <= rst;
AESL_start <= start;
AESL_ce <= ce;
AESL_continue <= continue;
AESL_slave_write_start_in <= slave_start_status ;
AESL_slave_start <= AESL_slave_write_start_finish;
AESL_done <= slave_done_status ;
slave_start_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
slave_start_status <= '1';
else
if (AESL_start = '1' ) then
start_rise <= '1';
end if;
if (start_rise = '1' and AESL_done = '1' ) then
slave_start_status <= '1';
end if;
if (AESL_slave_write_start_in = '1') then
slave_start_status <= '0';
start_rise <= '0';
end if;
end if;
end if;
end process;
slave_ready_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_slave_ready <= '0';
ready_rise <= '0';
else
if (AESL_ready = '1' ) then
ready_rise <= '1';
end if;
if (ready_rise = '1' and AESL_done_delay = '1' ) then
AESL_slave_ready <= '1';
end if;
if (AESL_slave_ready = '1') then
AESL_slave_ready <= '0';
ready_rise <= '0';
end if;
end if;
end if;
end process;
slave_done_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if (AESL_done = '1') then
slave_done_status <= '0';
elsif (AESL_slave_output_done = '1' ) then
slave_done_status <= '1';
end if;
end if;
end process;
AESL_inst_histo : AESL_autobram_histo port map (
Clk_A => bramhisto_Clk_A,
Rst_A => bramhisto_Rst_A,
EN_A => bramhisto_EN_A,
WEN_A => bramhisto_WEN_A,
Addr_A => bramhisto_Addr_A,
Din_A => bramhisto_Din_A,
Dout_A => bramhisto_Dout_A,
Clk_B => bramhisto_Clk_B,
Rst_B => bramhisto_Rst_B,
EN_B => bramhisto_EN_B,
WEN_B => bramhisto_WEN_B,
Addr_B => bramhisto_Addr_B,
Din_B => bramhisto_Din_B,
Dout_B => bramhisto_Dout_B,
ready => bramhisto_ready,
done => bramhisto_done
);
-- Assignment between dut and bramhisto
bramhisto_Clk_A <= histo_CLK_A;
bramhisto_Rst_A <= histo_RST_A;
bramhisto_Addr_A <= histo_ADDR_A;
bramhisto_EN_A <= histo_EN_A;
histo_DOUT_A <= bramhisto_Dout_A;
bramhisto_WEN_A <= histo_WEN_A;
bramhisto_Din_A <= histo_DIN_A;
bramhisto_WEN_B <= (others => '0');
bramhisto_Din_B <= (others => '0');
bramhisto_ready <= ready;
bramhisto_done <= interface_done;
AESL_axi_s_inst_inStream : AESL_axi_s_inStream port map (
clk => AESL_clock,
reset => AESL_reset,
TRAN_inStream_TDATA => inStream_TDATA,
inStream_TDATA_trans_num => ap_c_n_tvin_trans_num_inStream_V_data_V,
TRAN_inStream_TKEEP => inStream_TKEEP,
inStream_TKEEP_trans_num => ap_c_n_tvin_trans_num_inStream_V_keep_V,
TRAN_inStream_TSTRB => inStream_TSTRB,
inStream_TSTRB_trans_num => ap_c_n_tvin_trans_num_inStream_V_strb_V,
TRAN_inStream_TUSER => inStream_TUSER,
inStream_TUSER_trans_num => ap_c_n_tvin_trans_num_inStream_V_user_V,
TRAN_inStream_TLAST => inStream_TLAST,
inStream_TLAST_trans_num => ap_c_n_tvin_trans_num_inStream_V_last_V,
TRAN_inStream_TID => inStream_TID,
inStream_TID_trans_num => ap_c_n_tvin_trans_num_inStream_V_id_V,
TRAN_inStream_TDEST => inStream_TDEST,
inStream_TDEST_trans_num => ap_c_n_tvin_trans_num_inStream_V_dest_V,
TRAN_inStream_TVALID => axi_s_inStream_TVALID,
TRAN_inStream_TREADY => axi_s_inStream_TREADY,
ready => inStream_ready,
done => inStream_done
);
inStream_ready <= inStream_ready_reg or ready_initial;
inStream_done <= '0';
gen_reg_inStream_TVALID_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_inStream_TVALID <= axi_s_inStream_TVALID;
while(true) loop
wait until axi_s_inStream_TVALID'event;
if(axi_s_inStream_TVALID = '1') then
end if;
reg_inStream_TVALID <= axi_s_inStream_TVALID;
end loop;
end process;
inStream_TVALID <= reg_inStream_TVALID;
axi_s_inStream_TREADY <= inStream_TREADY;
AESL_axi_slave_inst_CTRL_BUS : AESL_AXI_SLAVE_CTRL_BUS port map (
clk => AESL_clock,
reset => AESL_reset,
TRAN_s_axi_CTRL_BUS_AWADDR => CTRL_BUS_AWADDR,
TRAN_s_axi_CTRL_BUS_AWVALID => CTRL_BUS_AWVALID,
TRAN_s_axi_CTRL_BUS_AWREADY => CTRL_BUS_AWREADY,
TRAN_s_axi_CTRL_BUS_WVALID => CTRL_BUS_WVALID,
TRAN_s_axi_CTRL_BUS_WREADY => CTRL_BUS_WREADY,
TRAN_s_axi_CTRL_BUS_WDATA => CTRL_BUS_WDATA,
TRAN_s_axi_CTRL_BUS_WSTRB => CTRL_BUS_WSTRB,
TRAN_s_axi_CTRL_BUS_ARADDR => CTRL_BUS_ARADDR,
TRAN_s_axi_CTRL_BUS_ARVALID => CTRL_BUS_ARVALID,
TRAN_s_axi_CTRL_BUS_ARREADY => CTRL_BUS_ARREADY,
TRAN_s_axi_CTRL_BUS_RVALID => CTRL_BUS_RVALID,
TRAN_s_axi_CTRL_BUS_RREADY => CTRL_BUS_RREADY,
TRAN_s_axi_CTRL_BUS_RDATA => CTRL_BUS_RDATA,
TRAN_s_axi_CTRL_BUS_RRESP => CTRL_BUS_RRESP,
TRAN_s_axi_CTRL_BUS_BVALID => CTRL_BUS_BVALID,
TRAN_s_axi_CTRL_BUS_BREADY => CTRL_BUS_BREADY,
TRAN_s_axi_CTRL_BUS_BRESP => CTRL_BUS_BRESP,
TRAN_CTRL_BUS_interrupt => CTRL_BUS_INTERRUPT,
TRAN_CTRL_BUS_ready_out => AESL_ready,
TRAN_CTRL_BUS_ready_in => AESL_slave_ready,
TRAN_CTRL_BUS_done_out => AESL_slave_output_done,
TRAN_CTRL_BUS_idle_out => AESL_idle,
TRAN_CTRL_BUS_write_start_in => AESL_slave_write_start_in,
TRAN_CTRL_BUS_write_start_finish => AESL_slave_write_start_finish,
TRAN_CTRL_BUS_transaction_done_in => AESL_done_delay,
TRAN_CTRL_BUS_start_in => AESL_slave_start
);
generate_ready_cnt_proc : process(ready_initial, AESL_clock)
begin
if(AESL_clock'event and AESL_clock = '0') then
if(ready_initial = '1') then
ready_cnt <= conv_std_logic_vector(1, 32);
end if;
elsif(AESL_clock'event and AESL_clock = '1') then
if(ready_cnt /= AUTOTB_TRANSACTION_NUM) then
if(AESL_ready = '1') then
ready_cnt <= ready_cnt + 1;
end if;
end if;
end if;
end process;
generate_done_cnt_proc : process(AESL_reset, AESL_clock)
begin
if(AESL_reset = '0') then
done_cnt <= (others => '0');
elsif(AESL_clock'event and AESL_clock = '1') then
if(done_cnt /= AUTOTB_TRANSACTION_NUM) then
if(AESL_done = '1') then
done_cnt <= done_cnt + 1;
end if;
end if;
end if;
end process;
generate_sim_done_proc : process
begin
while(done_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
wait until AESL_clock'event and AESL_clock = '1';
wait until AESL_clock'event and AESL_clock = '1';
wait until AESL_clock'event and AESL_clock = '1';
assert false report "simulation done!" severity note;
assert false report "NORMAL EXIT (note: failure is to force the simulator to stop)" severity failure;
wait;
end process;
gen_clock_proc : process
begin
AESL_clock <= '0';
while(true) loop
wait for AUTOTB_CLOCK_PERIOD_DIV2;
AESL_clock <= not AESL_clock;
end loop;
wait;
end process;
gen_reset_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
rst <= '0';
wait for 100 ns;
for i in 1 to 3 loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
rst <= '1';
wait;
end process;
gen_start_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
start <= '0';
ce <= '1';
wait until AESL_reset = '1';
wait until (AESL_clock'event and AESL_clock = '1');
start <= '1';
while(ready_cnt /= AUTOTB_TRANSACTION_NUM + 1) loop
wait until (AESL_clock'event and AESL_clock = '1');
if(AESL_ready = '1') then
start <= '0';
start <= '1';
end if;
end loop;
start <= '0';
wait;
end process;
gen_continue_proc : process(AESL_done)
begin
continue <= AESL_done;
end process;
gen_AESL_ready_delay_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_ready_delay <= '0';
else
AESL_ready_delay <= AESL_ready;
end if;
end if;
end process;
gen_ready_initial_proc : process
begin
ready_initial <= '0';
wait until AESL_start = '1';
ready_initial <= '1';
wait until AESL_clock'event and AESL_clock = '1';
ready_initial <= '0';
wait;
end process;
ready_last_n_proc : process
begin
ready_last_n <= '1';
while(ready_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
ready_last_n <= '0';
wait;
end process;
gen_ready_delay_n_last_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
ready_delay_last_n <= '0';
else
ready_delay_last_n <= ready_last_n;
end if;
end if;
end process;
ready <= (ready_initial or AESL_ready_delay);
ready_wire <= ready_initial or AESL_ready_delay;
done_delay_last_n <= '0' when done_cnt = AUTOTB_TRANSACTION_NUM else '1';
gen_done_delay_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_done_delay <= '0';
AESL_done_delay2 <= '0';
else
AESL_done_delay <= AESL_done and done_delay_last_n;
AESL_done_delay2 <= AESL_done_delay;
end if;
end if;
end process;
gen_interface_done : process(ready, AESL_ready_delay, AESL_done_delay)
begin
if(ready_cnt > 0 and ready_cnt < AUTOTB_TRANSACTION_NUM) then
interface_done <= AESL_ready_delay;
elsif(ready_cnt = AUTOTB_TRANSACTION_NUM) then
interface_done <= AESL_done_delay;
else
interface_done <= '0';
end if;
end process;
proc_gen_inStream_internal_ready : process
variable internal_trans_num : INTEGER;
begin
wait until AESL_reset = '1';
wait until ready_initial = '1';
inStream_ready_reg <= '0';
wait until AESL_clock'event and AESL_clock = '1';
internal_trans_num := 1;
while(internal_trans_num /= AUTOTB_TRANSACTION_NUM + 1) loop
if (true
and ap_c_n_tvin_trans_num_inStream_V_data_V > internal_trans_num
and ap_c_n_tvin_trans_num_inStream_V_keep_V > internal_trans_num
and ap_c_n_tvin_trans_num_inStream_V_strb_V > internal_trans_num
and ap_c_n_tvin_trans_num_inStream_V_user_V > internal_trans_num
and ap_c_n_tvin_trans_num_inStream_V_last_V > internal_trans_num
and ap_c_n_tvin_trans_num_inStream_V_id_V > internal_trans_num
and ap_c_n_tvin_trans_num_inStream_V_dest_V > internal_trans_num
) then
inStream_ready_reg <= '1';
wait until AESL_clock'event and AESL_clock = '1';
inStream_ready_reg <= '0';
internal_trans_num := internal_trans_num + 1;
else
wait until AESL_clock'event and AESL_clock = '1';
end if;
end loop;
inStream_ready_reg <= '0';
wait;
end process;
-- Write "[[[runtime]]]" and "[[[/runtime]]]" for output transactor
write_output_transactor_histo_runtime_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
begin
file_open(fstatus, fp, AUTOTB_TVOUT_histo_out_wrapc, WRITE_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVOUT_histo_out_wrapc & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line, string'("[[[runtime]]]"));
writeline(fp, token_line);
file_close(fp);
while done_cnt /= AUTOTB_TRANSACTION_NUM loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
wait until AESL_clock'event and AESL_clock = '1';
wait until AESL_clock'event and AESL_clock = '1';
file_open(fstatus, fp, AUTOTB_TVOUT_histo_out_wrapc, APPEND_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVOUT_histo_out_wrapc & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line, string'("[[[/runtime]]]"));
writeline(fp, token_line);
file_close(fp);
wait;
end process;
gen_clock_counter_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '0') then
if(AESL_reset = '0') then
AESL_clk_counter := 0;
else
AESL_clk_counter := AESL_clk_counter + 1;
end if;
end if;
end process;
gen_mLatcnterout_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_mLatCnterOut_addr := 0;
AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter + 1 ;
reported_stuck_cnt := 0;
else
if (AESL_done = '1' and AESL_mLatCnterOut_addr < AUTOTB_TRANSACTION_NUM + 1) then
AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter;
AESL_mLatCnterOut_addr := AESL_mLatCnterOut_addr + 1;
reported_stuck <= '0';
end if;
end if;
end if;
end process;
gen_mLatcnterin_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_mLatCnterIn_addr := 0;
else
if (AESL_slave_write_start_finish = '1' and AESL_mLatCnterIn_addr < AUTOTB_TRANSACTION_NUM + 1) then
AESL_mLatCnterIn(AESL_mLatCnterIn_addr) := AESL_clk_counter;
AESL_mLatCnterIn_addr := AESL_mLatCnterIn_addr + 1;
end if;
end if;
end if;
end process;
gen_performance_check_proc : process
variable transaction_counter : INTEGER;
variable i : INTEGER;
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable latthistime : INTEGER;
variable lattotal : INTEGER;
variable latmax : INTEGER;
variable latmin : INTEGER;
variable thrthistime : INTEGER;
variable thrtotal : INTEGER;
variable thrmax : INTEGER;
variable thrmin : INTEGER;
variable lataver : INTEGER;
variable thraver : INTEGER;
type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER;
variable lat_array : latency_record;
variable thr_array : latency_record;
begin
i := 0;
lattotal := 0;
latmax := 0;
latmin := 16#7fffffff#;
lataver := 0;
thrtotal := 0;
thrmax := 0;
thrmin := 16#7fffffff#;
thraver := 0;
wait until (AESL_clock'event and AESL_clock = '1');
wait until (AESL_reset = '1');
while (done_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until (AESL_clock'event and AESL_clock = '1');
end loop;
wait for 0.001 ns;
for i in 0 to AUTOTB_TRANSACTION_NUM - 1 loop
latthistime := AESL_mLatCnterOut(i) - AESL_mLatCnterIn(i);
lat_array(i) := latthistime;
if (latthistime > latmax) then
latmax := latthistime;
end if;
if (latthistime < latmin) then
latmin := latthistime;
end if;
lattotal := lattotal + latthistime;
if (AUTOTB_TRANSACTION_NUM = 1) then
thrthistime := latthistime;
else
thrthistime := AESL_mLatCnterIn(i + 1) - AESL_mLatCnterIn(i);
end if;
thr_array(i) := thrthistime;
if (thrthistime > thrmax) then
thrmax := thrthistime;
end if;
if (thrthistime < thrmin) then
thrmin := thrthistime;
end if;
thrtotal := thrtotal + thrthistime;
end loop;
lataver := lattotal / AUTOTB_TRANSACTION_NUM;
thraver := thrtotal / AUTOTB_TRANSACTION_NUM;
file_open(fstatus, fp, AUTOTB_LAT_RESULT_FILE, WRITE_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_LAT_RESULT_FILE & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
if (AUTOTB_TRANSACTION_NUM = 1) then
thrmax := 0;
thrmin := 0;
thraver := 0;
write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"');
writeline(fp, token_line);
write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(thrmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(thrmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(thraver) & '"');
writeline(fp, token_line);
else
write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"');
writeline(fp, token_line);
write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(latmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(latmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(lataver) & '"');
writeline(fp, token_line);
end if;
file_close(fp);
file_open(fstatus, fp, AUTOTB_PER_RESULT_TRANS_FILE, WRITE_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_PER_RESULT_TRANS_FILE & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line,string'(" latency interval"));
writeline(fp, token_line);
if (AUTOTB_TRANSACTION_NUM = 1) then
i := 0;
thr_array(i) := 0;
write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) );
writeline(fp, token_line);
else
for i in 0 to AESL_mLatCnterOut_addr - 1 loop
write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) );
writeline(fp, token_line);
end loop;
end if;
file_close(fp);
wait;
end process;
end behav;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Polynomial_Evaluator_N
-- Module Name: Polynomial_Evaluator_N
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 3rd step in Goppa Code Decoding.
--
-- This circuit is to be used together with find_correct_erros_n to find the roots
-- of polynomial sigma. This circuit can also be alone to evaluate a polynomial withing
-- a range of values.
--
-- For the computation this circuit applies the school book algorithm of powering x
-- and multiplying by the respective polynomial coefficient and adding into the accumulator.
-- This method is not appropriate for this computation, so in polynomial_evaluator_n_v2
-- Horner scheme is applied to reduce circuits costs.
--
-- The circuits parameters
--
-- number_of_pipelines :
--
-- Number of pipelines used in the circuit to test the support elements and
-- correct the message. Each pipeline needs at least 2 memory ram to store
-- intermediate results.
--
-- pipeline_size :
--
-- The number of stages the pipeline has. More stages means more values of value_sigma
-- are tested at once.
--
-- size_pipeline_size :
--
-- The number of bits necessary to store the pipeline_size.
-- This number is ceil(log2(pipeline_size))
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- polynomial_degree :
--
-- The polynomial degree to be evaluated. Therefore the polynomial has
-- polynomial_degree+1 coefficients. This parameters depends of the Goppa code used.
--
-- size_polynomial_degree :
--
-- The number of bits necessary to store polynomial_degree.
-- This number is ceil(log2(polynomial_degree+1))
--
-- number_of_values_x :
--
-- The size of the memory that holds all support elements. This parameter
-- depends of the Goppa code used.
--
-- size_number_of_values_x :
-- The number of bits necessary to store all support elements.
-- this number is ceil(log2(number_of_values_x)).
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- pipeline_polynomial_calc Rev 1.0
-- shift_register_rst_nbits Rev 1.0
-- shift_register_nbits Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- controller_polynomial_evaluator Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity polynomial_evaluator_n is
Generic (
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 11;
-- polynomial_degree : integer := 27;
-- size_polynomial_degree : integer := 5;
-- number_of_values_x: integer := 2048;
-- size_number_of_values_x : integer := 11
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 11;
-- polynomial_degree : integer := 50;
-- size_polynomial_degree : integer := 6;
-- number_of_values_x: integer := 2048;
-- size_number_of_values_x : integer := 11
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 12;
-- polynomial_degree : integer := 66;
-- size_polynomial_degree : integer := 7;
-- number_of_values_x: integer := 3307;
-- size_number_of_values_x : integer := 12
-- QD-GOPPA [2528, 2144, 32, 12] --
number_of_pipelines : integer := 1;
pipeline_size : integer := 9;
size_pipeline_size : integer := 5;
gf_2_m : integer range 1 to 20 := 12;
polynomial_degree : integer := 32;
size_polynomial_degree : integer := 6;
number_of_values_x: integer := 2528;
size_number_of_values_x : integer := 12
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 12;
-- polynomial_degree : integer := 64;
-- size_polynomial_degree : integer := 6;
-- number_of_values_x: integer := 2816;
-- size_number_of_values_x : integer := 12
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 12;
-- polynomial_degree : integer := 128;
-- size_polynomial_degree : integer := 7;
-- number_of_values_x: integer := 3200;
-- size_number_of_values_x : integer := 12
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 15;
-- polynomial_degree : integer := 128;
-- size_polynomial_degree : integer := 7;
-- number_of_values_x: integer := 8320;
-- size_number_of_values_x : integer := 14
);
Port(
value_x : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_x_pow : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
last_evaluations : out STD_LOGIC;
evaluation_finalized : out STD_LOGIC;
address_value_polynomial : out STD_LOGIC_VECTOR((size_polynomial_degree - 1) downto 0);
address_value_x : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
address_value_acc : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
address_value_x_pow : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
address_new_value_acc : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
address_new_value_x_pow : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
write_enable_new_value_acc : out STD_LOGIC;
write_enable_new_value_x_pow : out STD_LOGIC;
new_value_acc : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
new_value_x_pow : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0)
);
end polynomial_evaluator_n;
architecture RTL of polynomial_evaluator_n is
component pipeline_polynomial_calc
Generic (
gf_2_m : integer range 1 to 20 := 11;
size : integer := 2
);
Port (
value_x : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((((gf_2_m)*size) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_x_pow : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
clk : in STD_LOGIC;
new_value_x_pow : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component shift_register_rst_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
component shift_register_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
component register_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component controller_polynomial_evaluator
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
last_load_x_values : in STD_LOGIC;
last_store_x_values : in STD_LOGIC;
limit_polynomial_degree : in STD_LOGIC;
pipeline_ready : in STD_LOGIC;
evaluation_data_in : out STD_LOGIC;
reg_write_enable_rst : out STD_LOGIC;
ctr_load_x_address_ce : out STD_LOGIC;
ctr_load_x_address_rst : out STD_LOGIC;
ctr_store_x_address_ce : out STD_LOGIC;
ctr_store_x_address_rst : out STD_LOGIC;
reg_first_values_ce : out STD_LOGIC;
reg_first_values_rst : out STD_LOGIC;
ctr_address_polynomial_ce : out STD_LOGIC;
ctr_address_polynomial_rst : out STD_LOGIC;
shift_polynomial_ce_ce : out STD_LOGIC;
shift_polynomial_ce_rst : out STD_LOGIC;
last_coefficients : out STD_LOGIC;
evaluation_finalized : out STD_LOGIC
);
end component;
signal pipeline_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal pipeline_value_x_pow : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
constant coefficient_zero : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
constant first_acc : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
constant first_x_pow : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(1, gf_2_m));
signal reg_polynomial_coefficients_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_polynomial_coefficients_ce : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal reg_polynomial_coefficients_q : STD_LOGIC_VECTOR((((gf_2_m)*pipeline_size) - 1) downto 0);
signal shift_polynomial_ce_data_in : STD_LOGIC;
signal shift_polynomial_ce_ce : STD_LOGIC;
signal shift_polynomial_ce_rst : STD_LOGIC;
constant shift_polynomial_ce_rst_value : STD_LOGIC_VECTOR(pipeline_size downto 0) := std_logic_vector(to_unsigned(1, pipeline_size+1));
signal shift_polynomial_ce_q : STD_LOGIC_VECTOR(pipeline_size downto 0);
signal ctr_address_polynomial_ce : STD_LOGIC;
signal ctr_address_polynomial_rst : STD_LOGIC;
constant ctr_address_polynomial_rst_value : STD_LOGIC_VECTOR((size_polynomial_degree) downto 0) := std_logic_vector(to_unsigned(0, size_polynomial_degree+1));
signal ctr_address_polynomial_q : STD_LOGIC_VECTOR((size_polynomial_degree) downto 0);
signal ctr_load_x_address_ce : STD_LOGIC;
signal ctr_load_x_address_rst : STD_LOGIC;
constant ctr_load_x_address_rst_value : STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0) := std_logic_vector(to_unsigned(0, size_number_of_values_x));
signal ctr_load_x_address_q : STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
signal ctr_store_x_address_ce : STD_LOGIC;
signal ctr_store_x_address_rst : STD_LOGIC;
constant ctr_store_x_message_address_rst_value : STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0) := std_logic_vector(to_unsigned(0, size_number_of_values_x));
signal ctr_store_x_address_q : STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
signal reg_first_values_ce : STD_LOGIC;
signal reg_first_values_rst : STD_LOGIC;
signal reg_first_values_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "1";
signal reg_first_values_q : STD_LOGIC_VECTOR(0 downto 0);
signal evaluation_data_in : STD_LOGIC;
signal evaluation_data_out : STD_LOGIC;
signal reg_write_enable_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_write_enable_rst : STD_LOGIC;
constant reg_write_enable_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_write_enable_q : STD_LOGIC_VECTOR(0 downto 0);
signal pipeline_ready : STD_LOGIC;
signal limit_polynomial_degree : STD_LOGIC;
signal last_coefficients : STD_LOGIC;
signal last_load_x_values : STD_LOGIC;
signal last_store_x_values : STD_LOGIC;
begin
pipelines : for I in 0 to (number_of_pipelines - 1) generate
pipeline_I : pipeline_polynomial_calc
Generic Map (
gf_2_m => gf_2_m,
size => pipeline_size
)
Port Map(
value_x => value_x(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
value_polynomial => reg_polynomial_coefficients_q,
value_acc => pipeline_value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
value_x_pow => pipeline_value_x_pow(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
clk => clk,
new_value_x_pow => new_value_x_pow(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
new_value_acc => new_value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)))
);
pipeline_value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) <= first_acc when reg_first_values_q = "1" else
value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)));
pipeline_value_x_pow(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) <= first_x_pow when reg_first_values_q = "1" else
value_x_pow(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)));
end generate;
polynomial : for I in 0 to (pipeline_size - 1) generate
reg_polynomial_coefficients_I : register_nbits
Generic Map (size => gf_2_m)
Port Map(
d => reg_polynomial_coefficients_d,
clk => clk,
ce => reg_polynomial_coefficients_ce(I),
q => reg_polynomial_coefficients_q(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)))
);
end generate;
controller : controller_polynomial_evaluator
Port Map(
clk => clk,
rst => rst,
last_load_x_values => last_load_x_values,
last_store_x_values => last_store_x_values,
limit_polynomial_degree => limit_polynomial_degree,
pipeline_ready => pipeline_ready,
evaluation_data_in => evaluation_data_in,
reg_write_enable_rst => reg_write_enable_rst,
ctr_load_x_address_ce => ctr_load_x_address_ce,
ctr_load_x_address_rst => ctr_load_x_address_rst,
ctr_store_x_address_ce => ctr_store_x_address_ce,
ctr_store_x_address_rst => ctr_store_x_address_rst,
reg_first_values_ce => reg_first_values_ce,
reg_first_values_rst => reg_first_values_rst,
ctr_address_polynomial_ce => ctr_address_polynomial_ce,
ctr_address_polynomial_rst => ctr_address_polynomial_rst,
shift_polynomial_ce_ce => shift_polynomial_ce_ce,
shift_polynomial_ce_rst => shift_polynomial_ce_rst,
last_coefficients => last_coefficients,
evaluation_finalized => evaluation_finalized
);
shift_polynomial_ce : shift_register_rst_nbits
Generic Map(
size => pipeline_size + 1
)
Port Map(
data_in => shift_polynomial_ce_data_in,
clk => clk,
ce => shift_polynomial_ce_ce,
rst => shift_polynomial_ce_rst,
rst_value => shift_polynomial_ce_rst_value,
q => shift_polynomial_ce_q,
data_out => shift_polynomial_ce_data_in
);
evaluation : shift_register_nbits
Generic Map(
size => pipeline_size - 1
)
Port Map(
data_in => evaluation_data_in,
clk => clk,
ce => '1',
q => open,
data_out => evaluation_data_out
);
reg_write_enable : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_write_enable_d,
clk => clk,
ce => '1',
rst => reg_write_enable_rst,
rst_value => reg_write_enable_rst_value,
q => reg_write_enable_q
);
ctr_address_polynomial : counter_rst_nbits
Generic Map(
size => size_polynomial_degree+1,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_address_polynomial_ce,
rst => ctr_address_polynomial_rst,
rst_value => ctr_address_polynomial_rst_value,
q => ctr_address_polynomial_q
);
ctr_load_x_address : counter_rst_nbits
Generic Map(
size => size_number_of_values_x,
increment_value => number_of_pipelines
)
Port Map(
clk => clk,
ce => ctr_load_x_address_ce,
rst => ctr_load_x_address_rst,
rst_value => ctr_load_x_address_rst_value,
q => ctr_load_x_address_q
);
ctr_store_x_address : counter_rst_nbits
Generic Map(
size => size_number_of_values_x,
increment_value => number_of_pipelines
)
Port Map(
clk => clk,
ce => ctr_store_x_address_ce,
rst => ctr_store_x_address_rst,
rst_value => ctr_store_x_message_address_rst_value,
q => ctr_store_x_address_q
);
reg_first_values : register_rst_nbits
Generic Map(size => 1)
Port Map(
d => "0",
clk => clk,
ce => reg_first_values_ce,
rst => reg_first_values_rst,
rst_value => reg_first_values_rst_value,
q => reg_first_values_q
);
reg_polynomial_coefficients_d <= coefficient_zero when last_coefficients = '1' else
value_polynomial;
reg_polynomial_coefficients_ce <= shift_polynomial_ce_q((pipeline_size - 1) downto 0);
address_value_polynomial <= ctr_address_polynomial_q((size_polynomial_degree - 1) downto 0);
address_value_x <= ctr_load_x_address_q;
address_value_acc <= ctr_load_x_address_q;
address_value_x_pow <= ctr_load_x_address_q;
address_new_value_acc <= ctr_store_x_address_q;
address_new_value_x_pow <= ctr_store_x_address_q;
pipeline_ready <= shift_polynomial_ce_q(pipeline_size-1);
limit_polynomial_degree <= '1' when (unsigned(ctr_address_polynomial_q) = to_unsigned(polynomial_degree+1, ctr_address_polynomial_q'length)) else '0';
last_evaluations <= limit_polynomial_degree and shift_polynomial_ce_q(pipeline_size);
reg_write_enable_d(0) <= evaluation_data_out;
write_enable_new_value_acc <= reg_write_enable_q(0);
write_enable_new_value_x_pow <= reg_write_enable_q(0);
last_load_x_values <= '1' when ctr_load_x_address_q = std_logic_vector(to_unsigned(((number_of_values_x - 1)/number_of_pipelines)*number_of_pipelines, ctr_load_x_address_q'Length)) else '0';
last_store_x_values <= '1' when ctr_store_x_address_q = std_logic_vector(to_unsigned(((number_of_values_x - 1)/number_of_pipelines)*number_of_pipelines, ctr_load_x_address_q'Length)) else '0';
end RTL; |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:30 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_axi_gpio_1_0_sim_netlist.vhdl
-- Design : ip_design_axi_gpio_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
port (
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\ : out STD_LOGIC;
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
Q : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_read : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_wrack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
reg3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reg1 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
signal Bus_RNW_reg : STD_LOGIC;
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : STD_LOGIC;
signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal \ip2bus_data_i_D1[27]_i_2_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[27]_i_3_n_0\ : STD_LOGIC;
signal \^ip2bus_data_i_d1_reg[0]\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[5]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[6]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \Dual.gpio2_OE[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[0]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[2]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \Dual.gpio_OE[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \ip2bus_data_i_D1[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \ip2bus_data_i_D1[27]_i_3\ : label is "soft_lutpair2";
begin
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
\ip2bus_data_i_D1_reg[0]\(8 downto 0) <= \^ip2bus_data_i_d1_reg[0]\(8 downto 0);
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => Q,
I2 => Bus_RNW_reg,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => Bus_RNW_reg,
R => '0'
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => gpio_xferAck_Reg,
I3 => GPIO_xferAck_i,
O => \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\
);
\Dual.gpio2_Data_Out[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00100000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(1),
O => \Dual.gpio2_Data_Out_reg[0]\(0)
);
\Dual.gpio2_Data_Out[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => s_axi_wdata(2),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
O => D(2)
);
\Dual.gpio2_Data_Out[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => s_axi_wdata(1),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
O => D(1)
);
\Dual.gpio2_Data_Out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => s_axi_wdata(0),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
O => D(0)
);
\Dual.gpio2_OE[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \bus2ip_addr_i_reg[8]\(0),
O => \Dual.gpio2_OE_reg[0]\(0)
);
\Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \bus2ip_addr_i_reg[8]\(0),
O => E(0)
);
\Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(4),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => s_axi_wdata(7),
O => D(7)
);
\Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(3),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => s_axi_wdata(6),
O => D(6)
);
\Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(2),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => s_axi_wdata(5),
O => D(5)
);
\Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => s_axi_wdata(4),
O => D(4)
);
\Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => s_axi_wdata(3),
O => D(3)
);
\Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00100000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \bus2ip_addr_i_reg[8]\(0),
O => \Dual.gpio_OE_reg[0]\(0)
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(0),
I1 => \bus2ip_addr_i_reg[8]\(1),
O => ce_expnd_i_3
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_3,
Q => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(0),
I1 => \bus2ip_addr_i_reg[8]\(1),
O => ce_expnd_i_2
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_2,
Q => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(0),
O => ce_expnd_i_1
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_1,
Q => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_arready\,
I2 => s_axi_aresetn,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(0),
O => ce_expnd_i_0
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_0,
Q => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
R => cs_ce_clr
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => Q,
I2 => s_axi_aresetn,
I3 => \^s_axi_arready\,
I4 => \^s_axi_wready\,
O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\,
Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
R => '0'
);
\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00040400"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I1 => Bus_RNW_reg,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I4 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
O => \^ip2bus_data_i_d1_reg[0]\(8)
);
\ip2bus_data_i_D1[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00020000003C0000"
)
port map (
I0 => reg3(7),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I4 => Bus_RNW_reg,
I5 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => \^ip2bus_data_i_d1_reg[0]\(7)
);
\ip2bus_data_i_D1[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00020000003C0000"
)
port map (
I0 => reg3(6),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I4 => Bus_RNW_reg,
I5 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => \^ip2bus_data_i_d1_reg[0]\(6)
);
\ip2bus_data_i_D1[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00020000003C0000"
)
port map (
I0 => reg3(5),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I4 => Bus_RNW_reg,
I5 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => \^ip2bus_data_i_d1_reg[0]\(5)
);
\ip2bus_data_i_D1[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^ip2bus_data_i_d1_reg[0]\(8),
I1 => \ip2bus_data_i_D1[27]_i_2_n_0\,
I2 => reg1(4),
I3 => reg3(4),
I4 => \ip2bus_data_i_D1[27]_i_3_n_0\,
O => \^ip2bus_data_i_d1_reg[0]\(4)
);
\ip2bus_data_i_D1[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00020000"
)
port map (
I0 => Bus_RNW_reg,
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
O => \ip2bus_data_i_D1[27]_i_2_n_0\
);
\ip2bus_data_i_D1[27]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00020000"
)
port map (
I0 => Bus_RNW_reg,
I1 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => \ip2bus_data_i_D1[27]_i_3_n_0\
);
\ip2bus_data_i_D1[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^ip2bus_data_i_d1_reg[0]\(8),
I1 => \ip2bus_data_i_D1[27]_i_2_n_0\,
I2 => reg1(3),
I3 => reg3(3),
I4 => \ip2bus_data_i_D1[27]_i_3_n_0\,
O => \^ip2bus_data_i_d1_reg[0]\(3)
);
\ip2bus_data_i_D1[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^ip2bus_data_i_d1_reg[0]\(8),
I1 => \ip2bus_data_i_D1[27]_i_2_n_0\,
I2 => reg1(2),
I3 => reg3(2),
I4 => \ip2bus_data_i_D1[27]_i_3_n_0\,
O => \^ip2bus_data_i_d1_reg[0]\(2)
);
\ip2bus_data_i_D1[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^ip2bus_data_i_d1_reg[0]\(8),
I1 => \ip2bus_data_i_D1[27]_i_2_n_0\,
I2 => reg1(1),
I3 => reg3(1),
I4 => \ip2bus_data_i_D1[27]_i_3_n_0\,
O => \^ip2bus_data_i_d1_reg[0]\(1)
);
\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^ip2bus_data_i_d1_reg[0]\(8),
I1 => \ip2bus_data_i_D1[27]_i_2_n_0\,
I2 => reg1(0),
I3 => reg3(0),
I4 => \ip2bus_data_i_D1[27]_i_3_n_0\,
O => \^ip2bus_data_i_d1_reg[0]\(0)
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_rdack_i_D1,
I1 => is_read,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_wrack_i_D1,
I1 => is_write_reg,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => scndry_vect_out(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => scndry_vect_out(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => scndry_vect_out(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync__parameterized0\ is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync__parameterized0\ : entity is "cdc_sync";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync__parameterized0\ is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_5 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_6 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_7 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d2_5 : STD_LOGIC;
signal s_level_out_bus_d2_6 : STD_LOGIC;
signal s_level_out_bus_d2_7 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
signal s_level_out_bus_d3_5 : STD_LOGIC;
signal s_level_out_bus_d3_6 : STD_LOGIC;
signal s_level_out_bus_d3_7 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_5,
Q => s_level_out_bus_d2_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_6,
Q => s_level_out_bus_d2_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_7,
Q => s_level_out_bus_d2_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_5,
Q => s_level_out_bus_d3_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_6,
Q => s_level_out_bus_d3_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_7,
Q => s_level_out_bus_d3_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => scndry_vect_out(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => scndry_vect_out(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => scndry_vect_out(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_5,
Q => scndry_vect_out(5),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_6,
Q => scndry_vect_out(6),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_7,
Q => scndry_vect_out(7),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(5),
Q => s_level_out_bus_d1_cdc_to_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(6),
Q => s_level_out_bus_d1_cdc_to_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(7),
Q => s_level_out_bus_d1_cdc_to_7,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
port (
reg3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
reg1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[7]_0\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[6]_0\ : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[5]_0\ : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[4]_0\ : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[3]_0\ : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[2]_0\ : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[1]_0\ : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[0]_0\ : in STD_LOGIC;
Read_Reg_In : in STD_LOGIC_VECTOR ( 0 to 4 );
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
bus2ip_rnw_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal gpio2_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 7 );
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 4 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair13";
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(0),
Q => reg1(4),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G0.READ_REG_GEN[1].reg1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(1),
Q => reg1(3),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G0.READ_REG_GEN[2].reg1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(2),
Q => reg1(2),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G0.READ_REG_GEN[3].reg1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(3),
Q => reg1(1),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G0.READ_REG_GEN[4].reg1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(4),
Q => reg1(0),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.gpio2_Data_In_reg[0]_0\,
Q => reg3(7),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.gpio2_Data_In_reg[1]_0\,
Q => reg3(6),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.gpio2_Data_In_reg[2]_0\,
Q => reg3(5),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.gpio2_Data_In_reg[3]_0\,
Q => reg3(4),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.gpio2_Data_In_reg[4]_0\,
Q => reg3(3),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.gpio2_Data_In_reg[5]_0\,
Q => reg3(2),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.gpio2_Data_In_reg[6]_0\,
Q => reg3(1),
R => bus2ip_rnw_i_reg
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.gpio2_Data_In_reg[7]_0\,
Q => reg3(0),
R => bus2ip_rnw_i_reg
);
\Dual.INPUT_DOUBLE_REGS4\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
gpio_io_i(4 downto 0) => gpio_io_i(4 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(4) => gpio_io_i_d2(0),
scndry_vect_out(3) => gpio_io_i_d2(1),
scndry_vect_out(2) => gpio_io_i_d2(2),
scndry_vect_out(1) => gpio_io_i_d2(3),
scndry_vect_out(0) => gpio_io_i_d2(4)
);
\Dual.INPUT_DOUBLE_REGS5\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync__parameterized0\
port map (
gpio2_io_i(7 downto 0) => gpio2_io_i(7 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(7) => gpio2_io_i_d2(0),
scndry_vect_out(6) => gpio2_io_i_d2(1),
scndry_vect_out(5) => gpio2_io_i_d2(2),
scndry_vect_out(4) => gpio2_io_i_d2(3),
scndry_vect_out(3) => gpio2_io_i_d2(4),
scndry_vect_out(2) => gpio2_io_i_d2(5),
scndry_vect_out(1) => gpio2_io_i_d2(6),
scndry_vect_out(0) => gpio2_io_i_d2(7)
);
\Dual.gpio2_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(0),
Q => Q(7),
R => '0'
);
\Dual.gpio2_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(1),
Q => Q(6),
R => '0'
);
\Dual.gpio2_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(2),
Q => Q(5),
R => '0'
);
\Dual.gpio2_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(3),
Q => Q(4),
R => '0'
);
\Dual.gpio2_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(4),
Q => Q(3),
R => '0'
);
\Dual.gpio2_Data_In_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(5),
Q => Q(2),
R => '0'
);
\Dual.gpio2_Data_In_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(6),
Q => Q(1),
R => '0'
);
\Dual.gpio2_Data_In_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(7),
Q => Q(0),
R => '0'
);
\Dual.gpio2_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(7),
Q => gpio2_io_o(7),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(6),
Q => gpio2_io_o(6),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(5),
Q => gpio2_io_o(5),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(4),
Q => gpio2_io_o(4),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(3),
Q => gpio2_io_o(3),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(2),
Q => gpio2_io_o(2),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(1),
Q => gpio2_io_o(1),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(0),
Q => gpio2_io_o(0),
R => SS(0)
);
\Dual.gpio2_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_2(0),
D => D(7),
Q => gpio2_io_t(7),
S => SS(0)
);
\Dual.gpio2_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_2(0),
D => D(6),
Q => gpio2_io_t(6),
S => SS(0)
);
\Dual.gpio2_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_2(0),
D => D(5),
Q => gpio2_io_t(5),
S => SS(0)
);
\Dual.gpio2_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_2(0),
D => D(4),
Q => gpio2_io_t(4),
S => SS(0)
);
\Dual.gpio2_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_2(0),
D => D(3),
Q => gpio2_io_t(3),
S => SS(0)
);
\Dual.gpio2_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_2(0),
D => D(2),
Q => gpio2_io_t(2),
S => SS(0)
);
\Dual.gpio2_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_2(0),
D => D(1),
Q => gpio2_io_t(1),
S => SS(0)
);
\Dual.gpio2_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_2(0),
D => D(0),
Q => gpio2_io_t(0),
S => SS(0)
);
\Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(4),
R => '0'
);
\Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(3),
R => '0'
);
\Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(2),
Q => \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(2),
R => '0'
);
\Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(3),
Q => \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(1),
R => '0'
);
\Dual.gpio_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(4),
Q => \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(0),
R => '0'
);
\Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(7),
Q => gpio_io_o(4),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(6),
Q => gpio_io_o(3),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(5),
Q => gpio_io_o(2),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(4),
Q => gpio_io_o(1),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(3),
Q => gpio_io_o(0),
R => SS(0)
);
\Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(7),
Q => gpio_io_t(4),
S => SS(0)
);
\Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(6),
Q => gpio_io_t(3),
S => SS(0)
);
\Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(5),
Q => gpio_io_t(2),
S => SS(0)
);
\Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(4),
Q => gpio_io_t(1),
S => SS(0)
);
\Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(3),
Q => gpio_io_t(0),
S => SS(0)
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => SS(0)
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => bus2ip_cs,
I1 => \^gpio_xferack_reg\,
I2 => \^gpio_xferack_i\,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => SS(0)
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_wrack_i_D1_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
port (
SR : out STD_LOGIC;
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg_In : out STD_LOGIC_VECTOR ( 0 to 4 );
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 8 downto 0 );
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_t : in STD_LOGIC_VECTOR ( 7 downto 0 );
\ip2bus_data_i_D1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
reg3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reg1 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
signal \^dual.allin0_nd_g0.read_reg_gen[0].reg1_reg[27]\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^sr\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rst_i_1_n_0 : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal \s_axi_rdata_i[31]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \bus2ip_addr_i[8]_i_2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair9";
begin
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\ <= \^dual.allin0_nd_g0.read_reg_gen[0].reg1_reg[27]\;
SR <= \^sr\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020002"
)
port map (
I0 => Q(4),
I1 => bus2ip_addr(0),
I2 => bus2ip_addr(5),
I3 => bus2ip_addr(6),
I4 => gpio_io_t(4),
O => Read_Reg_In(0)
);
\Dual.ALLIN0_ND_G0.READ_REG_GEN[1].reg1[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020002"
)
port map (
I0 => Q(3),
I1 => bus2ip_addr(0),
I2 => bus2ip_addr(5),
I3 => bus2ip_addr(6),
I4 => gpio_io_t(3),
O => Read_Reg_In(1)
);
\Dual.ALLIN0_ND_G0.READ_REG_GEN[2].reg1[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020002"
)
port map (
I0 => Q(2),
I1 => bus2ip_addr(0),
I2 => bus2ip_addr(5),
I3 => bus2ip_addr(6),
I4 => gpio_io_t(2),
O => Read_Reg_In(2)
);
\Dual.ALLIN0_ND_G0.READ_REG_GEN[3].reg1[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020002"
)
port map (
I0 => Q(1),
I1 => bus2ip_addr(0),
I2 => bus2ip_addr(5),
I3 => bus2ip_addr(6),
I4 => gpio_io_t(1),
O => Read_Reg_In(3)
);
\Dual.ALLIN0_ND_G0.READ_REG_GEN[4].reg1[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020002"
)
port map (
I0 => Q(0),
I1 => bus2ip_addr(0),
I2 => bus2ip_addr(5),
I3 => bus2ip_addr(6),
I4 => gpio_io_t(0),
O => Read_Reg_In(4)
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000CA00"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(7),
I1 => gpio2_io_t(7),
I2 => bus2ip_addr(6),
I3 => bus2ip_addr(5),
I4 => bus2ip_addr(0),
O => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000CA00"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(6),
I1 => gpio2_io_t(6),
I2 => bus2ip_addr(6),
I3 => bus2ip_addr(5),
I4 => bus2ip_addr(0),
O => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]\
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000CA00"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(5),
I1 => gpio2_io_t(5),
I2 => bus2ip_addr(6),
I3 => bus2ip_addr(5),
I4 => bus2ip_addr(0),
O => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]\
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000CA00"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(4),
I1 => gpio2_io_t(4),
I2 => bus2ip_addr(6),
I3 => bus2ip_addr(5),
I4 => bus2ip_addr(0),
O => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]\
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000CA00"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(3),
I1 => gpio2_io_t(3),
I2 => bus2ip_addr(6),
I3 => bus2ip_addr(5),
I4 => bus2ip_addr(0),
O => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]\
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000CA00"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(2),
I1 => gpio2_io_t(2),
I2 => bus2ip_addr(6),
I3 => bus2ip_addr(5),
I4 => bus2ip_addr(0),
O => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]\
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000CA00"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(1),
I1 => gpio2_io_t(1),
I2 => bus2ip_addr(6),
I3 => bus2ip_addr(5),
I4 => bus2ip_addr(0),
O => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]\
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3[31]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000CA00"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(0),
I1 => gpio2_io_t(0),
I2 => bus2ip_addr(6),
I3 => bus2ip_addr(5),
I4 => bus2ip_addr(0),
O => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
port map (
D(7 downto 0) => D(7 downto 0),
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\ => \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\,
\Dual.gpio2_Data_Out_reg[0]\(0) => \Dual.gpio2_Data_Out_reg[0]\(0),
\Dual.gpio2_OE_reg[0]\(0) => \Dual.gpio2_OE_reg[0]\(0),
\Dual.gpio_OE_reg[0]\(0) => \Dual.gpio_OE_reg[0]\(0),
E(0) => E(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
Q => start2,
\bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(0),
\bus2ip_addr_i_reg[8]\(1) => bus2ip_addr(5),
\bus2ip_addr_i_reg[8]\(0) => bus2ip_addr(6),
bus2ip_rnw_i_reg => \^dual.allin0_nd_g0.read_reg_gen[0].reg1_reg[27]\,
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[0]\(8 downto 0) => \ip2bus_data_i_D1_reg[0]\(8 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
reg1(4 downto 0) => reg1(4 downto 0),
reg3(7 downto 0) => reg3(7 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
s_axi_wready => \^s_axi_wready\
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_awaddr(0),
I2 => s_axi_arvalid,
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_awaddr(1),
I2 => s_axi_arvalid,
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_awaddr(2),
I2 => s_axi_arvalid,
O => \bus2ip_addr_i[8]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => bus2ip_addr(6),
R => \^sr\
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => bus2ip_addr(5),
R => \^sr\
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[8]_i_2_n_0\,
Q => bus2ip_addr(0),
R => \^sr\
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => s_axi_arvalid,
Q => \^dual.allin0_nd_g0.read_reg_gen[0].reg1_reg[27]\,
R => \^sr\
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => \^sr\
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^sr\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => rst_i_1_n_0
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rst_i_1_n_0,
Q => \^sr\,
R => '0'
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^sr\
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => \s_axi_rdata_i[31]_i_1_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[0]_0\(0),
Q => s_axi_rdata(0),
R => \^sr\
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[0]_0\(1),
Q => s_axi_rdata(1),
R => \^sr\
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[0]_0\(2),
Q => s_axi_rdata(2),
R => \^sr\
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[0]_0\(8),
Q => s_axi_rdata(8),
R => \^sr\
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[0]_0\(3),
Q => s_axi_rdata(3),
R => \^sr\
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[0]_0\(4),
Q => s_axi_rdata(4),
R => \^sr\
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[0]_0\(5),
Q => s_axi_rdata(5),
R => \^sr\
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[0]_0\(6),
Q => s_axi_rdata(6),
R => \^sr\
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[0]_0\(7),
Q => s_axi_rdata(7),
R => \^sr\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^sr\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => state(0),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^sr\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77FC44FC"
)
port map (
I0 => \state1__2\,
I1 => state(0),
I2 => s_axi_arvalid,
I3 => state(1),
I4 => \^s_axi_wready\,
O => \state[0]_i_1_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5FFC50FC"
)
port map (
I0 => \state1__2\,
I1 => \state[1]_i_3_n_0\,
I2 => state(1),
I3 => state(0),
I4 => \^s_axi_arready\,
O => \state[1]_i_1_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => state(0),
R => \^sr\
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => state(1),
R => \^sr\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
port (
bus2ip_reset : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg_In : out STD_LOGIC_VECTOR ( 0 to 4 );
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]\ : out STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 8 downto 0 );
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
\Dual.gpio2_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_t : in STD_LOGIC_VECTOR ( 7 downto 0 );
\ip2bus_data_i_D1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
reg3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reg1 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
port map (
D(7 downto 0) => D(7 downto 0),
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\ => bus2ip_rnw,
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\ => \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\ => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]\ => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]\,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]\ => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]\,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]\ => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]\,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]\ => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]\,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]\ => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]\,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]\ => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]\,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]\ => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]\,
\Dual.gpio2_Data_In_reg[0]\(7 downto 0) => \Dual.gpio2_Data_In_reg[0]\(7 downto 0),
\Dual.gpio2_Data_Out_reg[0]\(0) => \Dual.gpio2_Data_Out_reg[0]\(0),
\Dual.gpio2_OE_reg[0]\(0) => \Dual.gpio2_OE_reg[0]\(0),
\Dual.gpio_OE_reg[0]\(0) => \Dual.gpio_OE_reg[0]\(0),
E(0) => E(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs,
Q(4 downto 0) => Q(4 downto 0),
Read_Reg_In(0 to 4) => Read_Reg_In(0 to 4),
SR => bus2ip_reset,
gpio2_io_t(7 downto 0) => gpio2_io_t(7 downto 0),
gpio_io_t(4 downto 0) => gpio_io_t(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[0]\(8 downto 0) => \ip2bus_data_i_D1_reg[0]\(8 downto 0),
\ip2bus_data_i_D1_reg[0]_0\(8 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(8 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
reg1(4 downto 0) => reg1(4 downto 0),
reg3(7 downto 0) => reg3(7 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(8 downto 0) => s_axi_rdata(8 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 1;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 1;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 8;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 5;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "LOGICORE";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_14 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_15 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_16 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_17 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_18 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_24 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_25 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_26 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_27 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_28 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_29 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_30 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_31 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_32 : STD_LOGIC;
signal GPIO_xferAck_i : STD_LOGIC;
signal Read_Reg_In : STD_LOGIC_VECTOR ( 0 to 4 );
signal bus2ip_cs : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio2_Data_In : STD_LOGIC_VECTOR ( 0 to 7 );
signal \^gpio2_io_t\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 4 );
signal gpio_core_1_n_16 : STD_LOGIC;
signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal gpio_xferAck_Reg : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal reg1 : STD_LOGIC_VECTOR ( 27 to 31 );
signal reg3 : STD_LOGIC_VECTOR ( 24 to 31 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 30 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
attribute sigis : string;
attribute sigis of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
attribute max_fanout : string;
attribute max_fanout of s_axi_aclk : signal is "10000";
attribute sigis of s_axi_aclk : signal is "Clk";
attribute max_fanout of s_axi_aresetn : signal is "10000";
attribute sigis of s_axi_aresetn : signal is "Rst";
begin
gpio2_io_t(7 downto 0) <= \^gpio2_io_t\(7 downto 0);
gpio_io_t(4 downto 0) <= \^gpio_io_t\(4 downto 0);
ip2intc_irpt <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(30);
s_axi_rdata(30) <= \^s_axi_rdata\(30);
s_axi_rdata(29) <= \^s_axi_rdata\(30);
s_axi_rdata(28) <= \^s_axi_rdata\(30);
s_axi_rdata(27) <= \^s_axi_rdata\(30);
s_axi_rdata(26) <= \^s_axi_rdata\(30);
s_axi_rdata(25) <= \^s_axi_rdata\(30);
s_axi_rdata(24) <= \^s_axi_rdata\(30);
s_axi_rdata(23) <= \^s_axi_rdata\(30);
s_axi_rdata(22) <= \^s_axi_rdata\(30);
s_axi_rdata(21) <= \^s_axi_rdata\(30);
s_axi_rdata(20) <= \^s_axi_rdata\(30);
s_axi_rdata(19) <= \^s_axi_rdata\(30);
s_axi_rdata(18) <= \^s_axi_rdata\(30);
s_axi_rdata(17) <= \^s_axi_rdata\(30);
s_axi_rdata(16) <= \^s_axi_rdata\(30);
s_axi_rdata(15) <= \^s_axi_rdata\(30);
s_axi_rdata(14) <= \^s_axi_rdata\(30);
s_axi_rdata(13) <= \^s_axi_rdata\(30);
s_axi_rdata(12) <= \^s_axi_rdata\(30);
s_axi_rdata(11) <= \^s_axi_rdata\(30);
s_axi_rdata(10) <= \^s_axi_rdata\(30);
s_axi_rdata(9) <= \^s_axi_rdata\(30);
s_axi_rdata(8) <= \^s_axi_rdata\(30);
s_axi_rdata(7 downto 0) <= \^s_axi_rdata\(7 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
port map (
D(7 downto 3) => p_0_out(4 downto 0),
D(2) => AXI_LITE_IPIF_I_n_12,
D(1) => AXI_LITE_IPIF_I_n_13,
D(0) => AXI_LITE_IPIF_I_n_14,
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]\ => AXI_LITE_IPIF_I_n_24,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\ => AXI_LITE_IPIF_I_n_32,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]\ => AXI_LITE_IPIF_I_n_31,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]\ => AXI_LITE_IPIF_I_n_30,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]\ => AXI_LITE_IPIF_I_n_29,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]\ => AXI_LITE_IPIF_I_n_28,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]\ => AXI_LITE_IPIF_I_n_27,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]\ => AXI_LITE_IPIF_I_n_26,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]\ => AXI_LITE_IPIF_I_n_25,
\Dual.gpio2_Data_In_reg[0]\(7) => gpio2_Data_In(0),
\Dual.gpio2_Data_In_reg[0]\(6) => gpio2_Data_In(1),
\Dual.gpio2_Data_In_reg[0]\(5) => gpio2_Data_In(2),
\Dual.gpio2_Data_In_reg[0]\(4) => gpio2_Data_In(3),
\Dual.gpio2_Data_In_reg[0]\(3) => gpio2_Data_In(4),
\Dual.gpio2_Data_In_reg[0]\(2) => gpio2_Data_In(5),
\Dual.gpio2_Data_In_reg[0]\(1) => gpio2_Data_In(6),
\Dual.gpio2_Data_In_reg[0]\(0) => gpio2_Data_In(7),
\Dual.gpio2_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_17,
\Dual.gpio2_OE_reg[0]\(0) => AXI_LITE_IPIF_I_n_18,
\Dual.gpio_OE_reg[0]\(0) => AXI_LITE_IPIF_I_n_16,
E(0) => AXI_LITE_IPIF_I_n_15,
GPIO_xferAck_i => GPIO_xferAck_i,
Q(4) => gpio_Data_In(0),
Q(3) => gpio_Data_In(1),
Q(2) => gpio_Data_In(2),
Q(1) => gpio_Data_In(3),
Q(0) => gpio_Data_In(4),
Read_Reg_In(0 to 4) => Read_Reg_In(0 to 4),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio2_io_t(7 downto 0) => \^gpio2_io_t\(7 downto 0),
gpio_io_t(4 downto 0) => \^gpio_io_t\(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[0]\(8) => ip2bus_data(0),
\ip2bus_data_i_D1_reg[0]\(7) => ip2bus_data(24),
\ip2bus_data_i_D1_reg[0]\(6) => ip2bus_data(25),
\ip2bus_data_i_D1_reg[0]\(5) => ip2bus_data(26),
\ip2bus_data_i_D1_reg[0]\(4) => ip2bus_data(27),
\ip2bus_data_i_D1_reg[0]\(3) => ip2bus_data(28),
\ip2bus_data_i_D1_reg[0]\(2) => ip2bus_data(29),
\ip2bus_data_i_D1_reg[0]\(1) => ip2bus_data(30),
\ip2bus_data_i_D1_reg[0]\(0) => ip2bus_data(31),
\ip2bus_data_i_D1_reg[0]_0\(8) => ip2bus_data_i_D1(0),
\ip2bus_data_i_D1_reg[0]_0\(7) => ip2bus_data_i_D1(24),
\ip2bus_data_i_D1_reg[0]_0\(6) => ip2bus_data_i_D1(25),
\ip2bus_data_i_D1_reg[0]_0\(5) => ip2bus_data_i_D1(26),
\ip2bus_data_i_D1_reg[0]_0\(4) => ip2bus_data_i_D1(27),
\ip2bus_data_i_D1_reg[0]_0\(3) => ip2bus_data_i_D1(28),
\ip2bus_data_i_D1_reg[0]_0\(2) => ip2bus_data_i_D1(29),
\ip2bus_data_i_D1_reg[0]_0\(1) => ip2bus_data_i_D1(30),
\ip2bus_data_i_D1_reg[0]_0\(0) => ip2bus_data_i_D1(31),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
reg1(4) => reg1(27),
reg1(3) => reg1(28),
reg1(2) => reg1(29),
reg1(1) => reg1(30),
reg1(0) => reg1(31),
reg3(7) => reg3(24),
reg3(6) => reg3(25),
reg3(5) => reg3(26),
reg3(4) => reg3(27),
reg3(3) => reg3(28),
reg3(2) => reg3(29),
reg3(1) => reg3(30),
reg3(0) => reg3(31),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2) => s_axi_araddr(8),
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2) => s_axi_awaddr(8),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(8) => \^s_axi_rdata\(30),
s_axi_rdata(7 downto 0) => \^s_axi_rdata\(7 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
gpio_core_1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
port map (
D(7 downto 3) => p_0_out(4 downto 0),
D(2) => AXI_LITE_IPIF_I_n_12,
D(1) => AXI_LITE_IPIF_I_n_13,
D(0) => AXI_LITE_IPIF_I_n_14,
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(4) => gpio_Data_In(0),
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(3) => gpio_Data_In(1),
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(2) => gpio_Data_In(2),
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(1) => gpio_Data_In(3),
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0\(0) => gpio_Data_In(4),
\Dual.gpio2_Data_In_reg[0]_0\ => AXI_LITE_IPIF_I_n_32,
\Dual.gpio2_Data_In_reg[1]_0\ => AXI_LITE_IPIF_I_n_31,
\Dual.gpio2_Data_In_reg[2]_0\ => AXI_LITE_IPIF_I_n_30,
\Dual.gpio2_Data_In_reg[3]_0\ => AXI_LITE_IPIF_I_n_29,
\Dual.gpio2_Data_In_reg[4]_0\ => AXI_LITE_IPIF_I_n_28,
\Dual.gpio2_Data_In_reg[5]_0\ => AXI_LITE_IPIF_I_n_27,
\Dual.gpio2_Data_In_reg[6]_0\ => AXI_LITE_IPIF_I_n_26,
\Dual.gpio2_Data_In_reg[7]_0\ => AXI_LITE_IPIF_I_n_25,
E(0) => AXI_LITE_IPIF_I_n_15,
GPIO_xferAck_i => GPIO_xferAck_i,
Q(7) => gpio2_Data_In(0),
Q(6) => gpio2_Data_In(1),
Q(5) => gpio2_Data_In(2),
Q(4) => gpio2_Data_In(3),
Q(3) => gpio2_Data_In(4),
Q(2) => gpio2_Data_In(5),
Q(1) => gpio2_Data_In(6),
Q(0) => gpio2_Data_In(7),
Read_Reg_In(0 to 4) => Read_Reg_In(0 to 4),
SS(0) => bus2ip_reset,
bus2ip_cs => bus2ip_cs,
bus2ip_rnw => bus2ip_rnw,
bus2ip_rnw_i_reg => AXI_LITE_IPIF_I_n_24,
bus2ip_rnw_i_reg_0(0) => AXI_LITE_IPIF_I_n_16,
bus2ip_rnw_i_reg_1(0) => AXI_LITE_IPIF_I_n_17,
bus2ip_rnw_i_reg_2(0) => AXI_LITE_IPIF_I_n_18,
gpio2_io_i(7 downto 0) => gpio2_io_i(7 downto 0),
gpio2_io_o(7 downto 0) => gpio2_io_o(7 downto 0),
gpio2_io_t(7 downto 0) => \^gpio2_io_t\(7 downto 0),
gpio_io_i(4 downto 0) => gpio_io_i(4 downto 0),
gpio_io_o(4 downto 0) => gpio_io_o(4 downto 0),
gpio_io_t(4 downto 0) => \^gpio_io_t\(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg => gpio_core_1_n_16,
reg1(4) => reg1(27),
reg1(3) => reg1(28),
reg1(2) => reg1(29),
reg1(1) => reg1(30),
reg1(0) => reg1(31),
reg3(7) => reg3(24),
reg3(6) => reg3(25),
reg3(5) => reg3(26),
reg3(4) => reg3(27),
reg3(3) => reg3(28),
reg3(2) => reg3(29),
reg3(1) => reg3(30),
reg3(0) => reg3(31),
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(0),
Q => ip2bus_data_i_D1(0),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(24),
Q => ip2bus_data_i_D1(24),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(25),
Q => ip2bus_data_i_D1(25),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(26),
Q => ip2bus_data_i_D1(26),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(27),
Q => ip2bus_data_i_D1(27),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_core_1_n_16,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_axi_gpio_1_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_gpio,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_gpio_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 1;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 1;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 8;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 5;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
attribute x_interface_info : string;
attribute x_interface_info of s_axi_aclk : signal is "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of s_axi_aclk : signal is "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of s_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
attribute x_interface_parameter of s_axi_aresetn : signal is "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW";
attribute x_interface_info of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
attribute x_interface_info of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
attribute x_interface_info of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
attribute x_interface_info of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
attribute x_interface_info of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
attribute x_interface_info of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
attribute x_interface_info of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
attribute x_interface_info of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
attribute x_interface_info of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
attribute x_interface_info of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
attribute x_interface_info of gpio2_io_i : signal is "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
attribute x_interface_parameter of gpio2_io_i : signal is "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE";
attribute x_interface_info of gpio_io_i : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
attribute x_interface_parameter of gpio_io_i : signal is "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
attribute x_interface_info of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
attribute x_interface_info of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
attribute x_interface_parameter of s_axi_awaddr : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute x_interface_info of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
attribute x_interface_info of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
attribute x_interface_info of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
attribute x_interface_info of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
attribute x_interface_info of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
port map (
gpio2_io_i(7 downto 0) => gpio2_io_i(7 downto 0),
gpio2_io_o(7 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(7 downto 0),
gpio2_io_t(7 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(7 downto 0),
gpio_io_i(4 downto 0) => gpio_io_i(4 downto 0),
gpio_io_o(4 downto 0) => NLW_U0_gpio_io_o_UNCONNECTED(4 downto 0),
gpio_io_t(4 downto 0) => NLW_U0_gpio_io_t_UNCONNECTED(4 downto 0),
ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
architecture RTL of ENT is
begin
-- Align left = no align paren = no
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_foo <=
resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_bar <= a or b and c
xor z and x or
w and z;
n_bar <=
a or b and c
xor z and x or
w and z;
-- Align left = no align paren = yes
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_foo <=
resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_bar <= a or b and c
xor z and x or
w and z;
n_bar <=
a or b and c
xor z and x or
w and z;
-- Align left = yes and align paren = no
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_foo <=
resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_bar <= a or b and c
xor z and x or
w and z;
n_bar <=
a or b and c
xor z and x or
w and z;
-- Align left = yes and align paren = yes
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_foo <=
resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_bar <= a or b and c
xor z and x or
w and z;
n_bar <=
a or b and c
xor z and x or
w and z;
end architecture RTL;
|
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_data_steer.vhd,v 1.1 2003/02/18 19:16:01 ostlerf Exp $
-------------------------------------------------------------------------------
-- IPIF_Data_Steer - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_data_steer.vhd
-- Version: v1.10.a
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_data_steer.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2-5-2002 -- First version
-- ^^^^^^
-- First version of IPIF steering logic.
-- ~~~~~~
-- BLT 2-12-2002 -- Removed BE_Steer, now generated internally
--
-- DET 2-24-2002 -- Added 'When others' to size case statement
-- in BE_STEER_PROC process.
-- BLT 5-13-2002 -- Added capability for peripherals larger
-- than bus, new optimizations
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_misc.all;
library ipif_common_v1_00_c;
use ipif_common_v1_00_c.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH_BUS : integer := width of host databus attached to the IPIF
-- C_DWIDTH_IP : integer := width of IP databus attached to the IPIF
-- C_SMALLEST_MASTER : integer := width of smallest master (not access size)
-- attached to the IPIF
-- C_SMALLEST_IP : integer := width of smallest IP device (not access size)
-- attached to the IPIF
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- BE_Steer : in BE_Steer = 1 : steer BE's onto IPIF BE bus
-- BE_Steer = 0 : don't steer BE's, pass through
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity IPIF_Data_Steer is
generic (
C_DWIDTH_BUS : integer := 32; -- 8, 16, 32, 64, 128, 256, or 512
C_DWIDTH_IP : integer := 64; -- 8, 16, 32, 64, 128, 256, or 512
C_SMALLEST_MASTER : integer := 32; -- 8, 16, 32, 64, 128, 256, or 512
C_SMALLEST_IP : integer := 8; -- 8, 16, 32, 64, 128, 256, or 512
C_AWIDTH : integer := 32
);
port (
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH_BUS-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH_IP-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH_BUS/8-1);
Decode_size : in std_logic_vector(0 to 2);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH_IP-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH_BUS-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH_IP/8-1)
);
end entity IPIF_Data_Steer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of IPIF_Data_Steer is
component Steer_Module_Write is
generic (
C_DWIDTH_IN : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_DWIDTH_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_SMALLEST_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH : integer
);
port (
Data_In : in std_logic_vector(0 to C_DWIDTH_IN-1);
BE_In : in std_logic_vector(0 to C_DWIDTH_IN/8-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
Decode_size : in std_logic_vector(0 to 2);
Data_Out : out std_logic_vector(0 to C_DWIDTH_OUT-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH_OUT/8-1)
);
end component Steer_Module_Write;
component Steer_Module_Read is
generic (
C_DWIDTH_IN : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_DWIDTH_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_IN : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH : integer
);
port (
Data_In : in std_logic_vector(0 to C_DWIDTH_IN-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
Decode_size : in std_logic_vector(0 to 2);
Data_Out : out std_logic_vector(0 to C_DWIDTH_OUT-1)
);
end component Steer_Module_Read;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- OPB Data Muxing and Steering
-----------------------------------------------------------------------------
-- Size indication (Decode_size)
-- n = 001 byte 2^0
-- n = 010 halfword 2^1
-- n = 011 word 2^2
-- n = 100 doubleword 2^3
-- n = 101 128-b
-- n = 110 256-b
-- n = 111 512-b
-- num_bytes = 2^(n-1)
WRITE_I: Steer_Module_Write
generic map (
C_DWIDTH_IN => C_DWIDTH_BUS, -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_DWIDTH_OUT => C_DWIDTH_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_SMALLEST_OUT => C_SMALLEST_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH => C_AWIDTH )
port map (
Data_In => Wr_Data_In, --[in]
BE_In => BE_In, --[in]
Addr => Addr, --[in]
Decode_size => Decode_size, --[in]
Data_Out => Wr_Data_Out, --[out]
BE_Out => BE_Out --[out]
);
READ_I: Steer_Module_Read
generic map (
C_DWIDTH_IN => C_DWIDTH_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_DWIDTH_OUT => C_DWIDTH_BUS, -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_OUT => C_SMALLEST_MASTER, -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_IN => C_SMALLEST_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH => C_AWIDTH )
port map (
Data_In => Rd_Data_In, --[in]
Addr => Addr, --[in]
Decode_size => Decode_size, --[in]
Data_Out => Rd_Data_Out --[out]
);
end architecture IMP;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity <<ENTITY_NAME>>_tb is
end <<ENTITY_NAME>>_tb;
architecture <<ARCH_TYPE>> of <<ENTITY_NAME>>_tb is
-- Declaração do componente.
component <<ENTITY_NAME>>
port (<<IN_P>>: in <<type>>; <<OUT_P>>: out <<type>>);
end component;
-- Especifica qual a entidade está vinculada com o componente.
for <<ENTITY_NAME>>_0: <<ENTITY_NAME>> use entity work.<<ENTITY_NAME>>;
signal <<s_t_sinais>>: <<type>>;
begin
-- Instanciação do Componente.
-- port map (<<p_in_1>> => <<s_t_in_1>>)
<<ENTITY_NAME>>_0: <<ENTITY_NAME>> port map (<<port_map_entity_tb>>);
-- Processo que faz o trabalho.
process
-- Um registro é criado com as entradas e saídas da entidade.
-- (<<entrada1>>, <<entradaN>>, <<saida1>>, <<saidaN>>)
type pattern_type is record
-- entradas.
<<record_in_vars>>: <<type>>;
-- saídas.
<<record_out_vars>>: <<type>>;
end record;
-- Os padrões de entrada que são aplicados (injetados) às entradas.
type pattern_array is array (natural range <>) of pattern_type;
-- Casos de teste.
constant patterns : pattern_array :=
(
(casos de testes com <<case_test_model>> colunas, '0'...),
(...)
);
begin
-- Checagem de padrões.
for i in patterns'range loop
-- Injeta as entradas.
<<inputs_signals_injection>>
-- Aguarda os resultados.
wait for 1 ns;
-- Checa o resultado com a saída esperada no padrão.
<<asserts_vars>>
end loop;
assert false report "Fim do teste." severity note;
-- Wait forever; Isto finaliza a simulação.
wait;
end process;
end <<ARCH_TYPE>>;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-02 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_01300_bad.vhd
-- File Creation date : 2015-04-02
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Number of ports declaration per line: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.pkg_HBK.all;
--CODE
entity STD_01300_bad is
port (
i_Clock, i_Reset_n, i_D : in std_logic; -- Clock, reset & D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_01300_bad;
architecture Behavioral of STD_01300_bad is
begin
DFlipFlop1 : DFlipFlop
port map (
i_Clock => i_Clock, i_Reset_n => i_Reset_n, i_D => i_D, o_Q => o_Q, o_Q_n => open
);
end Behavioral;
--CODE
|
library IEEE;
use IEEE.std_logic_1164.all;
--------------------------------------------------------------------------------
package main_tb_pkg is
----------------------------------------------------------------------------
-- Types & Constants
----------------------------------------------------------------------------
constant C_MAX_STRING_LENGTH : natural := 50;
constant C_TESTCASES : natural := 6;
type T_TESTCASE is record
NAME : string(1 to C_MAX_STRING_LENGTH);
L_NAME : natural;
BITS : natural;
PERIOD : natural;
EXPECTED : time;
end record;
type T_TESTSUITE is array (0 to C_TESTCASES-1) of T_TESTCASE;
type T_TESTRESULT is record
PASS_nFAIL : std_logic;
DONE : std_logic;
RUNTIME : time;
end record;
type T_TESTRESULTS is array (0 to C_TESTCASES-1) of T_TESTRESULT;
function done (
RESULTS : T_TESTRESULTS
) return std_logic;
function failures (
RESULTS : T_TESTRESULTS
) return natural;
end main_tb_pkg; |
architecture RTL of FIFO is
constant c_width : integer := 16;
constant c_depth : integer := 512;
constant c_word : integer := (12, 13, 15);
begin
process
constant c_width : integer := 16;
constant c_depth : integer := 512;
constant c_word : integer := (12, 13, 15);
constant c_word : integer := (12, 13, 15);
begin end process;
end architecture RTL;
|
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 23:40:00 11/19/2016
-- Design Name:
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.0
-- Description: This is the package for the AXI interfaces.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
-- Revision 0.2 - Changed indentation
-- Revision 0.3 - Updated package name
-- Added constants, subprograms and interface definition
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package axi is
------------------------------------------------------------------------------
-- Constants
------------------------------------------------------------------------------
constant cslv_axsize_1 : std_logic_vector(2 downto 0) := "000";
constant cslv_axsize_2 : std_logic_vector(2 downto 0) := "001";
constant cslv_axsize_4 : std_logic_vector(2 downto 0) := "010";
constant cslv_axsize_8 : std_logic_vector(2 downto 0) := "011";
constant cslv_axsize_16 : std_logic_vector(2 downto 0) := "100";
constant cslv_axsize_32 : std_logic_vector(2 downto 0) := "101";
constant cslv_axsize_64 : std_logic_vector(2 downto 0) := "110";
constant cslv_axsize_128 : std_logic_vector(2 downto 0) := "111";
constant cslv_axburst_fixed : std_logic_vector(1 downto 0) := "00";
constant cslv_axburst_incr : std_logic_vector(1 downto 0) := "01";
constant cslv_axburst_wrap : std_logic_vector(1 downto 0) := "10";
constant cslv_awlock_normal : std_logic_vector(1 downto 0) := "00";
constant cslv_awlock_exclusive : std_logic_vector(1 downto 0) := "01";
constant cslv_awlock_locked : std_logic_vector(1 downto 0) := "10";
constant cslv_axcache_dev_non_buf : std_logic_vector(3 downto 0) := "0000";
constant cslv_axcache_dev_buf : std_logic_vector(3 downto 0) := "0001";
constant cslv_axcache_norm_nc_nb : std_logic_vector(3 downto 0) := "0010";
constant cslv_axcache_norm_nc_b : std_logic_vector(3 downto 0) := "0010";
constant cslv_arcache_wt_no_alloc : std_logic_vector(3 downto 0) := "0011";
constant cslv_awcache_wt_no_alloc : std_logic_vector(3 downto 0) := "0110";
constant cslv_arcache_wt_r_alloc : std_logic_vector(3 downto 0) := "1110";
constant cslv_awcache_wt_r_alloc : std_logic_vector(3 downto 0) := "0110";
constant cslv_arcache_wt_w_alloc : std_logic_vector(3 downto 0) := "1010";
constant cslv_awcache_wt_w_alloc : std_logic_vector(3 downto 0) := "1110";
constant cslv_axcache_wtr_w_alloc : std_logic_vector(3 downto 0) := "1110";
constant cslv_arcache_wb_no_alloc : std_logic_vector(3 downto 0) := "1011";
constant cslv_awcache_wb_no_alloc : std_logic_vector(3 downto 0) := "0111";
constant cslv_arcache_wb_r_alloc : std_logic_vector(3 downto 0) := "1111";
constant cslv_awcache_wb_r_alloc : std_logic_vector(3 downto 0) := "0111";
constant cslv_axprot_u_access : std_logic_vector(2 downto 0) := "000";
constant cslv_axprot_p_access : std_logic_vector(2 downto 0) := "001";
constant cslv_axprot_s_access : std_logic_vector(2 downto 0) := "010";
constant cslv_axprot_ns_access : std_logic_vector(2 downto 0) := "011";
constant cslv_axprot_d_access : std_logic_vector(2 downto 0) := "100";
constant cslv_axprot_i_access : std_logic_vector(2 downto 0) := "100";
constant cslv_xresp_okay : std_logic_vector(1 downto 0) := "00";
constant cslv_xresp_exokay : std_logic_vector(1 downto 0) := "01";
constant cslv_xresp_slverr : std_logic_vector(1 downto 0) := "10";
constant cslv_xresp_decerr : std_logic_vector(1 downto 0) := "11";
------------------------------------------------------------------------------
-- AXI-4 Global Signals
------------------------------------------------------------------------------
type t_axi_wa_slv_in is record
slv_awid : std_logic_vector(3 downto 0);
slv_awaddr : std_logic_vector(31 downto 0);
slv_awlen : std_logic_vector(7 downto 0);
slv_awsize : std_logic_vector(2 downto 0);
slv_awburst : std_logic_vector(1 downto 0);
slv_awlock : std_logic_vector(1 downto 0);
slv_awcache : std_logic_Vector(3 downto 0);
slv_awprot : std_logic_vector(2 downto 0);
sl_awvalid : std_ulogic;
end record;
type t_axi_wa_slv_out is record
sl_awready : std_ulogic;
end record;
type t_axi_wd_slv_in is record
slv_wdata : std_logic_vector(31 downto 0);
slv_wstrb : std_logic_vector(3 downto 0);
sl_wlast : std_ulogic;
sl_wvalid : std_ulogic;
end record;
type t_axi_wd_slv_out is record
sl_wready : std_ulogic;
end record;
type t_axi_wr_slv_in is record
sl_bready : std_ulogic;
end record;
type t_axi_wr_slv_out is record
sl_bid : std_ulogic;
sl_bresp : std_ulogic;
sl_bvalid : std_ulogic;
end record;
type t_axi4_wd_slv_in is record
r_axi : t_axi_wd_slv_in;
sl_wuser : std_ulogic;
end record;
type t_axi_ra_slv_in is record
slv_arid : std_logic_vector(1 downto 0);
slv_araddr : std_logic_vector(31 downto 0);
slv_arlen : std_logic_vector(7 downto 0);
slv_arsize : std_logic_vector(2 downto 0);
slv_arburst : std_logic_vector(1 downto 0);
sl_arlock : std_logic;
slv_arcache : std_logic_vector(3 downto 0);
slv_arprot : std_logic_vector(2 downto 0);
slv_arqos : std_logic_vector(3 downto 0);
slv_arregion : std_logic_vector(3 downto 0);
sl_aruser : std_logic;
sl_arvalid : std_logic;
end record;
type t_axi_ra_slv_out is record
sl_arready : std_ulogic;
end record;
type t_axi_rd_slv_in is record
sl_rready : std_logic;
end record;
type t_axi_rd_slv_out is record
sl_rid : std_logic;
slv_rdata : std_logic_vector(31 downto 0);
slv_rresp : std_logic_vector(1 downto 0);
sl_rlast : std_logic;
sl_ruser : std_logic;
sl_rvalid : std_logic;
end record;
type t_axi_lpi_slv_in is record
sl_csysreq : std_ulogic;
end record;
type t_axi_lpi_slv_out is record
sl_csysack : std_ulogic;
sl_cactive : std_ulogic;
end record;
------------------------------------------------------------------------------
-- Sub-programs
------------------------------------------------------------------------------
--function axi_device_reg()
--return std_logic_vector;
function axireadword (
rdata : std_logic_vector(31 downto 0);
raddr : std_logic_vector(4 downto 0))
return std_logic_vector;
procedure axireadword (
rdata : in std_logic_vector(31 downto 0);
raddr : in std_logic_vector(4 downto 0);
data : out std_logic_vector(31 downto 0));
------------------------------------------------------------------------------
-- Components
------------------------------------------------------------------------------
component axi3_slave
port (
-- global signals
sl_aclk : in std_ulogic;
sl_aresetn : in std_ulogic;
-- write address channel
-- write data channel
-- write response channel
-- read data channel
-- low power interface
r_lpi_in : in t_axi_lpi_slv_in;
r_lpi_out : out t_axi_lpi_slv_out
);
end component;
component axi4_slave
port (
-- global signals
sl_aclk : in std_ulogic;
sl_areset_n : in std_ulogic;
-- write address channel
r_wac_in : in t_axi_wa_slv_in;
awqos : in std_logic_vector(3 downto 0);
awregion : in std_logic_vector(3 downto 0);
awuser : in std_ulogic;
r_wac_out : out t_axi_wa_slv_out;
-- write data channel
r_wdc_in : in t_axi4_wd_slv_in;
r_wdc_out : out t_axi_wd_slv_out;
-- write response channel
r_wrc_in : in t_axi_wr_slv_in;
r_wrc_out : out t_axi_wr_slv_out;
-- read address channel
r_rac_in : in t_axi_ra_slv_in;
r_rac_out : out t_axi_ra_slv_out;
-- read data channel
r_rdc_in : in t_axi_rd_slv_in;
r_rdc_out : out t_axi_rd_slv_out;
-- low power interface
r_lpi_in : in t_axi_lpi_slv_in;
r_lpi_out : out t_axi_lpi_slv_out
);
end component;
component axi4_light_slave
port (
-- global signals
sl_aclk : in std_ulogic;
sl_areset_n : in std_ulogic
);
end component;
end axi;
package body axi is
function axireadword (
rdata : std_logic_vector(31 downto 0);
raddr : std_logic_vector(4 downto 0))
return std_logic_vector is
begin
end axireadword;
procedure axireadword (
rdata : in std_logic_vector(31 downto 0);
raddr : in std_logic_vector(4 downto 0);
data : out std_logic_vector(31 downto 0)) is
begin
end axireadword;
end;
|
library verilog;
use verilog.vl_types.all;
entity mem_shifter is
port(
mem_data_out : in vl_logic_vector(31 downto 0);
mem_addr_in : in vl_logic_vector(1 downto 0);
IR_out : in vl_logic_vector(5 downto 0);
mem_data_shift : out vl_logic_vector(31 downto 0);
Rd_write_byte_en: out vl_logic_vector(3 downto 0)
);
end mem_shifter;
|
-------------------------------------------------------------------------------
-- $Id: pselect_mask.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_mask.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_mask.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect_mask.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- goran 2002-02-06 First Version
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- PS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_mask is
generic (
C_AW : integer := 32;
C_BAR : std_logic_vector(0 to 31) := "00000000000000100000000000000000";
C_MASK : std_logic_vector(0 to 31) := "00000000000001111100000000000000"
);
port (
A : in std_logic_vector(0 to C_AW-1);
Valid : in std_logic;
CS : out std_logic
);
end entity pselect_mask;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
library unisim;
use unisim.all;
architecture imp of pselect_mask is
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic := '0';
-- I1 : in std_logic := '0';
-- I2 : in std_logic := '0';
-- I3 : in std_logic := '0');
-- end component;
-- component MUXCY is
-- port (
-- O : out std_logic;
-- CI : in std_logic;
-- DI : in std_logic;
-- S : in std_logic
-- );
-- end component MUXCY;
function Nr_Of_Ones (S : std_logic_vector) return natural is
variable tmp : natural := 0;
begin -- function Nr_Of_Ones
for I in S'range loop
if (S(I) = '1') then
tmp := tmp + 1;
end if;
end loop; -- I
return tmp;
end function Nr_Of_Ones;
function fix_AB (B : boolean; I : integer) return integer is
begin -- function fix_AB
if (not B) then
return I + 1;
else
return I;
end if;
end function fix_AB;
constant Nr : integer := Nr_Of_Ones(C_MASK);
constant Use_CIN : boolean := ((Nr mod 4) = 0);
constant AB : integer := fix_AB(Use_CIN, Nr);
attribute INIT : string;
constant NUM_LUTS : integer := (AB-1)/4+1;
-- signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
-- signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-- function to initialize LUT within pselect
type int4 is array (3 downto 0) of integer;
function pselect_init_lut(i : integer;
AB : integer;
NUM_LUTS : integer;
C_AW : integer;
C_BAR : std_logic_vector(0 to 31))
return bit_vector is
variable init_vector : bit_vector(15 downto 0) := X"0001";
variable j : integer := 0;
variable val_in : int4;
begin
for j in 0 to 3 loop
if i < NUM_LUTS-1 or j <= ((AB-1) mod 4) then
val_in(j) := conv_integer(C_BAR(i*4+j));
else val_in(j) := 0;
end if;
end loop;
init_vector := To_bitvector(conv_std_logic_vector(2**(val_in(3)*8+
val_in(2)*4+val_in(1)*2+val_in(0)*1),16));
return init_vector;
end pselect_init_lut;
signal A_Bus : std_logic_vector(0 to AB);
signal BAR : std_logic_vector(0 to AB);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin -- VHDL_RTL
Make_Busses : process (A,Valid) is
variable tmp : natural;
begin -- process Make_Busses
tmp := 0;
A_Bus <= (others => '0');
BAR <= (others => '0');
for I in C_MASK'range loop
if (C_MASK(I) = '1') then
A_Bus(tmp) <= A(I);
BAR(tmp) <= C_BAR(I);
tmp := tmp + 1;
end if;
end loop; -- I
if (not Use_CIN) then
BAR(tmp) <= '1';
A_Bus(tmp) <= Valid;
end if;
end process Make_Busses;
-- More_Than_3_Bits : if (AB > 3) generate
-- Using_CIn: if (Use_CIN) generate
-- carry_chain(0) <= Valid;
-- end generate Using_CIn;
-- No_CIn: if (not Use_CIN) generate
-- carry_chain(0) <= '1';
-- end generate No_CIn;
-- GEN_DECODE : for i in 0 to NUM_LUTS-1 generate
-- signal lut_in : std_logic_vector(3 downto 0);
-- begin
-- GEN_LUT_INPUTS : for j in 0 to 3 generate
-- -- Generate to assign address bits to LUT4 inputs
-- GEN_INPUT : if i < NUM_LUTS-1 or j <= ((AB-1) mod 4) generate
-- lut_in(j) <= A_Bus(i*4+j);
-- end generate;
-- -- Generate to assign zeros to remaining LUT4 inputs
-- GEN_ZEROS : if not(i < NUM_LUTS-1 or j <= ((AB-1) mod 4)) generate
-- lut_in(j) <= '0';
-- end generate;
-- end generate;
---------------------------------------------------------------------------------
---- RTL version without LUT instantiation for XST
---------------------------------------------------------------------------------
-- lut_out(i) <= (lut_in(0) xnor BAR(i*4+0)) and
-- (lut_in(1) xnor BAR(i*4+1)) and
-- (lut_in(2) xnor BAR(i*4+2)) and
-- (lut_in(3) xnor BAR(i*4+3));
---------------------------------------------------------------------------------
---- Structural version with LUT instantiation for Synplicity (when RLOC is
---- desired for placing LUT
---------------------------------------------------------------------------------
---- LUT4_I : LUT4
---- generic map(
---- -- Function init_lut is used to generate INIT value for LUT4
---- INIT => pselect_init_lut(i,C_AB,NUM_LUTS,C_AW,C_BAR)
---- )
---- port map (
---- O => lut_out(i), -- [out]
---- I0 => lut_in(0), -- [in]
---- I1 => lut_in(1), -- [in]
---- I2 => lut_in(2), -- [in]
---- I3 => lut_in(3)); -- [in]
---------------------------------------------------------------------------------
-- MUXCY_I : MUXCY
-- port map (
-- O => carry_chain(i+1), --[out]
-- CI => carry_chain(i), --[in]
-- DI => '0', --[in]
-- S => lut_out(i) --[in]
-- );
-- end generate;
-- CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output
-- end generate More_Than_3_Bits;
-- Less_than_4_bits: if (AB < 4) generate
CS <= Valid when A_Bus=BAR else '0';
-- end generate Less_than_4_bits;
end imp;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY PC IS
PORT (
input : IN std_logic_vector(15 DOWNTO 0);
en_in, clock, done, reset : IN std_logic;
read_addr : OUT INTEGER
);
END PC;
ARCHITECTURE behavioural OF PC IS
SIGNAL addr_temp : INTEGER := 0;
BEGIN
PROCESS (clock, done, reset, en_in, input)
BEGIN
IF reset = '1' THEN
addr_temp <= 0;
ELSIF en_in = '1' THEN
addr_temp <= to_integer(unsigned(input));
ELSIF rising_edge(clock) AND done = '1' THEN
addr_temp <= addr_temp + 1;
END IF;
END PROCESS;
read_addr <= addr_temp;
END behavioural; |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst.vhd
--
-- Description:
--
-- AXI Master interface utilizing Xilinx LocalLink interface for User Logic
-- Side (IPIC) data transfer interface
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_master_burst.vhd
-- |
-- |-- proc_common_v4_0 (helper library)
-- |
-- |-- axi_master_burst_reset.vhd
-- |
-- |-- axi_master_rd_llink.vhd
-- |
-- |-- axi_master_wr_llink.vhd
-- |
-- |
-- |-- axi_master_burst_cmd_status.vhd
-- | |-- axi_master_burst_first_stb_offset.vhd
-- | |-- axi_master_burst_stbs_set.vhd
-- |
-- |-- axi_master_burst_rd_wr_cntlr.vhd
-- |-- axi_master_burst_pcc.vhd
-- | |-- axi_master_burst_strb_gen.vhd
-- |-- axi_master_burst_addr_cntl.vhd
-- | |-- axi_master_burst_fifo.vhd
-- | |-- proc_common_v4_0.srl_fifo_f
-- |-- axi_master_burst_rddata_cntl.vhd
-- | |-- axi_master_burst_rdmux.vhd
-- | |-- axi_master_burst_fifo.vhd
-- | |-- proc_common_v4_0.srl_fifo_f
-- |-- axi_master_burst_wrdata_cntl.vhd
-- | |-- axi_master_burst_strb_gen
-- | |-- axi_master_burst_fifo.vhd
-- | |-- proc_common_v4_0.srl_fifo_f
-- |-- axi_master_burst_rd_status_cntl.vhd
-- |-- axi_master_burst_wr_status_cntl.vhd
-- | |-- axi_master_burst_fifo.vhd
-- | |-- proc_common_v4_0.srl_fifo_f
-- |-- axi_master_burst_skid_buf.vhd
-- |-- axi_master_burst_skid2mm_buf.vhd
--
--
-------------------------------------------------------------------------------
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $$
--
-- History:
-- DET 01/18/2011 Version 1_00_a
--
-- DET 2/10/2011 Initial for EDK 13.1
-- ~~~~~~
-- -- Per CR593346
-- - Connected md_error output to the axi_master_burst_cmd_status rw_error
-- output.
-- ^^^^^^
--
-- DET 2/17/2011 Initial for 13.2
-- ~~~~~~
-- -- Per CR593967
-- - Added the port rdwr2llink_int_err to the Cmd/Status Module.
-- This output is now used to initiate a Locallink discontinue
-- when an internal error is detected.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axi_master_burst_v2_0;
Use axi_master_burst_v2_0.axi_master_burst_reset ;
Use axi_master_burst_v2_0.axi_master_burst_cmd_status ;
Use axi_master_burst_v2_0.axi_master_burst_rd_wr_cntlr ;
Use axi_master_burst_v2_0.axi_master_burst_rd_llink ;
Use axi_master_burst_v2_0.axi_master_burst_wr_llink ;
-------------------------------------------------------------------------------
entity axi_master_burst is
generic (
----------------------------------------------------------------------------
-- AXI4 Related Parameters
----------------------------------------------------------------------------
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
-- DataMover Master AXI Memory Map Address Width (bits)
C_M_AXI_DATA_WIDTH : integer range 32 to 256 := 32;
-- DataMover Master AXI Memory Map Data Width (bits)
C_MAX_BURST_LEN : Integer range 16 to 256 := 16;
-- Specifies the max number of databeats to use for each AXI MMap
-- transfer by the AXI Master Burst
C_ADDR_PIPE_DEPTH : Integer range 1 to 14 := 1;
-- Specifies the address pipeline depth for the AXI Master Burst
-- when submitting transfer requests to the AXI4 Read and Write
-- Address Channels.
----------------------------------------------------------------------------
-- IPIC Related Parameters
----------------------------------------------------------------------------
C_NATIVE_DATA_WIDTH : INTEGER range 32 to 128 := 32;
-- Set this equal to desired data bus width needed by IPIC
-- LocalLink Data Channels.
C_LENGTH_WIDTH : INTEGER range 12 to 20 := 12;
-- Set this to the desired bit width for the ip2bus_mst_length
-- input port required to specify the maximimum transfer byte
-- count needed for any one command by the User logic.
-- 12 bits = 4095 bytes max per command
-- 13 bits = 8191 bytes max per command
-- 14 bits = 16383 bytes max per command
-- 15 bits = 32767 bytes max per command
-- 16 bits = 65535 bytes max per command
-- 17 bits = 131071 bytes max per command
-- 18 bits = 262143 bytes max per command
-- 19 bits = 524287 bytes max per command
-- 20 bits = 1048575 bytes max per command
----------------------------------------------------------------------------
-- Target FPGA Family Parameter
----------------------------------------------------------------------------
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
----------------------------------------------------------------------------
-- Primary Clock
----------------------------------------------------------------------------
m_axi_aclk : in std_logic ;-- AXI4
----------------------------------------------------------------------------
-- Primary Reset Input (active low)
----------------------------------------------------------------------------
m_axi_aresetn : in std_logic ;-- AXI4
-----------------------------------------------------------------------
-- Master Detected Error output
-----------------------------------------------------------------------
md_error : out std_logic ;-- Error output discrete
----------------------------------------------------------------------------
-- AXI4 Master Read Channel
----------------------------------------------------------------------------
-- MMap Read Address Channel -- AXI4
m_axi_arready : in std_logic ;-- AXI4
m_axi_arvalid : out std_logic ;-- AXI4
m_axi_araddr : out std_logic_vector -- AXI4
(C_M_AXI_ADDR_WIDTH-1 downto 0) ;-- AXI4
m_axi_arlen : out std_logic_vector(7 downto 0) ;-- AXI4
m_axi_arsize : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_arburst : out std_logic_vector(1 downto 0) ;-- AXI4
m_axi_arprot : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_arcache : out std_logic_vector(3 downto 0) ;-- AXI4
-- AXI4
-- MMap Read Data Channel -- AXI4
m_axi_rready : out std_logic ;-- AXI4
m_axi_rvalid : in std_logic ;-- AXI4
m_axi_rdata : in std_logic_vector -- AXI4
(C_M_AXI_DATA_WIDTH-1 downto 0) ;-- AXI4
m_axi_rresp : in std_logic_vector(1 downto 0) ;-- AXI4
m_axi_rlast : in std_logic ;-- AXI4
-----------------------------------------------------------------------------
-- AXI4 Master Write Channel
-----------------------------------------------------------------------------
-- Write Address Channel -- AXI4
m_axi_awready : in std_logic ; -- AXI4
m_axi_awvalid : out std_logic ; -- AXI4
m_axi_awaddr : out std_logic_vector -- AXI4
(C_M_AXI_ADDR_WIDTH-1 downto 0) ; -- AXI4
m_axi_awlen : out std_logic_vector(7 downto 0) ; -- AXI4
m_axi_awsize : out std_logic_vector(2 downto 0) ; -- AXI4
m_axi_awburst : out std_logic_vector(1 downto 0) ; -- AXI4
m_axi_awprot : out std_logic_vector(2 downto 0) ; -- AXI4
m_axi_awcache : out std_logic_vector(3 downto 0) ; -- AXI4
-- AXI4
-- Write Data Channel -- AXI4
m_axi_wready : in std_logic ; -- AXI4
m_axi_wvalid : out std_logic ; -- AXI4
m_axi_wdata : out std_logic_vector -- AXI4
(C_M_AXI_DATA_WIDTH-1 downto 0) ; -- AXI4
m_axi_wstrb : out std_logic_vector -- AXI4
((C_M_AXI_DATA_WIDTH/8)-1 downto 0); -- AXI4
m_axi_wlast : out std_logic ; -- AXI4
-- AXI4
-- Write Response Channel -- AXI4
m_axi_bready : out std_logic ; -- AXI4
m_axi_bvalid : in std_logic ; -- AXI4
m_axi_bresp : in std_logic_vector(1 downto 0) ; -- AXI4
-----------------------------------------------------------------------------------------
-- IPIC Request/Qualifiers
-----------------------------------------------------------------------------------------
ip2bus_mstrd_req : In std_logic ;-- IPIC CMD
ip2bus_mstwr_req : In std_logic ;-- IPIC CMD
ip2bus_mst_addr : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) ;-- IPIC CMD
ip2bus_mst_length : in std_logic_vector(C_LENGTH_WIDTH-1 downto 0) ;-- IPIC CMD
ip2bus_mst_be : in std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);-- IPIC CMD
ip2bus_mst_type : in std_logic ;-- IPIC CMD
ip2bus_mst_lock : In std_logic ;-- IPIC CMD
ip2bus_mst_reset : In std_logic ;-- IPIC CMD
-----------------------------------------------------------------------------------------
-- IPIC Request Status Reply
-----------------------------------------------------------------------------------------
bus2ip_mst_cmdack : Out std_logic ;-- IPIC Stat
bus2ip_mst_cmplt : Out std_logic ;-- IPIC Stat
bus2ip_mst_error : Out std_logic ;-- IPIC Stat
bus2ip_mst_rearbitrate : Out std_logic ;-- IPIC Stat
bus2ip_mst_cmd_timeout : out std_logic ;-- IPIC Stat
-----------------------------------------------------------------------------------------
-- IPIC Read LocalLink Channel
-----------------------------------------------------------------------------------------
bus2ip_mstrd_d : out std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0 ) ;-- IPIC RD LLink
bus2ip_mstrd_rem : out std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);-- IPIC RD LLink
bus2ip_mstrd_sof_n : Out std_logic ;-- IPIC RD LLink
bus2ip_mstrd_eof_n : Out std_logic ;-- IPIC RD LLink
bus2ip_mstrd_src_rdy_n : Out std_logic ;-- IPIC RD LLink
bus2ip_mstrd_src_dsc_n : Out std_logic ;-- IPIC RD LLink
ip2bus_mstrd_dst_rdy_n : In std_logic ;-- IPIC RD LLink
ip2bus_mstrd_dst_dsc_n : In std_logic ;-- IPIC RD LLink
-----------------------------------------------------------------------------------------
-- IPIC Write LocalLink Channel
-----------------------------------------------------------------------------------------
ip2bus_mstwr_d : In std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0) ;-- IPIC WR LLink
ip2bus_mstwr_rem : In std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);-- IPIC WR LLink
ip2bus_mstwr_sof_n : In std_logic ;-- IPIC WR LLink
ip2bus_mstwr_eof_n : In std_logic ;-- IPIC WR LLink
ip2bus_mstwr_src_rdy_n : In std_logic ;-- IPIC WR LLink
ip2bus_mstwr_src_dsc_n : In std_logic ;-- IPIC WR LLink
bus2ip_mstwr_dst_rdy_n : Out std_logic ;-- IPIC WR LLink
bus2ip_mstwr_dst_dsc_n : Out std_logic -- IPIC WR LLink
);
end entity axi_master_burst;
architecture implementation of axi_master_burst is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant LLINK_DWIDTH : integer := C_NATIVE_DATA_WIDTH;
Constant LENGTH_WIDTH : integer := C_LENGTH_WIDTH;
Constant PCC_CMD_WIDTH : integer := 68; -- in bits
Constant STATUS_WIDTH : integer := 8; -- in bits
Constant RDWR_ID_WIDTH : integer := 4; -- in bits
Constant RDWR_ID : integer := 0; -- in bits
Constant RDWR_MAX_BURST_LEN : integer := C_MAX_BURST_LEN; -- in data beats
Constant RDWR_BTT_USED : integer := LENGTH_WIDTH;
Constant RDWR_ADDR_PIPE_DEPTH : integer := C_ADDR_PIPE_DEPTH;
-- Signal Declarations
signal sig_ipic_reset : std_logic := '0';
signal sig_rst2cmd_stat_reset : std_logic := '0';
signal sig_rst2rdwr_cntlr_reset : std_logic := '0';
signal sig_rst2llink_reset : std_logic := '0';
signal sig_rw_error : std_logic := '0';
signal sig_rdwr2llink_int_err : std_logic := '0';
signal sig_ip2bus_mstrd_req : std_logic := '0';
signal sig_ip2bus_mstwr_req : std_logic := '0';
signal sig_ip2bus_mst_addr : std_logic_vector(0 to C_M_AXI_ADDR_WIDTH-1) := (others => '0');
signal sig_ip2bus_mst_length : std_logic_vector(0 to LENGTH_WIDTH-1) := (others => '0');
signal sig_ip2bus_mst_be : std_logic_vector(0 to (C_NATIVE_DATA_WIDTH/8)-1) := (others => '0');
signal sig_ip2bus_mst_type : std_logic := '0';
signal sig_ip2bus_mst_lock : std_logic := '0';
signal sig_bus2ip_mst_cmdack : std_logic := '0';
signal sig_bus2ip_mst_cmplt : std_logic := '0';
signal sig_bus2ip_mst_error : std_logic := '0';
signal sig_bus2ip_mst_rearbitrate : std_logic := '0';
signal sig_bus2ip_mst_cmd_timeout : std_logic := '0';
signal sig_llink2cmd_rd_busy : std_logic := '0';
signal sig_llink2cmd_wr_busy : std_logic := '0';
signal sig_pcc2cmd_cmd_ready : std_logic := '0';
signal sig_cmd2pcc_cmd_valid : std_logic := '0';
signal sig_cmd2pcc_command : std_logic_vector(PCC_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2all_doing_read : std_logic := '0';
signal sig_cmd2all_doing_write : std_logic := '0';
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_llink2rd_allow_addr_req : std_logic := '0';
signal sig_rd2llink_addr_req_posted : std_logic := '0';
signal sig_rd2llink_xfer_cmplt : std_logic := '0';
signal sig_llink2wr_allow_addr_req : std_logic := '0';
signal sig_wr2llink_addr_req_posted : std_logic := '0';
signal sig_wr2llink_xfer_cmplt : std_logic := '0';
signal sig_rd2llink_strm_tdata : std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0);
signal sig_rd2llink_strm_tstrb : std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);
signal sig_rd2llink_strm_tlast : std_logic := '0';
signal sig_rd2llink_strm_tvalid : std_logic := '0';
signal sig_llink2rd_strm_tready : std_logic := '0';
signal sig_llink2wr_strm_tdata : std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0);
signal sig_llink2wr_strm_tstrb : std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);
signal sig_llink2wr_strm_tlast : std_logic := '0';
signal sig_llink2wr_strm_tvalid : std_logic := '0';
signal sig_llink2wr_strm_tready : std_logic := '0';
signal sig_rd_llink_enable : std_logic := '0';
signal sig_wr_llink_enable : std_logic := '0';
signal sig_md_error : std_logic := '0';
-----------------------------------------------------------------------------------------
-- IPIC Read LocalLink Channel (Little Endian bit ordering)
-----------------------------------------------------------------------------------------
-- signal sig_bus2ip_mstrd_d : std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0 ) ;-- IPIC RD LLink
-- signal sig_bus2ip_mstrd_rem : std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);-- IPIC RD LLink
-- signal sig_bus2ip_mstrd_sof_n : std_logic ;-- IPIC RD LLink
-- signal sig_bus2ip_mstrd_eof_n : std_logic ;-- IPIC RD LLink
-- signal sig_bus2ip_mstrd_src_rdy_n : std_logic ;-- IPIC RD LLink
-- signal sig_bus2ip_mstrd_src_dsc_n : std_logic ;-- IPIC RD LLink
--
-- signal sig_ip2bus_mstrd_dst_rdy_n : std_logic ;-- IPIC RD LLink
-- signal sig_ip2bus_mstrd_dst_dsc_n : std_logic ;-- IPIC RD LLink
-----------------------------------------------------------------------------------------
-- IPIC Read LocalLink Channel (Big Endian bit ordering)
-----------------------------------------------------------------------------------------
signal sig_bus2ip_mstrd_d : std_logic_vector(0 to C_NATIVE_DATA_WIDTH-1) ;-- IPIC RD LLink
signal sig_bus2ip_mstrd_rem : std_logic_vector(0 to (C_NATIVE_DATA_WIDTH/8)-1) ;-- IPIC RD LLink
signal sig_bus2ip_mstrd_sof_n : std_logic ;-- IPIC RD LLink
signal sig_bus2ip_mstrd_eof_n : std_logic ;-- IPIC RD LLink
signal sig_bus2ip_mstrd_src_rdy_n : std_logic ;-- IPIC RD LLink
signal sig_bus2ip_mstrd_src_dsc_n : std_logic ;-- IPIC RD LLink
signal sig_ip2bus_mstrd_dst_rdy_n : std_logic ;-- IPIC RD LLink
signal sig_ip2bus_mstrd_dst_dsc_n : std_logic ;-- IPIC RD LLink
-----------------------------------------------------------------------------------------
-- IPIC Write LocalLink Channel (Little Endian bit ordering)
-----------------------------------------------------------------------------------------
-- signal sig_ip2bus_mstwr_d : std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0) ;-- IPIC WR LLink
-- signal sig_ip2bus_mstwr_rem : std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);-- IPIC WR LLink
-- signal sig_ip2bus_mstwr_sof_n : std_logic ;-- IPIC WR LLink
-- signal sig_ip2bus_mstwr_eof_n : std_logic ;-- IPIC WR LLink
-- signal sig_ip2bus_mstwr_src_rdy_n : std_logic ;-- IPIC WR LLink
-- signal sig_ip2bus_mstwr_src_dsc_n : std_logic ;-- IPIC WR LLink
--
-- signal sig_bus2ip_mstwr_dst_rdy_n : std_logic ;-- IPIC WR LLink
-- signal sig_bus2ip_mstwr_dst_dsc_n : std_logic ;-- IPIC WR LLink
-----------------------------------------------------------------------------------------
-- IPIC Write LocalLink Channel (Big Endian bit ordering)
-----------------------------------------------------------------------------------------
signal sig_ip2bus_mstwr_d : std_logic_vector(0 to C_NATIVE_DATA_WIDTH-1) ;-- IPIC WR LLink
signal sig_ip2bus_mstwr_rem : std_logic_vector(0 to (C_NATIVE_DATA_WIDTH/8)-1) ;-- IPIC WR LLink
signal sig_ip2bus_mstwr_sof_n : std_logic ;-- IPIC WR LLink
signal sig_ip2bus_mstwr_eof_n : std_logic ;-- IPIC WR LLink
signal sig_ip2bus_mstwr_src_rdy_n : std_logic ;-- IPIC WR LLink
signal sig_ip2bus_mstwr_src_dsc_n : std_logic ;-- IPIC WR LLink
signal sig_bus2ip_mstwr_dst_rdy_n : std_logic ;-- IPIC WR LLink
signal sig_bus2ip_mstwr_dst_dsc_n : std_logic ;-- IPIC WR LLink
begin --(architecture implementation)
-- Master detected Error output discrete
-- md_error <= sig_md_error ;
md_error <= sig_rw_error ;
-- Assign IPIC Command Inputs
-- Note that this also changes the bit ordering
-- from Little Endian to big endian for vectors.
sig_ip2bus_mstrd_req <= ip2bus_mstrd_req ;
sig_ip2bus_mstwr_req <= ip2bus_mstwr_req ;
sig_ip2bus_mst_addr <= ip2bus_mst_addr ;
sig_ip2bus_mst_length <= ip2bus_mst_length ;
sig_ip2bus_mst_be <= ip2bus_mst_be ;
sig_ip2bus_mst_type <= ip2bus_mst_type ;
sig_ip2bus_mst_lock <= ip2bus_mst_lock ;
sig_ipic_reset <= ip2bus_mst_reset ;
-- Assign IPIC Status Outputs
bus2ip_mst_cmdack <= sig_bus2ip_mst_cmdack ;
bus2ip_mst_cmplt <= sig_bus2ip_mst_cmplt ;
bus2ip_mst_error <= sig_bus2ip_mst_error ;
bus2ip_mst_rearbitrate <= sig_bus2ip_mst_rearbitrate ;
bus2ip_mst_cmd_timeout <= sig_bus2ip_mst_cmd_timeout ;
-- Assign Read LocalLink Ports
-- Note that this also changes the bit ordering
-- from Little Endian to big endian for vectors.
bus2ip_mstrd_d <= sig_bus2ip_mstrd_d ;
bus2ip_mstrd_rem <= sig_bus2ip_mstrd_rem ;
bus2ip_mstrd_sof_n <= sig_bus2ip_mstrd_sof_n ;
bus2ip_mstrd_eof_n <= sig_bus2ip_mstrd_eof_n ;
bus2ip_mstrd_src_rdy_n <= sig_bus2ip_mstrd_src_rdy_n ;
bus2ip_mstrd_src_dsc_n <= sig_bus2ip_mstrd_src_dsc_n ;
sig_ip2bus_mstrd_dst_rdy_n <= ip2bus_mstrd_dst_rdy_n ;
sig_ip2bus_mstrd_dst_dsc_n <= ip2bus_mstrd_dst_dsc_n ;
-- Assign Write LocalLink Ports
-- Note that this also changes the bit ordering
-- from Little Endian to big endian for vectors.
sig_ip2bus_mstwr_d <= ip2bus_mstwr_d ;
sig_ip2bus_mstwr_rem <= ip2bus_mstwr_rem ;
sig_ip2bus_mstwr_sof_n <= ip2bus_mstwr_sof_n ;
sig_ip2bus_mstwr_eof_n <= ip2bus_mstwr_eof_n ;
sig_ip2bus_mstwr_src_rdy_n <= ip2bus_mstwr_src_rdy_n ;
sig_ip2bus_mstwr_src_dsc_n <= ip2bus_mstwr_src_dsc_n ;
bus2ip_mstwr_dst_rdy_n <= sig_bus2ip_mstwr_dst_rdy_n ;
bus2ip_mstwr_dst_dsc_n <= sig_bus2ip_mstwr_dst_dsc_n ;
------------------------------------------------------------
-- Instance: I_RESET_MODULE
--
-- Description:
-- Reset Module instance.
--
------------------------------------------------------------
I_RESET_MODULE : entity axi_master_burst_v2_0.axi_master_burst_reset
port map (
-- Clock Input
axi_aclk => m_axi_aclk ,
-- Reset Input (active low)
axi_aresetn => m_axi_aresetn ,
-- IPIC Reset Input
ip2bus_mst_reset => sig_ipic_reset ,
-- HW Reset to internal reset groups --------------------------
rst2cmd_reset_out => sig_rst2cmd_stat_reset ,
rst2rdwr_reset_out => sig_rst2rdwr_cntlr_reset ,
rst2llink_reset_out => sig_rst2llink_reset
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS_MODULE
--
-- Description:
-- Instance of the Command and Status Module
--
------------------------------------------------------------
I_CMD_STATUS_MODULE : entity axi_master_burst_v2_0.axi_master_burst_cmd_status
generic map (
C_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_NATIVE_DWIDTH => C_NATIVE_DATA_WIDTH,
C_CMD_WIDTH => PCC_CMD_WIDTH ,
C_CMD_BTT_USED_WIDTH => LENGTH_WIDTH ,
C_STS_WIDTH => STATUS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock inputs
axi_aclk => m_axi_aclk ,
-- Reset inputs
axi_reset => sig_rst2cmd_stat_reset ,
-- RW_ERROR Output Discrete
rw_error => sig_rw_error ,
-- Internal error Output Discrete to LocalLink backends
-- (Asserted until Pertinent LocalLink IF is not busy)
rdwr2llink_int_err => sig_rdwr2llink_int_err ,
-- IPIC Request/Qualifiers
ip2bus_mstrd_req => sig_ip2bus_mstrd_req ,
ip2bus_mstwr_req => sig_ip2bus_mstwr_req ,
ip2bus_mst_addr => sig_ip2bus_mst_addr ,
ip2bus_mst_length => sig_ip2bus_mst_length ,
ip2bus_mst_be => sig_ip2bus_mst_be ,
ip2bus_mst_type => sig_ip2bus_mst_type ,
ip2bus_mst_lock => sig_ip2bus_mst_lock ,
ip2bus_mst_reset => LOGIC_LOW ,
-- IPIC Request Status Reply
bus2ip_mst_cmdack => sig_bus2ip_mst_cmdack ,
bus2ip_mst_cmplt => sig_bus2ip_mst_cmplt ,
bus2ip_mst_error => sig_bus2ip_mst_error ,
bus2ip_mst_rearbitrate => sig_bus2ip_mst_rearbitrate ,
bus2ip_mst_cmd_timeout => sig_bus2ip_mst_cmd_timeout ,
-- IPIC LocalLink Busy Flag
mstrd_llink_busy => sig_llink2cmd_rd_busy ,
mstwr_llink_busy => sig_llink2cmd_wr_busy ,
-- PCC Command Interface
pcc2cmd_cmd_ready => sig_pcc2cmd_cmd_ready ,
cmd2pcc_cmd_valid => sig_cmd2pcc_cmd_valid ,
cmd2pcc_command => sig_cmd2pcc_command ,
-- Read/Write Command Indicator Interface
cmd2all_doing_read => sig_cmd2all_doing_read ,
cmd2all_doing_write => sig_cmd2all_doing_write ,
-- Read Status Controller Interface
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2stat_status => sig_rsc2stat_status ,
-- Write Status Controller Interface
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2stat_status => sig_wsc2stat_status
);
------------------------------------------------------------
-- Instance: I_RD_WR_CNTRL_MODULE
--
-- Description:
-- Instance of the Read and Write Controller Module
--
------------------------------------------------------------
I_RD_WR_CNTRL_MODULE : entity axi_master_burst_v2_0.axi_master_burst_rd_wr_cntlr
generic map (
C_RDWR_ID_WIDTH => RDWR_ID_WIDTH ,
C_RDWR_ARID => RDWR_ID ,
C_RDWR_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_RDWR_MDATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_RDWR_SDATA_WIDTH => C_NATIVE_DATA_WIDTH ,
C_RDWR_MAX_BURST_LEN => RDWR_MAX_BURST_LEN ,
C_RDWR_BTT_USED => RDWR_BTT_USED ,
C_RDWR_ADDR_PIPE_DEPTH => RDWR_ADDR_PIPE_DEPTH ,
C_RDWR_PCC_CMD_WIDTH => PCC_CMD_WIDTH ,
C_RDWR_STATUS_WIDTH => STATUS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- RDWR Primary Clock input
rdwr_aclk => m_axi_aclk ,
-- RDWR Primary Reset input
rdwr_areset => sig_rst2rdwr_cntlr_reset ,
-- RDWR Master detected Error Output Discrete
rdwr_md_error => sig_md_error ,
-- Command/Status Module PCC Command Interface (AXI Stream Like)
cmd2rdwr_cmd_valid => sig_cmd2pcc_cmd_valid ,
rdwr2cmd_cmd_ready => sig_pcc2cmd_cmd_ready ,
cmd2rdwr_cmd_data => sig_cmd2pcc_command ,
-- Command/Status Module Type Interface
cmd2rdwr_doing_read => sig_cmd2all_doing_read ,
cmd2rdwr_doing_write => sig_cmd2all_doing_write ,
-- Command/Status Module Read Status Ports (AXI Stream Like)
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2stat_status => sig_rsc2stat_status ,
-- Command/Status Module Write Status Ports (AXI Stream Like)
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2stat_status => sig_wsc2stat_status ,
-- Read Address Posting Contols/Status
rd_allow_addr_req => sig_llink2rd_allow_addr_req ,
rd_addr_req_posted => sig_rd2llink_addr_req_posted ,
rd_xfer_cmplt => sig_rd2llink_xfer_cmplt ,
-- Write Address Posting Contols/Status
wr_allow_addr_req => sig_llink2wr_allow_addr_req ,
wr_addr_req_posted => sig_wr2llink_addr_req_posted ,
wr_xfer_cmplt => sig_wr2llink_xfer_cmplt ,
-- LocalLink Enable Outputs (1 clock pulse)
rd_llink_enable => sig_rd_llink_enable ,
wr_llink_enable => sig_wr_llink_enable ,
-- AXI Read Address Channel I/O
rd_arid => open ,
rd_araddr => m_axi_araddr ,
rd_arlen => m_axi_arlen ,
rd_arsize => m_axi_arsize ,
rd_arburst => m_axi_arburst ,
rd_arprot => m_axi_arprot ,
rd_arcache => m_axi_arcache ,
rd_arvalid => m_axi_arvalid ,
rd_arready => m_axi_arready ,
-- AXI Read Data Channel I/O
rd_rdata => m_axi_rdata ,
rd_rresp => m_axi_rresp ,
rd_rlast => m_axi_rlast ,
rd_rvalid => m_axi_rvalid ,
rd_rready => m_axi_rready ,
-- AXI Read Master Stream Channel I/O
rd_strm_tdata => sig_rd2llink_strm_tdata ,
rd_strm_tstrb => sig_rd2llink_strm_tstrb ,
rd_strm_tlast => sig_rd2llink_strm_tlast ,
rd_strm_tvalid => sig_rd2llink_strm_tvalid ,
rd_strm_tready => sig_llink2rd_strm_tready ,
-- AXI Write Address Channel I/O
wr_awid => open ,
wr_awaddr => m_axi_awaddr ,
wr_awlen => m_axi_awlen ,
wr_awsize => m_axi_awsize ,
wr_awburst => m_axi_awburst ,
wr_awprot => m_axi_awprot ,
wr_awcache => m_axi_awcache ,
wr_awvalid => m_axi_awvalid ,
wr_awready => m_axi_awready ,
-- RDWR AXI Write Data Channel I/O
wr_wdata => m_axi_wdata ,
wr_wstrb => m_axi_wstrb ,
wr_wlast => m_axi_wlast ,
wr_wvalid => m_axi_wvalid ,
wr_wready => m_axi_wready ,
-- RDWR AXI Write response Channel I/O
wr_bresp => m_axi_bresp ,
wr_bvalid => m_axi_bvalid ,
wr_bready => m_axi_bready ,
-- RDWR AXI Slave Stream Channel I/O
wr_strm_tdata => sig_llink2wr_strm_tdata ,
wr_strm_tstrb => sig_llink2wr_strm_tstrb ,
wr_strm_tlast => sig_llink2wr_strm_tlast ,
wr_strm_tvalid => sig_llink2wr_strm_tvalid ,
wr_strm_tready => sig_llink2wr_strm_tready
);
------------------------------------------------------------
-- Instance: I_RD_LLINK_ADAPTER
--
-- Description:
-- Instance for the Read AXI Stream to Read LocalLink Adapter
--
------------------------------------------------------------
I_RD_LLINK_ADAPTER : entity axi_master_burst_v2_0.axi_master_burst_rd_llink
generic map (
C_NATIVE_DWIDTH => C_NATIVE_DATA_WIDTH
)
port map (
-- Read LocalLink Clock input
rdllink_aclk => m_axi_aclk ,
-- Read LocalLink Reset input
rdllink_areset => sig_rst2llink_reset ,
-- Read Cntlr Internal Error Indication
rdllink_rd_error => sig_rdwr2llink_int_err ,
-- LocalLink Enable Control (1 Clock wide pulse)
rdllink_llink_enable => sig_rd_llink_enable ,
-- IPIC LocalLink Busy Flag
rdllink_llink_busy => sig_llink2cmd_rd_busy ,
-- Read Address Posting Contols/Status
rdllink_allow_addr_req => sig_llink2rd_allow_addr_req ,
rdllink_addr_req_posted => sig_rd2llink_addr_req_posted ,
rdllink_xfer_cmplt => sig_rd2llink_xfer_cmplt ,
-- Read AXI Slave Master Channel
rdllink_strm_tdata => sig_rd2llink_strm_tdata ,
rdllink_strm_tstrb => sig_rd2llink_strm_tstrb ,
rdllink_strm_tlast => sig_rd2llink_strm_tlast ,
rdllink_strm_tvalid => sig_rd2llink_strm_tvalid ,
rdllink_strm_tready => sig_llink2rd_strm_tready ,
-- IPIC Read LocalLink Channel
bus2ip_mstrd_d => sig_bus2ip_mstrd_d ,
bus2ip_mstrd_rem => sig_bus2ip_mstrd_rem ,
bus2ip_mstrd_sof_n => sig_bus2ip_mstrd_sof_n ,
bus2ip_mstrd_eof_n => sig_bus2ip_mstrd_eof_n ,
bus2ip_mstrd_src_rdy_n => sig_bus2ip_mstrd_src_rdy_n ,
bus2ip_mstrd_src_dsc_n => sig_bus2ip_mstrd_src_dsc_n ,
ip2bus_mstrd_dst_rdy_n => sig_ip2bus_mstrd_dst_rdy_n ,
ip2bus_mstrd_dst_dsc_n => sig_ip2bus_mstrd_dst_dsc_n
);
------------------------------------------------------------
-- Instance: I_WR_LLINK_ADAPTER
--
-- Description:
-- Instance for the Write LocalLink to AXI Stream Adapter
--
------------------------------------------------------------
I_WR_LLINK_ADAPTER : entity axi_master_burst_v2_0.axi_master_burst_wr_llink
generic map (
C_NATIVE_DWIDTH => C_NATIVE_DATA_WIDTH
)
port map (
-- Write LocalLink Clock input
wrllink_aclk => m_axi_aclk ,
-- Write LocalLink Reset input
wrllink_areset => sig_rst2llink_reset ,
-- RDWR Cntlr Internal Error Indication
wrllink_wr_error => sig_rdwr2llink_int_err ,
-- LocalLink Enable Control (1 Clock wide pulse)
wrllink_llink_enable => sig_wr_llink_enable ,
-- IPIC LocalLink Busy Flag
wrllink_llink_busy => sig_llink2cmd_wr_busy ,
-- Write Address Posting Contols/Status
wrllink_allow_addr_req => sig_llink2wr_allow_addr_req ,
wrllink_addr_req_posted => sig_wr2llink_addr_req_posted ,
wrllink_xfer_cmplt => sig_wr2llink_xfer_cmplt ,
-- Write AXI Slave Master Channel
wrllink_strm_tdata => sig_llink2wr_strm_tdata ,
wrllink_strm_tstrb => sig_llink2wr_strm_tstrb ,
wrllink_strm_tlast => sig_llink2wr_strm_tlast ,
wrllink_strm_tvalid => sig_llink2wr_strm_tvalid ,
wrllink_strm_tready => sig_llink2wr_strm_tready ,
-- IPIC Write LocalLink Channel
ip2bus_mstwr_d => sig_ip2bus_mstwr_d ,
ip2bus_mstwr_rem => sig_ip2bus_mstwr_rem ,
ip2bus_mstwr_sof_n => sig_ip2bus_mstwr_sof_n ,
ip2bus_mstwr_eof_n => sig_ip2bus_mstwr_eof_n ,
ip2bus_mstwr_src_rdy_n => sig_ip2bus_mstwr_src_rdy_n ,
ip2bus_mstwr_src_dsc_n => sig_ip2bus_mstwr_src_dsc_n ,
bus2ip_mstwr_dst_rdy_n => sig_bus2ip_mstwr_dst_rdy_n ,
bus2ip_mstwr_dst_dsc_n => sig_bus2ip_mstwr_dst_dsc_n
);
end implementation;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_06a is
end entity inline_06a;
architecture test of inline_06a is
-- code from book
terminal a_bus : electrical_vector(1 to 8);
terminal b_bus : electrical_vector(8 downto 1);
--
quantity a_to_b_drops across a_to_b_currents through a_bus to b_bus;
--
nature electrical_bus is
record
strobe: electrical;
databus : electrical_vector(0 to 7);
end record;
terminal t1, t2 : electrical_bus;
--
quantity bus_voltages across t1 to t2;
--
terminal p1, p2 : electrical_vector(0 to 3);
quantity v across i through p1 to p2;
-- end code from book
begin
block_1 : block is
terminal anode, cathode : electrical;
-- code from book
quantity battery_voltage tolerance "battery_tolerance" across
battery_current tolerance "battery_tolerance" through anode to cathode;
-- end code from book
begin
end block block_1;
block_2 : block is
terminal anode, cathode : electrical;
-- code from book
quantity battery_volts := 5.0 across
battery_amps := 0.0 through
anode to cathode;
-- end code from book
begin
end block block_2;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_06a is
end entity inline_06a;
architecture test of inline_06a is
-- code from book
terminal a_bus : electrical_vector(1 to 8);
terminal b_bus : electrical_vector(8 downto 1);
--
quantity a_to_b_drops across a_to_b_currents through a_bus to b_bus;
--
nature electrical_bus is
record
strobe: electrical;
databus : electrical_vector(0 to 7);
end record;
terminal t1, t2 : electrical_bus;
--
quantity bus_voltages across t1 to t2;
--
terminal p1, p2 : electrical_vector(0 to 3);
quantity v across i through p1 to p2;
-- end code from book
begin
block_1 : block is
terminal anode, cathode : electrical;
-- code from book
quantity battery_voltage tolerance "battery_tolerance" across
battery_current tolerance "battery_tolerance" through anode to cathode;
-- end code from book
begin
end block block_1;
block_2 : block is
terminal anode, cathode : electrical;
-- code from book
quantity battery_volts := 5.0 across
battery_amps := 0.0 through
anode to cathode;
-- end code from book
begin
end block block_2;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_06a is
end entity inline_06a;
architecture test of inline_06a is
-- code from book
terminal a_bus : electrical_vector(1 to 8);
terminal b_bus : electrical_vector(8 downto 1);
--
quantity a_to_b_drops across a_to_b_currents through a_bus to b_bus;
--
nature electrical_bus is
record
strobe: electrical;
databus : electrical_vector(0 to 7);
end record;
terminal t1, t2 : electrical_bus;
--
quantity bus_voltages across t1 to t2;
--
terminal p1, p2 : electrical_vector(0 to 3);
quantity v across i through p1 to p2;
-- end code from book
begin
block_1 : block is
terminal anode, cathode : electrical;
-- code from book
quantity battery_voltage tolerance "battery_tolerance" across
battery_current tolerance "battery_tolerance" through anode to cathode;
-- end code from book
begin
end block block_1;
block_2 : block is
terminal anode, cathode : electrical;
-- code from book
quantity battery_volts := 5.0 across
battery_amps := 0.0 through
anode to cathode;
-- end code from book
begin
end block block_2;
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity shift_reg is
generic
(
width : integer := 4
);
port
(
input : in std_logic_vector((width - 1) downto 0);
control : in std_logic_vector(1 downto 0);
clear : in std_logic;
clock : in std_logic;
output : out std_logic_vector((width - 1) downto 0)
);
end shift_reg;
architecture behavior of shift_reg is
begin
P0 : process (clock, control, clear, input)
variable out_var : std_logic_vector((width - 1) downto 0);
variable Interim_Val : std_logic_vector((width - 1) downto 0);
begin
for I in width - 1 downto 0 loop
out_var(I) := '0';
end loop;
if (clear = '1') then
output <= out_var;
Interim_Val := out_var;
elsif (clock = '1' and not clock'STABLE and control = "01") then
output <= input;
end if;
if (clock = '1' and not clock'STABLE and control = "10") then
for I in 0 to width - 2 loop
Interim_Val(i) := Interim_Val(i + 1);
end loop;
Interim_Val(width - 1) := '0';
output <= Interim_Val;
end if;
if (clock = '1' and not clock'STABLE and control = "11") then
for I in width - 1 downto 1 loop
Interim_Val(i) := Interim_Val(i - 1);
end loop;
Interim_Val(0) := '0';
output <= Interim_Val;
end if;
end process P0;
end behavior; |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
-- Inspired by similar functionality in SystemVerilog and OSVVM.
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
use work.string_methods_pkg.all;
use work.global_signals_and_shared_variables_pkg.all;
use work.methods_pkg.all;
use work.rand_pkg.all;
package func_cov_pkg is
constant C_MAX_NUM_CROSS_BINS : positive := 16;
------------------------------------------------------------
-- Types
------------------------------------------------------------
type t_report_verbosity is (NON_VERBOSE, VERBOSE, HOLES_ONLY);
type t_rand_weight_visibility is (SHOW_RAND_WEIGHT, HIDE_RAND_WEIGHT);
type t_coverage_type is (BINS, HITS, BINS_AND_HITS);
type t_overall_coverage_type is (COVPTS, BINS, HITS);
type t_rand_sample_cov is (SAMPLE_COV, NO_SAMPLE_COV);
type t_cov_bin_type is (VAL, VAL_IGNORE, VAL_ILLEGAL, RAN, RAN_IGNORE, RAN_ILLEGAL, TRN, TRN_IGNORE, TRN_ILLEGAL);
type t_new_bin is record
contains : t_cov_bin_type;
values : integer_vector(0 to C_FC_MAX_NUM_BIN_VALUES-1);
num_values : natural range 0 to C_FC_MAX_NUM_BIN_VALUES;
end record;
type t_new_bin_vector is array (natural range <>) of t_new_bin;
type t_new_cov_bin is record
bin_vector : t_new_bin_vector(0 to C_FC_MAX_NUM_NEW_BINS-1);
num_bins : natural range 0 to C_FC_MAX_NUM_NEW_BINS;
proc_call : string(1 to C_FC_MAX_PROC_CALL_LENGTH);
end record;
type t_new_bin_array is array (natural range <>) of t_new_cov_bin;
constant C_EMPTY_NEW_BIN_ARRAY : t_new_bin_array(0 to 0) := (0 => ((0 to C_FC_MAX_NUM_NEW_BINS-1 => (VAL, (others => 0), 0)),
0,
(1 to C_FC_MAX_PROC_CALL_LENGTH => NUL)));
type t_bin is record
contains : t_cov_bin_type;
values : integer_vector(0 to C_FC_MAX_NUM_BIN_VALUES-1);
num_values : natural range 0 to C_FC_MAX_NUM_BIN_VALUES;
end record;
type t_bin_vector is array (natural range <>) of t_bin;
type t_cov_bin is record
cross_bins : t_bin_vector(0 to C_MAX_NUM_CROSS_BINS-1);
hits : natural;
min_hits : natural;
rand_weight : integer;
transition_mask : std_logic_vector(C_FC_MAX_NUM_BIN_VALUES-1 downto 0);
name : string(1 to C_FC_MAX_NAME_LENGTH);
end record;
type t_cov_bin_vector is array (natural range <>) of t_cov_bin;
type t_cov_bin_vector_ptr is access t_cov_bin_vector;
------------------------------------------------------------
-- Bin functions
------------------------------------------------------------
-- Creates a bin for a single value
impure function bin(
constant value : integer)
return t_new_bin_array;
-- Creates a bin for multiple values
impure function bin(
constant set_of_values : integer_vector)
return t_new_bin_array;
-- Creates a bin for a range of values. Several bins can be created by dividing the range into num_bins.
-- If num_bins is 0 then a bin is created for each value.
impure function bin_range(
constant min_value : integer;
constant max_value : integer;
constant num_bins : natural := 1)
return t_new_bin_array;
-- Creates a bin for a vector's range. Several bins can be created by dividing the range into num_bins.
-- If num_bins is 0 then a bin is created for each value.
impure function bin_vector(
constant vector : std_logic_vector;
constant num_bins : natural := 1)
return t_new_bin_array;
-- Creates a bin for a transition of values
impure function bin_transition(
constant set_of_values : integer_vector)
return t_new_bin_array;
-- Creates an ignore bin for a single value
impure function ignore_bin(
constant value : integer)
return t_new_bin_array;
-- Creates an ignore bin for a range of values
impure function ignore_bin_range(
constant min_value : integer;
constant max_value : integer)
return t_new_bin_array;
-- Creates an ignore bin for a transition of values
impure function ignore_bin_transition(
constant set_of_values : integer_vector)
return t_new_bin_array;
-- Creates an illegal bin for a single value
impure function illegal_bin(
constant value : integer)
return t_new_bin_array;
-- Creates an illegal bin for a range of values
impure function illegal_bin_range(
constant min_value : integer;
constant max_value : integer)
return t_new_bin_array;
-- Creates an illegal bin for a transition of values
impure function illegal_bin_transition(
constant set_of_values : integer_vector)
return t_new_bin_array;
------------------------------------------------------------
-- Overall coverage
------------------------------------------------------------
procedure fc_set_covpts_coverage_goal(
constant percentage : in positive range 1 to 100;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
impure function fc_get_covpts_coverage_goal(
constant VOID : t_void)
return positive;
impure function fc_get_overall_coverage(
constant coverage_type : t_overall_coverage_type)
return real;
impure function fc_overall_coverage_completed(
constant VOID : t_void)
return boolean;
procedure fc_report_overall_coverage(
constant VOID : in t_void);
procedure fc_report_overall_coverage(
constant verbosity : in t_report_verbosity;
constant file_name : in string := "";
constant open_mode : in file_open_kind := append_mode;
constant scope : in string := C_TB_SCOPE_DEFAULT);
------------------------------------------------------------
-- Protected type
------------------------------------------------------------
type t_coverpoint is protected
------------------------------------------------------------
-- Configuration
------------------------------------------------------------
procedure set_name(
constant name : in string);
impure function get_name(
constant VOID : t_void)
return string;
procedure set_scope(
constant scope : in string);
impure function get_scope(
constant VOID : t_void)
return string;
procedure set_overall_coverage_weight(
constant weight : in natural;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
impure function get_overall_coverage_weight(
constant VOID : t_void)
return natural;
procedure set_bins_coverage_goal(
constant percentage : in positive range 1 to 100;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
impure function get_bins_coverage_goal(
constant VOID : t_void)
return positive;
procedure set_hits_coverage_goal(
constant percentage : in positive;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
impure function get_hits_coverage_goal(
constant VOID : t_void)
return positive;
procedure set_illegal_bin_alert_level(
constant alert_level : in t_alert_level;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
impure function get_illegal_bin_alert_level(
constant VOID : t_void)
return t_alert_level;
procedure set_bin_overlap_alert_level(
constant alert_level : in t_alert_level;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
impure function get_bin_overlap_alert_level(
constant VOID : t_void)
return t_alert_level;
procedure write_coverage_db(
constant file_name : in string;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure load_coverage_db(
constant file_name : in string;
constant report_verbosity : in t_report_verbosity := HOLES_ONLY;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure clear_coverage(
constant VOID : in t_void);
procedure clear_coverage(
constant msg_id_panel : in t_msg_id_panel);
procedure set_num_allocated_bins(
constant value : in positive;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure set_num_allocated_bins_increment(
constant value : in positive);
procedure delete_coverpoint(
constant VOID : in t_void);
procedure delete_coverpoint(
constant msg_id_panel : in t_msg_id_panel);
-- Returns the number of bins crossed in the coverpoint
impure function get_num_bins_crossed(
constant VOID : t_void)
return integer;
-- Returns the number of valid bins in the coverpoint
impure function get_num_valid_bins(
constant VOID : t_void)
return natural;
-- Returns the number of illegal and ignore bins in the coverpoint
impure function get_num_invalid_bins(
constant VOID : t_void)
return natural;
-- Returns a valid bin in the coverpoint
impure function get_valid_bin(
constant bin_idx : natural)
return t_cov_bin;
-- Returns an invalid bin in the coverpoint
impure function get_invalid_bin(
constant bin_idx : natural)
return t_cov_bin;
-- Returns a vector with the valid bins in the coverpoint
impure function get_valid_bins(
constant VOID : t_void)
return t_cov_bin_vector;
-- Returns a vector with the illegal and ignore bins in the coverpoint
impure function get_invalid_bins(
constant VOID : t_void)
return t_cov_bin_vector;
-- Returns a string with all the bins, including illegal and ignore, in the coverpoint
impure function get_all_bins_string(
constant VOID : t_void)
return string;
------------------------------------------------------------
-- Add bins
------------------------------------------------------------
procedure add_bins(
constant bin : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
procedure add_bins(
constant bin : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure add_bins(
constant bin : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
------------------------------------------------------------
-- Add cross (2 bins)
------------------------------------------------------------
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
------------------------------------------------------------
-- Add cross (3 bins)
------------------------------------------------------------
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
------------------------------------------------------------
-- Add cross (4 bins)
------------------------------------------------------------
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
------------------------------------------------------------
-- Add cross (5 bins)
------------------------------------------------------------
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant bin5 : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant bin5 : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant bin5 : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
-- TODO: max 16 dimensions
------------------------------------------------------------
-- Add cross (2 coverpoints)
------------------------------------------------------------
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
------------------------------------------------------------
-- Add cross (3 coverpoints)
------------------------------------------------------------
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
------------------------------------------------------------
-- Add cross (4 coverpoints)
------------------------------------------------------------
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
------------------------------------------------------------
-- Add cross (5 coverpoints)
------------------------------------------------------------
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
variable coverpoint5 : inout t_coverpoint;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
variable coverpoint5 : inout t_coverpoint;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
variable coverpoint5 : inout t_coverpoint;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
------------------------------------------------------------
-- Coverage
------------------------------------------------------------
impure function is_defined(
constant VOID : t_void)
return boolean;
procedure sample_coverage(
constant value : in integer;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure sample_coverage(
constant values : in integer_vector;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
impure function get_coverage(
constant coverage_type : t_coverage_type;
constant percentage_of_goal : boolean := false)
return real;
impure function coverage_completed(
constant coverage_type : t_coverage_type)
return boolean;
procedure report_coverage(
constant VOID : in t_void);
procedure report_coverage(
constant verbosity : in t_report_verbosity;
constant file_name : in string := "";
constant open_mode : in file_open_kind := append_mode;
constant rand_weight_col : in t_rand_weight_visibility := HIDE_RAND_WEIGHT);
procedure report_config(
constant VOID : in t_void);
procedure report_config(
constant file_name : in string;
constant open_mode : in file_open_kind := append_mode);
------------------------------------------------------------
-- Optimized Randomization
------------------------------------------------------------
impure function rand(
constant sampling : t_rand_sample_cov;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel)
return integer;
impure function rand(
constant sampling : t_rand_sample_cov;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : string := "")
return integer_vector;
procedure set_rand_seeds(
constant seed1 : in positive;
constant seed2 : in positive);
procedure set_rand_seeds(
constant seeds : in t_positive_vector(0 to 1));
procedure get_rand_seeds(
variable seed1 : out positive;
variable seed2 : out positive);
impure function get_rand_seeds(
constant VOID : t_void)
return t_positive_vector;
end protected t_coverpoint;
end package func_cov_pkg;
package body func_cov_pkg is
-- Generates the correct procedure call to be used for logging or alerts
procedure create_proc_call(
constant proc_call : in string;
constant ext_proc_call : in string;
variable new_proc_call : inout line) is
begin
-- Called directly from sequencer/VVC
if ext_proc_call = "" then
write(new_proc_call, proc_call);
-- Called from another procedure
else
write(new_proc_call, ext_proc_call);
end if;
end procedure;
-- Creates a bin with a single value
impure function create_bin_single(
constant contains : t_cov_bin_type;
constant value : integer;
constant proc_call : string)
return t_new_bin_array is
variable v_ret : t_new_bin_array(0 to 0);
begin
v_ret(0).bin_vector(0).contains := contains;
v_ret(0).bin_vector(0).values(0) := value;
v_ret(0).bin_vector(0).num_values := 1;
v_ret(0).num_bins := 1;
if proc_call'length > C_FC_MAX_PROC_CALL_LENGTH then
v_ret(0).proc_call := proc_call(1 to C_FC_MAX_PROC_CALL_LENGTH-3) & "...";
else
v_ret(0).proc_call(1 to proc_call'length) := proc_call;
end if;
return v_ret;
end function;
-- Creates a bin with multiple values
impure function create_bin_multiple(
constant contains : t_cov_bin_type;
constant set_of_values : integer_vector;
constant proc_call : string)
return t_new_bin_array is
variable v_ret : t_new_bin_array(0 to 0);
begin
v_ret(0).bin_vector(0).contains := contains;
if set_of_values'length <= C_FC_MAX_NUM_BIN_VALUES then
v_ret(0).bin_vector(0).values(0 to set_of_values'length-1) := set_of_values;
v_ret(0).bin_vector(0).num_values := set_of_values'length;
else
v_ret(0).bin_vector(0).values := set_of_values(0 to C_FC_MAX_NUM_BIN_VALUES-1);
v_ret(0).bin_vector(0).num_values := C_FC_MAX_NUM_BIN_VALUES;
alert(TB_WARNING, proc_call & "=> Number of values (" & to_string(set_of_values'length) &
") exceeds C_FC_MAX_NUM_BIN_VALUES.\n Increase C_FC_MAX_NUM_BIN_VALUES in adaptations package.", C_TB_SCOPE_DEFAULT);
end if;
v_ret(0).num_bins := 1;
if proc_call'length > C_FC_MAX_PROC_CALL_LENGTH then
v_ret(0).proc_call := proc_call(1 to C_FC_MAX_PROC_CALL_LENGTH-3) & "...";
else
v_ret(0).proc_call(1 to proc_call'length) := proc_call;
end if;
return v_ret;
end function;
-- Creates a bin or bins from a range of values. If num_bins is 0 then a bin is created for each value.
impure function create_bin_range(
constant contains : t_cov_bin_type;
constant min_value : integer;
constant max_value : integer;
constant num_bins : natural;
constant proc_call : string)
return t_new_bin_array is
constant C_RANGE_WIDTH : integer := abs(max_value - min_value) + 1;
variable v_div_range : integer;
variable v_div_residue : integer := 0;
variable v_div_residue_min : integer := 0;
variable v_div_residue_max : integer := 0;
variable v_num_bins : integer := 0;
variable v_ret : t_new_bin_array(0 to 0);
begin
check_value(contains = RAN or contains = RAN_IGNORE or contains = RAN_ILLEGAL, TB_FAILURE, "This function should only be used with range types.",
C_TB_SCOPE_DEFAULT, ID_NEVER, caller_name => "create_bin_range()");
if min_value <= max_value then
-- Create a bin for each value in the range (when num_bins is not defined or range is smaller than the number of bins)
if num_bins = 0 or C_RANGE_WIDTH <= num_bins then
if C_RANGE_WIDTH > C_FC_MAX_NUM_NEW_BINS then
alert(TB_ERROR, proc_call & "=> Failed. Number of bins (" & to_string(C_RANGE_WIDTH) &
") added in a single procedure call exceeds C_FC_MAX_NUM_NEW_BINS.\n Increase C_FC_MAX_NUM_NEW_BINS in adaptations package.", C_TB_SCOPE_DEFAULT);
return C_EMPTY_NEW_BIN_ARRAY;
end if;
for i in min_value to max_value loop
v_ret(0).bin_vector(i-min_value).contains := VAL when contains = RAN else
VAL_IGNORE when contains = RAN_IGNORE else
VAL_ILLEGAL when contains = RAN_ILLEGAL;
v_ret(0).bin_vector(i-min_value).values(0) := i;
v_ret(0).bin_vector(i-min_value).num_values := 1;
end loop;
v_num_bins := C_RANGE_WIDTH;
-- Create several bins by diving the range
else
if num_bins > C_FC_MAX_NUM_NEW_BINS then
alert(TB_ERROR, proc_call & "=> Failed. Number of bins (" & to_string(num_bins) &
") added in a single procedure call exceeds C_FC_MAX_NUM_NEW_BINS.\n Increase C_FC_MAX_NUM_NEW_BINS in adaptations package.", C_TB_SCOPE_DEFAULT);
return C_EMPTY_NEW_BIN_ARRAY;
end if;
v_div_residue := C_RANGE_WIDTH mod num_bins;
v_div_range := C_RANGE_WIDTH / num_bins;
v_num_bins := num_bins;
for i in 0 to v_num_bins-1 loop
-- Add the residue values to the last bins
if v_div_residue /= 0 and i = v_num_bins-v_div_residue then
v_div_residue_max := v_div_residue_max + 1;
elsif v_div_residue /= 0 and i > v_num_bins-v_div_residue then
v_div_residue_min := v_div_residue_min + 1;
v_div_residue_max := v_div_residue_max + 1;
end if;
v_ret(0).bin_vector(i).contains := contains;
v_ret(0).bin_vector(i).values(0) := min_value + v_div_range*i + v_div_residue_min;
v_ret(0).bin_vector(i).values(1) := min_value + v_div_range*(i+1)-1 + v_div_residue_max;
v_ret(0).bin_vector(i).num_values := 2;
end loop;
end if;
v_ret(0).num_bins := v_num_bins;
if proc_call'length > C_FC_MAX_PROC_CALL_LENGTH then
v_ret(0).proc_call := proc_call(1 to C_FC_MAX_PROC_CALL_LENGTH-3) & "...";
else
v_ret(0).proc_call(1 to proc_call'length) := proc_call;
end if;
else
alert(TB_ERROR, proc_call & "=> Failed. min_value must be less or equal than max_value", C_TB_SCOPE_DEFAULT);
return C_EMPTY_NEW_BIN_ARRAY;
end if;
return v_ret;
end function;
------------------------------------------------------------
-- Bin functions
------------------------------------------------------------
-- Creates a bin for a single value
impure function bin(
constant value : integer)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "bin(" & to_string(value) & ")";
begin
return create_bin_single(VAL, value, C_LOCAL_CALL);
end function;
-- Creates a bin for multiple values
impure function bin(
constant set_of_values : integer_vector)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "bin(" & to_string(set_of_values) & ")";
begin
return create_bin_multiple(VAL, set_of_values, C_LOCAL_CALL);
end function;
-- Creates a bin for a range of values. Several bins can be created by dividing the range into num_bins.
-- If num_bins is 0 then a bin is created for each value.
impure function bin_range(
constant min_value : integer;
constant max_value : integer;
constant num_bins : natural := 1)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "bin_range(" & to_string(min_value) & ", " & to_string(max_value) &
return_string_if_true(", num_bins:" & to_string(num_bins), num_bins /= 1) & ")";
begin
return create_bin_range(RAN, min_value, max_value, num_bins, C_LOCAL_CALL);
end function;
-- Creates a bin for a vector's range. Several bins can be created by dividing the range into num_bins.
-- If num_bins is 0 then a bin is created for each value.
impure function bin_vector(
constant vector : std_logic_vector;
constant num_bins : natural := 1)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "bin_vector(LEN:" & to_string(vector'length) & return_string_if_true(", num_bins:" &
to_string(num_bins), num_bins /= 1) & ")";
begin
return create_bin_range(RAN, 0, 2**vector'length-1, num_bins, C_LOCAL_CALL);
end function;
-- Creates a bin for a transition of values
impure function bin_transition(
constant set_of_values : integer_vector)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "bin_transition(" & to_string(set_of_values) & ")";
begin
return create_bin_multiple(TRN, set_of_values, C_LOCAL_CALL);
end function;
-- Creates an ignore bin for a single value
impure function ignore_bin(
constant value : integer)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "ignore_bin(" & to_string(value) & ")";
begin
return create_bin_single(VAL_IGNORE, value, C_LOCAL_CALL);
end function;
-- Creates an ignore bin for a range of values
impure function ignore_bin_range(
constant min_value : integer;
constant max_value : integer)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "ignore_bin_range(" & to_string(min_value) & "," & to_string(max_value) & ")";
begin
return create_bin_range(RAN_IGNORE, min_value, max_value, 1, C_LOCAL_CALL);
end function;
-- Creates an ignore bin for a transition of values
impure function ignore_bin_transition(
constant set_of_values : integer_vector)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "ignore_bin_transition(" & to_string(set_of_values) & ")";
begin
return create_bin_multiple(TRN_IGNORE, set_of_values, C_LOCAL_CALL);
end function;
-- Creates an illegal bin for a single value
impure function illegal_bin(
constant value : integer)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "illegal_bin(" & to_string(value) & ")";
begin
return create_bin_single(VAL_ILLEGAL, value, C_LOCAL_CALL);
end function;
-- Creates an illegal bin for a range of values
impure function illegal_bin_range(
constant min_value : integer;
constant max_value : integer)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "illegal_bin_range(" & to_string(min_value) & "," & to_string(max_value) & ")";
begin
return create_bin_range(RAN_ILLEGAL, min_value, max_value, 1, C_LOCAL_CALL);
end function;
-- Creates an illegal bin for a transition of values
impure function illegal_bin_transition(
constant set_of_values : integer_vector)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "illegal_bin_transition(" & to_string(set_of_values) & ")";
begin
return create_bin_multiple(TRN_ILLEGAL, set_of_values, C_LOCAL_CALL);
end function;
------------------------------------------------------------
-- Overall coverage
------------------------------------------------------------
procedure fc_set_covpts_coverage_goal(
constant percentage : in positive range 1 to 100;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "fc_set_covpts_coverage_goal(" & to_string(percentage) & ")";
begin
log(ID_FUNC_COV_CONFIG, C_LOCAL_CALL, scope, msg_id_panel);
protected_covergroup_status.set_covpts_coverage_goal(percentage);
end procedure;
impure function fc_get_covpts_coverage_goal(
constant VOID : t_void)
return positive is
begin
return protected_covergroup_status.get_covpts_coverage_goal(VOID);
end function;
impure function fc_get_overall_coverage(
constant coverage_type : t_overall_coverage_type)
return real is
begin
if coverage_type = BINS then
return protected_covergroup_status.get_total_bins_coverage(VOID);
elsif coverage_type = HITS then
return protected_covergroup_status.get_total_hits_coverage(VOID);
else -- COVPTS
return protected_covergroup_status.get_total_covpts_coverage(NO_GOAL);
end if;
end function;
impure function fc_overall_coverage_completed(
constant VOID : t_void)
return boolean is
begin
return protected_covergroup_status.get_total_covpts_coverage(GOAL_CAPPED) = 100.0;
end function;
procedure fc_report_overall_coverage(
constant VOID : in t_void) is
begin
fc_report_overall_coverage(NON_VERBOSE);
end procedure;
procedure fc_report_overall_coverage(
constant verbosity : in t_report_verbosity;
constant file_name : in string := "";
constant open_mode : in file_open_kind := append_mode;
constant scope : in string := C_TB_SCOPE_DEFAULT) is
file file_handler : text;
constant C_PREFIX : string := C_LOG_PREFIX & " ";
constant C_HEADER_1 : string := "*** OVERALL COVERAGE REPORT (VERBOSE): " & to_string(scope) & " ***";
constant C_HEADER_2 : string := "*** OVERALL COVERAGE REPORT (NON VERBOSE): " & to_string(scope) & " ***";
constant C_HEADER_3 : string := "*** OVERALL HOLES REPORT: " & to_string(scope) & " ***";
constant C_COLUMN_WIDTH : positive := 20;
constant C_PRINT_GOAL : boolean := protected_covergroup_status.get_covpts_coverage_goal(VOID) /= 100;
variable v_line : line;
variable v_log_extra_space : integer := 0;
begin
-- Calculate how much space we can insert between the columns of the report
v_log_extra_space := (C_LOG_LINE_WIDTH - C_PREFIX'length - C_FC_MAX_NAME_LENGTH - C_COLUMN_WIDTH*5)/7;
if v_log_extra_space < 1 then
alert(TB_WARNING, "C_LOG_LINE_WIDTH is too small or C_FC_MAX_NAME_LENGTH is too big, the report will not be properly aligned.", scope);
v_log_extra_space := 1;
end if;
-- Print report header
write(v_line, LF & fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF);
if verbosity = VERBOSE then
write(v_line, timestamp_header(now, justify(C_HEADER_1, LEFT, C_LOG_LINE_WIDTH - C_PREFIX'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE)) & LF);
elsif verbosity = NON_VERBOSE then
write(v_line, timestamp_header(now, justify(C_HEADER_2, LEFT, C_LOG_LINE_WIDTH - C_PREFIX'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE)) & LF);
elsif verbosity = HOLES_ONLY then
write(v_line, timestamp_header(now, justify(C_HEADER_3, LEFT, C_LOG_LINE_WIDTH - C_PREFIX'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE)) & LF);
end if;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF);
-- Print summary
write(v_line, return_string_if_true("Goal: Covpts: " & to_string(protected_covergroup_status.get_covpts_coverage_goal(VOID)) & "%" & LF, C_PRINT_GOAL) &
return_string_if_true("% of Goal: Covpts: " & to_string(protected_covergroup_status.get_total_covpts_coverage(GOAL_CAPPED),2) & "%" & LF, C_PRINT_GOAL) &
return_string_if_true("% of Goal (uncapped): Covpts: " & to_string(protected_covergroup_status.get_total_covpts_coverage(GOAL_UNCAPPED),2) & "%" & LF, C_PRINT_GOAL) &
"Coverage (for goal 100): " &
justify("Covpts: " & to_string(protected_covergroup_status.get_total_covpts_coverage(NO_GOAL),2) & "%, ", left, 18, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("Bins: " & to_string(protected_covergroup_status.get_total_bins_coverage(VOID),2) & "%, ", left, 16, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("Hits: " & to_string(protected_covergroup_status.get_total_hits_coverage(VOID),2) & "%", left, 14, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF &
fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF);
if verbosity = VERBOSE or verbosity = HOLES_ONLY then
-- Print column headers
write(v_line, justify(
fill_string(' ', v_log_extra_space) &
justify("COVERPOINT" , center, C_FC_MAX_NAME_LENGTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("COVERAGE WEIGHT" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("COVERED BINS" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("COVERAGE(BINS|HITS)" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("GOAL(BINS|HITS)" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("% OF GOAL(BINS|HITS)", center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),
left, C_LOG_LINE_WIDTH - C_PREFIX'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
-- Print coverpoints
for i in 0 to C_FC_MAX_NUM_COVERPOINTS-1 loop
if protected_covergroup_status.is_initialized(i) then
if verbosity /= HOLES_ONLY or not(protected_covergroup_status.get_bins_coverage(i, GOAL_CAPPED) = 100.0 and protected_covergroup_status.get_hits_coverage(i, GOAL_CAPPED) = 100.0) then
write(v_line, justify(
fill_string(' ', v_log_extra_space) &
justify(protected_covergroup_status.get_name(i), center, C_FC_MAX_NAME_LENGTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(protected_covergroup_status.get_coverage_weight(i)), center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(protected_covergroup_status.get_num_covered_bins(i)) & " / " &
to_string(protected_covergroup_status.get_num_valid_bins(i)), center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(protected_covergroup_status.get_bins_coverage(i, NO_GOAL),2) & "% | " &
to_string(protected_covergroup_status.get_hits_coverage(i, NO_GOAL),2) & "%", center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(protected_covergroup_status.get_bins_coverage_goal(i)) & "% | " &
to_string(protected_covergroup_status.get_hits_coverage_goal(i)) & "%", center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(protected_covergroup_status.get_bins_coverage(i, GOAL_CAPPED),2) & "% | " &
to_string(protected_covergroup_status.get_hits_coverage(i, GOAL_CAPPED),2) & "%", center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),
left, C_LOG_LINE_WIDTH - C_PREFIX'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
end if;
end if;
end loop;
-- Print report bottom line
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF & LF);
end if;
-- Write the info string to transcript
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-C_PREFIX'length);
prefix_lines(v_line, C_PREFIX);
if file_name /= "" then
file_open(file_handler, file_name, open_mode);
tee(file_handler, v_line); -- write to file, while keeping the line contents
file_close(file_handler);
end if;
write_line_to_log_destination(v_line);
deallocate(v_line);
end procedure;
------------------------------------------------------------
-- Protected type
------------------------------------------------------------
type t_coverpoint is protected body
type t_bin_type_verbosity is (LONG, SHORT, NONE);
type t_samples_vector is array (natural range <>) of integer_vector(C_FC_MAX_NUM_BIN_VALUES-1 downto 0);
-- This means that the randomization weight of the bin will be equal to the min_hits
-- parameter and will be reduced by 1 every time the bin is sampled.
constant C_USE_ADAPTIVE_WEIGHT : integer := -1;
-- Indicates that the coverpoint hasn't been initialized
constant C_DEALLOCATED_ID : integer := -1;
-- Indicates an uninitialized natural value
constant C_UNINITIALIZED : integer := -1;
variable priv_id : integer := C_DEALLOCATED_ID;
variable priv_name : string(1 to C_FC_MAX_NAME_LENGTH);
variable priv_scope : string(1 to C_LOG_SCOPE_WIDTH) := C_TB_SCOPE_DEFAULT & fill_string(NUL, C_LOG_SCOPE_WIDTH-C_TB_SCOPE_DEFAULT'length);
variable priv_bins : t_cov_bin_vector_ptr := new t_cov_bin_vector(0 to C_FC_DEFAULT_INITIAL_NUM_BINS_ALLOCATED-1);
variable priv_bins_idx : natural := 0;
variable priv_invalid_bins : t_cov_bin_vector_ptr := new t_cov_bin_vector(0 to C_FC_DEFAULT_INITIAL_NUM_BINS_ALLOCATED-1);
variable priv_invalid_bins_idx : natural := 0;
variable priv_num_bins_crossed : integer := C_UNINITIALIZED;
variable priv_rand_gen : t_rand;
variable priv_rand_transition_bin_idx : integer := C_UNINITIALIZED;
variable priv_rand_transition_bin_value_idx : t_natural_vector(0 to C_MAX_NUM_CROSS_BINS-1) := (others => 0);
variable priv_bin_sample_shift_reg : t_samples_vector(0 to C_MAX_NUM_CROSS_BINS-1) := (others => (others => 0));
variable priv_illegal_bin_alert_level : t_alert_level := ERROR;
variable priv_bin_overlap_alert_level : t_alert_level := NO_ALERT;
variable priv_num_bins_allocated_increment : positive := C_FC_DEFAULT_NUM_BINS_ALLOCATED_INCREMENT;
------------------------------------------------------------
-- Internal functions and procedures
------------------------------------------------------------
-- Returns a string with all the procedure calls in the array
impure function get_proc_calls(
constant bin_array : t_new_bin_array)
return string is
variable v_line : line;
impure function return_and_deallocate return string is
constant ret : string := v_line.all;
begin
DEALLOCATE(v_line);
return ret;
end function;
begin
for i in bin_array'range loop
write(v_line, bin_array(i).proc_call);
if i < bin_array'length-1 then
write(v_line, ',');
end if;
end loop;
return return_and_deallocate;
end function;
-- Returns a string with all the bin values in the array
impure function get_bin_array_values(
constant bin_array : t_new_bin_array;
constant bin_verbosity : t_bin_type_verbosity := SHORT;
constant bin_delimiter : character := ',')
return string is
variable v_line : line;
impure function return_bin_type(
constant full_name : string;
constant short_name : string;
constant bin_verbosity : t_bin_type_verbosity)
return string is
begin
if bin_verbosity = LONG then
return full_name;
elsif bin_verbosity = SHORT then
return short_name;
else
return "";
end if;
end function;
impure function return_and_deallocate return string is
constant ret : string := v_line.all;
begin
DEALLOCATE(v_line);
return ret;
end function;
begin
for i in bin_array'range loop
for j in 0 to bin_array(i).num_bins-1 loop
case bin_array(i).bin_vector(j).contains is
when VAL | VAL_IGNORE | VAL_ILLEGAL =>
if bin_array(i).bin_vector(j).contains = VAL then
write(v_line, string'(return_bin_type("bin", "", bin_verbosity)));
elsif bin_array(i).bin_vector(j).contains = VAL_IGNORE then
write(v_line, string'(return_bin_type("ignore_bin", "IGN", bin_verbosity)));
else
write(v_line, string'(return_bin_type("illegal_bin", "ILL", bin_verbosity)));
end if;
if bin_array(i).bin_vector(j).num_values = 1 then
write(v_line, '(' & to_string(bin_array(i).bin_vector(j).values(0)) & ')');
else
write(v_line, to_string(bin_array(i).bin_vector(j).values(0 to bin_array(i).bin_vector(j).num_values-1)));
end if;
when RAN | RAN_IGNORE | RAN_ILLEGAL =>
if bin_array(i).bin_vector(j).contains = RAN then
write(v_line, string'(return_bin_type("bin_range", "", bin_verbosity)));
elsif bin_array(i).bin_vector(j).contains = RAN_IGNORE then
write(v_line, string'(return_bin_type("ignore_bin_range", "IGN", bin_verbosity)));
else
write(v_line, string'(return_bin_type("illegal_bin_range", "ILL", bin_verbosity)));
end if;
write(v_line, "(" & to_string(bin_array(i).bin_vector(j).values(0)) & " to " & to_string(bin_array(i).bin_vector(j).values(1)) & ")");
when TRN | TRN_IGNORE | TRN_ILLEGAL =>
if bin_array(i).bin_vector(j).contains = TRN then
write(v_line, string'(return_bin_type("bin_transition", "", bin_verbosity)));
elsif bin_array(i).bin_vector(j).contains = TRN_IGNORE then
write(v_line, string'(return_bin_type("ignore_bin_transition", "IGN", bin_verbosity)));
else
write(v_line, string'(return_bin_type("illegal_bin_transition", "ILL", bin_verbosity)));
end if;
write(v_line, '(');
for k in 0 to bin_array(i).bin_vector(j).num_values-1 loop
write(v_line, to_string(bin_array(i).bin_vector(j).values(k)));
if k < bin_array(i).bin_vector(j).num_values-1 then
write(v_line, string'("->"));
end if;
end loop;
write(v_line, ')');
end case;
if i < bin_array'length-1 or j < bin_array(i).num_bins-1 then
write(v_line, bin_delimiter);
end if;
end loop;
end loop;
if v_line /= NULL then
return return_and_deallocate;
else
return "";
end if;
end function;
-- Returns a string with all the values in the bin. Since it is
-- used in the report, if the string is bigger than the maximum
-- length allowed, the bin name is returned instead.
-- If max_str_length is 0 then the string with the values is
-- always returned.
impure function get_bin_values(
constant bin : t_cov_bin;
constant max_str_length : natural := 0)
return string is
variable v_new_bin_array : t_new_bin_array(0 to 0);
variable v_line : line;
impure function return_and_deallocate return string is
constant ret : string := v_line.all;
begin
DEALLOCATE(v_line);
return ret;
end function;
begin
for i in 0 to priv_num_bins_crossed-1 loop
v_new_bin_array(0).bin_vector(i).contains := bin.cross_bins(i).contains;
v_new_bin_array(0).bin_vector(i).values := bin.cross_bins(i).values;
v_new_bin_array(0).bin_vector(i).num_values := bin.cross_bins(i).num_values;
end loop;
v_new_bin_array(0).num_bins := priv_num_bins_crossed;
-- Used in the report, so the bins in each vector are crossed
write(v_line, get_bin_array_values(v_new_bin_array, NONE, 'x'));
if max_str_length /= 0 and v_line'length > max_str_length then
DEALLOCATE(v_line);
return to_string(bin.name);
else
return return_and_deallocate;
end if;
end function;
-- Returns a string with the bin content
impure function get_bin_info(
constant bin : t_bin)
return string is
variable v_new_bin_array : t_new_bin_array(0 to 0);
begin
v_new_bin_array(0).bin_vector(0).contains := bin.contains;
v_new_bin_array(0).bin_vector(0).values := bin.values;
v_new_bin_array(0).bin_vector(0).num_values := bin.num_values;
v_new_bin_array(0).num_bins := 1;
return get_bin_array_values(v_new_bin_array, LONG);
end function;
-- If the bin_name is empty, it returns a default name based on the bin_idx.
-- Otherwise it returns the bin_name padded to match the C_FC_MAX_NAME_LENGTH.
function get_bin_name(
constant bin_name : string;
constant bin_idx : string)
return string is
begin
if bin_name = "" then
return "bin_" & bin_idx & fill_string(NUL, C_FC_MAX_NAME_LENGTH-4-bin_idx'length);
else
if bin_name'length > C_FC_MAX_NAME_LENGTH then
return bin_name(1 to C_FC_MAX_NAME_LENGTH);
else
return bin_name & fill_string(NUL, C_FC_MAX_NAME_LENGTH-bin_name'length);
end if;
end if;
end function;
-- Returns a string with the coverpoint's name. Used as prefix in log messages
impure function get_name_prefix(
constant VOID : t_void)
return string is
begin
return "[" & to_string(priv_name) & "] ";
end function;
-- Returns true if the bin is ignored
impure function is_bin_ignore(
constant bin : t_cov_bin)
return boolean is
variable v_is_ignore : boolean := false;
begin
for i in 0 to priv_num_bins_crossed-1 loop
v_is_ignore := v_is_ignore or (bin.cross_bins(i).contains = VAL_IGNORE or
bin.cross_bins(i).contains = RAN_IGNORE or
bin.cross_bins(i).contains = TRN_IGNORE);
end loop;
return v_is_ignore;
end function;
-- Returns true if the bin is illegal
impure function is_bin_illegal(
constant bin : t_cov_bin)
return boolean is
variable v_is_illegal : boolean := false;
begin
for i in 0 to priv_num_bins_crossed-1 loop
v_is_illegal := v_is_illegal or (bin.cross_bins(i).contains = VAL_ILLEGAL or
bin.cross_bins(i).contains = RAN_ILLEGAL or
bin.cross_bins(i).contains = TRN_ILLEGAL);
end loop;
return v_is_illegal;
end function;
-- Returns the minimum number of hits multiplied by the hits coverage goal
impure function get_total_min_hits(
constant min_hits : natural)
return natural is
begin
return integer(real(min_hits)*real(protected_covergroup_status.get_hits_coverage_goal(priv_id))/100.0);
end function;
-- Returns the percentage of hits/min_hits in a bin. Note that it saturates at 100%
impure function get_bin_coverage(
constant bin : t_cov_bin)
return real is
variable v_coverage : real;
begin
if bin.hits < bin.min_hits then
v_coverage := real(bin.hits)*100.0/real(bin.min_hits);
else
v_coverage := 100.0;
end if;
return v_coverage;
end function;
-- Initializes a new coverpoint by registering it in the covergroup status register, setting its name and randomization seeds.
procedure initialize_coverpoint(
constant local_call : in string) is
begin
if priv_id = C_DEALLOCATED_ID then
priv_id := protected_covergroup_status.add_coverpoint(VOID);
if priv_id = C_DEALLOCATED_ID then
alert(TB_FAILURE, local_call & "=> Number of coverpoints exceeds C_FC_MAX_NUM_COVERPOINTS.\n Increase C_FC_MAX_NUM_COVERPOINTS in adaptations package.", priv_scope);
return;
end if;
-- Only set the default name if it hasn't been given
if priv_name = fill_string(NUL, priv_name'length) then
set_name(protected_covergroup_status.get_name(priv_id));
end if;
priv_rand_gen.set_rand_seeds(priv_name);
end if;
end procedure;
-- TODO: max 16 dimensions
-- Checks that the number of crossed bins does not change.
-- If the extra parameters are given, it checks that the coverpoints are not empty.
procedure check_num_bins_crossed(
constant num_bins_crossed : in integer;
constant local_call : in string;
constant coverpoint1_num_bins_crossed : in integer := 0;
constant coverpoint2_num_bins_crossed : in integer := 0;
constant coverpoint3_num_bins_crossed : in integer := 0;
constant coverpoint4_num_bins_crossed : in integer := 0;
constant coverpoint5_num_bins_crossed : in integer := 0) is
begin
initialize_coverpoint(local_call);
check_value(coverpoint1_num_bins_crossed /= C_UNINITIALIZED, TB_FAILURE, "Coverpoint 1 is empty", priv_scope, ID_NEVER, caller_name => local_call);
check_value(coverpoint2_num_bins_crossed /= C_UNINITIALIZED, TB_FAILURE, "Coverpoint 2 is empty", priv_scope, ID_NEVER, caller_name => local_call);
check_value(coverpoint3_num_bins_crossed /= C_UNINITIALIZED, TB_FAILURE, "Coverpoint 3 is empty", priv_scope, ID_NEVER, caller_name => local_call);
check_value(coverpoint4_num_bins_crossed /= C_UNINITIALIZED, TB_FAILURE, "Coverpoint 4 is empty", priv_scope, ID_NEVER, caller_name => local_call);
check_value(coverpoint5_num_bins_crossed /= C_UNINITIALIZED, TB_FAILURE, "Coverpoint 5 is empty", priv_scope, ID_NEVER, caller_name => local_call);
-- The number of bins crossed is set on the first call and can't be changed
if priv_num_bins_crossed = C_UNINITIALIZED and num_bins_crossed > 0 then
priv_num_bins_crossed := num_bins_crossed;
elsif priv_num_bins_crossed /= num_bins_crossed and num_bins_crossed > 0 then
alert(TB_FAILURE, local_call & "=> Cannot mix different number of crossed bins.", priv_scope);
end if;
end procedure;
-- Returns true if a bin is already stored in the bin vector
impure function find_duplicate_bin(
constant cov_bin_vector : t_cov_bin_vector;
constant cov_bin_idx : natural;
constant cross_bin_idx : natural)
return boolean is
constant C_CONTAINS : t_cov_bin_type := cov_bin_vector(cov_bin_idx).cross_bins(cross_bin_idx).contains;
constant C_NUM_VALUES : natural := cov_bin_vector(cov_bin_idx).cross_bins(cross_bin_idx).num_values;
constant C_VALUES : integer_vector(0 to C_NUM_VALUES-1) := cov_bin_vector(cov_bin_idx).cross_bins(cross_bin_idx).values(0 to C_NUM_VALUES-1);
begin
for i in 0 to cov_bin_idx-1 loop
if cov_bin_vector(i).cross_bins(cross_bin_idx).contains = C_CONTAINS and
cov_bin_vector(i).cross_bins(cross_bin_idx).num_values = C_NUM_VALUES and
cov_bin_vector(i).cross_bins(cross_bin_idx).values(0 to C_NUM_VALUES-1) = C_VALUES
then
return true;
end if;
end loop;
return false;
end function;
-- Copies all the bins in a bin array to a bin vector.
-- The bin array can contain several bin_vector elements depending on the
-- number of bins created by a single bin function. It can also contain
-- several array elements depending on the number of concatenated bin
-- functions used.
procedure copy_bins_in_bin_array(
constant bin_array : in t_new_bin_array;
variable cov_bin : out t_new_cov_bin;
constant proc_call : in string) is
variable v_num_bins : natural := 0;
begin
for i in bin_array'range loop
if v_num_bins + bin_array(i).num_bins > C_FC_MAX_NUM_NEW_BINS then
alert(TB_ERROR, proc_call & "=> Number of bins added in a single procedure call exceeds C_FC_MAX_NUM_NEW_BINS.\n" &
"Increase C_FC_MAX_NUM_NEW_BINS in adaptations package.", C_TB_SCOPE_DEFAULT);
return;
end if;
cov_bin.bin_vector(v_num_bins to v_num_bins+bin_array(i).num_bins-1) := bin_array(i).bin_vector(0 to bin_array(i).num_bins-1);
v_num_bins := v_num_bins + bin_array(i).num_bins;
end loop;
cov_bin.num_bins := v_num_bins;
end procedure;
-- Copies all the bins in a coverpoint to a bin array (including crossed bins)
-- Duplicate bins are not copied since they are assumed to be the result of a cross
procedure copy_bins_in_coverpoint(
variable coverpoint : inout t_coverpoint;
variable bin_array : out t_new_bin_array) is
variable v_coverpoint_bins : t_cov_bin_vector(0 to coverpoint.get_num_valid_bins(VOID)-1);
variable v_coverpoint_invalid_bins : t_cov_bin_vector(0 to coverpoint.get_num_invalid_bins(VOID)-1);
variable v_num_bins : natural := 0;
begin
v_coverpoint_bins := coverpoint.get_valid_bins(VOID);
v_coverpoint_invalid_bins := coverpoint.get_invalid_bins(VOID);
for cross in 0 to bin_array'length-1 loop
for i in v_coverpoint_bins'range loop
if not find_duplicate_bin(v_coverpoint_bins, i, cross) then
bin_array(cross).bin_vector(v_num_bins).contains := v_coverpoint_bins(i).cross_bins(cross).contains;
bin_array(cross).bin_vector(v_num_bins).values := v_coverpoint_bins(i).cross_bins(cross).values;
bin_array(cross).bin_vector(v_num_bins).num_values := v_coverpoint_bins(i).cross_bins(cross).num_values;
v_num_bins := v_num_bins + 1;
end if;
end loop;
for i in v_coverpoint_invalid_bins'range loop
if not find_duplicate_bin(v_coverpoint_invalid_bins, i, cross) then
bin_array(cross).bin_vector(v_num_bins).contains := v_coverpoint_invalid_bins(i).cross_bins(cross).contains;
bin_array(cross).bin_vector(v_num_bins).values := v_coverpoint_invalid_bins(i).cross_bins(cross).values;
bin_array(cross).bin_vector(v_num_bins).num_values := v_coverpoint_invalid_bins(i).cross_bins(cross).num_values;
v_num_bins := v_num_bins + 1;
end if;
end loop;
bin_array(cross).num_bins := v_num_bins;
v_num_bins := 0;
end loop;
end procedure;
-- Creates a bin array from several bin arrays
procedure create_bin_array(
constant proc_call : in string;
variable bin_array : out t_new_bin_array;
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array := C_EMPTY_NEW_BIN_ARRAY;
constant bin3 : in t_new_bin_array := C_EMPTY_NEW_BIN_ARRAY;
constant bin4 : in t_new_bin_array := C_EMPTY_NEW_BIN_ARRAY;
constant bin5 : in t_new_bin_array := C_EMPTY_NEW_BIN_ARRAY) is
begin
copy_bins_in_bin_array(bin1, bin_array(0), proc_call);
if bin2 /= C_EMPTY_NEW_BIN_ARRAY then
copy_bins_in_bin_array(bin2, bin_array(1), proc_call);
end if;
if bin3 /= C_EMPTY_NEW_BIN_ARRAY then
copy_bins_in_bin_array(bin3, bin_array(2), proc_call);
end if;
if bin4 /= C_EMPTY_NEW_BIN_ARRAY then
copy_bins_in_bin_array(bin4, bin_array(3), proc_call);
end if;
if bin5 /= C_EMPTY_NEW_BIN_ARRAY then
copy_bins_in_bin_array(bin5, bin_array(4), proc_call);
end if;
end procedure;
-- Creates a bin array from several coverpoints
procedure create_bin_array(
variable bin_array : out t_new_bin_array;
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint) is
variable v_bin_array1 : t_new_bin_array(0 to coverpoint1.get_num_bins_crossed(VOID)-1);
variable v_bin_array2 : t_new_bin_array(0 to coverpoint2.get_num_bins_crossed(VOID)-1);
begin
copy_bins_in_coverpoint(coverpoint1, v_bin_array1);
copy_bins_in_coverpoint(coverpoint2, v_bin_array2);
bin_array := v_bin_array1 & v_bin_array2;
end procedure;
-- Overload
procedure create_bin_array(
variable bin_array : out t_new_bin_array;
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint) is
variable v_bin_array1 : t_new_bin_array(0 to coverpoint1.get_num_bins_crossed(VOID)-1);
variable v_bin_array2 : t_new_bin_array(0 to coverpoint2.get_num_bins_crossed(VOID)-1);
variable v_bin_array3 : t_new_bin_array(0 to coverpoint3.get_num_bins_crossed(VOID)-1);
begin
copy_bins_in_coverpoint(coverpoint1, v_bin_array1);
copy_bins_in_coverpoint(coverpoint2, v_bin_array2);
copy_bins_in_coverpoint(coverpoint3, v_bin_array3);
bin_array := v_bin_array1 & v_bin_array2 & v_bin_array3;
end procedure;
-- Overload
procedure create_bin_array(
variable bin_array : out t_new_bin_array;
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint) is
variable v_bin_array1 : t_new_bin_array(0 to coverpoint1.get_num_bins_crossed(VOID)-1);
variable v_bin_array2 : t_new_bin_array(0 to coverpoint2.get_num_bins_crossed(VOID)-1);
variable v_bin_array3 : t_new_bin_array(0 to coverpoint3.get_num_bins_crossed(VOID)-1);
variable v_bin_array4 : t_new_bin_array(0 to coverpoint4.get_num_bins_crossed(VOID)-1);
begin
copy_bins_in_coverpoint(coverpoint1, v_bin_array1);
copy_bins_in_coverpoint(coverpoint2, v_bin_array2);
copy_bins_in_coverpoint(coverpoint3, v_bin_array3);
copy_bins_in_coverpoint(coverpoint4, v_bin_array4);
bin_array := v_bin_array1 & v_bin_array2 & v_bin_array3 & v_bin_array4;
end procedure;
-- TODO: create more overloads (16)
-- Overload
procedure create_bin_array(
variable bin_array : out t_new_bin_array;
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
variable coverpoint5 : inout t_coverpoint) is
variable v_bin_array1 : t_new_bin_array(0 to coverpoint1.get_num_bins_crossed(VOID)-1);
variable v_bin_array2 : t_new_bin_array(0 to coverpoint2.get_num_bins_crossed(VOID)-1);
variable v_bin_array3 : t_new_bin_array(0 to coverpoint3.get_num_bins_crossed(VOID)-1);
variable v_bin_array4 : t_new_bin_array(0 to coverpoint4.get_num_bins_crossed(VOID)-1);
variable v_bin_array5 : t_new_bin_array(0 to coverpoint5.get_num_bins_crossed(VOID)-1);
begin
copy_bins_in_coverpoint(coverpoint1, v_bin_array1);
copy_bins_in_coverpoint(coverpoint2, v_bin_array2);
copy_bins_in_coverpoint(coverpoint3, v_bin_array3);
copy_bins_in_coverpoint(coverpoint4, v_bin_array4);
copy_bins_in_coverpoint(coverpoint5, v_bin_array5);
bin_array := v_bin_array1 & v_bin_array2 & v_bin_array3 & v_bin_array4 & v_bin_array5;
end procedure;
-- Checks that the number of transitions is the same for all elements in a cross
procedure check_cross_num_transitions(
variable num_transitions : inout integer;
constant contains : in t_cov_bin_type;
constant num_values : in natural) is
begin
if contains = TRN or contains = TRN_IGNORE or contains = TRN_ILLEGAL then
if num_transitions = C_UNINITIALIZED then
num_transitions := num_values;
else
check_value(num_values, num_transitions, TB_ERROR, "Number of transition values must be the same in all cross elements", priv_scope, ID_NEVER);
end if;
end if;
end procedure;
-- Resizes the bin vector by creating a new memory structure and deallocating the old one
procedure resize_bin_vector(
variable bin_vector : inout t_cov_bin_vector_ptr;
constant size : in natural := 0) is
variable v_copy_ptr : t_cov_bin_vector_ptr;
begin
v_copy_ptr := bin_vector;
if size = 0 then
bin_vector := new t_cov_bin_vector(0 to v_copy_ptr'length + priv_num_bins_allocated_increment);
else
bin_vector := new t_cov_bin_vector(0 to size-1);
end if;
bin_vector(0 to v_copy_ptr'length-1) := v_copy_ptr.all;
DEALLOCATE(v_copy_ptr);
end procedure;
-- Adds bins in a recursive way
procedure add_bins_recursive(
constant bin_array : in t_new_bin_array;
constant bin_array_idx : in integer;
variable idx_reg : inout integer_vector;
constant min_hits : in positive;
constant rand_weight : in natural;
constant use_rand_weight : in boolean;
constant bin_name : in string) is
constant C_NUM_CROSS_BINS : natural := bin_array'length;
variable v_bin_is_valid : boolean := true;
variable v_bin_is_illegal : boolean := false;
variable v_num_transitions : integer;
begin
check_value(priv_id /= C_DEALLOCATED_ID, TB_FAILURE, "Coverpoint has not been initialized", priv_scope, ID_NEVER);
-- Iterate through the bins in the current array element
for i in 0 to bin_array(bin_array_idx).num_bins-1 loop
-- Store the bin index for the current element of the array
idx_reg(bin_array_idx) := i;
-- Last element of the array has been reached, add bins
if bin_array_idx = C_NUM_CROSS_BINS-1 then
-- Check that all the bins being added are valid
for j in 0 to C_NUM_CROSS_BINS-1 loop
v_bin_is_valid := v_bin_is_valid and (bin_array(j).bin_vector(idx_reg(j)).contains = VAL or
bin_array(j).bin_vector(idx_reg(j)).contains = RAN or
bin_array(j).bin_vector(idx_reg(j)).contains = TRN);
v_bin_is_illegal := v_bin_is_illegal or (bin_array(j).bin_vector(idx_reg(j)).contains = VAL_ILLEGAL or
bin_array(j).bin_vector(idx_reg(j)).contains = RAN_ILLEGAL or
bin_array(j).bin_vector(idx_reg(j)).contains = TRN_ILLEGAL);
end loop;
v_num_transitions := C_UNINITIALIZED;
-- Store valid bins
if v_bin_is_valid then
-- Resize if there's no space in the list
if priv_bins_idx = priv_bins'length then
resize_bin_vector(priv_bins);
end if;
for j in 0 to C_NUM_CROSS_BINS-1 loop
check_cross_num_transitions(v_num_transitions, bin_array(j).bin_vector(idx_reg(j)).contains, bin_array(j).bin_vector(idx_reg(j)).num_values);
priv_bins(priv_bins_idx).cross_bins(j).contains := bin_array(j).bin_vector(idx_reg(j)).contains;
priv_bins(priv_bins_idx).cross_bins(j).values := bin_array(j).bin_vector(idx_reg(j)).values;
priv_bins(priv_bins_idx).cross_bins(j).num_values := bin_array(j).bin_vector(idx_reg(j)).num_values;
end loop;
priv_bins(priv_bins_idx).hits := 0;
priv_bins(priv_bins_idx).min_hits := min_hits;
priv_bins(priv_bins_idx).rand_weight := rand_weight when use_rand_weight else C_USE_ADAPTIVE_WEIGHT;
priv_bins(priv_bins_idx).transition_mask := (others => '0');
priv_bins(priv_bins_idx).name := get_bin_name(bin_name, to_string(priv_bins_idx+priv_invalid_bins_idx));
priv_bins_idx := priv_bins_idx + 1;
-- Update covergroup status register
protected_covergroup_status.increment_valid_bin_count(priv_id);
protected_covergroup_status.increment_min_hits_count(priv_id, min_hits);
-- Store ignore or illegal bins
else
-- Check if there's space in the list
if priv_invalid_bins_idx = priv_invalid_bins'length then
resize_bin_vector(priv_invalid_bins);
end if;
for j in 0 to C_NUM_CROSS_BINS-1 loop
check_cross_num_transitions(v_num_transitions, bin_array(j).bin_vector(idx_reg(j)).contains, bin_array(j).bin_vector(idx_reg(j)).num_values);
priv_invalid_bins(priv_invalid_bins_idx).cross_bins(j).contains := bin_array(j).bin_vector(idx_reg(j)).contains;
priv_invalid_bins(priv_invalid_bins_idx).cross_bins(j).values := bin_array(j).bin_vector(idx_reg(j)).values;
priv_invalid_bins(priv_invalid_bins_idx).cross_bins(j).num_values := bin_array(j).bin_vector(idx_reg(j)).num_values;
end loop;
priv_invalid_bins(priv_invalid_bins_idx).hits := 0;
priv_invalid_bins(priv_invalid_bins_idx).min_hits := 0;
priv_invalid_bins(priv_invalid_bins_idx).rand_weight := 0;
priv_invalid_bins(priv_invalid_bins_idx).transition_mask := (others => '0');
priv_invalid_bins(priv_invalid_bins_idx).name := get_bin_name(bin_name, to_string(priv_bins_idx+priv_invalid_bins_idx));
priv_invalid_bins_idx := priv_invalid_bins_idx + 1;
end if;
-- Go to the next element of the array
else
add_bins_recursive(bin_array, bin_array_idx+1, idx_reg, min_hits, rand_weight, use_rand_weight, bin_name);
end if;
end loop;
end procedure;
------------------------------------------------------------
-- Configuration
------------------------------------------------------------
procedure set_name(
constant name : in string) is
constant C_LOCAL_CALL : string := "set_name(" & name & ")";
begin
if name'length > C_FC_MAX_NAME_LENGTH then
priv_name := name(1 to C_FC_MAX_NAME_LENGTH);
else
priv_name := name & fill_string(NUL, C_FC_MAX_NAME_LENGTH-name'length);
end if;
initialize_coverpoint(C_LOCAL_CALL);
protected_covergroup_status.set_name(priv_id, priv_name);
end procedure;
impure function get_name(
constant VOID : t_void)
return string is
begin
return to_string(priv_name);
end function;
procedure set_scope(
constant scope : in string) is
constant C_LOCAL_CALL : string := "set_scope(" & scope & ")";
begin
initialize_coverpoint(C_LOCAL_CALL);
if scope'length > C_LOG_SCOPE_WIDTH then
priv_scope := scope(1 to C_LOG_SCOPE_WIDTH);
else
priv_scope := scope & fill_string(NUL, C_LOG_SCOPE_WIDTH-scope'length);
end if;
end procedure;
impure function get_scope(
constant VOID : t_void)
return string is
begin
return to_string(priv_scope);
end function;
procedure set_overall_coverage_weight(
constant weight : in natural;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "set_overall_coverage_weight(" & to_string(weight) & ")";
begin
initialize_coverpoint(C_LOCAL_CALL);
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
protected_covergroup_status.set_coverage_weight(priv_id, weight);
end procedure;
impure function get_overall_coverage_weight(
constant VOID : t_void)
return natural is
begin
if priv_id /= C_DEALLOCATED_ID then
return protected_covergroup_status.get_coverage_weight(priv_id);
else
return 1;
end if;
end function;
procedure set_bins_coverage_goal(
constant percentage : in positive range 1 to 100;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "set_bins_coverage_goal(" & to_string(percentage) & ")";
begin
initialize_coverpoint(C_LOCAL_CALL);
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
protected_covergroup_status.set_bins_coverage_goal(priv_id, percentage);
end procedure;
impure function get_bins_coverage_goal(
constant VOID : t_void)
return positive is
begin
if priv_id /= C_DEALLOCATED_ID then
return protected_covergroup_status.get_bins_coverage_goal(priv_id);
else
return 100;
end if;
end function;
procedure set_hits_coverage_goal(
constant percentage : in positive;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "set_hits_coverage_goal(" & to_string(percentage) & ")";
begin
initialize_coverpoint(C_LOCAL_CALL);
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
protected_covergroup_status.set_hits_coverage_goal(priv_id, percentage);
end procedure;
impure function get_hits_coverage_goal(
constant VOID : t_void)
return positive is
begin
if priv_id /= C_DEALLOCATED_ID then
return protected_covergroup_status.get_hits_coverage_goal(priv_id);
else
return 100;
end if;
end function;
procedure set_illegal_bin_alert_level(
constant alert_level : in t_alert_level;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "set_illegal_bin_alert_level(" & to_upper(to_string(alert_level)) & ")";
begin
initialize_coverpoint(C_LOCAL_CALL);
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
priv_illegal_bin_alert_level := alert_level;
end procedure;
impure function get_illegal_bin_alert_level(
constant VOID : t_void)
return t_alert_level is
begin
return priv_illegal_bin_alert_level;
end function;
procedure set_bin_overlap_alert_level(
constant alert_level : in t_alert_level;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "set_bin_overlap_alert_level(" & to_upper(to_string(alert_level)) & ")";
begin
initialize_coverpoint(C_LOCAL_CALL);
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
priv_bin_overlap_alert_level := alert_level;
end procedure;
impure function get_bin_overlap_alert_level(
constant VOID : t_void)
return t_alert_level is
begin
return priv_bin_overlap_alert_level;
end function;
procedure write_coverage_db(
constant file_name : in string;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "write_coverage_db(" & file_name & ")";
file file_handler : text open write_mode is file_name;
variable v_line : line;
procedure write_value(
constant value : in integer) is
begin
write(v_line, value);
writeline(file_handler, v_line);
end procedure;
procedure write_value(
constant value : in integer_vector) is
begin
for i in 0 to value'length-1 loop
write(v_line, value(i));
if i < value'length-1 then
write(v_line, ' ');
end if;
end loop;
writeline(file_handler, v_line);
end procedure;
procedure write_value(
constant value : in string) is
begin
write(v_line, value);
writeline(file_handler, v_line);
end procedure;
--procedure write_value(
-- constant value : in boolean) is
--begin
-- write(v_line, value);
-- writeline(file_handler, v_line);
--end procedure;
procedure write_bins(
constant bin_idx : in natural;
variable bin_vector : in t_cov_bin_vector_ptr) is
begin
write(v_line, bin_idx);
writeline(file_handler, v_line);
for i in 0 to bin_idx-1 loop
write(v_line, bin_vector(i).name);
writeline(file_handler, v_line);
write(v_line, to_string(bin_vector(i).hits) & ' ' &
to_string(bin_vector(i).min_hits) & ' ' &
to_string(bin_vector(i).rand_weight) & ' ' &
to_string(bin_vector(i).transition_mask));
writeline(file_handler, v_line);
for j in 0 to priv_num_bins_crossed-1 loop
write(v_line, to_string(t_cov_bin_type'pos(bin_vector(i).cross_bins(j).contains)) & ' ' &
to_string(bin_vector(i).cross_bins(j).num_values) & ' ');
for k in 0 to bin_vector(i).cross_bins(j).num_values-1 loop
write(v_line, bin_vector(i).cross_bins(j).values(k));
write(v_line, ' ');
end loop;
writeline(file_handler, v_line);
end loop;
end loop;
end procedure;
begin
if priv_id /= C_DEALLOCATED_ID then
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
-- Coverpoint config
write_value(priv_name);
write_value(priv_scope);
write_value(priv_num_bins_crossed);
write_value(integer_vector(priv_rand_gen.get_rand_seeds(VOID)));
write_value(priv_rand_transition_bin_idx);
write_value(integer_vector(priv_rand_transition_bin_value_idx));
for i in 0 to priv_num_bins_crossed-1 loop
write_value(priv_bin_sample_shift_reg(i));
end loop;
write_value(t_alert_level'pos(priv_illegal_bin_alert_level));
write_value(t_alert_level'pos(priv_bin_overlap_alert_level));
-- Covergroup config
write_value(protected_covergroup_status.get_num_valid_bins(priv_id));
write_value(protected_covergroup_status.get_num_covered_bins(priv_id));
write_value(protected_covergroup_status.get_total_bin_min_hits(priv_id));
write_value(protected_covergroup_status.get_total_bin_hits(priv_id));
write_value(protected_covergroup_status.get_total_coverage_bin_hits(priv_id));
write_value(protected_covergroup_status.get_total_goal_bin_hits(priv_id));
write_value(protected_covergroup_status.get_coverage_weight(priv_id));
write_value(protected_covergroup_status.get_bins_coverage_goal(priv_id));
write_value(protected_covergroup_status.get_hits_coverage_goal(priv_id));
write_value(protected_covergroup_status.get_covpts_coverage_goal(VOID));
-- Bin structure
write_bins(priv_bins_idx, priv_bins);
write_bins(priv_invalid_bins_idx, priv_invalid_bins);
else
alert(TB_ERROR, C_LOCAL_CALL & "=> Coverpoint has not been initialized", priv_scope);
end if;
file_close(file_handler);
DEALLOCATE(v_line);
end procedure;
procedure load_coverage_db(
constant file_name : in string;
constant report_verbosity : in t_report_verbosity := HOLES_ONLY;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "load_coverage_db(" & file_name & ")";
file file_handler : text;
variable v_open_status : file_open_status;
variable v_line : line;
variable v_value : integer;
variable v_rand_seeds : integer_vector(0 to 1);
variable v_rand_transition_bin_value_idx : integer_vector(0 to C_MAX_NUM_CROSS_BINS-1);
procedure read_value(
variable value : out integer) is
begin
readline(file_handler, v_line);
read(v_line, value);
end procedure;
procedure read_value(
variable value : out integer_vector) is
variable v_idx : natural := 0;
begin
readline(file_handler, v_line);
while v_line.all'length > 0 loop
read(v_line, value(v_idx));
v_idx := v_idx + 1;
exit when v_idx > value'length-1;
end loop;
end procedure;
procedure read_value(
variable value : out string) is
begin
readline(file_handler, v_line);
read(v_line, value);
end procedure;
--procedure read_value(
-- variable value : out boolean) is
--begin
-- readline(file_handler, v_line);
-- read(v_line, value);
--end procedure;
procedure read_bins(
constant bin_idx : in natural;
variable bin_vector : inout t_cov_bin_vector_ptr) is
variable v_contains : integer;
variable v_num_values : integer;
begin
if bin_idx > bin_vector'length-1 then
resize_bin_vector(bin_vector, bin_idx);
end if;
for i in 0 to bin_idx-1 loop
readline(file_handler, v_line);
read(v_line, bin_vector(i).name); -- read() crops the string
readline(file_handler, v_line);
read(v_line, bin_vector(i).hits);
read(v_line, bin_vector(i).min_hits);
read(v_line, bin_vector(i).rand_weight);
read(v_line, bin_vector(i).transition_mask);
for j in 0 to priv_num_bins_crossed-1 loop
readline(file_handler, v_line);
read(v_line, v_contains);
bin_vector(i).cross_bins(j).contains := t_cov_bin_type'val(v_contains);
read(v_line, v_num_values);
check_value(v_num_values <= C_FC_MAX_NUM_BIN_VALUES, TB_FAILURE, "Cannot load the " & to_string(v_num_values) & " bin values. Increase C_FC_MAX_NUM_BIN_VALUES",
priv_scope, ID_NEVER, caller_name => C_LOCAL_CALL);
bin_vector(i).cross_bins(j).num_values := v_num_values;
for k in 0 to v_num_values-1 loop
read(v_line, bin_vector(i).cross_bins(j).values(k));
end loop;
end loop;
end loop;
end procedure;
begin
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
file_open(v_open_status, file_handler, file_name, read_mode);
if v_open_status /= open_ok then
alert(TB_WARNING, C_LOCAL_CALL & "=> Cannot open file: " & file_name, priv_scope);
return;
end if;
-- Add coverpoint to covergroup status register
if priv_id = C_DEALLOCATED_ID then
priv_id := protected_covergroup_status.add_coverpoint(VOID);
check_value(priv_id /= C_DEALLOCATED_ID, TB_FAILURE, "Number of coverpoints exceeds C_FC_MAX_NUM_COVERPOINTS.\n Increase C_FC_MAX_NUM_COVERPOINTS in adaptations package.",
priv_scope, ID_NEVER, caller_name => C_LOCAL_CALL);
else
alert(TB_WARNING, C_LOCAL_CALL & "=> " & to_string(priv_name) & " will be overwritten.", priv_scope);
end if;
-- Coverpoint config
read_value(priv_name); -- read() crops the string
set_name(priv_name);
read_value(priv_scope); -- read() crops the string
set_scope(priv_scope);
read_value(priv_num_bins_crossed);
check_value(priv_num_bins_crossed <= C_MAX_NUM_CROSS_BINS, TB_FAILURE, "Cannot load the " & to_string(priv_num_bins_crossed) & " crossed bins. Increase C_MAX_NUM_CROSS_BINS",
priv_scope, ID_NEVER, caller_name => C_LOCAL_CALL);
read_value(v_rand_seeds);
priv_rand_gen.set_rand_seeds(t_positive_vector(v_rand_seeds));
read_value(priv_rand_transition_bin_idx);
read_value(v_rand_transition_bin_value_idx);
priv_rand_transition_bin_value_idx := t_natural_vector(v_rand_transition_bin_value_idx);
for i in 0 to priv_num_bins_crossed-1 loop
read_value(priv_bin_sample_shift_reg(i));
end loop;
read_value(v_value);
priv_illegal_bin_alert_level := t_alert_level'val(v_value);
read_value(v_value);
priv_bin_overlap_alert_level := t_alert_level'val(v_value);
-- Covergroup config
protected_covergroup_status.set_name(priv_id, priv_name); -- Previously read from the file
read_value(v_value);
protected_covergroup_status.set_num_valid_bins(priv_id, v_value);
read_value(v_value);
protected_covergroup_status.set_num_covered_bins(priv_id, v_value);
read_value(v_value);
protected_covergroup_status.set_total_bin_min_hits(priv_id, v_value);
read_value(v_value);
protected_covergroup_status.set_total_bin_hits(priv_id, v_value);
read_value(v_value);
protected_covergroup_status.set_total_coverage_bin_hits(priv_id, v_value);
read_value(v_value);
protected_covergroup_status.set_total_goal_bin_hits(priv_id, v_value);
read_value(v_value);
protected_covergroup_status.set_coverage_weight(priv_id, v_value);
read_value(v_value);
protected_covergroup_status.set_bins_coverage_goal(priv_id, v_value);
read_value(v_value);
protected_covergroup_status.set_hits_coverage_goal(priv_id, v_value);
read_value(v_value);
protected_covergroup_status.set_covpts_coverage_goal(v_value);
-- Bin structure
read_value(priv_bins_idx);
read_bins(priv_bins_idx, priv_bins);
read_value(priv_invalid_bins_idx);
read_bins(priv_invalid_bins_idx, priv_invalid_bins);
file_close(file_handler);
DEALLOCATE(v_line);
report_coverage(report_verbosity);
end procedure;
procedure clear_coverage(
constant VOID : in t_void) is
begin
clear_coverage(shared_msg_id_panel);
end procedure;
procedure clear_coverage(
constant msg_id_panel : in t_msg_id_panel) is
constant C_LOCAL_CALL : string := "clear_coverage()";
begin
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
for i in 0 to priv_bins_idx-1 loop
priv_bins(i).hits := 0;
priv_bins(i).transition_mask := (others => '0');
end loop;
for i in 0 to priv_invalid_bins_idx-1 loop
priv_invalid_bins(i).hits := 0;
priv_invalid_bins(i).transition_mask := (others => '0');
end loop;
priv_rand_transition_bin_idx := C_UNINITIALIZED;
priv_rand_transition_bin_value_idx := (others => 0);
priv_bin_sample_shift_reg := (others => (others => 0));
if priv_id /= C_DEALLOCATED_ID then
protected_covergroup_status.set_num_covered_bins(priv_id, 0);
protected_covergroup_status.set_total_coverage_bin_hits(priv_id, 0);
protected_covergroup_status.set_total_goal_bin_hits(priv_id, 0);
protected_covergroup_status.set_total_bin_hits(priv_id, 0);
end if;
end procedure;
procedure set_num_allocated_bins(
constant value : in positive;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "set_num_allocated_bins(" & to_string(value) & ")";
begin
initialize_coverpoint(C_LOCAL_CALL);
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
if value >= priv_bins_idx then
resize_bin_vector(priv_bins, value);
else
alert(TB_ERROR, C_LOCAL_CALL & "=> Cannot set the allocated size to a value smaller than the actual number of bins", priv_scope);
end if;
end procedure;
procedure set_num_allocated_bins_increment(
constant value : in positive) is
begin
priv_num_bins_allocated_increment := value;
end procedure;
procedure delete_coverpoint(
constant VOID : in t_void) is
begin
delete_coverpoint(shared_msg_id_panel);
end procedure;
procedure delete_coverpoint(
constant msg_id_panel : in t_msg_id_panel) is
constant C_LOCAL_CALL : string := "delete_coverpoint()";
begin
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
if priv_id /= C_DEALLOCATED_ID then
protected_covergroup_status.remove_coverpoint(priv_id);
end if;
priv_id := C_DEALLOCATED_ID;
priv_name := fill_string(NUL, C_FC_MAX_NAME_LENGTH);
priv_scope := C_TB_SCOPE_DEFAULT & fill_string(NUL, C_LOG_SCOPE_WIDTH-C_TB_SCOPE_DEFAULT'length);
DEALLOCATE(priv_bins);
priv_bins := new t_cov_bin_vector(0 to C_FC_DEFAULT_INITIAL_NUM_BINS_ALLOCATED-1);
priv_bins_idx := 0;
DEALLOCATE(priv_invalid_bins);
priv_invalid_bins := new t_cov_bin_vector(0 to C_FC_DEFAULT_INITIAL_NUM_BINS_ALLOCATED-1);
priv_invalid_bins_idx := 0;
priv_num_bins_crossed := C_UNINITIALIZED;
priv_rand_gen.set_rand_seeds(C_RAND_INIT_SEED_1, C_RAND_INIT_SEED_2);
priv_rand_transition_bin_idx := C_UNINITIALIZED;
priv_rand_transition_bin_value_idx := (others => 0);
priv_bin_sample_shift_reg := (others => (others => 0));
priv_illegal_bin_alert_level := ERROR;
priv_bin_overlap_alert_level := NO_ALERT;
priv_num_bins_allocated_increment := C_FC_DEFAULT_NUM_BINS_ALLOCATED_INCREMENT;
end procedure;
-- Returns the number of bins crossed in the coverpoint
impure function get_num_bins_crossed(
constant VOID : t_void)
return integer is
begin
return priv_num_bins_crossed;
end function;
-- Returns the number of valid bins in the coverpoint
impure function get_num_valid_bins(
constant VOID : t_void)
return natural is
begin
return priv_bins_idx;
end function;
-- Returns the number of illegal and ignore bins in the coverpoint
impure function get_num_invalid_bins(
constant VOID : t_void)
return natural is
begin
return priv_invalid_bins_idx;
end function;
-- Returns a valid bin in the coverpoint
impure function get_valid_bin(
constant bin_idx : natural)
return t_cov_bin is
constant C_LOCAL_CALL : string := "get_valid_bin(" & to_string(bin_idx) & ")";
begin
check_value(bin_idx < priv_bins'length, TB_ERROR, "bin_idx is out of range", priv_scope, ID_NEVER, caller_name => C_LOCAL_CALL);
return priv_bins(bin_idx);
end function;
-- Returns an invalid bin in the coverpoint
impure function get_invalid_bin(
constant bin_idx : natural)
return t_cov_bin is
constant C_LOCAL_CALL : string := "get_invalid_bin(" & to_string(bin_idx) & ")";
begin
check_value(bin_idx < priv_invalid_bins'length, TB_ERROR, "bin_idx is out of range", priv_scope, ID_NEVER, caller_name => C_LOCAL_CALL);
return priv_invalid_bins(bin_idx);
end function;
-- Returns a vector with the valid bins in the coverpoint
impure function get_valid_bins(
constant VOID : t_void)
return t_cov_bin_vector is
begin
return priv_bins(0 to priv_bins_idx-1);
end function;
-- Returns a vector with the illegal and ignore bins in the coverpoint
impure function get_invalid_bins(
constant VOID : t_void)
return t_cov_bin_vector is
begin
return priv_invalid_bins(0 to priv_invalid_bins_idx-1);
end function;
-- Returns a string with all the bins in the coverpoint including illegal, ignore and cross
-- Duplicate bins are not printed since they are assumed to be the result of a cross
impure function get_all_bins_string(
constant VOID : t_void)
return string is
variable v_new_bin_array : t_new_bin_array(0 to priv_num_bins_crossed-1);
variable v_line : line;
variable v_num_bins : natural := 0;
impure function return_and_deallocate return string is
constant ret : string := v_line.all;
begin
DEALLOCATE(v_line);
return ret;
end function;
begin
if priv_bins_idx = 0 and priv_invalid_bins_idx = 0 then
return "";
end if;
for cross in v_new_bin_array'range loop
for i in 0 to priv_bins_idx-1 loop
if not find_duplicate_bin(priv_bins.all, i, cross) then
v_new_bin_array(cross).bin_vector(v_num_bins).contains := priv_bins(i).cross_bins(cross).contains;
v_new_bin_array(cross).bin_vector(v_num_bins).values := priv_bins(i).cross_bins(cross).values;
v_new_bin_array(cross).bin_vector(v_num_bins).num_values := priv_bins(i).cross_bins(cross).num_values;
v_num_bins := v_num_bins + 1;
end if;
end loop;
for i in 0 to priv_invalid_bins_idx-1 loop
if not find_duplicate_bin(priv_invalid_bins.all, i, cross) then
v_new_bin_array(cross).bin_vector(v_num_bins).contains := priv_invalid_bins(i).cross_bins(cross).contains;
v_new_bin_array(cross).bin_vector(v_num_bins).values := priv_invalid_bins(i).cross_bins(cross).values;
v_new_bin_array(cross).bin_vector(v_num_bins).num_values := priv_invalid_bins(i).cross_bins(cross).num_values;
v_num_bins := v_num_bins + 1;
end if;
end loop;
v_new_bin_array(cross).num_bins := v_num_bins;
v_num_bins := 0;
write(v_line, get_bin_array_values(v_new_bin_array(cross to cross)));
if cross < v_new_bin_array'length-1 then
write(v_line, string'(" x "));
end if;
end loop;
return return_and_deallocate;
end function;
------------------------------------------------------------
-- Add bins
------------------------------------------------------------
procedure add_bins(
constant bin : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "add_bins(" & get_proc_calls(bin) & ", min_hits:" & to_string(min_hits) &
", rand_weight:" & to_string(rand_weight) & ", """ & bin_name & """)";
constant C_NUM_CROSS_BINS : natural := 1;
constant C_USE_RAND_WEIGHT : boolean := ext_proc_call = ""; -- When procedure is called from the sequencer
variable v_proc_call : line;
variable v_bin_array : t_new_bin_array(0 to C_NUM_CROSS_BINS-1);
variable v_idx_reg : integer_vector(0 to C_NUM_CROSS_BINS-1);
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
check_num_bins_crossed(C_NUM_CROSS_BINS, v_proc_call.all);
log(ID_FUNC_COV_BINS, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
log(ID_FUNC_COV_BINS_INFO, get_name_prefix(VOID) & "Adding bins: " & get_bin_array_values(bin) & ", min_hits:" & to_string(min_hits) &
", rand_weight:" & return_string1_if_true_otherwise_string2(to_string(rand_weight), to_string(min_hits), C_USE_RAND_WEIGHT) &
", """ & bin_name & """", priv_scope, msg_id_panel);
-- Copy the bins into an array and use a recursive procedure to add them to the list
create_bin_array(v_proc_call.all, v_bin_array, bin);
add_bins_recursive(v_bin_array, 0, v_idx_reg, min_hits, rand_weight, C_USE_RAND_WEIGHT, bin_name);
DEALLOCATE(v_proc_call);
end procedure;
procedure add_bins(
constant bin : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_bins(" & get_proc_calls(bin) & ", min_hits:" & to_string(min_hits) &
", """ & bin_name & """)";
begin
add_bins(bin, min_hits, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure add_bins(
constant bin : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_bins(" & get_proc_calls(bin) & ", """ & bin_name & """)";
begin
add_bins(bin, 1, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
------------------------------------------------------------
-- Add cross (2 bins)
------------------------------------------------------------
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & to_string(rand_weight) & ", """ & bin_name & """)";
constant C_NUM_CROSS_BINS : natural := 2;
constant C_USE_RAND_WEIGHT : boolean := ext_proc_call = ""; -- When procedure is called from the sequencer
variable v_proc_call : line;
variable v_bin_array : t_new_bin_array(0 to C_NUM_CROSS_BINS-1);
variable v_idx_reg : integer_vector(0 to C_NUM_CROSS_BINS-1);
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
check_num_bins_crossed(C_NUM_CROSS_BINS, v_proc_call.all);
log(ID_FUNC_COV_BINS, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
log(ID_FUNC_COV_BINS_INFO, get_name_prefix(VOID) & "Adding cross: " & get_bin_array_values(bin1) & " x " & get_bin_array_values(bin2) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & return_string1_if_true_otherwise_string2(to_string(rand_weight), to_string(min_hits), C_USE_RAND_WEIGHT) &
", """ & bin_name & """", priv_scope, msg_id_panel);
-- Copy the bins into an array and use a recursive procedure to add them to the list
create_bin_array(v_proc_call.all, v_bin_array, bin1, bin2);
add_bins_recursive(v_bin_array, 0, v_idx_reg, min_hits, rand_weight, C_USE_RAND_WEIGHT, bin_name);
DEALLOCATE(v_proc_call);
end procedure;
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) &
", min_hits:" & to_string(min_hits) & ", """ & bin_name & """)";
begin
add_cross(bin1, bin2, min_hits, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) &
", """ & bin_name & """)";
begin
add_cross(bin1, bin2, 1, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
------------------------------------------------------------
-- Add cross (3 bins)
------------------------------------------------------------
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) & ", " & get_proc_calls(bin3) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & to_string(rand_weight) & ", """ & bin_name & """)";
constant C_NUM_CROSS_BINS : natural := 3;
constant C_USE_RAND_WEIGHT : boolean := ext_proc_call = ""; -- When procedure is called from the sequencer
variable v_proc_call : line;
variable v_bin_array : t_new_bin_array(0 to C_NUM_CROSS_BINS-1);
variable v_idx_reg : integer_vector(0 to C_NUM_CROSS_BINS-1);
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
check_num_bins_crossed(C_NUM_CROSS_BINS, v_proc_call.all);
log(ID_FUNC_COV_BINS, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
log(ID_FUNC_COV_BINS_INFO, get_name_prefix(VOID) & "Adding cross: " & get_bin_array_values(bin1) & " x " & get_bin_array_values(bin2) & " x " & get_bin_array_values(bin3) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & return_string1_if_true_otherwise_string2(to_string(rand_weight), to_string(min_hits), C_USE_RAND_WEIGHT) &
", """ & bin_name & """", priv_scope, msg_id_panel);
-- Copy the bins into an array and use a recursive procedure to add them to the list
create_bin_array(v_proc_call.all, v_bin_array, bin1, bin2, bin3);
add_bins_recursive(v_bin_array, 0, v_idx_reg, min_hits, rand_weight, C_USE_RAND_WEIGHT, bin_name);
DEALLOCATE(v_proc_call);
end procedure;
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) & ", " & get_proc_calls(bin3) &
", min_hits:" & to_string(min_hits) & ", """ & bin_name & """)";
begin
add_cross(bin1, bin2, bin3, min_hits, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) & ", " & get_proc_calls(bin3) &
", """ & bin_name & """)";
begin
add_cross(bin1, bin2, bin3, 1, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
------------------------------------------------------------
-- Add cross (4 bins)
------------------------------------------------------------
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) & ", " & get_proc_calls(bin3) &
", " & get_proc_calls(bin4) & ", min_hits:" & to_string(min_hits) & ", rand_weight:" & to_string(rand_weight) & ", """ & bin_name & """)";
constant C_NUM_CROSS_BINS : natural := 4;
constant C_USE_RAND_WEIGHT : boolean := ext_proc_call = ""; -- When procedure is called from the sequencer
variable v_proc_call : line;
variable v_bin_array : t_new_bin_array(0 to C_NUM_CROSS_BINS-1);
variable v_idx_reg : integer_vector(0 to C_NUM_CROSS_BINS-1);
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
check_num_bins_crossed(C_NUM_CROSS_BINS, v_proc_call.all);
log(ID_FUNC_COV_BINS, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
log(ID_FUNC_COV_BINS_INFO, get_name_prefix(VOID) & "Adding cross: " & get_bin_array_values(bin1) & " x " & get_bin_array_values(bin2) & " x " & get_bin_array_values(bin3) &
" x " & get_bin_array_values(bin4) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & return_string1_if_true_otherwise_string2(to_string(rand_weight), to_string(min_hits), C_USE_RAND_WEIGHT) &
", """ & bin_name & """", priv_scope, msg_id_panel);
-- Copy the bins into an array and use a recursive procedure to add them to the list
create_bin_array(v_proc_call.all, v_bin_array, bin1, bin2, bin3, bin4);
add_bins_recursive(v_bin_array, 0, v_idx_reg, min_hits, rand_weight, C_USE_RAND_WEIGHT, bin_name);
DEALLOCATE(v_proc_call);
end procedure;
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) & ", " & get_proc_calls(bin3) &
", " & get_proc_calls(bin4) & ", min_hits:" & to_string(min_hits) & ", """ & bin_name & """)";
begin
add_cross(bin1, bin2, bin3, bin4, min_hits, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) & ", " & get_proc_calls(bin3) &
", " & get_proc_calls(bin4) & ", """ & bin_name & """)";
begin
add_cross(bin1, bin2, bin3, bin4, 1, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
------------------------------------------------------------
-- Add cross (5 bins)
------------------------------------------------------------
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant bin5 : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) & ", " & get_proc_calls(bin3) &
", " & get_proc_calls(bin4) & ", " & get_proc_calls(bin5) & ", min_hits:" & to_string(min_hits) & ", rand_weight:" & to_string(rand_weight) & ", """ & bin_name & """)";
constant C_NUM_CROSS_BINS : natural := 5;
constant C_USE_RAND_WEIGHT : boolean := ext_proc_call = ""; -- When procedure is called from the sequencer
variable v_proc_call : line;
variable v_bin_array : t_new_bin_array(0 to C_NUM_CROSS_BINS-1);
variable v_idx_reg : integer_vector(0 to C_NUM_CROSS_BINS-1);
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
check_num_bins_crossed(C_NUM_CROSS_BINS, v_proc_call.all);
log(ID_FUNC_COV_BINS, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
log(ID_FUNC_COV_BINS_INFO, get_name_prefix(VOID) & "Adding cross: " & get_bin_array_values(bin1) & " x " & get_bin_array_values(bin2) & " x " & get_bin_array_values(bin3) &
" x " & get_bin_array_values(bin4) & " x " & get_bin_array_values(bin5) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & return_string1_if_true_otherwise_string2(to_string(rand_weight), to_string(min_hits), C_USE_RAND_WEIGHT) &
", """ & bin_name & """", priv_scope, msg_id_panel);
-- Copy the bins into an array and use a recursive procedure to add them to the list
create_bin_array(v_proc_call.all, v_bin_array, bin1, bin2, bin3, bin4, bin5);
add_bins_recursive(v_bin_array, 0, v_idx_reg, min_hits, rand_weight, C_USE_RAND_WEIGHT, bin_name);
DEALLOCATE(v_proc_call);
end procedure;
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant bin5 : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) & ", " & get_proc_calls(bin3) &
", " & get_proc_calls(bin4) & ", " & get_proc_calls(bin5) & ", min_hits:" & to_string(min_hits) & ", """ & bin_name & """)";
begin
add_cross(bin1, bin2, bin3, bin4, bin5, min_hits, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant bin5 : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) & ", " & get_proc_calls(bin3) &
", " & get_proc_calls(bin4) & ", " & get_proc_calls(bin5) & ", """ & bin_name & """)";
begin
add_cross(bin1, bin2, bin3, bin4, bin5, 1, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
------------------------------------------------------------
-- Add cross (2 coverpoints)
------------------------------------------------------------
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & to_string(rand_weight) & ", """ & bin_name & """)";
constant C_NUM_CROSS_BINS : integer := coverpoint1.get_num_bins_crossed(VOID) + coverpoint2.get_num_bins_crossed(VOID);
constant C_USE_RAND_WEIGHT : boolean := ext_proc_call = ""; -- When procedure is called from the sequencer
variable v_proc_call : line;
variable v_bin_array : t_new_bin_array(0 to C_NUM_CROSS_BINS-1);
variable v_idx_reg : integer_vector(0 to C_NUM_CROSS_BINS-1);
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
check_num_bins_crossed(C_NUM_CROSS_BINS, v_proc_call.all, coverpoint1.get_num_bins_crossed(VOID), coverpoint2.get_num_bins_crossed(VOID));
log(ID_FUNC_COV_BINS, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
log(ID_FUNC_COV_BINS_INFO, get_name_prefix(VOID) & "Adding cross: " & coverpoint1.get_all_bins_string(VOID) & " x " & coverpoint2.get_all_bins_string(VOID) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & return_string1_if_true_otherwise_string2(to_string(rand_weight), to_string(min_hits), C_USE_RAND_WEIGHT) &
", """ & bin_name & """", priv_scope, msg_id_panel);
-- Copy the bins into an array and use a recursive procedure to add them to the list
create_bin_array(v_bin_array, coverpoint1, coverpoint2);
add_bins_recursive(v_bin_array, 0, v_idx_reg, min_hits, rand_weight, C_USE_RAND_WEIGHT, bin_name);
DEALLOCATE(v_proc_call);
end procedure;
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) &
", min_hits:" & to_string(min_hits) & ", """ & bin_name & """)";
begin
add_cross(coverpoint1, coverpoint2, min_hits, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) &
", """ & bin_name & """)";
begin
add_cross(coverpoint1, coverpoint2, 1, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
------------------------------------------------------------
-- Add cross (3 coverpoints)
------------------------------------------------------------
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) & ", " &
coverpoint3.get_name(VOID) & ", min_hits:" & to_string(min_hits) & ", rand_weight:" & to_string(rand_weight) & ", """ & bin_name & """)";
constant C_NUM_CROSS_BINS : integer := coverpoint1.get_num_bins_crossed(VOID) + coverpoint2.get_num_bins_crossed(VOID) +
coverpoint3.get_num_bins_crossed(VOID);
constant C_USE_RAND_WEIGHT : boolean := ext_proc_call = ""; -- When procedure is called from the sequencer
variable v_proc_call : line;
variable v_bin_array : t_new_bin_array(0 to C_NUM_CROSS_BINS-1);
variable v_idx_reg : integer_vector(0 to C_NUM_CROSS_BINS-1);
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
check_num_bins_crossed(C_NUM_CROSS_BINS, v_proc_call.all, coverpoint1.get_num_bins_crossed(VOID), coverpoint2.get_num_bins_crossed(VOID),
coverpoint3.get_num_bins_crossed(VOID));
log(ID_FUNC_COV_BINS, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
log(ID_FUNC_COV_BINS_INFO, get_name_prefix(VOID) & "Adding cross: " & coverpoint1.get_all_bins_string(VOID) & " x " & coverpoint2.get_all_bins_string(VOID) &
" x " & coverpoint3.get_all_bins_string(VOID) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & return_string1_if_true_otherwise_string2(to_string(rand_weight), to_string(min_hits), C_USE_RAND_WEIGHT) &
", """ & bin_name & """", priv_scope, msg_id_panel);
-- Copy the bins into an array and use a recursive procedure to add them to the list
create_bin_array(v_bin_array, coverpoint1, coverpoint2, coverpoint3);
add_bins_recursive(v_bin_array, 0, v_idx_reg, min_hits, rand_weight, C_USE_RAND_WEIGHT, bin_name);
DEALLOCATE(v_proc_call);
end procedure;
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) & ", " &
coverpoint3.get_name(VOID) & ", min_hits:" & to_string(min_hits) & ", """ & bin_name & """)";
begin
add_cross(coverpoint1, coverpoint2, coverpoint3, min_hits, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) & ", " &
coverpoint3.get_name(VOID) & ", """ & bin_name & """)";
begin
add_cross(coverpoint1, coverpoint2, coverpoint3, 1, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
------------------------------------------------------------
-- Add cross (4 coverpoints)
------------------------------------------------------------
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) & ", " &
coverpoint3.get_name(VOID) & ", " & coverpoint4.get_name(VOID) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & to_string(rand_weight) & ", """ & bin_name & """)";
constant C_NUM_CROSS_BINS : integer := coverpoint1.get_num_bins_crossed(VOID) + coverpoint2.get_num_bins_crossed(VOID) +
coverpoint3.get_num_bins_crossed(VOID) + coverpoint4.get_num_bins_crossed(VOID);
constant C_USE_RAND_WEIGHT : boolean := ext_proc_call = ""; -- When procedure is called from the sequencer
variable v_proc_call : line;
variable v_bin_array : t_new_bin_array(0 to C_NUM_CROSS_BINS-1);
variable v_idx_reg : integer_vector(0 to C_NUM_CROSS_BINS-1);
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
check_num_bins_crossed(C_NUM_CROSS_BINS, v_proc_call.all, coverpoint1.get_num_bins_crossed(VOID), coverpoint2.get_num_bins_crossed(VOID),
coverpoint3.get_num_bins_crossed(VOID), coverpoint4.get_num_bins_crossed(VOID));
log(ID_FUNC_COV_BINS, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
log(ID_FUNC_COV_BINS_INFO, get_name_prefix(VOID) & "Adding cross: " & coverpoint1.get_all_bins_string(VOID) & " x " & coverpoint2.get_all_bins_string(VOID) &
" x " & coverpoint3.get_all_bins_string(VOID) & " x " & coverpoint4.get_all_bins_string(VOID) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & return_string1_if_true_otherwise_string2(to_string(rand_weight), to_string(min_hits), C_USE_RAND_WEIGHT) &
", """ & bin_name & """", priv_scope, msg_id_panel);
-- Copy the bins into an array and use a recursive procedure to add them to the list
create_bin_array(v_bin_array, coverpoint1, coverpoint2, coverpoint3, coverpoint4);
add_bins_recursive(v_bin_array, 0, v_idx_reg, min_hits, rand_weight, C_USE_RAND_WEIGHT, bin_name);
DEALLOCATE(v_proc_call);
end procedure;
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) & ", " &
coverpoint3.get_name(VOID) & ", " & coverpoint4.get_name(VOID) & ", min_hits:" & to_string(min_hits) & ", """ & bin_name & """)";
begin
add_cross(coverpoint1, coverpoint2, coverpoint3, coverpoint4, min_hits, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) & ", " &
coverpoint3.get_name(VOID) & ", " & coverpoint4.get_name(VOID) & ", """ & bin_name & """)";
begin
add_cross(coverpoint1, coverpoint2, coverpoint3, coverpoint4, 1, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
------------------------------------------------------------
-- Add cross (5 coverpoints)
------------------------------------------------------------
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
variable coverpoint5 : inout t_coverpoint;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) & ", " &
coverpoint3.get_name(VOID) & ", " & coverpoint4.get_name(VOID) & ", " & coverpoint5.get_name(VOID) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & to_string(rand_weight) & ", """ & bin_name & """)";
constant C_NUM_CROSS_BINS : integer := coverpoint1.get_num_bins_crossed(VOID) + coverpoint2.get_num_bins_crossed(VOID) +
coverpoint3.get_num_bins_crossed(VOID) + coverpoint4.get_num_bins_crossed(VOID) + coverpoint5.get_num_bins_crossed(VOID);
constant C_USE_RAND_WEIGHT : boolean := ext_proc_call = ""; -- When procedure is called from the sequencer
variable v_proc_call : line;
variable v_bin_array : t_new_bin_array(0 to C_NUM_CROSS_BINS-1);
variable v_idx_reg : integer_vector(0 to C_NUM_CROSS_BINS-1);
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
check_num_bins_crossed(C_NUM_CROSS_BINS, v_proc_call.all, coverpoint1.get_num_bins_crossed(VOID), coverpoint2.get_num_bins_crossed(VOID),
coverpoint3.get_num_bins_crossed(VOID), coverpoint4.get_num_bins_crossed(VOID), coverpoint5.get_num_bins_crossed(VOID));
log(ID_FUNC_COV_BINS, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
log(ID_FUNC_COV_BINS_INFO, get_name_prefix(VOID) & "Adding cross: " & coverpoint1.get_all_bins_string(VOID) & " x " & coverpoint2.get_all_bins_string(VOID) &
" x " & coverpoint3.get_all_bins_string(VOID) & " x " & coverpoint4.get_all_bins_string(VOID) & " x " & coverpoint5.get_all_bins_string(VOID) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & return_string1_if_true_otherwise_string2(to_string(rand_weight), to_string(min_hits), C_USE_RAND_WEIGHT) &
", """ & bin_name & """", priv_scope, msg_id_panel);
-- Copy the bins into an array and use a recursive procedure to add them to the list
create_bin_array(v_bin_array, coverpoint1, coverpoint2, coverpoint3, coverpoint4, coverpoint5);
add_bins_recursive(v_bin_array, 0, v_idx_reg, min_hits, rand_weight, C_USE_RAND_WEIGHT, bin_name);
DEALLOCATE(v_proc_call);
end procedure;
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
variable coverpoint5 : inout t_coverpoint;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) & ", " &
coverpoint3.get_name(VOID) & ", " & coverpoint4.get_name(VOID) & ", " & coverpoint5.get_name(VOID) &
", min_hits:" & to_string(min_hits) &", """ & bin_name & """)";
begin
add_cross(coverpoint1, coverpoint2, coverpoint3, coverpoint4, coverpoint5, min_hits, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
variable coverpoint5 : inout t_coverpoint;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) & ", " &
coverpoint3.get_name(VOID) & ", " & coverpoint4.get_name(VOID) & ", " & coverpoint5.get_name(VOID) & ", """ & bin_name & """)";
begin
add_cross(coverpoint1, coverpoint2, coverpoint3, coverpoint4, coverpoint5, 1, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
------------------------------------------------------------
-- Coverage
------------------------------------------------------------
impure function is_defined(
constant VOID : t_void)
return boolean is
begin
return priv_num_bins_crossed /= C_UNINITIALIZED;
end function;
procedure sample_coverage(
constant value : in integer;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "sample_coverage(" & to_string(value) & ")";
variable v_values : integer_vector(0 to 0) := (0 => value);
begin
log(ID_FUNC_COV_SAMPLE, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
sample_coverage(v_values, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure sample_coverage(
constant values : in integer_vector;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "sample_coverage(" & to_string(values) & ")";
variable v_proc_call : line;
variable v_invalid_sample : boolean := false;
variable v_value_match : std_logic_vector(0 to priv_num_bins_crossed-1) := (others => '0');
variable v_illegal_match_idx : integer := -1;
variable v_num_occurrences : natural := 0;
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
if priv_num_bins_crossed = C_UNINITIALIZED then
alert(TB_ERROR, v_proc_call.all & "=> Coverpoint does not contain any bins", priv_scope);
DEALLOCATE(v_proc_call);
return;
end if;
if ext_proc_call = "" then -- Do not print log message when being called from another method
log(ID_FUNC_COV_SAMPLE, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
end if;
if priv_num_bins_crossed /= values'length then
alert(TB_FAILURE, v_proc_call.all & "=> Number of values does not match the number of crossed bins", priv_scope);
end if;
-- Shift register used to check transition bins
for i in 0 to priv_num_bins_crossed-1 loop
priv_bin_sample_shift_reg(i) := priv_bin_sample_shift_reg(i)(priv_bin_sample_shift_reg(0)'length-2 downto 0) & values(i);
end loop;
-- Check if the values should be ignored or are illegal
for i in 0 to priv_invalid_bins_idx-1 loop
priv_invalid_bins(i).transition_mask := priv_invalid_bins(i).transition_mask(priv_invalid_bins(i).transition_mask'length-2 downto 0) & '1';
for j in 0 to priv_num_bins_crossed-1 loop
case priv_invalid_bins(i).cross_bins(j).contains is
when VAL | VAL_IGNORE | VAL_ILLEGAL =>
for k in 0 to priv_invalid_bins(i).cross_bins(j).num_values-1 loop
if values(j) = priv_invalid_bins(i).cross_bins(j).values(k) then
v_value_match(j) := '1';
v_illegal_match_idx := j when priv_invalid_bins(i).cross_bins(j).contains = VAL_ILLEGAL;
end if;
end loop;
when RAN | RAN_IGNORE | RAN_ILLEGAL =>
if values(j) >= priv_invalid_bins(i).cross_bins(j).values(0) and values(j) <= priv_invalid_bins(i).cross_bins(j).values(1) then
v_value_match(j) := '1';
v_illegal_match_idx := j when priv_invalid_bins(i).cross_bins(j).contains = RAN_ILLEGAL;
end if;
when TRN | TRN_IGNORE | TRN_ILLEGAL =>
-- Check if there are enough valid values in the shift register to compare the transition
if priv_invalid_bins(i).transition_mask(priv_invalid_bins(i).cross_bins(j).num_values-1) = '1' and
priv_bin_sample_shift_reg(j)(priv_invalid_bins(i).cross_bins(j).num_values-1 downto 0) = priv_invalid_bins(i).cross_bins(j).values(0 to priv_invalid_bins(i).cross_bins(j).num_values-1)
then
v_value_match(j) := '1';
v_illegal_match_idx := j when priv_invalid_bins(i).cross_bins(j).contains = TRN_ILLEGAL;
end if;
when others =>
alert(TB_FAILURE, v_proc_call.all & "=> Unexpected error, invalid bin contains " & to_upper(to_string(priv_invalid_bins(i).cross_bins(j).contains)), priv_scope);
end case;
end loop;
if and(v_value_match) = '1' then
v_invalid_sample := true;
priv_invalid_bins(i).transition_mask := (others => '0');
priv_invalid_bins(i).hits := priv_invalid_bins(i).hits + 1;
if v_illegal_match_idx /= -1 then
alert(priv_illegal_bin_alert_level, get_name_prefix(VOID) & v_proc_call.all & "=> Sampled " & get_bin_info(priv_invalid_bins(i).cross_bins(v_illegal_match_idx)), priv_scope);
end if;
end if;
v_value_match := (others => '0');
v_illegal_match_idx := -1;
end loop;
-- Check if the values are in the valid bins
if not(v_invalid_sample) then
for i in 0 to priv_bins_idx-1 loop
priv_bins(i).transition_mask := priv_bins(i).transition_mask(priv_bins(i).transition_mask'length-2 downto 0) & '1';
for j in 0 to priv_num_bins_crossed-1 loop
case priv_bins(i).cross_bins(j).contains is
when VAL =>
for k in 0 to priv_bins(i).cross_bins(j).num_values-1 loop
if values(j) = priv_bins(i).cross_bins(j).values(k) then
v_value_match(j) := '1';
end if;
end loop;
when RAN =>
if values(j) >= priv_bins(i).cross_bins(j).values(0) and values(j) <= priv_bins(i).cross_bins(j).values(1) then
v_value_match(j) := '1';
end if;
when TRN =>
-- Check if there are enough valid values in the shift register to compare the transition
if priv_bins(i).transition_mask(priv_bins(i).cross_bins(j).num_values-1) = '1' and
priv_bin_sample_shift_reg(j)(priv_bins(i).cross_bins(j).num_values-1 downto 0) = priv_bins(i).cross_bins(j).values(0 to priv_bins(i).cross_bins(j).num_values-1)
then
v_value_match(j) := '1';
end if;
when others =>
alert(TB_FAILURE, v_proc_call.all & "=> Unexpected error, valid bin contains " & to_upper(to_string(priv_bins(i).cross_bins(j).contains)), priv_scope);
end case;
end loop;
if and(v_value_match) = '1' then
priv_bins(i).transition_mask := (others => '0');
priv_bins(i).hits := priv_bins(i).hits + 1;
v_num_occurrences := v_num_occurrences + 1;
-- Update covergroup status register
protected_covergroup_status.increment_hits_count(priv_id); -- Count the total hits
if priv_bins(i).hits <= priv_bins(i).min_hits then
protected_covergroup_status.increment_coverage_hits_count(priv_id); -- Count until min_hits has been reached
end if;
if priv_bins(i).hits <= get_total_min_hits(priv_bins(i).min_hits) then
protected_covergroup_status.increment_goal_hits_count(priv_id); -- Count until min_hits x goal has been reached
end if;
if priv_bins(i).hits = priv_bins(i).min_hits and priv_bins(i).min_hits /= 0 then
protected_covergroup_status.increment_covered_bin_count(priv_id); -- Count the covered bins
end if;
end if;
v_value_match := (others => '0');
end loop;
if v_num_occurrences > 1 then
alert(priv_bin_overlap_alert_level, get_name_prefix(VOID) & "There is an overlap between " & to_string(v_num_occurrences) & " bins.", priv_scope);
end if;
else
-- When an ignore or illegal bin is sampled, valid bins won't be sampled so we need to clear all transition masks in the valid bins
for i in 0 to priv_bins_idx-1 loop
priv_bins(i).transition_mask := (others => '0');
end loop;
end if;
DEALLOCATE(v_proc_call);
end procedure;
impure function get_coverage(
constant coverage_type : t_coverage_type;
constant percentage_of_goal : boolean := false)
return real is
constant C_LOCAL_CALL : string := "get_coverage(" & to_upper(to_string(coverage_type)) & ")";
variable v_coverage_representation : t_coverage_representation;
begin
if priv_id /= C_DEALLOCATED_ID then
v_coverage_representation := GOAL_CAPPED when percentage_of_goal else NO_GOAL;
if coverage_type = BINS then
return protected_covergroup_status.get_bins_coverage(priv_id, v_coverage_representation);
elsif coverage_type = HITS then
return protected_covergroup_status.get_hits_coverage(priv_id, v_coverage_representation);
else -- BINS_AND_HITS
alert(TB_ERROR, C_LOCAL_CALL & "=> Use either BINS or HITS.", priv_scope);
return 0.0;
end if;
else
return 0.0;
end if;
end function;
impure function coverage_completed(
constant coverage_type : t_coverage_type)
return boolean is
begin
if priv_id /= C_DEALLOCATED_ID then
if coverage_type = BINS then
return protected_covergroup_status.get_bins_coverage(priv_id, GOAL_CAPPED) = 100.0;
elsif coverage_type = HITS then
return protected_covergroup_status.get_hits_coverage(priv_id, GOAL_CAPPED) = 100.0;
else -- BINS_AND_HITS
return protected_covergroup_status.get_bins_coverage(priv_id, GOAL_CAPPED) = 100.0 and
protected_covergroup_status.get_hits_coverage(priv_id, GOAL_CAPPED) = 100.0;
end if;
else
return false;
end if;
end function;
procedure report_coverage(
constant VOID : in t_void) is
begin
report_coverage(NON_VERBOSE);
end procedure;
procedure report_coverage(
constant verbosity : in t_report_verbosity;
constant file_name : in string := "";
constant open_mode : in file_open_kind := append_mode;
constant rand_weight_col : in t_rand_weight_visibility := HIDE_RAND_WEIGHT) is
file file_handler : text;
constant C_PREFIX : string := C_LOG_PREFIX & " ";
constant C_HEADER_1 : string := "*** COVERAGE SUMMARY REPORT (VERBOSE): " & to_string(priv_scope) & " ***";
constant C_HEADER_2 : string := "*** COVERAGE SUMMARY REPORT (NON VERBOSE): " & to_string(priv_scope) & " ***";
constant C_HEADER_3 : string := "*** COVERAGE HOLES REPORT: " & to_string(priv_scope) & " ***";
constant C_BIN_COLUMN_WIDTH : positive := 40;
constant C_COLUMN_WIDTH : positive := 15;
variable v_line : line;
variable v_log_extra_space : integer := 0;
variable v_print_goal : boolean;
variable v_rand_weight : natural;
begin
-- Calculate how much space we can insert between the columns of the report
v_log_extra_space := (C_LOG_LINE_WIDTH - C_PREFIX'length - C_BIN_COLUMN_WIDTH - C_COLUMN_WIDTH*5 - C_FC_MAX_NAME_LENGTH)/8;
if v_log_extra_space < 1 then
alert(TB_WARNING, "C_LOG_LINE_WIDTH is too small or C_FC_MAX_NAME_LENGTH is too big, the report will not be properly aligned.", priv_scope);
v_log_extra_space := 1;
end if;
-- Print report header
write(v_line, LF & fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF);
if verbosity = VERBOSE then
write(v_line, timestamp_header(now, justify(C_HEADER_1, LEFT, C_LOG_LINE_WIDTH - C_PREFIX'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE)) & LF);
elsif verbosity = NON_VERBOSE then
write(v_line, timestamp_header(now, justify(C_HEADER_2, LEFT, C_LOG_LINE_WIDTH - C_PREFIX'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE)) & LF);
elsif verbosity = HOLES_ONLY then
write(v_line, timestamp_header(now, justify(C_HEADER_3, LEFT, C_LOG_LINE_WIDTH - C_PREFIX'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE)) & LF);
end if;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF);
-- Print summary
if priv_id /= C_DEALLOCATED_ID then
v_print_goal := protected_covergroup_status.get_bins_coverage_goal(priv_id) /= 100 or
protected_covergroup_status.get_hits_coverage_goal(priv_id) /= 100;
write(v_line, "Coverpoint: " & to_string(priv_name) & LF &
return_string_if_true("Goal: " &
justify("Bins: " & to_string(protected_covergroup_status.get_bins_coverage_goal(priv_id)) & "%, ", left, 16, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("Hits: " & to_string(protected_covergroup_status.get_hits_coverage_goal(priv_id)) & "%", left, 14, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF, v_print_goal) &
return_string_if_true("% of Goal: " &
justify("Bins: " & to_string(protected_covergroup_status.get_bins_coverage(priv_id, GOAL_CAPPED),2) & "%, ", left, 16, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("Hits: " & to_string(protected_covergroup_status.get_hits_coverage(priv_id, GOAL_CAPPED),2) & "%", left, 14, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF, v_print_goal) &
return_string_if_true("% of Goal (uncapped): " &
justify("Bins: " & to_string(protected_covergroup_status.get_bins_coverage(priv_id, GOAL_UNCAPPED),2) & "%, ", left, 16, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("Hits: " & to_string(protected_covergroup_status.get_hits_coverage(priv_id, GOAL_UNCAPPED),2) & "%", left, 14, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF, v_print_goal) &
"Coverage (for goal 100): " &
justify("Bins: " & to_string(protected_covergroup_status.get_bins_coverage(priv_id, NO_GOAL),2) & "%, ", left, 16, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("Hits: " & to_string(protected_covergroup_status.get_hits_coverage(priv_id, NO_GOAL),2) & "%", left, 14, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF &
fill_string('-', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF);
else
write(v_line, "Coverpoint: " & to_string(priv_name) & LF &
"Coverage (for goal 100): " &
justify("Bins: 0.0%, ", left, 16, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("Hits: 0.0%", left, 14, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF &
fill_string('-', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF);
end if;
-- Print column headers
write(v_line, justify(
fill_string(' ', v_log_extra_space) &
justify("BINS" , center, C_BIN_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("HITS" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("MIN HITS" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("HIT COVERAGE" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
return_string_if_true(justify("RAND WEIGHT", center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),rand_weight_col = SHOW_RAND_WEIGHT) &
justify("NAME" , center, C_FC_MAX_NAME_LENGTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("ILLEGAL/IGNORE", center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),
left, C_LOG_LINE_WIDTH - C_PREFIX'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
-- Print illegal bins
for i in 0 to priv_invalid_bins_idx-1 loop
if is_bin_illegal(priv_invalid_bins(i)) and (verbosity = VERBOSE or (verbosity = NON_VERBOSE and priv_invalid_bins(i).hits > 0)) then
write(v_line, justify(
fill_string(' ', v_log_extra_space) &
justify(get_bin_values(priv_invalid_bins(i), C_BIN_COLUMN_WIDTH), center, C_BIN_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(priv_invalid_bins(i).hits) , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("N/A" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("N/A" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
return_string_if_true(justify("N/A" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),rand_weight_col = SHOW_RAND_WEIGHT) &
justify(to_string(priv_invalid_bins(i).name) , center, C_FC_MAX_NAME_LENGTH, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("ILLEGAL" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),
left, C_LOG_LINE_WIDTH - C_PREFIX'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
end if;
end loop;
-- Print ignore bins
if verbosity = VERBOSE then
for i in 0 to priv_invalid_bins_idx-1 loop
if is_bin_ignore(priv_invalid_bins(i)) then
write(v_line, justify(
fill_string(' ', v_log_extra_space) &
justify(get_bin_values(priv_invalid_bins(i), C_BIN_COLUMN_WIDTH), center, C_BIN_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(priv_invalid_bins(i).hits) , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("N/A" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("N/A" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
return_string_if_true(justify("N/A" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),rand_weight_col = SHOW_RAND_WEIGHT) &
justify(to_string(priv_invalid_bins(i).name) , center, C_FC_MAX_NAME_LENGTH, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("IGNORE" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),
left, C_LOG_LINE_WIDTH - C_PREFIX'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
end if;
end loop;
end if;
-- Print valid bins
for i in 0 to priv_bins_idx-1 loop
if verbosity = VERBOSE or verbosity = NON_VERBOSE or (verbosity = HOLES_ONLY and priv_bins(i).hits < get_total_min_hits(priv_bins(i).min_hits)) then
v_rand_weight := priv_bins(i).min_hits when priv_bins(i).rand_weight = C_USE_ADAPTIVE_WEIGHT else priv_bins(i).rand_weight;
write(v_line, justify(
fill_string(' ', v_log_extra_space) &
justify(get_bin_values(priv_bins(i), C_BIN_COLUMN_WIDTH) , center, C_BIN_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(priv_bins(i).hits) , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(priv_bins(i).min_hits) , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_bin_coverage(priv_bins(i)),2) & "%", center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
return_string_if_true(justify(to_string(v_rand_weight) , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),rand_weight_col = SHOW_RAND_WEIGHT) &
justify(to_string(priv_bins(i).name) , center, C_FC_MAX_NAME_LENGTH, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("-" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),
left, C_LOG_LINE_WIDTH - C_PREFIX'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
end if;
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF);
-- Print bin values that didn't fit in section above
for i in 0 to priv_invalid_bins_idx-1 loop
if is_bin_illegal(priv_invalid_bins(i)) and (verbosity = VERBOSE or (verbosity = NON_VERBOSE and priv_invalid_bins(i).hits > 0)) then
if get_bin_values(priv_invalid_bins(i), C_BIN_COLUMN_WIDTH) = to_string(priv_invalid_bins(i).name) then
write(v_line, to_string(priv_invalid_bins(i).name) & ": " & get_bin_values(priv_invalid_bins(i)) & LF);
end if;
end if;
end loop;
if verbosity = VERBOSE then
for i in 0 to priv_invalid_bins_idx-1 loop
if is_bin_ignore(priv_invalid_bins(i)) then
if get_bin_values(priv_invalid_bins(i), C_BIN_COLUMN_WIDTH) = to_string(priv_invalid_bins(i).name) then
write(v_line, to_string(priv_invalid_bins(i).name) & ": " & get_bin_values(priv_invalid_bins(i)) & LF);
end if;
end if;
end loop;
end if;
for i in 0 to priv_bins_idx-1 loop
if verbosity = VERBOSE or verbosity = NON_VERBOSE or (verbosity = HOLES_ONLY and priv_bins(i).hits < get_total_min_hits(priv_bins(i).min_hits)) then
if get_bin_values(priv_bins(i), C_BIN_COLUMN_WIDTH) = to_string(priv_bins(i).name) then
write(v_line, to_string(priv_bins(i).name) & ": " & get_bin_values(priv_bins(i)) & LF);
end if;
end if;
end loop;
-- Print report bottom line
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF & LF);
-- Write the info string to transcript
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-C_PREFIX'length);
prefix_lines(v_line, C_PREFIX);
if file_name /= "" then
file_open(file_handler, file_name, open_mode);
tee(file_handler, v_line); -- write to file, while keeping the line contents
file_close(file_handler);
end if;
write_line_to_log_destination(v_line);
DEALLOCATE(v_line);
end procedure;
procedure report_config(
constant VOID : in t_void) is
begin
report_config("");
end procedure;
procedure report_config(
constant file_name : in string;
constant open_mode : in file_open_kind := append_mode) is
file file_handler : text;
constant C_PREFIX : string := C_LOG_PREFIX & " ";
constant C_COLUMN1_WIDTH : positive := 24;
constant C_COLUMN2_WIDTH : positive := MAXIMUM(C_FC_MAX_NAME_LENGTH, C_LOG_SCOPE_WIDTH);
variable v_line : line;
begin
-- Print report header
write(v_line, LF & fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF &
"*** COVERPOINT CONFIGURATION REPORT ***" & LF &
fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF);
-- Print report config
if priv_id /= C_DEALLOCATED_ID then
write(v_line, " " & justify("NAME", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(priv_name), right, C_COLUMN2_WIDTH) & LF);
else
write(v_line, " " & justify("NAME", left, C_COLUMN1_WIDTH) & ": " & justify("**uninitialized**", right, C_COLUMN2_WIDTH) & LF);
end if;
write(v_line, " " & justify("SCOPE", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(priv_scope), right, C_COLUMN2_WIDTH) & LF);
write(v_line, " " & justify("ILLEGAL BIN ALERT LEVEL", left, C_COLUMN1_WIDTH) & ": " & justify(to_upper(to_string(priv_illegal_bin_alert_level)), right, C_COLUMN2_WIDTH) & LF);
write(v_line, " " & justify("BIN OVERLAP ALERT LEVEL", left, C_COLUMN1_WIDTH) & ": " & justify(to_upper(to_string(priv_bin_overlap_alert_level)), right, C_COLUMN2_WIDTH) & LF);
if priv_id /= C_DEALLOCATED_ID then
write(v_line, " " & justify("COVERAGE WEIGHT", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(protected_covergroup_status.get_coverage_weight(priv_id)), right, C_COLUMN2_WIDTH) & LF);
write(v_line, " " & justify("BINS COVERAGE GOAL", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(protected_covergroup_status.get_bins_coverage_goal(priv_id)), right, C_COLUMN2_WIDTH) & LF);
write(v_line, " " & justify("HITS COVERAGE GOAL", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(protected_covergroup_status.get_hits_coverage_goal(priv_id)), right, C_COLUMN2_WIDTH) & LF);
else
write(v_line, " " & justify("COVERAGE WEIGHT", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(1), right, C_COLUMN2_WIDTH) & LF);
write(v_line, " " & justify("BINS COVERAGE GOAL", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(100), right, C_COLUMN2_WIDTH) & LF);
write(v_line, " " & justify("HITS COVERAGE GOAL", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(100), right, C_COLUMN2_WIDTH) & LF);
end if;
write(v_line, " " & justify("COVERPOINTS GOAL", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(protected_covergroup_status.get_covpts_coverage_goal(VOID)), right, C_COLUMN2_WIDTH) & LF);
write(v_line, " " & justify("NUMBER OF BINS", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(priv_bins_idx+priv_invalid_bins_idx), right, C_COLUMN2_WIDTH) & LF);
write(v_line, " " & justify("CROSS DIMENSIONS", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(priv_num_bins_crossed), right, C_COLUMN2_WIDTH) & LF);
-- Print report bottom line
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF & LF);
-- Write the info string to transcript
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-C_PREFIX'length);
prefix_lines(v_line, C_PREFIX);
if file_name /= "" then
file_open(file_handler, file_name, open_mode);
tee(file_handler, v_line); -- write to file, while keeping the line contents
file_close(file_handler);
end if;
write_line_to_log_destination(v_line);
DEALLOCATE(v_line);
end procedure;
------------------------------------------------------------
-- Optimized Randomization
------------------------------------------------------------
impure function rand(
constant sampling : t_rand_sample_cov;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel)
return integer is
constant C_LOCAL_CALL : string := "rand(" & to_upper(to_string(sampling)) & ")";
variable v_ret : integer_vector(0 to 0);
begin
v_ret := rand(sampling, msg_id_panel, C_LOCAL_CALL);
if priv_num_bins_crossed /= C_UNINITIALIZED then
log(ID_FUNC_COV_RAND, get_name_prefix(VOID) & C_LOCAL_CALL & "=> " & to_string(v_ret(0)), priv_scope, msg_id_panel);
end if;
return v_ret(0);
end function;
impure function rand(
constant sampling : t_rand_sample_cov;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : string := "")
return integer_vector is
constant C_LOCAL_CALL : string := "rand(" & to_upper(to_string(sampling)) & ")";
variable v_bin_weight_list : t_val_weight_int_vec(0 to priv_bins_idx-1);
variable v_acc_weight : natural := 0;
variable v_values_vec : integer_vector(0 to C_FC_MAX_NUM_BIN_VALUES-1);
variable v_bin_idx : natural;
variable v_ret : integer_vector(0 to MAXIMUM(priv_num_bins_crossed,1)-1);
variable v_hits : natural := 0;
variable v_iteration : natural := 0;
begin
if priv_num_bins_crossed = C_UNINITIALIZED then
alert(TB_ERROR, C_LOCAL_CALL & "=> Coverpoint does not contain any bins", priv_scope);
return v_ret;
end if;
-- A transition bin returns all the transition values before allowing to select a different bin value
if priv_rand_transition_bin_idx /= C_UNINITIALIZED then
v_bin_idx := priv_rand_transition_bin_idx;
else
-- Assign each bin a randomization weight
while v_acc_weight = 0 loop
for i in 0 to priv_bins_idx-1 loop
v_bin_weight_list(i).value := i;
v_hits := priv_bins(i).hits - (v_iteration * get_total_min_hits(priv_bins(i).min_hits));
if v_hits < get_total_min_hits(priv_bins(i).min_hits) then
v_bin_weight_list(i).weight := get_total_min_hits(priv_bins(i).min_hits) - v_hits when priv_bins(i).rand_weight = C_USE_ADAPTIVE_WEIGHT else
priv_bins(i).rand_weight;
else
v_bin_weight_list(i).weight := 0;
end if;
v_acc_weight := v_acc_weight + v_bin_weight_list(i).weight;
end loop;
-- When all the bins have reached their min_hits, the accumulated weight will be 0 and
-- a new iteration will be done where all the bins are uncovered again by simulating
-- the number of hits are cleared
v_iteration := v_iteration + 1;
end loop;
-- Choose a random bin index
v_bin_idx := priv_rand_gen.rand_val_weight(v_bin_weight_list, msg_id_panel);
end if;
-- Select the random bin values to return (ignore and illegal bin values are never selected)
for i in 0 to priv_num_bins_crossed-1 loop
v_values_vec := (others => 0);
if priv_bins(v_bin_idx).cross_bins(i).contains = VAL then
if priv_bins(v_bin_idx).cross_bins(i).num_values = 1 then
v_ret(i) := priv_bins(v_bin_idx).cross_bins(i).values(0);
else
for j in 0 to priv_bins(v_bin_idx).cross_bins(i).num_values-1 loop
v_values_vec(j) := priv_bins(v_bin_idx).cross_bins(i).values(j);
end loop;
v_ret(i) := priv_rand_gen.rand(ONLY, v_values_vec(0 to priv_bins(v_bin_idx).cross_bins(i).num_values-1), NON_CYCLIC, msg_id_panel);
end if;
elsif priv_bins(v_bin_idx).cross_bins(i).contains = RAN then
v_ret(i) := priv_rand_gen.rand(priv_bins(v_bin_idx).cross_bins(i).values(0), priv_bins(v_bin_idx).cross_bins(i).values(1), NON_CYCLIC, msg_id_panel);
elsif priv_bins(v_bin_idx).cross_bins(i).contains = TRN then
-- Store the bin index to return the next value in the following rand() call
if priv_rand_transition_bin_idx = C_UNINITIALIZED then
priv_rand_transition_bin_idx := v_bin_idx;
end if;
v_ret(i) := priv_bins(v_bin_idx).cross_bins(i).values(priv_rand_transition_bin_value_idx(i));
if priv_rand_transition_bin_value_idx(i) < priv_bins(v_bin_idx).cross_bins(i).num_values then
priv_rand_transition_bin_value_idx(i) := priv_rand_transition_bin_value_idx(i) + 1;
end if;
else
alert(TB_FAILURE, C_LOCAL_CALL & "=> Unexpected error, bin contains " & to_upper(to_string(priv_bins(v_bin_idx).cross_bins(i).contains)), priv_scope);
end if;
-- Reset transition index variables when all the transitions in a bin have been generated
if i = priv_num_bins_crossed-1 and priv_rand_transition_bin_idx /= C_UNINITIALIZED then
for j in 0 to priv_num_bins_crossed-1 loop
if priv_bins(v_bin_idx).cross_bins(j).contains = TRN and priv_rand_transition_bin_value_idx(j) < priv_bins(v_bin_idx).cross_bins(j).num_values then
exit;
elsif j = priv_num_bins_crossed-1 then
priv_rand_transition_bin_idx := C_UNINITIALIZED;
priv_rand_transition_bin_value_idx := (others => 0);
end if;
end loop;
end if;
end loop;
if sampling = SAMPLE_COV then
sample_coverage(v_ret, msg_id_panel, C_LOCAL_CALL);
end if;
if ext_proc_call = "" then -- Do not print log message when being called from another method
log(ID_FUNC_COV_RAND, get_name_prefix(VOID) & C_LOCAL_CALL & "=> " & to_string(v_ret), priv_scope, msg_id_panel);
end if;
return v_ret;
end function;
procedure set_rand_seeds(
constant seed1 : in positive;
constant seed2 : in positive) is
begin
initialize_coverpoint("set_rand_seeds");
priv_rand_gen.set_rand_seeds(seed1, seed2);
end procedure;
procedure set_rand_seeds(
constant seeds : in t_positive_vector(0 to 1)) is
begin
initialize_coverpoint("set_rand_seeds");
priv_rand_gen.set_rand_seeds(seeds);
end procedure;
procedure get_rand_seeds(
variable seed1 : out positive;
variable seed2 : out positive) is
begin
priv_rand_gen.get_rand_seeds(seed1, seed2);
end procedure;
impure function get_rand_seeds(
constant VOID : t_void)
return t_positive_vector is
begin
return priv_rand_gen.get_rand_seeds(VOID);
end function;
end protected body t_coverpoint;
end package body func_cov_pkg;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0_11;
USE axi_bram_ctrl_v4_0_11.axi_bram_ctrl;
ENTITY zynq_design_1_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END zynq_design_1_axi_bram_ctrl_0_0;
ARCHITECTURE zynq_design_1_axi_bram_ctrl_0_0_arch OF zynq_design_1_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 16384,
C_BRAM_ADDR_WIDTH => 14,
C_S_AXI_ADDR_WIDTH => 16,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 0,
C_FAMILY => "zynq",
C_SELECT_XPM => 0,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rst_b => bram_rst_b,
bram_clk_b => bram_clk_b,
bram_en_b => bram_en_b,
bram_we_b => bram_we_b,
bram_addr_b => bram_addr_b,
bram_wrdata_b => bram_wrdata_b,
bram_rddata_b => bram_rddata_b
);
END zynq_design_1_axi_bram_ctrl_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0_11;
USE axi_bram_ctrl_v4_0_11.axi_bram_ctrl;
ENTITY zynq_design_1_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END zynq_design_1_axi_bram_ctrl_0_0;
ARCHITECTURE zynq_design_1_axi_bram_ctrl_0_0_arch OF zynq_design_1_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 16384,
C_BRAM_ADDR_WIDTH => 14,
C_S_AXI_ADDR_WIDTH => 16,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 0,
C_FAMILY => "zynq",
C_SELECT_XPM => 0,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rst_b => bram_rst_b,
bram_clk_b => bram_clk_b,
bram_en_b => bram_en_b,
bram_we_b => bram_we_b,
bram_addr_b => bram_addr_b,
bram_wrdata_b => bram_wrdata_b,
bram_rddata_b => bram_rddata_b
);
END zynq_design_1_axi_bram_ctrl_0_0_arch;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: tech_umc18
-- File: tech_umc18.vhd
-- Author: Raijmond Keulen, Irotech
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Contains UMC umc18 specific pads and ram generators
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.iface.all;
package tech_umc18 is
-- sync ram generator
component umc18_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
address : in std_logic_vector(abits -1 downto 0);
clk : in std_logic;
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_logic;
write : in std_logic);
end component;
-- regfile generator
component umc18_regfile
generic ( abits : integer := 8; dbits : integer := 32; words : integer := 128);
port (
rst : in std_logic;
clk : in clk_type;
clkn : in clk_type;
rfi : in rf_in_type;
rfo : out rf_out_type);
end component;
-- pads
component umc18_inpad
port (pad : in std_logic; q : out std_logic);
end component;
component umc18_smpad
port (pad : in std_logic; q : out std_logic);
end component;
component umc18_outpad
generic (drive : integer := 1);
port (d : in std_logic; pad : out std_logic);
end component;
component umc18_toutpadu
generic (drive : integer := 1);
port (d, en : in std_logic; pad : out std_logic);
end component;
component umc18_iopad
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component umc18_iopadu
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component umc18_iodpad
generic (drive : integer := 1);
port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component umc18_odpad
generic (drive : integer := 1);
port ( d : in std_logic; pad : out std_logic);
end component;
component umc18_smiopad
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
end;
------------------------------------------------------------------
-- behavioural pad models --------------------------------------------
------------------------------------------------------------------
-- Only needed for simulation, not synthesis.
-- pragma translate_off
-- input pad 1xDrive
library IEEE;
use IEEE.std_logic_1164.all;
entity C3I40 is port (PAD : in std_logic; DI : out std_logic); end;
architecture rtl of C3I40 is begin DI <= to_x01(PAD) after 1 ns; end;
-- input schmitt pad 1xDrive
library IEEE;
use IEEE.std_logic_1164.all;
entity C3I42 is port (PAD : in std_logic; DI : out std_logic); end;
architecture rtl of C3I42 is begin DI <= to_x01(PAD) after 1 ns; end;
-- output pad 2mA
library IEEE;
use IEEE.std_logic_1164.all;
entity C3O10 is port (DO : in std_logic; PAD : out std_logic); end;
architecture rtl of C3O10 is begin PAD <= to_x01(DO) after 2 ns; end;
-- output pad 4mA
library IEEE;
use IEEE.std_logic_1164.all;
entity C3O20 is port (DO : in std_logic; PAD : out std_logic); end;
architecture rtl of C3O20 is begin PAD <= to_x01(DO) after 2 ns; end;
-- output pad 8mA
library IEEE;
use IEEE.std_logic_1164.all;
entity C3O40 is port (DO : in std_logic; PAD : out std_logic); end;
architecture rtl of C3O40 is begin PAD <= to_x01(DO) after 2 ns; end;
-- bidirectional pad pullup 2mA, used as tri-state output pad with pull-up *
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B10U is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B10U is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad pullup 4mA, used as tri-state output pad with pull-up *
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B20U is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B20U is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad pullup 8mA, used as tri-state output pad with pull-up *
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B40U is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B40U is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad 2mA *
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B10 is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B10 is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad 4mA *
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B20 is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B20 is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad 8mA *
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B40 is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B40 is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad 2mA with open drain
library IEEE;
use IEEE.std_logic_1164.all;
entity CD3B10T is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of CD3B10T is
begin
PAD <= '0' after 2 ns when (EN and not DO) = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad 4mA with open drain
library IEEE;
use IEEE.std_logic_1164.all;
entity CD3B20T is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of CD3B20T is
begin
PAD <= '0' after 2 ns when (EN and not DO) = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad 8mA with open drain
library IEEE;
use IEEE.std_logic_1164.all;
entity CD3B40T is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of CD3B40T is
begin
PAD <= '0' after 2 ns when (EN and not DO) = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- output pad 2mA with open drain
library IEEE;
use IEEE.std_logic_1164.all;
entity CD3O10T is
port ( DO : in std_logic; PAD : out std_logic);
end;
architecture rtl of CD3O10T is
begin
PAD <= '0' after 2 ns when DO = '0' else 'Z' after 2 ns;
end;
-- output pad 4mA with open drain
library IEEE;
use IEEE.std_logic_1164.all;
entity CD3O20T is
port ( DO : in std_logic; PAD : out std_logic);
end;
architecture rtl of CD3O20T is
begin
PAD <= '0' after 2 ns when DO = '0' else 'Z' after 2 ns;
end;
-- output pad 8mA with open drain
library IEEE;
use IEEE.std_logic_1164.all;
entity CD3O40T is
port ( DO : in std_logic; PAD : out std_logic);
end;
architecture rtl of CD3O40T is
begin
PAD <= '0' after 2 ns when DO = '0' else 'Z' after 2 ns;
end;
-- bidirectional pad 8mA schmitt trigger
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B42 is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B42 is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
------------------------------------------------------------------
-- behavioural ram models ----------------------------------------
------------------------------------------------------------------
-- Address and control latched on rising clka, data latched on falling clkb.
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity umc18_dpram_ss is
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
DI: in std_logic_vector (dbits -1 downto 0);
RADR,WADR: in std_logic_vector (abits -1 downto 0);
REN,WEN : in std_logic;
RCK,WCK : in std_logic;
DOUT: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of umc18_dpram_ss is
signal DI_l,DOUT_l : std_logic_vector (dbits -1 downto 0);
signal RADR_l, WADR_l : std_logic_vector (abits -1 downto 0);
signal REN_l, WEN_l : std_logic;
type dregtype is array (0 to words - 1)
of std_logic_vector(dbits -1 downto 0);
signal data : dregtype;
attribute syn_ramstyle : string;
attribute syn_ramstyle of data: signal is "block_ram";
begin
writeport : process(WCK)
begin
if rising_edge(WCK) then
DI_l <= DI;
WEN_l <= WEN;
WADR_l <= WADR;
end if;
end process;
readport : process(RCK)
begin
if rising_edge(RCK) then
REN_l <= REN;
RADR_l <= RADR;
end if;
end process;
ram : process(DI_l, WEN_l, WADR_l, REN_l, RADR_l, data)
begin
if WEN_l = '0' then
if not ( is_x(WADR_l) or (conv_integer(unsigned(WADR_l)) >= words)) then
data(conv_integer(unsigned(WADR_l))) <= DI_l;
end if;
end if;
if REN_l = '0' then
if not (is_x(RADR_l) or (conv_integer(unsigned(RADR_l)) >= words)) then
DOUT_l <= data(conv_integer(unsigned(RADR_l)));
else
DOUT_l <= (others => 'X');
end if;
else
DOUT_l <= (others => 'Z');
end if;
end process;
DOUT <= DOUT_l;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity umc18_syncram_ss is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
ADR : in std_logic_vector((abits -1) downto 0);
DI : in std_logic_vector((dbits -1) downto 0);
DOUT : out std_logic_vector((dbits -1) downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of umc18_syncram_ss is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
attribute syn_ramstyle : string;
attribute syn_ramstyle of memarr: signal is "block_ram";
signal ADR_l : std_logic_vector((abits -1) downto 0);
signal DI_l : std_logic_vector((dbits -1) downto 0);
signal WEN_l : std_logic;
signal CEN_l : std_logic;
signal DOUT_l : std_logic_vector((dbits -1) downto 0);
begin
input_latch : process(CK)
begin
if rising_edge(CK) then
ADR_l <= ADR;
DI_l <= DI;
WEN_l <= WEN;
CEN_l <= CEN;
end if;
end process;
ram : process(ADR_l,DI_l,WEN_l,CEN_l,memarr)
begin
if CEN_l = '0' then
if WEN_l = '0' then
if not is_x(ADR_l) then
memarr(conv_integer(unsigned(ADR_l))) <= DI_l;
end if;
end if;
if not is_x(ADR_l) then
DOUT_l <= memarr(conv_integer(unsigned(ADR_l)));
else
DOUT_l <= (others => 'X');
end if;
end if;
end process;
DOUT <= DOUT_l when OEN = '0' else (others => 'Z');
end;
-- syncronous umc18 sram
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package tech_umc18_sim is
component umc18_syncram_ss
generic ( abits : integer := 10; dbits : integer := 8 );
port (
ADR : in std_logic_vector((abits -1) downto 0);
DI : in std_logic_vector((dbits -1) downto 0);
DOUT : out std_logic_vector((dbits -1) downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end component;
-- syncronous umc18 dpram
component umc18_dpram_ss
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
DI: in std_logic_vector (dbits -1 downto 0);
RADR: in std_logic_vector (abits -1 downto 0);
WADR: in std_logic_vector (abits -1 downto 0);
REN,WEN : in std_logic;
RCK,WCK : in std_logic;
DOUT: out std_logic_vector (dbits -1 downto 0)
);
end component;
end;
-- Address, control and data signals latched on rising ME.
-- Write enable (WEN) active low.
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R256X24M4 is
port (
ADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(23 downto 0);
DOUT : out std_logic_vector(23 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R256X24M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 8, dbits => 24)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R256X25M4 is
port (
ADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(24 downto 0);
DOUT : out std_logic_vector(24 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R256X25M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 8, dbits => 25)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R256X26M4 is
port (
ADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(25 downto 0);
DOUT : out std_logic_vector(25 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R256X26M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 8, dbits => 26)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R1024X32M4 is
port (
ADR : in std_logic_vector(9 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R1024X32M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 10, dbits => 32)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R1024X33M4 is
port (
ADR : in std_logic_vector(9 downto 0);
DI : in std_logic_vector(32 downto 0);
DOUT : out std_logic_vector(32 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R1024X33M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 10, dbits => 33)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R2048X32M8 is
port (
ADR : in std_logic_vector(10 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R2048X32M8 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 11, dbits => 32)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R256X28M4 is
port (
ADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(27 downto 0);
DOUT : out std_logic_vector(27 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R256X28M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 8, dbits => 28)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R1024X34M4 is
port (
ADR : in std_logic_vector(10 downto 0);
DI : in std_logic_vector(33 downto 0);
DOUT : out std_logic_vector(33 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R1024X34M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 10, dbits => 34)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R2048x34M8 is
port (
ADR : in std_logic_vector(11 downto 0);
DI : in std_logic_vector(33 downto 0);
DOUT : out std_logic_vector(33 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R2048x34M8 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 11, dbits => 34)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity RF68X32M1 is
port ( RCK : in std_logic;
REN : in std_logic;
RADR : in std_logic_vector(6 downto 0);
WCK : in std_logic;
WEN : in std_logic;
WADR : in std_logic_vector(6 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0) );
end;
architecture behav of RF68X32M1 is
begin
dp0 : umc18_dpram_ss
generic map (abits => 7, dbits => 32, words => 68)
port map ( DI => DI, RADR => RADR, WADR => WADR, WEN => WEN,
REN => REN, RCK => RCK, WCK => WCK, DOUT => DOUT);
end;
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity RF68X33M1 is
port ( RCK : in std_logic;
REN : in std_logic;
RADR : in std_logic_vector(6 downto 0);
WCK : in std_logic;
WEN : in std_logic;
WADR : in std_logic_vector(6 downto 0);
DI : in std_logic_vector(32 downto 0);
DOUT : out std_logic_vector(32 downto 0) );
end;
architecture behav of RF68X33M1 is
begin
dp0 : umc18_dpram_ss
generic map (abits => 7, dbits => 33, words => 68)
port map ( DI => DI, RADR => RADR, WADR => WADR, WEN => WEN,
REN => REN, RCK => RCK, WCK => WCK, DOUT => DOUT);
end;
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity RF136X32M1 is
port ( RCK : in std_logic;
REN : in std_logic;
RADR : in std_logic_vector(7 downto 0);
WCK : in std_logic;
WEN : in std_logic;
WADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0) );
end;
architecture behav of RF136X32M1 is
begin
dp0 : umc18_dpram_ss
generic map (abits => 8, dbits => 32, words => 136)
port map ( DI => DI, RADR => RADR, WADR => WADR, WEN => WEN,
REN => REN, RCK => RCK, WCK => WCK, DOUT => DOUT);
end;
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity RF136X33M1 is
port ( RCK : in std_logic;
REN : in std_logic;
RADR : in std_logic_vector(7 downto 0);
WCK : in std_logic;
WEN : in std_logic;
WADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(32 downto 0);
DOUT : out std_logic_vector(32 downto 0) );
end;
architecture behav of RF136X33M1 is
begin
dp0 : umc18_dpram_ss
generic map (abits => 8, dbits => 33, words => 136)
port map ( DI => DI, RADR => RADR, WADR => WADR, WEN => WEN,
REN => REN, RCK => RCK, WCK => WCK, DOUT => DOUT);
end;
-- simple gate models
library IEEE;
use IEEE.std_logic_1164.all;
entity INVDL is port( A : in std_logic; Z : out std_logic); end;
architecture rtl of INVDL is begin Z <= not A; end;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2DL is port( A1, A2 : in std_logic; Z : out std_logic); end;
architecture rtl of AND2DL is begin Z <= A1 and A2; end;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2DL is port( A1, A2 : in std_logic; Z : out std_logic); end;
architecture rtl of OR2DL is begin Z <= A1 or A2; end;
library IEEE;
use IEEE.std_logic_1164.all;
entity EXOR2DL is port( A1, A2 : in std_logic; Z : out std_logic); end;
architecture rtl of EXOR2DL is begin Z <= A1 xor A2; end;
-- pragma translate_on
-- component declarations from true tech library
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package tech_umc18_syn is
component RF136X32M1
port ( RCK : in std_logic;
REN : in std_logic;
RADR : in std_logic_vector(7 downto 0);
WCK : in std_logic;
WEN : in std_logic;
WADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0) );
end component;
component R256X24M4
port ( ADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(23 downto 0);
DOUT : out std_logic_vector(23 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic );
end component;
component R256X26M4
port ( ADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(25 downto 0);
DOUT : out std_logic_vector(25 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic );
end component;
component R1024X32M4
port ( ADR : in std_logic_vector(9 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic );
end component;
component R2048x32M8
port ( ADR : in std_logic_vector(10 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic );
end component;
component C3I40
port (PAD : in std_logic; DI : out std_logic);
end component;
component C3I42
port (PAD : in std_logic; DI : out std_logic);
end component;
component C3O10
port (DO : in std_logic; PAD : out std_logic);
end component;
component C3O20
port (DO : in std_logic; PAD : out std_logic);
end component;
component C3O40
port (DO : in std_logic; PAD : out std_logic);
end component;
component C3B10U
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component C3B20U
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component C3B40U
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component C3B10
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component C3B20
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component C3B40
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component CD3B10T
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component CD3B20T
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component CD3B40T
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component CD3O10T
port ( DO : in std_logic; PAD : out std_logic);
end component;
component CD3O20T
port ( DO : in std_logic; PAD : out std_logic);
end component;
component CD3O40T
port ( DO : in std_logic; PAD : out std_logic);
end component;
component C3B42
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component INVDL port( A : in std_logic; Z : out std_logic); end component;
component AND2DL port( A1, A2 : in std_logic; Z : out std_logic); end component;
component OR2DL port( A1, A2 : in std_logic; Z : out std_logic); end component;
component EXOR2DL port( A1, A2 : in std_logic; Z : out std_logic); end component;
end;
------------------------------------------------------------------
-- sync ram generator --------------------------------------------
------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
address : in std_logic_vector(abits -1 downto 0);
clk : in std_logic;
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_logic;
write : in std_logic
);
end;
architecture rtl of umc18_syncram is
signal gnd : std_logic;
signal wr : std_logic;
signal a : std_logic_vector(19 downto 0);
signal d, q : std_logic_vector(34 downto 0);
constant synopsys_bug : std_logic_vector(37 downto 0) := (others => '0');
begin
wr <= not write;
gnd <= '0';
a(abits -1 downto 0) <= address;
a(abits+1 downto abits) <= synopsys_bug(abits+1 downto abits);
d(dbits -1 downto 0) <= datain;
d(dbits+1 downto dbits) <= synopsys_bug(dbits+1 downto dbits);
dataout <= q(dbits -1 downto 0);
a8d24 : if (abits = 8) and (dbits = 24) generate
id0 : R256X24M4
port map ( ADR => a(7 downto 0), DI => d(23 downto 0),
DOUT => q(23 downto 0), CK => clk, WEN => wr,
CEN => gnd, OEN => gnd);
end generate;
a8d26 : if (abits = 8) and (dbits = 26) generate
id0 : R256X26M4
port map ( ADR => a(7 downto 0), DI => d(25 downto 0),
DOUT => q(25 downto 0), CK => clk, WEN => wr,
CEN => gnd, OEN => gnd);
end generate;
a10d32 : if (abits = 10) and (dbits = 32) generate
id0 : R1024X32M4
port map ( ADR => a(9 downto 0), DI => d(31 downto 0),
DOUT => q(31 downto 0), CK => clk, WEN => wr,
CEN => gnd, OEN => gnd);
end generate;
a11d32 : if (abits = 11) and (dbits = 32) generate
id0 : R2048X32M8
port map ( ADR => a(10 downto 0), DI => d(31 downto 0),
DOUT => q(31 downto 0), CK => clk, WEN => wr,
CEN => gnd, OEN => gnd);
end generate;
end rtl;
------------------------------------------------------------------
-- regfile generator --------------------------------------------
------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.iface.all;
use work.tech_umc18_syn.all;
entity umc18_regfile is
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 128
);
port (
rst : in std_logic;
clk : in clk_type;
clkn : in clk_type;
rfi : in rf_in_type;
rfo : out rf_out_type);
end;
architecture rtl of umc18_regfile is
signal qq1, qq2 : std_logic_vector(dbits-1 downto 0);
signal wen, ren1, ren2 : std_logic;
begin
ren1 <= not rfi.ren1;
ren2 <= not rfi.ren2;
wen <= not rfi.wren;
dp136x32 : if (words = 136) and (dbits = 32) generate
u0: RF136X32M1
port map (RCK => clkn, REN => ren1, RADR => rfi.rd1addr(abits -1 downto 0),
WCK => clk, WEN => wen, WADR => rfi.wraddr(abits -1 downto 0),
DI => rfi.wrdata(dbits -1 downto 0), DOUT => qq1);
u1: RF136X32M1
port map (RCK => clkn, REN => ren2, RADR => rfi.rd2addr(abits -1 downto 0),
WCK => clk, WEN => wen, WADR => rfi.wraddr(abits -1 downto 0),
DI => rfi.wrdata(dbits -1 downto 0), DOUT => qq2);
end generate;
rfo.data1 <= qq1(dbits-1 downto 0);
rfo.data2 <= qq2(dbits-1 downto 0);
end;
------------------------------------------------------------------
-- mapping generic pads on tech pads ---------------------------------
------------------------------------------------------------------
-- input pad
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_inpad is port (pad : in std_logic; q : out std_logic); end;
architecture syn of umc18_inpad is begin
i0 : C3I40 port map (PAD => pad, DI => q);
end;
-- input schmitt pad
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_smpad is port (pad : in std_logic; q : out std_logic); end;
architecture syn of umc18_smpad is begin
i0 : C3I42 port map (PAD => pad, DI => q);
end;
-- output pads
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_outpad is
generic (drive : integer := 1);
port (d : in std_logic; pad : out std_logic);
end;
architecture syn of umc18_outpad is begin
d1 : if drive = 1 generate
u0 : C3O10 port map (PAD => pad, DO => d);
end generate;
d2 : if drive = 2 generate
i0 : C3O20 port map (PAD => pad, DO => d);
end generate;
d3 : if drive > 2 generate
i0 : C3O40 port map (PAD => pad, DO => d);
end generate;
end;
-- tri-state output pads with pull-up
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_toutpadu is
generic (drive : integer := 1);
port (d, en : in std_logic; pad : out std_logic);
end;
architecture syn of umc18_toutpadu is
signal nc,p : std_logic;
begin
d1 : if drive = 1 generate
i0 : C3B10U port map (PAD => p, DO => d, DI => nc, EN => en);
end generate;
d2 : if drive = 2 generate
i0 : C3B20U port map (PAD => p, DO => d, DI => nc, EN => en);
end generate;
d3 : if drive > 2 generate
i0 : C3B40U port map (PAD => p, DO => d, DI => nc, EN => en);
end generate;
pad <= p;
end;
-- bidirectional pad 2/4/8mA 4X
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_iopad is
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end;
architecture syn of umc18_iopad is
signal eni : std_logic;
begin
eni <= not en;
d1 : if drive = 1 generate
i0 : C3B10 port map (PAD => pad, DO => d, EN => eni, DI => q);
end generate;
d2 : if drive = 2 generate
i0 : C3B20 port map (PAD => pad, DO => d, EN => eni, DI => q);
end generate;
d3 : if drive > 2 generate
i0 : C3B40 port map (PAD => pad, DO => d, EN => eni, DI => q);
end generate;
end;
-- bidirectional pad with open-drain
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_iodpad is
generic (drive : integer := 1);
port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
end;
architecture syn of umc18_iodpad is
signal vcc : std_logic;
begin
vcc <= '1';
d1 : if drive = 1 generate
i0 : CD3B10T port map (PAD => pad, DO => d, EN => vcc, DI => q);
end generate;
d2 : if drive = 2 generate
i0 : CD3B20T port map (PAD => pad, DO => d, EN => vcc, DI => q);
end generate;
d3 : if drive > 2 generate
i0 : CD3B40T port map (PAD => pad, DO => d, EN => vcc, DI => q);
end generate;
end;
-- output pad with open-drain
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_odpad is
generic (drive : integer := 1);
port (d : in std_logic; pad : out std_logic);
end;
architecture syn of umc18_odpad is
begin
d1 : if drive = 1 generate
i0 : CD3O10T port map (PAD => pad, DO => d);
end generate;
d2 : if drive = 2 generate
i0 : CD3O20T port map (PAD => pad, DO => d);
end generate;
d3 : if drive > 2 generate
i0 : CD3O40T port map (PAD => pad, DO => d);
end generate;
end;
-- bidirectional pad 8mA 4X schmitt trigger
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_smiopad is
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end;
architecture syn of umc18_smiopad is
signal eni : std_logic;
begin
eni <= not en;
i0 : C3B42 port map (PAD => pad, DO => d, EN => eni, DI => q);
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: tech_umc18
-- File: tech_umc18.vhd
-- Author: Raijmond Keulen, Irotech
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Contains UMC umc18 specific pads and ram generators
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.iface.all;
package tech_umc18 is
-- sync ram generator
component umc18_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
address : in std_logic_vector(abits -1 downto 0);
clk : in std_logic;
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_logic;
write : in std_logic);
end component;
-- regfile generator
component umc18_regfile
generic ( abits : integer := 8; dbits : integer := 32; words : integer := 128);
port (
rst : in std_logic;
clk : in clk_type;
clkn : in clk_type;
rfi : in rf_in_type;
rfo : out rf_out_type);
end component;
-- pads
component umc18_inpad
port (pad : in std_logic; q : out std_logic);
end component;
component umc18_smpad
port (pad : in std_logic; q : out std_logic);
end component;
component umc18_outpad
generic (drive : integer := 1);
port (d : in std_logic; pad : out std_logic);
end component;
component umc18_toutpadu
generic (drive : integer := 1);
port (d, en : in std_logic; pad : out std_logic);
end component;
component umc18_iopad
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component umc18_iopadu
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component umc18_iodpad
generic (drive : integer := 1);
port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component umc18_odpad
generic (drive : integer := 1);
port ( d : in std_logic; pad : out std_logic);
end component;
component umc18_smiopad
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
end;
------------------------------------------------------------------
-- behavioural pad models --------------------------------------------
------------------------------------------------------------------
-- Only needed for simulation, not synthesis.
-- pragma translate_off
-- input pad 1xDrive
library IEEE;
use IEEE.std_logic_1164.all;
entity C3I40 is port (PAD : in std_logic; DI : out std_logic); end;
architecture rtl of C3I40 is begin DI <= to_x01(PAD) after 1 ns; end;
-- input schmitt pad 1xDrive
library IEEE;
use IEEE.std_logic_1164.all;
entity C3I42 is port (PAD : in std_logic; DI : out std_logic); end;
architecture rtl of C3I42 is begin DI <= to_x01(PAD) after 1 ns; end;
-- output pad 2mA
library IEEE;
use IEEE.std_logic_1164.all;
entity C3O10 is port (DO : in std_logic; PAD : out std_logic); end;
architecture rtl of C3O10 is begin PAD <= to_x01(DO) after 2 ns; end;
-- output pad 4mA
library IEEE;
use IEEE.std_logic_1164.all;
entity C3O20 is port (DO : in std_logic; PAD : out std_logic); end;
architecture rtl of C3O20 is begin PAD <= to_x01(DO) after 2 ns; end;
-- output pad 8mA
library IEEE;
use IEEE.std_logic_1164.all;
entity C3O40 is port (DO : in std_logic; PAD : out std_logic); end;
architecture rtl of C3O40 is begin PAD <= to_x01(DO) after 2 ns; end;
-- bidirectional pad pullup 2mA, used as tri-state output pad with pull-up *
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B10U is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B10U is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad pullup 4mA, used as tri-state output pad with pull-up *
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B20U is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B20U is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad pullup 8mA, used as tri-state output pad with pull-up *
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B40U is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B40U is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad 2mA *
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B10 is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B10 is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad 4mA *
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B20 is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B20 is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad 8mA *
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B40 is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B40 is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad 2mA with open drain
library IEEE;
use IEEE.std_logic_1164.all;
entity CD3B10T is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of CD3B10T is
begin
PAD <= '0' after 2 ns when (EN and not DO) = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad 4mA with open drain
library IEEE;
use IEEE.std_logic_1164.all;
entity CD3B20T is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of CD3B20T is
begin
PAD <= '0' after 2 ns when (EN and not DO) = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad 8mA with open drain
library IEEE;
use IEEE.std_logic_1164.all;
entity CD3B40T is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of CD3B40T is
begin
PAD <= '0' after 2 ns when (EN and not DO) = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- output pad 2mA with open drain
library IEEE;
use IEEE.std_logic_1164.all;
entity CD3O10T is
port ( DO : in std_logic; PAD : out std_logic);
end;
architecture rtl of CD3O10T is
begin
PAD <= '0' after 2 ns when DO = '0' else 'Z' after 2 ns;
end;
-- output pad 4mA with open drain
library IEEE;
use IEEE.std_logic_1164.all;
entity CD3O20T is
port ( DO : in std_logic; PAD : out std_logic);
end;
architecture rtl of CD3O20T is
begin
PAD <= '0' after 2 ns when DO = '0' else 'Z' after 2 ns;
end;
-- output pad 8mA with open drain
library IEEE;
use IEEE.std_logic_1164.all;
entity CD3O40T is
port ( DO : in std_logic; PAD : out std_logic);
end;
architecture rtl of CD3O40T is
begin
PAD <= '0' after 2 ns when DO = '0' else 'Z' after 2 ns;
end;
-- bidirectional pad 8mA schmitt trigger
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B42 is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B42 is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
------------------------------------------------------------------
-- behavioural ram models ----------------------------------------
------------------------------------------------------------------
-- Address and control latched on rising clka, data latched on falling clkb.
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity umc18_dpram_ss is
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
DI: in std_logic_vector (dbits -1 downto 0);
RADR,WADR: in std_logic_vector (abits -1 downto 0);
REN,WEN : in std_logic;
RCK,WCK : in std_logic;
DOUT: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of umc18_dpram_ss is
signal DI_l,DOUT_l : std_logic_vector (dbits -1 downto 0);
signal RADR_l, WADR_l : std_logic_vector (abits -1 downto 0);
signal REN_l, WEN_l : std_logic;
type dregtype is array (0 to words - 1)
of std_logic_vector(dbits -1 downto 0);
signal data : dregtype;
attribute syn_ramstyle : string;
attribute syn_ramstyle of data: signal is "block_ram";
begin
writeport : process(WCK)
begin
if rising_edge(WCK) then
DI_l <= DI;
WEN_l <= WEN;
WADR_l <= WADR;
end if;
end process;
readport : process(RCK)
begin
if rising_edge(RCK) then
REN_l <= REN;
RADR_l <= RADR;
end if;
end process;
ram : process(DI_l, WEN_l, WADR_l, REN_l, RADR_l, data)
begin
if WEN_l = '0' then
if not ( is_x(WADR_l) or (conv_integer(unsigned(WADR_l)) >= words)) then
data(conv_integer(unsigned(WADR_l))) <= DI_l;
end if;
end if;
if REN_l = '0' then
if not (is_x(RADR_l) or (conv_integer(unsigned(RADR_l)) >= words)) then
DOUT_l <= data(conv_integer(unsigned(RADR_l)));
else
DOUT_l <= (others => 'X');
end if;
else
DOUT_l <= (others => 'Z');
end if;
end process;
DOUT <= DOUT_l;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity umc18_syncram_ss is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
ADR : in std_logic_vector((abits -1) downto 0);
DI : in std_logic_vector((dbits -1) downto 0);
DOUT : out std_logic_vector((dbits -1) downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of umc18_syncram_ss is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
attribute syn_ramstyle : string;
attribute syn_ramstyle of memarr: signal is "block_ram";
signal ADR_l : std_logic_vector((abits -1) downto 0);
signal DI_l : std_logic_vector((dbits -1) downto 0);
signal WEN_l : std_logic;
signal CEN_l : std_logic;
signal DOUT_l : std_logic_vector((dbits -1) downto 0);
begin
input_latch : process(CK)
begin
if rising_edge(CK) then
ADR_l <= ADR;
DI_l <= DI;
WEN_l <= WEN;
CEN_l <= CEN;
end if;
end process;
ram : process(ADR_l,DI_l,WEN_l,CEN_l,memarr)
begin
if CEN_l = '0' then
if WEN_l = '0' then
if not is_x(ADR_l) then
memarr(conv_integer(unsigned(ADR_l))) <= DI_l;
end if;
end if;
if not is_x(ADR_l) then
DOUT_l <= memarr(conv_integer(unsigned(ADR_l)));
else
DOUT_l <= (others => 'X');
end if;
end if;
end process;
DOUT <= DOUT_l when OEN = '0' else (others => 'Z');
end;
-- syncronous umc18 sram
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package tech_umc18_sim is
component umc18_syncram_ss
generic ( abits : integer := 10; dbits : integer := 8 );
port (
ADR : in std_logic_vector((abits -1) downto 0);
DI : in std_logic_vector((dbits -1) downto 0);
DOUT : out std_logic_vector((dbits -1) downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end component;
-- syncronous umc18 dpram
component umc18_dpram_ss
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
DI: in std_logic_vector (dbits -1 downto 0);
RADR: in std_logic_vector (abits -1 downto 0);
WADR: in std_logic_vector (abits -1 downto 0);
REN,WEN : in std_logic;
RCK,WCK : in std_logic;
DOUT: out std_logic_vector (dbits -1 downto 0)
);
end component;
end;
-- Address, control and data signals latched on rising ME.
-- Write enable (WEN) active low.
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R256X24M4 is
port (
ADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(23 downto 0);
DOUT : out std_logic_vector(23 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R256X24M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 8, dbits => 24)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R256X25M4 is
port (
ADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(24 downto 0);
DOUT : out std_logic_vector(24 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R256X25M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 8, dbits => 25)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R256X26M4 is
port (
ADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(25 downto 0);
DOUT : out std_logic_vector(25 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R256X26M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 8, dbits => 26)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R1024X32M4 is
port (
ADR : in std_logic_vector(9 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R1024X32M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 10, dbits => 32)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R1024X33M4 is
port (
ADR : in std_logic_vector(9 downto 0);
DI : in std_logic_vector(32 downto 0);
DOUT : out std_logic_vector(32 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R1024X33M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 10, dbits => 33)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R2048X32M8 is
port (
ADR : in std_logic_vector(10 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R2048X32M8 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 11, dbits => 32)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R256X28M4 is
port (
ADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(27 downto 0);
DOUT : out std_logic_vector(27 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R256X28M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 8, dbits => 28)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R1024X34M4 is
port (
ADR : in std_logic_vector(10 downto 0);
DI : in std_logic_vector(33 downto 0);
DOUT : out std_logic_vector(33 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R1024X34M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 10, dbits => 34)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R2048x34M8 is
port (
ADR : in std_logic_vector(11 downto 0);
DI : in std_logic_vector(33 downto 0);
DOUT : out std_logic_vector(33 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R2048x34M8 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 11, dbits => 34)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity RF68X32M1 is
port ( RCK : in std_logic;
REN : in std_logic;
RADR : in std_logic_vector(6 downto 0);
WCK : in std_logic;
WEN : in std_logic;
WADR : in std_logic_vector(6 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0) );
end;
architecture behav of RF68X32M1 is
begin
dp0 : umc18_dpram_ss
generic map (abits => 7, dbits => 32, words => 68)
port map ( DI => DI, RADR => RADR, WADR => WADR, WEN => WEN,
REN => REN, RCK => RCK, WCK => WCK, DOUT => DOUT);
end;
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity RF68X33M1 is
port ( RCK : in std_logic;
REN : in std_logic;
RADR : in std_logic_vector(6 downto 0);
WCK : in std_logic;
WEN : in std_logic;
WADR : in std_logic_vector(6 downto 0);
DI : in std_logic_vector(32 downto 0);
DOUT : out std_logic_vector(32 downto 0) );
end;
architecture behav of RF68X33M1 is
begin
dp0 : umc18_dpram_ss
generic map (abits => 7, dbits => 33, words => 68)
port map ( DI => DI, RADR => RADR, WADR => WADR, WEN => WEN,
REN => REN, RCK => RCK, WCK => WCK, DOUT => DOUT);
end;
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity RF136X32M1 is
port ( RCK : in std_logic;
REN : in std_logic;
RADR : in std_logic_vector(7 downto 0);
WCK : in std_logic;
WEN : in std_logic;
WADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0) );
end;
architecture behav of RF136X32M1 is
begin
dp0 : umc18_dpram_ss
generic map (abits => 8, dbits => 32, words => 136)
port map ( DI => DI, RADR => RADR, WADR => WADR, WEN => WEN,
REN => REN, RCK => RCK, WCK => WCK, DOUT => DOUT);
end;
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity RF136X33M1 is
port ( RCK : in std_logic;
REN : in std_logic;
RADR : in std_logic_vector(7 downto 0);
WCK : in std_logic;
WEN : in std_logic;
WADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(32 downto 0);
DOUT : out std_logic_vector(32 downto 0) );
end;
architecture behav of RF136X33M1 is
begin
dp0 : umc18_dpram_ss
generic map (abits => 8, dbits => 33, words => 136)
port map ( DI => DI, RADR => RADR, WADR => WADR, WEN => WEN,
REN => REN, RCK => RCK, WCK => WCK, DOUT => DOUT);
end;
-- simple gate models
library IEEE;
use IEEE.std_logic_1164.all;
entity INVDL is port( A : in std_logic; Z : out std_logic); end;
architecture rtl of INVDL is begin Z <= not A; end;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2DL is port( A1, A2 : in std_logic; Z : out std_logic); end;
architecture rtl of AND2DL is begin Z <= A1 and A2; end;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2DL is port( A1, A2 : in std_logic; Z : out std_logic); end;
architecture rtl of OR2DL is begin Z <= A1 or A2; end;
library IEEE;
use IEEE.std_logic_1164.all;
entity EXOR2DL is port( A1, A2 : in std_logic; Z : out std_logic); end;
architecture rtl of EXOR2DL is begin Z <= A1 xor A2; end;
-- pragma translate_on
-- component declarations from true tech library
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package tech_umc18_syn is
component RF136X32M1
port ( RCK : in std_logic;
REN : in std_logic;
RADR : in std_logic_vector(7 downto 0);
WCK : in std_logic;
WEN : in std_logic;
WADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0) );
end component;
component R256X24M4
port ( ADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(23 downto 0);
DOUT : out std_logic_vector(23 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic );
end component;
component R256X26M4
port ( ADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(25 downto 0);
DOUT : out std_logic_vector(25 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic );
end component;
component R1024X32M4
port ( ADR : in std_logic_vector(9 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic );
end component;
component R2048x32M8
port ( ADR : in std_logic_vector(10 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic );
end component;
component C3I40
port (PAD : in std_logic; DI : out std_logic);
end component;
component C3I42
port (PAD : in std_logic; DI : out std_logic);
end component;
component C3O10
port (DO : in std_logic; PAD : out std_logic);
end component;
component C3O20
port (DO : in std_logic; PAD : out std_logic);
end component;
component C3O40
port (DO : in std_logic; PAD : out std_logic);
end component;
component C3B10U
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component C3B20U
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component C3B40U
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component C3B10
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component C3B20
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component C3B40
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component CD3B10T
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component CD3B20T
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component CD3B40T
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component CD3O10T
port ( DO : in std_logic; PAD : out std_logic);
end component;
component CD3O20T
port ( DO : in std_logic; PAD : out std_logic);
end component;
component CD3O40T
port ( DO : in std_logic; PAD : out std_logic);
end component;
component C3B42
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component INVDL port( A : in std_logic; Z : out std_logic); end component;
component AND2DL port( A1, A2 : in std_logic; Z : out std_logic); end component;
component OR2DL port( A1, A2 : in std_logic; Z : out std_logic); end component;
component EXOR2DL port( A1, A2 : in std_logic; Z : out std_logic); end component;
end;
------------------------------------------------------------------
-- sync ram generator --------------------------------------------
------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
address : in std_logic_vector(abits -1 downto 0);
clk : in std_logic;
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_logic;
write : in std_logic
);
end;
architecture rtl of umc18_syncram is
signal gnd : std_logic;
signal wr : std_logic;
signal a : std_logic_vector(19 downto 0);
signal d, q : std_logic_vector(34 downto 0);
constant synopsys_bug : std_logic_vector(37 downto 0) := (others => '0');
begin
wr <= not write;
gnd <= '0';
a(abits -1 downto 0) <= address;
a(abits+1 downto abits) <= synopsys_bug(abits+1 downto abits);
d(dbits -1 downto 0) <= datain;
d(dbits+1 downto dbits) <= synopsys_bug(dbits+1 downto dbits);
dataout <= q(dbits -1 downto 0);
a8d24 : if (abits = 8) and (dbits = 24) generate
id0 : R256X24M4
port map ( ADR => a(7 downto 0), DI => d(23 downto 0),
DOUT => q(23 downto 0), CK => clk, WEN => wr,
CEN => gnd, OEN => gnd);
end generate;
a8d26 : if (abits = 8) and (dbits = 26) generate
id0 : R256X26M4
port map ( ADR => a(7 downto 0), DI => d(25 downto 0),
DOUT => q(25 downto 0), CK => clk, WEN => wr,
CEN => gnd, OEN => gnd);
end generate;
a10d32 : if (abits = 10) and (dbits = 32) generate
id0 : R1024X32M4
port map ( ADR => a(9 downto 0), DI => d(31 downto 0),
DOUT => q(31 downto 0), CK => clk, WEN => wr,
CEN => gnd, OEN => gnd);
end generate;
a11d32 : if (abits = 11) and (dbits = 32) generate
id0 : R2048X32M8
port map ( ADR => a(10 downto 0), DI => d(31 downto 0),
DOUT => q(31 downto 0), CK => clk, WEN => wr,
CEN => gnd, OEN => gnd);
end generate;
end rtl;
------------------------------------------------------------------
-- regfile generator --------------------------------------------
------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.iface.all;
use work.tech_umc18_syn.all;
entity umc18_regfile is
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 128
);
port (
rst : in std_logic;
clk : in clk_type;
clkn : in clk_type;
rfi : in rf_in_type;
rfo : out rf_out_type);
end;
architecture rtl of umc18_regfile is
signal qq1, qq2 : std_logic_vector(dbits-1 downto 0);
signal wen, ren1, ren2 : std_logic;
begin
ren1 <= not rfi.ren1;
ren2 <= not rfi.ren2;
wen <= not rfi.wren;
dp136x32 : if (words = 136) and (dbits = 32) generate
u0: RF136X32M1
port map (RCK => clkn, REN => ren1, RADR => rfi.rd1addr(abits -1 downto 0),
WCK => clk, WEN => wen, WADR => rfi.wraddr(abits -1 downto 0),
DI => rfi.wrdata(dbits -1 downto 0), DOUT => qq1);
u1: RF136X32M1
port map (RCK => clkn, REN => ren2, RADR => rfi.rd2addr(abits -1 downto 0),
WCK => clk, WEN => wen, WADR => rfi.wraddr(abits -1 downto 0),
DI => rfi.wrdata(dbits -1 downto 0), DOUT => qq2);
end generate;
rfo.data1 <= qq1(dbits-1 downto 0);
rfo.data2 <= qq2(dbits-1 downto 0);
end;
------------------------------------------------------------------
-- mapping generic pads on tech pads ---------------------------------
------------------------------------------------------------------
-- input pad
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_inpad is port (pad : in std_logic; q : out std_logic); end;
architecture syn of umc18_inpad is begin
i0 : C3I40 port map (PAD => pad, DI => q);
end;
-- input schmitt pad
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_smpad is port (pad : in std_logic; q : out std_logic); end;
architecture syn of umc18_smpad is begin
i0 : C3I42 port map (PAD => pad, DI => q);
end;
-- output pads
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_outpad is
generic (drive : integer := 1);
port (d : in std_logic; pad : out std_logic);
end;
architecture syn of umc18_outpad is begin
d1 : if drive = 1 generate
u0 : C3O10 port map (PAD => pad, DO => d);
end generate;
d2 : if drive = 2 generate
i0 : C3O20 port map (PAD => pad, DO => d);
end generate;
d3 : if drive > 2 generate
i0 : C3O40 port map (PAD => pad, DO => d);
end generate;
end;
-- tri-state output pads with pull-up
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_toutpadu is
generic (drive : integer := 1);
port (d, en : in std_logic; pad : out std_logic);
end;
architecture syn of umc18_toutpadu is
signal nc,p : std_logic;
begin
d1 : if drive = 1 generate
i0 : C3B10U port map (PAD => p, DO => d, DI => nc, EN => en);
end generate;
d2 : if drive = 2 generate
i0 : C3B20U port map (PAD => p, DO => d, DI => nc, EN => en);
end generate;
d3 : if drive > 2 generate
i0 : C3B40U port map (PAD => p, DO => d, DI => nc, EN => en);
end generate;
pad <= p;
end;
-- bidirectional pad 2/4/8mA 4X
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_iopad is
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end;
architecture syn of umc18_iopad is
signal eni : std_logic;
begin
eni <= not en;
d1 : if drive = 1 generate
i0 : C3B10 port map (PAD => pad, DO => d, EN => eni, DI => q);
end generate;
d2 : if drive = 2 generate
i0 : C3B20 port map (PAD => pad, DO => d, EN => eni, DI => q);
end generate;
d3 : if drive > 2 generate
i0 : C3B40 port map (PAD => pad, DO => d, EN => eni, DI => q);
end generate;
end;
-- bidirectional pad with open-drain
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_iodpad is
generic (drive : integer := 1);
port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
end;
architecture syn of umc18_iodpad is
signal vcc : std_logic;
begin
vcc <= '1';
d1 : if drive = 1 generate
i0 : CD3B10T port map (PAD => pad, DO => d, EN => vcc, DI => q);
end generate;
d2 : if drive = 2 generate
i0 : CD3B20T port map (PAD => pad, DO => d, EN => vcc, DI => q);
end generate;
d3 : if drive > 2 generate
i0 : CD3B40T port map (PAD => pad, DO => d, EN => vcc, DI => q);
end generate;
end;
-- output pad with open-drain
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_odpad is
generic (drive : integer := 1);
port (d : in std_logic; pad : out std_logic);
end;
architecture syn of umc18_odpad is
begin
d1 : if drive = 1 generate
i0 : CD3O10T port map (PAD => pad, DO => d);
end generate;
d2 : if drive = 2 generate
i0 : CD3O20T port map (PAD => pad, DO => d);
end generate;
d3 : if drive > 2 generate
i0 : CD3O40T port map (PAD => pad, DO => d);
end generate;
end;
-- bidirectional pad 8mA 4X schmitt trigger
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_smiopad is
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end;
architecture syn of umc18_smiopad is
signal eni : std_logic;
begin
eni <= not en;
i0 : C3B42 port map (PAD => pad, DO => d, EN => eni, DI => q);
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: tech_umc18
-- File: tech_umc18.vhd
-- Author: Raijmond Keulen, Irotech
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Contains UMC umc18 specific pads and ram generators
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.iface.all;
package tech_umc18 is
-- sync ram generator
component umc18_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
address : in std_logic_vector(abits -1 downto 0);
clk : in std_logic;
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_logic;
write : in std_logic);
end component;
-- regfile generator
component umc18_regfile
generic ( abits : integer := 8; dbits : integer := 32; words : integer := 128);
port (
rst : in std_logic;
clk : in clk_type;
clkn : in clk_type;
rfi : in rf_in_type;
rfo : out rf_out_type);
end component;
-- pads
component umc18_inpad
port (pad : in std_logic; q : out std_logic);
end component;
component umc18_smpad
port (pad : in std_logic; q : out std_logic);
end component;
component umc18_outpad
generic (drive : integer := 1);
port (d : in std_logic; pad : out std_logic);
end component;
component umc18_toutpadu
generic (drive : integer := 1);
port (d, en : in std_logic; pad : out std_logic);
end component;
component umc18_iopad
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component umc18_iopadu
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component umc18_iodpad
generic (drive : integer := 1);
port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component umc18_odpad
generic (drive : integer := 1);
port ( d : in std_logic; pad : out std_logic);
end component;
component umc18_smiopad
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
end;
------------------------------------------------------------------
-- behavioural pad models --------------------------------------------
------------------------------------------------------------------
-- Only needed for simulation, not synthesis.
-- pragma translate_off
-- input pad 1xDrive
library IEEE;
use IEEE.std_logic_1164.all;
entity C3I40 is port (PAD : in std_logic; DI : out std_logic); end;
architecture rtl of C3I40 is begin DI <= to_x01(PAD) after 1 ns; end;
-- input schmitt pad 1xDrive
library IEEE;
use IEEE.std_logic_1164.all;
entity C3I42 is port (PAD : in std_logic; DI : out std_logic); end;
architecture rtl of C3I42 is begin DI <= to_x01(PAD) after 1 ns; end;
-- output pad 2mA
library IEEE;
use IEEE.std_logic_1164.all;
entity C3O10 is port (DO : in std_logic; PAD : out std_logic); end;
architecture rtl of C3O10 is begin PAD <= to_x01(DO) after 2 ns; end;
-- output pad 4mA
library IEEE;
use IEEE.std_logic_1164.all;
entity C3O20 is port (DO : in std_logic; PAD : out std_logic); end;
architecture rtl of C3O20 is begin PAD <= to_x01(DO) after 2 ns; end;
-- output pad 8mA
library IEEE;
use IEEE.std_logic_1164.all;
entity C3O40 is port (DO : in std_logic; PAD : out std_logic); end;
architecture rtl of C3O40 is begin PAD <= to_x01(DO) after 2 ns; end;
-- bidirectional pad pullup 2mA, used as tri-state output pad with pull-up *
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B10U is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B10U is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad pullup 4mA, used as tri-state output pad with pull-up *
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B20U is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B20U is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad pullup 8mA, used as tri-state output pad with pull-up *
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B40U is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B40U is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad 2mA *
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B10 is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B10 is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad 4mA *
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B20 is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B20 is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad 8mA *
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B40 is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B40 is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad 2mA with open drain
library IEEE;
use IEEE.std_logic_1164.all;
entity CD3B10T is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of CD3B10T is
begin
PAD <= '0' after 2 ns when (EN and not DO) = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad 4mA with open drain
library IEEE;
use IEEE.std_logic_1164.all;
entity CD3B20T is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of CD3B20T is
begin
PAD <= '0' after 2 ns when (EN and not DO) = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- bidirectional pad 8mA with open drain
library IEEE;
use IEEE.std_logic_1164.all;
entity CD3B40T is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of CD3B40T is
begin
PAD <= '0' after 2 ns when (EN and not DO) = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
-- output pad 2mA with open drain
library IEEE;
use IEEE.std_logic_1164.all;
entity CD3O10T is
port ( DO : in std_logic; PAD : out std_logic);
end;
architecture rtl of CD3O10T is
begin
PAD <= '0' after 2 ns when DO = '0' else 'Z' after 2 ns;
end;
-- output pad 4mA with open drain
library IEEE;
use IEEE.std_logic_1164.all;
entity CD3O20T is
port ( DO : in std_logic; PAD : out std_logic);
end;
architecture rtl of CD3O20T is
begin
PAD <= '0' after 2 ns when DO = '0' else 'Z' after 2 ns;
end;
-- output pad 8mA with open drain
library IEEE;
use IEEE.std_logic_1164.all;
entity CD3O40T is
port ( DO : in std_logic; PAD : out std_logic);
end;
architecture rtl of CD3O40T is
begin
PAD <= '0' after 2 ns when DO = '0' else 'Z' after 2 ns;
end;
-- bidirectional pad 8mA schmitt trigger
library IEEE;
use IEEE.std_logic_1164.all;
entity C3B42 is
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end;
architecture rtl of C3B42 is
begin
PAD <= to_x01(DO) after 2 ns when EN = '1' else 'Z' after 2 ns;
DI <= to_x01(PAD) after 2 ns;
end;
------------------------------------------------------------------
-- behavioural ram models ----------------------------------------
------------------------------------------------------------------
-- Address and control latched on rising clka, data latched on falling clkb.
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity umc18_dpram_ss is
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
DI: in std_logic_vector (dbits -1 downto 0);
RADR,WADR: in std_logic_vector (abits -1 downto 0);
REN,WEN : in std_logic;
RCK,WCK : in std_logic;
DOUT: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of umc18_dpram_ss is
signal DI_l,DOUT_l : std_logic_vector (dbits -1 downto 0);
signal RADR_l, WADR_l : std_logic_vector (abits -1 downto 0);
signal REN_l, WEN_l : std_logic;
type dregtype is array (0 to words - 1)
of std_logic_vector(dbits -1 downto 0);
signal data : dregtype;
attribute syn_ramstyle : string;
attribute syn_ramstyle of data: signal is "block_ram";
begin
writeport : process(WCK)
begin
if rising_edge(WCK) then
DI_l <= DI;
WEN_l <= WEN;
WADR_l <= WADR;
end if;
end process;
readport : process(RCK)
begin
if rising_edge(RCK) then
REN_l <= REN;
RADR_l <= RADR;
end if;
end process;
ram : process(DI_l, WEN_l, WADR_l, REN_l, RADR_l, data)
begin
if WEN_l = '0' then
if not ( is_x(WADR_l) or (conv_integer(unsigned(WADR_l)) >= words)) then
data(conv_integer(unsigned(WADR_l))) <= DI_l;
end if;
end if;
if REN_l = '0' then
if not (is_x(RADR_l) or (conv_integer(unsigned(RADR_l)) >= words)) then
DOUT_l <= data(conv_integer(unsigned(RADR_l)));
else
DOUT_l <= (others => 'X');
end if;
else
DOUT_l <= (others => 'Z');
end if;
end process;
DOUT <= DOUT_l;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity umc18_syncram_ss is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
ADR : in std_logic_vector((abits -1) downto 0);
DI : in std_logic_vector((dbits -1) downto 0);
DOUT : out std_logic_vector((dbits -1) downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of umc18_syncram_ss is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
attribute syn_ramstyle : string;
attribute syn_ramstyle of memarr: signal is "block_ram";
signal ADR_l : std_logic_vector((abits -1) downto 0);
signal DI_l : std_logic_vector((dbits -1) downto 0);
signal WEN_l : std_logic;
signal CEN_l : std_logic;
signal DOUT_l : std_logic_vector((dbits -1) downto 0);
begin
input_latch : process(CK)
begin
if rising_edge(CK) then
ADR_l <= ADR;
DI_l <= DI;
WEN_l <= WEN;
CEN_l <= CEN;
end if;
end process;
ram : process(ADR_l,DI_l,WEN_l,CEN_l,memarr)
begin
if CEN_l = '0' then
if WEN_l = '0' then
if not is_x(ADR_l) then
memarr(conv_integer(unsigned(ADR_l))) <= DI_l;
end if;
end if;
if not is_x(ADR_l) then
DOUT_l <= memarr(conv_integer(unsigned(ADR_l)));
else
DOUT_l <= (others => 'X');
end if;
end if;
end process;
DOUT <= DOUT_l when OEN = '0' else (others => 'Z');
end;
-- syncronous umc18 sram
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package tech_umc18_sim is
component umc18_syncram_ss
generic ( abits : integer := 10; dbits : integer := 8 );
port (
ADR : in std_logic_vector((abits -1) downto 0);
DI : in std_logic_vector((dbits -1) downto 0);
DOUT : out std_logic_vector((dbits -1) downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end component;
-- syncronous umc18 dpram
component umc18_dpram_ss
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
DI: in std_logic_vector (dbits -1 downto 0);
RADR: in std_logic_vector (abits -1 downto 0);
WADR: in std_logic_vector (abits -1 downto 0);
REN,WEN : in std_logic;
RCK,WCK : in std_logic;
DOUT: out std_logic_vector (dbits -1 downto 0)
);
end component;
end;
-- Address, control and data signals latched on rising ME.
-- Write enable (WEN) active low.
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R256X24M4 is
port (
ADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(23 downto 0);
DOUT : out std_logic_vector(23 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R256X24M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 8, dbits => 24)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R256X25M4 is
port (
ADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(24 downto 0);
DOUT : out std_logic_vector(24 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R256X25M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 8, dbits => 25)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R256X26M4 is
port (
ADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(25 downto 0);
DOUT : out std_logic_vector(25 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R256X26M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 8, dbits => 26)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R1024X32M4 is
port (
ADR : in std_logic_vector(9 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R1024X32M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 10, dbits => 32)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R1024X33M4 is
port (
ADR : in std_logic_vector(9 downto 0);
DI : in std_logic_vector(32 downto 0);
DOUT : out std_logic_vector(32 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R1024X33M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 10, dbits => 33)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R2048X32M8 is
port (
ADR : in std_logic_vector(10 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R2048X32M8 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 11, dbits => 32)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R256X28M4 is
port (
ADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(27 downto 0);
DOUT : out std_logic_vector(27 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R256X28M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 8, dbits => 28)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R1024X34M4 is
port (
ADR : in std_logic_vector(10 downto 0);
DI : in std_logic_vector(33 downto 0);
DOUT : out std_logic_vector(33 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R1024X34M4 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 10, dbits => 34)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity R2048x34M8 is
port (
ADR : in std_logic_vector(11 downto 0);
DI : in std_logic_vector(33 downto 0);
DOUT : out std_logic_vector(33 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic
);
end;
architecture behavioral of R2048x34M8 is
begin
syncram0 : umc18_syncram_ss
generic map ( abits => 11, dbits => 34)
port map ( ADR => ADR, DI => DI, DOUT => DOUT, CK => CK,
WEN => WEN, CEN => CEN, OEN => OEN);
end behavioral;
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity RF68X32M1 is
port ( RCK : in std_logic;
REN : in std_logic;
RADR : in std_logic_vector(6 downto 0);
WCK : in std_logic;
WEN : in std_logic;
WADR : in std_logic_vector(6 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0) );
end;
architecture behav of RF68X32M1 is
begin
dp0 : umc18_dpram_ss
generic map (abits => 7, dbits => 32, words => 68)
port map ( DI => DI, RADR => RADR, WADR => WADR, WEN => WEN,
REN => REN, RCK => RCK, WCK => WCK, DOUT => DOUT);
end;
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity RF68X33M1 is
port ( RCK : in std_logic;
REN : in std_logic;
RADR : in std_logic_vector(6 downto 0);
WCK : in std_logic;
WEN : in std_logic;
WADR : in std_logic_vector(6 downto 0);
DI : in std_logic_vector(32 downto 0);
DOUT : out std_logic_vector(32 downto 0) );
end;
architecture behav of RF68X33M1 is
begin
dp0 : umc18_dpram_ss
generic map (abits => 7, dbits => 33, words => 68)
port map ( DI => DI, RADR => RADR, WADR => WADR, WEN => WEN,
REN => REN, RCK => RCK, WCK => WCK, DOUT => DOUT);
end;
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity RF136X32M1 is
port ( RCK : in std_logic;
REN : in std_logic;
RADR : in std_logic_vector(7 downto 0);
WCK : in std_logic;
WEN : in std_logic;
WADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0) );
end;
architecture behav of RF136X32M1 is
begin
dp0 : umc18_dpram_ss
generic map (abits => 8, dbits => 32, words => 136)
port map ( DI => DI, RADR => RADR, WADR => WADR, WEN => WEN,
REN => REN, RCK => RCK, WCK => WCK, DOUT => DOUT);
end;
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.tech_umc18_sim.all;
entity RF136X33M1 is
port ( RCK : in std_logic;
REN : in std_logic;
RADR : in std_logic_vector(7 downto 0);
WCK : in std_logic;
WEN : in std_logic;
WADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(32 downto 0);
DOUT : out std_logic_vector(32 downto 0) );
end;
architecture behav of RF136X33M1 is
begin
dp0 : umc18_dpram_ss
generic map (abits => 8, dbits => 33, words => 136)
port map ( DI => DI, RADR => RADR, WADR => WADR, WEN => WEN,
REN => REN, RCK => RCK, WCK => WCK, DOUT => DOUT);
end;
-- simple gate models
library IEEE;
use IEEE.std_logic_1164.all;
entity INVDL is port( A : in std_logic; Z : out std_logic); end;
architecture rtl of INVDL is begin Z <= not A; end;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2DL is port( A1, A2 : in std_logic; Z : out std_logic); end;
architecture rtl of AND2DL is begin Z <= A1 and A2; end;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2DL is port( A1, A2 : in std_logic; Z : out std_logic); end;
architecture rtl of OR2DL is begin Z <= A1 or A2; end;
library IEEE;
use IEEE.std_logic_1164.all;
entity EXOR2DL is port( A1, A2 : in std_logic; Z : out std_logic); end;
architecture rtl of EXOR2DL is begin Z <= A1 xor A2; end;
-- pragma translate_on
-- component declarations from true tech library
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package tech_umc18_syn is
component RF136X32M1
port ( RCK : in std_logic;
REN : in std_logic;
RADR : in std_logic_vector(7 downto 0);
WCK : in std_logic;
WEN : in std_logic;
WADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0) );
end component;
component R256X24M4
port ( ADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(23 downto 0);
DOUT : out std_logic_vector(23 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic );
end component;
component R256X26M4
port ( ADR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(25 downto 0);
DOUT : out std_logic_vector(25 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic );
end component;
component R1024X32M4
port ( ADR : in std_logic_vector(9 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic );
end component;
component R2048x32M8
port ( ADR : in std_logic_vector(10 downto 0);
DI : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0);
CK : in std_logic;
WEN : in std_logic;
CEN : in std_logic;
OEN : in std_logic );
end component;
component C3I40
port (PAD : in std_logic; DI : out std_logic);
end component;
component C3I42
port (PAD : in std_logic; DI : out std_logic);
end component;
component C3O10
port (DO : in std_logic; PAD : out std_logic);
end component;
component C3O20
port (DO : in std_logic; PAD : out std_logic);
end component;
component C3O40
port (DO : in std_logic; PAD : out std_logic);
end component;
component C3B10U
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component C3B20U
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component C3B40U
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component C3B10
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component C3B20
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component C3B40
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component CD3B10T
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component CD3B20T
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component CD3B40T
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component CD3O10T
port ( DO : in std_logic; PAD : out std_logic);
end component;
component CD3O20T
port ( DO : in std_logic; PAD : out std_logic);
end component;
component CD3O40T
port ( DO : in std_logic; PAD : out std_logic);
end component;
component C3B42
port ( DO, EN : in std_logic; DI : out std_logic; PAD : inout std_logic);
end component;
component INVDL port( A : in std_logic; Z : out std_logic); end component;
component AND2DL port( A1, A2 : in std_logic; Z : out std_logic); end component;
component OR2DL port( A1, A2 : in std_logic; Z : out std_logic); end component;
component EXOR2DL port( A1, A2 : in std_logic; Z : out std_logic); end component;
end;
------------------------------------------------------------------
-- sync ram generator --------------------------------------------
------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
address : in std_logic_vector(abits -1 downto 0);
clk : in std_logic;
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_logic;
write : in std_logic
);
end;
architecture rtl of umc18_syncram is
signal gnd : std_logic;
signal wr : std_logic;
signal a : std_logic_vector(19 downto 0);
signal d, q : std_logic_vector(34 downto 0);
constant synopsys_bug : std_logic_vector(37 downto 0) := (others => '0');
begin
wr <= not write;
gnd <= '0';
a(abits -1 downto 0) <= address;
a(abits+1 downto abits) <= synopsys_bug(abits+1 downto abits);
d(dbits -1 downto 0) <= datain;
d(dbits+1 downto dbits) <= synopsys_bug(dbits+1 downto dbits);
dataout <= q(dbits -1 downto 0);
a8d24 : if (abits = 8) and (dbits = 24) generate
id0 : R256X24M4
port map ( ADR => a(7 downto 0), DI => d(23 downto 0),
DOUT => q(23 downto 0), CK => clk, WEN => wr,
CEN => gnd, OEN => gnd);
end generate;
a8d26 : if (abits = 8) and (dbits = 26) generate
id0 : R256X26M4
port map ( ADR => a(7 downto 0), DI => d(25 downto 0),
DOUT => q(25 downto 0), CK => clk, WEN => wr,
CEN => gnd, OEN => gnd);
end generate;
a10d32 : if (abits = 10) and (dbits = 32) generate
id0 : R1024X32M4
port map ( ADR => a(9 downto 0), DI => d(31 downto 0),
DOUT => q(31 downto 0), CK => clk, WEN => wr,
CEN => gnd, OEN => gnd);
end generate;
a11d32 : if (abits = 11) and (dbits = 32) generate
id0 : R2048X32M8
port map ( ADR => a(10 downto 0), DI => d(31 downto 0),
DOUT => q(31 downto 0), CK => clk, WEN => wr,
CEN => gnd, OEN => gnd);
end generate;
end rtl;
------------------------------------------------------------------
-- regfile generator --------------------------------------------
------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.iface.all;
use work.tech_umc18_syn.all;
entity umc18_regfile is
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 128
);
port (
rst : in std_logic;
clk : in clk_type;
clkn : in clk_type;
rfi : in rf_in_type;
rfo : out rf_out_type);
end;
architecture rtl of umc18_regfile is
signal qq1, qq2 : std_logic_vector(dbits-1 downto 0);
signal wen, ren1, ren2 : std_logic;
begin
ren1 <= not rfi.ren1;
ren2 <= not rfi.ren2;
wen <= not rfi.wren;
dp136x32 : if (words = 136) and (dbits = 32) generate
u0: RF136X32M1
port map (RCK => clkn, REN => ren1, RADR => rfi.rd1addr(abits -1 downto 0),
WCK => clk, WEN => wen, WADR => rfi.wraddr(abits -1 downto 0),
DI => rfi.wrdata(dbits -1 downto 0), DOUT => qq1);
u1: RF136X32M1
port map (RCK => clkn, REN => ren2, RADR => rfi.rd2addr(abits -1 downto 0),
WCK => clk, WEN => wen, WADR => rfi.wraddr(abits -1 downto 0),
DI => rfi.wrdata(dbits -1 downto 0), DOUT => qq2);
end generate;
rfo.data1 <= qq1(dbits-1 downto 0);
rfo.data2 <= qq2(dbits-1 downto 0);
end;
------------------------------------------------------------------
-- mapping generic pads on tech pads ---------------------------------
------------------------------------------------------------------
-- input pad
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_inpad is port (pad : in std_logic; q : out std_logic); end;
architecture syn of umc18_inpad is begin
i0 : C3I40 port map (PAD => pad, DI => q);
end;
-- input schmitt pad
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_smpad is port (pad : in std_logic; q : out std_logic); end;
architecture syn of umc18_smpad is begin
i0 : C3I42 port map (PAD => pad, DI => q);
end;
-- output pads
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_outpad is
generic (drive : integer := 1);
port (d : in std_logic; pad : out std_logic);
end;
architecture syn of umc18_outpad is begin
d1 : if drive = 1 generate
u0 : C3O10 port map (PAD => pad, DO => d);
end generate;
d2 : if drive = 2 generate
i0 : C3O20 port map (PAD => pad, DO => d);
end generate;
d3 : if drive > 2 generate
i0 : C3O40 port map (PAD => pad, DO => d);
end generate;
end;
-- tri-state output pads with pull-up
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_toutpadu is
generic (drive : integer := 1);
port (d, en : in std_logic; pad : out std_logic);
end;
architecture syn of umc18_toutpadu is
signal nc,p : std_logic;
begin
d1 : if drive = 1 generate
i0 : C3B10U port map (PAD => p, DO => d, DI => nc, EN => en);
end generate;
d2 : if drive = 2 generate
i0 : C3B20U port map (PAD => p, DO => d, DI => nc, EN => en);
end generate;
d3 : if drive > 2 generate
i0 : C3B40U port map (PAD => p, DO => d, DI => nc, EN => en);
end generate;
pad <= p;
end;
-- bidirectional pad 2/4/8mA 4X
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_iopad is
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end;
architecture syn of umc18_iopad is
signal eni : std_logic;
begin
eni <= not en;
d1 : if drive = 1 generate
i0 : C3B10 port map (PAD => pad, DO => d, EN => eni, DI => q);
end generate;
d2 : if drive = 2 generate
i0 : C3B20 port map (PAD => pad, DO => d, EN => eni, DI => q);
end generate;
d3 : if drive > 2 generate
i0 : C3B40 port map (PAD => pad, DO => d, EN => eni, DI => q);
end generate;
end;
-- bidirectional pad with open-drain
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_iodpad is
generic (drive : integer := 1);
port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
end;
architecture syn of umc18_iodpad is
signal vcc : std_logic;
begin
vcc <= '1';
d1 : if drive = 1 generate
i0 : CD3B10T port map (PAD => pad, DO => d, EN => vcc, DI => q);
end generate;
d2 : if drive = 2 generate
i0 : CD3B20T port map (PAD => pad, DO => d, EN => vcc, DI => q);
end generate;
d3 : if drive > 2 generate
i0 : CD3B40T port map (PAD => pad, DO => d, EN => vcc, DI => q);
end generate;
end;
-- output pad with open-drain
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_odpad is
generic (drive : integer := 1);
port (d : in std_logic; pad : out std_logic);
end;
architecture syn of umc18_odpad is
begin
d1 : if drive = 1 generate
i0 : CD3O10T port map (PAD => pad, DO => d);
end generate;
d2 : if drive = 2 generate
i0 : CD3O20T port map (PAD => pad, DO => d);
end generate;
d3 : if drive > 2 generate
i0 : CD3O40T port map (PAD => pad, DO => d);
end generate;
end;
-- bidirectional pad 8mA 4X schmitt trigger
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_umc18_syn.all;
entity umc18_smiopad is
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end;
architecture syn of umc18_smiopad is
signal eni : std_logic;
begin
eni <= not en;
i0 : C3B42 port map (PAD => pad, DO => d, EN => eni, DI => q);
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Oct 17 02:51:11 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top RAT_xlslice_0_0 -prefix
-- RAT_xlslice_0_0_ RAT_slice_1_0_0_stub.vhdl
-- Design : RAT_slice_1_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RAT_xlslice_0_0 is
Port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end RAT_xlslice_0_0;
architecture stub of RAT_xlslice_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "Din[17:0],Dout[9:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "xlslice,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Oct 17 02:51:11 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top RAT_xlslice_0_0 -prefix
-- RAT_xlslice_0_0_ RAT_slice_1_0_0_stub.vhdl
-- Design : RAT_slice_1_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RAT_xlslice_0_0 is
Port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end RAT_xlslice_0_0;
architecture stub of RAT_xlslice_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "Din[17:0],Dout[9:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "xlslice,Vivado 2016.4";
begin
end;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20000)
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`protect end_protected
|
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ZynqDesign_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
leds_8bits_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
sws_8bits_tri_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end ZynqDesign_wrapper;
architecture STRUCTURE of ZynqDesign_wrapper is
component ZynqDesign is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
leds_8bits_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
sws_8bits_tri_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component ZynqDesign;
begin
ZynqDesign_i: component ZynqDesign
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
leds_8bits_tri_o(7 downto 0) => leds_8bits_tri_o(7 downto 0),
sws_8bits_tri_i(7 downto 0) => sws_8bits_tri_i(7 downto 0)
);
end STRUCTURE;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Declaration and implementation of the types_common package.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
--! @brief Definition of the generic VHDL methods and constants.
--! @details This package defines common mathematical methods and
--! utility methods for the VHDL types conversions.
package types_common is
--! @brief Array declaration of the pre-computed log2 values.
type log2arr is array(0 to 512) of integer;
--! @brief Array definition of the pre-computed log2 values.
--! @details These values are used as an argument in bus width
--! declaration.
--!
--! Example usage:
--! @code
--! component foo_component is
--! generic (
--! max_clients : integer := 8
--! );
--! port (
--! foo : inout std_logic_vector(log2(max_clients)-1 downto 0)
--! );
--! end component;
--! @endcode
constant log2 : log2arr := (
0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
others => 9);
constant log2x : log2arr := (
0,1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
others => 9);
constant zero32 : std_logic_vector(31 downto 0) := X"00000000";
constant zero64 : std_logic_vector(63 downto 0) := zero32 & zero32;
function "-" (i : integer; d : std_logic_vector) return std_logic_vector;
function "-" (d : std_logic_vector; i : integer) return std_logic_vector;
function "-" (a, b : std_logic_vector) return std_logic_vector;
function "+" (d : std_logic_vector; i : integer) return std_logic_vector;
function "+" (a, b : std_logic_vector) return std_logic_vector;
function "+" (d : std_logic_vector; i : std_ulogic) return std_logic_vector;
function conv_integer(v : std_logic_vector) return integer;
function conv_integer(v : std_logic) return integer;
function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector;
function conv_std_logic_vector_signed(i : integer; w : integer) return std_logic_vector;
function conv_std_logic(b : boolean) return std_ulogic;
end;
package body types_common is
function conv_integer(v : std_logic_vector) return integer is
begin
if not is_x(v) then return(to_integer(unsigned(v)));
else return(0); end if;
end;
function conv_integer(v : std_logic) return integer is
begin
if not is_x(v) then
if v = '1' then return(1);
else return(0); end if;
else return(0); end if;
end;
function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector is
variable tmp : std_logic_vector(w-1 downto 0);
begin
tmp := std_logic_vector(to_unsigned(i, w));
return(tmp);
end;
function conv_std_logic_vector_signed(i : integer; w : integer) return std_logic_vector is
variable tmp : std_logic_vector(w-1 downto 0);
begin
tmp := std_logic_vector(to_signed(i, w));
return(tmp);
end;
function conv_std_logic(b : boolean) return std_ulogic is
begin
if b then return('1'); else return('0'); end if;
end;
function "+" (d : std_logic_vector; i : integer) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
-- pragma translate_off
if not is_x(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) + i));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "+" (a, b : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(a'length-1 downto 0);
variable y : std_logic_vector(b'length-1 downto 0);
begin
-- pragma translate_off
if not is_x(a&b) then
-- pragma translate_on
return(std_logic_vector(unsigned(a) + unsigned(b)));
-- pragma translate_off
else
x := (others =>'X'); y := (others =>'X');
if (x'length > y'length) then return(x); else return(y); end if;
end if;
-- pragma translate_on
end;
function "+" (d : std_logic_vector; i : std_ulogic) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
variable y : std_logic_vector(0 downto 0);
begin
y(0) := i;
-- pragma translate_off
if not is_x(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) + unsigned(y)));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "-" (i : integer; d : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
-- pragma translate_off
if not is_x(d) then
-- pragma translate_on
return(std_logic_vector(i - unsigned(d)));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "-" (d : std_logic_vector; i : integer) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
-- pragma translate_off
if not is_x(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) - i));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "-" (a, b : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(a'length-1 downto 0);
variable y : std_logic_vector(b'length-1 downto 0);
begin
-- pragma translate_off
if not is_x(a&b) then
-- pragma translate_on
return(std_logic_vector(unsigned(a) - unsigned(b)));
-- pragma translate_off
else
x := (others =>'X'); y := (others =>'X');
if (x'length > y'length) then return(x); else return(y); end if;
end if;
-- pragma translate_on
end;
end;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Declaration and implementation of the types_common package.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
--! @brief Definition of the generic VHDL methods and constants.
--! @details This package defines common mathematical methods and
--! utility methods for the VHDL types conversions.
package types_common is
--! @brief Array declaration of the pre-computed log2 values.
type log2arr is array(0 to 512) of integer;
--! @brief Array definition of the pre-computed log2 values.
--! @details These values are used as an argument in bus width
--! declaration.
--!
--! Example usage:
--! @code
--! component foo_component is
--! generic (
--! max_clients : integer := 8
--! );
--! port (
--! foo : inout std_logic_vector(log2(max_clients)-1 downto 0)
--! );
--! end component;
--! @endcode
constant log2 : log2arr := (
0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
others => 9);
constant log2x : log2arr := (
0,1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
others => 9);
constant zero32 : std_logic_vector(31 downto 0) := X"00000000";
constant zero64 : std_logic_vector(63 downto 0) := zero32 & zero32;
function "-" (i : integer; d : std_logic_vector) return std_logic_vector;
function "-" (d : std_logic_vector; i : integer) return std_logic_vector;
function "-" (a, b : std_logic_vector) return std_logic_vector;
function "+" (d : std_logic_vector; i : integer) return std_logic_vector;
function "+" (a, b : std_logic_vector) return std_logic_vector;
function "+" (d : std_logic_vector; i : std_ulogic) return std_logic_vector;
function conv_integer(v : std_logic_vector) return integer;
function conv_integer(v : std_logic) return integer;
function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector;
function conv_std_logic_vector_signed(i : integer; w : integer) return std_logic_vector;
function conv_std_logic(b : boolean) return std_ulogic;
end;
package body types_common is
function conv_integer(v : std_logic_vector) return integer is
begin
if not is_x(v) then return(to_integer(unsigned(v)));
else return(0); end if;
end;
function conv_integer(v : std_logic) return integer is
begin
if not is_x(v) then
if v = '1' then return(1);
else return(0); end if;
else return(0); end if;
end;
function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector is
variable tmp : std_logic_vector(w-1 downto 0);
begin
tmp := std_logic_vector(to_unsigned(i, w));
return(tmp);
end;
function conv_std_logic_vector_signed(i : integer; w : integer) return std_logic_vector is
variable tmp : std_logic_vector(w-1 downto 0);
begin
tmp := std_logic_vector(to_signed(i, w));
return(tmp);
end;
function conv_std_logic(b : boolean) return std_ulogic is
begin
if b then return('1'); else return('0'); end if;
end;
function "+" (d : std_logic_vector; i : integer) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
-- pragma translate_off
if not is_x(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) + i));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "+" (a, b : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(a'length-1 downto 0);
variable y : std_logic_vector(b'length-1 downto 0);
begin
-- pragma translate_off
if not is_x(a&b) then
-- pragma translate_on
return(std_logic_vector(unsigned(a) + unsigned(b)));
-- pragma translate_off
else
x := (others =>'X'); y := (others =>'X');
if (x'length > y'length) then return(x); else return(y); end if;
end if;
-- pragma translate_on
end;
function "+" (d : std_logic_vector; i : std_ulogic) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
variable y : std_logic_vector(0 downto 0);
begin
y(0) := i;
-- pragma translate_off
if not is_x(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) + unsigned(y)));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "-" (i : integer; d : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
-- pragma translate_off
if not is_x(d) then
-- pragma translate_on
return(std_logic_vector(i - unsigned(d)));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "-" (d : std_logic_vector; i : integer) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
-- pragma translate_off
if not is_x(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) - i));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "-" (a, b : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(a'length-1 downto 0);
variable y : std_logic_vector(b'length-1 downto 0);
begin
-- pragma translate_off
if not is_x(a&b) then
-- pragma translate_on
return(std_logic_vector(unsigned(a) - unsigned(b)));
-- pragma translate_off
else
x := (others =>'X'); y := (others =>'X');
if (x'length > y'length) then return(x); else return(y); end if;
end if;
-- pragma translate_on
end;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc675.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:59 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:30 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:38 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00675ent IS
END c03s04b01x00p23n01i00675ent;
ARCHITECTURE c03s04b01x00p23n01i00675arch OF c03s04b01x00p23n01i00675ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type SWITCH_LEVEL is ( '0', '1', 'Z' );
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
type FT is file of LOGIC_SWITCH;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.49";
-- Declare a variable into which we will read.
constant CON : LOGIC_SWITCH := '1';
variable VAR : LOGIC_SWITCH ;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00675"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00675 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00675arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc675.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:59 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:30 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:38 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00675ent IS
END c03s04b01x00p23n01i00675ent;
ARCHITECTURE c03s04b01x00p23n01i00675arch OF c03s04b01x00p23n01i00675ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type SWITCH_LEVEL is ( '0', '1', 'Z' );
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
type FT is file of LOGIC_SWITCH;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.49";
-- Declare a variable into which we will read.
constant CON : LOGIC_SWITCH := '1';
variable VAR : LOGIC_SWITCH ;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00675"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00675 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00675arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc675.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:59 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:30 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:38 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00675ent IS
END c03s04b01x00p23n01i00675ent;
ARCHITECTURE c03s04b01x00p23n01i00675arch OF c03s04b01x00p23n01i00675ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type SWITCH_LEVEL is ( '0', '1', 'Z' );
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
type FT is file of LOGIC_SWITCH;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.49";
-- Declare a variable into which we will read.
constant CON : LOGIC_SWITCH := '1';
variable VAR : LOGIC_SWITCH ;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00675"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00675 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00675arch;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the MM2S
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-- system signals
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- dma control and sg engine status signals --
mm2s_run_stop : in std_logic ; --
--
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_cmnd_idle : in std_logic ; --
mm2s_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
mm2s_stop : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
--
-- system state and control --
mm2s_all_idle : out std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic --
);
end axi_dma_mm2s_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal mm2s_datamover_idle : std_logic := '0';
signal mm2s_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal mm2s_halt_cmpt_cdc_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_cdc_d2 : SIGNAL IS "true";
signal mm2s_halt_cmpt_d2 : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Everything is idle when everything is idle
all_is_idle <= mm2s_ftch_idle
and mm2s_updt_idle
and mm2s_cmnd_idle
and mm2s_sts_idle;
-- Pass out for soft reset use
mm2s_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
AWVLD_CDC_TO : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => mm2s_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- mm2s_halt_cmpt_d1_cdc_tig <= '0';
-- -- mm2s_halt_cmpt_d2 <= '0';
-- -- else
-- mm2s_halt_cmpt_d1_cdc_tig <= mm2s_halt_cmplt;
-- mm2s_halt_cmpt_cdc_d2 <= mm2s_halt_cmpt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
mm2s_halt_cmpt_d2 <= mm2s_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
mm2s_halt_cmpt_d2 <= mm2s_halt_cmplt;
end generate GEN_FOR_SYNC;
mm2s_datamover_idle <= '1' when (mm2s_stop = '1' and mm2s_halt_cmpt_d2 = '1')
or (mm2s_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_set <= '0';
-- DMACR.Run/Stop is cleared, all processes are idle, datamover halt cmplted
elsif(mm2s_run_stop = '0' and all_is_idle = '1' and mm2s_datamover_idle = '1')then
mm2s_halted_set <= '1';
else
mm2s_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_clr <= '0';
elsif(mm2s_run_stop = '1')then
mm2s_halted_clr <= '1';
else
mm2s_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
mm2s_idle_set <= all_is_idle_re and mm2s_run_stop;
mm2s_idle_clr <= all_is_idle_fe;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the MM2S
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-- system signals
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- dma control and sg engine status signals --
mm2s_run_stop : in std_logic ; --
--
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_cmnd_idle : in std_logic ; --
mm2s_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
mm2s_stop : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
--
-- system state and control --
mm2s_all_idle : out std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic --
);
end axi_dma_mm2s_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal mm2s_datamover_idle : std_logic := '0';
signal mm2s_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal mm2s_halt_cmpt_cdc_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_cdc_d2 : SIGNAL IS "true";
signal mm2s_halt_cmpt_d2 : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Everything is idle when everything is idle
all_is_idle <= mm2s_ftch_idle
and mm2s_updt_idle
and mm2s_cmnd_idle
and mm2s_sts_idle;
-- Pass out for soft reset use
mm2s_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
AWVLD_CDC_TO : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => mm2s_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- mm2s_halt_cmpt_d1_cdc_tig <= '0';
-- -- mm2s_halt_cmpt_d2 <= '0';
-- -- else
-- mm2s_halt_cmpt_d1_cdc_tig <= mm2s_halt_cmplt;
-- mm2s_halt_cmpt_cdc_d2 <= mm2s_halt_cmpt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
mm2s_halt_cmpt_d2 <= mm2s_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
mm2s_halt_cmpt_d2 <= mm2s_halt_cmplt;
end generate GEN_FOR_SYNC;
mm2s_datamover_idle <= '1' when (mm2s_stop = '1' and mm2s_halt_cmpt_d2 = '1')
or (mm2s_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_set <= '0';
-- DMACR.Run/Stop is cleared, all processes are idle, datamover halt cmplted
elsif(mm2s_run_stop = '0' and all_is_idle = '1' and mm2s_datamover_idle = '1')then
mm2s_halted_set <= '1';
else
mm2s_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_clr <= '0';
elsif(mm2s_run_stop = '1')then
mm2s_halted_clr <= '1';
else
mm2s_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
mm2s_idle_set <= all_is_idle_re and mm2s_run_stop;
mm2s_idle_clr <= all_is_idle_fe;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the MM2S
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-- system signals
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- dma control and sg engine status signals --
mm2s_run_stop : in std_logic ; --
--
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_cmnd_idle : in std_logic ; --
mm2s_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
mm2s_stop : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
--
-- system state and control --
mm2s_all_idle : out std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic --
);
end axi_dma_mm2s_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal mm2s_datamover_idle : std_logic := '0';
signal mm2s_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal mm2s_halt_cmpt_cdc_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_cdc_d2 : SIGNAL IS "true";
signal mm2s_halt_cmpt_d2 : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Everything is idle when everything is idle
all_is_idle <= mm2s_ftch_idle
and mm2s_updt_idle
and mm2s_cmnd_idle
and mm2s_sts_idle;
-- Pass out for soft reset use
mm2s_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
AWVLD_CDC_TO : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => mm2s_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- mm2s_halt_cmpt_d1_cdc_tig <= '0';
-- -- mm2s_halt_cmpt_d2 <= '0';
-- -- else
-- mm2s_halt_cmpt_d1_cdc_tig <= mm2s_halt_cmplt;
-- mm2s_halt_cmpt_cdc_d2 <= mm2s_halt_cmpt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
mm2s_halt_cmpt_d2 <= mm2s_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
mm2s_halt_cmpt_d2 <= mm2s_halt_cmplt;
end generate GEN_FOR_SYNC;
mm2s_datamover_idle <= '1' when (mm2s_stop = '1' and mm2s_halt_cmpt_d2 = '1')
or (mm2s_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_set <= '0';
-- DMACR.Run/Stop is cleared, all processes are idle, datamover halt cmplted
elsif(mm2s_run_stop = '0' and all_is_idle = '1' and mm2s_datamover_idle = '1')then
mm2s_halted_set <= '1';
else
mm2s_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_clr <= '0';
elsif(mm2s_run_stop = '1')then
mm2s_halted_clr <= '1';
else
mm2s_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
mm2s_idle_set <= all_is_idle_re and mm2s_run_stop;
mm2s_idle_clr <= all_is_idle_fe;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the MM2S
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-- system signals
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- dma control and sg engine status signals --
mm2s_run_stop : in std_logic ; --
--
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_cmnd_idle : in std_logic ; --
mm2s_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
mm2s_stop : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
--
-- system state and control --
mm2s_all_idle : out std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic --
);
end axi_dma_mm2s_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal mm2s_datamover_idle : std_logic := '0';
signal mm2s_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal mm2s_halt_cmpt_cdc_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_cdc_d2 : SIGNAL IS "true";
signal mm2s_halt_cmpt_d2 : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Everything is idle when everything is idle
all_is_idle <= mm2s_ftch_idle
and mm2s_updt_idle
and mm2s_cmnd_idle
and mm2s_sts_idle;
-- Pass out for soft reset use
mm2s_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
AWVLD_CDC_TO : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => mm2s_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- mm2s_halt_cmpt_d1_cdc_tig <= '0';
-- -- mm2s_halt_cmpt_d2 <= '0';
-- -- else
-- mm2s_halt_cmpt_d1_cdc_tig <= mm2s_halt_cmplt;
-- mm2s_halt_cmpt_cdc_d2 <= mm2s_halt_cmpt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
mm2s_halt_cmpt_d2 <= mm2s_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
mm2s_halt_cmpt_d2 <= mm2s_halt_cmplt;
end generate GEN_FOR_SYNC;
mm2s_datamover_idle <= '1' when (mm2s_stop = '1' and mm2s_halt_cmpt_d2 = '1')
or (mm2s_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_set <= '0';
-- DMACR.Run/Stop is cleared, all processes are idle, datamover halt cmplted
elsif(mm2s_run_stop = '0' and all_is_idle = '1' and mm2s_datamover_idle = '1')then
mm2s_halted_set <= '1';
else
mm2s_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_clr <= '0';
elsif(mm2s_run_stop = '1')then
mm2s_halted_clr <= '1';
else
mm2s_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
mm2s_idle_set <= all_is_idle_re and mm2s_run_stop;
mm2s_idle_clr <= all_is_idle_fe;
end implementation;
|
-- SIMON 64/128
-- Encryption & decryption test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_simon IS
END tb_simon;
ARCHITECTURE behavior OF tb_simon IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT simon
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (0 = enc, 1 = dec)
key : in std_logic_vector(127 downto 0);
block_in : in std_logic_vector(63 downto 0);
block_out : out std_logic_vector(63 downto 0));
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal enc : std_logic := '0';
signal key : std_logic_vector(127 downto 0) := (others => '0');
signal block_in : std_logic_vector(63 downto 0) := (others => '0');
--Outputs
signal block_out : std_logic_vector(63 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: simon PORT MAP (
clk => clk,
rst => rst,
enc => enc,
key => key,
block_in => block_in,
block_out => block_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
-- ==============================================
-- T_0: Test encryption and subsequent decryption
-- ==============================================
-- Test encryption
enc <= '0';
-- Initialize
rst <= '1';
-- SIMON 64/128 test vectors
block_in <= X"656b696c20646e75";
key <= X"1b1a1918131211100b0a090803020100";
-- Wait for initialization
wait for clk_period;
-- Run
rst <= '0';
-- Do 44 rounds
wait for 43*clk_period;
-- plus final round to properly set stage for subsequent decryption
wait for clk_period;
assert block_out = X"44c8fc20b9dfa07a"
report "ENCRYPT ERROR (e_0)" severity FAILURE;
-- Test decryption
enc <= '1';
-- Use output of encryption as input for decryption
block_in <= block_out;
-- Initialize
rst <= '1';
-- Wait for initialization
wait for clk_period;
-- Run
rst <= '0';
-- Do 44 rounds
wait for 43*clk_period;
assert block_out = X"656b696c20646e75"
report "DECRYPT ERROR (d_0)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0_10;
USE dist_mem_gen_v8_0_10.dist_mem_gen_v8_0_10;
ENTITY dist_mem_gen_0 IS
PORT (
a : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END dist_mem_gen_0;
ARCHITECTURE dist_mem_gen_0_arch OF dist_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dist_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0_10 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0_10;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF dist_mem_gen_0_arch: ARCHITECTURE IS "dist_mem_gen_v8_0_10,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF dist_mem_gen_0_arch : ARCHITECTURE IS "dist_mem_gen_0,dist_mem_gen_v8_0_10,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF dist_mem_gen_0_arch: ARCHITECTURE IS "dist_mem_gen_0,dist_mem_gen_v8_0_10,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_ADDR_WIDTH=11,C_DEFAULT_DATA=0,C_DEPTH=1600,C_HAS_CLK=0,C_HAS_D=0,C_HAS_DPO=0,C_HAS_DPRA=0,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=0,C_MEM_INI" &
"T_FILE=dist_mem_gen_0.mif,C_ELABORATION_DIR=./,C_MEM_TYPE=0,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=1,C_REG_A_D_INPUTS=0,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=24,C_PARSER_TYPE=1}";
BEGIN
U0 : dist_mem_gen_v8_0_10
GENERIC MAP (
C_FAMILY => "artix7",
C_ADDR_WIDTH => 11,
C_DEFAULT_DATA => "0",
C_DEPTH => 1600,
C_HAS_CLK => 0,
C_HAS_D => 0,
C_HAS_DPO => 0,
C_HAS_DPRA => 0,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 0,
C_MEM_INIT_FILE => "dist_mem_gen_0.mif",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 0,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 1,
C_REG_A_D_INPUTS => 0,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 24,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
dpra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
clk => '0',
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo
);
END dist_mem_gen_0_arch;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
architecture functional of S_R_flipflop is
begin
q <= '1' when s = '1' else
'0' when r = '1';
q_n <= '0' when s = '1' else
'1' when r = '1';
end architecture functional;
entity tb_S_R_flipflop is
end entity tb_S_R_flipflop;
architecture test of tb_S_R_flipflop is
signal s, r : bit := '0';
signal q, q_n : bit;
begin
dut : entity work.S_R_flipflop(functional)
port map ( s => s, r => r, q => q, q_n => q_n );
stimulus : process is
begin
wait for 10 ns;
s <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '1'; wait for 10 ns;
r <= '0'; wait for 10 ns;
s <= '1'; wait for 10 ns;
r <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '0'; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
architecture functional of S_R_flipflop is
begin
q <= '1' when s = '1' else
'0' when r = '1';
q_n <= '0' when s = '1' else
'1' when r = '1';
end architecture functional;
entity tb_S_R_flipflop is
end entity tb_S_R_flipflop;
architecture test of tb_S_R_flipflop is
signal s, r : bit := '0';
signal q, q_n : bit;
begin
dut : entity work.S_R_flipflop(functional)
port map ( s => s, r => r, q => q, q_n => q_n );
stimulus : process is
begin
wait for 10 ns;
s <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '1'; wait for 10 ns;
r <= '0'; wait for 10 ns;
s <= '1'; wait for 10 ns;
r <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '0'; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
architecture functional of S_R_flipflop is
begin
q <= '1' when s = '1' else
'0' when r = '1';
q_n <= '0' when s = '1' else
'1' when r = '1';
end architecture functional;
entity tb_S_R_flipflop is
end entity tb_S_R_flipflop;
architecture test of tb_S_R_flipflop is
signal s, r : bit := '0';
signal q, q_n : bit;
begin
dut : entity work.S_R_flipflop(functional)
port map ( s => s, r => r, q => q, q_n => q_n );
stimulus : process is
begin
wait for 10 ns;
s <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '1'; wait for 10 ns;
r <= '0'; wait for 10 ns;
s <= '1'; wait for 10 ns;
r <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '0'; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_b3 (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2014.4-2018.3; ghdl 0.31-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.4.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.4 use typ for DL,PC,LP; add dz11,ibtst
-- 2018-09-22 1050 1.3.6 add sys_conf_dmpcnt
-- 2018-09-08 1043 1.3.5 add sys_conf_ibd_kw11p
-- 2017-01-29 847 1.3.4 add sys_conf_ibd_deuna
-- 2016-06-18 775 1.3.3 use PLL for clkser_gentype
-- 2016-05-28 770 1.3.2 sys_conf_mem_losize now type natural
-- 2016-05-26 768 1.3.1 set dmscnt=0 (vivado fsm issue)
-- 2016-03-28 755 1.3 use serport_2clock2 -> define clkser
-- 2016-03-22 750 1.2 add sys_conf_cache_twidth
-- 2016-03-13 742 1.1.2 add sysmon_bus (but disabled like for fpga)
-- 2015-06-26 695 1.1.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*)
-- 2015-03-14 658 1.1 add sys_conf_ibd_* definitions
-- 2015-02-21 649 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_mawidth : positive := 4;
constant sys_conf_memctl_nblock : positive := 11;
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs
constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs
constant sys_conf_rbd_sysmon : boolean := false; -- SYSMON(XADC)
-- configure w11 cpu core --------------------------------------------------
-- sys_conf_mem_losize is highest 64 byte MMU block number
-- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks
constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1;
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
|
--------------------------------------------
-- Author: Mike Field <[email protected]>
--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity clocking is
Port ( clk : in STD_LOGIC;
clk_100 : out STD_LOGIC);
end clocking;
architecture Behavioral of clocking is
signal clkfb : std_logic := '0';
begin
DCM_SP_inst : DCM_SP
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 2, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 6, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 20.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE"
CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X"
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or
-- an integer from 0 to 15
DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
port map (
CLK0 => clkfb,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLKDV => open,
CLKFX => clk_100,
CLKFX180 => open,
LOCKED => open,
PSDONE => open,
STATUS => open,
CLKFB => clkfb,
CLKIN => clk, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => open,
PSEN => '0',
PSINCDEC => '0',
RST => '0'
);
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity unconnected is
port (
output: out std_logic
);
end entity;
architecture arch of unconnected is
signal no_value: std_logic;
begin
output <= no_value;
end;
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- cond_destroy_1.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_cond_t * cond = (hthread_cond_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- hthread_cond_init( cond, NULL );
when STATE_1 =>
-- Push NULL
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Push cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_cond_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- hthread_cond_destroy( cond );
when STATE_4 =>
-- Push the argument to hthread_cond_init
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- Call hthread_cond_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
-- retVal = hthread_cond_init( cond, NULL );
when STATE_6 =>
-- Push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- Push cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_8;
when STATE_8 =>
-- Call hthread_cond_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_9;
next_state <= WAIT_STATE;
when STATE_9 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
-------------------------------------------------------------------------------
--! @file fetch_page.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-11-19
--! @brief Prepare page for NanoFIP communication.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
--! @brief Entity declaration of fetch_page
--! @details
--! The paged data of the NanoFIP response needs to be prepared every cycle.
entity fetch_page is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name Commands
--! @{
--! Start flag
start_i : in std_ulogic;
--! Done flag
done_o : out std_ulogic;
--! Memory index
idx_i : in std_ulogic_vector(14 downto 0);
--! Memory index type
idx_type_i : in std_ulogic_vector(2 downto 0);
--! @}
--! @name Memory page interface
--! @{
--! Address
page_addr_o : out std_ulogic_vector(5 downto 0);
--! Write enable
page_wr_en_o : out std_ulogic;
--! Data output
page_data_o : out std_ulogic_vector(7 downto 0);
--! Done flag
page_done_i : in std_ulogic;
--! @}
--! @name External SRAM ADC data
--! @{
--! Address
sram_adc_addr_o : out std_ulogic_vector(4 downto 0);
--! Read request
sram_adc_rd_en_o : out std_ulogic;
--! Data input
sram_adc_data_i : in std_ulogic_vector(23 downto 0);
--! Data input enable
sram_adc_data_en_i : in std_ulogic;
--! Done flag
sram_adc_done_o : out std_ulogic;
--! @}
--! @name External SRAM DIM data
--! @{
--! Address
sram_dim_addr_o : out std_ulogic_vector(4 downto 0);
--! Read request
sram_dim_rd_en_o : out std_ulogic;
--! Data input
sram_dim_data_i : in std_ulogic_vector(15 downto 0);
--! Data input enable
sram_dim_data_en_i : in std_ulogic;
--! Done flag
sram_dim_done_o : out std_ulogic;
--! @}
--! @name DIM data
--! @{
--! Address
dim_addr_o : out std_ulogic_vector(6 downto 0);
--! Read enable
dim_rd_en_o : out std_ulogic;
--! Data input
dim_data_i : in std_ulogic_vector(15 downto 0);
--! Data input enable
dim_data_en_i : in std_ulogic;
--! @}
--! @name One-wire data
--! @{
--! Address
ow_addr_o : out std_ulogic_vector(5 downto 0);
--! Read enable
ow_rd_en_o : out std_ulogic;
--! Data input
ow_data_i : in std_ulogic_vector(79 downto 0);
--! Data input enable
ow_data_en_i : in std_ulogic);
--! @}
end entity fetch_page;
--! RTL implementation of fetch_page
architecture rtl of fetch_page is
---------------------------------------------------------------------------
--! @name Types and Constants
---------------------------------------------------------------------------
--! @{
type source_t is (DIM, ONEWIRE, SRAM_ADC, SRAM_DIM);
--! @}
---------------------------------------------------------------------------
--! @name Internal Registers
---------------------------------------------------------------------------
--! @{
signal source : source_t;
signal start_dim : std_ulogic;
signal start_ow : std_ulogic;
signal start_sram_adc : std_ulogic;
signal start_sram_dim : std_ulogic;
--! @}
---------------------------------------------------------------------------
--! @name Internal Wires
---------------------------------------------------------------------------
--! @{
signal sram_adc_addr : std_ulogic_vector(5 downto 0);
signal sram_adc_wr_en : std_ulogic;
signal sram_adc_data : std_ulogic_vector(7 downto 0);
signal sram_adc_done : std_ulogic;
signal sram_dim_addr : std_ulogic_vector(5 downto 0);
signal sram_dim_wr_en : std_ulogic;
signal sram_dim_data : std_ulogic_vector(7 downto 0);
signal sram_dim_done : std_ulogic;
signal dim_addr : std_ulogic_vector(5 downto 0);
signal dim_wr_en : std_ulogic;
signal dim_data : std_ulogic_vector(7 downto 0);
signal dim_done : std_ulogic;
signal ow_addr : std_ulogic_vector(5 downto 0);
signal ow_wr_en : std_ulogic;
signal ow_data : std_ulogic_vector(7 downto 0);
signal ow_done : std_ulogic;
--! @}
begin -- architecture rtl
---------------------------------------------------------------------------
-- Outputs
---------------------------------------------------------------------------
with source select page_addr_o <=
sram_adc_addr when SRAM_ADC,
sram_dim_addr when SRAM_DIM,
dim_addr when DIM,
ow_addr when ONEWIRE,
(others => '0') when others;
with source select page_wr_en_o <=
sram_adc_wr_en when SRAM_ADC,
sram_dim_wr_en when SRAM_DIM,
dim_wr_en when DIM,
ow_wr_en when ONEWIRE,
'0' when others;
with source select page_data_o <=
sram_adc_data when SRAM_ADC,
sram_dim_data when SRAM_DIM,
dim_data when DIM,
ow_data when ONEWIRE,
(others => '0') when others;
with source select done_o <=
sram_adc_done when SRAM_ADC,
sram_dim_done when SRAM_DIM,
dim_done when DIM,
ow_done when ONEWIRE,
'0' when others;
sram_adc_done_o <= sram_adc_done;
sram_dim_done_o <= sram_dim_done;
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
fetch_dim_inst : entity work.fetch_page_dim
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
start_i => start_dim,
done_o => dim_done,
idx_i => idx_i,
page_addr_o => dim_addr,
page_wr_en_o => dim_wr_en,
page_data_o => dim_data,
page_done_i => page_done_i,
dim_addr_o => dim_addr_o,
dim_rd_en_o => dim_rd_en_o,
dim_data_i => dim_data_i,
dim_data_en_i => dim_data_en_i);
fetch_ow_inst : entity work.fetch_page_ow
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
start_i => start_ow,
done_o => ow_done,
idx_i => idx_i,
page_addr_o => ow_addr,
page_wr_en_o => ow_wr_en,
page_data_o => ow_data,
page_done_i => page_done_i,
ow_addr_o => ow_addr_o,
ow_rd_en_o => ow_rd_en_o,
ow_data_i => ow_data_i,
ow_data_en_i => ow_data_en_i);
fetch_sram_adc_inst : entity work.fetch_page_sram_adc
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
start_i => start_sram_adc,
done_o => sram_adc_done,
page_addr_o => sram_adc_addr,
page_wr_en_o => sram_adc_wr_en,
page_data_o => sram_adc_data,
page_done_i => page_done_i,
sram_addr_o => sram_adc_addr_o,
sram_rd_en_o => sram_adc_rd_en_o,
sram_data_i => sram_adc_data_i,
sram_data_en_i => sram_adc_data_en_i);
fetch_sram_dim_inst : entity work.fetch_page_sram_dim
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
start_i => start_sram_dim,
done_o => sram_dim_done,
page_addr_o => sram_dim_addr,
page_wr_en_o => sram_dim_wr_en,
page_data_o => sram_dim_data,
page_done_i => page_done_i,
sram_addr_o => sram_dim_addr_o,
sram_rd_en_o => sram_dim_rd_en_o,
sram_data_i => sram_dim_data_i,
sram_data_en_i => sram_dim_data_en_i);
---------------------------------------------------------------------------
-- Registers
---------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
source <= DIM;
start_dim <= '0';
start_ow <= '0';
start_sram_adc <= '0';
start_sram_dim <= '0';
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
start_dim <= '0';
start_ow <= '0';
start_sram_adc <= '0';
start_sram_dim <= '0';
if start_i = '1' then
if idx_type_i = "000" then
source <= DIM;
start_dim <= '1';
elsif idx_type_i = "001" then
source <= ONEWIRE;
start_ow <= '1';
elsif idx_type_i = "101" then
source <= SRAM_DIM;
start_sram_dim <= '1';
else
source <= SRAM_ADC;
start_sram_adc <= '1';
end if;
end if;
end if;
end if;
end process regs;
end architecture rtl;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
valid_in_vc: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_en_vc_N : in std_logic;
read_en_vc_E : in std_logic;
read_en_vc_W : in std_logic;
read_en_vc_S : in std_logic;
read_en_vc_L : in std_logic;
credit_out: out std_logic;
credit_out_vc: out std_logic;
empty_out: out std_logic;
empty_out_vc: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
Data_out_vc: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal read_pointer_vc, read_pointer_in_vc, write_pointer_vc, write_pointer_in_vc: std_logic_vector(3 downto 0);
signal full_vc, empty_vc: std_logic;
signal read_en_vc, write_en_vc: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_vc_1, FIFO_MEM_vc_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_vc_2, FIFO_MEM_vc_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_vc_3, FIFO_MEM_vc_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_vc_4, FIFO_MEM_vc_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
credit_out <= '0';
read_pointer_vc <= "0001";
write_pointer_vc <= "0001";
FIFO_MEM_vc_1 <= (others=>'0');
FIFO_MEM_vc_2 <= (others=>'0');
FIFO_MEM_vc_3 <= (others=>'0');
FIFO_MEM_vc_4 <= (others=>'0');
credit_out_vc <= '0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
credit_out <= '0';
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
if read_en = '1' then
credit_out <= '1';
end if;
write_pointer_vc <= write_pointer_in_vc;
read_pointer_vc <= read_pointer_in_vc;
credit_out_vc <= '0';
if write_en_vc = '1' then
--write into the memory
FIFO_MEM_vc_1 <= FIFO_MEM_vc_1_in;
FIFO_MEM_vc_2 <= FIFO_MEM_vc_2_in;
FIFO_MEM_vc_3 <= FIFO_MEM_vc_3_in;
FIFO_MEM_vc_4 <= FIFO_MEM_vc_4_in;
end if;
if read_en_vc = '1' then
credit_out_vc <= '1';
end if;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
process(RX, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1'then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in) begin
if valid_in = '1' and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
-------------------------------------------------------------------------------
--- VC stuff
---
-------------------------------------------------------------------------------
process(RX, write_pointer_vc, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( write_pointer_vc ) is
when "0001" => FIFO_MEM_vc_1_in <= RX; FIFO_MEM_vc_2_in <= FIFO_MEM_vc_2; FIFO_MEM_vc_3_in <= FIFO_MEM_vc_3; FIFO_MEM_vc_4_in <= FIFO_MEM_vc_4;
when "0010" => FIFO_MEM_vc_1_in <= FIFO_MEM_vc_1; FIFO_MEM_vc_2_in <= RX; FIFO_MEM_vc_3_in <= FIFO_MEM_vc_3; FIFO_MEM_vc_4_in <= FIFO_MEM_vc_4;
when "0100" => FIFO_MEM_vc_1_in <= FIFO_MEM_vc_1; FIFO_MEM_vc_2_in <= FIFO_MEM_vc_2; FIFO_MEM_vc_3_in <= RX; FIFO_MEM_vc_4_in <= FIFO_MEM_vc_4;
when "1000" => FIFO_MEM_vc_1_in <= FIFO_MEM_vc_1; FIFO_MEM_vc_2_in <= FIFO_MEM_vc_2; FIFO_MEM_vc_3_in <= FIFO_MEM_vc_3; FIFO_MEM_vc_4_in <= RX;
when others => FIFO_MEM_vc_1_in <= FIFO_MEM_vc_1; FIFO_MEM_vc_2_in <= FIFO_MEM_vc_2; FIFO_MEM_vc_3_in <= FIFO_MEM_vc_3; FIFO_MEM_vc_4_in <= FIFO_MEM_vc_4;
end case ;
end process;
process(read_pointer_vc, FIFO_MEM_vc_1, FIFO_MEM_vc_2, FIFO_MEM_vc_3, FIFO_MEM_vc_4)begin
case( read_pointer_vc ) is
when "0001" => Data_out_vc <= FIFO_MEM_vc_1;
when "0010" => Data_out_vc <= FIFO_MEM_vc_2;
when "0100" => Data_out_vc <= FIFO_MEM_vc_3;
when "1000" => Data_out_vc <= FIFO_MEM_vc_4;
when others => Data_out_vc <= FIFO_MEM_vc_1;
end case ;
end process;
read_en_vc <= (read_en_vc_N or read_en_vc_E or read_en_vc_W or read_en_vc_S or read_en_vc_L) and not empty_vc;
empty_out_vc <= empty_vc;
process(write_en_vc, write_pointer_vc)begin
if write_en_vc = '1'then
write_pointer_in_vc <= write_pointer_vc(2 downto 0)&write_pointer_vc(3);
else
write_pointer_in_vc <= write_pointer_vc;
end if;
end process;
process(read_en_vc, empty_vc, read_pointer_vc)begin
if (read_en_vc = '1' and empty_vc = '0') then
read_pointer_in_vc <= read_pointer_vc(2 downto 0)&read_pointer_vc(3);
else
read_pointer_in_vc <= read_pointer_vc;
end if;
end process;
process(full_vc, valid_in_vc) begin
if valid_in_vc = '1' and full_vc ='0' then
write_en_vc <= '1';
else
write_en_vc <= '0';
end if;
end process;
process(write_pointer_vc, read_pointer_vc) begin
if read_pointer_vc = write_pointer_vc then
empty_vc <= '1';
else
empty_vc <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer_vc = read_pointer_vc(0)&read_pointer_vc(3 downto 1) then
full_vc <= '1';
else
full_vc <= '0';
end if;
end process;
end;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_19.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package ch_05_19 is
-- code from book:
subtype digit is bit_vector(3 downto 0);
-- end of code from book
end package ch_05_19;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_19.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package ch_05_19 is
-- code from book:
subtype digit is bit_vector(3 downto 0);
-- end of code from book
end package ch_05_19;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_19.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package ch_05_19 is
-- code from book:
subtype digit is bit_vector(3 downto 0);
-- end of code from book
end package ch_05_19;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram128bw
-- File: syncram128bw.vhd
-- Author: Nils-Johan Wessman - Aeroflex Gaisler AB
-- Description: 128-bit data + 28-bit edac syncronous 1-port ram with 16-bit write strobes
-- and tech selection
--
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allmem.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncram156bw is
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits: integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (155 downto 0);
dataout : out std_logic_vector (155 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none
);
end;
architecture rtl of syncram156bw is
-- component unisim_syncram128bw
-- generic ( abits : integer := 9);
-- port (
-- clk : in std_ulogic;
-- address : in std_logic_vector (abits -1 downto 0);
-- datain : in std_logic_vector (127 downto 0);
-- dataout : out std_logic_vector (127 downto 0);
-- enable : in std_logic_vector (15 downto 0);
-- write : in std_logic_vector (15 downto 0)
-- );
-- end component;
--
-- component altera_syncram128bw
-- generic ( abits : integer := 9);
-- port (
-- clk : in std_ulogic;
-- address : in std_logic_vector (abits -1 downto 0);
-- datain : in std_logic_vector (127 downto 0);
-- dataout : out std_logic_vector (127 downto 0);
-- enable : in std_logic_vector (15 downto 0);
-- write : in std_logic_vector (15 downto 0)
-- );
-- end component;
--
component cust1_syncram156bw
generic ( abits : integer := 14; testen : integer := 0);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (155 downto 0);
dataout : out std_logic_vector (155 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (3 downto 0) := "0000"
);
end component;
component ut90nhbd_syncram156bw
generic (abits : integer := 14);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (155 downto 0);
dataout : out std_logic_vector (155 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
tdbn : in std_ulogic);
end component;
component rhs65_syncram156bw
generic (abits : integer := 14);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (155 downto 0);
dataout : out std_logic_vector (155 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
scanen : in std_ulogic;
bypass : in std_ulogic;
mbtdi : in std_ulogic;
mbtdo : out std_ulogic;
mbshft : in std_ulogic;
mbcapt : in std_ulogic;
mbupd : in std_ulogic;
mbclk : in std_ulogic;
mbrstn : in std_ulogic;
mbcgate : in std_ulogic;
mbpres : out std_ulogic;
mbmuxo : out std_logic_vector(5 downto 0)
);
end component;
signal xenable, xwrite : std_logic_vector(15 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
signal customclkx: std_ulogic;
signal dataoutx: std_logic_vector(155 downto 0);
begin
xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
dataout <= dataoutx;
custominx <= (others => '0');
customclkx <= '0';
nocust: if syncram_has_customif(tech)=0 or has_sram156bw(tech)=0 generate
customoutx <= (others => '0');
end generate;
s156 : if has_sram156bw(tech) = 1 generate
-- xc2v : if (is_unisim(tech) = 1) generate
-- x0 : unisim_syncram128bw generic map (abits)
-- port map (clk, address, datain, dataout, enable, write);
-- end generate;
-- alt : if (tech = stratix2) or (tech = stratix3) or
-- (tech = cyclone3) or (tech = altera) generate
-- x0 : altera_syncram128bw generic map (abits)
-- port map (clk, address, datain, dataout, enable, write);
-- end generate;
cust1u : if tech = custom1 generate
x0 : cust1_syncram156bw generic map (abits, testen)
port map (clk, address, datain, dataoutx, xenable, xwrite, testin);
end generate;
ut90u : if tech = ut90 generate
x0 : ut90nhbd_syncram156bw generic map (abits)
port map (clk, address, datain, dataoutx, xenable, xwrite, testin(TESTIN_WIDTH-3));
end generate;
rhs65u : if tech = rhs65 generate
x0 : rhs65_syncram156bw generic map (abits)
port map (clk, address, datain, dataoutx, enable, write,
testin(TESTIN_WIDTH-8), testin(TESTIN_WIDTH-3),
custominx(0),customoutx(0),
testin(TESTIN_WIDTH-4), testin(TESTIN_WIDTH-5), testin(TESTIN_WIDTH-6),
customclkx,
testin(TESTIN_WIDTH-7),'0',
customoutx(1), customoutx(7 downto 2));
customoutx(customoutx'high downto 8) <= (others => '0');
end generate;
-- pragma translate_off
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram156bw: " & tost(2**abits) & "x156" &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
chk : if GRLIB_CONFIG_ARRAY(grlib_syncram_selftest_enable) /= 0 generate
chkblk: block
signal refdo: std_logic_vector(155 downto 0);
signal pren: std_ulogic;
signal prmask: std_logic_vector(15 downto 0);
signal paddr: std_logic_vector(abits-1 downto 0);
begin
rx : for i in 0 to 15 generate
x0 : generic_syncram generic map (abits, 8)
port map (clk, address, datain(i*8+7 downto i*8),
refdo(i*8+7 downto i*8), write(i));
c0 : if i mod 4 = 0 generate
x0 : generic_syncram generic map (abits, 7)
port map (clk, address, datain(i/4*7+128+6 downto i/4*7+128),
refdo(i/4*7+128+6 downto i/4*7+128), write(i));
end generate; -- c0
end generate; -- rx
p: process(clk)
begin
if rising_edge(clk) then
for x in 15 downto 0 loop
assert pren/='1' or prmask(x)/='1' or
(refdo(8*x+7 downto 8*x)=dataoutx(8*x+7 downto 8*x) and
refdo(128+(x/4)*7+6 downto 128+(x/4)*7)=dataoutx(128+(x/4)*7+6 downto 128+(x/4)*7)) or
is_x(refdo) or is_x(paddr);
end loop;
pren <= not orv(write);
prmask <= enable;
paddr <= address;
end if;
end process;
end block; -- chkblk
end generate; -- chk
-- pragma translate_on
end generate;
nos156 : if has_sram156bw(tech) = 0 generate
rx : for i in 0 to 15 generate
x0 : syncram generic map (tech, abits, 8, testen, custombits)
port map (clk, address, datain(i*8+7 downto i*8),
dataoutx(i*8+7 downto i*8), enable(i), write(i), testin
);
c0 : if i mod 4 = 0 generate
x0 : syncram generic map (tech, abits, 7, testen, custombits)
port map (clk, address, datain(i/4*7+128+6 downto i/4*7+128),
dataoutx(i/4*7+128+6 downto i/4*7+128), enable(i), write(i), testin
);
end generate;
end generate;
end generate;
end;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "hall_sensor_decoder"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.hall_sensor_decoder_pkg.all;
use work.motor_control_pkg.all;
-------------------------------------------------------------------------------
entity hall_sensor_decoder_tb is
end hall_sensor_decoder_tb;
-------------------------------------------------------------------------------
architecture tb of hall_sensor_decoder_tb is
type input_type is record
a : std_logic;
b : std_logic;
c : std_logic;
end record;
type expect_type is record
step : std_logic;
dir : std_logic;
error : std_logic;
end record;
type stimulus_type is record
input : input_type;
expect : expect_type;
end record;
type stimuli_type is array (natural range <>) of stimulus_type;
constant stimuli : stimuli_type := (
-- A B C step dir error
(input => ('0', '0', '1'), expect => ('0', '-', '0')),
(input => ('1', '0', '1'), expect => ('1', '-', '0')),
(input => ('1', '0', '0'), expect => ('1', '1', '0')),
(input => ('1', '0', '0'), expect => ('0', '-', '0')),
(input => ('1', '1', '0'), expect => ('1', '1', '0')),
(input => ('0', '1', '0'), expect => ('1', '1', '0')),
(input => ('0', '1', '1'), expect => ('1', '1', '0')),
(input => ('0', '0', '1'), expect => ('1', '1', '0')),
(input => ('1', '0', '1'), expect => ('1', '1', '0')),
(input => ('1', '0', '1'), expect => ('0', '-', '0')),
(input => ('0', '0', '1'), expect => ('1', '0', '0')),
(input => ('0', '1', '1'), expect => ('1', '0', '0')),
(input => ('0', '1', '0'), expect => ('1', '0', '0')),
(input => ('1', '1', '0'), expect => ('1', '0', '0')),
(input => ('1', '1', '0'), expect => ('0', '-', '0')),
(input => ('0', '1', '0'), expect => ('1', '1', '0')),
(input => ('1', '1', '0'), expect => ('1', '0', '0')),
(input => ('0', '1', '0'), expect => ('1', '1', '0')),
(input => ('0', '1', '1'), expect => ('1', '1', '0')),
(input => ('0', '0', '1'), expect => ('1', '1', '0')),
(input => ('1', '0', '1'), expect => ('1', '1', '0')),
(input => ('1', '1', '1'), expect => ('0', '-', '1')),
(input => ('0', '1', '1'), expect => ('0', '-', '0')),
(input => ('0', '1', '0'), expect => ('1', '0', '0')),
(input => ('1', '1', '0'), expect => ('1', '0', '0')),
(input => ('0', '0', '0'), expect => ('0', '-', '1')),
(input => ('1', '0', '1'), expect => ('0', '0', '0'))
);
-- component ports
signal abc : hall_sensor_type := (a => '0', b => '0', c => '0');
signal step : std_logic;
signal dir : std_logic;
signal error : std_logic;
-- clock
signal clk : std_logic := '1';
begin
-- component instantiation
DUT : hall_sensor_decoder
port map (
hall_sensor_p => abc,
step_p => step,
dir_p => dir,
error_p => error,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
wave : process
begin
wait for 20 ns;
for i in stimuli'left to (stimuli'right + 2) loop
wait until rising_edge(clk);
if i <= stimuli'right then
abc.a <= stimuli(i).input.a;
abc.b <= stimuli(i).input.b;
abc.c <= stimuli(i).input.c;
else
abc.a <= '0';
abc.b <= '0';
abc.c <= '1';
end if;
if i > (stimuli'left + 2) then
-- values are active at the output after two clock cycles
assert (step = stimuli(i-2).expect.step) report "Wrong value for 'step'" severity note;
if not (stimuli(i-2).expect.dir = '-') then
assert (dir = stimuli(i-2).expect.dir) report "Wrong value for 'dir'" severity note;
end if;
assert (error = stimuli(i-2).expect.error) report "Wrong value for 'error'" severity note;
end if;
end loop; -- i
end process wave;
end tb;
|
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