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library ieee;
use ieee.std_logic_1164.all;
-- Dummy sld_virtual_jtag - ModelSim crashes on default one
entity sld_virtual_jtag is
generic (
lpm_type : string := "SLD_VIRTUAL_JTAG";
-- required by coding standard
lpm_hint : string := "SLD_VIRTUAL_JTAG"; -- required by coding standard
sld_auto_instance_index : string := "NO";
-- Yes of auto index is desired and no otherwise
sld_instance_index : integer := 0;
-- Index to be used if SLD_AUTO_INSTANCE_INDEX is no
sld_ir_width : integer := 1;
-- the width of the IR register
sld_sim_n_scan : integer := 0;
-- the number of scans in the simulation model
sld_sim_total_length : integer := 0;
-- the total bit width of all DR scan values
sld_sim_action : string := "");
-- the actions to be simulated in a format specified by the documentation
port (
tdo : in std_logic := '0'; -- tdo signal into megafunction
ir_out : in std_logic_vector(sld_ir_width - 1 downto 0) := (others => '0');
-- parallel ir data into megafunction
tck : out std_logic; -- tck signal from megafunction
tdi : out std_logic; -- tdi signal from megafunction
ir_in : out std_logic_vector(sld_ir_width - 1 downto 0);
-- paraller ir data from megafunction
virtual_state_cdr : out std_logic; -- cdr state signal of megafunction
virtual_state_sdr : out std_logic; -- sdr state signal of megafunction
virtual_state_e1dr : out std_logic;
-- e1dr state signal of megafunction
virtual_state_pdr : out std_logic; -- pdr state signal of megafunction
virtual_state_e2dr : out std_logic;
-- e2dr state signal of megafunction
virtual_state_udr : out std_logic; -- udr state signal of megafunction
virtual_state_cir : out std_logic; -- cir state signal of megafunction
virtual_state_uir : out std_logic; -- uir state signal of megafunction
jtag_state_tlr : out std_logic; -- Test, Logic, Reset state
jtag_state_rti : out std_logic; -- Run, Test, Idle state
jtag_state_sdrs : out std_logic; -- Select DR scan state
jtag_state_cdr : out std_logic; -- capture DR state
jtag_state_sdr : out std_logic; -- Shift DR state
jtag_state_e1dr : out std_logic; -- exit 1 dr state
jtag_state_pdr : out std_logic; -- pause dr state
jtag_state_e2dr : out std_logic; -- exit 2 dr state
jtag_state_udr : out std_logic; -- update dr state
jtag_state_sirs : out std_logic; -- Select IR scan state
jtag_state_cir : out std_logic; -- capture IR state
jtag_state_sir : out std_logic; -- shift IR state
jtag_state_e1ir : out std_logic; -- exit 1 IR state
jtag_state_pir : out std_logic; -- pause IR state
jtag_state_e2ir : out std_logic; -- exit 2 IR state
jtag_state_uir : out std_logic; -- update IR state
tms : out std_logic); -- tms signal
end sld_virtual_jtag;
architecture structural of sld_virtual_jtag is
begin -- structural
-- dummy drivers to avoid modelsim warnings
tck <= '0';
tdi <= '0';
ir_in <= (others => '0');
virtual_state_cdr <= '0';
virtual_state_sdr <= '0';
virtual_state_udr <= '0';
end structural;
|
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package cycloneiiils_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE cycloneiiils_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end cycloneiiils_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body cycloneiiils_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end cycloneiiils_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package cycloneiiils_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end cycloneiiils_pllpack;
package body cycloneiiils_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end cycloneiiils_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiiils_dffe : entity is TRUE;
end cycloneiiils_dffe;
-- architecture body --
architecture behave of cycloneiiils_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- cycloneiiils_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of cycloneiiils_mux21 : entity is TRUE;
end cycloneiiils_mux21;
architecture AltVITAL of cycloneiiils_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiiils_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiiils_mux41 : entity is TRUE;
end cycloneiiils_mux41;
architecture AltVITAL of cycloneiiils_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiiils_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiiils_atom_pack.all;
-- entity declaration --
entity cycloneiiils_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiiils_and1 : entity is TRUE;
end cycloneiiils_and1;
-- architecture body --
architecture AltVITAL of cycloneiiils_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_lcell_comb
--
-- Description : Cyclone III LS LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_lcell_comb is
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiiils_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiiils_lcell_comb : entity is TRUE;
end cycloneiiils_lcell_comb;
architecture vital_lcell_comb of cycloneiiils_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal cin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
cin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
-- output variables
variable combout_tmp : std_logic;
variable cout_tmp : std_logic;
begin
-- lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
if (sum_lutc_input = "datac") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
elsif (sum_lutc_input = "cin") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
cin_ipd,
datab_ipd,
dataa_ipd));
end if;
-- cout
cout_tmp := VitalMUX(data => lut_mask,
dselect => ('0',
cin_ipd,
datab_ipd,
dataa_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_routing_wire
--
-- Description : Cyclone III LS Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiiils_routing_wire : entity is TRUE;
end cycloneiiils_routing_wire;
ARCHITECTURE behave of cycloneiiils_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiiils_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the Cyclone III LS PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiiils_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END cycloneiiils_mn_cntr;
ARCHITECTURE behave of cycloneiiils_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiiils_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the Cyclone III LS PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiiils_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END cycloneiiils_scale_cntr;
ARCHITECTURE behave of cycloneiiils_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiiils_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY cycloneiiils_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end cycloneiiils_pll_reg;
ARCHITECTURE behave of cycloneiiils_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiiils_pll
--
-- Description : Timing simulation model for the Cyclone III LS PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.cycloneiiils_atom_pack.all;
USE work.cycloneiiils_pllpack.all;
USE work.cycloneiiils_mn_cntr;
USE work.cycloneiiils_scale_cntr;
USE work.cycloneiiils_dffe;
USE work.cycloneiiils_pll_reg;
-- New Features : The list below outlines key new features in CYCLONEIIILS:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY cycloneiiils_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneiiils_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "Cyclone III LS";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END cycloneiiils_pll;
ARCHITECTURE vital_pll of cycloneiiils_pll is
function get_vco_min_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_min * 2;
else
return vco_min;
end if;
end;
function get_vco_max_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_max * 2;
else
return vco_max;
end if;
end;
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
constant VCO_MIN_NO_DIVISION : integer := get_vco_min_no_division(vco_post_scale);
constant VCO_MAX_NO_DIVISION : integer := get_vco_max_no_division(vco_post_scale);
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min;
signal i_vco_max : integer := vco_max;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_high_val : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val : int_array(0 to 4) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 4) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 4);
signal clk_num : str_array(0 to 4);
-- old values
signal c_high_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 4);
-- hold registers
signal c_high_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 4);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 4) := (OTHERS => 0);
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(4 downto 0) := (" C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 4);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 5;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 4);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(2 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 4);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT cycloneiiils_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiiils_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiiils_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT cycloneiiils_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1)
else false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : cycloneiiils_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (areset_ipd = '0') then
if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
elsif (inclk0_period /= 0 ps) then
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : cycloneiiils_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : cycloneiiils_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : cycloneiiils_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : cycloneiiils_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : cycloneiiils_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : cycloneiiils_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 4) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 4) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 4);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 4);
variable i_c_low : int_array(0 to 4);
variable i_c_initial : int_array(0 to 4);
variable i_c_ph : int_array(0 to 4);
variable i_c_mode : str_array(0 to 4);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
1,1,1,1,1,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
"unused","unused","unused","unused","unused",
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
0,
0,
0,
0,
0
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 4 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
scan_chain_length := SCAN_CHAIN;
num_output_cntrs <= 5;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= VCO_MAX_NO_DIVISION/2;
i_vco_min <= VCO_MIN_NO_DIVISION/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
n_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
n_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
m_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
m_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(36) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(18) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiiils_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiiils_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "111") THEN -- no counters selected
IF (phasecounterselect_ipd = "000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(SCAN_CHAIN - 2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after 1 ps;
end loop;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
locked_tmp := '0';
end if;
pll_is_in_reset := false;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
---------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_ff
--
-- Description : Cyclone III LS FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
use work.cycloneiiils_and1;
entity cycloneiiils_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiiils_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiiils_ff : entity is TRUE;
end cycloneiiils_ff;
architecture vital_lcell_ff of cycloneiiils_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component cycloneiiils_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: cycloneiiils_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: cycloneiiils_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: cycloneiiils_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
----------------------------------------------------------------------------
-- Module Name : cycloneiiils_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END cycloneiiils_ram_register;
ARCHITECTURE reg_arch OF cycloneiiils_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiiils_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF cycloneiiils_ram_pulse_generator:ENTITY IS TRUE;
END cycloneiiils_ram_pulse_generator;
ARCHITECTURE pgen_arch OF cycloneiiils_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiiils_atom_pack.all;
USE work.cycloneiiils_ram_register;
USE work.cycloneiiils_ram_pulse_generator;
ENTITY cycloneiiils_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneiiils_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END cycloneiiils_ram_block;
ARCHITECTURE block_arch OF cycloneiiils_ram_block IS
COMPONENT cycloneiiils_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiiils_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch, dataout_b_clr_reg_latch : STD_LOGIC;
SIGNAL dataout_a_clr_reg_latch_in, dataout_b_clr_reg_latch_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch_out, dataout_b_clr_reg_latch_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr_reg <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_a_clr <= dataout_a_clr_reg WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
'0';
dataout_b_clr_reg <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= dataout_b_clr_reg WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
'0';
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : cycloneiiils_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : cycloneiiils_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : cycloneiiils_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : cycloneiiils_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : cycloneiiils_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : cycloneiiils_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : cycloneiiils_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : cycloneiiils_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : cycloneiiils_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : cycloneiiils_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : cycloneiiils_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : cycloneiiils_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : cycloneiiils_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : cycloneiiils_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0') AND (dataout_a_clr = '0')) ELSE '0';
rpgen_a : cycloneiiils_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0') AND (dataout_b_clr = '0')) ELSE '0';
rpgen_b : cycloneiiils_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a AND (dataout_a_clr = '0')) ELSE '0';
rwpgen_a : cycloneiiils_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b AND (dataout_b_clr = '0')) ELSE '0';
rwpgen_b : cycloneiiils_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
dataout_a_clr, dataout_b_clr,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
-- Latch Clear
IF (dataout_a_clr'EVENT AND dataout_a_clr = '1') THEN
IF (primary_port_is_a) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
IF (dataout_b_clr'EVENT AND dataout_b_clr = '1') THEN
IF (primary_port_is_b) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init4 & mem_init3 & mem_init2 & mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1') AND (dataout_a_clr = '0')) ELSE '0';
ftpgen_a : cycloneiiils_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1') AND (dataout_b_clr = '0')) ELSE '0';
ftpgen_b : cycloneiiils_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1' AND dataout_a_clr = '0' AND dataout_a_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1' AND dataout_b_clr = '0' AND dataout_b_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_latch_in(0) <= dataout_a_clr;
aclr_a_mux_register : cycloneiiils_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_latch_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_latch_out
);
dataout_a_clr_reg_latch <= dataout_a_clr_reg_latch_out(0);
-- Port B output register clear
dataout_b_clr_reg_latch_in(0) <= dataout_b_clr;
aclr_b_mux_register : cycloneiiils_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_latch_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_latch_out
);
dataout_b_clr_reg_latch <= dataout_b_clr_reg_latch_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : cycloneiiils_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : cycloneiiils_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-----------------------------------------------------------------------
--
-- Module Name : cycloneiiils_mac_data_reg
--
-- Description : Simulation model for the data input register of
-- Cyclone III LS MAC_MULT
--
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_mac_data_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END cycloneiiils_mac_data_reg;
ARCHITECTURE vital_cycloneiiils_mac_data_reg OF cycloneiiils_mac_data_reg IS
SIGNAL data_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL aclr_ipd : std_logic;
SIGNAL clk_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
SIGNAL dataout_tmp : std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
process (clk_ipd, aclr_ipd, data_ipd)
begin
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= data_ipd;
end if;
end process;
sh: block
begin
g0 : for i in data'range generate
process (data_ipd(i),clk_ipd,ena_ipd)
variable Tviol_data_clk : std_ulogic := '0';
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data_ipd(i),
TestSignalName => "DATA(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_data_clk_noedge_posedge(i),
SetupLow => tsetup_data_clk_noedge_posedge(i),
HoldHigh => thold_data_clk_noedge_posedge(i),
HoldLow => thold_data_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout_tmp'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn);
end process;
end generate;
end block;
END vital_cycloneiiils_mac_data_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiiils_mac_sign_reg
--
-- Description : Simulation model for the sign input register of
-- Cyclone III LS MAC_MULT
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_mac_sign_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END cycloneiiils_mac_sign_reg;
ARCHITECTURE cycloneiiils_mac_sign_reg OF cycloneiiils_mac_sign_reg IS
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
signal aclr_ipd : std_logic;
signal ena_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END cycloneiiils_mac_sign_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiiils_mac_mult_internal
--
-- Description : Cyclone III LS MAC_MULT_INTERNAL VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_mac_mult_internal IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END cycloneiiils_mac_mult_internal;
ARCHITECTURE vital_cycloneiiils_mac_mult_internal OF cycloneiiils_mac_mult_internal IS
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL signa_ipd : std_logic;
SIGNAL signb_ipd : std_logic;
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, signa_ipd, signb_ipd)
begin
if((signa_ipd = '0') and (signb_ipd = '1')) then
dataout_tmp <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '0')) then
dataout_tmp <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '1')) then
dataout_tmp(dataout'range) <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
else --((signa_ipd = '0') and (signb_ipd = '0')) then
dataout_tmp(dataout'range) <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE );
end process;
end generate;
end block;
END vital_cycloneiiils_mac_mult_internal;
--------------------------------------------------------------------
--
-- Module Name : cycloneiiils_mac_mult
--
-- Description : Cyclone III LS MAC_MULT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiiils_atom_pack.all;
USE work.cycloneiiils_mac_data_reg;
USE work.cycloneiiils_mac_sign_reg;
USE work.cycloneiiils_mac_mult_internal;
ENTITY cycloneiiils_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
lpm_hint : string := "true";
lpm_type : string := "cycloneiiils_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiiils_mac_mult;
ARCHITECTURE vital_cycloneiiils_mac_mult OF cycloneiiils_mac_mult IS
COMPONENT cycloneiiils_mac_data_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneiiils_mac_sign_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END COMPONENT;
COMPONENT cycloneiiils_mac_mult_internal
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END COMPONENT;
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL idataa_reg : std_logic_vector(17 DOWNTO 0); -- optional register for dataa input
SIGNAL idatab_reg : std_logic_vector(17 DOWNTO 0); -- optional register for datab input
SIGNAL isigna_reg : std_logic; -- optional register for signa input
SIGNAL isignb_reg : std_logic; -- optional register for signb input
SIGNAL idataa_int : std_logic_vector(17 DOWNTO 0); -- dataa as seen by the multiplier input
SIGNAL idatab_int : std_logic_vector(17 DOWNTO 0); -- datab as seen by the multiplier input
SIGNAL isigna_int : std_logic; -- signa as seen by the multiplier input
SIGNAL isignb_int : std_logic; -- signb as seen by the multiplier input
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
reg_aclr <= (NOT devpor) OR (NOT devclrn) OR (aclr) ;
-- padding input data to full bus width
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
-- Optional input registers for dataa,b and signa,b
dataa_reg : cycloneiiils_mac_data_reg
GENERIC MAP (
data_width => dataa_width)
PORT MAP (
clk => clk,
data => dataa_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idataa_reg);
datab_reg : cycloneiiils_mac_data_reg
GENERIC MAP (
data_width => datab_width)
PORT MAP (
clk => clk,
data => datab_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idatab_reg);
signa_reg : cycloneiiils_mac_sign_reg
PORT MAP (
clk => clk,
d => signa,
ena => ena,
aclr => reg_aclr,
q => isigna_reg);
signb_reg : cycloneiiils_mac_sign_reg
PORT MAP (
clk => clk,
d => signb,
ena => ena,
aclr => reg_aclr,
q => isignb_reg);
idataa_int <= dataa_ipd WHEN (dataa_clock = "none") ELSE idataa_reg;
idatab_int <= datab_ipd WHEN (datab_clock = "none") ELSE idatab_reg;
isigna_int <= signa WHEN (signa_clock = "none") ELSE isigna_reg;
isignb_int <= signb WHEN (signb_clock = "none") ELSE isignb_reg;
mac_multiply : cycloneiiils_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => idataa_int,
datab => idatab_int,
signa => isigna_int,
signb => isignb_int,
dataout => dataout
);
END vital_cycloneiiils_mac_mult;
--------------------------------------------------------------------
--
-- Module Name : cycloneiiils_mac_out
--
-- Description : Cyclone III LS MAC_OUT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_mac_out IS
GENERIC (
dataa_width : integer := 1;
output_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_hint : string := "true";
lpm_type : string := "cycloneiiils_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiiils_mac_out;
ARCHITECTURE vital_cycloneiiils_mac_out OF cycloneiiils_mac_out IS
-- internal variables
SIGNAL dataa_ipd : std_logic_vector(dataa'range);
SIGNAL clk_ipd : std_logic;
SIGNAL aclr_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
-- optional register
SIGNAL use_reg : std_logic;
SIGNAL dataout_tmp : std_logic_vector(dataout'range) := (OTHERS => '0');
BEGIN
---------------------
-- PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
VITALtiming : process (clk_ipd, aclr_ipd, dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), use_reg = '1'),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), use_reg = '1'),
2 => (dataa_ipd(i)'last_event, tpd_dataa_dataout(i), use_reg = '0')),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
use_reg <= '1' WHEN (output_clock /= "none") ELSE '0';
sh: block
begin
g0 : for i in dataa'range generate
VITALtiming : process (clk_ipd, ena_ipd, dataa_ipd(i))
variable Tviol_dataa_clk : std_ulogic := '0';
variable TimingData_dataa_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_dataa_clk,
TimingData => TimingData_dataa_clk,
TestSignal => dataa(i),
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_dataa_clk_noedge_posedge(i),
SetupLow => tsetup_dataa_clk_noedge_posedge(i),
HoldHigh => thold_dataa_clk_noedge_posedge(i),
HoldLow => thold_dataa_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR (NOT use_reg) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT use_reg)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
process (clk_ipd, aclr_ipd,ena_ipd, dataa_ipd)
begin
if (use_reg = '0') then
dataout_tmp <= dataa_ipd;
else
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= dataa_ipd;
end if;
end if;
end process;
END vital_cycloneiiils_mac_out;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_io_ibuf
--
-- Description : Cyclone III LS IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneiiils_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END cycloneiiils_io_ibuf;
ARCHITECTURE arch OF cycloneiiils_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_io_obuf
--
-- Description : Cyclone III LS IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiiils_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiiils_io_obuf;
ARCHITECTURE arch OF cycloneiiils_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
SIGNAL seriesterminationcontrol_ipd : std_logic_vector(15 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
g1 :for i in seriesterminationcontrol'range generate
VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i));
end generate;
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_ddio_oe
--
-- Description : Cyclone III LS DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiiils_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiiils_ddio_oe;
ARCHITECTURE arch OF cycloneiiils_ddio_oe IS
component cycloneiiils_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : cycloneiiils_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_latch
--
-- Description : Cyclone III LS latch VHDL simulation model
--
--
---------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_latch is
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneiiils_latch";
tsetup_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiiils_latch : entity is TRUE;
end cycloneiiils_latch;
architecture vital_latch of cycloneiiils_latch is
attribute VITAL_LEVEL0 of vital_latch : architecture is TRUE;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal clr_ipd : std_logic;
signal pre_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clr_ipd, clr, tipd_clr);
VitalWireDelay (pre_ipd, pre, tipd_pre);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( d_dly, clr_ipd, pre_ipd,ena_ipd)
variable Tviol_d_ena : std_ulogic := '0';
variable TimingData_d_ena : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_ena,
TimingData => TimingData_d_ena,
TestSignal => d_ipd,
TestSignalName => "DATAIN",
RefSignal => ena_ipd,
RefSignalName => "ENA",
SetupHigh => tsetup_d_ena_noedge_negedge,
SetupLow => tsetup_d_ena_noedge_negedge,
HoldHigh => thold_d_ena_noedge_negedge,
HoldLow => thold_d_ena_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiiils_latch",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
violation := Tviol_d_ena;
if ( (clr_ipd = '0')) then
iq := '0';
elsif (pre_ipd = '0') then
iq := '1';
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif (ena_ipd = '1') then
iq := d_dly;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clr_ipd'last_event, tpd_clr_q_negedge, TRUE),
1 => (pre_ipd'last_event, tpd_pre_q_negedge, TRUE),
2 => (ena_ipd'last_event, tpd_ena_q_negedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_latch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_ddio_out
--
-- Description : Cyclone III LS DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneiiils_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiiils_ddio_out;
ARCHITECTURE arch OF cycloneiiils_ddio_out IS
component cycloneiiils_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
component cycloneiiils_latch
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneiiils_latch";
tsetup_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal sel_mux_hi_in : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
signal dffhi_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
process(dffhi_tmp)
begin
dffhi_tmp1 <= dffhi_tmp;
end process;
--DDIO HIGH Register
clk_hi <= ((NOT clkhi_ipd) and ena_ipd) when(use_new_clocking_model = "true") else ((NOT clk_ipd) and ena_ipd);
datainhi_tmp <= '1' when (ddioreg_sclr ='0'and ddioreg_sload = '1')else '0'when (ddioreg_sclr ='1'and ddioreg_sload = '0') else datainhi;
ddioreg_hi : cycloneiiils_latch
PORT MAP (
d=> datainhi_tmp,
ena => clk_hi,
pre => ddioreg_prn,
clr => ddioreg_aclr,
q => dffhi_tmp
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= NOT mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi_tmp1;
sel_mux : cycloneiiils_mux21
port map (
A => sel_mux_hi_in,
B => sel_mux_lo_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi <= dffhi_tmp;
END arch;
----------------------------------------------------------------------------------
--Module Name: cycloneiiils_pseudo_diff_out --
--Description: Simulation model for Cyclone III LS Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneiiils_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiiils_pseudo_diff_out;
ARCHITECTURE arch OF cycloneiiils_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiiils_io_pad
-- Description : Simulation model for cycloneiiils IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY cycloneiiils_io_pad IS
GENERIC (
lpm_type : string := "cycloneiiils_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END cycloneiiils_io_pad;
ARCHITECTURE arch OF cycloneiiils_io_pad IS
BEGIN
padout <= padin;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiiils_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiiils_ena_reg : entity is TRUE;
end cycloneiiils_ena_reg;
ARCHITECTURE behave of cycloneiiils_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/cycloneiiils_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Cyclone III LS CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- CYCLONEIIILS_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
use work.cycloneiiils_ena_reg;
entity cycloneiiils_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiiils_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiiils_clkctrl : entity is TRUE;
end cycloneiiils_clkctrl;
architecture vital_clkctrl of cycloneiiils_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component cycloneiiils_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal outclk_tmp : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : cycloneiiils_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena1_reg : cycloneiiils_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk_tmp <= ena_out AND clkmux_out;
-- output path
process (inclk_ipd,outclk_tmp)
variable outclk_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => outclk,
OutSignalName => "OUTCLK",
OutTemp => outclk_tmp,
Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE),
1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE),
2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE),
3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE)),
GlitchData => outclk_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_clkctrl;
--
--
-- CYCLONEIIILS_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "cycloneiiils_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end cycloneiiils_rublock;
architecture architecture_rublock of cycloneiiils_rublock is
begin
end architecture_rublock;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_controller
--
-- Description : cycloneiiils CONTROLLER VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_controller is
generic (
lpm_type : string := "cycloneiiils_controller"
);
port (
nceout : out std_logic
);
end cycloneiiils_controller;
architecture architecture_controller of cycloneiiils_controller is
begin
end architecture_controller;
--------------------------------------------------------------------
--
-- Module Name : cycloneiiils_termination
--
-- Description : Cyclone III LS Termination Atom VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cycloneiiils_termination IS
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiiils_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END cycloneiiils_termination;
ARCHITECTURE cycloneiiils_termination_arch OF cycloneiiils_termination IS
SIGNAL rup_compout : std_logic := '0';
SIGNAL rdn_compout : std_logic := '1';
BEGIN
calibrationdone <= '1'; -- power-up calibration status
comparatorprobe <= rup_compout WHEN (pullup_control_to_core = "true") ELSE rdn_compout;
rup_compout <= rup;
rdn_compout <= not rdn;
END cycloneiiils_termination_arch;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_jtag
--
-- Description : cycloneiiils JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_jtag is
generic (
lpm_type : string := "cycloneiiils_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end cycloneiiils_jtag;
architecture architecture_jtag of cycloneiiils_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_crcblock
--
-- Description : Cyclone III LS CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiiils_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
cyclecomplete : out std_logic;
regout : out std_logic
);
end cycloneiiils_crcblock;
architecture architecture_crcblock of cycloneiiils_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
--
--
-- CYCLONEIIILS_OSCILLATOR Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_oscillator is
generic
(
lpm_type: string := "cycloneiiils_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
clkout1: out std_logic;
observableoutputport: out std_logic;
clkout : out std_logic
);
end cycloneiiils_oscillator;
architecture architecture_oscillator of cycloneiiils_oscillator is
signal oscena_ipd : std_logic;
signal int_osc : std_logic := '0';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (oscena_ipd, oscena, tipd_oscena);
end block;
VITAL_osc : process(oscena_ipd, int_osc)
variable OSC_PW : time := 6250 ps; -- pulse width for 80MHz clock
variable osc_VitalGlitchData : VitalGlitchDataType;
begin
if (oscena_ipd = '1') then
if ((int_osc = '0') or (int_osc = '1')) then
int_osc <= not int_osc after OSC_PW;
else
int_osc <= '0' after OSC_PW;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "osc",
OutTemp => int_osc,
Paths => (0 => (InputChangeTime => oscena_ipd'last_event,
PathDelay => tpd_oscena_clkout_posedge,
PathCondition => (oscena_ipd = '1'))),
GlitchData => osc_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end architecture_oscillator;
|
-- Test bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.ALL;
entity wasca_tb is
end entity wasca_tb;
architecture SIMULATE of wasca_tb is
-- Clock
signal clk_clk : std_logic ;
-- SDRAM
signal external_sdram_controller_wire_addr : std_logic_vector(12 downto 0);
signal external_sdram_controller_wire_ba : std_logic_vector( 1 downto 0);
signal external_sdram_controller_wire_cas_n : std_logic ;
signal external_sdram_controller_wire_cke : std_logic ;
signal external_sdram_controller_wire_cs_n : std_logic ;
signal external_sdram_controller_wire_dq : std_logic_vector(15 downto 0);
signal external_sdram_controller_wire_dqm : std_logic_vector( 1 downto 0);
signal external_sdram_controller_wire_ras_n : std_logic ;
signal external_sdram_controller_wire_we_n : std_logic ;
signal external_sdram_clk_pin : std_logic ;
-- Reset signal from Saturn
signal reset_reset_n : std_logic ;
-- A-Bus
signal abus_slave_0_abus_address : std_logic_vector(24 downto 16);
signal abus_slave_0_abus_addressdata : std_logic_vector(15 downto 0);
signal abus_slave_0_abus_chipselect : std_logic_vector( 2 downto 0);
signal abus_slave_0_abus_read : std_logic ;
signal abus_slave_0_abus_write : std_logic_vector( 1 downto 0);
signal abus_slave_0_abus_waitrequest : std_logic ;
signal abus_slave_0_abus_interrupt : std_logic ;
signal abus_slave_0_abus_disableout : std_logic ;
signal abus_slave_0_abus_muxing : std_logic_vector( 1 downto 0);
signal abus_slave_0_abus_direction : std_logic ;
-- SPI for SD card
--signal spi_sd_card_MISO : std_logic ;
--signal spi_sd_card_MOSI : std_logic ;
--signal spi_sd_card_SCLK : std_logic ;
--signal spi_sd_card_SS_n : std_logic ;
-- UART (FT232RL)
signal uart_0_external_connection_txd : std_logic ;
signal uart_0_external_connection_rxd : std_logic ;
-- LEDs
signal leds_conn_export : std_logic_vector( 2 downto 0);
-- Switches
signal switches_conn_export : std_logic_vector( 2 downto 0);
--- - SPI for STM32
-- signal spi_stm32_MISO : std_logic ;
-- signal spi_stm32_MOSI : std_logic ;
-- signal spi_stm32_SCLK : std_logic ;
-- signal spi_stm32_SS_n : std_logic ;
-- Audio output
--signal audio_out_BCLK : std_logic ;
--signal audio_out_DACDAT : std_logic ;
--signal audio_out_DACLRCK : std_logic ;
--signal audio_SSEL : std_logic ;
-- constant values
constant clk_in_t : time := 44.289 ns; -- SCSPCLK : 22.579 MHz -> 44.288941051419 ns
begin -- architecture SIMULATE
-- component instantiation
uut: entity work.wasca_toplevel
port map
(
clk_clk => clk_clk , -- in std_logic -- Saturn clock (22.579 MHz)
external_sdram_controller_wire_addr => external_sdram_controller_wire_addr , -- out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba => external_sdram_controller_wire_ba , -- out std_logic_vector( 1 downto 0); -- .ba
external_sdram_controller_wire_cas_n => external_sdram_controller_wire_cas_n , -- out std_logic -- .cas_n
external_sdram_controller_wire_cke => external_sdram_controller_wire_cke , -- out std_logic -- .cke
external_sdram_controller_wire_cs_n => external_sdram_controller_wire_cs_n , -- out std_logic -- .cs_n
external_sdram_controller_wire_dq => external_sdram_controller_wire_dq , -- inout std_logic_vector(15 downto 0) -- .dq
external_sdram_controller_wire_dqm => external_sdram_controller_wire_dqm , -- out std_logic_vector( 1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n => external_sdram_controller_wire_ras_n , -- out std_logic -- .ras_n
external_sdram_controller_wire_we_n => external_sdram_controller_wire_we_n , -- out std_logic -- .we_n
external_sdram_clk_pin => external_sdram_clk_pin , -- out std_logic -- .clk
reset_reset_n => reset_reset_n , -- in std_logic -- Saturn reset, power on.
abus_slave_0_abus_address => abus_slave_0_abus_address , -- in std_logic_vector(25 downto 16) -- abus_slave_0_abus.address
abus_slave_0_abus_addressdata => abus_slave_0_abus_addressdata , -- inout std_logic_vector(15 downto 0) -- .data
abus_slave_0_abus_chipselect => abus_slave_0_abus_chipselect , -- in std_logic_vector( 2 downto 0) -- .chipselect
abus_slave_0_abus_read => abus_slave_0_abus_read , -- in std_logic -- .read
abus_slave_0_abus_write => abus_slave_0_abus_write , -- in std_logic_vector( 1 downto 0) -- .write
abus_slave_0_abus_waitrequest => abus_slave_0_abus_waitrequest , -- out std_logic -- .waitrequest
abus_slave_0_abus_interrupt => abus_slave_0_abus_interrupt , -- out std_logic -- .interrupt
abus_slave_0_abus_disableout => abus_slave_0_abus_disableout , -- out std_logic -- .muxing
abus_slave_0_abus_muxing => abus_slave_0_abus_muxing , -- out std_logic_vector( 1 downto 0) -- .muxing
abus_slave_0_abus_direction => abus_slave_0_abus_direction , -- out std_logic -- .direction
--spi_sd_card_MISO => spi_sd_card_MISO , -- in std_logic -- MISO
--spi_sd_card_MOSI => spi_sd_card_MOSI , -- out std_logic -- MOSI
--spi_sd_card_SCLK => spi_sd_card_SCLK , -- out std_logic -- SCLK
--spi_sd_card_SS_n => spi_sd_card_SS_n , -- out std_logic -- SS_n
uart_0_external_connection_txd => uart_0_external_connection_txd , -- out std_logic --
uart_0_external_connection_rxd => uart_0_external_connection_rxd , -- in std_logic --
leds_conn_export => leds_conn_export , -- out std_logic_vector( 2 downto 0); -- leds_conn_export[0]: ledr1, leds_conn_export[1]: ledg1, leds_conn_export[2]: ledr2
switches_conn_export => switches_conn_export -- in std_logic_vector( 2 downto 0); -- switches_conn_export[0]: sw1, switches_conn_export[1]: sw2, switches_conn_export[2]: STM32 SPI synchronization
--spi_stm32_MISO => spi_stm32_MISO , -- in std_logic -- MISO
--spi_stm32_MOSI => spi_stm32_MOSI , -- out std_logic -- MOSI
--spi_stm32_SCLK => spi_stm32_SCLK , -- out std_logic -- SCLK
--spi_stm32_SS_n => spi_stm32_SS_n -- out std_logic -- SS_n
--audio_out_BCLK => audio_out_BCLK , -- in std_logic -- BCLK
--audio_out_DACDAT => audio_out_DACDAT , -- out std_logic -- DACDAT
--audio_out_DACLRCK => audio_out_DACLRCK , -- in std_logic -- DACLRCK
--audio_SSEL => audio_SSEL , -- out std_logic --
);
process is
begin -- process
-- Activate sysres signal on startup
reset_reset_n <= '0';
wait for 350 ns;
reset_reset_n <= '1';
wait for 999999 ns;
end process;
process is
begin -- SCSPCLK
clk_clk <= '0';
wait for clk_in_t / 2;
clk_clk <= '1';
wait for clk_in_t / 2;
end process;
-- process is
-- begin -- process
-- -- Dummy values for dout
-- io_sd_dout <= '0';
-- wait for 250 ns;
-- io_sd_dout <= '1';
-- wait for 150 ns;
-- end process;
process is
begin -- process
-- Test switchs always to '1'
switches_conn_export(0) <= '1';
switches_conn_export(1) <= '1';
switches_conn_export(2) <= '1';
wait for clk_in_t * 2;
end process;
-- process is
-- begin -- process
-- -- Beg for hardware version
-- io_address <= "001";
-- io_data <= "ZZZZZZZZ";
-- io_oe_al <= '0';
-- io_rd_al <= '0';
-- io_wr0 <= '0';
-- io_wr1 <= '0';
-- io_sd_adr <= '0';
--
--
--
--
-- wait for 50 ns;
-- io_wr0 <= '0';
-- io_wr1 <= '1';
-- wait for 50 ns;
-- io_wr0 <= '1';
-- io_wr1 <= '0';
--
-- -- Beg for dout pin state
-- io_address <= "000";
-- wait for 140 ns;
-- io_wr0 <= '1';
-- io_wr1 <= '1';
--
-- wait for 120 ns;
--
-- -- Write to CS/DIN/CLK pins
-- io_address <= "000";
-- io_data <= "00000111";
-- io_oe_al <= '1';
-- io_rd_al <= '1';
-- wait for 80 ns;
-- io_data <= "00000101";
-- wait for 80 ns;
-- io_data <= "00000100";
-- wait for 80 ns;
-- io_data <= "00000001";
--
--
-- wait for 700 ns;
-- end process;
-- process is
-- begin -- process
-- -- Ask for build date #1
-- io_up_addr <= "0110"; -- SD card
-- io_address <= "00000"; -- CPLD version
-- io_data <= "ZZZZZZZZZZZZZZZZ";
-- io_cs0_al <= '0';
-- io_rd_al <= '0';
-- io_wr0 <= '0';
-- io_wr1 <= '0';
-- wait for clk_in_t * 4;
--
-- -- Ask for build date #2
-- io_up_addr <= "0110"; -- SD card
-- io_address <= "00001"; -- CPLD version
-- io_data <= "ZZZZZZZZZZZZZZZZ";
-- io_cs0_al <= '0';
-- io_rd_al <= '0';
-- io_wr0 <= '0';
-- io_wr1 <= '0';
-- wait for clk_in_t * 4;
--
-- -- Ask for DOUT value
-- io_up_addr <= "0110"; -- SD card
-- io_address <= "01010"; -- DOUT read
-- io_data <= "ZZZZZZZZZZZZZZZZ";
-- io_cs0_al <= '0';
-- io_rd_al <= '0';
-- io_wr0 <= '0';
-- io_wr1 <= '0';
-- wait for clk_in_t * 4;
--
-- -- Set DIN/CS/CLK
-- io_up_addr <= "0110"; -- SD card
-- io_address <= "01000"; -- CS/DIN/CLK set
-- io_data <= "0000000000000100";
-- io_cs0_al <= '0';
-- io_rd_al <= '1';
-- io_wr0 <= '1';
-- io_wr1 <= '1';
-- wait for clk_in_t * 4;
-- -- Set DIN/CS/CLK
-- io_up_addr <= "0110"; -- SD card
-- io_address <= "01000"; -- CS/DIN/CLK set
-- io_data <= "0000000000000010";
-- io_cs0_al <= '0';
-- io_rd_al <= '1';
-- io_wr0 <= '1';
-- io_wr1 <= '1';
-- wait for clk_in_t * 4;
--
-- end process;
end architecture SIMULATE;
-------------------------------------------------------------------------------
--
-- -- Configuration for simulation
-- library work;
-- configuration wasca_tb_cfg of wasca_tb is
-- for SIMULATE
-- -- for DUTC : wasca_tb
-- -- use entity work.wasca(structure);
-- -- end for;
-- end for;
-- end wasca_tb_cfg;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: wizpll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY wizpll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END wizpll;
ARCHITECTURE SYN OF wizpll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=wizpll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "10"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "5.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "wizpll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:41:42 12/26/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs2/tb_datapath.vhd
-- Project Name: idea_rcs2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: datapath
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_datapath IS
END tb_datapath;
ARCHITECTURE behavior OF tb_datapath IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT datapath
PORT(
Clock : IN std_logic;
S : IN std_logic_vector(1 downto 0);
S_t : IN std_logic_vector(1 downto 0);
EN125 : IN std_logic;
EN346 : IN std_logic;
EN78 : IN std_logic;
X1 : IN std_logic_vector(15 downto 0);
X2 : IN std_logic_vector(15 downto 0);
X3 : IN std_logic_vector(15 downto 0);
X4 : IN std_logic_vector(15 downto 0);
Z1 : IN std_logic_vector(15 downto 0);
Z2 : IN std_logic_vector(15 downto 0);
Z3 : IN std_logic_vector(15 downto 0);
Z4 : IN std_logic_vector(15 downto 0);
Z5 : IN std_logic_vector(15 downto 0);
Z6 : IN std_logic_vector(15 downto 0);
Y1_trafo : OUT std_logic_vector(15 downto 0);
Y2_trafo : OUT std_logic_vector(15 downto 0);
Y3_trafo : OUT std_logic_vector(15 downto 0);
Y4_trafo : OUT std_logic_vector(15 downto 0);
Y1 : OUT std_logic_vector(15 downto 0);
Y2 : OUT std_logic_vector(15 downto 0);
Y3 : OUT std_logic_vector(15 downto 0);
Y4 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal Clock : std_logic := '0';
signal S : std_logic_vector(1 downto 0) := (others => '0');
signal S_t : std_logic_vector(1 downto 0) := (others => '0');
signal EN125 : std_logic := '0';
signal EN346 : std_logic := '0';
signal EN78 : std_logic := '0';
signal X1 : std_logic_vector(15 downto 0) := (others => '0');
signal X2 : std_logic_vector(15 downto 0) := (others => '0');
signal X3 : std_logic_vector(15 downto 0) := (others => '0');
signal X4 : std_logic_vector(15 downto 0) := (others => '0');
signal Z1 : std_logic_vector(15 downto 0) := (others => '0');
signal Z2 : std_logic_vector(15 downto 0) := (others => '0');
signal Z3 : std_logic_vector(15 downto 0) := (others => '0');
signal Z4 : std_logic_vector(15 downto 0) := (others => '0');
signal Z5 : std_logic_vector(15 downto 0) := (others => '0');
signal Z6 : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal Y1_trafo : std_logic_vector(15 downto 0);
signal Y2_trafo : std_logic_vector(15 downto 0);
signal Y3_trafo : std_logic_vector(15 downto 0);
signal Y4_trafo : std_logic_vector(15 downto 0);
signal Y1 : std_logic_vector(15 downto 0);
signal Y2 : std_logic_vector(15 downto 0);
signal Y3 : std_logic_vector(15 downto 0);
signal Y4 : std_logic_vector(15 downto 0);
-- Clock period definitions
constant Clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: datapath PORT MAP (
Clock => Clock,
S => S,
S_t => S_t,
EN125 => EN125,
EN346 => EN346,
EN78 => EN78,
X1 => X1,
X2 => X2,
X3 => X3,
X4 => X4,
Z1 => Z1,
Z2 => Z2,
Z3 => Z3,
Z4 => Z4,
Z5 => Z5,
Z6 => Z6,
Y1_trafo => Y1_trafo,
Y2_trafo => Y2_trafo,
Y3_trafo => Y3_trafo,
Y4_trafo => Y4_trafo,
Y1 => Y1,
Y2 => Y2,
Y3 => Y3,
Y4 => Y4
);
-- Clock process definitions
Clock_process :process
begin
Clock <= '0';
wait for Clock_period/2;
Clock <= '1';
wait for Clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clock_period*10;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:41:42 12/26/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs2/tb_datapath.vhd
-- Project Name: idea_rcs2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: datapath
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_datapath IS
END tb_datapath;
ARCHITECTURE behavior OF tb_datapath IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT datapath
PORT(
Clock : IN std_logic;
S : IN std_logic_vector(1 downto 0);
S_t : IN std_logic_vector(1 downto 0);
EN125 : IN std_logic;
EN346 : IN std_logic;
EN78 : IN std_logic;
X1 : IN std_logic_vector(15 downto 0);
X2 : IN std_logic_vector(15 downto 0);
X3 : IN std_logic_vector(15 downto 0);
X4 : IN std_logic_vector(15 downto 0);
Z1 : IN std_logic_vector(15 downto 0);
Z2 : IN std_logic_vector(15 downto 0);
Z3 : IN std_logic_vector(15 downto 0);
Z4 : IN std_logic_vector(15 downto 0);
Z5 : IN std_logic_vector(15 downto 0);
Z6 : IN std_logic_vector(15 downto 0);
Y1_trafo : OUT std_logic_vector(15 downto 0);
Y2_trafo : OUT std_logic_vector(15 downto 0);
Y3_trafo : OUT std_logic_vector(15 downto 0);
Y4_trafo : OUT std_logic_vector(15 downto 0);
Y1 : OUT std_logic_vector(15 downto 0);
Y2 : OUT std_logic_vector(15 downto 0);
Y3 : OUT std_logic_vector(15 downto 0);
Y4 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal Clock : std_logic := '0';
signal S : std_logic_vector(1 downto 0) := (others => '0');
signal S_t : std_logic_vector(1 downto 0) := (others => '0');
signal EN125 : std_logic := '0';
signal EN346 : std_logic := '0';
signal EN78 : std_logic := '0';
signal X1 : std_logic_vector(15 downto 0) := (others => '0');
signal X2 : std_logic_vector(15 downto 0) := (others => '0');
signal X3 : std_logic_vector(15 downto 0) := (others => '0');
signal X4 : std_logic_vector(15 downto 0) := (others => '0');
signal Z1 : std_logic_vector(15 downto 0) := (others => '0');
signal Z2 : std_logic_vector(15 downto 0) := (others => '0');
signal Z3 : std_logic_vector(15 downto 0) := (others => '0');
signal Z4 : std_logic_vector(15 downto 0) := (others => '0');
signal Z5 : std_logic_vector(15 downto 0) := (others => '0');
signal Z6 : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal Y1_trafo : std_logic_vector(15 downto 0);
signal Y2_trafo : std_logic_vector(15 downto 0);
signal Y3_trafo : std_logic_vector(15 downto 0);
signal Y4_trafo : std_logic_vector(15 downto 0);
signal Y1 : std_logic_vector(15 downto 0);
signal Y2 : std_logic_vector(15 downto 0);
signal Y3 : std_logic_vector(15 downto 0);
signal Y4 : std_logic_vector(15 downto 0);
-- Clock period definitions
constant Clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: datapath PORT MAP (
Clock => Clock,
S => S,
S_t => S_t,
EN125 => EN125,
EN346 => EN346,
EN78 => EN78,
X1 => X1,
X2 => X2,
X3 => X3,
X4 => X4,
Z1 => Z1,
Z2 => Z2,
Z3 => Z3,
Z4 => Z4,
Z5 => Z5,
Z6 => Z6,
Y1_trafo => Y1_trafo,
Y2_trafo => Y2_trafo,
Y3_trafo => Y3_trafo,
Y4_trafo => Y4_trafo,
Y1 => Y1,
Y2 => Y2,
Y3 => Y3,
Y4 => Y4
);
-- Clock process definitions
Clock_process :process
begin
Clock <= '0';
wait for Clock_period/2;
Clock <= '1';
wait for Clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clock_period*10;
-- insert stimulus here
wait;
end process;
END;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: CLK4Hz
-- Project Name: CLOCK COUNTER
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Clock Divider
-- Lower the Clock frequency from
-- 50 Mhz to 4 hz
-- 50Mhz = 50,000,000/12,500,000 = 2 Hz
-- 4Hz ~= 1/2 second
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk4Hz is
Port ( CLK_IN : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end clk4Hz;
architecture Behavioral of clk4Hz is
signal clkdv: STD_LOGIC:='0';
signal counter : integer range 0 to 12500000 := 0;
begin
frequency_divider: process (RST, CLK_IN) begin
if (RST = '1') then
clkdv <= '0';
counter <= 0;
elsif rising_edge(CLK_IN) then
if (counter = 12500000) then
if(clkdv='0') then
clkdv <= '1';
else
clkdv <= '0';
end if;
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
CLK_OUT <= clkdv;
end Behavioral;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:19:39 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ led_controller_design_led_controller_0_1_sim_netlist.vhdl
-- Design : led_controller_design_led_controller_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI is
port (
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_bvalid : out STD_LOGIC;
s00_axi_arvalid : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_aresetn : in STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI is
signal \^leds_out\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal aw_en_i_1_n_0 : STD_LOGIC;
signal aw_en_reg_n_0 : STD_LOGIC;
signal axi_araddr : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \axi_araddr[2]_i_1_n_0\ : STD_LOGIC;
signal \axi_araddr[3]_i_1_n_0\ : STD_LOGIC;
signal axi_arready_i_1_n_0 : STD_LOGIC;
signal \axi_awaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \axi_awaddr[3]_i_1_n_0\ : STD_LOGIC;
signal axi_awready0 : STD_LOGIC;
signal axi_bvalid_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_i_1_n_0 : STD_LOGIC;
signal axi_wready0 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 7 );
signal reg_data_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s00_axi_bvalid\ : STD_LOGIC;
signal \^s00_axi_rvalid\ : STD_LOGIC;
signal slv_reg0 : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \slv_reg0[7]_i_1_n_0\ : STD_LOGIC;
signal slv_reg1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \slv_reg1[15]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg1[23]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg1[31]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg1[7]_i_1_n_0\ : STD_LOGIC;
signal slv_reg2 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \slv_reg2[15]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg2[23]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg2[31]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg2[7]_i_1_n_0\ : STD_LOGIC;
signal slv_reg3 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \slv_reg3[15]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg3[23]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg3[31]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg3[7]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg_rden__0\ : STD_LOGIC;
signal \slv_reg_wren__0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axi_araddr[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of axi_arready_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of axi_wready_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \slv_reg0[7]_i_3\ : label is "soft_lutpair0";
begin
LEDs_out(7 downto 0) <= \^leds_out\(7 downto 0);
S_AXI_ARREADY <= \^s_axi_arready\;
S_AXI_AWREADY <= \^s_axi_awready\;
S_AXI_WREADY <= \^s_axi_wready\;
s00_axi_bvalid <= \^s00_axi_bvalid\;
s00_axi_rvalid <= \^s00_axi_rvalid\;
aw_en_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFC4CCC4CCC4CC"
)
port map (
I0 => s00_axi_wvalid,
I1 => aw_en_reg_n_0,
I2 => \^s_axi_awready\,
I3 => s00_axi_awvalid,
I4 => s00_axi_bready,
I5 => \^s00_axi_bvalid\,
O => aw_en_i_1_n_0
);
aw_en_reg: unisim.vcomponents.FDSE
port map (
C => s00_axi_aclk,
CE => '1',
D => aw_en_i_1_n_0,
Q => aw_en_reg_n_0,
S => \slv_reg0[7]_i_1_n_0\
);
\axi_araddr[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s00_axi_araddr(0),
I1 => s00_axi_arvalid,
I2 => \^s_axi_arready\,
I3 => axi_araddr(2),
O => \axi_araddr[2]_i_1_n_0\
);
\axi_araddr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s00_axi_araddr(1),
I1 => s00_axi_arvalid,
I2 => \^s_axi_arready\,
I3 => axi_araddr(3),
O => \axi_araddr[3]_i_1_n_0\
);
\axi_araddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_araddr[2]_i_1_n_0\,
Q => axi_araddr(2),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_araddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_araddr[3]_i_1_n_0\,
Q => axi_araddr(3),
R => \slv_reg0[7]_i_1_n_0\
);
axi_arready_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s00_axi_arvalid,
I1 => \^s_axi_arready\,
O => axi_arready_i_1_n_0
);
axi_arready_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_arready_i_1_n_0,
Q => \^s_axi_arready\,
R => \slv_reg0[7]_i_1_n_0\
);
\axi_awaddr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFFFF08000000"
)
port map (
I0 => s00_axi_awaddr(0),
I1 => s00_axi_awvalid,
I2 => \^s_axi_awready\,
I3 => aw_en_reg_n_0,
I4 => s00_axi_wvalid,
I5 => p_0_in(0),
O => \axi_awaddr[2]_i_1_n_0\
);
\axi_awaddr[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFFFF08000000"
)
port map (
I0 => s00_axi_awaddr(1),
I1 => s00_axi_awvalid,
I2 => \^s_axi_awready\,
I3 => aw_en_reg_n_0,
I4 => s00_axi_wvalid,
I5 => p_0_in(1),
O => \axi_awaddr[3]_i_1_n_0\
);
\axi_awaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_awaddr[2]_i_1_n_0\,
Q => p_0_in(0),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_awaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_awaddr[3]_i_1_n_0\,
Q => p_0_in(1),
R => \slv_reg0[7]_i_1_n_0\
);
axi_awready_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => s00_axi_awvalid,
I1 => \^s_axi_awready\,
I2 => aw_en_reg_n_0,
I3 => s00_axi_wvalid,
O => axi_awready0
);
axi_awready_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_awready0,
Q => \^s_axi_awready\,
R => \slv_reg0[7]_i_1_n_0\
);
axi_bvalid_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF80008000"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_awready\,
I2 => s00_axi_awvalid,
I3 => s00_axi_wvalid,
I4 => s00_axi_bready,
I5 => \^s00_axi_bvalid\,
O => axi_bvalid_i_1_n_0
);
axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_bvalid_i_1_n_0,
Q => \^s00_axi_bvalid\,
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(0),
I1 => \^leds_out\(0),
I2 => slv_reg3(0),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(0),
O => reg_data_out(0)
);
\axi_rdata[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(10),
I1 => slv_reg0(10),
I2 => slv_reg3(10),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(10),
O => reg_data_out(10)
);
\axi_rdata[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(11),
I1 => slv_reg0(11),
I2 => slv_reg3(11),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(11),
O => reg_data_out(11)
);
\axi_rdata[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(12),
I1 => slv_reg0(12),
I2 => slv_reg3(12),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(12),
O => reg_data_out(12)
);
\axi_rdata[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(13),
I1 => slv_reg0(13),
I2 => slv_reg3(13),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(13),
O => reg_data_out(13)
);
\axi_rdata[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(14),
I1 => slv_reg0(14),
I2 => slv_reg3(14),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(14),
O => reg_data_out(14)
);
\axi_rdata[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(15),
I1 => slv_reg0(15),
I2 => slv_reg3(15),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(15),
O => reg_data_out(15)
);
\axi_rdata[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(16),
I1 => slv_reg0(16),
I2 => slv_reg3(16),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(16),
O => reg_data_out(16)
);
\axi_rdata[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(17),
I1 => slv_reg0(17),
I2 => slv_reg3(17),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(17),
O => reg_data_out(17)
);
\axi_rdata[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(18),
I1 => slv_reg0(18),
I2 => slv_reg3(18),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(18),
O => reg_data_out(18)
);
\axi_rdata[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(19),
I1 => slv_reg0(19),
I2 => slv_reg3(19),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(19),
O => reg_data_out(19)
);
\axi_rdata[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(1),
I1 => \^leds_out\(1),
I2 => slv_reg3(1),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(1),
O => reg_data_out(1)
);
\axi_rdata[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(20),
I1 => slv_reg0(20),
I2 => slv_reg3(20),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(20),
O => reg_data_out(20)
);
\axi_rdata[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(21),
I1 => slv_reg0(21),
I2 => slv_reg3(21),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(21),
O => reg_data_out(21)
);
\axi_rdata[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(22),
I1 => slv_reg0(22),
I2 => slv_reg3(22),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(22),
O => reg_data_out(22)
);
\axi_rdata[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(23),
I1 => slv_reg0(23),
I2 => slv_reg3(23),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(23),
O => reg_data_out(23)
);
\axi_rdata[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(24),
I1 => slv_reg0(24),
I2 => slv_reg3(24),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(24),
O => reg_data_out(24)
);
\axi_rdata[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(25),
I1 => slv_reg0(25),
I2 => slv_reg3(25),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(25),
O => reg_data_out(25)
);
\axi_rdata[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(26),
I1 => slv_reg0(26),
I2 => slv_reg3(26),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(26),
O => reg_data_out(26)
);
\axi_rdata[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(27),
I1 => slv_reg0(27),
I2 => slv_reg3(27),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(27),
O => reg_data_out(27)
);
\axi_rdata[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(28),
I1 => slv_reg0(28),
I2 => slv_reg3(28),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(28),
O => reg_data_out(28)
);
\axi_rdata[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(29),
I1 => slv_reg0(29),
I2 => slv_reg3(29),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(29),
O => reg_data_out(29)
);
\axi_rdata[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(2),
I1 => \^leds_out\(2),
I2 => slv_reg3(2),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(2),
O => reg_data_out(2)
);
\axi_rdata[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(30),
I1 => slv_reg0(30),
I2 => slv_reg3(30),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(30),
O => reg_data_out(30)
);
\axi_rdata[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(31),
I1 => slv_reg0(31),
I2 => slv_reg3(31),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(31),
O => reg_data_out(31)
);
\axi_rdata[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(3),
I1 => \^leds_out\(3),
I2 => slv_reg3(3),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(3),
O => reg_data_out(3)
);
\axi_rdata[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(4),
I1 => \^leds_out\(4),
I2 => slv_reg3(4),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(4),
O => reg_data_out(4)
);
\axi_rdata[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(5),
I1 => \^leds_out\(5),
I2 => slv_reg3(5),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(5),
O => reg_data_out(5)
);
\axi_rdata[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(6),
I1 => \^leds_out\(6),
I2 => slv_reg3(6),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(6),
O => reg_data_out(6)
);
\axi_rdata[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(7),
I1 => \^leds_out\(7),
I2 => slv_reg3(7),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(7),
O => reg_data_out(7)
);
\axi_rdata[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(8),
I1 => slv_reg0(8),
I2 => slv_reg3(8),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(8),
O => reg_data_out(8)
);
\axi_rdata[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(9),
I1 => slv_reg0(9),
I2 => slv_reg3(9),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(9),
O => reg_data_out(9)
);
\axi_rdata_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(0),
Q => s00_axi_rdata(0),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(10),
Q => s00_axi_rdata(10),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(11),
Q => s00_axi_rdata(11),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(12),
Q => s00_axi_rdata(12),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(13),
Q => s00_axi_rdata(13),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(14),
Q => s00_axi_rdata(14),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(15),
Q => s00_axi_rdata(15),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(16),
Q => s00_axi_rdata(16),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(17),
Q => s00_axi_rdata(17),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(18),
Q => s00_axi_rdata(18),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(19),
Q => s00_axi_rdata(19),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(1),
Q => s00_axi_rdata(1),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(20),
Q => s00_axi_rdata(20),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(21),
Q => s00_axi_rdata(21),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(22),
Q => s00_axi_rdata(22),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(23),
Q => s00_axi_rdata(23),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(24),
Q => s00_axi_rdata(24),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(25),
Q => s00_axi_rdata(25),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(26),
Q => s00_axi_rdata(26),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(27),
Q => s00_axi_rdata(27),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(28),
Q => s00_axi_rdata(28),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(29),
Q => s00_axi_rdata(29),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(2),
Q => s00_axi_rdata(2),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(30),
Q => s00_axi_rdata(30),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(31),
Q => s00_axi_rdata(31),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(3),
Q => s00_axi_rdata(3),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(4),
Q => s00_axi_rdata(4),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(5),
Q => s00_axi_rdata(5),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(6),
Q => s00_axi_rdata(6),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(7),
Q => s00_axi_rdata(7),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(8),
Q => s00_axi_rdata(8),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(9),
Q => s00_axi_rdata(9),
R => \slv_reg0[7]_i_1_n_0\
);
axi_rvalid_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"08F8"
)
port map (
I0 => \^s_axi_arready\,
I1 => s00_axi_arvalid,
I2 => \^s00_axi_rvalid\,
I3 => s00_axi_rready,
O => axi_rvalid_i_1_n_0
);
axi_rvalid_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_rvalid_i_1_n_0,
Q => \^s00_axi_rvalid\,
R => \slv_reg0[7]_i_1_n_0\
);
axi_wready_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \^s_axi_wready\,
I1 => s00_axi_wvalid,
I2 => s00_axi_awvalid,
I3 => aw_en_reg_n_0,
O => axi_wready0
);
axi_wready_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_wready0,
Q => \^s_axi_wready\,
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(1),
O => p_1_in(15)
);
\slv_reg0[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(2),
O => p_1_in(23)
);
\slv_reg0[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(3),
O => p_1_in(31)
);
\slv_reg0[7]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s00_axi_aresetn,
O => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(0),
O => p_1_in(7)
);
\slv_reg0[7]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_awready\,
I2 => s00_axi_awvalid,
I3 => s00_axi_wvalid,
O => \slv_reg_wren__0\
);
\slv_reg0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(0),
Q => \^leds_out\(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(10),
Q => slv_reg0(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(11),
Q => slv_reg0(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(12),
Q => slv_reg0(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(13),
Q => slv_reg0(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(14),
Q => slv_reg0(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(15),
Q => slv_reg0(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(16),
Q => slv_reg0(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(17),
Q => slv_reg0(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(18),
Q => slv_reg0(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(19),
Q => slv_reg0(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(1),
Q => \^leds_out\(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(20),
Q => slv_reg0(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(21),
Q => slv_reg0(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(22),
Q => slv_reg0(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(23),
Q => slv_reg0(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(24),
Q => slv_reg0(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(25),
Q => slv_reg0(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(26),
Q => slv_reg0(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(27),
Q => slv_reg0(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(28),
Q => slv_reg0(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(29),
Q => slv_reg0(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(2),
Q => \^leds_out\(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(30),
Q => slv_reg0(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(31),
Q => slv_reg0(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(3),
Q => \^leds_out\(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(4),
Q => \^leds_out\(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(5),
Q => \^leds_out\(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(6),
Q => \^leds_out\(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(7),
Q => \^leds_out\(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(8),
Q => slv_reg0(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(9),
Q => slv_reg0(9),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(1),
I3 => p_0_in(0),
O => \slv_reg1[15]_i_1_n_0\
);
\slv_reg1[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(2),
I3 => p_0_in(0),
O => \slv_reg1[23]_i_1_n_0\
);
\slv_reg1[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(3),
I3 => p_0_in(0),
O => \slv_reg1[31]_i_1_n_0\
);
\slv_reg1[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(0),
I3 => p_0_in(0),
O => \slv_reg1[7]_i_1_n_0\
);
\slv_reg1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(0),
Q => slv_reg1(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(10),
Q => slv_reg1(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(11),
Q => slv_reg1(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(12),
Q => slv_reg1(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(13),
Q => slv_reg1(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(14),
Q => slv_reg1(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(15),
Q => slv_reg1(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(16),
Q => slv_reg1(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(17),
Q => slv_reg1(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(18),
Q => slv_reg1(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(19),
Q => slv_reg1(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(1),
Q => slv_reg1(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(20),
Q => slv_reg1(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(21),
Q => slv_reg1(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(22),
Q => slv_reg1(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(23),
Q => slv_reg1(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(24),
Q => slv_reg1(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(25),
Q => slv_reg1(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(26),
Q => slv_reg1(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(27),
Q => slv_reg1(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(28),
Q => slv_reg1(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(29),
Q => slv_reg1(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(2),
Q => slv_reg1(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(30),
Q => slv_reg1(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(31),
Q => slv_reg1(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(3),
Q => slv_reg1(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(4),
Q => slv_reg1(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(5),
Q => slv_reg1(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(6),
Q => slv_reg1(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(7),
Q => slv_reg1(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(8),
Q => slv_reg1(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(9),
Q => slv_reg1(9),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(1),
I3 => p_0_in(0),
O => \slv_reg2[15]_i_1_n_0\
);
\slv_reg2[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(2),
I3 => p_0_in(0),
O => \slv_reg2[23]_i_1_n_0\
);
\slv_reg2[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(3),
I3 => p_0_in(0),
O => \slv_reg2[31]_i_1_n_0\
);
\slv_reg2[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(0),
I3 => p_0_in(0),
O => \slv_reg2[7]_i_1_n_0\
);
\slv_reg2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(0),
Q => slv_reg2(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(10),
Q => slv_reg2(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(11),
Q => slv_reg2(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(12),
Q => slv_reg2(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(13),
Q => slv_reg2(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(14),
Q => slv_reg2(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(15),
Q => slv_reg2(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(16),
Q => slv_reg2(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(17),
Q => slv_reg2(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(18),
Q => slv_reg2(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(19),
Q => slv_reg2(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(1),
Q => slv_reg2(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(20),
Q => slv_reg2(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(21),
Q => slv_reg2(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(22),
Q => slv_reg2(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(23),
Q => slv_reg2(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(24),
Q => slv_reg2(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(25),
Q => slv_reg2(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(26),
Q => slv_reg2(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(27),
Q => slv_reg2(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(28),
Q => slv_reg2(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(29),
Q => slv_reg2(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(2),
Q => slv_reg2(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(30),
Q => slv_reg2(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(31),
Q => slv_reg2(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(3),
Q => slv_reg2(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(4),
Q => slv_reg2(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(5),
Q => slv_reg2(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(6),
Q => slv_reg2(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(7),
Q => slv_reg2(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(8),
Q => slv_reg2(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(9),
Q => slv_reg2(9),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(1),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[15]_i_1_n_0\
);
\slv_reg3[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(2),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[23]_i_1_n_0\
);
\slv_reg3[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(3),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[31]_i_1_n_0\
);
\slv_reg3[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(0),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[7]_i_1_n_0\
);
\slv_reg3_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(0),
Q => slv_reg3(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(10),
Q => slv_reg3(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(11),
Q => slv_reg3(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(12),
Q => slv_reg3(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(13),
Q => slv_reg3(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(14),
Q => slv_reg3(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(15),
Q => slv_reg3(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(16),
Q => slv_reg3(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(17),
Q => slv_reg3(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(18),
Q => slv_reg3(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(19),
Q => slv_reg3(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(1),
Q => slv_reg3(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(20),
Q => slv_reg3(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(21),
Q => slv_reg3(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(22),
Q => slv_reg3(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(23),
Q => slv_reg3(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(24),
Q => slv_reg3(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(25),
Q => slv_reg3(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(26),
Q => slv_reg3(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(27),
Q => slv_reg3(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(28),
Q => slv_reg3(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(29),
Q => slv_reg3(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(2),
Q => slv_reg3(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(30),
Q => slv_reg3(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(31),
Q => slv_reg3(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(3),
Q => slv_reg3(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(4),
Q => slv_reg3(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(5),
Q => slv_reg3(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(6),
Q => slv_reg3(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(7),
Q => slv_reg3(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(8),
Q => slv_reg3(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(9),
Q => slv_reg3(9),
R => \slv_reg0[7]_i_1_n_0\
);
slv_reg_rden: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^s00_axi_rvalid\,
I1 => s00_axi_arvalid,
I2 => \^s_axi_arready\,
O => \slv_reg_rden__0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0 is
port (
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_bvalid : out STD_LOGIC;
s00_axi_arvalid : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_aresetn : in STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0 is
begin
led_controller_v1_0_S00_AXI_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI
port map (
LEDs_out(7 downto 0) => LEDs_out(7 downto 0),
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WREADY => S_AXI_WREADY,
s00_axi_aclk => s00_axi_aclk,
s00_axi_araddr(1 downto 0) => s00_axi_araddr(1 downto 0),
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_awaddr(1 downto 0) => s00_axi_awaddr(1 downto 0),
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
s00_axi_rready => s00_axi_rready,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
s00_axi_wvalid => s00_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "led_controller_design_led_controller_0_1,led_controller_v1_0,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "led_controller_v1_0,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal \<const0>\ : STD_LOGIC;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of s00_axi_aclk : signal is "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of s00_axi_aclk : signal is "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of s00_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
attribute X_INTERFACE_PARAMETER of s00_axi_aresetn : signal is "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of s00_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
attribute X_INTERFACE_INFO of s00_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
attribute X_INTERFACE_INFO of s00_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
attribute X_INTERFACE_INFO of s00_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
attribute X_INTERFACE_INFO of s00_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
attribute X_INTERFACE_INFO of s00_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
attribute X_INTERFACE_INFO of s00_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
attribute X_INTERFACE_PARAMETER of s00_axi_rready : signal is "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s00_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
attribute X_INTERFACE_INFO of s00_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
attribute X_INTERFACE_INFO of s00_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
attribute X_INTERFACE_INFO of s00_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
attribute X_INTERFACE_INFO of s00_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
attribute X_INTERFACE_INFO of s00_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
attribute X_INTERFACE_INFO of s00_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
attribute X_INTERFACE_INFO of s00_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
attribute X_INTERFACE_INFO of s00_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
attribute X_INTERFACE_INFO of s00_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
attribute X_INTERFACE_INFO of s00_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
attribute X_INTERFACE_INFO of s00_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
begin
s00_axi_bresp(1) <= \<const0>\;
s00_axi_bresp(0) <= \<const0>\;
s00_axi_rresp(1) <= \<const0>\;
s00_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0
port map (
LEDs_out(7 downto 0) => LEDs_out(7 downto 0),
S_AXI_ARREADY => s00_axi_arready,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WREADY => s00_axi_wready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_araddr(1 downto 0) => s00_axi_araddr(3 downto 2),
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_awaddr(1 downto 0) => s00_axi_awaddr(3 downto 2),
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
s00_axi_rready => s00_axi_rready,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
s00_axi_wvalid => s00_axi_wvalid
);
end STRUCTURE;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Counter_rst_set_n_bits
-- Module Name: Counter_rst_set_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Counter of size bits with reset and set signal, that only increments when ce equals to 1.
-- The reset and set are synchronous.
-- The value loaded during reset is defined by reset_value.
-- The value loaded during set is defined by set_value.
--
-- The circuits parameters
--
-- size :
--
-- The size of the counter in bits.
--
-- increment_value :
--
-- The amount will be incremented each cycle.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_rst_set_nbits is
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
set : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
set_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end counter_rst_set_nbits;
architecture Behavioral of counter_rst_set_nbits is
signal internal_value : UNSIGNED((size - 1) downto 0);
begin
process(clk, ce, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
internal_value <= unsigned(rst_value);
elsif(set = '1') then
internal_value <= unsigned(set_value);
elsif(ce = '1') then
internal_value <= internal_value + to_unsigned(increment_value, internal_value'Length);
else
null;
end if;
end if;
end process;
q <= std_logic_vector(internal_value);
end Behavioral; |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY system_axi_gpio_led_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END system_axi_gpio_led_0;
ARCHITECTURE system_axi_gpio_led_0_arch OF system_axi_gpio_led_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_led_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_gpio_led_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_gpio_led_0_arch : ARCHITECTURE IS "system_axi_gpio_led_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_gpio_led_0_arch: ARCHITECTURE IS "system_axi_gpio_led_0,axi_gpio,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=12,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=1,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 12,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => gpio2_io_i,
gpio2_io_o => gpio2_io_o,
gpio2_io_t => gpio2_io_t
);
END system_axi_gpio_led_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity LX9CoProZ80 is
port (
-- GOP Signals
fastclk : in std_logic;
test : inout std_logic_vector(8 downto 1);
sw : in std_logic_vector(3 downto 0);
-- Tube signals (use 16 out of 22 DIL pins)
h_phi2 : in std_logic; -- 1,2,12,21,23 are global clocks
h_addr : in std_logic_vector(2 downto 0);
h_data : inout std_logic_vector(7 downto 0);
h_rdnw : in std_logic;
h_cs_b : in std_logic;
h_rst_b : in std_logic;
h_irq_b : inout std_logic;
-- Ram Signals
ram_ub_b : out std_logic;
ram_lb_b : out std_logic;
ram_cs : out std_logic;
ram_oe : out std_logic;
ram_wr : out std_logic;
ram_addr : out std_logic_vector (18 downto 0);
ram_data : inout std_logic_vector (7 downto 0)
);
end LX9CoProZ80;
architecture BEHAVIORAL of LX9CoProZ80 is
-------------------------------------------------
-- clock and reset signals
-------------------------------------------------
signal cpu_clk : std_logic;
signal cpu_clken : std_logic;
signal bootmode : std_logic;
signal RSTn : std_logic;
signal RSTn_sync : std_logic;
-------------------------------------------------
-- parasite signals
-------------------------------------------------
signal p_cs_b : std_logic;
signal tube_cs_b : std_logic;
signal p_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- ram/rom signals
-------------------------------------------------
signal ram_cs_b : std_logic;
signal ram_oe_int : std_logic;
signal ram_wr_int : std_logic;
signal rom_cs_b : std_logic;
signal rom_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- cpu signals
-------------------------------------------------
signal cpu_rd_n : std_logic;
signal cpu_wr_n : std_logic;
signal cpu_iorq_n : std_logic;
signal cpu_mreq_n : std_logic;
signal cpu_m1_n : std_logic;
signal cpu_addr : std_logic_vector (15 downto 0);
signal cpu_din : std_logic_vector (7 downto 0);
signal cpu_dout : std_logic_vector (7 downto 0);
signal cpu_IRQ_n : std_logic;
signal cpu_NMI_n : std_logic;
signal cpu_IRQ_n_sync : std_logic;
signal cpu_NMI_n_sync : std_logic;
begin
---------------------------------------------------------------------
-- instantiated components
---------------------------------------------------------------------
inst_ICAP_config : entity work.ICAP_config port map (
fastclk => fastclk,
sw_in => sw,
sw_out => open,
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b
);
inst_dcm_32_16 : entity work.dcm_32_16 port map (
CLKIN_IN => fastclk,
CLK0_OUT => cpu_clk,
CLK0_OUT1 => open,
CLK2X_OUT => open);
inst_tuberom : entity work.tuberom_z80 port map (
CLK => cpu_clk,
ADDR => cpu_addr(11 downto 0),
DATA => rom_data_out
);
inst_Z80 : entity work.T80se port map (
RESET_n => RSTn_sync,
CLK_n => cpu_clk,
CLKEN => cpu_clken,
WAIT_n => '1',
INT_n => cpu_IRQ_n_sync,
NMI_n => cpu_NMI_n_sync,
BUSRQ_n => '1',
M1_n => cpu_m1_n,
MREQ_n => cpu_mreq_n,
IORQ_n => cpu_iorq_n,
RD_n => cpu_rd_n,
WR_n => cpu_wr_n,
RFSH_n => open,
HALT_n => open,
BUSAK_n => open,
A => cpu_addr,
DI => cpu_din,
DO => cpu_dout
);
inst_tube: entity work.tube port map (
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b,
h_irq_b => h_irq_b,
p_addr => cpu_addr(2 downto 0),
p_cs_b => tube_cs_b,
p_data_in => cpu_dout,
p_data_out => p_data_out,
p_phi2 => cpu_clk,
p_rdnw => cpu_wr_n,
p_rst_b => RSTn,
p_nmi_b => cpu_NMI_n,
p_irq_b => cpu_IRQ_n
);
tube_cs_b <= not ((not p_cs_b) and cpu_clken);
p_cs_b <= '0' when cpu_mreq_n = '1' and cpu_iorq_n = '0' and cpu_addr(7 downto 3) = "00000" else '1';
rom_cs_b <= '0' when cpu_mreq_n = '0' and cpu_rd_n = '0' and bootmode = '1' else '1';
ram_cs_b <= '0' when cpu_mreq_n = '0' and rom_cs_b = '1' else '1';
cpu_din <=
p_data_out when p_cs_b = '0' else
rom_data_out when rom_cs_b = '0' else
ram_data when ram_cs_b = '0' else
x"fe";
ram_ub_b <= '0';
ram_lb_b <= '0';
ram_cs <= ram_cs_b;
ram_oe_int <= not ((not ram_cs_b) and (not cpu_rd_n));
ram_oe <= ram_oe_int;
ram_wr_int <= not ((not ram_cs_b) and (not cpu_wr_n));
ram_wr <= ram_wr_int;
ram_addr <= "000" & cpu_addr;
ram_data <= cpu_dout when cpu_wr_n = '0' else "ZZZZZZZZ";
--------------------------------------------------------
-- test signals
--------------------------------------------------------
-- default to hi-impedence, to avoid conflicts with
-- a Raspberry Pi connected to the test connector
test <= (others => 'Z');
--------------------------------------------------------
-- boot mode generator
--------------------------------------------------------
boot_gen : process(cpu_clk, RSTn_sync)
begin
if RSTn_sync = '0' then
bootmode <= '1';
elsif rising_edge(cpu_clk) then
if (cpu_mreq_n = '0' and cpu_m1_n = '0') then
if (cpu_addr = x"0066") then
bootmode <= '1';
elsif cpu_addr(15) = '1' then
bootmode <= '0';
end if;
end if;
end if;
end process;
--------------------------------------------------------
-- synchronize interrupts etc into Z80 core
--------------------------------------------------------
sync_gen : process(cpu_clk, RSTn_sync)
begin
if RSTn_sync = '0' then
cpu_NMI_n_sync <= '1';
cpu_IRQ_n_sync <= '1';
elsif rising_edge(cpu_clk) then
if (cpu_clken = '1') then
cpu_NMI_n_sync <= cpu_NMI_n;
cpu_IRQ_n_sync <= cpu_IRQ_n;
end if;
end if;
end process;
--------------------------------------------------------
-- clock enable generator
--------------------------------------------------------
clk_gen : process(cpu_clk)
begin
if rising_edge(cpu_clk) then
cpu_clken <= not cpu_clken;
RSTn_sync <= RSTn;
end if;
end process;
end BEHAVIORAL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity LX9CoProSPI is
port (
-- GOP Signals
fastclk : in std_logic;
sw : in std_logic_vector(3 downto 0);
-- Tube signals
h_phi2 : in std_logic;
h_addr : in std_logic_vector(2 downto 0);
h_data : inout std_logic_vector(7 downto 0);
h_rdnw : in std_logic;
h_cs_b : in std_logic;
h_rst_b : in std_logic;
h_irq_b : inout std_logic;
-- Ram Signals
ram_ub_b : out std_logic;
ram_lb_b : out std_logic;
ram_cs : out std_logic;
ram_oe : out std_logic;
ram_wr : out std_logic;
ram_addr : out std_logic_vector (18 downto 0);
ram_data : inout std_logic_vector (7 downto 0);
-- SPI Slave
p_spi_ssel : in std_logic;
p_spi_sck : in std_logic;
p_spi_mosi : in std_logic;
p_spi_miso : out std_logic;
-- Interrupts/Control
p_irq_b : out std_logic;
p_nmi_b : out std_logic;
p_rst_b : out std_logic;
-- Test signals for debugging
p_test : out std_logic
);
end LX9CoProSPI;
architecture BEHAVIORAL of LX9CoProSPI is
signal h_data_in : std_logic_vector(7 downto 0);
signal h_data_out : std_logic_vector(7 downto 0);
signal spi_attached : std_logic := '0';
signal h_rst_b1 : std_logic;
signal h_rst_b2 : std_logic;
signal h_rst_b3 : std_logic;
signal h_phi2_b : std_logic;
begin
---------------------------------------------------------------------
-- instantiated components
---------------------------------------------------------------------
inst_ICAP_config : entity work.ICAP_config port map (
fastclk => fastclk,
sw_in => sw,
sw_out => open,
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b
);
h_phi2_b <= not h_phi2;
inst_CoProSPI : entity work.CoProSPI port map (
h_clk => h_phi2_b,
h_cs_b => h_cs_b,
h_rdnw => h_rdnw,
h_addr => h_addr,
h_data_in => h_data_in,
h_data_out => h_data_out,
h_rst_b => h_rst_b,
h_irq_b => h_irq_b,
-- Parasite Clock (32 MHz)
p_clk => fastclk,
-- SPI Slave
p_spi_ssel => p_spi_ssel,
p_spi_sck => p_spi_sck,
p_spi_mosi => p_spi_mosi,
p_spi_miso => p_spi_miso,
-- Interrupts/Control
p_irq_b => p_irq_b,
p_nmi_b => p_nmi_b,
p_rst_b => p_rst_b,
-- Test signals for debugging
test => open
);
h_data_in <= h_data;
h_data <= h_data_out when spi_attached = '1' and h_cs_b = '0' and h_rdnw = '1' and h_phi2 = '1' else
x"FE" when spi_attached = '0' and h_cs_b = '0' and h_rdnw = '1' and h_phi2 = '1' else
(others => 'Z');
--------------------------------------------------------
-- SPI / Null mode selection
--------------------------------------------------------
process(fastclk)
begin
if rising_edge(fastclk) then
h_rst_b1 <= h_rst_b;
h_rst_b2 <= h_rst_b1;
h_rst_b3 <= h_rst_b2;
if h_rst_b3 = '0' and h_rst_b2 = '1' then
spi_attached <= p_spi_ssel;
end if;
end if;
end process;
--------------------------------------------------------
-- external Ram unused
--------------------------------------------------------
ram_ub_b <= '1';
ram_lb_b <= '1';
ram_cs <= '1';
ram_oe <= '1';
ram_wr <= '1';
ram_addr <= (others => '1');
ram_data <= (others => '1');
--------------------------------------------------------
-- test signals
--------------------------------------------------------
p_test <= spi_attached;
end BEHAVIORAL;
|
---------------------------------------------------------------------------------
-- Title : ARP Packet TX
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : IPv4Tx.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Connects to Ethernet layer, sends IPv4 packets
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
entity IPv4Tx is
generic (
GATE_DELAY_G : time := 1 ns
);
port (
-- 125 MHz ethernet clock in
ethTxClk : in sl;
ethTxRst : in sl := '0';
-- Header data
ipPacketLength : in slv(15 downto 0);
ipPacketId : in slv(15 downto 0);
ipMoreFragments : in sl;
ipFragOffset : in slv(12 downto 0);
ipProtocol : in slv( 7 downto 0);
ipSrcAddr : in IpAddrType;
ipDstAddr : in IpAddrType;
-- User data to be sent
ipData : in slv(31 downto 0);
ipDataValid : in sl;
ipDataReady : out sl;
-- Interface to Ethernet frame block
ethTxDataIn : out slv(7 downto 0);
ethTxDataValid : out sl;
ethTxDataLastByte : out sl;
ethTxDataReady : in sl
);
end IPv4Tx;
architecture rtl of IPv4Tx is
type StateType is (IDLE_S, HEADER_PREP_0_S, HEADER_PREP_1_S,
HEADER_PREP_2_S, HEADER_PREP_3_S,
HEADER_0_S, HEADER_1_S, HEADER_2_S, HEADER_3_S, HEADER_4_S,
PAYLOAD_S, PAUSE_S);
type RegType is record
state : StateType;
byteCount : slv( 1 downto 0);
header0 : slv(31 downto 0);
header1 : slv(31 downto 0);
header2 : slv(31 downto 0);
header3 : slv(31 downto 0);
header4 : slv(31 downto 0);
header0Checksum : slv(31 downto 0);
header1Checksum : slv(31 downto 0);
header2Checksum : slv(31 downto 0);
header3Checksum : slv(31 downto 0);
header4Checksum : slv(31 downto 0);
ipCheckSum32 : slv(31 downto 0);
ipCheckSum16 : slv(15 downto 0);
wordsLeft : slv(13 downto 0);
data32 : slv(31 downto 0);
data8 : slv( 7 downto 0);
data8Valid : sl;
data8Last : sl;
ethTxDataIn : slv(7 downto 0);
ethTxDataValid : sl;
ethTxDataLast : sl;
ipDataReady : sl;
end record RegType;
constant REG_INIT_C : RegType := (
state => IDLE_S,
byteCount => (others => '1'),
header0 => (others => '0'),
header1 => (others => '0'),
header2 => (others => '0'),
header3 => (others => '0'),
header4 => (others => '0'),
header0Checksum => (others => '0'),
header1Checksum => (others => '0'),
header2Checksum => (others => '0'),
header3Checksum => (others => '0'),
header4Checksum => (others => '0'),
ipCheckSum32 => (others => '0'),
ipChecksum16 => (others => '0'),
wordsLeft => (others => '0'),
data32 => (others => '0'),
data8 => (others => '0'),
data8Valid => '0',
data8Last => '0',
ethTxDataIn => (others => '0'),
ethTxDataValid => '0',
ethTxDataLast => '0',
ipDataReady => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
----------------------------------
-- State machine to prep packet --
----------------------------------
comb : process(r,ethTxRst,ipPacketLength,ipPacketId,ipMoreFragments,
ipFragOffset,ipProtocol,ipSrcAddr,ipDstAddr,
ipData,ipDataValid,ethTxDataReady) is
variable v : RegType;
begin
v := r;
-- Set defaults / reset any pulsed signals
v.data8Valid := '0';
v.data8Last := '0';
v.ipDataReady := '0';
-- State machine
case(r.state) is
when IDLE_S =>
v.byteCount := (others => '1');
if ipDataValid = '1' then
-- Prepare header words
v.header0 := IPV4_VERSION_C & IPV4_IHL_C & IPV4_DSCP_C & IPV4_ECN_C & ipPacketLength;
v.header1 := ipPacketId & "00" & ipMoreFragments & ipFragOffset;
v.header2 := IPV4_TTL_C & ipProtocol & x"0000"; --Placeholder for checksum
v.header3 := ipSrcAddr(3) & ipSrcAddr(2) & ipSrcAddr(1) & ipSrcAddr(0);
v.header4 := ipDstAddr(3) & ipDstAddr(2) & ipDstAddr(1) & ipDstAddr(0);
-- Prepare initial checksum stages
v.header0Checksum := conv_std_logic_vector(conv_integer(v.header0(31 downto 16)) + conv_integer(v.header0(15 downto 0)),32);
v.header1Checksum := conv_std_logic_vector(conv_integer(v.header1(31 downto 16)) + conv_integer(v.header1(15 downto 0)),32);
v.header2Checksum := conv_std_logic_vector(conv_integer(v.header2(31 downto 16)) + conv_integer(v.header2(15 downto 0)),32);
v.header3Checksum := conv_std_logic_vector(conv_integer(v.header3(31 downto 16)) + conv_integer(v.header3(15 downto 0)),32);
v.header4Checksum := conv_std_logic_vector(conv_integer(v.header4(31 downto 16)) + conv_integer(v.header4(15 downto 0)),32);
-- Prep number of total payload words to read, not including header
v.wordsLeft := ipPacketLength(15 downto 2) - 5 - 1;
-- Move to next state
v.state := HEADER_PREP_0_S;
end if;
when HEADER_PREP_0_S =>
-- Partial addition of checksum
v.ipChecksum32 := r.header0Checksum + r.header1Checksum + r.header2Checksum;
v.state := HEADER_PREP_1_S;
-- Also go ahead and grab first word here and allow upstream block to clock to next word
v.data32 := ipData;
v.ipDataReady := '1';
when HEADER_PREP_1_S =>
-- Remaining addition of checksum
v.ipChecksum32 := r.ipChecksum32 + r.header3Checksum + r.header4Checksum;
v.state := HEADER_PREP_2_S;
when HEADER_PREP_2_S =>
-- Switch checksum to 16 bit version
v.ipChecksum16 := conv_std_logic_vector(conv_integer(r.ipChecksum32(15 downto 0)) + conv_integer(r.ipChecksum32(31 downto 16)),16);
v.state := HEADER_PREP_3_S;
when HEADER_PREP_3_S =>
-- Bit flip of the checksum and place it into header
v.header2(15 downto 0) := not(r.ipChecksum16);
-- Move into actual data
v.data8 := getByte(conv_integer(r.byteCount),r.header0);
v.data8Valid := '1';
v.state := HEADER_0_S;
when HEADER_0_S =>
v.data8Valid := '1';
if ethTxDataReady = '1' and r.data8Valid = '1' then
v.byteCount := r.byteCount - 1;
v.data8 := getByte(conv_integer(v.byteCount),r.header0);
if v.byteCount = 0 then
v.state := HEADER_1_S;
end if;
end if;
when HEADER_1_S =>
v.data8Valid := '1';
if ethTxDataReady = '1' and r.data8Valid = '1' then
v.byteCount := r.byteCount - 1;
v.data8 := getByte(conv_integer(v.byteCount),r.header1);
if v.byteCount = 0 then
v.state := HEADER_2_S;
end if;
end if;
when HEADER_2_S =>
v.data8Valid := '1';
if ethTxDataReady = '1' and r.data8Valid = '1' then
v.byteCount := r.byteCount - 1;
v.data8 := getByte(conv_integer(v.byteCount),r.header2);
if v.byteCount = 0 then
v.state := HEADER_3_S;
end if;
end if;
when HEADER_3_S =>
v.data8Valid := '1';
if ethTxDataReady = '1' and r.data8Valid = '1' then
v.byteCount := r.byteCount - 1;
v.data8 := getByte(conv_integer(v.byteCount),r.header3);
if v.byteCount = 0 then
v.state := HEADER_4_S;
end if;
end if;
when HEADER_4_S =>
v.data8Valid := '1';
if ethTxDataReady = '1' and r.data8Valid = '1' then
v.byteCount := r.byteCount - 1;
v.data8 := getByte(conv_integer(v.byteCount),r.header4);
if v.byteCount = 0 then
v.state := PAYLOAD_S;
end if;
end if;
when PAYLOAD_S =>
v.data8Valid := '1';
if ethTxDataReady = '1' and r.data8Valid = '1' then
v.byteCount := r.byteCount - 1;
v.data8 := getByte(conv_integer(v.byteCount),r.data32);
if r.byteCount = 1 and r.wordsLeft /= 0 then
v.ipDataReady := '1';
end if;
if v.byteCount = 0 then
v.data32 := ipData;
if r.wordsLeft = 0 then
v.data8Last := '1';
v.state := PAUSE_S;
else
v.wordsLeft := r.wordsLeft - 1;
end if;
end if;
end if;
when PAUSE_S =>
v.data8Valid := '1';
v.data8Last := '1';
if ethTxDataReady = '1' and r.data8Valid = '1' then
v.data8Valid := '0';
v.data8Last := '0';
v.state := IDLE_S;
end if;
-- -- Hold one extra cycle here to let the transfer finish
-- if r.data8Last = '0' then
-- v.state := IDLE_S;
-- end if;
when others =>
v.state := IDLE_S;
end case;
-- Reset logic
if (ethTxRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
ethTxDataIn <= r.data8;
ethTxDataValid <= r.data8Valid;
ethTxDataLastByte <= r.data8Last;
ipDataReady <= r.ipDataReady;
-- Assign variable to signal
rin <= v;
end process;
seq : process (ethTxClk) is
begin
if (rising_edge(ethTxClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
|
-- ----------------------------------------------------------------
-- adder_tree.vhd
--
-- 4/28/2011 D. W. Hawkins ([email protected])
--
-- Adder tree.
--
-- This component calculates the pipelined sum of parallel input
-- arguments and generates a single output. The sums are
-- implemented in pairs. The width of the sums increases 1-bit
-- per layer. The number of sum layers is ceil(log2(NINPUTS)),
-- where NINPUTS is the number of inputs.
--
-- The sum pipeline pads the number of sums at the input to the
-- next power of two; synthesis removes unused logic. The sum
-- indexing for an 8 input example is;
--
-- sum(0) --|\ sum(8)
-- |+|--------|\
-- sum(1) --|/ | | sum(12)
-- |+|---------|\
-- sum(2) --|\ sum(9) | | | |
-- |+|--------|/ | |
-- sum(3) --|/ | | sum(14)
-- |+|---------
-- sum(4) --|\ sum(10) | |
-- |+|--------|\ | |
-- sum(5) --|/ | | sum(13) | |
-- |+|---------|/
-- sum(6) --|\ sum(11)| |
-- |+|--------|/
-- sum(7) --|/
--
-- The width of the full-precision output can be reduce by
-- rounding using the unbiased 'convergent' rounding component.
--
-- The parallel inputs are signed values packed into a wide
-- std_logic_vector.
--
-- ----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-- ----------------------------------------------------------------
entity adder_tree is
generic (
-- Number of inputs
NINPUTS : integer;
-- Input data width
IWIDTH : integer;
-- Output data width
-- * full-precision requires that
-- OWIDTH = IWIDTH + ceil(log2(NINPUTS))
OWIDTH : integer
);
port (
-- Reset and clock
rstN : in std_logic;
clk : in std_logic;
-- Input data
-- * NINPUTS x signed(IWIDTH-1 downto 0)
d : in std_logic_vector(NINPUTS*IWIDTH-1 downto 0);
-- Output data
q : out signed(OWIDTH-1 downto 0)
);
end entity;
-- ----------------------------------------------------------------
architecture mixed of adder_tree is
-- ------------------------------------------------------------
-- Local functions
-- ------------------------------------------------------------
--
-- Input lookup and signed conversion
impure function din(i : integer) return signed is
begin
return signed(d((i+1)*IWIDTH-1 downto i*IWIDTH));
end function;
-- ------------------------------------------------------------
-- Constants
-- ------------------------------------------------------------
--
-- Number of stages required to sum the inputs
constant NSTAGES : integer :=
integer(ceil(log2(real(NINPUTS))));
-- Number of inputs padded to next power-of-2
-- * the width of the first stage of sums
constant PWIDTH : integer := 2**NSTAGES;
-- The total number of sums in the pipeline
constant NSUMS : integer := PWIDTH-1;
-- The width of the last sum (used for all sums)
constant SWIDTH : integer :=
IWIDTH + NSTAGES;
-- ------------------------------------------------------------
-- Signals
-- ------------------------------------------------------------
--
-- Sum pipeline
type sum_t is array (0 to NSUMS-1) of
signed(SWIDTH-1 downto 0);
signal sum : sum_t;
begin
-- ------------------------------------------------------------
-- Pipelined adders
-- ------------------------------------------------------------
--
process(clk,rstN)
variable prev_index : integer;
variable curr_index : integer;
variable num_sums : integer;
begin
if (rstN = '0') then
sum <= (others => (others => '0'));
elsif rising_edge(clk) then
-- First stage; pairs of input sums
-- * unused power-of-2 padding is left at the
-- reset value of zero.
num_sums := PWIDTH/2;
for j in 0 to num_sums-1 loop
if (2*j+1 < NINPUTS) then
-- Resize and then sum (to avoid overflow)
sum(j) <=
resize(din(2*j), SWIDTH) +
resize(din(2*j+1), SWIDTH);
elsif (2*j < NINPUTS) then
sum(j) <= resize(din(2*j), SWIDTH);
end if;
end loop;
-- Subsequent stages; sums of previous sums
prev_index := 0;
curr_index := num_sums;
num_sums := num_sums/2;
for i in 1 to NSTAGES-1 loop
for j in 0 to num_sums-1 loop
sum(curr_index + j) <=
sum(prev_index + 2*j) +
sum(prev_index + 2*j + 1);
end loop;
prev_index := curr_index;
curr_index := curr_index + num_sums;
num_sums := num_sums/2;
end loop;
end if;
end process;
-- ------------------------------------------------------------
-- Full-precision output sum
-- ------------------------------------------------------------
--
q <= sum(NSUMS-1)(OWIDTH-1 downto 0);
end architecture; |
----------------------------------------------------------------------
--- A synchronous memory
----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
entity memory256x8 is
port (
ck : in std_logic;
we : in std_logic; -- write enable
address : in std_logic_vector(7 downto 0);
datain : in std_logic_vector(7 downto 0);
dataout : out std_logic_vector(7 downto 0)
);
end entity memory256x8;
architecture rtl of memory256x8 is
type ram_array is array (0 to 255) of std_logic_vector(7 downto 0);
-- this ram has its first two bytes initialized, you may add more
signal ram : ram_array := (
x"20", x"21", x"22", x"23", x"24", x"7F", x"01",
others => x"00");
begin
ram_process: process(ck) is
begin
if rising_edge(ck) then
-- note that the two following statements are sequential
if we = '1' then -- write enable
ram(to_integer(unsigned(address))) <= datain;
end if;
dataout <= ram(to_integer(unsigned(address)));
end if;
end process ram_process;
end architecture rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY tb_sqrt IS
END tb_sqrt;
ARCHITECTURE sqrt_arch OF tb_sqrt IS
-- constants
-- signals
SIGNAL btn : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL hex0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL hex1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL hex2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL hex3 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL led : STD_LOGIC_VECTOR(9 DOWNTO 0);
--SIGNAL pulse : STD_LOGIC;
SIGNAL sw : STD_LOGIC_VECTOR(9 DOWNTO 0);
COMPONENT sqrt
PORT (
btn : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
hex0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
hex1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
hex2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
hex3 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
led : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
--pulse : IN STD_LOGIC;
sw : IN STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
BEGIN
i1 : sqrt
PORT MAP (
-- list connections between master ports and signals
btn => btn,
hex0 => hex0,
hex1 => hex1,
hex2 => hex2,
hex3 => hex3,
led => led,
--pulse => pulse,
sw => sw
);
init : PROCESS
-- variable declarations
BEGIN
-- code that executes only once
WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
-- code executes for every event on sensitivity list
-- wait for about 3 ms;
-- ans = sqrt("c350") = X"df.9b" (preset)
-- hex[0, 1, 2, 3] = [83, 98, 0e, a1]
btn <= "111";
sw <= "0000000000";
wait for 1 ms;
-- ans = sqrt(X"fe00") = X"fe.ff"
-- hex[0, 1, 2, 3] = [8e, 8e, 06, 8e]
btn <= "110"; -- set sw <= X"00", pushing btn(0)
sw(7 downto 0) <= X"00";
wait for 50 ns;
btn <= "101"; -- set sw <= X"fe", pushing btn(1)
sw(7 downto 0) <= X"fe";
wait for 1 us;
btn <= "011"; -- push btn(2), and wait for finishing program
wait for 1 ms;
-- ans = sqrt(X"c350") = X"df.9b"
-- hex[0, 1, 2, 3] = [83, 98, 0e, a1]
btn <= "110"; -- set sw <= X"50", pushing btn(0)
sw(7 downto 0) <= X"50";
wait for 50 ns;
btn <= "101"; -- set sw <= X"c3", pushing btn(1)
sw(7 downto 0) <= X"c3";
wait for 1 us;
btn <= "011"; -- push btn(2), and wait for finishing program
wait for 1 ms;
WAIT;
END PROCESS always;
END sqrt_arch;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: delayLineBRAM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : READ_FIRST
-- C_WRITE_WIDTH_A : 17
-- C_READ_WIDTH_A : 17
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 17
-- C_READ_WIDTH_B : 17
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY delayLineBRAM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END delayLineBRAM_prod;
ARCHITECTURE xilinx OF delayLineBRAM_prod IS
COMPONENT delayLineBRAM_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : delayLineBRAM_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: delayLineBRAM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : READ_FIRST
-- C_WRITE_WIDTH_A : 17
-- C_READ_WIDTH_A : 17
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 17
-- C_READ_WIDTH_B : 17
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY delayLineBRAM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END delayLineBRAM_prod;
ARCHITECTURE xilinx OF delayLineBRAM_prod IS
COMPONENT delayLineBRAM_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : delayLineBRAM_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdctrl
-- File: sdctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: 64-bit SDRAM memory controller.
-- Supports HSIZE_DWORD AMBA accesses when connected to
-- AHB data bus wider than 32 bits.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity sdctrl64 is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of sdctrl64 is
constant WPROTEN : boolean := wprot = 1;
constant SDINVCLK : boolean := invclk = 1;
constant REVISION : integer := 0;
constant PM_PD : std_logic_vector(2 downto 0) := "001";
constant PM_SR : std_logic_vector(2 downto 0) := "010";
constant PM_DPD : std_logic_vector(2 downto 0) := "101";
constant std_rammask: Std_Logic_Vector(31 downto 20) :=
Conv_Std_Logic_Vector(hmask, 12);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SDCTRL64, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4, wr5, sidle,
sref, pd, dpd);
type icycletype is (iidle, pre, ref, lmode, emode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
cke : std_ulogic; -- Clock enable
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
nbdrive : std_ulogic;
burst : std_ulogic;
wprothit : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(63 downto 0);
hwdata : std_logic_vector(63 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(3 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(3 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
address : std_logic_vector(16 downto 1); -- memory address
idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
pwron : std_ulogic;
end record;
signal r, ri : reg_type;
signal rbdrive, ribdrive : std_logic_vector(63 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
ctrl : process(rst, ahbsi, r, sdi, rbdrive)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec0 : std_ulogic;
variable adec1 : std_ulogic;
variable rams : std_logic_vector(3 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable dout : std_logic_vector(63 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(63 downto 0);
variable bdrive : std_ulogic;
variable lline : std_logic_vector(2 downto 0);
variable haddr_tmp : std_logic_vector(31 downto 0);
variable arefresh : std_logic;
variable hwdata : std_logic_vector(63 downto 0);
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive; arefresh := '0';
-- lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
lline := '1' & not r.cfg.casdel & '1';
v.hrdata(63 downto 0) := sdi.data(63 downto 0);
-- Select input data depending on AHB DW and AMBA data mux settings
if AHBDW = 32 then
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
else
hwdata := ahbreaddword(ahbsi.hwdata, r.haddr(4 downto 2));
end if;
v.hwdata := hwdata;
-- AHB access
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := v.hio;
end if;
v.haddr := ahbsi.haddr;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
v.haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr;
htrans := r.htrans; hwrite := r.hwrite;
else
haddr := ahbsi.haddr;
htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if fast = 1 then haddr := r.haddr; end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- main state
case r.size is
when "00" =>
case r.haddr(2 downto 0) is
when "000" => dqm := "01111111";
when "001" => dqm := "10111111";
when "010" => dqm := "11011111";
when "011" => dqm := "11101111";
when "100" => dqm := "11110111";
when "101" => dqm := "11111011";
when "110" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
case r.haddr(2 downto 1) is
when "00" => dqm := "00111111";
when "01" => dqm := "11001111";
when "10" => dqm := "11110011";
when others => dqm := "11111100";
end case;
when "10" =>
if r.hwrite = '0' then dqm := "00000000";
elsif r.haddr(2) = '0' then dqm := "00001111";
else dqm := "11110000"; end if;
when others => dqm := "00000000";
end case;
-- main FSM
case r.mstate is
when midle =>
if ((v.hsel and htrans(1) and not v.hio) = '1') then
if (r.sdstate = sidle) and (r.cfg.command = "000")
and (r.cmstate = midle) and (v.hio = '0')
then
if fast = 0 then startsd := '1'; else v.startsd := '1'; end if;
v.mstate := active;
elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
and (r.cfg.command = "000") and (r.cmstate = midle) and (v.hio = '0')
then
v.startsd := '1';
if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
v.hresp := HRESP_ERROR;
else
v.mstate := active;
end if;
end if;
end if;
when others => null;
end case;
startsd := startsd or r.startsd;
-- generate row and column address size
case r.cfg.csize is
when "00" => raddr := haddr(23 downto 11);
when "01" => raddr := haddr(24 downto 12);
when "10" => raddr := haddr(25 downto 13);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(27 downto 15);
else raddr := haddr(26 downto 14); end if;
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 21)) &
genmux(r.cfg.bsize, haddr(28 downto 20));
-- generate chip select
adec0 := genmux(r.cfg.bsize, haddr(29 downto 22));
adec1 := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := (adec1 and adec0) & (adec1 and not adec0) & (not adec1 and adec0) & (not adec1 and not adec0);
-- sdram access FSM
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
v.address(16 downto 1) := ba & raddr & '0';
v.sdcsn := not rams(3 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
case r.cfg.pmode is
when PM_SR =>
v.cfg.cke := '0'; v.sdstate := sref;
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
when PM_DPD =>
v.cfg.cke := '0'; v.sdstate := dpd;
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
when others =>
end case;
end if;
when act1 =>
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
end if;
if WPROTEN then
v.wprothit := sdi.wprot;
if sdi.wprot = '1' then v.hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
v.address(14 downto 1) := r.haddr(14 downto 13) & '0' & r.haddr(12 downto 2);
v.dqm := dqm; v.burst := r.hready;
if r.hwrite = '1' then
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0';
if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '1';
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '1'; v.casn := '1';
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.dqm := dqm;
v.address(14 downto 2) := r.haddr(14 downto 13) & '0' & r.haddr(12 downto 3);
if ((((r.burst and r.hready) = '1') and (r.htrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))) then
v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready;
if ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (r.trfc(2 downto 1) = "00") then
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
end if;
when wr3 =>
if (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "1111"; v.rasn := '1'; v.sdwen := '1'; v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when wr4 =>
v.sdcsn := "1111"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
when wr5 =>
v.sdstate := sidle; v.idlecnt := (others => '1');
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if (ahbsi.htrans = "11") then
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
when rd7 =>
v.casn := '1';
if r.cfg.casdel = '1' then
v.sdstate := rd2;
if (ahbsi.htrans = "11") then
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
else
v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
else
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
else
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "1111"; v.dqm := (others => '1');
else
if (ahbsi.htrans = "11") then
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (ahbsi.htrans /= "11") or (r.sdcsn = "1111") or
((r.haddr(5 downto 2) = ("111" & not r.size(0))) and (r.cfg.command = "100")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "1111") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
else
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when sref =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
if r.trfc = "0000" then -- Minimum duration (= tRAS)
v.cfg.cke := '1';
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
end if;
if r.cfg.cke = '1' then
if (r.idlecnt = "0000") then -- tXSR ns with NOP
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.sref_tmpcom := r.cfg.command;
v.cfg.command := "100";
end if;
else
v.idlecnt := r.cfg.txsr;
end if;
end if;
when pd =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
v.cfg.cke := '1';
v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when dpd =>
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
v.cfg.renable := '0';
if (startsd = '1' and r.hio = '0') then
v.hready := '1'; -- ack all accesses with Error response
v.startsd := '0';
v.hresp := HRESP_ERROR;
elsif r.cfg.pmode /= PM_DPD then
v.cfg.cke := '1';
if r.cfg.cke = '1' then
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.cfg.renable := '1';
end if;
end if;
when others =>
v.sdstate := sidle; v.idlecnt := (others => '1');
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "010" => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when "100" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "110" => -- Lodad Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0000";
when "111" => -- Load Ext-Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
& r.cfg.pasr(2 downto 0);
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; --v.cfg.command := "000";
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
when leadout =>
if r.trfc = "0000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
v.cfg.cke := '1';
if (r.cfg.renable = '1' or (pwron /= 0 and r.pwron = '1')) and r.cfg.cke = '1' then
v.cfg.command := "010"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.mobileen = "11" then
v.cfg.command := "111"; v.istate := emode;
else
v.istate := finish;
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := finish;
end if;
when others =>
if pwron /= 0 then v.pwron := '0'; end if;
if r.cfg.renable = '0' and r.sdstate /= dpd then
v.istate := iidle;
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
-- pragma translate_off
if not is_x(r.cfg.refresh) then
-- pragma translate_on
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "100";
arefresh := '1';
end if;
end if;
-- pragma translate_off
end if;
-- pragma translate_on
-- AHB register access
if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then
if r.haddr(3 downto 2) = "00" then
v.cfg.command := hwdata(20 downto 18);
v.cfg.csize := hwdata(22 downto 21);
v.cfg.bsize := hwdata(25 downto 23);
v.cfg.casdel := hwdata(26);
v.cfg.trfc := hwdata(29 downto 27);
v.cfg.trp := hwdata(30);
v.cfg.renable := hwdata(31);
v.cfg.refresh := hwdata(14 downto 0);
v.refresh := (others => '0');
elsif r.haddr(3 downto 2) = "01" then
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := hwdata(31); end if;
if r.cfg.pmode = "000" then
v.cfg.cke := hwdata(30);
end if;
if r.cfg.mobileen(1) = '1' then
v.cfg.txsr := hwdata(23 downto 20);
v.cfg.pmode := hwdata(18 downto 16);
v.cfg.ds(3 downto 2) := hwdata( 6 downto 5);
v.cfg.tcsr(3 downto 2) := hwdata( 4 downto 3);
v.cfg.pasr(5 downto 3) := hwdata( 2 downto 0);
end if;
end if;
end if;
-- Disable CS and DPD when Mobile SDR is Disabled
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
-- Update EMR when ds, tcsr or pasr change
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
end if;
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
end if;
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
end if;
end if;
regsd := (others => '0');
if r.haddr(3 downto 2) = "00" then
regsd(31 downto 18) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
regsd(16) := r.cfg.mobileen(1);
regsd(15) := '1'; -- 64-bit support
regsd(14 downto 0) := r.cfg.refresh;
elsif r.haddr(3 downto 2) = "01" then
regsd(31) := r.cfg.mobileen(0);
regsd(30) := r.cfg.cke;
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
end if;
if (r.hsel and r.hio) = '1' then dout := regsd & regsd;
else
dout := r.hrdata;
-- Possibly duplicate data for reads < HSIZE_DWORD since the system may
-- not be fully AMBA compliant and other cores may expect that the valid
-- WORD is present on 31:0 of AMBA HRDATA.
if andv(r.size) /= '1' and r.haddr(2) = '0' then
dout(31 downto 0) := r.hrdata(63 downto 32);
if r.hready = '1' then v.hrdata := r.hrdata; end if;
end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "000";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
v.cfg.renable := '0';
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.startsd := '0';
if pwron /= 0 then v.pwron := '1'; end if;
if mobile >= 2 then v.cfg.mobileen := "11";
elsif mobile = 1 then v.cfg.mobileen := "10";
else v.cfg.mobileen := "00"; end if;
v.cfg.txsr := (others => '1');
v.cfg.pmode := (others => '0');
v.cfg.ds := (others => '0');
v.cfg.tcsr := (others => '0');
v.cfg.pasr := (others => '0');
if mobile >= 2 then v.cfg.cke := '0';
else v.cfg.cke := '1'; end if;
v.sref_tmpcom := "000";
v.idlecnt := (others => '1');
v.hio := '0';
end if;
if pwron = 0 then v.pwron := '0'; end if;
if not WPROTEN then v.wprothit := '0'; end if;
ri <= v;
ribdrive <= vbdrive;
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(dout);
end process;
--sdo.sdcke <= (others => '1');
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
sdo.cb <= (others => '0'); sdo.ba <= (others => '0');
sdo.cal_en <= (others => '0'); sdo.sdck <= (others => '0');
sdo.cal_pll <= (others => '0'); sdo.cal_inc <= (others => '0');
sdo.conf <= (others => '0'); sdo.odt <= (others => '0');
sdo.oct <= '0';
sdo.qdrive <= '0';
sdo.ce <= '0';
sdo.moben <= '0';
sdo.cal_rst <= '0';
sdo.vcbdrive <= (others => '0');
sdo.cbdqm <= (others => '0');
sdo.cbcal_en <= (others => '0');
sdo.cbcal_inc <= (others => '0');
sdo.read_pend <= (others => '0');
sdo.regwdata <= (others => '0');
sdo.regwrite <= (others => '0');
sdo.dqs_gate <= '0';
sdo.nbdrive <= '0';
regs : process(clk, rst) begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive;
if rst = '0' then r.icnt <= (others => '0'); end if;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
end if;
end process;
rgen : if not SDINVCLK generate
sdo.address <= r.address(16 downto 2);
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= r.sdcsn(1 downto 0);
sdo.xsdcsn <= "1111" & r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
sdo.data <= zero64 & r.hwdata;
end generate;
ngen : if SDINVCLK generate
nregs : process(clk, rst) begin
if falling_edge(clk) then
sdo.address <= r.address(16 downto 2);
if oepol = 1 then sdo.bdrive <= r.nbdrive;
else sdo.bdrive <= r.bdrive; end if;
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= r.sdcsn(1 downto 0);
sdo.xsdcsn <= "1111" & r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
sdo.data(63 downto 0) <= r.hwdata;
end if;
if rst = '0' then sdo.sdcsn <= (others => '1'); end if;
end process;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("sdctrl64" & tost(hindex) &
": 64-bit PC133 SDRAM controller rev " & tost(REVISION));
-- pragma translate_on
end;
|
----------------------------------------------------------------------------------------------------
--
-- FileName: DRAM.vhd
-- Description: MainBoard DRAM Controller CPLD Top Level.
--
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY DRAMController IS
PORT
(
Clk : IN STD_LOGIC; -- Clock
nReset : IN STD_LOGIC; -- Reset
Address : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- Address Bus
nAS : IN STD_LOGIC; -- CPU Address signal
nSIZ0 : IN STD_LOGIC; -- CPU SIZ 0 signal
nSIZ1 : IN STD_LOGIC; -- CPU SIZ 1 signal
Func : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- CPU Function Signals
nWR : IN STD_LOGIC; -- CPU Read/Write signal
nCS_ROM : IN STD_LOGIC; -- ROM Chip Select
nDSACK0_OUT : OUT STD_LOGIC; -- CPU DSACK 0 signal
nDSACK1_OUT : OUT STD_LOGIC; -- CPU DSACK 1 signal
MA : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); -- Multiplexed Address Bus
nRAS_DRAM : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- Row Address Select
nCAS_DRAM : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- Column Address Select
nWE_DRAM : OUT STD_LOGIC -- DRAM Read/Write signal
);
END DRAMController;
ARCHITECTURE Behavioral OF DRAMController IS
-- Component Declaration for the State Machine
COMPONENT StateMachine
PORT (
Clk : IN STD_LOGIC; -- Clock
nReset : IN STD_LOGIC; -- Reset
nWR : IN STD_LOGIC; -- CPU Read/Write signal
nCS_DRAM : IN STD_LOGIC; -- DRAM Chip Select
nPage_Hit : IN STD_LOGIC; -- Request is in Same Page
nBank : IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- DRAM Bank to Address
nByte : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- Byte/s Selected
nPreCharge : OUT STD_LOGIC; -- Flag to show when in PreCharge
nDSACK0 : OUT STD_LOGIC; -- Data size/ack signal 0 to CPU
nDSACK1 : OUT STD_LOGIC; -- Data size/ack signal 1 to CPU
nRAS : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- Row Address Select
nCAS : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- Column Address Select
nWE_DRAM : OUT STD_LOGIC -- DRAM Read/Write signal
);
END COMPONENT;
-- Component Declaration for the Decoder
COMPONENT Decoder
PORT (
nReset : IN STD_LOGIC; -- Reset
nAS : IN STD_LOGIC; -- CPU Address signal
nSIZ0 : IN STD_LOGIC; -- CPU SIZ 0 signal
nSIZ1 : IN STD_LOGIC; -- CPU SIZ 1 signal
nPreCharge : IN STD_LOGIC; -- Flag to show when in PreCharge
Func : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- CPU Function Signals
Address : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- Address Bus
nCS_ROM : IN STD_LOGIC; -- ROM Chip Select
nBank : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- DRAM Bank to Address
nByte : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- Byte/s Selected
nCS_DRAM : OUT STD_LOGIC; -- DRAM Chip Select
nPage_Hit : OUT STD_LOGIC -- Request is in Same Page
);
END COMPONENT;
-- Component Declaration for the Multiplexer
COMPONENT Multiplexer
PORT (
Address : IN STD_LOGIC_VECTOR (23 DOWNTO 0); -- Address Bus
nRAS : IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- Row Address Select
MA : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) -- Multiplexed Address Bus
);
END COMPONENT;
-- Define internal signals.
SIGNAL nCS_DRAM : STD_LOGIC;
SIGNAL nPage_Hit : STD_LOGIC;
SIGNAL nPreCharge : STD_LOGIC;
SIGNAL nBank : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL nByte : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL nRAS : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL nDSACK0 : STD_LOGIC;
SIGNAL nDSACK1 : STD_LOGIC;
BEGIN
-- Instantiate the State Machine
State_Machine : StateMachine PORT MAP (
Clk => Clk,
nReset => nReset,
nWR => nWR,
nCS_DRAM => nCS_DRAM,
nPage_Hit => nPage_Hit,
nBank => nBank,
nByte => nByte,
nPreCharge => nPreCharge,
nDSACK0 => nDSACK0,
nDSACK1 => nDSACK1,
nRAS => nRAS,
nCAS => nCAS_DRAM,
nWE_DRAM => nWE_DRAM
);
-- Instantiate the Decoder
Address_Decoder : Decoder PORT MAP (
nReset => nReset,
nAS => nAS,
nSIZ0 => nSIZ0,
nSIZ1 => nSIZ1,
nPreCharge => nPreCharge,
Func => Func,
Address => Address,
nCS_ROM => nCS_ROM,
nBank => nBank,
nByte => nByte,
nCS_DRAM => nCS_DRAM,
nPage_Hit => nPage_Hit
);
-- Instantiate the Multiplexer
Address_Multiplexer : Multiplexer PORT MAP (
Address(23 DOWNTO 0) => Address(25 DOWNTO 2),
nRAS => nRAS,
MA => MA
);
-- Connect signals that also tie to external ports to those ports
nRAS_DRAM <= nRAS;
nDSACK0_OUT <= '0' WHEN nDSACK0 = '0' ELSE 'Z';
nDSACK1_OUT <= '0' WHEN nDSACK1 = '0' ELSE 'Z';
END Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity fsm_163 is
port (
clock : in std_logic;
reset : in std_logic;
out91 : out std_logic;
out92 : out std_logic;
out93 : out std_logic;
in7 : in std_logic;
out94 : out std_logic;
out95 : out std_logic;
out98 : out std_logic;
out100 : out std_logic;
out101 : out std_logic;
out102 : out std_logic;
out104 : out std_logic;
out105 : out std_logic;
out106 : out std_logic;
out107 : out std_logic;
out108 : out std_logic;
out109 : out std_logic;
out111 : out std_logic;
out114 : out std_logic;
out116 : out std_logic;
out118 : out std_logic;
out119 : out std_logic;
out120 : out std_logic;
out128 : out std_logic;
out130 : out std_logic;
out131 : out std_logic;
out132 : out std_logic;
out137 : out std_logic;
in8 : in std_logic;
out152 : out std_logic;
out155 : out std_logic;
out156 : out std_logic;
out31 : out std_logic;
in2 : in std_logic;
out28 : out std_logic;
out29 : out std_logic;
out30 : out std_logic;
out26 : out std_logic;
out27 : out std_logic;
out24 : out std_logic;
out25 : out std_logic;
out77 : out std_logic;
out79 : out std_logic;
out80 : out std_logic;
out82 : out std_logic;
out34 : out std_logic;
out35 : out std_logic;
out36 : out std_logic;
out32 : out std_logic;
out33 : out std_logic;
out40 : out std_logic;
out41 : out std_logic;
out88 : out std_logic;
out89 : out std_logic;
out21 : out std_logic;
out22 : out std_logic;
out23 : out std_logic;
out73 : out std_logic;
out76 : out std_logic;
in6 : in std_logic;
out70 : out std_logic;
out12 : out std_logic;
out13 : out std_logic;
out14 : out std_logic;
out17 : out std_logic;
out18 : out std_logic;
out19 : out std_logic;
out20 : out std_logic;
out9 : out std_logic;
out11 : out std_logic;
out8 : out std_logic;
out2 : out std_logic;
out4 : out std_logic;
out5 : out std_logic;
in1 : in std_logic;
out6 : out std_logic;
out7 : out std_logic;
out0 : out std_logic;
out1 : out std_logic;
out37 : out std_logic;
out38 : out std_logic;
out39 : out std_logic;
out1222 : out std_logic;
out1223 : out std_logic;
out1224 : out std_logic;
out1225 : out std_logic;
out1226 : out std_logic;
out1228 : out std_logic;
out1230 : out std_logic;
in0 : in std_logic;
out67 : out std_logic;
out68 : out std_logic;
out65 : out std_logic;
out66 : out std_logic;
in5 : in std_logic;
out62 : out std_logic;
out58 : out std_logic;
out56 : out std_logic;
in4 : in std_logic;
out57 : out std_logic;
out54 : out std_logic;
out55 : out std_logic;
out51 : out std_logic;
out52 : out std_logic;
out53 : out std_logic;
in3 : in std_logic;
out46 : out std_logic;
out47 : out std_logic;
out48 : out std_logic;
out49 : out std_logic;
out50 : out std_logic;
out42 : out std_logic;
out43 : out std_logic;
out44 : out std_logic;
out45 : out std_logic;
in9 : in std_logic;
in10 : in std_logic;
out171 : out std_logic;
in11 : in std_logic;
out191 : out std_logic;
out207 : out std_logic;
out208 : out std_logic;
out209 : out std_logic;
out212 : out std_logic;
out213 : out std_logic;
out216 : out std_logic;
out220 : out std_logic;
out221 : out std_logic;
out223 : out std_logic;
out224 : out std_logic;
out226 : out std_logic;
out227 : out std_logic;
out228 : out std_logic;
out229 : out std_logic;
out230 : out std_logic;
out233 : out std_logic;
out235 : out std_logic;
out236 : out std_logic;
out237 : out std_logic;
out238 : out std_logic;
out239 : out std_logic;
out241 : out std_logic;
out250 : out std_logic;
out258 : out std_logic;
out259 : out std_logic;
out261 : out std_logic;
out270 : out std_logic;
out276 : out std_logic;
out277 : out std_logic;
out283 : out std_logic;
out285 : out std_logic;
out287 : out std_logic;
out290 : out std_logic;
out291 : out std_logic;
out293 : out std_logic;
out301 : out std_logic;
out303 : out std_logic;
out304 : out std_logic;
out315 : out std_logic;
out319 : out std_logic;
out321 : out std_logic;
out330 : out std_logic;
out335 : out std_logic;
out338 : out std_logic;
out341 : out std_logic;
out342 : out std_logic;
out344 : out std_logic;
out347 : out std_logic;
out351 : out std_logic;
out354 : out std_logic;
out355 : out std_logic;
out356 : out std_logic;
out357 : out std_logic;
out358 : out std_logic;
out360 : out std_logic;
out361 : out std_logic;
out362 : out std_logic;
out365 : out std_logic;
out367 : out std_logic;
out368 : out std_logic;
out370 : out std_logic;
out375 : out std_logic;
out376 : out std_logic;
out378 : out std_logic;
out381 : out std_logic;
out382 : out std_logic;
out386 : out std_logic;
out387 : out std_logic;
out388 : out std_logic;
out390 : out std_logic;
out392 : out std_logic;
out393 : out std_logic;
out394 : out std_logic;
out397 : out std_logic;
out403 : out std_logic;
out404 : out std_logic;
out408 : out std_logic;
out409 : out std_logic;
out410 : out std_logic;
out412 : out std_logic;
out416 : out std_logic;
out417 : out std_logic;
out418 : out std_logic;
out419 : out std_logic;
out420 : out std_logic;
out421 : out std_logic;
out424 : out std_logic;
out425 : out std_logic;
out430 : out std_logic;
out431 : out std_logic;
out434 : out std_logic;
out436 : out std_logic;
out438 : out std_logic;
out439 : out std_logic;
out440 : out std_logic;
out441 : out std_logic;
out442 : out std_logic;
out443 : out std_logic;
out444 : out std_logic;
out445 : out std_logic;
out446 : out std_logic;
out447 : out std_logic;
out448 : out std_logic;
out450 : out std_logic;
out451 : out std_logic;
out454 : out std_logic;
out457 : out std_logic;
out460 : out std_logic;
out463 : out std_logic;
out465 : out std_logic;
out466 : out std_logic;
out472 : out std_logic;
out473 : out std_logic;
out475 : out std_logic;
out476 : out std_logic;
out479 : out std_logic;
out480 : out std_logic;
out481 : out std_logic;
out482 : out std_logic;
out484 : out std_logic;
out485 : out std_logic;
out489 : out std_logic;
out491 : out std_logic;
out494 : out std_logic;
out497 : out std_logic;
out500 : out std_logic;
out503 : out std_logic;
out504 : out std_logic;
out505 : out std_logic;
out508 : out std_logic;
out509 : out std_logic;
out513 : out std_logic;
out514 : out std_logic;
out516 : out std_logic;
out521 : out std_logic;
out523 : out std_logic;
out524 : out std_logic;
out525 : out std_logic;
out530 : out std_logic;
out532 : out std_logic;
out533 : out std_logic;
out535 : out std_logic;
out536 : out std_logic;
out539 : out std_logic;
out541 : out std_logic;
out543 : out std_logic;
out545 : out std_logic;
out547 : out std_logic;
out549 : out std_logic;
out550 : out std_logic;
out552 : out std_logic;
out558 : out std_logic;
out559 : out std_logic;
out563 : out std_logic;
out566 : out std_logic;
out572 : out std_logic;
out573 : out std_logic;
out576 : out std_logic;
out577 : out std_logic;
out581 : out std_logic;
out582 : out std_logic;
out590 : out std_logic;
out591 : out std_logic;
out592 : out std_logic;
out593 : out std_logic;
out595 : out std_logic;
out611 : out std_logic;
out619 : out std_logic;
out638 : out std_logic;
out643 : out std_logic;
out644 : out std_logic;
out645 : out std_logic;
out646 : out std_logic;
out648 : out std_logic;
out650 : out std_logic;
out652 : out std_logic;
out657 : out std_logic;
out659 : out std_logic;
out662 : out std_logic;
out677 : out std_logic;
out678 : out std_logic;
out679 : out std_logic;
out680 : out std_logic;
out682 : out std_logic;
out686 : out std_logic;
out692 : out std_logic;
out1218 : out std_logic;
out1219 : out std_logic;
out1220 : out std_logic;
out1221 : out std_logic;
out695 : out std_logic;
out697 : out std_logic;
out706 : out std_logic;
out719 : out std_logic;
out729 : out std_logic;
out744 : out std_logic;
out746 : out std_logic;
out748 : out std_logic;
out833 : out std_logic;
out834 : out std_logic;
out836 : out std_logic;
out837 : out std_logic;
out839 : out std_logic;
out840 : out std_logic;
out841 : out std_logic;
out844 : out std_logic;
out845 : out std_logic;
out846 : out std_logic;
out848 : out std_logic;
out850 : out std_logic;
out852 : out std_logic;
out854 : out std_logic;
out856 : out std_logic;
out858 : out std_logic;
out860 : out std_logic;
out863 : out std_logic;
out865 : out std_logic;
out866 : out std_logic;
out873 : out std_logic;
out877 : out std_logic;
out888 : out std_logic;
out891 : out std_logic;
out893 : out std_logic;
out895 : out std_logic;
out898 : out std_logic;
out900 : out std_logic;
out902 : out std_logic;
out903 : out std_logic;
out904 : out std_logic;
out905 : out std_logic;
out906 : out std_logic;
out907 : out std_logic;
out908 : out std_logic;
out909 : out std_logic;
out910 : out std_logic;
out912 : out std_logic;
out913 : out std_logic;
out914 : out std_logic;
out915 : out std_logic;
out917 : out std_logic;
out920 : out std_logic;
out921 : out std_logic;
out924 : out std_logic;
out934 : out std_logic;
out935 : out std_logic;
out937 : out std_logic;
out938 : out std_logic;
out940 : out std_logic;
out943 : out std_logic;
out945 : out std_logic;
out957 : out std_logic;
out958 : out std_logic;
out962 : out std_logic;
out968 : out std_logic;
out972 : out std_logic;
out973 : out std_logic;
out974 : out std_logic;
out975 : out std_logic;
out976 : out std_logic;
out980 : out std_logic;
out986 : out std_logic;
out988 : out std_logic;
out989 : out std_logic;
out990 : out std_logic;
out1004 : out std_logic;
out1008 : out std_logic;
out999 : out std_logic;
out1000 : out std_logic;
out1002 : out std_logic;
out1003 : out std_logic;
out1050 : out std_logic;
out1052 : out std_logic;
out1053 : out std_logic;
out1055 : out std_logic;
out1056 : out std_logic;
out1057 : out std_logic;
out1059 : out std_logic;
out1015 : out std_logic;
out1025 : out std_logic;
out1026 : out std_logic;
out1038 : out std_logic;
out1039 : out std_logic;
out1042 : out std_logic;
out1043 : out std_logic;
out1046 : out std_logic;
out1048 : out std_logic;
out1061 : out std_logic;
out1063 : out std_logic;
out1064 : out std_logic;
out1067 : out std_logic;
out1068 : out std_logic;
out1069 : out std_logic;
out1071 : out std_logic;
out1073 : out std_logic;
out1076 : out std_logic;
out1077 : out std_logic;
out1078 : out std_logic;
out1080 : out std_logic;
out1081 : out std_logic;
out1083 : out std_logic;
out1085 : out std_logic;
out1087 : out std_logic;
out1089 : out std_logic;
out1092 : out std_logic;
out1096 : out std_logic;
out1100 : out std_logic;
out1103 : out std_logic;
out1115 : out std_logic;
out1122 : out std_logic;
out1123 : out std_logic;
out1127 : out std_logic;
out1130 : out std_logic;
out1133 : out std_logic;
out1138 : out std_logic;
out1139 : out std_logic;
out1140 : out std_logic;
out1141 : out std_logic;
out1142 : out std_logic;
out1143 : out std_logic;
out1144 : out std_logic;
out1145 : out std_logic;
out1146 : out std_logic;
out1147 : out std_logic;
out1148 : out std_logic;
out1149 : out std_logic;
out1150 : out std_logic;
out1151 : out std_logic;
out1152 : out std_logic;
out1153 : out std_logic;
out1154 : out std_logic;
out1155 : out std_logic;
out1156 : out std_logic;
out1157 : out std_logic;
out1158 : out std_logic;
out1159 : out std_logic;
out1160 : out std_logic;
out1161 : out std_logic;
out1162 : out std_logic;
out1163 : out std_logic;
out1164 : out std_logic;
out1165 : out std_logic;
out1166 : out std_logic;
out1167 : out std_logic;
out1168 : out std_logic;
out1169 : out std_logic;
out1170 : out std_logic;
out1171 : out std_logic;
out1172 : out std_logic;
out1173 : out std_logic;
out1174 : out std_logic;
out1175 : out std_logic;
out1176 : out std_logic;
out1177 : out std_logic;
out1178 : out std_logic;
out1179 : out std_logic;
out1180 : out std_logic;
out1181 : out std_logic;
out1182 : out std_logic;
out1183 : out std_logic;
out1184 : out std_logic;
out1185 : out std_logic;
out1186 : out std_logic;
out1187 : out std_logic;
out1188 : out std_logic;
out1189 : out std_logic;
out1190 : out std_logic;
out1191 : out std_logic;
out1192 : out std_logic;
out1193 : out std_logic;
out1194 : out std_logic;
out1195 : out std_logic;
out1196 : out std_logic;
out1197 : out std_logic;
out1198 : out std_logic;
out1199 : out std_logic;
out1200 : out std_logic;
out1201 : out std_logic;
out1202 : out std_logic;
out1203 : out std_logic;
out1204 : out std_logic;
out1205 : out std_logic;
out1206 : out std_logic;
out1207 : out std_logic;
out1208 : out std_logic;
out1209 : out std_logic;
out1210 : out std_logic;
out1211 : out std_logic;
out1212 : out std_logic;
out1213 : out std_logic;
out1214 : out std_logic;
out1215 : out std_logic;
out1216 : out std_logic;
out1217 : out std_logic
);
end fsm_163;
architecture augh of fsm_163 is
signal state_cur : std_logic_vector(0 to 523) := (141 => '1', others => '0');
signal state_next : std_logic_vector(0 to 523) := (141 => '1', others => '0');
-- Buffers for outputs
signal out386_buf : std_logic := '0';
signal out386_bufn : std_logic;
signal out404_buf : std_logic := '0';
signal out404_bufn : std_logic;
signal out457_buf : std_logic := '0';
signal out457_bufn : std_logic;
signal out841_buf : std_logic := '0';
signal out841_bufn : std_logic;
signal out276_buf : std_logic := '0';
signal out276_bufn : std_logic;
signal out67_buf : std_logic := '0';
signal out67_bufn : std_logic;
signal out239_buf : std_logic := '0';
signal out239_bufn : std_logic;
signal out259_buf : std_logic := '0';
signal out259_bufn : std_logic;
signal out416_buf : std_logic := '0';
signal out416_bufn : std_logic;
signal out646_buf : std_logic := '0';
signal out646_bufn : std_logic;
signal out485_buf : std_logic := '0';
signal out485_bufn : std_logic;
signal out935_buf : std_logic := '0';
signal out935_bufn : std_logic;
signal out463_buf : std_logic := '0';
signal out463_bufn : std_logic;
signal out120_buf : std_logic := '0';
signal out120_bufn : std_logic;
signal out293_buf : std_logic := '0';
signal out293_bufn : std_logic;
signal out216_buf : std_logic := '0';
signal out216_bufn : std_logic;
signal out319_buf : std_logic := '0';
signal out319_bufn : std_logic;
signal out230_buf : std_logic := '0';
signal out230_bufn : std_logic;
signal out1_buf : std_logic := '0';
signal out1_bufn : std_logic;
signal out93_buf : std_logic := '0';
signal out93_bufn : std_logic;
signal out89_buf : std_logic := '0';
signal out89_bufn : std_logic;
signal out539_buf : std_logic := '0';
signal out539_bufn : std_logic;
signal out62_buf : std_logic := '0';
signal out62_bufn : std_logic;
signal out856_buf : std_logic := '0';
signal out856_bufn : std_logic;
signal out451_buf : std_logic := '0';
signal out451_bufn : std_logic;
signal out287_buf : std_logic := '0';
signal out287_bufn : std_logic;
signal out315_buf : std_logic := '0';
signal out315_bufn : std_logic;
signal out536_buf : std_logic := '0';
signal out536_bufn : std_logic;
signal out209_buf : std_logic := '0';
signal out209_bufn : std_logic;
signal out221_buf : std_logic := '0';
signal out221_bufn : std_logic;
signal out283_buf : std_logic := '0';
signal out283_bufn : std_logic;
signal out368_buf : std_logic := '0';
signal out368_bufn : std_logic;
signal out516_buf : std_logic := '0';
signal out516_bufn : std_logic;
signal out393_buf : std_logic := '0';
signal out393_bufn : std_logic;
signal out1008_buf : std_logic := '0';
signal out1008_bufn : std_logic;
signal out392_buf : std_logic := '0';
signal out392_bufn : std_logic;
signal out261_buf : std_logic := '0';
signal out261_bufn : std_logic;
signal out559_buf : std_logic := '0';
signal out559_bufn : std_logic;
signal out543_buf : std_logic := '0';
signal out543_bufn : std_logic;
signal out895_buf : std_logic := '0';
signal out895_bufn : std_logic;
signal out82_buf : std_logic := '0';
signal out82_bufn : std_logic;
signal out220_buf : std_logic := '0';
signal out220_bufn : std_logic;
signal out95_buf : std_logic := '0';
signal out95_bufn : std_logic;
signal out943_buf : std_logic := '0';
signal out943_bufn : std_logic;
signal out465_buf : std_logic := '0';
signal out465_bufn : std_logic;
signal out238_buf : std_logic := '0';
signal out238_bufn : std_logic;
signal out1025_buf : std_logic := '0';
signal out1025_bufn : std_logic;
signal out132_buf : std_logic := '0';
signal out132_bufn : std_logic;
signal out79_buf : std_logic := '0';
signal out79_bufn : std_logic;
signal out500_buf : std_logic := '0';
signal out500_bufn : std_logic;
signal out65_buf : std_logic := '0';
signal out65_bufn : std_logic;
signal out111_buf : std_logic := '0';
signal out111_bufn : std_logic;
signal out420_buf : std_logic := '0';
signal out420_bufn : std_logic;
signal out1076_buf : std_logic := '0';
signal out1076_bufn : std_logic;
signal out101_buf : std_logic := '0';
signal out101_bufn : std_logic;
signal out106_buf : std_logic := '0';
signal out106_bufn : std_logic;
signal out68_buf : std_logic := '0';
signal out68_bufn : std_logic;
signal out1069_buf : std_logic := '0';
signal out1069_bufn : std_logic;
signal out77_buf : std_logic := '0';
signal out77_bufn : std_logic;
signal out102_buf : std_logic := '0';
signal out102_bufn : std_logic;
signal out394_buf : std_logic := '0';
signal out394_bufn : std_logic;
signal out342_buf : std_logic := '0';
signal out342_bufn : std_logic;
signal out104_buf : std_logic := '0';
signal out104_bufn : std_logic;
signal out361_buf : std_logic := '0';
signal out361_bufn : std_logic;
signal out116_buf : std_logic := '0';
signal out116_bufn : std_logic;
signal out595_buf : std_logic := '0';
signal out595_bufn : std_logic;
signal out1004_buf : std_logic := '0';
signal out1004_bufn : std_logic;
signal out227_buf : std_logic := '0';
signal out227_bufn : std_logic;
signal out109_buf : std_logic := '0';
signal out109_bufn : std_logic;
signal out619_buf : std_logic := '0';
signal out619_bufn : std_logic;
signal out410_buf : std_logic := '0';
signal out410_bufn : std_logic;
signal out989_buf : std_logic := '0';
signal out989_bufn : std_logic;
signal out431_buf : std_logic := '0';
signal out431_bufn : std_logic;
signal out938_buf : std_logic := '0';
signal out938_bufn : std_logic;
signal out525_buf : std_logic := '0';
signal out525_bufn : std_logic;
signal out73_buf : std_logic := '0';
signal out73_bufn : std_logic;
signal out837_buf : std_logic := '0';
signal out837_bufn : std_logic;
signal out860_buf : std_logic := '0';
signal out860_bufn : std_logic;
signal out228_buf : std_logic := '0';
signal out228_bufn : std_logic;
signal out421_buf : std_logic := '0';
signal out421_bufn : std_logic;
signal out409_buf : std_logic := '0';
signal out409_bufn : std_logic;
signal out473_buf : std_logic := '0';
signal out473_bufn : std_logic;
signal out509_buf : std_logic := '0';
signal out509_bufn : std_logic;
signal out94_buf : std_logic := '0';
signal out94_bufn : std_logic;
signal out1048_buf : std_logic := '0';
signal out1048_bufn : std_logic;
signal out98_buf : std_logic := '0';
signal out98_bufn : std_logic;
signal out945_buf : std_logic := '0';
signal out945_bufn : std_logic;
signal out156_buf : std_logic := '0';
signal out156_bufn : std_logic;
signal out152_buf : std_logic := '0';
signal out152_bufn : std_logic;
-- Retiming: counters
signal rtmcounter0 : unsigned(4 downto 0) := (others => '0');
signal rtmcounter0_next : unsigned(4 downto 0);
-- Retiming: Output of comparators
signal rtmcmp92 : std_logic;
signal rtmcmp128 : std_logic;
signal rtmcmp276 : std_logic;
signal rtmcmp290 : std_logic;
-- Don't understand why these two function declarations are needed...
function "/=" (L, R: std_logic) return std_logic is
begin
if L /= R then
return '1';
end if;
return '0';
end function;
function "=" (L, R: std_logic) return std_logic is
begin
if L = R then
return '1';
end if;
return '0';
end function;
begin
-- Sequential process
-- Set the current state
process (clock)
begin
if rising_edge(clock) then
-- Next state
state_cur <= state_next;
-- Buffers for outputs
out386_buf <= out386_bufn;
out404_buf <= out404_bufn;
out457_buf <= out457_bufn;
out841_buf <= out841_bufn;
out276_buf <= out276_bufn;
out67_buf <= out67_bufn;
out239_buf <= out239_bufn;
out259_buf <= out259_bufn;
out416_buf <= out416_bufn;
out646_buf <= out646_bufn;
out485_buf <= out485_bufn;
out935_buf <= out935_bufn;
out463_buf <= out463_bufn;
out120_buf <= out120_bufn;
out293_buf <= out293_bufn;
out216_buf <= out216_bufn;
out319_buf <= out319_bufn;
out230_buf <= out230_bufn;
out1_buf <= out1_bufn;
out93_buf <= out93_bufn;
out89_buf <= out89_bufn;
out539_buf <= out539_bufn;
out62_buf <= out62_bufn;
out856_buf <= out856_bufn;
out451_buf <= out451_bufn;
out287_buf <= out287_bufn;
out315_buf <= out315_bufn;
out536_buf <= out536_bufn;
out209_buf <= out209_bufn;
out221_buf <= out221_bufn;
out283_buf <= out283_bufn;
out368_buf <= out368_bufn;
out516_buf <= out516_bufn;
out393_buf <= out393_bufn;
out1008_buf <= out1008_bufn;
out392_buf <= out392_bufn;
out261_buf <= out261_bufn;
out559_buf <= out559_bufn;
out543_buf <= out543_bufn;
out895_buf <= out895_bufn;
out82_buf <= out82_bufn;
out220_buf <= out220_bufn;
out95_buf <= out95_bufn;
out943_buf <= out943_bufn;
out465_buf <= out465_bufn;
out238_buf <= out238_bufn;
out1025_buf <= out1025_bufn;
out132_buf <= out132_bufn;
out79_buf <= out79_bufn;
out500_buf <= out500_bufn;
out65_buf <= out65_bufn;
out111_buf <= out111_bufn;
out420_buf <= out420_bufn;
out1076_buf <= out1076_bufn;
out101_buf <= out101_bufn;
out106_buf <= out106_bufn;
out68_buf <= out68_bufn;
out1069_buf <= out1069_bufn;
out77_buf <= out77_bufn;
out102_buf <= out102_bufn;
out394_buf <= out394_bufn;
out342_buf <= out342_bufn;
out104_buf <= out104_bufn;
out361_buf <= out361_bufn;
out116_buf <= out116_bufn;
out595_buf <= out595_bufn;
out1004_buf <= out1004_bufn;
out227_buf <= out227_bufn;
out109_buf <= out109_bufn;
out619_buf <= out619_bufn;
out410_buf <= out410_bufn;
out989_buf <= out989_bufn;
out431_buf <= out431_bufn;
out938_buf <= out938_bufn;
out525_buf <= out525_bufn;
out73_buf <= out73_bufn;
out837_buf <= out837_bufn;
out860_buf <= out860_bufn;
out228_buf <= out228_bufn;
out421_buf <= out421_bufn;
out409_buf <= out409_bufn;
out473_buf <= out473_bufn;
out509_buf <= out509_bufn;
out94_buf <= out94_bufn;
out1048_buf <= out1048_bufn;
out98_buf <= out98_bufn;
out945_buf <= out945_bufn;
out156_buf <= out156_bufn;
out152_buf <= out152_bufn;
-- Retiming: counters
rtmcounter0 <= rtmcounter0_next;
end if;
end process;
-- Retiming: the counters
rtmcounter0_next <= rtmcounter0 + 1 when (reset /= '1') and (
(state_cur(290) = '1' and rtmcmp290 = '0') or (state_cur(276) = '1' and rtmcmp276 = '0') or (state_cur(128) = '1' and rtmcmp128 = '0') or (state_cur(92) = '1' and rtmcmp92 = '0')
) else (others => '0');
-- Next state bits
state_next(0) <= (reset /= '1') and ( ( state_cur(90) and not ( (NOT(in0)) = '1' ) ) );
state_next(1) <= (reset /= '1') and ( ( state_cur(86) and not ( (NOT(in1)) = '1' ) ) );
state_next(2) <= (reset /= '1') and ( ( state_cur(44) and not ( (NOT(in0)) = '1' ) ) );
state_next(3) <= (reset /= '1') and ( ( state_cur(201) and not ( (NOT(in0)) = '1' ) ) );
state_next(4) <= (reset /= '1') and ( ( state_cur(48) and not ( (NOT(in0)) = '1' ) ) );
state_next(5) <= (reset /= '1') and ( ( state_cur(6) and not ( (NOT(in0)) = '1' ) ) );
state_next(6) <= (reset /= '1') and ( state_cur(32) or ( state_cur(6) and (NOT(in0)) = '1' ) );
state_next(7) <= (reset /= '1') and ( ( state_cur(207) and not ( (NOT(in0)) = '1' ) ) );
state_next(8) <= (reset /= '1') and ( ( state_cur(17) and not ( (NOT(in0)) = '1' ) ) );
state_next(9) <= (reset /= '1') and ( ( state_cur(13) and not ( (NOT(in0)) = '1' ) ) );
state_next(10) <= (reset /= '1') and ( state_cur(221) or ( state_cur(10) and (NOT(in0)) = '1' ) );
state_next(11) <= (reset /= '1') and ( state_cur(83) or ( state_cur(11) and (NOT(in1)) = '1' ) );
state_next(12) <= (reset /= '1') and ( state_cur(23) or ( state_cur(12) and (NOT(in0)) = '1' ) );
state_next(13) <= (reset /= '1') and ( state_cur(321) or ( state_cur(13) and (NOT(in0)) = '1' ) );
state_next(14) <= (reset /= '1') and ( state_cur(251) or ( state_cur(14) and (NOT(in0)) = '1' ) );
state_next(15) <= (reset /= '1') and ( ( state_cur(263) and not ( (NOT(in0)) = '1' ) ) );
state_next(16) <= (reset /= '1') and ( ( state_cur(188) and not ( (NOT(in0)) = '1' ) ) );
state_next(17) <= (reset /= '1') and ( ( state_cur(17) and (NOT(in0)) = '1' ) or state_cur(9) );
state_next(18) <= (reset /= '1') and ( ( state_cur(239) and not ( (NOT(in0)) = '1' ) ) );
state_next(19) <= (reset /= '1') and ( ( state_cur(14) and not ( (NOT(in0)) = '1' ) ) );
state_next(20) <= (reset /= '1') and ( ( state_cur(27) and not ( (NOT(in0)) = '1' ) ) );
state_next(21) <= (reset /= '1') and ( state_cur(22) or ( state_cur(21) and (NOT(in0)) = '1' ) );
state_next(22) <= (reset /= '1') and ( ( state_cur(26) and not ( (NOT(in0)) = '1' ) ) );
state_next(23) <= (reset /= '1') and ( ( state_cur(117) and not ( (NOT(in0)) = '1' ) ) );
state_next(24) <= (reset /= '1') and ( state_cur(254) or ( state_cur(24) and (NOT(in0)) = '1' ) );
state_next(25) <= (reset /= '1') and ( ( state_cur(320) and not ( (NOT(in0)) = '1' ) ) );
state_next(26) <= (reset /= '1') and ( ( state_cur(26) and (NOT(in0)) = '1' ) or state_cur(25) );
state_next(27) <= (reset /= '1') and ( state_cur(81) or ( state_cur(27) and (NOT(in0)) = '1' ) );
state_next(28) <= (reset /= '1') and ( state_cur(261) or ( state_cur(28) and (NOT(in0)) = '1' ) );
state_next(29) <= (reset /= '1') and ( state_cur(198) or ( state_cur(29) and (NOT(in1)) = '1' ) );
state_next(30) <= (reset /= '1') and ( ( state_cur(324) and not ( (NOT(in0)) = '1' ) ) );
state_next(31) <= (reset /= '1') and ( ( state_cur(33) and not ( (NOT(in0)) = '1' ) ) );
state_next(32) <= (reset /= '1') and ( ( state_cur(259) and not ( (NOT(in0)) = '1' ) ) );
state_next(33) <= (reset /= '1') and ( state_cur(267) or ( state_cur(33) and (NOT(in0)) = '1' ) );
state_next(34) <= (reset /= '1') and ( ( state_cur(34) and (NOT(in0)) = '1' ) or state_cur(31) );
state_next(35) <= (reset /= '1') and ( state_cur(36) or ( state_cur(35) and (NOT(in0)) = '1' ) );
state_next(36) <= (reset /= '1') and ( ( state_cur(34) and not ( (NOT(in0)) = '1' ) ) );
state_next(37) <= (reset /= '1') and ( state_cur(38) or ( state_cur(37) and (NOT(in0)) = '1' ) );
state_next(38) <= (reset /= '1') and ( ( state_cur(35) and not ( (NOT(in0)) = '1' ) ) );
state_next(39) <= (reset /= '1') and ( ( state_cur(323) and not ( (NOT(in0)) = '1' ) ) );
state_next(40) <= (reset /= '1') and ( ( state_cur(285) and not ( (NOT(in0)) = '1' ) ) );
state_next(41) <= (reset /= '1') and ( ( state_cur(41) and (NOT(in0)) = '1' ) or state_cur(8) );
state_next(42) <= (reset /= '1') and ( state_cur(180) or ( state_cur(42) and (NOT(in1)) = '1' ) );
state_next(43) <= (reset /= '1') and ( ( state_cur(41) and not ( (NOT(in0)) = '1' ) ) );
state_next(44) <= (reset /= '1') and ( state_cur(66) or ( state_cur(44) and (NOT(in0)) = '1' ) );
state_next(45) <= (reset /= '1') and ( ( state_cur(37) and not ( (NOT(in0)) = '1' ) ) );
state_next(46) <= (reset /= '1') and ( ( state_cur(46) and (NOT(in0)) = '1' ) or state_cur(43) );
state_next(47) <= (reset /= '1') and ( ( state_cur(46) and not ( (NOT(in0)) = '1' ) ) );
state_next(48) <= (reset /= '1') and ( ( state_cur(48) and (NOT(in0)) = '1' ) or state_cur(40) );
state_next(49) <= (reset /= '1') and ( ( state_cur(49) and (NOT(in0)) = '1' ) or state_cur(18) );
state_next(50) <= (reset /= '1') and ( ( state_cur(50) and (NOT(in0)) = '1' ) or state_cur(47) );
state_next(51) <= (reset /= '1') and ( state_cur(53) or ( state_cur(51) and (NOT(in0)) = '1' ) );
state_next(52) <= (reset /= '1') and ( state_cur(56) or ( state_cur(52) and (NOT(in0)) = '1' ) );
state_next(53) <= (reset /= '1') and ( ( state_cur(52) and not ( (NOT(in0)) = '1' ) ) );
state_next(54) <= (reset /= '1') and ( ( state_cur(51) and not ( (NOT(in0)) = '1' ) ) );
state_next(55) <= (reset /= '1') and ( ( state_cur(55) and (NOT(in0)) = '1' ) or state_cur(54) );
state_next(56) <= (reset /= '1') and ( ( state_cur(21) and not ( (NOT(in0)) = '1' ) ) );
state_next(57) <= (reset /= '1') and ( ( state_cur(104) and not ( (NOT(in0)) = '1' ) ) );
state_next(58) <= (reset /= '1') and ( ( state_cur(12) and not ( (NOT(in0)) = '1' ) ) );
state_next(59) <= (reset /= '1') and ( ( state_cur(61) and not ( (NOT(in0)) = '1' ) ) );
state_next(60) <= (reset /= '1') and ( ( state_cur(246) and not ( (NOT(in0)) = '1' ) ) );
state_next(61) <= (reset /= '1') and ( state_cur(260) or ( state_cur(61) and (NOT(in0)) = '1' ) );
state_next(62) <= (reset /= '1') and ( ( state_cur(65) and not ( (NOT(in0)) = '1' ) ) );
state_next(63) <= (reset /= '1') and ( ( state_cur(24) and not ( (NOT(in0)) = '1' ) ) );
state_next(64) <= (reset /= '1') and ( state_cur(277) or ( state_cur(64) and (NOT(in0)) = '1' ) );
state_next(65) <= (reset /= '1') and ( state_cur(329) or ( state_cur(65) and (NOT(in0)) = '1' ) );
state_next(66) <= (reset /= '1') and ( ( state_cur(256) and not ( (NOT(in0)) = '1' ) ) );
state_next(67) <= (reset /= '1') and ( ( state_cur(67) and (NOT(in0)) = '1' ) or state_cur(62) );
state_next(68) <= (reset /= '1') and ( ( state_cur(68) and (NOT(in0)) = '1' ) or state_cur(60) );
state_next(69) <= (reset /= '1') and ( ( state_cur(258) and not ( (NOT(in0)) = '1' ) ) );
state_next(70) <= (reset /= '1') and ( ( state_cur(278) and not ( (NOT(in0)) = '1' ) ) );
state_next(71) <= (reset /= '1') and ( ( state_cur(255) and not ( (NOT(in1)) = '1' ) ) );
state_next(72) <= (reset /= '1') and ( state_cur(85) or ( state_cur(72) and (NOT(in1)) = '1' ) );
state_next(73) <= (reset /= '1') and ( ( state_cur(106) and not ( (NOT(in1)) = '1' ) ) );
state_next(74) <= (reset /= '1') and ( ( state_cur(297) and not ( (NOT(in0)) = '1' ) ) );
state_next(75) <= (reset /= '1') and ( ( state_cur(75) and (NOT(in0)) = '1' ) or state_cur(57) );
state_next(76) <= (reset /= '1') and ( ( state_cur(272) and not ( (NOT(in0)) = '1' ) ) );
state_next(77) <= (reset /= '1') and ( state_cur(199) or ( state_cur(77) and (NOT(in0)) = '1' ) );
state_next(78) <= (reset /= '1') and ( state_cur(115) or ( state_cur(78) and (NOT(in1)) = '1' ) );
state_next(79) <= (reset /= '1') and ( ( state_cur(42) and not ( (NOT(in1)) = '1' ) ) );
state_next(80) <= (reset /= '1') and ( ( state_cur(80) and (NOT(in0)) = '1' ) or state_cur(7) );
state_next(81) <= (reset /= '1') and ( ( state_cur(80) and not ( (NOT(in0)) = '1' ) ) );
state_next(82) <= (reset /= '1') and ( ( state_cur(217) and not ( (NOT(in0)) = '1' ) ) );
state_next(83) <= (reset /= '1') and ( ( state_cur(72) and not ( (NOT(in1)) = '1' ) ) );
state_next(84) <= (reset /= '1') and ( ( state_cur(84) and (NOT(in0)) = '1' ) or state_cur(82) );
state_next(85) <= (reset /= '1') and ( ( state_cur(29) and not ( (NOT(in1)) = '1' ) ) );
state_next(86) <= (reset /= '1') and ( state_cur(195) or ( state_cur(86) and (NOT(in1)) = '1' ) );
state_next(87) <= (reset /= '1') and ( ( state_cur(87) and (NOT(in0)) = '1' ) or state_cur(20) );
state_next(88) <= (reset /= '1') and ( ( state_cur(288) and not ( (NOT(in0)) = '1' ) ) );
state_next(89) <= (reset /= '1') and ( ( state_cur(140) and not ( (NOT(in0)) = '1' ) ) );
state_next(90) <= (reset /= '1') and ( ( state_cur(90) and (NOT(in0)) = '1' ) or state_cur(89) );
state_next(91) <= (reset /= '1') and ( state_cur(337) );
state_next(92) <= (reset /= '1') and ( (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) );
state_next(93) <= (reset /= '1') and ( state_cur(339) );
state_next(94) <= (reset /= '1') and ( ( state_cur(175) and not ( (in4) = '1' ) ) );
state_next(95) <= (reset /= '1') and ( state_cur(334) );
state_next(96) <= (reset /= '1') and ( state_cur(333) );
state_next(97) <= (reset /= '1') and ( state_cur(244) or ( state_cur(97) and (NOT(in0)) = '1' ) );
state_next(98) <= (reset /= '1') and ( state_cur(228) );
state_next(99) <= (reset /= '1') and ( state_cur(273) or state_cur(105) );
state_next(100) <= (reset /= '1') and ( state_cur(203) );
state_next(101) <= (reset /= '1') and ( ( state_cur(101) and (NOT(in0)) = '1' ) or state_cur(5) );
state_next(102) <= (reset /= '1') and ( state_cur(98) );
state_next(103) <= (reset /= '1') and ( state_cur(200) );
state_next(104) <= (reset /= '1') and ( state_cur(111) or ( state_cur(104) and (NOT(in0)) = '1' ) );
state_next(105) <= (reset /= '1') and ( state_cur(301) );
state_next(106) <= (reset /= '1') and ( state_cur(214) or ( state_cur(106) and (NOT(in1)) = '1' ) );
state_next(107) <= (reset /= '1') and ( rtmcmp276 );
state_next(108) <= (reset /= '1') and ( state_cur(224) );
state_next(109) <= (reset /= '1') and ( ( state_cur(310) and (in9) = '1' ) );
state_next(110) <= (reset /= '1') and ( state_cur(222) or ( state_cur(110) and (NOT(in1)) = '1' ) );
state_next(111) <= (reset /= '1') and ( ( state_cur(112) and not ( (NOT(in0)) = '1' ) ) );
state_next(112) <= (reset /= '1') and ( state_cur(293) or ( state_cur(112) and (NOT(in0)) = '1' ) );
state_next(113) <= (reset /= '1') and ( ( state_cur(304) and not ( (NOT(in0)) = '1' ) ) );
state_next(114) <= (reset /= '1') and ( state_cur(523) or state_cur(129) );
state_next(115) <= (reset /= '1') and ( ( state_cur(110) and not ( (NOT(in1)) = '1' ) ) );
state_next(116) <= (reset /= '1') and ( state_cur(327) or ( state_cur(116) and (NOT(in0)) = '1' ) );
state_next(117) <= (reset /= '1') and ( ( state_cur(117) and (NOT(in0)) = '1' ) or state_cur(2) );
state_next(118) <= (reset /= '1') and ( state_cur(181) or ( state_cur(118) and (NOT(in0)) = '1' ) );
state_next(119) <= (reset /= '1') and ( state_cur(274) );
state_next(120) <= (reset /= '1') and ( ( state_cur(120) and (NOT(in0)) = '1' ) or state_cur(15) );
state_next(121) <= (reset /= '1') and ( state_cur(227) or ( state_cur(121) and (NOT(in0)) = '1' ) );
state_next(122) <= (reset /= '1') and ( ( state_cur(122) and (NOT(in0)) = '1' ) or state_cur(4) );
state_next(123) <= (reset /= '1') and ( state_cur(303) );
state_next(124) <= (reset /= '1') and ( state_cur(133) or ( state_cur(124) and (NOT(in0)) = '1' ) );
state_next(125) <= (reset /= '1') and ( ( state_cur(343) and not ( (NOT(in1)) = '1' ) ) );
state_next(126) <= (reset /= '1') and ( ( state_cur(314) and not ( (NOT(in0)) = '1' ) ) );
state_next(127) <= (reset /= '1') and ( ( state_cur(127) and (NOT(in0)) = '1' ) or state_cur(126) );
state_next(128) <= (reset /= '1') and ( (state_cur(128) = '1' and rtmcmp128 = '0') or state_cur(296) );
state_next(129) <= (reset /= '1') and ( ( state_cur(208) and (in5) = '1' ) );
state_next(130) <= (reset /= '1') and ( state_cur(137) or ( state_cur(130) and (NOT(in0)) = '1' ) );
state_next(131) <= (reset /= '1') and ( ( state_cur(127) and not ( (NOT(in0)) = '1' ) ) );
state_next(132) <= (reset /= '1') and ( state_cur(191) );
state_next(133) <= (reset /= '1') and ( ( state_cur(118) and not ( (NOT(in0)) = '1' ) ) );
state_next(134) <= (reset /= '1') and ( state_cur(172) );
state_next(135) <= (reset /= '1') and ( state_cur(284) or ( state_cur(135) and (NOT(in0)) = '1' ) );
state_next(136) <= (reset /= '1') and ( state_cur(230) or ( state_cur(136) and (NOT(in0)) = '1' ) );
state_next(137) <= (reset /= '1') and ( ( state_cur(116) and not ( (NOT(in0)) = '1' ) ) );
state_next(138) <= (reset /= '1') and ( ( state_cur(175) and (in4) = '1' ) );
state_next(139) <= (reset /= '1') and ( ( state_cur(101) and not ( (NOT(in0)) = '1' ) ) );
state_next(140) <= (reset /= '1') and ( ( state_cur(140) and (NOT(in0)) = '1' ) or state_cur(139) );
state_next(141) <= (reset = '1') or ( ( state_cur(141) and (NOT(in2)) = '1' ) );
state_next(142) <= (reset /= '1') and ( state_cur(270) );
state_next(143) <= (reset /= '1') and ( state_cur(204) );
state_next(144) <= (reset /= '1') and ( state_cur(173) );
state_next(145) <= (reset /= '1') and ( state_cur(322) );
state_next(146) <= (reset /= '1') and ( state_cur(331) );
state_next(147) <= (reset /= '1') and ( state_cur(197) );
state_next(148) <= (reset /= '1') and ( state_cur(306) );
state_next(149) <= (reset /= '1') and ( state_cur(187) );
state_next(150) <= (reset /= '1') and ( state_cur(294) );
state_next(151) <= (reset /= '1') and ( state_cur(289) );
state_next(152) <= (reset /= '1') and ( ( state_cur(153) and not ( (NOT(in0)) = '1' ) ) );
state_next(153) <= (reset /= '1') and ( state_cur(154) or ( state_cur(153) and (NOT(in0)) = '1' ) );
state_next(154) <= (reset /= '1') and ( ( state_cur(155) and not ( (NOT(in0)) = '1' ) ) );
state_next(155) <= (reset /= '1') and ( state_cur(156) or ( state_cur(155) and (NOT(in0)) = '1' ) );
state_next(156) <= (reset /= '1') and ( ( state_cur(157) and not ( (NOT(in0)) = '1' ) ) );
state_next(157) <= (reset /= '1') and ( state_cur(158) or ( state_cur(157) and (NOT(in0)) = '1' ) );
state_next(158) <= (reset /= '1') and ( ( state_cur(159) and not ( (NOT(in0)) = '1' ) ) );
state_next(159) <= (reset /= '1') and ( state_cur(160) or ( state_cur(159) and (NOT(in0)) = '1' ) );
state_next(160) <= (reset /= '1') and ( ( state_cur(161) and not ( (NOT(in0)) = '1' ) ) );
state_next(161) <= (reset /= '1') and ( state_cur(162) or ( state_cur(161) and (NOT(in0)) = '1' ) );
state_next(162) <= (reset /= '1') and ( ( state_cur(163) and not ( (NOT(in0)) = '1' ) ) );
state_next(163) <= (reset /= '1') and ( state_cur(164) or ( state_cur(163) and (NOT(in0)) = '1' ) );
state_next(164) <= (reset /= '1') and ( ( state_cur(165) and not ( (NOT(in0)) = '1' ) ) );
state_next(165) <= (reset /= '1') and ( state_cur(166) or ( state_cur(165) and (NOT(in0)) = '1' ) );
state_next(166) <= (reset /= '1') and ( ( state_cur(167) and not ( (NOT(in0)) = '1' ) ) );
state_next(167) <= (reset /= '1') and ( state_cur(168) or ( state_cur(167) and (NOT(in0)) = '1' ) );
state_next(168) <= (reset /= '1') and ( ( state_cur(55) and not ( (NOT(in0)) = '1' ) ) );
state_next(169) <= (reset /= '1') and ( state_cur(332) );
state_next(170) <= (reset /= '1') and ( state_cur(169) );
state_next(171) <= (reset /= '1') and ( ( state_cur(171) and (NOT(in0)) = '1' ) or state_cur(16) );
state_next(172) <= (reset /= '1') and ( state_cur(174) );
state_next(173) <= (reset /= '1') and ( ( state_cur(325) and (in10) = '1' ) or ( state_cur(310) and not ( (in9) = '1' ) ) );
state_next(174) <= (reset /= '1') and ( state_cur(319) );
state_next(175) <= (reset /= '1') and ( state_cur(170) );
state_next(176) <= (reset /= '1') and ( ( state_cur(176) and (NOT(in0)) = '1' ) or state_cur(70) );
state_next(177) <= (reset /= '1') and ( ( state_cur(279) and not ( (NOT(in0)) = '1' ) ) );
state_next(178) <= (reset /= '1') and ( ( state_cur(150) and (in3) = '1' ) );
state_next(179) <= (reset /= '1') and ( state_cur(282) );
state_next(180) <= (reset /= '1') and ( ( state_cur(520) and not ( (NOT(in1)) = '1' ) ) );
state_next(181) <= (reset /= '1') and ( ( state_cur(226) and not ( (NOT(in0)) = '1' ) ) );
state_next(182) <= (reset /= '1') and ( state_cur(223) );
state_next(183) <= (reset /= '1') and ( state_cur(280) );
state_next(184) <= (reset /= '1') and ( state_cur(183) );
state_next(185) <= (reset /= '1') and ( ( state_cur(135) and not ( (NOT(in0)) = '1' ) ) );
state_next(186) <= (reset /= '1') and ( rtmcmp290 );
state_next(187) <= (reset /= '1') and ( state_cur(184) );
state_next(188) <= (reset /= '1') and ( state_cur(206) or ( state_cur(188) and (NOT(in0)) = '1' ) );
state_next(189) <= (reset /= '1') and ( state_cur(179) );
state_next(190) <= (reset /= '1') and ( state_cur(186) );
state_next(191) <= (reset /= '1') and ( state_cur(190) );
state_next(192) <= (reset /= '1') and ( ( state_cur(192) and (NOT(in0)) = '1' ) or state_cur(76) );
state_next(193) <= (reset /= '1') and ( state_cur(233) );
state_next(194) <= (reset /= '1') and ( state_cur(252) or ( state_cur(194) and (NOT(in0)) = '1' ) );
state_next(195) <= (reset /= '1') and ( ( state_cur(521) and not ( (NOT(in1)) = '1' ) ) );
state_next(196) <= (reset /= '1') and ( state_cur(231) );
state_next(197) <= (reset /= '1') and ( state_cur(218) );
state_next(198) <= (reset /= '1') and ( ( state_cur(78) and not ( (NOT(in1)) = '1' ) ) );
state_next(199) <= (reset /= '1') and ( ( state_cur(120) and not ( (NOT(in0)) = '1' ) ) );
state_next(200) <= (reset /= '1') and ( state_cur(95) );
state_next(201) <= (reset /= '1') and ( state_cur(307) or ( state_cur(201) and (NOT(in0)) = '1' ) );
state_next(202) <= (reset /= '1') and ( state_cur(266) or ( state_cur(202) and (NOT(in0)) = '1' ) );
state_next(203) <= (reset /= '1') and ( state_cur(91) );
state_next(204) <= (reset /= '1') and ( state_cur(123) );
state_next(205) <= (reset /= '1') and ( ( state_cur(211) and not ( (NOT(in0)) = '1' ) ) );
state_next(206) <= (reset /= '1') and ( ( state_cur(136) and not ( (NOT(in0)) = '1' ) ) );
state_next(207) <= (reset /= '1') and ( ( state_cur(207) and (NOT(in0)) = '1' ) or state_cur(205) );
state_next(208) <= (reset /= '1') and ( state_cur(300) );
state_next(209) <= (reset /= '1') and ( state_cur(312) );
state_next(210) <= (reset /= '1') and ( state_cur(292) );
state_next(211) <= (reset /= '1') and ( ( state_cur(211) and (NOT(in0)) = '1' ) or state_cur(185) );
state_next(212) <= (reset /= '1') and ( state_cur(326) );
state_next(213) <= (reset /= '1') and ( state_cur(340) );
state_next(214) <= (reset /= '1') and ( ( state_cur(11) and not ( (NOT(in1)) = '1' ) ) );
state_next(215) <= (reset /= '1') and ( state_cur(229) or ( state_cur(215) and (NOT(in0)) = '1' ) );
state_next(216) <= (reset /= '1') and ( state_cur(248) or ( state_cur(216) and (NOT(in0)) = '1' ) );
state_next(217) <= (reset /= '1') and ( state_cur(271) or ( state_cur(217) and (NOT(in0)) = '1' ) );
state_next(218) <= (reset /= '1') and ( state_cur(146) or state_cur(138) );
state_next(219) <= (reset /= '1') and ( state_cur(151) );
state_next(220) <= (reset /= '1') and ( state_cur(298) );
state_next(221) <= (reset /= '1') and ( ( state_cur(318) and not ( (NOT(in0)) = '1' ) ) );
state_next(222) <= (reset /= '1') and ( state_cur(152) or ( state_cur(141) and not ( (NOT(in2)) = '1' ) ) );
state_next(223) <= (reset /= '1') and ( state_cur(232) );
state_next(224) <= (reset /= '1') and ( state_cur(342) );
state_next(225) <= (reset /= '1') and ( ( state_cur(202) and not ( (NOT(in0)) = '1' ) ) );
state_next(226) <= (reset /= '1') and ( state_cur(311) or ( state_cur(226) and (NOT(in0)) = '1' ) );
state_next(227) <= (reset /= '1') and ( ( state_cur(250) and not ( (NOT(in0)) = '1' ) ) );
state_next(228) <= (reset /= '1') and ( state_cur(189) );
state_next(229) <= (reset /= '1') and ( ( state_cur(216) and not ( (NOT(in0)) = '1' ) ) );
state_next(230) <= (reset /= '1') and ( ( state_cur(176) and not ( (NOT(in0)) = '1' ) ) );
state_next(231) <= (reset /= '1') and ( state_cur(234) );
state_next(232) <= (reset /= '1') and ( state_cur(145) );
state_next(233) <= (reset /= '1') and ( state_cur(236) );
state_next(234) <= (reset /= '1') and ( state_cur(235) );
state_next(235) <= (reset /= '1') and ( state_cur(102) );
state_next(236) <= (reset /= '1') and ( state_cur(237) );
state_next(237) <= (reset /= '1') and ( state_cur(99) );
state_next(238) <= (reset /= '1') and ( ( state_cur(287) and not ( (NOT(in0)) = '1' ) ) );
state_next(239) <= (reset /= '1') and ( ( state_cur(239) and (NOT(in0)) = '1' ) or state_cur(58) );
state_next(240) <= (reset /= '1') and ( state_cur(241) or state_cur(148) );
state_next(241) <= (reset /= '1') and ( ( state_cur(245) and not ( (in8) = '1' ) ) );
state_next(242) <= (reset /= '1') and ( ( state_cur(97) and not ( (NOT(in0)) = '1' ) ) );
state_next(243) <= (reset /= '1') and ( state_cur(275) or ( state_cur(243) and (NOT(in0)) = '1' ) );
state_next(244) <= (reset /= '1') and ( ( state_cur(245) and (in8) = '1' ) );
state_next(245) <= (reset /= '1') and ( state_cur(247) or state_cur(242) );
state_next(246) <= (reset /= '1') and ( state_cur(253) or ( state_cur(246) and (NOT(in0)) = '1' ) );
state_next(247) <= (reset /= '1') and ( ( state_cur(328) and not ( (in11) = '1' ) ) );
state_next(248) <= (reset /= '1') and ( ( state_cur(302) and not ( (NOT(in0)) = '1' ) ) );
state_next(249) <= (reset /= '1') and ( ( state_cur(77) and not ( (NOT(in0)) = '1' ) ) );
state_next(250) <= (reset /= '1') and ( ( state_cur(250) and (NOT(in0)) = '1' ) or state_cur(88) );
state_next(251) <= (reset /= '1') and ( ( state_cur(130) and not ( (NOT(in0)) = '1' ) ) );
state_next(252) <= (reset /= '1') and ( ( state_cur(171) and not ( (NOT(in0)) = '1' ) ) );
state_next(253) <= (reset /= '1') and ( ( state_cur(49) and not ( (NOT(in0)) = '1' ) ) );
state_next(254) <= (reset /= '1') and ( ( state_cur(68) and not ( (NOT(in0)) = '1' ) ) );
state_next(255) <= (reset /= '1') and ( ( state_cur(255) and (NOT(in1)) = '1' ) or state_cur(79) );
state_next(256) <= (reset /= '1') and ( ( state_cur(256) and (NOT(in0)) = '1' ) or state_cur(69) );
state_next(257) <= (reset /= '1') and ( ( state_cur(64) and not ( (NOT(in0)) = '1' ) ) );
state_next(258) <= (reset /= '1') and ( ( state_cur(258) and (NOT(in0)) = '1' ) or state_cur(249) );
state_next(259) <= (reset /= '1') and ( state_cur(283) or ( state_cur(259) and (NOT(in0)) = '1' ) );
state_next(260) <= (reset /= '1') and ( ( state_cur(50) and not ( (NOT(in0)) = '1' ) ) );
state_next(261) <= (reset /= '1') and ( ( state_cur(269) and not ( (NOT(in0)) = '1' ) ) );
state_next(262) <= (reset /= '1') and ( ( state_cur(240) and not ( (in7) = '1' ) ) );
state_next(263) <= (reset /= '1') and ( ( state_cur(263) and (NOT(in0)) = '1' ) or state_cur(19) );
state_next(264) <= (reset /= '1') and ( state_cur(315) or ( state_cur(264) and (NOT(in0)) = '1' ) );
state_next(265) <= (reset /= '1') and ( ( state_cur(124) and not ( (NOT(in0)) = '1' ) ) );
state_next(266) <= (reset /= '1') and ( ( state_cur(87) and not ( (NOT(in0)) = '1' ) ) );
state_next(267) <= (reset /= '1') and ( ( state_cur(243) and not ( (NOT(in0)) = '1' ) ) );
state_next(268) <= (reset /= '1') and ( state_cur(103) );
state_next(269) <= (reset /= '1') and ( ( state_cur(269) and (NOT(in0)) = '1' ) or state_cur(257) );
state_next(270) <= (reset /= '1') and ( state_cur(144) );
state_next(271) <= (reset /= '1') and ( ( state_cur(28) and not ( (NOT(in0)) = '1' ) ) );
state_next(272) <= (reset /= '1') and ( ( state_cur(272) and (NOT(in0)) = '1' ) or state_cur(225) );
state_next(273) <= (reset /= '1') and ( ( state_cur(220) and (in6) = '1' ) );
state_next(274) <= (reset /= '1') and ( state_cur(134) );
state_next(275) <= (reset /= '1') and ( ( state_cur(75) and not ( (NOT(in0)) = '1' ) ) );
state_next(276) <= (reset /= '1') and ( (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114) );
state_next(277) <= (reset /= '1') and ( ( state_cur(67) and not ( (NOT(in0)) = '1' ) ) );
state_next(278) <= (reset /= '1') and ( ( state_cur(278) and (NOT(in0)) = '1' ) or state_cur(265) );
state_next(279) <= (reset /= '1') and ( ( state_cur(279) and (NOT(in0)) = '1' ) or state_cur(3) );
state_next(280) <= (reset /= '1') and ( state_cur(281) );
state_next(281) <= (reset /= '1') and ( ( state_cur(208) and not ( (in5) = '1' ) ) );
state_next(282) <= (reset /= '1') and ( state_cur(100) );
state_next(283) <= (reset /= '1') and ( ( state_cur(10) and not ( (NOT(in0)) = '1' ) ) );
state_next(284) <= (reset /= '1') and ( ( state_cur(264) and not ( (NOT(in0)) = '1' ) ) );
state_next(285) <= (reset /= '1') and ( state_cur(286) or ( state_cur(285) and (NOT(in0)) = '1' ) );
state_next(286) <= (reset /= '1') and ( ( state_cur(313) and not ( (NOT(in0)) = '1' ) ) );
state_next(287) <= (reset /= '1') and ( ( state_cur(287) and (NOT(in0)) = '1' ) or state_cur(177) );
state_next(288) <= (reset /= '1') and ( ( state_cur(288) and (NOT(in0)) = '1' ) or state_cur(45) );
state_next(289) <= (reset /= '1') and ( state_cur(210) );
state_next(290) <= (reset /= '1') and ( (state_cur(290) = '1' and rtmcmp290 = '0') or state_cur(291) );
state_next(291) <= (reset /= '1') and ( ( state_cur(240) and (in7) = '1' ) );
state_next(292) <= (reset /= '1') and ( state_cur(147) );
state_next(293) <= (reset /= '1') and ( ( state_cur(295) and not ( (NOT(in0)) = '1' ) ) );
state_next(294) <= (reset /= '1') and ( state_cur(132) );
state_next(295) <= (reset /= '1') and ( ( state_cur(295) and (NOT(in0)) = '1' ) or state_cur(113) );
state_next(296) <= (reset /= '1') and ( state_cur(268) or state_cur(178) );
state_next(297) <= (reset /= '1') and ( ( state_cur(297) and (NOT(in0)) = '1' ) or state_cur(0) );
state_next(298) <= (reset /= '1') and ( state_cur(143) );
state_next(299) <= (reset /= '1') and ( ( state_cur(194) and not ( (NOT(in0)) = '1' ) ) );
state_next(300) <= (reset /= '1') and ( state_cur(142) );
state_next(301) <= (reset /= '1') and ( state_cur(108) );
state_next(302) <= (reset /= '1') and ( ( state_cur(302) and (NOT(in0)) = '1' ) or state_cur(299) );
state_next(303) <= (reset /= '1') and ( rtmcmp128 );
state_next(304) <= (reset /= '1') and ( ( state_cur(304) and (NOT(in0)) = '1' ) or state_cur(39) );
state_next(305) <= (reset /= '1') and ( ( state_cur(305) and (NOT(in0)) = '1' ) or state_cur(30) );
state_next(306) <= (reset /= '1') and ( state_cur(209) );
state_next(307) <= (reset /= '1') and ( ( state_cur(192) and not ( (NOT(in0)) = '1' ) ) );
state_next(308) <= (reset /= '1') and ( ( state_cur(325) and not ( (in10) = '1' ) ) );
state_next(309) <= (reset /= '1') and ( ( state_cur(122) and not ( (NOT(in0)) = '1' ) ) );
state_next(310) <= (reset /= '1') and ( state_cur(308) or state_cur(196) );
state_next(311) <= (reset /= '1') and ( ( state_cur(84) and not ( (NOT(in0)) = '1' ) ) );
state_next(312) <= (reset /= '1') and ( state_cur(119) );
state_next(313) <= (reset /= '1') and ( state_cur(330) or ( state_cur(313) and (NOT(in0)) = '1' ) );
state_next(314) <= (reset /= '1') and ( ( state_cur(314) and (NOT(in0)) = '1' ) or state_cur(59) );
state_next(315) <= (reset /= '1') and ( ( state_cur(121) and not ( (NOT(in0)) = '1' ) ) );
state_next(316) <= (reset /= '1') and ( ( state_cur(316) and (NOT(in0)) = '1' ) or state_cur(63) );
state_next(317) <= (reset /= '1') and ( ( state_cur(317) and (NOT(in0)) = '1' ) or state_cur(74) );
state_next(318) <= (reset /= '1') and ( ( state_cur(318) and (NOT(in0)) = '1' ) or state_cur(262) );
state_next(319) <= (reset /= '1') and ( state_cur(338) );
state_next(320) <= (reset /= '1') and ( ( state_cur(320) and (NOT(in0)) = '1' ) or state_cur(131) );
state_next(321) <= (reset /= '1') and ( ( state_cur(316) and not ( (NOT(in0)) = '1' ) ) );
state_next(322) <= (reset /= '1') and ( state_cur(212) );
state_next(323) <= (reset /= '1') and ( ( state_cur(323) and (NOT(in0)) = '1' ) or state_cur(309) );
state_next(324) <= (reset /= '1') and ( ( state_cur(324) and (NOT(in0)) = '1' ) or state_cur(238) );
state_next(325) <= (reset /= '1') and ( state_cur(109) );
state_next(326) <= (reset /= '1') and ( state_cur(107) );
state_next(327) <= (reset /= '1') and ( ( state_cur(215) and not ( (NOT(in0)) = '1' ) ) );
state_next(328) <= (reset /= '1') and ( state_cur(219) or state_cur(125) );
state_next(329) <= (reset /= '1') and ( ( state_cur(305) and not ( (NOT(in0)) = '1' ) ) );
state_next(330) <= (reset /= '1') and ( ( state_cur(317) and not ( (NOT(in0)) = '1' ) ) );
state_next(331) <= (reset /= '1') and ( state_cur(213) );
state_next(332) <= (reset /= '1') and ( state_cur(335) );
state_next(333) <= (reset /= '1') and ( ( state_cur(150) and not ( (in3) = '1' ) ) );
state_next(334) <= (reset /= '1') and ( state_cur(96) );
state_next(335) <= (reset /= '1') and ( state_cur(182) );
state_next(336) <= (reset /= '1') and ( ( state_cur(328) and (in11) = '1' ) );
state_next(337) <= (reset /= '1') and ( rtmcmp92 );
state_next(338) <= (reset /= '1') and ( state_cur(193) );
state_next(339) <= (reset /= '1') and ( state_cur(94) );
state_next(340) <= (reset /= '1') and ( state_cur(93) );
state_next(341) <= (reset /= '1') and ( state_cur(522) );
state_next(342) <= (reset /= '1') and ( state_cur(341) );
state_next(343) <= (reset /= '1') and ( state_cur(344) or ( state_cur(343) and (NOT(in1)) = '1' ) );
state_next(344) <= (reset /= '1') and ( ( state_cur(345) and not ( (NOT(in1)) = '1' ) ) );
state_next(345) <= (reset /= '1') and ( state_cur(346) or ( state_cur(345) and (NOT(in1)) = '1' ) );
state_next(346) <= (reset /= '1') and ( ( state_cur(347) and not ( (NOT(in1)) = '1' ) ) );
state_next(347) <= (reset /= '1') and ( state_cur(348) or ( state_cur(347) and (NOT(in1)) = '1' ) );
state_next(348) <= (reset /= '1') and ( ( state_cur(349) and not ( (NOT(in1)) = '1' ) ) );
state_next(349) <= (reset /= '1') and ( state_cur(350) or ( state_cur(349) and (NOT(in1)) = '1' ) );
state_next(350) <= (reset /= '1') and ( ( state_cur(351) and not ( (NOT(in1)) = '1' ) ) );
state_next(351) <= (reset /= '1') and ( state_cur(352) or ( state_cur(351) and (NOT(in1)) = '1' ) );
state_next(352) <= (reset /= '1') and ( ( state_cur(353) and not ( (NOT(in1)) = '1' ) ) );
state_next(353) <= (reset /= '1') and ( state_cur(354) or ( state_cur(353) and (NOT(in1)) = '1' ) );
state_next(354) <= (reset /= '1') and ( ( state_cur(355) and not ( (NOT(in1)) = '1' ) ) );
state_next(355) <= (reset /= '1') and ( state_cur(356) or ( state_cur(355) and (NOT(in1)) = '1' ) );
state_next(356) <= (reset /= '1') and ( ( state_cur(357) and not ( (NOT(in1)) = '1' ) ) );
state_next(357) <= (reset /= '1') and ( state_cur(358) or ( state_cur(357) and (NOT(in1)) = '1' ) );
state_next(358) <= (reset /= '1') and ( ( state_cur(359) and not ( (NOT(in1)) = '1' ) ) );
state_next(359) <= (reset /= '1') and ( state_cur(360) or ( state_cur(359) and (NOT(in1)) = '1' ) );
state_next(360) <= (reset /= '1') and ( ( state_cur(361) and not ( (NOT(in1)) = '1' ) ) );
state_next(361) <= (reset /= '1') and ( state_cur(362) or ( state_cur(361) and (NOT(in1)) = '1' ) );
state_next(362) <= (reset /= '1') and ( ( state_cur(363) and not ( (NOT(in1)) = '1' ) ) );
state_next(363) <= (reset /= '1') and ( state_cur(364) or ( state_cur(363) and (NOT(in1)) = '1' ) );
state_next(364) <= (reset /= '1') and ( ( state_cur(365) and not ( (NOT(in1)) = '1' ) ) );
state_next(365) <= (reset /= '1') and ( state_cur(366) or ( state_cur(365) and (NOT(in1)) = '1' ) );
state_next(366) <= (reset /= '1') and ( ( state_cur(367) and not ( (NOT(in1)) = '1' ) ) );
state_next(367) <= (reset /= '1') and ( state_cur(368) or ( state_cur(367) and (NOT(in1)) = '1' ) );
state_next(368) <= (reset /= '1') and ( ( state_cur(369) and not ( (NOT(in1)) = '1' ) ) );
state_next(369) <= (reset /= '1') and ( state_cur(370) or ( state_cur(369) and (NOT(in1)) = '1' ) );
state_next(370) <= (reset /= '1') and ( ( state_cur(371) and not ( (NOT(in1)) = '1' ) ) );
state_next(371) <= (reset /= '1') and ( state_cur(372) or ( state_cur(371) and (NOT(in1)) = '1' ) );
state_next(372) <= (reset /= '1') and ( ( state_cur(373) and not ( (NOT(in1)) = '1' ) ) );
state_next(373) <= (reset /= '1') and ( state_cur(374) or ( state_cur(373) and (NOT(in1)) = '1' ) );
state_next(374) <= (reset /= '1') and ( ( state_cur(375) and not ( (NOT(in1)) = '1' ) ) );
state_next(375) <= (reset /= '1') and ( state_cur(376) or ( state_cur(375) and (NOT(in1)) = '1' ) );
state_next(376) <= (reset /= '1') and ( ( state_cur(377) and not ( (NOT(in1)) = '1' ) ) );
state_next(377) <= (reset /= '1') and ( state_cur(378) or ( state_cur(377) and (NOT(in1)) = '1' ) );
state_next(378) <= (reset /= '1') and ( ( state_cur(379) and not ( (NOT(in1)) = '1' ) ) );
state_next(379) <= (reset /= '1') and ( state_cur(380) or ( state_cur(379) and (NOT(in1)) = '1' ) );
state_next(380) <= (reset /= '1') and ( ( state_cur(381) and not ( (NOT(in1)) = '1' ) ) );
state_next(381) <= (reset /= '1') and ( state_cur(382) or ( state_cur(381) and (NOT(in1)) = '1' ) );
state_next(382) <= (reset /= '1') and ( ( state_cur(383) and not ( (NOT(in1)) = '1' ) ) );
state_next(383) <= (reset /= '1') and ( state_cur(384) or ( state_cur(383) and (NOT(in1)) = '1' ) );
state_next(384) <= (reset /= '1') and ( ( state_cur(385) and not ( (NOT(in1)) = '1' ) ) );
state_next(385) <= (reset /= '1') and ( state_cur(386) or ( state_cur(385) and (NOT(in1)) = '1' ) );
state_next(386) <= (reset /= '1') and ( ( state_cur(387) and not ( (NOT(in1)) = '1' ) ) );
state_next(387) <= (reset /= '1') and ( state_cur(388) or ( state_cur(387) and (NOT(in1)) = '1' ) );
state_next(388) <= (reset /= '1') and ( ( state_cur(389) and not ( (NOT(in1)) = '1' ) ) );
state_next(389) <= (reset /= '1') and ( state_cur(390) or ( state_cur(389) and (NOT(in1)) = '1' ) );
state_next(390) <= (reset /= '1') and ( ( state_cur(391) and not ( (NOT(in1)) = '1' ) ) );
state_next(391) <= (reset /= '1') and ( state_cur(392) or ( state_cur(391) and (NOT(in1)) = '1' ) );
state_next(392) <= (reset /= '1') and ( ( state_cur(393) and not ( (NOT(in1)) = '1' ) ) );
state_next(393) <= (reset /= '1') and ( state_cur(394) or ( state_cur(393) and (NOT(in1)) = '1' ) );
state_next(394) <= (reset /= '1') and ( ( state_cur(395) and not ( (NOT(in1)) = '1' ) ) );
state_next(395) <= (reset /= '1') and ( state_cur(396) or ( state_cur(395) and (NOT(in1)) = '1' ) );
state_next(396) <= (reset /= '1') and ( ( state_cur(397) and not ( (NOT(in1)) = '1' ) ) );
state_next(397) <= (reset /= '1') and ( state_cur(398) or ( state_cur(397) and (NOT(in1)) = '1' ) );
state_next(398) <= (reset /= '1') and ( ( state_cur(399) and not ( (NOT(in1)) = '1' ) ) );
state_next(399) <= (reset /= '1') and ( state_cur(400) or ( state_cur(399) and (NOT(in1)) = '1' ) );
state_next(400) <= (reset /= '1') and ( ( state_cur(401) and not ( (NOT(in1)) = '1' ) ) );
state_next(401) <= (reset /= '1') and ( state_cur(402) or ( state_cur(401) and (NOT(in1)) = '1' ) );
state_next(402) <= (reset /= '1') and ( ( state_cur(403) and not ( (NOT(in1)) = '1' ) ) );
state_next(403) <= (reset /= '1') and ( state_cur(404) or ( state_cur(403) and (NOT(in1)) = '1' ) );
state_next(404) <= (reset /= '1') and ( ( state_cur(405) and not ( (NOT(in1)) = '1' ) ) );
state_next(405) <= (reset /= '1') and ( state_cur(406) or ( state_cur(405) and (NOT(in1)) = '1' ) );
state_next(406) <= (reset /= '1') and ( ( state_cur(407) and not ( (NOT(in1)) = '1' ) ) );
state_next(407) <= (reset /= '1') and ( state_cur(408) or ( state_cur(407) and (NOT(in1)) = '1' ) );
state_next(408) <= (reset /= '1') and ( ( state_cur(409) and not ( (NOT(in1)) = '1' ) ) );
state_next(409) <= (reset /= '1') and ( state_cur(410) or ( state_cur(409) and (NOT(in1)) = '1' ) );
state_next(410) <= (reset /= '1') and ( ( state_cur(411) and not ( (NOT(in1)) = '1' ) ) );
state_next(411) <= (reset /= '1') and ( state_cur(412) or ( state_cur(411) and (NOT(in1)) = '1' ) );
state_next(412) <= (reset /= '1') and ( ( state_cur(413) and not ( (NOT(in1)) = '1' ) ) );
state_next(413) <= (reset /= '1') and ( state_cur(414) or ( state_cur(413) and (NOT(in1)) = '1' ) );
state_next(414) <= (reset /= '1') and ( ( state_cur(415) and not ( (NOT(in1)) = '1' ) ) );
state_next(415) <= (reset /= '1') and ( state_cur(416) or ( state_cur(415) and (NOT(in1)) = '1' ) );
state_next(416) <= (reset /= '1') and ( ( state_cur(417) and not ( (NOT(in1)) = '1' ) ) );
state_next(417) <= (reset /= '1') and ( state_cur(418) or ( state_cur(417) and (NOT(in1)) = '1' ) );
state_next(418) <= (reset /= '1') and ( ( state_cur(419) and not ( (NOT(in1)) = '1' ) ) );
state_next(419) <= (reset /= '1') and ( state_cur(420) or ( state_cur(419) and (NOT(in1)) = '1' ) );
state_next(420) <= (reset /= '1') and ( ( state_cur(421) and not ( (NOT(in1)) = '1' ) ) );
state_next(421) <= (reset /= '1') and ( state_cur(422) or ( state_cur(421) and (NOT(in1)) = '1' ) );
state_next(422) <= (reset /= '1') and ( ( state_cur(423) and not ( (NOT(in1)) = '1' ) ) );
state_next(423) <= (reset /= '1') and ( state_cur(424) or ( state_cur(423) and (NOT(in1)) = '1' ) );
state_next(424) <= (reset /= '1') and ( ( state_cur(425) and not ( (NOT(in1)) = '1' ) ) );
state_next(425) <= (reset /= '1') and ( state_cur(426) or ( state_cur(425) and (NOT(in1)) = '1' ) );
state_next(426) <= (reset /= '1') and ( ( state_cur(427) and not ( (NOT(in1)) = '1' ) ) );
state_next(427) <= (reset /= '1') and ( state_cur(428) or ( state_cur(427) and (NOT(in1)) = '1' ) );
state_next(428) <= (reset /= '1') and ( ( state_cur(429) and not ( (NOT(in1)) = '1' ) ) );
state_next(429) <= (reset /= '1') and ( state_cur(430) or ( state_cur(429) and (NOT(in1)) = '1' ) );
state_next(430) <= (reset /= '1') and ( ( state_cur(431) and not ( (NOT(in1)) = '1' ) ) );
state_next(431) <= (reset /= '1') and ( state_cur(432) or ( state_cur(431) and (NOT(in1)) = '1' ) );
state_next(432) <= (reset /= '1') and ( ( state_cur(433) and not ( (NOT(in1)) = '1' ) ) );
state_next(433) <= (reset /= '1') and ( state_cur(434) or ( state_cur(433) and (NOT(in1)) = '1' ) );
state_next(434) <= (reset /= '1') and ( ( state_cur(435) and not ( (NOT(in1)) = '1' ) ) );
state_next(435) <= (reset /= '1') and ( state_cur(436) or ( state_cur(435) and (NOT(in1)) = '1' ) );
state_next(436) <= (reset /= '1') and ( ( state_cur(437) and not ( (NOT(in1)) = '1' ) ) );
state_next(437) <= (reset /= '1') and ( state_cur(438) or ( state_cur(437) and (NOT(in1)) = '1' ) );
state_next(438) <= (reset /= '1') and ( ( state_cur(439) and not ( (NOT(in1)) = '1' ) ) );
state_next(439) <= (reset /= '1') and ( state_cur(440) or ( state_cur(439) and (NOT(in1)) = '1' ) );
state_next(440) <= (reset /= '1') and ( ( state_cur(441) and not ( (NOT(in1)) = '1' ) ) );
state_next(441) <= (reset /= '1') and ( state_cur(442) or ( state_cur(441) and (NOT(in1)) = '1' ) );
state_next(442) <= (reset /= '1') and ( ( state_cur(443) and not ( (NOT(in1)) = '1' ) ) );
state_next(443) <= (reset /= '1') and ( state_cur(444) or ( state_cur(443) and (NOT(in1)) = '1' ) );
state_next(444) <= (reset /= '1') and ( ( state_cur(445) and not ( (NOT(in1)) = '1' ) ) );
state_next(445) <= (reset /= '1') and ( state_cur(446) or ( state_cur(445) and (NOT(in1)) = '1' ) );
state_next(446) <= (reset /= '1') and ( ( state_cur(447) and not ( (NOT(in1)) = '1' ) ) );
state_next(447) <= (reset /= '1') and ( state_cur(448) or ( state_cur(447) and (NOT(in1)) = '1' ) );
state_next(448) <= (reset /= '1') and ( ( state_cur(449) and not ( (NOT(in1)) = '1' ) ) );
state_next(449) <= (reset /= '1') and ( state_cur(450) or ( state_cur(449) and (NOT(in1)) = '1' ) );
state_next(450) <= (reset /= '1') and ( ( state_cur(451) and not ( (NOT(in1)) = '1' ) ) );
state_next(451) <= (reset /= '1') and ( state_cur(452) or ( state_cur(451) and (NOT(in1)) = '1' ) );
state_next(452) <= (reset /= '1') and ( ( state_cur(453) and not ( (NOT(in1)) = '1' ) ) );
state_next(453) <= (reset /= '1') and ( state_cur(454) or ( state_cur(453) and (NOT(in1)) = '1' ) );
state_next(454) <= (reset /= '1') and ( ( state_cur(455) and not ( (NOT(in1)) = '1' ) ) );
state_next(455) <= (reset /= '1') and ( state_cur(456) or ( state_cur(455) and (NOT(in1)) = '1' ) );
state_next(456) <= (reset /= '1') and ( ( state_cur(457) and not ( (NOT(in1)) = '1' ) ) );
state_next(457) <= (reset /= '1') and ( state_cur(458) or ( state_cur(457) and (NOT(in1)) = '1' ) );
state_next(458) <= (reset /= '1') and ( ( state_cur(459) and not ( (NOT(in1)) = '1' ) ) );
state_next(459) <= (reset /= '1') and ( state_cur(460) or ( state_cur(459) and (NOT(in1)) = '1' ) );
state_next(460) <= (reset /= '1') and ( ( state_cur(461) and not ( (NOT(in1)) = '1' ) ) );
state_next(461) <= (reset /= '1') and ( state_cur(462) or ( state_cur(461) and (NOT(in1)) = '1' ) );
state_next(462) <= (reset /= '1') and ( ( state_cur(463) and not ( (NOT(in1)) = '1' ) ) );
state_next(463) <= (reset /= '1') and ( state_cur(464) or ( state_cur(463) and (NOT(in1)) = '1' ) );
state_next(464) <= (reset /= '1') and ( ( state_cur(465) and not ( (NOT(in1)) = '1' ) ) );
state_next(465) <= (reset /= '1') and ( state_cur(466) or ( state_cur(465) and (NOT(in1)) = '1' ) );
state_next(466) <= (reset /= '1') and ( ( state_cur(467) and not ( (NOT(in1)) = '1' ) ) );
state_next(467) <= (reset /= '1') and ( state_cur(468) or ( state_cur(467) and (NOT(in1)) = '1' ) );
state_next(468) <= (reset /= '1') and ( ( state_cur(469) and not ( (NOT(in1)) = '1' ) ) );
state_next(469) <= (reset /= '1') and ( state_cur(470) or ( state_cur(469) and (NOT(in1)) = '1' ) );
state_next(470) <= (reset /= '1') and ( ( state_cur(471) and not ( (NOT(in1)) = '1' ) ) );
state_next(471) <= (reset /= '1') and ( state_cur(472) or ( state_cur(471) and (NOT(in1)) = '1' ) );
state_next(472) <= (reset /= '1') and ( ( state_cur(473) and not ( (NOT(in1)) = '1' ) ) );
state_next(473) <= (reset /= '1') and ( state_cur(474) or ( state_cur(473) and (NOT(in1)) = '1' ) );
state_next(474) <= (reset /= '1') and ( ( state_cur(475) and not ( (NOT(in1)) = '1' ) ) );
state_next(475) <= (reset /= '1') and ( state_cur(476) or ( state_cur(475) and (NOT(in1)) = '1' ) );
state_next(476) <= (reset /= '1') and ( ( state_cur(477) and not ( (NOT(in1)) = '1' ) ) );
state_next(477) <= (reset /= '1') and ( state_cur(478) or ( state_cur(477) and (NOT(in1)) = '1' ) );
state_next(478) <= (reset /= '1') and ( ( state_cur(479) and not ( (NOT(in1)) = '1' ) ) );
state_next(479) <= (reset /= '1') and ( state_cur(480) or ( state_cur(479) and (NOT(in1)) = '1' ) );
state_next(480) <= (reset /= '1') and ( ( state_cur(481) and not ( (NOT(in1)) = '1' ) ) );
state_next(481) <= (reset /= '1') and ( state_cur(482) or ( state_cur(481) and (NOT(in1)) = '1' ) );
state_next(482) <= (reset /= '1') and ( ( state_cur(483) and not ( (NOT(in1)) = '1' ) ) );
state_next(483) <= (reset /= '1') and ( state_cur(484) or ( state_cur(483) and (NOT(in1)) = '1' ) );
state_next(484) <= (reset /= '1') and ( ( state_cur(485) and not ( (NOT(in1)) = '1' ) ) );
state_next(485) <= (reset /= '1') and ( state_cur(486) or ( state_cur(485) and (NOT(in1)) = '1' ) );
state_next(486) <= (reset /= '1') and ( ( state_cur(487) and not ( (NOT(in1)) = '1' ) ) );
state_next(487) <= (reset /= '1') and ( state_cur(488) or ( state_cur(487) and (NOT(in1)) = '1' ) );
state_next(488) <= (reset /= '1') and ( ( state_cur(489) and not ( (NOT(in1)) = '1' ) ) );
state_next(489) <= (reset /= '1') and ( state_cur(490) or ( state_cur(489) and (NOT(in1)) = '1' ) );
state_next(490) <= (reset /= '1') and ( ( state_cur(491) and not ( (NOT(in1)) = '1' ) ) );
state_next(491) <= (reset /= '1') and ( state_cur(492) or ( state_cur(491) and (NOT(in1)) = '1' ) );
state_next(492) <= (reset /= '1') and ( ( state_cur(493) and not ( (NOT(in1)) = '1' ) ) );
state_next(493) <= (reset /= '1') and ( state_cur(494) or ( state_cur(493) and (NOT(in1)) = '1' ) );
state_next(494) <= (reset /= '1') and ( ( state_cur(495) and not ( (NOT(in1)) = '1' ) ) );
state_next(495) <= (reset /= '1') and ( state_cur(496) or ( state_cur(495) and (NOT(in1)) = '1' ) );
state_next(496) <= (reset /= '1') and ( ( state_cur(497) and not ( (NOT(in1)) = '1' ) ) );
state_next(497) <= (reset /= '1') and ( state_cur(498) or ( state_cur(497) and (NOT(in1)) = '1' ) );
state_next(498) <= (reset /= '1') and ( ( state_cur(499) and not ( (NOT(in1)) = '1' ) ) );
state_next(499) <= (reset /= '1') and ( state_cur(500) or ( state_cur(499) and (NOT(in1)) = '1' ) );
state_next(500) <= (reset /= '1') and ( ( state_cur(501) and not ( (NOT(in1)) = '1' ) ) );
state_next(501) <= (reset /= '1') and ( state_cur(502) or ( state_cur(501) and (NOT(in1)) = '1' ) );
state_next(502) <= (reset /= '1') and ( ( state_cur(503) and not ( (NOT(in1)) = '1' ) ) );
state_next(503) <= (reset /= '1') and ( state_cur(504) or ( state_cur(503) and (NOT(in1)) = '1' ) );
state_next(504) <= (reset /= '1') and ( ( state_cur(505) and not ( (NOT(in1)) = '1' ) ) );
state_next(505) <= (reset /= '1') and ( state_cur(506) or ( state_cur(505) and (NOT(in1)) = '1' ) );
state_next(506) <= (reset /= '1') and ( ( state_cur(507) and not ( (NOT(in1)) = '1' ) ) );
state_next(507) <= (reset /= '1') and ( state_cur(508) or ( state_cur(507) and (NOT(in1)) = '1' ) );
state_next(508) <= (reset /= '1') and ( ( state_cur(509) and not ( (NOT(in1)) = '1' ) ) );
state_next(509) <= (reset /= '1') and ( state_cur(510) or ( state_cur(509) and (NOT(in1)) = '1' ) );
state_next(510) <= (reset /= '1') and ( ( state_cur(511) and not ( (NOT(in1)) = '1' ) ) );
state_next(511) <= (reset /= '1') and ( state_cur(512) or ( state_cur(511) and (NOT(in1)) = '1' ) );
state_next(512) <= (reset /= '1') and ( ( state_cur(513) and not ( (NOT(in1)) = '1' ) ) );
state_next(513) <= (reset /= '1') and ( state_cur(514) or ( state_cur(513) and (NOT(in1)) = '1' ) );
state_next(514) <= (reset /= '1') and ( ( state_cur(515) and not ( (NOT(in1)) = '1' ) ) );
state_next(515) <= (reset /= '1') and ( state_cur(516) or ( state_cur(515) and (NOT(in1)) = '1' ) );
state_next(516) <= (reset /= '1') and ( ( state_cur(517) and not ( (NOT(in1)) = '1' ) ) );
state_next(517) <= (reset /= '1') and ( state_cur(518) or ( state_cur(517) and (NOT(in1)) = '1' ) );
state_next(518) <= (reset /= '1') and ( ( state_cur(519) and not ( (NOT(in1)) = '1' ) ) );
state_next(519) <= (reset /= '1') and ( ( state_cur(519) and (NOT(in1)) = '1' ) or state_cur(1) );
state_next(520) <= (reset /= '1') and ( ( state_cur(520) and (NOT(in1)) = '1' ) or state_cur(73) );
state_next(521) <= (reset /= '1') and ( ( state_cur(521) and (NOT(in1)) = '1' ) or state_cur(71) );
state_next(522) <= (reset /= '1') and ( ( state_cur(220) and not ( (in6) = '1' ) ) );
state_next(523) <= (reset /= '1') and ( state_cur(149) );
-- Assignment of buffers for buffered outputs
out386_bufn <= state_cur(186) or state_cur(270);
out404_bufn <= (state_cur(290) = '1' and rtmcmp290 = '0') or state_cur(291) or state_cur(173);
out457_bufn <= state_cur(142) or state_cur(190) or state_cur(169);
out841_bufn <= rtmcmp92 or state_cur(189);
out276_bufn <= state_cur(233) or state_cur(274);
out67_bufn <= state_cur(189) or state_cur(282) or state_cur(98) or state_cur(203) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) or state_cur(337);
out239_bufn <= ( state_cur(240) and (in7) = '1' ) or state_cur(523) or state_cur(129);
out259_bufn <= state_cur(268) or state_cur(178) or ( state_cur(220) and (in6) = '1' ) or ( state_cur(150) and (in3) = '1' ) or ( state_cur(175) and (in4) = '1' ) or ( state_cur(208) and (in5) = '1' ) or state_cur(523) or state_cur(129);
out416_bufn <= state_cur(338) or state_cur(143) or state_cur(289) or state_cur(322);
out646_bufn <= state_cur(340) or state_cur(326);
out485_bufn <= ( state_cur(240) and (in7) = '1' ) or ( state_cur(150) and (in3) = '1' );
out935_bufn <= state_cur(193) or state_cur(134);
out463_bufn <= state_cur(338) or state_cur(119) or state_cur(134) or state_cur(233) or state_cur(174);
out120_bufn <= rtmcmp92 or state_cur(100) or state_cur(91) or state_cur(179) or state_cur(228);
out293_bufn <= state_cur(342) or state_cur(303);
out216_bufn <= state_cur(107) or state_cur(212) or rtmcmp128 or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114) or state_cur(326) or state_cur(123) or state_cur(190) or state_cur(186) or rtmcmp290 or state_cur(204) or state_cur(191) or state_cur(303) or rtmcmp276;
out319_bufn <= (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114) or state_cur(99) or state_cur(218) or (state_cur(128) = '1' and rtmcmp128 = '0') or state_cur(296);
out230_bufn <= ( state_cur(220) and (in6) = '1' ) or state_cur(224);
out1_bufn <= ( state_cur(317) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(305) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(215) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(316) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(121) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(84) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(122) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(192) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(194) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(295) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(313) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(264) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(10) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(67) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(75) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(28) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(243) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(87) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(124) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(240) and not ( (in7) = '1' ) ) or ( state_cur(269) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(50) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(64) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(68) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(49) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(171) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(130) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(77) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(302) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(287) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(176) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(216) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(250) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(202) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(318) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(136) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(211) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(120) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(135) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(226) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(279) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(55) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(167) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(165) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(163) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(161) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(159) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(157) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(155) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(101) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(116) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(118) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(127) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(314) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(304) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(112) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(140) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(288) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(217) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(80) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(272) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(297) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(278) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(258) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(256) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(24) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(65) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(246) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(61) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(12) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(104) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(21) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(51) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(52) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(46) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(37) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(41) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(285) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(323) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(35) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(34) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(259) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(33) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(324) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(320) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(117) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(26) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(27) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(14) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(239) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(188) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(263) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(13) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(17) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(207) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(6) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(48) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(201) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(44) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(90) and not ( (NOT(in0)) = '1' ) );
out93_bufn <= state_cur(522) or state_cur(93) or state_cur(96) or state_cur(108) or ( state_cur(220) and (in6) = '1' ) or state_cur(342) or state_cur(340) or state_cur(95) or state_cur(184) or ( state_cur(150) and (in3) = '1' ) or state_cur(187) or ( state_cur(175) and (in4) = '1' ) or ( state_cur(208) and (in5) = '1' ) or state_cur(334) or state_cur(339);
out89_bufn <= state_cur(149) or state_cur(341) or state_cur(522) or state_cur(93) or state_cur(94) or state_cur(96) or state_cur(213) or state_cur(108) or state_cur(281) or state_cur(103) or state_cur(342) or state_cur(340) or state_cur(95) or state_cur(184) or state_cur(183) or state_cur(280) or state_cur(187) or state_cur(331) or state_cur(224) or state_cur(301) or state_cur(200) or state_cur(333) or state_cur(334) or state_cur(339);
out539_bufn <= state_cur(142) or state_cur(190);
out62_bufn <= state_cur(193) or rtmcmp92 or state_cur(107) or state_cur(212) or state_cur(338) or state_cur(119) or rtmcmp128 or state_cur(100) or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114) or state_cur(134) or state_cur(236) or state_cur(189) or state_cur(326) or state_cur(312) or state_cur(123) or state_cur(91) or state_cur(233) or state_cur(190) or state_cur(186) or state_cur(179) or rtmcmp290 or state_cur(282) or state_cur(319) or state_cur(174) or state_cur(204) or state_cur(172) or state_cur(191) or state_cur(303) or state_cur(274) or rtmcmp276 or state_cur(98) or state_cur(203) or state_cur(228) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) or state_cur(337);
out856_bufn <= state_cur(107) or state_cur(147) or state_cur(236);
out451_bufn <= state_cur(123) or state_cur(169);
out287_bufn <= state_cur(332) or state_cur(303);
out315_bufn <= state_cur(268) or state_cur(178) or (state_cur(128) = '1' and rtmcmp128 = '0') or state_cur(296);
out536_bufn <= state_cur(95) or state_cur(190);
out209_bufn <= state_cur(191) or state_cur(200);
out221_bufn <= rtmcmp128 or state_cur(237) or state_cur(197) or rtmcmp276;
out283_bufn <= state_cur(193) or state_cur(236) or state_cur(312) or state_cur(319) or state_cur(172) or state_cur(274);
out368_bufn <= state_cur(213) or ( state_cur(175) and (in4) = '1' );
out516_bufn <= ( state_cur(208) and not ( (in5) = '1' ) ) or state_cur(281) or state_cur(183) or state_cur(280);
out393_bufn <= state_cur(193) or state_cur(212) or state_cur(338) or state_cur(143) or state_cur(210) or state_cur(289) or state_cur(322) or state_cur(204);
out1008_bufn <= state_cur(182) or state_cur(268) or state_cur(178);
out392_bufn <= state_cur(108) or state_cur(204);
out261_bufn <= state_cur(268) or state_cur(178) or state_cur(523) or state_cur(129);
out559_bufn <= state_cur(99) or state_cur(218);
out543_bufn <= state_cur(326) or state_cur(292) or state_cur(123) or state_cur(233);
out895_bufn <= state_cur(219) or state_cur(125) or state_cur(247) or state_cur(242) or state_cur(241) or state_cur(148);
out82_bufn <= ( state_cur(208) and (in5) = '1' ) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336);
out220_bufn <= state_cur(107) or rtmcmp128 or state_cur(147) or state_cur(237) or state_cur(236) or state_cur(197) or rtmcmp276;
out95_bufn <= state_cur(522) or state_cur(93) or state_cur(96) or state_cur(108) or state_cur(342) or state_cur(340) or state_cur(95) or state_cur(184) or state_cur(187) or state_cur(334) or state_cur(339);
out943_bufn <= (state_cur(290) = '1' and rtmcmp290 = '0') or state_cur(291) or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114);
out465_bufn <= state_cur(319) or state_cur(174);
out238_bufn <= ( state_cur(175) and (in4) = '1' ) or state_cur(523) or state_cur(129);
out1025_bufn <= ( state_cur(328) and (in11) = '1' ) or state_cur(268) or state_cur(178);
out132_bufn <= state_cur(146) or state_cur(138) or state_cur(273) or state_cur(105);
out79_bufn <= ( state_cur(328) and (in11) = '1' ) or state_cur(98) or state_cur(228) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336);
out500_bufn <= state_cur(91) or state_cur(282);
out65_bufn <= state_cur(179) or state_cur(337);
out111_bufn <= state_cur(96) or state_cur(95) or state_cur(334);
out420_bufn <= ( state_cur(328) and (in11) = '1' ) or state_cur(306);
out1076_bufn <= state_cur(93) or state_cur(107);
out101_bufn <= state_cur(523) or state_cur(129) or ( state_cur(175) and not ( (in4) = '1' ) );
out106_bufn <= ( state_cur(220) and not ( (in6) = '1' ) ) or state_cur(341) or state_cur(94) or ( state_cur(150) and not ( (in3) = '1' ) ) or state_cur(213) or ( state_cur(208) and not ( (in5) = '1' ) ) or state_cur(281) or state_cur(183) or state_cur(280) or state_cur(224) or state_cur(200) or state_cur(333) or ( state_cur(175) and not ( (in4) = '1' ) );
out68_bufn <= state_cur(193) or rtmcmp92 or state_cur(338) or state_cur(119) or state_cur(100) or state_cur(134) or state_cur(236) or state_cur(189) or state_cur(312) or state_cur(91) or state_cur(233) or state_cur(179) or state_cur(282) or state_cur(319) or state_cur(174) or state_cur(172) or state_cur(274) or state_cur(98) or state_cur(203) or state_cur(228) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) or state_cur(337);
out1069_bufn <= state_cur(213) or state_cur(212);
out77_bufn <= state_cur(228) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336);
out102_bufn <= state_cur(94) or state_cur(213) or ( state_cur(175) and not ( (in4) = '1' ) );
out394_bufn <= state_cur(193) or state_cur(212) or state_cur(210) or state_cur(204);
out342_bufn <= ( state_cur(220) and (in6) = '1' ) or ( state_cur(150) and (in3) = '1' ) or ( state_cur(175) and (in4) = '1' ) or ( state_cur(208) and (in5) = '1' );
out104_bufn <= ( state_cur(220) and not ( (in6) = '1' ) ) or state_cur(341) or state_cur(94) or ( state_cur(150) and not ( (in3) = '1' ) ) or state_cur(213) or ( state_cur(208) and not ( (in5) = '1' ) ) or state_cur(281) or ( state_cur(220) and (in6) = '1' ) or state_cur(146) or state_cur(138) or state_cur(183) or state_cur(280) or ( state_cur(150) and (in3) = '1' ) or ( state_cur(175) and (in4) = '1' ) or ( state_cur(208) and (in5) = '1' ) or state_cur(224) or state_cur(200) or state_cur(273) or state_cur(105) or state_cur(333) or ( state_cur(175) and not ( (in4) = '1' ) );
out361_bufn <= state_cur(338) or state_cur(172);
out116_bufn <= ( state_cur(150) and not ( (in3) = '1' ) ) or state_cur(200) or state_cur(333);
out595_bufn <= state_cur(119) or state_cur(237) or state_cur(236) or state_cur(312);
out1004_bufn <= state_cur(143) or state_cur(132);
out227_bufn <= state_cur(123) or state_cur(224);
out109_bufn <= state_cur(186) or state_cur(334);
out619_bufn <= state_cur(237) or state_cur(312);
out410_bufn <= state_cur(335) or state_cur(143) or state_cur(132) or state_cur(322);
out989_bufn <= ( state_cur(150) and not ( (in3) = '1' ) ) or ( state_cur(240) and (in7) = '1' );
out431_bufn <= state_cur(184) or state_cur(187);
out938_bufn <= state_cur(94) or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114);
out525_bufn <= state_cur(96) or rtmcmp290;
out73_bufn <= rtmcmp92 or (state_cur(290) = '1' and rtmcmp290 = '0') or state_cur(291) or state_cur(91) or state_cur(203) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) or state_cur(337);
out837_bufn <= state_cur(522) or state_cur(108) or state_cur(342);
out860_bufn <= state_cur(119) or state_cur(236);
out228_bufn <= ( state_cur(220) and not ( (in6) = '1' ) ) or state_cur(341) or state_cur(224);
out421_bufn <= ( state_cur(328) and (in11) = '1' ) or ( state_cur(325) and not ( (in10) = '1' ) ) or ( state_cur(97) and not ( (NOT(in0)) = '1' ) ) or state_cur(306);
out409_bufn <= state_cur(132) or state_cur(322);
out473_bufn <= state_cur(99) or state_cur(218) or ( state_cur(325) and (in10) = '1' ) or ( state_cur(310) and not ( (in9) = '1' ) );
out509_bufn <= state_cur(123) or state_cur(223);
out94_bufn <= rtmcmp276 or state_cur(339);
out1048_bufn <= state_cur(341) or rtmcmp128;
out98_bufn <= state_cur(93) or state_cur(340) or state_cur(339);
out945_bufn <= ( state_cur(240) and (in7) = '1' ) or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114);
out156_bufn <= ( state_cur(328) and (in11) = '1' ) or state_cur(98);
out152_bufn <= state_cur(100) or state_cur(203);
-- Assignment of non-buffered outputs
out80 <=
state_cur(92);
out576 <=
state_cur(200);
out1103 <=
state_cur(336);
out438 <=
state_cur(151);
out171 <=
state_cur(222) or state_cur(102);
out378 <=
state_cur(340) or state_cur(222) or state_cur(138);
out940 <=
state_cur(276);
out131 <=
state_cur(99);
out376 <=
state_cur(138);
out891 <=
state_cur(237);
out611 <=
state_cur(209);
out638 <=
state_cur(222) or state_cur(209);
out354 <=
state_cur(129);
out7 <=
state_cur(3);
out1127 <=
state_cur(339);
out888 <=
state_cur(237);
out1141 <=
state_cur(348);
out6 <=
state_cur(2);
out1200 <=
state_cur(466);
out1148 <=
state_cur(362);
out250 <=
state_cur(114);
out1100 <=
state_cur(335);
out1168 <=
state_cur(402);
out1158 <=
state_cur(382);
out581 <=
state_cur(204);
out549 <=
state_cur(222) or state_cur(193);
out412 <=
state_cur(145);
out381 <=
state_cur(222) or state_cur(213) or state_cur(138);
out38 <=
state_cur(56);
out100 <=
state_cur(522) or state_cur(342) or state_cur(341) or state_cur(340) or state_cur(339) or state_cur(334) or state_cur(333) or state_cur(331) or
state_cur(301) or state_cur(281) or state_cur(280) or state_cur(224) or state_cur(213) or state_cur(200) or state_cur(187) or state_cur(184) or
state_cur(183) or state_cur(149) or state_cur(108) or state_cur(103) or state_cur(96) or state_cur(95) or state_cur(94) or state_cur(93);
out1181 <=
state_cur(428);
out22 <=
state_cur(20);
out56 <=
state_cur(85);
out224 <=
state_cur(326) or state_cur(303) or state_cur(292) or rtmcmp276 or state_cur(237) or state_cur(236) or state_cur(233) or state_cur(197) or
state_cur(147) or rtmcmp128 or state_cur(123) or state_cur(107);
out1115 <=
state_cur(336);
out191 <=
state_cur(102);
out290 <=
state_cur(123);
out1226 <=
state_cur(518);
out921 <=
state_cur(271);
out535 <=
state_cur(191);
out489 <=
state_cur(178);
out13 <=
state_cur(8);
out1161 <=
state_cur(388);
out408 <=
state_cur(144);
out1197 <=
state_cur(460);
out521 <=
state_cur(184);
out128 <=
state_cur(296) or state_cur(218) or state_cur(114) or state_cur(99);
out440 <=
state_cur(154);
out330 <=
state_cur(128);
out1003 <=
state_cur(294);
out1145 <=
state_cur(356);
out1156 <=
state_cur(378);
out497 <=
state_cur(268) or state_cur(222) or state_cur(178);
out52 <=
state_cur(79);
out659 <=
state_cur(218);
out566 <=
state_cur(197);
out850 <=
state_cur(231);
out1123 <=
state_cur(338);
out558 <=
state_cur(197);
out902 <=
state_cur(248);
out1217 <=
state_cur(500);
out357 <=
state_cur(132);
out229 <=
state_cur(108);
out1096 <=
state_cur(335);
out1188 <=
state_cur(442);
out39 <=
state_cur(57);
out118 <=
state_cur(96);
out387 <=
state_cur(142);
out514 <=
state_cur(183);
out425 <=
state_cur(148);
out508 <=
state_cur(182);
out1155 <=
state_cur(376);
out877 <=
state_cur(236);
out844 <=
state_cur(228);
out237 <=
state_cur(113);
out1133 <=
state_cur(341);
out1046 <=
state_cur(301);
out365 <=
state_cur(137);
out858 <=
state_cur(233);
out873 <=
state_cur(235);
out909 <=
state_cur(260);
out846 <=
state_cur(230);
out484 <=
state_cur(177);
out836 <=
state_cur(224);
out898 <=
state_cur(242);
out1196 <=
state_cur(458);
out26 <=
state_cur(30);
out1147 <=
state_cur(360);
out744 <=
state_cur(342) or state_cur(273) or state_cur(222);
out1026 <=
state_cur(296);
out430 <=
state_cur(149);
out962 <=
state_cur(281);
out45 <=
state_cur(66);
out9 <=
state_cur(5);
out1002 <=
state_cur(294);
out1139 <=
state_cur(344);
out1143 <=
state_cur(352);
out1173 <=
state_cur(412);
out28 <=
state_cur(32);
out1092 <=
state_cur(334);
out1140 <=
state_cur(346);
out40 <=
state_cur(58);
out119 <=
state_cur(98);
out382 <=
state_cur(139);
out241 <=
state_cur(114);
out91 <=
state_cur(93);
out920 <=
state_cur(270);
out986 <=
state_cur(290);
out657 <=
state_cur(222) or state_cur(218);
out375 <=
state_cur(331) or state_cur(222) or state_cur(138);
out866 <=
state_cur(235);
out577 <=
state_cur(203);
out1159 <=
state_cur(384);
out236 <=
state_cur(111);
out367 <=
state_cur(339) or state_cur(222) or state_cur(138);
out1130 <=
state_cur(340);
out25 <=
state_cur(25);
out258 <=
state_cur(222) or state_cur(114);
out990 <=
state_cur(291);
out900 <=
state_cur(244);
out748 <=
state_cur(273) or state_cur(224) or state_cur(222);
out1219 <=
state_cur(504);
out552 <=
state_cur(196);
out852 <=
state_cur(232);
out644 <=
state_cur(222) or state_cur(210);
out4 <=
state_cur(1);
out1142 <=
state_cur(350);
out1089 <=
state_cur(333);
out937 <=
state_cur(275);
out291 <=
state_cur(335) or state_cur(332) or state_cur(303) or state_cur(169) or rtmcmp128 or state_cur(123);
out482 <=
state_cur(222) or state_cur(175);
out924 <=
state_cur(273);
out1218 <=
state_cur(502);
out590 <=
state_cur(205);
out20 <=
state_cur(18);
out114 <=
state_cur(222) or state_cur(178) or state_cur(96);
out30 <=
state_cur(38);
out1224 <=
state_cur(514);
out107 <=
state_cur(95);
out915 <=
state_cur(268);
out34 <=
state_cur(45);
out1213 <=
state_cur(492);
out33 <=
state_cur(43);
out530 <=
state_cur(187);
out1191 <=
state_cur(448);
out223 <=
state_cur(107);
out834 <=
state_cur(231) or state_cur(223);
out1038 <=
state_cur(298);
out454 <=
state_cur(170);
out1087 <=
state_cur(332);
out233 <=
state_cur(109);
out66 <=
state_cur(91);
out347 <=
state_cur(222) or state_cur(149) or state_cur(129);
out848 <=
state_cur(231);
out746 <=
state_cur(301) or state_cur(273) or state_cur(222);
out695 <=
state_cur(232) or state_cur(222);
out1203 <=
state_cur(472);
out1085 <=
state_cur(332);
out1157 <=
state_cur(380);
out1039 <=
state_cur(298);
out532 <=
state_cur(189);
out1138 <=
state_cur(342);
out441 <=
state_cur(156);
out845 <=
state_cur(229);
out48 <=
state_cur(71);
out593 <=
state_cur(222) or state_cur(208);
out1182 <=
state_cur(430);
out57 <=
state_cur(88);
out44 <=
state_cur(63);
out1183 <=
state_cur(432);
out29 <=
state_cur(36);
out1015 <=
state_cur(296);
out910 <=
state_cur(261);
out524 <=
state_cur(186);
out958 <=
state_cur(280);
out460 <=
state_cur(300) or state_cur(204) or state_cur(191) or state_cur(170);
out50 <=
state_cur(74);
out304 <=
state_cur(126);
out130 <=
state_cur(222) or state_cur(99);
out833 <=
state_cur(223);
out513 <=
rtmcmp290 or state_cur(223) or state_cur(182);
out1210 <=
state_cur(486);
out370 <=
state_cur(222) or state_cur(146) or state_cur(138);
out481 <=
state_cur(175);
out207 <=
state_cur(103);
out445 <=
state_cur(164);
out362 <=
state_cur(134);
out908 <=
state_cur(257);
out1186 <=
state_cur(438);
out466 <=
state_cur(172);
out1083 <=
state_cur(331);
out475 <=
state_cur(173);
out19 <=
state_cur(16);
out645 <=
state_cur(212);
out582 <=
state_cur(222) or state_cur(204);
out547 <=
state_cur(193);
out1154 <=
state_cur(374);
out854 <=
state_cur(232);
out208 <=
state_cur(222) or state_cur(178) or state_cur(103);
out975 <=
state_cur(286);
out1150 <=
state_cur(366);
out503 <=
state_cur(179);
out650 <=
state_cur(213);
out863 <=
state_cur(234);
out1211 <=
state_cur(488);
out1228 <=
state_cur(522);
out5 <=
state_cur(518) or state_cur(516) or state_cur(514) or state_cur(512) or state_cur(510) or state_cur(508) or state_cur(506) or state_cur(504) or
state_cur(502) or state_cur(500) or state_cur(498) or state_cur(496) or state_cur(494) or state_cur(492) or state_cur(490) or state_cur(488) or
state_cur(486) or state_cur(484) or state_cur(482) or state_cur(480) or state_cur(478) or state_cur(476) or state_cur(474) or state_cur(472) or
state_cur(470) or state_cur(468) or state_cur(466) or state_cur(464) or state_cur(462) or state_cur(460) or state_cur(458) or state_cur(456) or
state_cur(454) or state_cur(452) or state_cur(450) or state_cur(448) or state_cur(446) or state_cur(444) or state_cur(442) or state_cur(440) or
state_cur(438) or state_cur(436) or state_cur(434) or state_cur(432) or state_cur(430) or state_cur(428) or state_cur(426) or state_cur(424) or
state_cur(422) or state_cur(420) or state_cur(418) or state_cur(416) or state_cur(414) or state_cur(412) or state_cur(410) or state_cur(408) or
state_cur(406) or state_cur(404) or state_cur(402) or state_cur(400) or state_cur(398) or state_cur(396) or state_cur(394) or state_cur(392) or
state_cur(390) or state_cur(388) or state_cur(386) or state_cur(384) or state_cur(382) or state_cur(380) or state_cur(378) or state_cur(376) or
state_cur(374) or state_cur(372) or state_cur(370) or state_cur(368) or state_cur(366) or state_cur(364) or state_cur(362) or state_cur(360) or
state_cur(358) or state_cur(356) or state_cur(354) or state_cur(352) or state_cur(350) or state_cur(348) or state_cur(346) or state_cur(344) or
state_cur(214) or state_cur(198) or state_cur(195) or state_cur(180) or state_cur(125) or state_cur(115) or state_cur(85) or state_cur(83) or
state_cur(79) or state_cur(73) or state_cur(71) or state_cur(1);
out1081 <=
state_cur(330);
out980 <=
rtmcmp290;
out533 <=
state_cur(190);
out338 <=
state_cur(280) or state_cur(222) or state_cur(129);
out32 <=
state_cur(40);
out1080 <=
state_cur(329);
out27 <=
state_cur(31);
out893 <=
state_cur(238);
out397 <=
state_cur(143);
out1000 <=
state_cur(293);
out55 <=
state_cur(83);
out235 <=
state_cur(109);
out1198 <=
state_cur(462);
out12 <=
state_cur(7);
out1221 <=
state_cur(508);
out277 <=
state_cur(119);
out1205 <=
state_cur(476);
out321 <=
state_cur(338) or state_cur(322) or state_cur(319) or state_cur(298) or state_cur(289) or rtmcmp276 or state_cur(237) or state_cur(197) or
state_cur(151) or state_cur(145) or state_cur(143) or rtmcmp128;
out1216 <=
state_cur(498);
out999 <=
state_cur(292);
out1190 <=
state_cur(446);
out1078 <=
state_cur(327);
out17 <=
state_cur(521) or state_cur(520) or state_cur(519) or state_cur(517) or state_cur(515) or state_cur(513) or state_cur(511) or state_cur(509) or
state_cur(507) or state_cur(505) or state_cur(503) or state_cur(501) or state_cur(499) or state_cur(497) or state_cur(495) or state_cur(493) or
state_cur(491) or state_cur(489) or state_cur(487) or state_cur(485) or state_cur(483) or state_cur(481) or state_cur(479) or state_cur(477) or
state_cur(475) or state_cur(473) or state_cur(471) or state_cur(469) or state_cur(467) or state_cur(465) or state_cur(463) or state_cur(461) or
state_cur(459) or state_cur(457) or state_cur(455) or state_cur(453) or state_cur(451) or state_cur(449) or state_cur(447) or state_cur(445) or
state_cur(443) or state_cur(441) or state_cur(439) or state_cur(437) or state_cur(435) or state_cur(433) or state_cur(431) or state_cur(429) or
state_cur(427) or state_cur(425) or state_cur(423) or state_cur(421) or state_cur(419) or state_cur(417) or state_cur(415) or state_cur(413) or
state_cur(411) or state_cur(409) or state_cur(407) or state_cur(405) or state_cur(403) or state_cur(401) or state_cur(399) or state_cur(397) or
state_cur(395) or state_cur(393) or state_cur(391) or state_cur(389) or state_cur(387) or state_cur(385) or state_cur(383) or state_cur(381) or
state_cur(379) or state_cur(377) or state_cur(375) or state_cur(373) or state_cur(371) or state_cur(369) or state_cur(367) or state_cur(365) or
state_cur(363) or state_cur(361) or state_cur(359) or state_cur(357) or state_cur(355) or state_cur(353) or state_cur(351) or state_cur(349) or
state_cur(347) or state_cur(345) or state_cur(343) or state_cur(255) or state_cur(110) or state_cur(106) or state_cur(86) or state_cur(78) or
state_cur(72) or state_cur(42) or state_cur(29) or state_cur(11);
out1209 <=
state_cur(484);
out70 <=
state_cur(337) or state_cur(336) or state_cur(282) or state_cur(228) or state_cur(203) or state_cur(189) or state_cur(179) or state_cur(102) or
state_cur(100) or state_cur(98) or rtmcmp92 or state_cur(91);
out1077 <=
state_cur(326);
out1215 <=
state_cur(496);
out285 <=
state_cur(338) or state_cur(319) or state_cur(312) or state_cur(274) or state_cur(236) or state_cur(233) or state_cur(209) or state_cur(193) or
state_cur(174) or state_cur(172) or state_cur(134) or state_cur(119);
out1206 <=
state_cur(478);
out1175 <=
state_cur(416);
out1222 <=
state_cur(510);
out443 <=
state_cur(160);
out212 <=
state_cur(105);
out270 <=
state_cur(296) or state_cur(114);
out865 <=
state_cur(234);
out648 <=
state_cur(222) or state_cur(212);
out1176 <=
state_cur(418);
out1174 <=
state_cur(414);
out54 <=
state_cur(82);
out706 <=
state_cur(296) or state_cur(222);
out913 <=
state_cur(266);
out24 <=
state_cur(23);
out1164 <=
state_cur(394);
out729 <=
state_cur(341) or state_cur(273) or state_cur(222);
out1204 <=
state_cur(474);
out573 <=
state_cur(199);
out480 <=
state_cur(222) or state_cur(174);
out14 <=
state_cur(9);
out1073 <=
state_cur(325);
out974 <=
state_cur(284);
out358 <=
state_cur(222) or state_cur(132);
out504 <=
state_cur(180);
out21 <=
state_cur(19);
out37 <=
state_cur(54);
out541 <=
state_cur(222) or state_cur(191);
out1071 <=
state_cur(322);
out23 <=
state_cur(22);
out1122 <=
state_cur(337);
out8 <=
state_cur(4);
out839 <=
state_cur(225);
out35 <=
state_cur(47);
out988 <=
state_cur(291);
out419 <=
state_cur(147);
out976 <=
state_cur(289);
out973 <=
state_cur(283);
out58 <=
state_cur(89);
out424 <=
state_cur(306) or state_cur(148);
out450 <=
state_cur(222) or state_cur(170);
out1068 <=
state_cur(321);
out1170 <=
state_cur(406);
out1067 <=
state_cur(319);
out1225 <=
state_cur(516);
out1187 <=
state_cur(440);
out563 <=
state_cur(222) or state_cur(197);
out1178 <=
state_cur(422);
out31 <=
state_cur(39);
out51 <=
state_cur(76);
out1171 <=
state_cur(408);
out41 <=
state_cur(59);
out360 <=
state_cur(133);
out1162 <=
state_cur(390);
out403 <=
state_cur(144);
out1179 <=
state_cur(424);
out1212 <=
state_cur(490);
out1189 <=
state_cur(444);
out1166 <=
state_cur(398);
out42 <=
state_cur(60);
out1220 <=
state_cur(506);
out137 <=
state_cur(99);
out643 <=
state_cur(210);
out692 <=
rtmcmp276 or state_cur(222);
out43 <=
state_cur(62);
out972 <=
state_cur(282);
out472 <=
state_cur(173);
out505 <=
state_cur(181);
out934 <=
state_cur(274);
out1165 <=
state_cur(396);
out494 <=
state_cur(334) or state_cur(222) or state_cur(178);
out1208 <=
state_cur(482);
out1172 <=
state_cur(410);
out550 <=
state_cur(195);
out439 <=
state_cur(152);
out388 <=
rtmcmp290 or state_cur(270) or state_cur(190) or state_cur(186) or state_cur(144) or state_cur(142);
out1195 <=
state_cur(456);
out479 <=
state_cur(174);
out1193 <=
state_cur(452);
out105 <=
state_cur(94);
out903 <=
state_cur(249);
out697 <=
state_cur(300) or state_cur(222);
out1149 <=
state_cur(364);
out49 <=
state_cur(73);
out448 <=
state_cur(169);
out436 <=
state_cur(150);
out917 <=
state_cur(270);
out1064 <=
state_cur(315);
out912 <=
state_cur(265);
out592 <=
state_cur(208);
out1167 <=
state_cur(400);
out719 <=
state_cur(237) or state_cur(222);
out301 <=
state_cur(125);
out1152 <=
state_cur(370);
out1063 <=
state_cur(312);
out1230 <=
state_cur(523);
out46 <=
state_cur(69);
out47 <=
state_cur(70);
out351 <=
state_cur(222) or state_cur(184) or state_cur(129);
out1169 <=
state_cur(404);
out491 <=
state_cur(222) or state_cur(200) or state_cur(178);
out1061 <=
state_cur(311);
out434 <=
state_cur(150);
out76 <=
state_cur(337) or state_cur(336) or state_cur(326) or state_cur(322) or state_cur(303) or state_cur(296) or state_cur(291) or rtmcmp290 or
rtmcmp276 or state_cur(212) or state_cur(204) or state_cur(203) or state_cur(191) or state_cur(190) or state_cur(186) or state_cur(143) or
state_cur(132) or rtmcmp128 or state_cur(123) or state_cur(114) or state_cur(107) or state_cur(100) or rtmcmp92 or state_cur(91);
out840 <=
state_cur(227);
out88 <=
state_cur(336) or state_cur(296) or state_cur(291) or rtmcmp290 or rtmcmp276 or rtmcmp128 or state_cur(114) or rtmcmp92;
out356 <=
state_cur(131);
out442 <=
state_cur(158);
out1199 <=
state_cur(464);
out1043 <=
state_cur(300);
out11 <=
state_cur(324) or state_cur(323) or state_cur(320) or state_cur(318) or state_cur(317) or state_cur(316) or state_cur(314) or state_cur(313) or
state_cur(305) or state_cur(304) or state_cur(302) or state_cur(297) or state_cur(295) or state_cur(288) or state_cur(287) or state_cur(285) or
state_cur(279) or state_cur(278) or state_cur(272) or state_cur(269) or state_cur(264) or state_cur(263) or state_cur(259) or state_cur(258) or
state_cur(256) or state_cur(250) or state_cur(246) or state_cur(243) or state_cur(239) or state_cur(226) or state_cur(217) or state_cur(216) or
state_cur(215) or state_cur(211) or state_cur(207) or state_cur(202) or state_cur(201) or state_cur(194) or state_cur(192) or state_cur(188) or
state_cur(176) or state_cur(171) or state_cur(167) or state_cur(165) or state_cur(163) or state_cur(161) or state_cur(159) or state_cur(157) or
state_cur(155) or state_cur(153) or state_cur(140) or state_cur(136) or state_cur(135) or state_cur(130) or state_cur(127) or state_cur(124) or
state_cur(122) or state_cur(121) or state_cur(120) or state_cur(118) or state_cur(117) or state_cur(116) or state_cur(112) or state_cur(104) or
state_cur(101) or state_cur(97) or state_cur(90) or state_cur(87) or state_cur(84) or state_cur(80) or state_cur(77) or state_cur(75) or
state_cur(68) or state_cur(67) or state_cur(65) or state_cur(64) or state_cur(61) or state_cur(55) or state_cur(52) or state_cur(51) or
state_cur(50) or state_cur(49) or state_cur(48) or state_cur(46) or state_cur(44) or state_cur(41) or state_cur(37) or state_cur(35) or
state_cur(34) or state_cur(33) or state_cur(28) or state_cur(27) or state_cur(26) or state_cur(24) or state_cur(21) or state_cur(17) or
state_cur(14) or state_cur(13) or state_cur(12) or state_cur(10) or state_cur(6);
out591 <=
state_cur(206);
out1180 <=
state_cur(426);
out476 <=
state_cur(291) or state_cur(173);
out1059 <=
state_cur(310);
out92 <=
state_cur(222) or state_cur(138) or state_cur(93);
out418 <=
state_cur(146);
out1042 <=
state_cur(299);
out1057 <=
state_cur(309);
out213 <=
state_cur(273) or state_cur(222) or state_cur(105);
out444 <=
state_cur(162);
out1153 <=
state_cur(372);
out1056 <=
state_cur(336) or state_cur(308);
out957 <=
state_cur(277);
out344 <=
state_cur(222) or state_cur(183) or state_cur(129);
out545 <=
state_cur(212) or state_cur(210) or state_cur(204) or state_cur(193);
out1055 <=
state_cur(308);
out968 <=
state_cur(282);
out335 <=
state_cur(222) or rtmcmp128;
out226 <=
state_cur(273) or state_cur(222) or state_cur(108);
out905 <=
state_cur(252);
out1177 <=
state_cur(420);
out904 <=
state_cur(251);
out1053 <=
state_cur(307);
out1052 <=
state_cur(306);
out417 <=
state_cur(145);
out1201 <=
state_cur(468);
out1163 <=
state_cur(392);
out2 <=
state_cur(330) or state_cur(329) or state_cur(327) or state_cur(321) or state_cur(315) or state_cur(311) or state_cur(309) or state_cur(307) or
state_cur(299) or state_cur(293) or state_cur(286) or state_cur(284) or state_cur(283) or state_cur(277) or state_cur(275) or state_cur(271) or
state_cur(267) or state_cur(266) or state_cur(265) or state_cur(262) or state_cur(261) or state_cur(260) or state_cur(257) or state_cur(254) or
state_cur(253) or state_cur(252) or state_cur(251) or state_cur(249) or state_cur(248) or state_cur(244) or state_cur(238) or state_cur(230) or
state_cur(229) or state_cur(227) or state_cur(225) or state_cur(221) or state_cur(206) or state_cur(205) or state_cur(199) or state_cur(185) or
state_cur(181) or state_cur(177) or state_cur(168) or state_cur(166) or state_cur(164) or state_cur(162) or state_cur(160) or state_cur(158) or
state_cur(156) or state_cur(154) or state_cur(139) or state_cur(137) or state_cur(133) or state_cur(131) or state_cur(126) or state_cur(113) or
state_cur(111) or state_cur(89) or state_cur(88) or state_cur(82) or state_cur(81) or state_cur(76) or state_cur(74) or state_cur(70) or
state_cur(69) or state_cur(66) or state_cur(63) or state_cur(62) or state_cur(60) or state_cur(59) or state_cur(58) or state_cur(57) or
state_cur(56) or state_cur(54) or state_cur(53) or state_cur(47) or state_cur(45) or state_cur(43) or state_cur(40) or state_cur(39) or
state_cur(38) or state_cur(36) or state_cur(32) or state_cur(31) or state_cur(30) or state_cur(25) or state_cur(23) or state_cur(22) or
state_cur(20) or state_cur(19) or state_cur(18) or state_cur(16) or state_cur(15) or state_cur(9) or state_cur(8) or state_cur(7) or
state_cur(5) or state_cur(4) or state_cur(3) or state_cur(2) or state_cur(0);
out447 <=
state_cur(168);
out1202 <=
state_cur(470);
out1192 <=
state_cur(450);
out1050 <=
state_cur(303);
out1144 <=
state_cur(354);
out0 <=
state_cur(0);
out446 <=
state_cur(166);
out914 <=
state_cur(267);
out1194 <=
state_cur(454);
out906 <=
state_cur(253);
out1146 <=
state_cur(358);
out572 <=
state_cur(198);
out1223 <=
state_cur(512);
out53 <=
state_cur(81);
out36 <=
state_cur(53);
out355 <=
state_cur(222) or state_cur(187) or state_cur(129);
out1184 <=
state_cur(434);
out907 <=
state_cur(254);
out1207 <=
state_cur(480);
out18 <=
state_cur(15);
out108 <=
state_cur(222) or state_cur(178) or state_cur(95);
out1160 <=
state_cur(386);
out662 <=
state_cur(218);
out303 <=
state_cur(247) or state_cur(242) or state_cur(241) or state_cur(197) or state_cur(152) or state_cur(148) or state_cur(125);
out1214 <=
state_cur(494);
out1185 <=
state_cur(436);
out341 <=
state_cur(523) or state_cur(222) or state_cur(129);
out1151 <=
state_cur(368);
out652 <=
state_cur(214);
out390 <=
state_cur(222) or state_cur(143);
out523 <=
state_cur(185);
out686 <=
state_cur(222);
out155 <=
state_cur(100);
out682 <=
state_cur(221);
out680 <=
state_cur(222) or state_cur(220);
out679 <=
state_cur(220);
out678 <=
state_cur(222) or state_cur(219);
out677 <=
state_cur(219);
-- Assignment of buffered outputs
out386 <= out386_buf;
out404 <= out404_buf;
out457 <= out457_buf;
out841 <= out841_buf;
out276 <= out276_buf;
out67 <= out67_buf;
out239 <= out239_buf;
out259 <= out259_buf;
out416 <= out416_buf;
out646 <= out646_buf;
out485 <= out485_buf;
out935 <= out935_buf;
out463 <= out463_buf;
out120 <= out120_buf;
out293 <= out293_buf;
out216 <= out216_buf;
out319 <= out319_buf;
out230 <= out230_buf;
out1 <= out1_buf;
out93 <= out93_buf;
out89 <= out89_buf;
out539 <= out539_buf;
out62 <= out62_buf;
out856 <= out856_buf;
out451 <= out451_buf;
out287 <= out287_buf;
out315 <= out315_buf;
out536 <= out536_buf;
out209 <= out209_buf;
out221 <= out221_buf;
out283 <= out283_buf;
out368 <= out368_buf;
out516 <= out516_buf;
out393 <= out393_buf;
out1008 <= out1008_buf;
out392 <= out392_buf;
out261 <= out261_buf;
out559 <= out559_buf;
out543 <= out543_buf;
out895 <= out895_buf;
out82 <= out82_buf;
out220 <= out220_buf;
out95 <= out95_buf;
out943 <= out943_buf;
out465 <= out465_buf;
out238 <= out238_buf;
out1025 <= out1025_buf;
out132 <= out132_buf;
out79 <= out79_buf;
out500 <= out500_buf;
out65 <= out65_buf;
out111 <= out111_buf;
out420 <= out420_buf;
out1076 <= out1076_buf;
out101 <= out101_buf;
out106 <= out106_buf;
out68 <= out68_buf;
out1069 <= out1069_buf;
out77 <= out77_buf;
out102 <= out102_buf;
out394 <= out394_buf;
out342 <= out342_buf;
out104 <= out104_buf;
out361 <= out361_buf;
out116 <= out116_buf;
out595 <= out595_buf;
out1004 <= out1004_buf;
out227 <= out227_buf;
out109 <= out109_buf;
out619 <= out619_buf;
out410 <= out410_buf;
out989 <= out989_buf;
out431 <= out431_buf;
out938 <= out938_buf;
out525 <= out525_buf;
out73 <= out73_buf;
out837 <= out837_buf;
out860 <= out860_buf;
out228 <= out228_buf;
out421 <= out421_buf;
out409 <= out409_buf;
out473 <= out473_buf;
out509 <= out509_buf;
out94 <= out94_buf;
out1048 <= out1048_buf;
out98 <= out98_buf;
out945 <= out945_buf;
out156 <= out156_buf;
out152 <= out152_buf;
-- Retiming: the comparators
rtmcmp92 <= '1' when state_cur(92) = '1' and rtmcounter0 = 1 else '0';
rtmcmp128 <= '1' when state_cur(128) = '1' and rtmcounter0 = 1 else '0';
rtmcmp276 <= '1' when state_cur(276) = '1' and rtmcounter0 = 1 else '0';
rtmcmp290 <= '1' when state_cur(290) = '1' and rtmcounter0 = 1 else '0';
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity fsm_163 is
port (
clock : in std_logic;
reset : in std_logic;
out91 : out std_logic;
out92 : out std_logic;
out93 : out std_logic;
in7 : in std_logic;
out94 : out std_logic;
out95 : out std_logic;
out98 : out std_logic;
out100 : out std_logic;
out101 : out std_logic;
out102 : out std_logic;
out104 : out std_logic;
out105 : out std_logic;
out106 : out std_logic;
out107 : out std_logic;
out108 : out std_logic;
out109 : out std_logic;
out111 : out std_logic;
out114 : out std_logic;
out116 : out std_logic;
out118 : out std_logic;
out119 : out std_logic;
out120 : out std_logic;
out128 : out std_logic;
out130 : out std_logic;
out131 : out std_logic;
out132 : out std_logic;
out137 : out std_logic;
in8 : in std_logic;
out152 : out std_logic;
out155 : out std_logic;
out156 : out std_logic;
out31 : out std_logic;
in2 : in std_logic;
out28 : out std_logic;
out29 : out std_logic;
out30 : out std_logic;
out26 : out std_logic;
out27 : out std_logic;
out24 : out std_logic;
out25 : out std_logic;
out77 : out std_logic;
out79 : out std_logic;
out80 : out std_logic;
out82 : out std_logic;
out34 : out std_logic;
out35 : out std_logic;
out36 : out std_logic;
out32 : out std_logic;
out33 : out std_logic;
out40 : out std_logic;
out41 : out std_logic;
out88 : out std_logic;
out89 : out std_logic;
out21 : out std_logic;
out22 : out std_logic;
out23 : out std_logic;
out73 : out std_logic;
out76 : out std_logic;
in6 : in std_logic;
out70 : out std_logic;
out12 : out std_logic;
out13 : out std_logic;
out14 : out std_logic;
out17 : out std_logic;
out18 : out std_logic;
out19 : out std_logic;
out20 : out std_logic;
out9 : out std_logic;
out11 : out std_logic;
out8 : out std_logic;
out2 : out std_logic;
out4 : out std_logic;
out5 : out std_logic;
in1 : in std_logic;
out6 : out std_logic;
out7 : out std_logic;
out0 : out std_logic;
out1 : out std_logic;
out37 : out std_logic;
out38 : out std_logic;
out39 : out std_logic;
out1222 : out std_logic;
out1223 : out std_logic;
out1224 : out std_logic;
out1225 : out std_logic;
out1226 : out std_logic;
out1228 : out std_logic;
out1230 : out std_logic;
in0 : in std_logic;
out67 : out std_logic;
out68 : out std_logic;
out65 : out std_logic;
out66 : out std_logic;
in5 : in std_logic;
out62 : out std_logic;
out58 : out std_logic;
out56 : out std_logic;
in4 : in std_logic;
out57 : out std_logic;
out54 : out std_logic;
out55 : out std_logic;
out51 : out std_logic;
out52 : out std_logic;
out53 : out std_logic;
in3 : in std_logic;
out46 : out std_logic;
out47 : out std_logic;
out48 : out std_logic;
out49 : out std_logic;
out50 : out std_logic;
out42 : out std_logic;
out43 : out std_logic;
out44 : out std_logic;
out45 : out std_logic;
in9 : in std_logic;
in10 : in std_logic;
out171 : out std_logic;
in11 : in std_logic;
out191 : out std_logic;
out207 : out std_logic;
out208 : out std_logic;
out209 : out std_logic;
out212 : out std_logic;
out213 : out std_logic;
out216 : out std_logic;
out220 : out std_logic;
out221 : out std_logic;
out223 : out std_logic;
out224 : out std_logic;
out226 : out std_logic;
out227 : out std_logic;
out228 : out std_logic;
out229 : out std_logic;
out230 : out std_logic;
out233 : out std_logic;
out235 : out std_logic;
out236 : out std_logic;
out237 : out std_logic;
out238 : out std_logic;
out239 : out std_logic;
out241 : out std_logic;
out250 : out std_logic;
out258 : out std_logic;
out259 : out std_logic;
out261 : out std_logic;
out270 : out std_logic;
out276 : out std_logic;
out277 : out std_logic;
out283 : out std_logic;
out285 : out std_logic;
out287 : out std_logic;
out290 : out std_logic;
out291 : out std_logic;
out293 : out std_logic;
out301 : out std_logic;
out303 : out std_logic;
out304 : out std_logic;
out315 : out std_logic;
out319 : out std_logic;
out321 : out std_logic;
out330 : out std_logic;
out335 : out std_logic;
out338 : out std_logic;
out341 : out std_logic;
out342 : out std_logic;
out344 : out std_logic;
out347 : out std_logic;
out351 : out std_logic;
out354 : out std_logic;
out355 : out std_logic;
out356 : out std_logic;
out357 : out std_logic;
out358 : out std_logic;
out360 : out std_logic;
out361 : out std_logic;
out362 : out std_logic;
out365 : out std_logic;
out367 : out std_logic;
out368 : out std_logic;
out370 : out std_logic;
out375 : out std_logic;
out376 : out std_logic;
out378 : out std_logic;
out381 : out std_logic;
out382 : out std_logic;
out386 : out std_logic;
out387 : out std_logic;
out388 : out std_logic;
out390 : out std_logic;
out392 : out std_logic;
out393 : out std_logic;
out394 : out std_logic;
out397 : out std_logic;
out403 : out std_logic;
out404 : out std_logic;
out408 : out std_logic;
out409 : out std_logic;
out410 : out std_logic;
out412 : out std_logic;
out416 : out std_logic;
out417 : out std_logic;
out418 : out std_logic;
out419 : out std_logic;
out420 : out std_logic;
out421 : out std_logic;
out424 : out std_logic;
out425 : out std_logic;
out430 : out std_logic;
out431 : out std_logic;
out434 : out std_logic;
out436 : out std_logic;
out438 : out std_logic;
out439 : out std_logic;
out440 : out std_logic;
out441 : out std_logic;
out442 : out std_logic;
out443 : out std_logic;
out444 : out std_logic;
out445 : out std_logic;
out446 : out std_logic;
out447 : out std_logic;
out448 : out std_logic;
out450 : out std_logic;
out451 : out std_logic;
out454 : out std_logic;
out457 : out std_logic;
out460 : out std_logic;
out463 : out std_logic;
out465 : out std_logic;
out466 : out std_logic;
out472 : out std_logic;
out473 : out std_logic;
out475 : out std_logic;
out476 : out std_logic;
out479 : out std_logic;
out480 : out std_logic;
out481 : out std_logic;
out482 : out std_logic;
out484 : out std_logic;
out485 : out std_logic;
out489 : out std_logic;
out491 : out std_logic;
out494 : out std_logic;
out497 : out std_logic;
out500 : out std_logic;
out503 : out std_logic;
out504 : out std_logic;
out505 : out std_logic;
out508 : out std_logic;
out509 : out std_logic;
out513 : out std_logic;
out514 : out std_logic;
out516 : out std_logic;
out521 : out std_logic;
out523 : out std_logic;
out524 : out std_logic;
out525 : out std_logic;
out530 : out std_logic;
out532 : out std_logic;
out533 : out std_logic;
out535 : out std_logic;
out536 : out std_logic;
out539 : out std_logic;
out541 : out std_logic;
out543 : out std_logic;
out545 : out std_logic;
out547 : out std_logic;
out549 : out std_logic;
out550 : out std_logic;
out552 : out std_logic;
out558 : out std_logic;
out559 : out std_logic;
out563 : out std_logic;
out566 : out std_logic;
out572 : out std_logic;
out573 : out std_logic;
out576 : out std_logic;
out577 : out std_logic;
out581 : out std_logic;
out582 : out std_logic;
out590 : out std_logic;
out591 : out std_logic;
out592 : out std_logic;
out593 : out std_logic;
out595 : out std_logic;
out611 : out std_logic;
out619 : out std_logic;
out638 : out std_logic;
out643 : out std_logic;
out644 : out std_logic;
out645 : out std_logic;
out646 : out std_logic;
out648 : out std_logic;
out650 : out std_logic;
out652 : out std_logic;
out657 : out std_logic;
out659 : out std_logic;
out662 : out std_logic;
out677 : out std_logic;
out678 : out std_logic;
out679 : out std_logic;
out680 : out std_logic;
out682 : out std_logic;
out686 : out std_logic;
out692 : out std_logic;
out1218 : out std_logic;
out1219 : out std_logic;
out1220 : out std_logic;
out1221 : out std_logic;
out695 : out std_logic;
out697 : out std_logic;
out706 : out std_logic;
out719 : out std_logic;
out729 : out std_logic;
out744 : out std_logic;
out746 : out std_logic;
out748 : out std_logic;
out833 : out std_logic;
out834 : out std_logic;
out836 : out std_logic;
out837 : out std_logic;
out839 : out std_logic;
out840 : out std_logic;
out841 : out std_logic;
out844 : out std_logic;
out845 : out std_logic;
out846 : out std_logic;
out848 : out std_logic;
out850 : out std_logic;
out852 : out std_logic;
out854 : out std_logic;
out856 : out std_logic;
out858 : out std_logic;
out860 : out std_logic;
out863 : out std_logic;
out865 : out std_logic;
out866 : out std_logic;
out873 : out std_logic;
out877 : out std_logic;
out888 : out std_logic;
out891 : out std_logic;
out893 : out std_logic;
out895 : out std_logic;
out898 : out std_logic;
out900 : out std_logic;
out902 : out std_logic;
out903 : out std_logic;
out904 : out std_logic;
out905 : out std_logic;
out906 : out std_logic;
out907 : out std_logic;
out908 : out std_logic;
out909 : out std_logic;
out910 : out std_logic;
out912 : out std_logic;
out913 : out std_logic;
out914 : out std_logic;
out915 : out std_logic;
out917 : out std_logic;
out920 : out std_logic;
out921 : out std_logic;
out924 : out std_logic;
out934 : out std_logic;
out935 : out std_logic;
out937 : out std_logic;
out938 : out std_logic;
out940 : out std_logic;
out943 : out std_logic;
out945 : out std_logic;
out957 : out std_logic;
out958 : out std_logic;
out962 : out std_logic;
out968 : out std_logic;
out972 : out std_logic;
out973 : out std_logic;
out974 : out std_logic;
out975 : out std_logic;
out976 : out std_logic;
out980 : out std_logic;
out986 : out std_logic;
out988 : out std_logic;
out989 : out std_logic;
out990 : out std_logic;
out1004 : out std_logic;
out1008 : out std_logic;
out999 : out std_logic;
out1000 : out std_logic;
out1002 : out std_logic;
out1003 : out std_logic;
out1050 : out std_logic;
out1052 : out std_logic;
out1053 : out std_logic;
out1055 : out std_logic;
out1056 : out std_logic;
out1057 : out std_logic;
out1059 : out std_logic;
out1015 : out std_logic;
out1025 : out std_logic;
out1026 : out std_logic;
out1038 : out std_logic;
out1039 : out std_logic;
out1042 : out std_logic;
out1043 : out std_logic;
out1046 : out std_logic;
out1048 : out std_logic;
out1061 : out std_logic;
out1063 : out std_logic;
out1064 : out std_logic;
out1067 : out std_logic;
out1068 : out std_logic;
out1069 : out std_logic;
out1071 : out std_logic;
out1073 : out std_logic;
out1076 : out std_logic;
out1077 : out std_logic;
out1078 : out std_logic;
out1080 : out std_logic;
out1081 : out std_logic;
out1083 : out std_logic;
out1085 : out std_logic;
out1087 : out std_logic;
out1089 : out std_logic;
out1092 : out std_logic;
out1096 : out std_logic;
out1100 : out std_logic;
out1103 : out std_logic;
out1115 : out std_logic;
out1122 : out std_logic;
out1123 : out std_logic;
out1127 : out std_logic;
out1130 : out std_logic;
out1133 : out std_logic;
out1138 : out std_logic;
out1139 : out std_logic;
out1140 : out std_logic;
out1141 : out std_logic;
out1142 : out std_logic;
out1143 : out std_logic;
out1144 : out std_logic;
out1145 : out std_logic;
out1146 : out std_logic;
out1147 : out std_logic;
out1148 : out std_logic;
out1149 : out std_logic;
out1150 : out std_logic;
out1151 : out std_logic;
out1152 : out std_logic;
out1153 : out std_logic;
out1154 : out std_logic;
out1155 : out std_logic;
out1156 : out std_logic;
out1157 : out std_logic;
out1158 : out std_logic;
out1159 : out std_logic;
out1160 : out std_logic;
out1161 : out std_logic;
out1162 : out std_logic;
out1163 : out std_logic;
out1164 : out std_logic;
out1165 : out std_logic;
out1166 : out std_logic;
out1167 : out std_logic;
out1168 : out std_logic;
out1169 : out std_logic;
out1170 : out std_logic;
out1171 : out std_logic;
out1172 : out std_logic;
out1173 : out std_logic;
out1174 : out std_logic;
out1175 : out std_logic;
out1176 : out std_logic;
out1177 : out std_logic;
out1178 : out std_logic;
out1179 : out std_logic;
out1180 : out std_logic;
out1181 : out std_logic;
out1182 : out std_logic;
out1183 : out std_logic;
out1184 : out std_logic;
out1185 : out std_logic;
out1186 : out std_logic;
out1187 : out std_logic;
out1188 : out std_logic;
out1189 : out std_logic;
out1190 : out std_logic;
out1191 : out std_logic;
out1192 : out std_logic;
out1193 : out std_logic;
out1194 : out std_logic;
out1195 : out std_logic;
out1196 : out std_logic;
out1197 : out std_logic;
out1198 : out std_logic;
out1199 : out std_logic;
out1200 : out std_logic;
out1201 : out std_logic;
out1202 : out std_logic;
out1203 : out std_logic;
out1204 : out std_logic;
out1205 : out std_logic;
out1206 : out std_logic;
out1207 : out std_logic;
out1208 : out std_logic;
out1209 : out std_logic;
out1210 : out std_logic;
out1211 : out std_logic;
out1212 : out std_logic;
out1213 : out std_logic;
out1214 : out std_logic;
out1215 : out std_logic;
out1216 : out std_logic;
out1217 : out std_logic
);
end fsm_163;
architecture augh of fsm_163 is
signal state_cur : std_logic_vector(0 to 523) := (141 => '1', others => '0');
signal state_next : std_logic_vector(0 to 523) := (141 => '1', others => '0');
-- Buffers for outputs
signal out386_buf : std_logic := '0';
signal out386_bufn : std_logic;
signal out404_buf : std_logic := '0';
signal out404_bufn : std_logic;
signal out457_buf : std_logic := '0';
signal out457_bufn : std_logic;
signal out841_buf : std_logic := '0';
signal out841_bufn : std_logic;
signal out276_buf : std_logic := '0';
signal out276_bufn : std_logic;
signal out67_buf : std_logic := '0';
signal out67_bufn : std_logic;
signal out239_buf : std_logic := '0';
signal out239_bufn : std_logic;
signal out259_buf : std_logic := '0';
signal out259_bufn : std_logic;
signal out416_buf : std_logic := '0';
signal out416_bufn : std_logic;
signal out646_buf : std_logic := '0';
signal out646_bufn : std_logic;
signal out485_buf : std_logic := '0';
signal out485_bufn : std_logic;
signal out935_buf : std_logic := '0';
signal out935_bufn : std_logic;
signal out463_buf : std_logic := '0';
signal out463_bufn : std_logic;
signal out120_buf : std_logic := '0';
signal out120_bufn : std_logic;
signal out293_buf : std_logic := '0';
signal out293_bufn : std_logic;
signal out216_buf : std_logic := '0';
signal out216_bufn : std_logic;
signal out319_buf : std_logic := '0';
signal out319_bufn : std_logic;
signal out230_buf : std_logic := '0';
signal out230_bufn : std_logic;
signal out1_buf : std_logic := '0';
signal out1_bufn : std_logic;
signal out93_buf : std_logic := '0';
signal out93_bufn : std_logic;
signal out89_buf : std_logic := '0';
signal out89_bufn : std_logic;
signal out539_buf : std_logic := '0';
signal out539_bufn : std_logic;
signal out62_buf : std_logic := '0';
signal out62_bufn : std_logic;
signal out856_buf : std_logic := '0';
signal out856_bufn : std_logic;
signal out451_buf : std_logic := '0';
signal out451_bufn : std_logic;
signal out287_buf : std_logic := '0';
signal out287_bufn : std_logic;
signal out315_buf : std_logic := '0';
signal out315_bufn : std_logic;
signal out536_buf : std_logic := '0';
signal out536_bufn : std_logic;
signal out209_buf : std_logic := '0';
signal out209_bufn : std_logic;
signal out221_buf : std_logic := '0';
signal out221_bufn : std_logic;
signal out283_buf : std_logic := '0';
signal out283_bufn : std_logic;
signal out368_buf : std_logic := '0';
signal out368_bufn : std_logic;
signal out516_buf : std_logic := '0';
signal out516_bufn : std_logic;
signal out393_buf : std_logic := '0';
signal out393_bufn : std_logic;
signal out1008_buf : std_logic := '0';
signal out1008_bufn : std_logic;
signal out392_buf : std_logic := '0';
signal out392_bufn : std_logic;
signal out261_buf : std_logic := '0';
signal out261_bufn : std_logic;
signal out559_buf : std_logic := '0';
signal out559_bufn : std_logic;
signal out543_buf : std_logic := '0';
signal out543_bufn : std_logic;
signal out895_buf : std_logic := '0';
signal out895_bufn : std_logic;
signal out82_buf : std_logic := '0';
signal out82_bufn : std_logic;
signal out220_buf : std_logic := '0';
signal out220_bufn : std_logic;
signal out95_buf : std_logic := '0';
signal out95_bufn : std_logic;
signal out943_buf : std_logic := '0';
signal out943_bufn : std_logic;
signal out465_buf : std_logic := '0';
signal out465_bufn : std_logic;
signal out238_buf : std_logic := '0';
signal out238_bufn : std_logic;
signal out1025_buf : std_logic := '0';
signal out1025_bufn : std_logic;
signal out132_buf : std_logic := '0';
signal out132_bufn : std_logic;
signal out79_buf : std_logic := '0';
signal out79_bufn : std_logic;
signal out500_buf : std_logic := '0';
signal out500_bufn : std_logic;
signal out65_buf : std_logic := '0';
signal out65_bufn : std_logic;
signal out111_buf : std_logic := '0';
signal out111_bufn : std_logic;
signal out420_buf : std_logic := '0';
signal out420_bufn : std_logic;
signal out1076_buf : std_logic := '0';
signal out1076_bufn : std_logic;
signal out101_buf : std_logic := '0';
signal out101_bufn : std_logic;
signal out106_buf : std_logic := '0';
signal out106_bufn : std_logic;
signal out68_buf : std_logic := '0';
signal out68_bufn : std_logic;
signal out1069_buf : std_logic := '0';
signal out1069_bufn : std_logic;
signal out77_buf : std_logic := '0';
signal out77_bufn : std_logic;
signal out102_buf : std_logic := '0';
signal out102_bufn : std_logic;
signal out394_buf : std_logic := '0';
signal out394_bufn : std_logic;
signal out342_buf : std_logic := '0';
signal out342_bufn : std_logic;
signal out104_buf : std_logic := '0';
signal out104_bufn : std_logic;
signal out361_buf : std_logic := '0';
signal out361_bufn : std_logic;
signal out116_buf : std_logic := '0';
signal out116_bufn : std_logic;
signal out595_buf : std_logic := '0';
signal out595_bufn : std_logic;
signal out1004_buf : std_logic := '0';
signal out1004_bufn : std_logic;
signal out227_buf : std_logic := '0';
signal out227_bufn : std_logic;
signal out109_buf : std_logic := '0';
signal out109_bufn : std_logic;
signal out619_buf : std_logic := '0';
signal out619_bufn : std_logic;
signal out410_buf : std_logic := '0';
signal out410_bufn : std_logic;
signal out989_buf : std_logic := '0';
signal out989_bufn : std_logic;
signal out431_buf : std_logic := '0';
signal out431_bufn : std_logic;
signal out938_buf : std_logic := '0';
signal out938_bufn : std_logic;
signal out525_buf : std_logic := '0';
signal out525_bufn : std_logic;
signal out73_buf : std_logic := '0';
signal out73_bufn : std_logic;
signal out837_buf : std_logic := '0';
signal out837_bufn : std_logic;
signal out860_buf : std_logic := '0';
signal out860_bufn : std_logic;
signal out228_buf : std_logic := '0';
signal out228_bufn : std_logic;
signal out421_buf : std_logic := '0';
signal out421_bufn : std_logic;
signal out409_buf : std_logic := '0';
signal out409_bufn : std_logic;
signal out473_buf : std_logic := '0';
signal out473_bufn : std_logic;
signal out509_buf : std_logic := '0';
signal out509_bufn : std_logic;
signal out94_buf : std_logic := '0';
signal out94_bufn : std_logic;
signal out1048_buf : std_logic := '0';
signal out1048_bufn : std_logic;
signal out98_buf : std_logic := '0';
signal out98_bufn : std_logic;
signal out945_buf : std_logic := '0';
signal out945_bufn : std_logic;
signal out156_buf : std_logic := '0';
signal out156_bufn : std_logic;
signal out152_buf : std_logic := '0';
signal out152_bufn : std_logic;
-- Retiming: counters
signal rtmcounter0 : unsigned(4 downto 0) := (others => '0');
signal rtmcounter0_next : unsigned(4 downto 0);
-- Retiming: Output of comparators
signal rtmcmp92 : std_logic;
signal rtmcmp128 : std_logic;
signal rtmcmp276 : std_logic;
signal rtmcmp290 : std_logic;
-- Don't understand why these two function declarations are needed...
function "/=" (L, R: std_logic) return std_logic is
begin
if L /= R then
return '1';
end if;
return '0';
end function;
function "=" (L, R: std_logic) return std_logic is
begin
if L = R then
return '1';
end if;
return '0';
end function;
begin
-- Sequential process
-- Set the current state
process (clock)
begin
if rising_edge(clock) then
-- Next state
state_cur <= state_next;
-- Buffers for outputs
out386_buf <= out386_bufn;
out404_buf <= out404_bufn;
out457_buf <= out457_bufn;
out841_buf <= out841_bufn;
out276_buf <= out276_bufn;
out67_buf <= out67_bufn;
out239_buf <= out239_bufn;
out259_buf <= out259_bufn;
out416_buf <= out416_bufn;
out646_buf <= out646_bufn;
out485_buf <= out485_bufn;
out935_buf <= out935_bufn;
out463_buf <= out463_bufn;
out120_buf <= out120_bufn;
out293_buf <= out293_bufn;
out216_buf <= out216_bufn;
out319_buf <= out319_bufn;
out230_buf <= out230_bufn;
out1_buf <= out1_bufn;
out93_buf <= out93_bufn;
out89_buf <= out89_bufn;
out539_buf <= out539_bufn;
out62_buf <= out62_bufn;
out856_buf <= out856_bufn;
out451_buf <= out451_bufn;
out287_buf <= out287_bufn;
out315_buf <= out315_bufn;
out536_buf <= out536_bufn;
out209_buf <= out209_bufn;
out221_buf <= out221_bufn;
out283_buf <= out283_bufn;
out368_buf <= out368_bufn;
out516_buf <= out516_bufn;
out393_buf <= out393_bufn;
out1008_buf <= out1008_bufn;
out392_buf <= out392_bufn;
out261_buf <= out261_bufn;
out559_buf <= out559_bufn;
out543_buf <= out543_bufn;
out895_buf <= out895_bufn;
out82_buf <= out82_bufn;
out220_buf <= out220_bufn;
out95_buf <= out95_bufn;
out943_buf <= out943_bufn;
out465_buf <= out465_bufn;
out238_buf <= out238_bufn;
out1025_buf <= out1025_bufn;
out132_buf <= out132_bufn;
out79_buf <= out79_bufn;
out500_buf <= out500_bufn;
out65_buf <= out65_bufn;
out111_buf <= out111_bufn;
out420_buf <= out420_bufn;
out1076_buf <= out1076_bufn;
out101_buf <= out101_bufn;
out106_buf <= out106_bufn;
out68_buf <= out68_bufn;
out1069_buf <= out1069_bufn;
out77_buf <= out77_bufn;
out102_buf <= out102_bufn;
out394_buf <= out394_bufn;
out342_buf <= out342_bufn;
out104_buf <= out104_bufn;
out361_buf <= out361_bufn;
out116_buf <= out116_bufn;
out595_buf <= out595_bufn;
out1004_buf <= out1004_bufn;
out227_buf <= out227_bufn;
out109_buf <= out109_bufn;
out619_buf <= out619_bufn;
out410_buf <= out410_bufn;
out989_buf <= out989_bufn;
out431_buf <= out431_bufn;
out938_buf <= out938_bufn;
out525_buf <= out525_bufn;
out73_buf <= out73_bufn;
out837_buf <= out837_bufn;
out860_buf <= out860_bufn;
out228_buf <= out228_bufn;
out421_buf <= out421_bufn;
out409_buf <= out409_bufn;
out473_buf <= out473_bufn;
out509_buf <= out509_bufn;
out94_buf <= out94_bufn;
out1048_buf <= out1048_bufn;
out98_buf <= out98_bufn;
out945_buf <= out945_bufn;
out156_buf <= out156_bufn;
out152_buf <= out152_bufn;
-- Retiming: counters
rtmcounter0 <= rtmcounter0_next;
end if;
end process;
-- Retiming: the counters
rtmcounter0_next <= rtmcounter0 + 1 when (reset /= '1') and (
(state_cur(290) = '1' and rtmcmp290 = '0') or (state_cur(276) = '1' and rtmcmp276 = '0') or (state_cur(128) = '1' and rtmcmp128 = '0') or (state_cur(92) = '1' and rtmcmp92 = '0')
) else (others => '0');
-- Next state bits
state_next(0) <= (reset /= '1') and ( ( state_cur(90) and not ( (NOT(in0)) = '1' ) ) );
state_next(1) <= (reset /= '1') and ( ( state_cur(86) and not ( (NOT(in1)) = '1' ) ) );
state_next(2) <= (reset /= '1') and ( ( state_cur(44) and not ( (NOT(in0)) = '1' ) ) );
state_next(3) <= (reset /= '1') and ( ( state_cur(201) and not ( (NOT(in0)) = '1' ) ) );
state_next(4) <= (reset /= '1') and ( ( state_cur(48) and not ( (NOT(in0)) = '1' ) ) );
state_next(5) <= (reset /= '1') and ( ( state_cur(6) and not ( (NOT(in0)) = '1' ) ) );
state_next(6) <= (reset /= '1') and ( state_cur(32) or ( state_cur(6) and (NOT(in0)) = '1' ) );
state_next(7) <= (reset /= '1') and ( ( state_cur(207) and not ( (NOT(in0)) = '1' ) ) );
state_next(8) <= (reset /= '1') and ( ( state_cur(17) and not ( (NOT(in0)) = '1' ) ) );
state_next(9) <= (reset /= '1') and ( ( state_cur(13) and not ( (NOT(in0)) = '1' ) ) );
state_next(10) <= (reset /= '1') and ( state_cur(221) or ( state_cur(10) and (NOT(in0)) = '1' ) );
state_next(11) <= (reset /= '1') and ( state_cur(83) or ( state_cur(11) and (NOT(in1)) = '1' ) );
state_next(12) <= (reset /= '1') and ( state_cur(23) or ( state_cur(12) and (NOT(in0)) = '1' ) );
state_next(13) <= (reset /= '1') and ( state_cur(321) or ( state_cur(13) and (NOT(in0)) = '1' ) );
state_next(14) <= (reset /= '1') and ( state_cur(251) or ( state_cur(14) and (NOT(in0)) = '1' ) );
state_next(15) <= (reset /= '1') and ( ( state_cur(263) and not ( (NOT(in0)) = '1' ) ) );
state_next(16) <= (reset /= '1') and ( ( state_cur(188) and not ( (NOT(in0)) = '1' ) ) );
state_next(17) <= (reset /= '1') and ( ( state_cur(17) and (NOT(in0)) = '1' ) or state_cur(9) );
state_next(18) <= (reset /= '1') and ( ( state_cur(239) and not ( (NOT(in0)) = '1' ) ) );
state_next(19) <= (reset /= '1') and ( ( state_cur(14) and not ( (NOT(in0)) = '1' ) ) );
state_next(20) <= (reset /= '1') and ( ( state_cur(27) and not ( (NOT(in0)) = '1' ) ) );
state_next(21) <= (reset /= '1') and ( state_cur(22) or ( state_cur(21) and (NOT(in0)) = '1' ) );
state_next(22) <= (reset /= '1') and ( ( state_cur(26) and not ( (NOT(in0)) = '1' ) ) );
state_next(23) <= (reset /= '1') and ( ( state_cur(117) and not ( (NOT(in0)) = '1' ) ) );
state_next(24) <= (reset /= '1') and ( state_cur(254) or ( state_cur(24) and (NOT(in0)) = '1' ) );
state_next(25) <= (reset /= '1') and ( ( state_cur(320) and not ( (NOT(in0)) = '1' ) ) );
state_next(26) <= (reset /= '1') and ( ( state_cur(26) and (NOT(in0)) = '1' ) or state_cur(25) );
state_next(27) <= (reset /= '1') and ( state_cur(81) or ( state_cur(27) and (NOT(in0)) = '1' ) );
state_next(28) <= (reset /= '1') and ( state_cur(261) or ( state_cur(28) and (NOT(in0)) = '1' ) );
state_next(29) <= (reset /= '1') and ( state_cur(198) or ( state_cur(29) and (NOT(in1)) = '1' ) );
state_next(30) <= (reset /= '1') and ( ( state_cur(324) and not ( (NOT(in0)) = '1' ) ) );
state_next(31) <= (reset /= '1') and ( ( state_cur(33) and not ( (NOT(in0)) = '1' ) ) );
state_next(32) <= (reset /= '1') and ( ( state_cur(259) and not ( (NOT(in0)) = '1' ) ) );
state_next(33) <= (reset /= '1') and ( state_cur(267) or ( state_cur(33) and (NOT(in0)) = '1' ) );
state_next(34) <= (reset /= '1') and ( ( state_cur(34) and (NOT(in0)) = '1' ) or state_cur(31) );
state_next(35) <= (reset /= '1') and ( state_cur(36) or ( state_cur(35) and (NOT(in0)) = '1' ) );
state_next(36) <= (reset /= '1') and ( ( state_cur(34) and not ( (NOT(in0)) = '1' ) ) );
state_next(37) <= (reset /= '1') and ( state_cur(38) or ( state_cur(37) and (NOT(in0)) = '1' ) );
state_next(38) <= (reset /= '1') and ( ( state_cur(35) and not ( (NOT(in0)) = '1' ) ) );
state_next(39) <= (reset /= '1') and ( ( state_cur(323) and not ( (NOT(in0)) = '1' ) ) );
state_next(40) <= (reset /= '1') and ( ( state_cur(285) and not ( (NOT(in0)) = '1' ) ) );
state_next(41) <= (reset /= '1') and ( ( state_cur(41) and (NOT(in0)) = '1' ) or state_cur(8) );
state_next(42) <= (reset /= '1') and ( state_cur(180) or ( state_cur(42) and (NOT(in1)) = '1' ) );
state_next(43) <= (reset /= '1') and ( ( state_cur(41) and not ( (NOT(in0)) = '1' ) ) );
state_next(44) <= (reset /= '1') and ( state_cur(66) or ( state_cur(44) and (NOT(in0)) = '1' ) );
state_next(45) <= (reset /= '1') and ( ( state_cur(37) and not ( (NOT(in0)) = '1' ) ) );
state_next(46) <= (reset /= '1') and ( ( state_cur(46) and (NOT(in0)) = '1' ) or state_cur(43) );
state_next(47) <= (reset /= '1') and ( ( state_cur(46) and not ( (NOT(in0)) = '1' ) ) );
state_next(48) <= (reset /= '1') and ( ( state_cur(48) and (NOT(in0)) = '1' ) or state_cur(40) );
state_next(49) <= (reset /= '1') and ( ( state_cur(49) and (NOT(in0)) = '1' ) or state_cur(18) );
state_next(50) <= (reset /= '1') and ( ( state_cur(50) and (NOT(in0)) = '1' ) or state_cur(47) );
state_next(51) <= (reset /= '1') and ( state_cur(53) or ( state_cur(51) and (NOT(in0)) = '1' ) );
state_next(52) <= (reset /= '1') and ( state_cur(56) or ( state_cur(52) and (NOT(in0)) = '1' ) );
state_next(53) <= (reset /= '1') and ( ( state_cur(52) and not ( (NOT(in0)) = '1' ) ) );
state_next(54) <= (reset /= '1') and ( ( state_cur(51) and not ( (NOT(in0)) = '1' ) ) );
state_next(55) <= (reset /= '1') and ( ( state_cur(55) and (NOT(in0)) = '1' ) or state_cur(54) );
state_next(56) <= (reset /= '1') and ( ( state_cur(21) and not ( (NOT(in0)) = '1' ) ) );
state_next(57) <= (reset /= '1') and ( ( state_cur(104) and not ( (NOT(in0)) = '1' ) ) );
state_next(58) <= (reset /= '1') and ( ( state_cur(12) and not ( (NOT(in0)) = '1' ) ) );
state_next(59) <= (reset /= '1') and ( ( state_cur(61) and not ( (NOT(in0)) = '1' ) ) );
state_next(60) <= (reset /= '1') and ( ( state_cur(246) and not ( (NOT(in0)) = '1' ) ) );
state_next(61) <= (reset /= '1') and ( state_cur(260) or ( state_cur(61) and (NOT(in0)) = '1' ) );
state_next(62) <= (reset /= '1') and ( ( state_cur(65) and not ( (NOT(in0)) = '1' ) ) );
state_next(63) <= (reset /= '1') and ( ( state_cur(24) and not ( (NOT(in0)) = '1' ) ) );
state_next(64) <= (reset /= '1') and ( state_cur(277) or ( state_cur(64) and (NOT(in0)) = '1' ) );
state_next(65) <= (reset /= '1') and ( state_cur(329) or ( state_cur(65) and (NOT(in0)) = '1' ) );
state_next(66) <= (reset /= '1') and ( ( state_cur(256) and not ( (NOT(in0)) = '1' ) ) );
state_next(67) <= (reset /= '1') and ( ( state_cur(67) and (NOT(in0)) = '1' ) or state_cur(62) );
state_next(68) <= (reset /= '1') and ( ( state_cur(68) and (NOT(in0)) = '1' ) or state_cur(60) );
state_next(69) <= (reset /= '1') and ( ( state_cur(258) and not ( (NOT(in0)) = '1' ) ) );
state_next(70) <= (reset /= '1') and ( ( state_cur(278) and not ( (NOT(in0)) = '1' ) ) );
state_next(71) <= (reset /= '1') and ( ( state_cur(255) and not ( (NOT(in1)) = '1' ) ) );
state_next(72) <= (reset /= '1') and ( state_cur(85) or ( state_cur(72) and (NOT(in1)) = '1' ) );
state_next(73) <= (reset /= '1') and ( ( state_cur(106) and not ( (NOT(in1)) = '1' ) ) );
state_next(74) <= (reset /= '1') and ( ( state_cur(297) and not ( (NOT(in0)) = '1' ) ) );
state_next(75) <= (reset /= '1') and ( ( state_cur(75) and (NOT(in0)) = '1' ) or state_cur(57) );
state_next(76) <= (reset /= '1') and ( ( state_cur(272) and not ( (NOT(in0)) = '1' ) ) );
state_next(77) <= (reset /= '1') and ( state_cur(199) or ( state_cur(77) and (NOT(in0)) = '1' ) );
state_next(78) <= (reset /= '1') and ( state_cur(115) or ( state_cur(78) and (NOT(in1)) = '1' ) );
state_next(79) <= (reset /= '1') and ( ( state_cur(42) and not ( (NOT(in1)) = '1' ) ) );
state_next(80) <= (reset /= '1') and ( ( state_cur(80) and (NOT(in0)) = '1' ) or state_cur(7) );
state_next(81) <= (reset /= '1') and ( ( state_cur(80) and not ( (NOT(in0)) = '1' ) ) );
state_next(82) <= (reset /= '1') and ( ( state_cur(217) and not ( (NOT(in0)) = '1' ) ) );
state_next(83) <= (reset /= '1') and ( ( state_cur(72) and not ( (NOT(in1)) = '1' ) ) );
state_next(84) <= (reset /= '1') and ( ( state_cur(84) and (NOT(in0)) = '1' ) or state_cur(82) );
state_next(85) <= (reset /= '1') and ( ( state_cur(29) and not ( (NOT(in1)) = '1' ) ) );
state_next(86) <= (reset /= '1') and ( state_cur(195) or ( state_cur(86) and (NOT(in1)) = '1' ) );
state_next(87) <= (reset /= '1') and ( ( state_cur(87) and (NOT(in0)) = '1' ) or state_cur(20) );
state_next(88) <= (reset /= '1') and ( ( state_cur(288) and not ( (NOT(in0)) = '1' ) ) );
state_next(89) <= (reset /= '1') and ( ( state_cur(140) and not ( (NOT(in0)) = '1' ) ) );
state_next(90) <= (reset /= '1') and ( ( state_cur(90) and (NOT(in0)) = '1' ) or state_cur(89) );
state_next(91) <= (reset /= '1') and ( state_cur(337) );
state_next(92) <= (reset /= '1') and ( (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) );
state_next(93) <= (reset /= '1') and ( state_cur(339) );
state_next(94) <= (reset /= '1') and ( ( state_cur(175) and not ( (in4) = '1' ) ) );
state_next(95) <= (reset /= '1') and ( state_cur(334) );
state_next(96) <= (reset /= '1') and ( state_cur(333) );
state_next(97) <= (reset /= '1') and ( state_cur(244) or ( state_cur(97) and (NOT(in0)) = '1' ) );
state_next(98) <= (reset /= '1') and ( state_cur(228) );
state_next(99) <= (reset /= '1') and ( state_cur(273) or state_cur(105) );
state_next(100) <= (reset /= '1') and ( state_cur(203) );
state_next(101) <= (reset /= '1') and ( ( state_cur(101) and (NOT(in0)) = '1' ) or state_cur(5) );
state_next(102) <= (reset /= '1') and ( state_cur(98) );
state_next(103) <= (reset /= '1') and ( state_cur(200) );
state_next(104) <= (reset /= '1') and ( state_cur(111) or ( state_cur(104) and (NOT(in0)) = '1' ) );
state_next(105) <= (reset /= '1') and ( state_cur(301) );
state_next(106) <= (reset /= '1') and ( state_cur(214) or ( state_cur(106) and (NOT(in1)) = '1' ) );
state_next(107) <= (reset /= '1') and ( rtmcmp276 );
state_next(108) <= (reset /= '1') and ( state_cur(224) );
state_next(109) <= (reset /= '1') and ( ( state_cur(310) and (in9) = '1' ) );
state_next(110) <= (reset /= '1') and ( state_cur(222) or ( state_cur(110) and (NOT(in1)) = '1' ) );
state_next(111) <= (reset /= '1') and ( ( state_cur(112) and not ( (NOT(in0)) = '1' ) ) );
state_next(112) <= (reset /= '1') and ( state_cur(293) or ( state_cur(112) and (NOT(in0)) = '1' ) );
state_next(113) <= (reset /= '1') and ( ( state_cur(304) and not ( (NOT(in0)) = '1' ) ) );
state_next(114) <= (reset /= '1') and ( state_cur(523) or state_cur(129) );
state_next(115) <= (reset /= '1') and ( ( state_cur(110) and not ( (NOT(in1)) = '1' ) ) );
state_next(116) <= (reset /= '1') and ( state_cur(327) or ( state_cur(116) and (NOT(in0)) = '1' ) );
state_next(117) <= (reset /= '1') and ( ( state_cur(117) and (NOT(in0)) = '1' ) or state_cur(2) );
state_next(118) <= (reset /= '1') and ( state_cur(181) or ( state_cur(118) and (NOT(in0)) = '1' ) );
state_next(119) <= (reset /= '1') and ( state_cur(274) );
state_next(120) <= (reset /= '1') and ( ( state_cur(120) and (NOT(in0)) = '1' ) or state_cur(15) );
state_next(121) <= (reset /= '1') and ( state_cur(227) or ( state_cur(121) and (NOT(in0)) = '1' ) );
state_next(122) <= (reset /= '1') and ( ( state_cur(122) and (NOT(in0)) = '1' ) or state_cur(4) );
state_next(123) <= (reset /= '1') and ( state_cur(303) );
state_next(124) <= (reset /= '1') and ( state_cur(133) or ( state_cur(124) and (NOT(in0)) = '1' ) );
state_next(125) <= (reset /= '1') and ( ( state_cur(343) and not ( (NOT(in1)) = '1' ) ) );
state_next(126) <= (reset /= '1') and ( ( state_cur(314) and not ( (NOT(in0)) = '1' ) ) );
state_next(127) <= (reset /= '1') and ( ( state_cur(127) and (NOT(in0)) = '1' ) or state_cur(126) );
state_next(128) <= (reset /= '1') and ( (state_cur(128) = '1' and rtmcmp128 = '0') or state_cur(296) );
state_next(129) <= (reset /= '1') and ( ( state_cur(208) and (in5) = '1' ) );
state_next(130) <= (reset /= '1') and ( state_cur(137) or ( state_cur(130) and (NOT(in0)) = '1' ) );
state_next(131) <= (reset /= '1') and ( ( state_cur(127) and not ( (NOT(in0)) = '1' ) ) );
state_next(132) <= (reset /= '1') and ( state_cur(191) );
state_next(133) <= (reset /= '1') and ( ( state_cur(118) and not ( (NOT(in0)) = '1' ) ) );
state_next(134) <= (reset /= '1') and ( state_cur(172) );
state_next(135) <= (reset /= '1') and ( state_cur(284) or ( state_cur(135) and (NOT(in0)) = '1' ) );
state_next(136) <= (reset /= '1') and ( state_cur(230) or ( state_cur(136) and (NOT(in0)) = '1' ) );
state_next(137) <= (reset /= '1') and ( ( state_cur(116) and not ( (NOT(in0)) = '1' ) ) );
state_next(138) <= (reset /= '1') and ( ( state_cur(175) and (in4) = '1' ) );
state_next(139) <= (reset /= '1') and ( ( state_cur(101) and not ( (NOT(in0)) = '1' ) ) );
state_next(140) <= (reset /= '1') and ( ( state_cur(140) and (NOT(in0)) = '1' ) or state_cur(139) );
state_next(141) <= (reset = '1') or ( ( state_cur(141) and (NOT(in2)) = '1' ) );
state_next(142) <= (reset /= '1') and ( state_cur(270) );
state_next(143) <= (reset /= '1') and ( state_cur(204) );
state_next(144) <= (reset /= '1') and ( state_cur(173) );
state_next(145) <= (reset /= '1') and ( state_cur(322) );
state_next(146) <= (reset /= '1') and ( state_cur(331) );
state_next(147) <= (reset /= '1') and ( state_cur(197) );
state_next(148) <= (reset /= '1') and ( state_cur(306) );
state_next(149) <= (reset /= '1') and ( state_cur(187) );
state_next(150) <= (reset /= '1') and ( state_cur(294) );
state_next(151) <= (reset /= '1') and ( state_cur(289) );
state_next(152) <= (reset /= '1') and ( ( state_cur(153) and not ( (NOT(in0)) = '1' ) ) );
state_next(153) <= (reset /= '1') and ( state_cur(154) or ( state_cur(153) and (NOT(in0)) = '1' ) );
state_next(154) <= (reset /= '1') and ( ( state_cur(155) and not ( (NOT(in0)) = '1' ) ) );
state_next(155) <= (reset /= '1') and ( state_cur(156) or ( state_cur(155) and (NOT(in0)) = '1' ) );
state_next(156) <= (reset /= '1') and ( ( state_cur(157) and not ( (NOT(in0)) = '1' ) ) );
state_next(157) <= (reset /= '1') and ( state_cur(158) or ( state_cur(157) and (NOT(in0)) = '1' ) );
state_next(158) <= (reset /= '1') and ( ( state_cur(159) and not ( (NOT(in0)) = '1' ) ) );
state_next(159) <= (reset /= '1') and ( state_cur(160) or ( state_cur(159) and (NOT(in0)) = '1' ) );
state_next(160) <= (reset /= '1') and ( ( state_cur(161) and not ( (NOT(in0)) = '1' ) ) );
state_next(161) <= (reset /= '1') and ( state_cur(162) or ( state_cur(161) and (NOT(in0)) = '1' ) );
state_next(162) <= (reset /= '1') and ( ( state_cur(163) and not ( (NOT(in0)) = '1' ) ) );
state_next(163) <= (reset /= '1') and ( state_cur(164) or ( state_cur(163) and (NOT(in0)) = '1' ) );
state_next(164) <= (reset /= '1') and ( ( state_cur(165) and not ( (NOT(in0)) = '1' ) ) );
state_next(165) <= (reset /= '1') and ( state_cur(166) or ( state_cur(165) and (NOT(in0)) = '1' ) );
state_next(166) <= (reset /= '1') and ( ( state_cur(167) and not ( (NOT(in0)) = '1' ) ) );
state_next(167) <= (reset /= '1') and ( state_cur(168) or ( state_cur(167) and (NOT(in0)) = '1' ) );
state_next(168) <= (reset /= '1') and ( ( state_cur(55) and not ( (NOT(in0)) = '1' ) ) );
state_next(169) <= (reset /= '1') and ( state_cur(332) );
state_next(170) <= (reset /= '1') and ( state_cur(169) );
state_next(171) <= (reset /= '1') and ( ( state_cur(171) and (NOT(in0)) = '1' ) or state_cur(16) );
state_next(172) <= (reset /= '1') and ( state_cur(174) );
state_next(173) <= (reset /= '1') and ( ( state_cur(325) and (in10) = '1' ) or ( state_cur(310) and not ( (in9) = '1' ) ) );
state_next(174) <= (reset /= '1') and ( state_cur(319) );
state_next(175) <= (reset /= '1') and ( state_cur(170) );
state_next(176) <= (reset /= '1') and ( ( state_cur(176) and (NOT(in0)) = '1' ) or state_cur(70) );
state_next(177) <= (reset /= '1') and ( ( state_cur(279) and not ( (NOT(in0)) = '1' ) ) );
state_next(178) <= (reset /= '1') and ( ( state_cur(150) and (in3) = '1' ) );
state_next(179) <= (reset /= '1') and ( state_cur(282) );
state_next(180) <= (reset /= '1') and ( ( state_cur(520) and not ( (NOT(in1)) = '1' ) ) );
state_next(181) <= (reset /= '1') and ( ( state_cur(226) and not ( (NOT(in0)) = '1' ) ) );
state_next(182) <= (reset /= '1') and ( state_cur(223) );
state_next(183) <= (reset /= '1') and ( state_cur(280) );
state_next(184) <= (reset /= '1') and ( state_cur(183) );
state_next(185) <= (reset /= '1') and ( ( state_cur(135) and not ( (NOT(in0)) = '1' ) ) );
state_next(186) <= (reset /= '1') and ( rtmcmp290 );
state_next(187) <= (reset /= '1') and ( state_cur(184) );
state_next(188) <= (reset /= '1') and ( state_cur(206) or ( state_cur(188) and (NOT(in0)) = '1' ) );
state_next(189) <= (reset /= '1') and ( state_cur(179) );
state_next(190) <= (reset /= '1') and ( state_cur(186) );
state_next(191) <= (reset /= '1') and ( state_cur(190) );
state_next(192) <= (reset /= '1') and ( ( state_cur(192) and (NOT(in0)) = '1' ) or state_cur(76) );
state_next(193) <= (reset /= '1') and ( state_cur(233) );
state_next(194) <= (reset /= '1') and ( state_cur(252) or ( state_cur(194) and (NOT(in0)) = '1' ) );
state_next(195) <= (reset /= '1') and ( ( state_cur(521) and not ( (NOT(in1)) = '1' ) ) );
state_next(196) <= (reset /= '1') and ( state_cur(231) );
state_next(197) <= (reset /= '1') and ( state_cur(218) );
state_next(198) <= (reset /= '1') and ( ( state_cur(78) and not ( (NOT(in1)) = '1' ) ) );
state_next(199) <= (reset /= '1') and ( ( state_cur(120) and not ( (NOT(in0)) = '1' ) ) );
state_next(200) <= (reset /= '1') and ( state_cur(95) );
state_next(201) <= (reset /= '1') and ( state_cur(307) or ( state_cur(201) and (NOT(in0)) = '1' ) );
state_next(202) <= (reset /= '1') and ( state_cur(266) or ( state_cur(202) and (NOT(in0)) = '1' ) );
state_next(203) <= (reset /= '1') and ( state_cur(91) );
state_next(204) <= (reset /= '1') and ( state_cur(123) );
state_next(205) <= (reset /= '1') and ( ( state_cur(211) and not ( (NOT(in0)) = '1' ) ) );
state_next(206) <= (reset /= '1') and ( ( state_cur(136) and not ( (NOT(in0)) = '1' ) ) );
state_next(207) <= (reset /= '1') and ( ( state_cur(207) and (NOT(in0)) = '1' ) or state_cur(205) );
state_next(208) <= (reset /= '1') and ( state_cur(300) );
state_next(209) <= (reset /= '1') and ( state_cur(312) );
state_next(210) <= (reset /= '1') and ( state_cur(292) );
state_next(211) <= (reset /= '1') and ( ( state_cur(211) and (NOT(in0)) = '1' ) or state_cur(185) );
state_next(212) <= (reset /= '1') and ( state_cur(326) );
state_next(213) <= (reset /= '1') and ( state_cur(340) );
state_next(214) <= (reset /= '1') and ( ( state_cur(11) and not ( (NOT(in1)) = '1' ) ) );
state_next(215) <= (reset /= '1') and ( state_cur(229) or ( state_cur(215) and (NOT(in0)) = '1' ) );
state_next(216) <= (reset /= '1') and ( state_cur(248) or ( state_cur(216) and (NOT(in0)) = '1' ) );
state_next(217) <= (reset /= '1') and ( state_cur(271) or ( state_cur(217) and (NOT(in0)) = '1' ) );
state_next(218) <= (reset /= '1') and ( state_cur(146) or state_cur(138) );
state_next(219) <= (reset /= '1') and ( state_cur(151) );
state_next(220) <= (reset /= '1') and ( state_cur(298) );
state_next(221) <= (reset /= '1') and ( ( state_cur(318) and not ( (NOT(in0)) = '1' ) ) );
state_next(222) <= (reset /= '1') and ( state_cur(152) or ( state_cur(141) and not ( (NOT(in2)) = '1' ) ) );
state_next(223) <= (reset /= '1') and ( state_cur(232) );
state_next(224) <= (reset /= '1') and ( state_cur(342) );
state_next(225) <= (reset /= '1') and ( ( state_cur(202) and not ( (NOT(in0)) = '1' ) ) );
state_next(226) <= (reset /= '1') and ( state_cur(311) or ( state_cur(226) and (NOT(in0)) = '1' ) );
state_next(227) <= (reset /= '1') and ( ( state_cur(250) and not ( (NOT(in0)) = '1' ) ) );
state_next(228) <= (reset /= '1') and ( state_cur(189) );
state_next(229) <= (reset /= '1') and ( ( state_cur(216) and not ( (NOT(in0)) = '1' ) ) );
state_next(230) <= (reset /= '1') and ( ( state_cur(176) and not ( (NOT(in0)) = '1' ) ) );
state_next(231) <= (reset /= '1') and ( state_cur(234) );
state_next(232) <= (reset /= '1') and ( state_cur(145) );
state_next(233) <= (reset /= '1') and ( state_cur(236) );
state_next(234) <= (reset /= '1') and ( state_cur(235) );
state_next(235) <= (reset /= '1') and ( state_cur(102) );
state_next(236) <= (reset /= '1') and ( state_cur(237) );
state_next(237) <= (reset /= '1') and ( state_cur(99) );
state_next(238) <= (reset /= '1') and ( ( state_cur(287) and not ( (NOT(in0)) = '1' ) ) );
state_next(239) <= (reset /= '1') and ( ( state_cur(239) and (NOT(in0)) = '1' ) or state_cur(58) );
state_next(240) <= (reset /= '1') and ( state_cur(241) or state_cur(148) );
state_next(241) <= (reset /= '1') and ( ( state_cur(245) and not ( (in8) = '1' ) ) );
state_next(242) <= (reset /= '1') and ( ( state_cur(97) and not ( (NOT(in0)) = '1' ) ) );
state_next(243) <= (reset /= '1') and ( state_cur(275) or ( state_cur(243) and (NOT(in0)) = '1' ) );
state_next(244) <= (reset /= '1') and ( ( state_cur(245) and (in8) = '1' ) );
state_next(245) <= (reset /= '1') and ( state_cur(247) or state_cur(242) );
state_next(246) <= (reset /= '1') and ( state_cur(253) or ( state_cur(246) and (NOT(in0)) = '1' ) );
state_next(247) <= (reset /= '1') and ( ( state_cur(328) and not ( (in11) = '1' ) ) );
state_next(248) <= (reset /= '1') and ( ( state_cur(302) and not ( (NOT(in0)) = '1' ) ) );
state_next(249) <= (reset /= '1') and ( ( state_cur(77) and not ( (NOT(in0)) = '1' ) ) );
state_next(250) <= (reset /= '1') and ( ( state_cur(250) and (NOT(in0)) = '1' ) or state_cur(88) );
state_next(251) <= (reset /= '1') and ( ( state_cur(130) and not ( (NOT(in0)) = '1' ) ) );
state_next(252) <= (reset /= '1') and ( ( state_cur(171) and not ( (NOT(in0)) = '1' ) ) );
state_next(253) <= (reset /= '1') and ( ( state_cur(49) and not ( (NOT(in0)) = '1' ) ) );
state_next(254) <= (reset /= '1') and ( ( state_cur(68) and not ( (NOT(in0)) = '1' ) ) );
state_next(255) <= (reset /= '1') and ( ( state_cur(255) and (NOT(in1)) = '1' ) or state_cur(79) );
state_next(256) <= (reset /= '1') and ( ( state_cur(256) and (NOT(in0)) = '1' ) or state_cur(69) );
state_next(257) <= (reset /= '1') and ( ( state_cur(64) and not ( (NOT(in0)) = '1' ) ) );
state_next(258) <= (reset /= '1') and ( ( state_cur(258) and (NOT(in0)) = '1' ) or state_cur(249) );
state_next(259) <= (reset /= '1') and ( state_cur(283) or ( state_cur(259) and (NOT(in0)) = '1' ) );
state_next(260) <= (reset /= '1') and ( ( state_cur(50) and not ( (NOT(in0)) = '1' ) ) );
state_next(261) <= (reset /= '1') and ( ( state_cur(269) and not ( (NOT(in0)) = '1' ) ) );
state_next(262) <= (reset /= '1') and ( ( state_cur(240) and not ( (in7) = '1' ) ) );
state_next(263) <= (reset /= '1') and ( ( state_cur(263) and (NOT(in0)) = '1' ) or state_cur(19) );
state_next(264) <= (reset /= '1') and ( state_cur(315) or ( state_cur(264) and (NOT(in0)) = '1' ) );
state_next(265) <= (reset /= '1') and ( ( state_cur(124) and not ( (NOT(in0)) = '1' ) ) );
state_next(266) <= (reset /= '1') and ( ( state_cur(87) and not ( (NOT(in0)) = '1' ) ) );
state_next(267) <= (reset /= '1') and ( ( state_cur(243) and not ( (NOT(in0)) = '1' ) ) );
state_next(268) <= (reset /= '1') and ( state_cur(103) );
state_next(269) <= (reset /= '1') and ( ( state_cur(269) and (NOT(in0)) = '1' ) or state_cur(257) );
state_next(270) <= (reset /= '1') and ( state_cur(144) );
state_next(271) <= (reset /= '1') and ( ( state_cur(28) and not ( (NOT(in0)) = '1' ) ) );
state_next(272) <= (reset /= '1') and ( ( state_cur(272) and (NOT(in0)) = '1' ) or state_cur(225) );
state_next(273) <= (reset /= '1') and ( ( state_cur(220) and (in6) = '1' ) );
state_next(274) <= (reset /= '1') and ( state_cur(134) );
state_next(275) <= (reset /= '1') and ( ( state_cur(75) and not ( (NOT(in0)) = '1' ) ) );
state_next(276) <= (reset /= '1') and ( (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114) );
state_next(277) <= (reset /= '1') and ( ( state_cur(67) and not ( (NOT(in0)) = '1' ) ) );
state_next(278) <= (reset /= '1') and ( ( state_cur(278) and (NOT(in0)) = '1' ) or state_cur(265) );
state_next(279) <= (reset /= '1') and ( ( state_cur(279) and (NOT(in0)) = '1' ) or state_cur(3) );
state_next(280) <= (reset /= '1') and ( state_cur(281) );
state_next(281) <= (reset /= '1') and ( ( state_cur(208) and not ( (in5) = '1' ) ) );
state_next(282) <= (reset /= '1') and ( state_cur(100) );
state_next(283) <= (reset /= '1') and ( ( state_cur(10) and not ( (NOT(in0)) = '1' ) ) );
state_next(284) <= (reset /= '1') and ( ( state_cur(264) and not ( (NOT(in0)) = '1' ) ) );
state_next(285) <= (reset /= '1') and ( state_cur(286) or ( state_cur(285) and (NOT(in0)) = '1' ) );
state_next(286) <= (reset /= '1') and ( ( state_cur(313) and not ( (NOT(in0)) = '1' ) ) );
state_next(287) <= (reset /= '1') and ( ( state_cur(287) and (NOT(in0)) = '1' ) or state_cur(177) );
state_next(288) <= (reset /= '1') and ( ( state_cur(288) and (NOT(in0)) = '1' ) or state_cur(45) );
state_next(289) <= (reset /= '1') and ( state_cur(210) );
state_next(290) <= (reset /= '1') and ( (state_cur(290) = '1' and rtmcmp290 = '0') or state_cur(291) );
state_next(291) <= (reset /= '1') and ( ( state_cur(240) and (in7) = '1' ) );
state_next(292) <= (reset /= '1') and ( state_cur(147) );
state_next(293) <= (reset /= '1') and ( ( state_cur(295) and not ( (NOT(in0)) = '1' ) ) );
state_next(294) <= (reset /= '1') and ( state_cur(132) );
state_next(295) <= (reset /= '1') and ( ( state_cur(295) and (NOT(in0)) = '1' ) or state_cur(113) );
state_next(296) <= (reset /= '1') and ( state_cur(268) or state_cur(178) );
state_next(297) <= (reset /= '1') and ( ( state_cur(297) and (NOT(in0)) = '1' ) or state_cur(0) );
state_next(298) <= (reset /= '1') and ( state_cur(143) );
state_next(299) <= (reset /= '1') and ( ( state_cur(194) and not ( (NOT(in0)) = '1' ) ) );
state_next(300) <= (reset /= '1') and ( state_cur(142) );
state_next(301) <= (reset /= '1') and ( state_cur(108) );
state_next(302) <= (reset /= '1') and ( ( state_cur(302) and (NOT(in0)) = '1' ) or state_cur(299) );
state_next(303) <= (reset /= '1') and ( rtmcmp128 );
state_next(304) <= (reset /= '1') and ( ( state_cur(304) and (NOT(in0)) = '1' ) or state_cur(39) );
state_next(305) <= (reset /= '1') and ( ( state_cur(305) and (NOT(in0)) = '1' ) or state_cur(30) );
state_next(306) <= (reset /= '1') and ( state_cur(209) );
state_next(307) <= (reset /= '1') and ( ( state_cur(192) and not ( (NOT(in0)) = '1' ) ) );
state_next(308) <= (reset /= '1') and ( ( state_cur(325) and not ( (in10) = '1' ) ) );
state_next(309) <= (reset /= '1') and ( ( state_cur(122) and not ( (NOT(in0)) = '1' ) ) );
state_next(310) <= (reset /= '1') and ( state_cur(308) or state_cur(196) );
state_next(311) <= (reset /= '1') and ( ( state_cur(84) and not ( (NOT(in0)) = '1' ) ) );
state_next(312) <= (reset /= '1') and ( state_cur(119) );
state_next(313) <= (reset /= '1') and ( state_cur(330) or ( state_cur(313) and (NOT(in0)) = '1' ) );
state_next(314) <= (reset /= '1') and ( ( state_cur(314) and (NOT(in0)) = '1' ) or state_cur(59) );
state_next(315) <= (reset /= '1') and ( ( state_cur(121) and not ( (NOT(in0)) = '1' ) ) );
state_next(316) <= (reset /= '1') and ( ( state_cur(316) and (NOT(in0)) = '1' ) or state_cur(63) );
state_next(317) <= (reset /= '1') and ( ( state_cur(317) and (NOT(in0)) = '1' ) or state_cur(74) );
state_next(318) <= (reset /= '1') and ( ( state_cur(318) and (NOT(in0)) = '1' ) or state_cur(262) );
state_next(319) <= (reset /= '1') and ( state_cur(338) );
state_next(320) <= (reset /= '1') and ( ( state_cur(320) and (NOT(in0)) = '1' ) or state_cur(131) );
state_next(321) <= (reset /= '1') and ( ( state_cur(316) and not ( (NOT(in0)) = '1' ) ) );
state_next(322) <= (reset /= '1') and ( state_cur(212) );
state_next(323) <= (reset /= '1') and ( ( state_cur(323) and (NOT(in0)) = '1' ) or state_cur(309) );
state_next(324) <= (reset /= '1') and ( ( state_cur(324) and (NOT(in0)) = '1' ) or state_cur(238) );
state_next(325) <= (reset /= '1') and ( state_cur(109) );
state_next(326) <= (reset /= '1') and ( state_cur(107) );
state_next(327) <= (reset /= '1') and ( ( state_cur(215) and not ( (NOT(in0)) = '1' ) ) );
state_next(328) <= (reset /= '1') and ( state_cur(219) or state_cur(125) );
state_next(329) <= (reset /= '1') and ( ( state_cur(305) and not ( (NOT(in0)) = '1' ) ) );
state_next(330) <= (reset /= '1') and ( ( state_cur(317) and not ( (NOT(in0)) = '1' ) ) );
state_next(331) <= (reset /= '1') and ( state_cur(213) );
state_next(332) <= (reset /= '1') and ( state_cur(335) );
state_next(333) <= (reset /= '1') and ( ( state_cur(150) and not ( (in3) = '1' ) ) );
state_next(334) <= (reset /= '1') and ( state_cur(96) );
state_next(335) <= (reset /= '1') and ( state_cur(182) );
state_next(336) <= (reset /= '1') and ( ( state_cur(328) and (in11) = '1' ) );
state_next(337) <= (reset /= '1') and ( rtmcmp92 );
state_next(338) <= (reset /= '1') and ( state_cur(193) );
state_next(339) <= (reset /= '1') and ( state_cur(94) );
state_next(340) <= (reset /= '1') and ( state_cur(93) );
state_next(341) <= (reset /= '1') and ( state_cur(522) );
state_next(342) <= (reset /= '1') and ( state_cur(341) );
state_next(343) <= (reset /= '1') and ( state_cur(344) or ( state_cur(343) and (NOT(in1)) = '1' ) );
state_next(344) <= (reset /= '1') and ( ( state_cur(345) and not ( (NOT(in1)) = '1' ) ) );
state_next(345) <= (reset /= '1') and ( state_cur(346) or ( state_cur(345) and (NOT(in1)) = '1' ) );
state_next(346) <= (reset /= '1') and ( ( state_cur(347) and not ( (NOT(in1)) = '1' ) ) );
state_next(347) <= (reset /= '1') and ( state_cur(348) or ( state_cur(347) and (NOT(in1)) = '1' ) );
state_next(348) <= (reset /= '1') and ( ( state_cur(349) and not ( (NOT(in1)) = '1' ) ) );
state_next(349) <= (reset /= '1') and ( state_cur(350) or ( state_cur(349) and (NOT(in1)) = '1' ) );
state_next(350) <= (reset /= '1') and ( ( state_cur(351) and not ( (NOT(in1)) = '1' ) ) );
state_next(351) <= (reset /= '1') and ( state_cur(352) or ( state_cur(351) and (NOT(in1)) = '1' ) );
state_next(352) <= (reset /= '1') and ( ( state_cur(353) and not ( (NOT(in1)) = '1' ) ) );
state_next(353) <= (reset /= '1') and ( state_cur(354) or ( state_cur(353) and (NOT(in1)) = '1' ) );
state_next(354) <= (reset /= '1') and ( ( state_cur(355) and not ( (NOT(in1)) = '1' ) ) );
state_next(355) <= (reset /= '1') and ( state_cur(356) or ( state_cur(355) and (NOT(in1)) = '1' ) );
state_next(356) <= (reset /= '1') and ( ( state_cur(357) and not ( (NOT(in1)) = '1' ) ) );
state_next(357) <= (reset /= '1') and ( state_cur(358) or ( state_cur(357) and (NOT(in1)) = '1' ) );
state_next(358) <= (reset /= '1') and ( ( state_cur(359) and not ( (NOT(in1)) = '1' ) ) );
state_next(359) <= (reset /= '1') and ( state_cur(360) or ( state_cur(359) and (NOT(in1)) = '1' ) );
state_next(360) <= (reset /= '1') and ( ( state_cur(361) and not ( (NOT(in1)) = '1' ) ) );
state_next(361) <= (reset /= '1') and ( state_cur(362) or ( state_cur(361) and (NOT(in1)) = '1' ) );
state_next(362) <= (reset /= '1') and ( ( state_cur(363) and not ( (NOT(in1)) = '1' ) ) );
state_next(363) <= (reset /= '1') and ( state_cur(364) or ( state_cur(363) and (NOT(in1)) = '1' ) );
state_next(364) <= (reset /= '1') and ( ( state_cur(365) and not ( (NOT(in1)) = '1' ) ) );
state_next(365) <= (reset /= '1') and ( state_cur(366) or ( state_cur(365) and (NOT(in1)) = '1' ) );
state_next(366) <= (reset /= '1') and ( ( state_cur(367) and not ( (NOT(in1)) = '1' ) ) );
state_next(367) <= (reset /= '1') and ( state_cur(368) or ( state_cur(367) and (NOT(in1)) = '1' ) );
state_next(368) <= (reset /= '1') and ( ( state_cur(369) and not ( (NOT(in1)) = '1' ) ) );
state_next(369) <= (reset /= '1') and ( state_cur(370) or ( state_cur(369) and (NOT(in1)) = '1' ) );
state_next(370) <= (reset /= '1') and ( ( state_cur(371) and not ( (NOT(in1)) = '1' ) ) );
state_next(371) <= (reset /= '1') and ( state_cur(372) or ( state_cur(371) and (NOT(in1)) = '1' ) );
state_next(372) <= (reset /= '1') and ( ( state_cur(373) and not ( (NOT(in1)) = '1' ) ) );
state_next(373) <= (reset /= '1') and ( state_cur(374) or ( state_cur(373) and (NOT(in1)) = '1' ) );
state_next(374) <= (reset /= '1') and ( ( state_cur(375) and not ( (NOT(in1)) = '1' ) ) );
state_next(375) <= (reset /= '1') and ( state_cur(376) or ( state_cur(375) and (NOT(in1)) = '1' ) );
state_next(376) <= (reset /= '1') and ( ( state_cur(377) and not ( (NOT(in1)) = '1' ) ) );
state_next(377) <= (reset /= '1') and ( state_cur(378) or ( state_cur(377) and (NOT(in1)) = '1' ) );
state_next(378) <= (reset /= '1') and ( ( state_cur(379) and not ( (NOT(in1)) = '1' ) ) );
state_next(379) <= (reset /= '1') and ( state_cur(380) or ( state_cur(379) and (NOT(in1)) = '1' ) );
state_next(380) <= (reset /= '1') and ( ( state_cur(381) and not ( (NOT(in1)) = '1' ) ) );
state_next(381) <= (reset /= '1') and ( state_cur(382) or ( state_cur(381) and (NOT(in1)) = '1' ) );
state_next(382) <= (reset /= '1') and ( ( state_cur(383) and not ( (NOT(in1)) = '1' ) ) );
state_next(383) <= (reset /= '1') and ( state_cur(384) or ( state_cur(383) and (NOT(in1)) = '1' ) );
state_next(384) <= (reset /= '1') and ( ( state_cur(385) and not ( (NOT(in1)) = '1' ) ) );
state_next(385) <= (reset /= '1') and ( state_cur(386) or ( state_cur(385) and (NOT(in1)) = '1' ) );
state_next(386) <= (reset /= '1') and ( ( state_cur(387) and not ( (NOT(in1)) = '1' ) ) );
state_next(387) <= (reset /= '1') and ( state_cur(388) or ( state_cur(387) and (NOT(in1)) = '1' ) );
state_next(388) <= (reset /= '1') and ( ( state_cur(389) and not ( (NOT(in1)) = '1' ) ) );
state_next(389) <= (reset /= '1') and ( state_cur(390) or ( state_cur(389) and (NOT(in1)) = '1' ) );
state_next(390) <= (reset /= '1') and ( ( state_cur(391) and not ( (NOT(in1)) = '1' ) ) );
state_next(391) <= (reset /= '1') and ( state_cur(392) or ( state_cur(391) and (NOT(in1)) = '1' ) );
state_next(392) <= (reset /= '1') and ( ( state_cur(393) and not ( (NOT(in1)) = '1' ) ) );
state_next(393) <= (reset /= '1') and ( state_cur(394) or ( state_cur(393) and (NOT(in1)) = '1' ) );
state_next(394) <= (reset /= '1') and ( ( state_cur(395) and not ( (NOT(in1)) = '1' ) ) );
state_next(395) <= (reset /= '1') and ( state_cur(396) or ( state_cur(395) and (NOT(in1)) = '1' ) );
state_next(396) <= (reset /= '1') and ( ( state_cur(397) and not ( (NOT(in1)) = '1' ) ) );
state_next(397) <= (reset /= '1') and ( state_cur(398) or ( state_cur(397) and (NOT(in1)) = '1' ) );
state_next(398) <= (reset /= '1') and ( ( state_cur(399) and not ( (NOT(in1)) = '1' ) ) );
state_next(399) <= (reset /= '1') and ( state_cur(400) or ( state_cur(399) and (NOT(in1)) = '1' ) );
state_next(400) <= (reset /= '1') and ( ( state_cur(401) and not ( (NOT(in1)) = '1' ) ) );
state_next(401) <= (reset /= '1') and ( state_cur(402) or ( state_cur(401) and (NOT(in1)) = '1' ) );
state_next(402) <= (reset /= '1') and ( ( state_cur(403) and not ( (NOT(in1)) = '1' ) ) );
state_next(403) <= (reset /= '1') and ( state_cur(404) or ( state_cur(403) and (NOT(in1)) = '1' ) );
state_next(404) <= (reset /= '1') and ( ( state_cur(405) and not ( (NOT(in1)) = '1' ) ) );
state_next(405) <= (reset /= '1') and ( state_cur(406) or ( state_cur(405) and (NOT(in1)) = '1' ) );
state_next(406) <= (reset /= '1') and ( ( state_cur(407) and not ( (NOT(in1)) = '1' ) ) );
state_next(407) <= (reset /= '1') and ( state_cur(408) or ( state_cur(407) and (NOT(in1)) = '1' ) );
state_next(408) <= (reset /= '1') and ( ( state_cur(409) and not ( (NOT(in1)) = '1' ) ) );
state_next(409) <= (reset /= '1') and ( state_cur(410) or ( state_cur(409) and (NOT(in1)) = '1' ) );
state_next(410) <= (reset /= '1') and ( ( state_cur(411) and not ( (NOT(in1)) = '1' ) ) );
state_next(411) <= (reset /= '1') and ( state_cur(412) or ( state_cur(411) and (NOT(in1)) = '1' ) );
state_next(412) <= (reset /= '1') and ( ( state_cur(413) and not ( (NOT(in1)) = '1' ) ) );
state_next(413) <= (reset /= '1') and ( state_cur(414) or ( state_cur(413) and (NOT(in1)) = '1' ) );
state_next(414) <= (reset /= '1') and ( ( state_cur(415) and not ( (NOT(in1)) = '1' ) ) );
state_next(415) <= (reset /= '1') and ( state_cur(416) or ( state_cur(415) and (NOT(in1)) = '1' ) );
state_next(416) <= (reset /= '1') and ( ( state_cur(417) and not ( (NOT(in1)) = '1' ) ) );
state_next(417) <= (reset /= '1') and ( state_cur(418) or ( state_cur(417) and (NOT(in1)) = '1' ) );
state_next(418) <= (reset /= '1') and ( ( state_cur(419) and not ( (NOT(in1)) = '1' ) ) );
state_next(419) <= (reset /= '1') and ( state_cur(420) or ( state_cur(419) and (NOT(in1)) = '1' ) );
state_next(420) <= (reset /= '1') and ( ( state_cur(421) and not ( (NOT(in1)) = '1' ) ) );
state_next(421) <= (reset /= '1') and ( state_cur(422) or ( state_cur(421) and (NOT(in1)) = '1' ) );
state_next(422) <= (reset /= '1') and ( ( state_cur(423) and not ( (NOT(in1)) = '1' ) ) );
state_next(423) <= (reset /= '1') and ( state_cur(424) or ( state_cur(423) and (NOT(in1)) = '1' ) );
state_next(424) <= (reset /= '1') and ( ( state_cur(425) and not ( (NOT(in1)) = '1' ) ) );
state_next(425) <= (reset /= '1') and ( state_cur(426) or ( state_cur(425) and (NOT(in1)) = '1' ) );
state_next(426) <= (reset /= '1') and ( ( state_cur(427) and not ( (NOT(in1)) = '1' ) ) );
state_next(427) <= (reset /= '1') and ( state_cur(428) or ( state_cur(427) and (NOT(in1)) = '1' ) );
state_next(428) <= (reset /= '1') and ( ( state_cur(429) and not ( (NOT(in1)) = '1' ) ) );
state_next(429) <= (reset /= '1') and ( state_cur(430) or ( state_cur(429) and (NOT(in1)) = '1' ) );
state_next(430) <= (reset /= '1') and ( ( state_cur(431) and not ( (NOT(in1)) = '1' ) ) );
state_next(431) <= (reset /= '1') and ( state_cur(432) or ( state_cur(431) and (NOT(in1)) = '1' ) );
state_next(432) <= (reset /= '1') and ( ( state_cur(433) and not ( (NOT(in1)) = '1' ) ) );
state_next(433) <= (reset /= '1') and ( state_cur(434) or ( state_cur(433) and (NOT(in1)) = '1' ) );
state_next(434) <= (reset /= '1') and ( ( state_cur(435) and not ( (NOT(in1)) = '1' ) ) );
state_next(435) <= (reset /= '1') and ( state_cur(436) or ( state_cur(435) and (NOT(in1)) = '1' ) );
state_next(436) <= (reset /= '1') and ( ( state_cur(437) and not ( (NOT(in1)) = '1' ) ) );
state_next(437) <= (reset /= '1') and ( state_cur(438) or ( state_cur(437) and (NOT(in1)) = '1' ) );
state_next(438) <= (reset /= '1') and ( ( state_cur(439) and not ( (NOT(in1)) = '1' ) ) );
state_next(439) <= (reset /= '1') and ( state_cur(440) or ( state_cur(439) and (NOT(in1)) = '1' ) );
state_next(440) <= (reset /= '1') and ( ( state_cur(441) and not ( (NOT(in1)) = '1' ) ) );
state_next(441) <= (reset /= '1') and ( state_cur(442) or ( state_cur(441) and (NOT(in1)) = '1' ) );
state_next(442) <= (reset /= '1') and ( ( state_cur(443) and not ( (NOT(in1)) = '1' ) ) );
state_next(443) <= (reset /= '1') and ( state_cur(444) or ( state_cur(443) and (NOT(in1)) = '1' ) );
state_next(444) <= (reset /= '1') and ( ( state_cur(445) and not ( (NOT(in1)) = '1' ) ) );
state_next(445) <= (reset /= '1') and ( state_cur(446) or ( state_cur(445) and (NOT(in1)) = '1' ) );
state_next(446) <= (reset /= '1') and ( ( state_cur(447) and not ( (NOT(in1)) = '1' ) ) );
state_next(447) <= (reset /= '1') and ( state_cur(448) or ( state_cur(447) and (NOT(in1)) = '1' ) );
state_next(448) <= (reset /= '1') and ( ( state_cur(449) and not ( (NOT(in1)) = '1' ) ) );
state_next(449) <= (reset /= '1') and ( state_cur(450) or ( state_cur(449) and (NOT(in1)) = '1' ) );
state_next(450) <= (reset /= '1') and ( ( state_cur(451) and not ( (NOT(in1)) = '1' ) ) );
state_next(451) <= (reset /= '1') and ( state_cur(452) or ( state_cur(451) and (NOT(in1)) = '1' ) );
state_next(452) <= (reset /= '1') and ( ( state_cur(453) and not ( (NOT(in1)) = '1' ) ) );
state_next(453) <= (reset /= '1') and ( state_cur(454) or ( state_cur(453) and (NOT(in1)) = '1' ) );
state_next(454) <= (reset /= '1') and ( ( state_cur(455) and not ( (NOT(in1)) = '1' ) ) );
state_next(455) <= (reset /= '1') and ( state_cur(456) or ( state_cur(455) and (NOT(in1)) = '1' ) );
state_next(456) <= (reset /= '1') and ( ( state_cur(457) and not ( (NOT(in1)) = '1' ) ) );
state_next(457) <= (reset /= '1') and ( state_cur(458) or ( state_cur(457) and (NOT(in1)) = '1' ) );
state_next(458) <= (reset /= '1') and ( ( state_cur(459) and not ( (NOT(in1)) = '1' ) ) );
state_next(459) <= (reset /= '1') and ( state_cur(460) or ( state_cur(459) and (NOT(in1)) = '1' ) );
state_next(460) <= (reset /= '1') and ( ( state_cur(461) and not ( (NOT(in1)) = '1' ) ) );
state_next(461) <= (reset /= '1') and ( state_cur(462) or ( state_cur(461) and (NOT(in1)) = '1' ) );
state_next(462) <= (reset /= '1') and ( ( state_cur(463) and not ( (NOT(in1)) = '1' ) ) );
state_next(463) <= (reset /= '1') and ( state_cur(464) or ( state_cur(463) and (NOT(in1)) = '1' ) );
state_next(464) <= (reset /= '1') and ( ( state_cur(465) and not ( (NOT(in1)) = '1' ) ) );
state_next(465) <= (reset /= '1') and ( state_cur(466) or ( state_cur(465) and (NOT(in1)) = '1' ) );
state_next(466) <= (reset /= '1') and ( ( state_cur(467) and not ( (NOT(in1)) = '1' ) ) );
state_next(467) <= (reset /= '1') and ( state_cur(468) or ( state_cur(467) and (NOT(in1)) = '1' ) );
state_next(468) <= (reset /= '1') and ( ( state_cur(469) and not ( (NOT(in1)) = '1' ) ) );
state_next(469) <= (reset /= '1') and ( state_cur(470) or ( state_cur(469) and (NOT(in1)) = '1' ) );
state_next(470) <= (reset /= '1') and ( ( state_cur(471) and not ( (NOT(in1)) = '1' ) ) );
state_next(471) <= (reset /= '1') and ( state_cur(472) or ( state_cur(471) and (NOT(in1)) = '1' ) );
state_next(472) <= (reset /= '1') and ( ( state_cur(473) and not ( (NOT(in1)) = '1' ) ) );
state_next(473) <= (reset /= '1') and ( state_cur(474) or ( state_cur(473) and (NOT(in1)) = '1' ) );
state_next(474) <= (reset /= '1') and ( ( state_cur(475) and not ( (NOT(in1)) = '1' ) ) );
state_next(475) <= (reset /= '1') and ( state_cur(476) or ( state_cur(475) and (NOT(in1)) = '1' ) );
state_next(476) <= (reset /= '1') and ( ( state_cur(477) and not ( (NOT(in1)) = '1' ) ) );
state_next(477) <= (reset /= '1') and ( state_cur(478) or ( state_cur(477) and (NOT(in1)) = '1' ) );
state_next(478) <= (reset /= '1') and ( ( state_cur(479) and not ( (NOT(in1)) = '1' ) ) );
state_next(479) <= (reset /= '1') and ( state_cur(480) or ( state_cur(479) and (NOT(in1)) = '1' ) );
state_next(480) <= (reset /= '1') and ( ( state_cur(481) and not ( (NOT(in1)) = '1' ) ) );
state_next(481) <= (reset /= '1') and ( state_cur(482) or ( state_cur(481) and (NOT(in1)) = '1' ) );
state_next(482) <= (reset /= '1') and ( ( state_cur(483) and not ( (NOT(in1)) = '1' ) ) );
state_next(483) <= (reset /= '1') and ( state_cur(484) or ( state_cur(483) and (NOT(in1)) = '1' ) );
state_next(484) <= (reset /= '1') and ( ( state_cur(485) and not ( (NOT(in1)) = '1' ) ) );
state_next(485) <= (reset /= '1') and ( state_cur(486) or ( state_cur(485) and (NOT(in1)) = '1' ) );
state_next(486) <= (reset /= '1') and ( ( state_cur(487) and not ( (NOT(in1)) = '1' ) ) );
state_next(487) <= (reset /= '1') and ( state_cur(488) or ( state_cur(487) and (NOT(in1)) = '1' ) );
state_next(488) <= (reset /= '1') and ( ( state_cur(489) and not ( (NOT(in1)) = '1' ) ) );
state_next(489) <= (reset /= '1') and ( state_cur(490) or ( state_cur(489) and (NOT(in1)) = '1' ) );
state_next(490) <= (reset /= '1') and ( ( state_cur(491) and not ( (NOT(in1)) = '1' ) ) );
state_next(491) <= (reset /= '1') and ( state_cur(492) or ( state_cur(491) and (NOT(in1)) = '1' ) );
state_next(492) <= (reset /= '1') and ( ( state_cur(493) and not ( (NOT(in1)) = '1' ) ) );
state_next(493) <= (reset /= '1') and ( state_cur(494) or ( state_cur(493) and (NOT(in1)) = '1' ) );
state_next(494) <= (reset /= '1') and ( ( state_cur(495) and not ( (NOT(in1)) = '1' ) ) );
state_next(495) <= (reset /= '1') and ( state_cur(496) or ( state_cur(495) and (NOT(in1)) = '1' ) );
state_next(496) <= (reset /= '1') and ( ( state_cur(497) and not ( (NOT(in1)) = '1' ) ) );
state_next(497) <= (reset /= '1') and ( state_cur(498) or ( state_cur(497) and (NOT(in1)) = '1' ) );
state_next(498) <= (reset /= '1') and ( ( state_cur(499) and not ( (NOT(in1)) = '1' ) ) );
state_next(499) <= (reset /= '1') and ( state_cur(500) or ( state_cur(499) and (NOT(in1)) = '1' ) );
state_next(500) <= (reset /= '1') and ( ( state_cur(501) and not ( (NOT(in1)) = '1' ) ) );
state_next(501) <= (reset /= '1') and ( state_cur(502) or ( state_cur(501) and (NOT(in1)) = '1' ) );
state_next(502) <= (reset /= '1') and ( ( state_cur(503) and not ( (NOT(in1)) = '1' ) ) );
state_next(503) <= (reset /= '1') and ( state_cur(504) or ( state_cur(503) and (NOT(in1)) = '1' ) );
state_next(504) <= (reset /= '1') and ( ( state_cur(505) and not ( (NOT(in1)) = '1' ) ) );
state_next(505) <= (reset /= '1') and ( state_cur(506) or ( state_cur(505) and (NOT(in1)) = '1' ) );
state_next(506) <= (reset /= '1') and ( ( state_cur(507) and not ( (NOT(in1)) = '1' ) ) );
state_next(507) <= (reset /= '1') and ( state_cur(508) or ( state_cur(507) and (NOT(in1)) = '1' ) );
state_next(508) <= (reset /= '1') and ( ( state_cur(509) and not ( (NOT(in1)) = '1' ) ) );
state_next(509) <= (reset /= '1') and ( state_cur(510) or ( state_cur(509) and (NOT(in1)) = '1' ) );
state_next(510) <= (reset /= '1') and ( ( state_cur(511) and not ( (NOT(in1)) = '1' ) ) );
state_next(511) <= (reset /= '1') and ( state_cur(512) or ( state_cur(511) and (NOT(in1)) = '1' ) );
state_next(512) <= (reset /= '1') and ( ( state_cur(513) and not ( (NOT(in1)) = '1' ) ) );
state_next(513) <= (reset /= '1') and ( state_cur(514) or ( state_cur(513) and (NOT(in1)) = '1' ) );
state_next(514) <= (reset /= '1') and ( ( state_cur(515) and not ( (NOT(in1)) = '1' ) ) );
state_next(515) <= (reset /= '1') and ( state_cur(516) or ( state_cur(515) and (NOT(in1)) = '1' ) );
state_next(516) <= (reset /= '1') and ( ( state_cur(517) and not ( (NOT(in1)) = '1' ) ) );
state_next(517) <= (reset /= '1') and ( state_cur(518) or ( state_cur(517) and (NOT(in1)) = '1' ) );
state_next(518) <= (reset /= '1') and ( ( state_cur(519) and not ( (NOT(in1)) = '1' ) ) );
state_next(519) <= (reset /= '1') and ( ( state_cur(519) and (NOT(in1)) = '1' ) or state_cur(1) );
state_next(520) <= (reset /= '1') and ( ( state_cur(520) and (NOT(in1)) = '1' ) or state_cur(73) );
state_next(521) <= (reset /= '1') and ( ( state_cur(521) and (NOT(in1)) = '1' ) or state_cur(71) );
state_next(522) <= (reset /= '1') and ( ( state_cur(220) and not ( (in6) = '1' ) ) );
state_next(523) <= (reset /= '1') and ( state_cur(149) );
-- Assignment of buffers for buffered outputs
out386_bufn <= state_cur(186) or state_cur(270);
out404_bufn <= (state_cur(290) = '1' and rtmcmp290 = '0') or state_cur(291) or state_cur(173);
out457_bufn <= state_cur(142) or state_cur(190) or state_cur(169);
out841_bufn <= rtmcmp92 or state_cur(189);
out276_bufn <= state_cur(233) or state_cur(274);
out67_bufn <= state_cur(189) or state_cur(282) or state_cur(98) or state_cur(203) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) or state_cur(337);
out239_bufn <= ( state_cur(240) and (in7) = '1' ) or state_cur(523) or state_cur(129);
out259_bufn <= state_cur(268) or state_cur(178) or ( state_cur(220) and (in6) = '1' ) or ( state_cur(150) and (in3) = '1' ) or ( state_cur(175) and (in4) = '1' ) or ( state_cur(208) and (in5) = '1' ) or state_cur(523) or state_cur(129);
out416_bufn <= state_cur(338) or state_cur(143) or state_cur(289) or state_cur(322);
out646_bufn <= state_cur(340) or state_cur(326);
out485_bufn <= ( state_cur(240) and (in7) = '1' ) or ( state_cur(150) and (in3) = '1' );
out935_bufn <= state_cur(193) or state_cur(134);
out463_bufn <= state_cur(338) or state_cur(119) or state_cur(134) or state_cur(233) or state_cur(174);
out120_bufn <= rtmcmp92 or state_cur(100) or state_cur(91) or state_cur(179) or state_cur(228);
out293_bufn <= state_cur(342) or state_cur(303);
out216_bufn <= state_cur(107) or state_cur(212) or rtmcmp128 or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114) or state_cur(326) or state_cur(123) or state_cur(190) or state_cur(186) or rtmcmp290 or state_cur(204) or state_cur(191) or state_cur(303) or rtmcmp276;
out319_bufn <= (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114) or state_cur(99) or state_cur(218) or (state_cur(128) = '1' and rtmcmp128 = '0') or state_cur(296);
out230_bufn <= ( state_cur(220) and (in6) = '1' ) or state_cur(224);
out1_bufn <= ( state_cur(317) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(305) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(215) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(316) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(121) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(84) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(122) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(192) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(194) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(295) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(313) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(264) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(10) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(67) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(75) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(28) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(243) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(87) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(124) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(240) and not ( (in7) = '1' ) ) or ( state_cur(269) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(50) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(64) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(68) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(49) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(171) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(130) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(77) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(302) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(287) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(176) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(216) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(250) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(202) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(318) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(136) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(211) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(120) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(135) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(226) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(279) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(55) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(167) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(165) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(163) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(161) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(159) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(157) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(155) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(101) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(116) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(118) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(127) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(314) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(304) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(112) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(140) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(288) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(217) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(80) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(272) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(297) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(278) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(258) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(256) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(24) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(65) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(246) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(61) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(12) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(104) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(21) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(51) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(52) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(46) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(37) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(41) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(285) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(323) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(35) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(34) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(259) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(33) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(324) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(320) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(117) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(26) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(27) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(14) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(239) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(188) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(263) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(13) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(17) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(207) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(6) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(48) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(201) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(44) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(90) and not ( (NOT(in0)) = '1' ) );
out93_bufn <= state_cur(522) or state_cur(93) or state_cur(96) or state_cur(108) or ( state_cur(220) and (in6) = '1' ) or state_cur(342) or state_cur(340) or state_cur(95) or state_cur(184) or ( state_cur(150) and (in3) = '1' ) or state_cur(187) or ( state_cur(175) and (in4) = '1' ) or ( state_cur(208) and (in5) = '1' ) or state_cur(334) or state_cur(339);
out89_bufn <= state_cur(149) or state_cur(341) or state_cur(522) or state_cur(93) or state_cur(94) or state_cur(96) or state_cur(213) or state_cur(108) or state_cur(281) or state_cur(103) or state_cur(342) or state_cur(340) or state_cur(95) or state_cur(184) or state_cur(183) or state_cur(280) or state_cur(187) or state_cur(331) or state_cur(224) or state_cur(301) or state_cur(200) or state_cur(333) or state_cur(334) or state_cur(339);
out539_bufn <= state_cur(142) or state_cur(190);
out62_bufn <= state_cur(193) or rtmcmp92 or state_cur(107) or state_cur(212) or state_cur(338) or state_cur(119) or rtmcmp128 or state_cur(100) or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114) or state_cur(134) or state_cur(236) or state_cur(189) or state_cur(326) or state_cur(312) or state_cur(123) or state_cur(91) or state_cur(233) or state_cur(190) or state_cur(186) or state_cur(179) or rtmcmp290 or state_cur(282) or state_cur(319) or state_cur(174) or state_cur(204) or state_cur(172) or state_cur(191) or state_cur(303) or state_cur(274) or rtmcmp276 or state_cur(98) or state_cur(203) or state_cur(228) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) or state_cur(337);
out856_bufn <= state_cur(107) or state_cur(147) or state_cur(236);
out451_bufn <= state_cur(123) or state_cur(169);
out287_bufn <= state_cur(332) or state_cur(303);
out315_bufn <= state_cur(268) or state_cur(178) or (state_cur(128) = '1' and rtmcmp128 = '0') or state_cur(296);
out536_bufn <= state_cur(95) or state_cur(190);
out209_bufn <= state_cur(191) or state_cur(200);
out221_bufn <= rtmcmp128 or state_cur(237) or state_cur(197) or rtmcmp276;
out283_bufn <= state_cur(193) or state_cur(236) or state_cur(312) or state_cur(319) or state_cur(172) or state_cur(274);
out368_bufn <= state_cur(213) or ( state_cur(175) and (in4) = '1' );
out516_bufn <= ( state_cur(208) and not ( (in5) = '1' ) ) or state_cur(281) or state_cur(183) or state_cur(280);
out393_bufn <= state_cur(193) or state_cur(212) or state_cur(338) or state_cur(143) or state_cur(210) or state_cur(289) or state_cur(322) or state_cur(204);
out1008_bufn <= state_cur(182) or state_cur(268) or state_cur(178);
out392_bufn <= state_cur(108) or state_cur(204);
out261_bufn <= state_cur(268) or state_cur(178) or state_cur(523) or state_cur(129);
out559_bufn <= state_cur(99) or state_cur(218);
out543_bufn <= state_cur(326) or state_cur(292) or state_cur(123) or state_cur(233);
out895_bufn <= state_cur(219) or state_cur(125) or state_cur(247) or state_cur(242) or state_cur(241) or state_cur(148);
out82_bufn <= ( state_cur(208) and (in5) = '1' ) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336);
out220_bufn <= state_cur(107) or rtmcmp128 or state_cur(147) or state_cur(237) or state_cur(236) or state_cur(197) or rtmcmp276;
out95_bufn <= state_cur(522) or state_cur(93) or state_cur(96) or state_cur(108) or state_cur(342) or state_cur(340) or state_cur(95) or state_cur(184) or state_cur(187) or state_cur(334) or state_cur(339);
out943_bufn <= (state_cur(290) = '1' and rtmcmp290 = '0') or state_cur(291) or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114);
out465_bufn <= state_cur(319) or state_cur(174);
out238_bufn <= ( state_cur(175) and (in4) = '1' ) or state_cur(523) or state_cur(129);
out1025_bufn <= ( state_cur(328) and (in11) = '1' ) or state_cur(268) or state_cur(178);
out132_bufn <= state_cur(146) or state_cur(138) or state_cur(273) or state_cur(105);
out79_bufn <= ( state_cur(328) and (in11) = '1' ) or state_cur(98) or state_cur(228) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336);
out500_bufn <= state_cur(91) or state_cur(282);
out65_bufn <= state_cur(179) or state_cur(337);
out111_bufn <= state_cur(96) or state_cur(95) or state_cur(334);
out420_bufn <= ( state_cur(328) and (in11) = '1' ) or state_cur(306);
out1076_bufn <= state_cur(93) or state_cur(107);
out101_bufn <= state_cur(523) or state_cur(129) or ( state_cur(175) and not ( (in4) = '1' ) );
out106_bufn <= ( state_cur(220) and not ( (in6) = '1' ) ) or state_cur(341) or state_cur(94) or ( state_cur(150) and not ( (in3) = '1' ) ) or state_cur(213) or ( state_cur(208) and not ( (in5) = '1' ) ) or state_cur(281) or state_cur(183) or state_cur(280) or state_cur(224) or state_cur(200) or state_cur(333) or ( state_cur(175) and not ( (in4) = '1' ) );
out68_bufn <= state_cur(193) or rtmcmp92 or state_cur(338) or state_cur(119) or state_cur(100) or state_cur(134) or state_cur(236) or state_cur(189) or state_cur(312) or state_cur(91) or state_cur(233) or state_cur(179) or state_cur(282) or state_cur(319) or state_cur(174) or state_cur(172) or state_cur(274) or state_cur(98) or state_cur(203) or state_cur(228) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) or state_cur(337);
out1069_bufn <= state_cur(213) or state_cur(212);
out77_bufn <= state_cur(228) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336);
out102_bufn <= state_cur(94) or state_cur(213) or ( state_cur(175) and not ( (in4) = '1' ) );
out394_bufn <= state_cur(193) or state_cur(212) or state_cur(210) or state_cur(204);
out342_bufn <= ( state_cur(220) and (in6) = '1' ) or ( state_cur(150) and (in3) = '1' ) or ( state_cur(175) and (in4) = '1' ) or ( state_cur(208) and (in5) = '1' );
out104_bufn <= ( state_cur(220) and not ( (in6) = '1' ) ) or state_cur(341) or state_cur(94) or ( state_cur(150) and not ( (in3) = '1' ) ) or state_cur(213) or ( state_cur(208) and not ( (in5) = '1' ) ) or state_cur(281) or ( state_cur(220) and (in6) = '1' ) or state_cur(146) or state_cur(138) or state_cur(183) or state_cur(280) or ( state_cur(150) and (in3) = '1' ) or ( state_cur(175) and (in4) = '1' ) or ( state_cur(208) and (in5) = '1' ) or state_cur(224) or state_cur(200) or state_cur(273) or state_cur(105) or state_cur(333) or ( state_cur(175) and not ( (in4) = '1' ) );
out361_bufn <= state_cur(338) or state_cur(172);
out116_bufn <= ( state_cur(150) and not ( (in3) = '1' ) ) or state_cur(200) or state_cur(333);
out595_bufn <= state_cur(119) or state_cur(237) or state_cur(236) or state_cur(312);
out1004_bufn <= state_cur(143) or state_cur(132);
out227_bufn <= state_cur(123) or state_cur(224);
out109_bufn <= state_cur(186) or state_cur(334);
out619_bufn <= state_cur(237) or state_cur(312);
out410_bufn <= state_cur(335) or state_cur(143) or state_cur(132) or state_cur(322);
out989_bufn <= ( state_cur(150) and not ( (in3) = '1' ) ) or ( state_cur(240) and (in7) = '1' );
out431_bufn <= state_cur(184) or state_cur(187);
out938_bufn <= state_cur(94) or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114);
out525_bufn <= state_cur(96) or rtmcmp290;
out73_bufn <= rtmcmp92 or (state_cur(290) = '1' and rtmcmp290 = '0') or state_cur(291) or state_cur(91) or state_cur(203) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) or state_cur(337);
out837_bufn <= state_cur(522) or state_cur(108) or state_cur(342);
out860_bufn <= state_cur(119) or state_cur(236);
out228_bufn <= ( state_cur(220) and not ( (in6) = '1' ) ) or state_cur(341) or state_cur(224);
out421_bufn <= ( state_cur(328) and (in11) = '1' ) or ( state_cur(325) and not ( (in10) = '1' ) ) or ( state_cur(97) and not ( (NOT(in0)) = '1' ) ) or state_cur(306);
out409_bufn <= state_cur(132) or state_cur(322);
out473_bufn <= state_cur(99) or state_cur(218) or ( state_cur(325) and (in10) = '1' ) or ( state_cur(310) and not ( (in9) = '1' ) );
out509_bufn <= state_cur(123) or state_cur(223);
out94_bufn <= rtmcmp276 or state_cur(339);
out1048_bufn <= state_cur(341) or rtmcmp128;
out98_bufn <= state_cur(93) or state_cur(340) or state_cur(339);
out945_bufn <= ( state_cur(240) and (in7) = '1' ) or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114);
out156_bufn <= ( state_cur(328) and (in11) = '1' ) or state_cur(98);
out152_bufn <= state_cur(100) or state_cur(203);
-- Assignment of non-buffered outputs
out80 <=
state_cur(92);
out576 <=
state_cur(200);
out1103 <=
state_cur(336);
out438 <=
state_cur(151);
out171 <=
state_cur(222) or state_cur(102);
out378 <=
state_cur(340) or state_cur(222) or state_cur(138);
out940 <=
state_cur(276);
out131 <=
state_cur(99);
out376 <=
state_cur(138);
out891 <=
state_cur(237);
out611 <=
state_cur(209);
out638 <=
state_cur(222) or state_cur(209);
out354 <=
state_cur(129);
out7 <=
state_cur(3);
out1127 <=
state_cur(339);
out888 <=
state_cur(237);
out1141 <=
state_cur(348);
out6 <=
state_cur(2);
out1200 <=
state_cur(466);
out1148 <=
state_cur(362);
out250 <=
state_cur(114);
out1100 <=
state_cur(335);
out1168 <=
state_cur(402);
out1158 <=
state_cur(382);
out581 <=
state_cur(204);
out549 <=
state_cur(222) or state_cur(193);
out412 <=
state_cur(145);
out381 <=
state_cur(222) or state_cur(213) or state_cur(138);
out38 <=
state_cur(56);
out100 <=
state_cur(522) or state_cur(342) or state_cur(341) or state_cur(340) or state_cur(339) or state_cur(334) or state_cur(333) or state_cur(331) or
state_cur(301) or state_cur(281) or state_cur(280) or state_cur(224) or state_cur(213) or state_cur(200) or state_cur(187) or state_cur(184) or
state_cur(183) or state_cur(149) or state_cur(108) or state_cur(103) or state_cur(96) or state_cur(95) or state_cur(94) or state_cur(93);
out1181 <=
state_cur(428);
out22 <=
state_cur(20);
out56 <=
state_cur(85);
out224 <=
state_cur(326) or state_cur(303) or state_cur(292) or rtmcmp276 or state_cur(237) or state_cur(236) or state_cur(233) or state_cur(197) or
state_cur(147) or rtmcmp128 or state_cur(123) or state_cur(107);
out1115 <=
state_cur(336);
out191 <=
state_cur(102);
out290 <=
state_cur(123);
out1226 <=
state_cur(518);
out921 <=
state_cur(271);
out535 <=
state_cur(191);
out489 <=
state_cur(178);
out13 <=
state_cur(8);
out1161 <=
state_cur(388);
out408 <=
state_cur(144);
out1197 <=
state_cur(460);
out521 <=
state_cur(184);
out128 <=
state_cur(296) or state_cur(218) or state_cur(114) or state_cur(99);
out440 <=
state_cur(154);
out330 <=
state_cur(128);
out1003 <=
state_cur(294);
out1145 <=
state_cur(356);
out1156 <=
state_cur(378);
out497 <=
state_cur(268) or state_cur(222) or state_cur(178);
out52 <=
state_cur(79);
out659 <=
state_cur(218);
out566 <=
state_cur(197);
out850 <=
state_cur(231);
out1123 <=
state_cur(338);
out558 <=
state_cur(197);
out902 <=
state_cur(248);
out1217 <=
state_cur(500);
out357 <=
state_cur(132);
out229 <=
state_cur(108);
out1096 <=
state_cur(335);
out1188 <=
state_cur(442);
out39 <=
state_cur(57);
out118 <=
state_cur(96);
out387 <=
state_cur(142);
out514 <=
state_cur(183);
out425 <=
state_cur(148);
out508 <=
state_cur(182);
out1155 <=
state_cur(376);
out877 <=
state_cur(236);
out844 <=
state_cur(228);
out237 <=
state_cur(113);
out1133 <=
state_cur(341);
out1046 <=
state_cur(301);
out365 <=
state_cur(137);
out858 <=
state_cur(233);
out873 <=
state_cur(235);
out909 <=
state_cur(260);
out846 <=
state_cur(230);
out484 <=
state_cur(177);
out836 <=
state_cur(224);
out898 <=
state_cur(242);
out1196 <=
state_cur(458);
out26 <=
state_cur(30);
out1147 <=
state_cur(360);
out744 <=
state_cur(342) or state_cur(273) or state_cur(222);
out1026 <=
state_cur(296);
out430 <=
state_cur(149);
out962 <=
state_cur(281);
out45 <=
state_cur(66);
out9 <=
state_cur(5);
out1002 <=
state_cur(294);
out1139 <=
state_cur(344);
out1143 <=
state_cur(352);
out1173 <=
state_cur(412);
out28 <=
state_cur(32);
out1092 <=
state_cur(334);
out1140 <=
state_cur(346);
out40 <=
state_cur(58);
out119 <=
state_cur(98);
out382 <=
state_cur(139);
out241 <=
state_cur(114);
out91 <=
state_cur(93);
out920 <=
state_cur(270);
out986 <=
state_cur(290);
out657 <=
state_cur(222) or state_cur(218);
out375 <=
state_cur(331) or state_cur(222) or state_cur(138);
out866 <=
state_cur(235);
out577 <=
state_cur(203);
out1159 <=
state_cur(384);
out236 <=
state_cur(111);
out367 <=
state_cur(339) or state_cur(222) or state_cur(138);
out1130 <=
state_cur(340);
out25 <=
state_cur(25);
out258 <=
state_cur(222) or state_cur(114);
out990 <=
state_cur(291);
out900 <=
state_cur(244);
out748 <=
state_cur(273) or state_cur(224) or state_cur(222);
out1219 <=
state_cur(504);
out552 <=
state_cur(196);
out852 <=
state_cur(232);
out644 <=
state_cur(222) or state_cur(210);
out4 <=
state_cur(1);
out1142 <=
state_cur(350);
out1089 <=
state_cur(333);
out937 <=
state_cur(275);
out291 <=
state_cur(335) or state_cur(332) or state_cur(303) or state_cur(169) or rtmcmp128 or state_cur(123);
out482 <=
state_cur(222) or state_cur(175);
out924 <=
state_cur(273);
out1218 <=
state_cur(502);
out590 <=
state_cur(205);
out20 <=
state_cur(18);
out114 <=
state_cur(222) or state_cur(178) or state_cur(96);
out30 <=
state_cur(38);
out1224 <=
state_cur(514);
out107 <=
state_cur(95);
out915 <=
state_cur(268);
out34 <=
state_cur(45);
out1213 <=
state_cur(492);
out33 <=
state_cur(43);
out530 <=
state_cur(187);
out1191 <=
state_cur(448);
out223 <=
state_cur(107);
out834 <=
state_cur(231) or state_cur(223);
out1038 <=
state_cur(298);
out454 <=
state_cur(170);
out1087 <=
state_cur(332);
out233 <=
state_cur(109);
out66 <=
state_cur(91);
out347 <=
state_cur(222) or state_cur(149) or state_cur(129);
out848 <=
state_cur(231);
out746 <=
state_cur(301) or state_cur(273) or state_cur(222);
out695 <=
state_cur(232) or state_cur(222);
out1203 <=
state_cur(472);
out1085 <=
state_cur(332);
out1157 <=
state_cur(380);
out1039 <=
state_cur(298);
out532 <=
state_cur(189);
out1138 <=
state_cur(342);
out441 <=
state_cur(156);
out845 <=
state_cur(229);
out48 <=
state_cur(71);
out593 <=
state_cur(222) or state_cur(208);
out1182 <=
state_cur(430);
out57 <=
state_cur(88);
out44 <=
state_cur(63);
out1183 <=
state_cur(432);
out29 <=
state_cur(36);
out1015 <=
state_cur(296);
out910 <=
state_cur(261);
out524 <=
state_cur(186);
out958 <=
state_cur(280);
out460 <=
state_cur(300) or state_cur(204) or state_cur(191) or state_cur(170);
out50 <=
state_cur(74);
out304 <=
state_cur(126);
out130 <=
state_cur(222) or state_cur(99);
out833 <=
state_cur(223);
out513 <=
rtmcmp290 or state_cur(223) or state_cur(182);
out1210 <=
state_cur(486);
out370 <=
state_cur(222) or state_cur(146) or state_cur(138);
out481 <=
state_cur(175);
out207 <=
state_cur(103);
out445 <=
state_cur(164);
out362 <=
state_cur(134);
out908 <=
state_cur(257);
out1186 <=
state_cur(438);
out466 <=
state_cur(172);
out1083 <=
state_cur(331);
out475 <=
state_cur(173);
out19 <=
state_cur(16);
out645 <=
state_cur(212);
out582 <=
state_cur(222) or state_cur(204);
out547 <=
state_cur(193);
out1154 <=
state_cur(374);
out854 <=
state_cur(232);
out208 <=
state_cur(222) or state_cur(178) or state_cur(103);
out975 <=
state_cur(286);
out1150 <=
state_cur(366);
out503 <=
state_cur(179);
out650 <=
state_cur(213);
out863 <=
state_cur(234);
out1211 <=
state_cur(488);
out1228 <=
state_cur(522);
out5 <=
state_cur(518) or state_cur(516) or state_cur(514) or state_cur(512) or state_cur(510) or state_cur(508) or state_cur(506) or state_cur(504) or
state_cur(502) or state_cur(500) or state_cur(498) or state_cur(496) or state_cur(494) or state_cur(492) or state_cur(490) or state_cur(488) or
state_cur(486) or state_cur(484) or state_cur(482) or state_cur(480) or state_cur(478) or state_cur(476) or state_cur(474) or state_cur(472) or
state_cur(470) or state_cur(468) or state_cur(466) or state_cur(464) or state_cur(462) or state_cur(460) or state_cur(458) or state_cur(456) or
state_cur(454) or state_cur(452) or state_cur(450) or state_cur(448) or state_cur(446) or state_cur(444) or state_cur(442) or state_cur(440) or
state_cur(438) or state_cur(436) or state_cur(434) or state_cur(432) or state_cur(430) or state_cur(428) or state_cur(426) or state_cur(424) or
state_cur(422) or state_cur(420) or state_cur(418) or state_cur(416) or state_cur(414) or state_cur(412) or state_cur(410) or state_cur(408) or
state_cur(406) or state_cur(404) or state_cur(402) or state_cur(400) or state_cur(398) or state_cur(396) or state_cur(394) or state_cur(392) or
state_cur(390) or state_cur(388) or state_cur(386) or state_cur(384) or state_cur(382) or state_cur(380) or state_cur(378) or state_cur(376) or
state_cur(374) or state_cur(372) or state_cur(370) or state_cur(368) or state_cur(366) or state_cur(364) or state_cur(362) or state_cur(360) or
state_cur(358) or state_cur(356) or state_cur(354) or state_cur(352) or state_cur(350) or state_cur(348) or state_cur(346) or state_cur(344) or
state_cur(214) or state_cur(198) or state_cur(195) or state_cur(180) or state_cur(125) or state_cur(115) or state_cur(85) or state_cur(83) or
state_cur(79) or state_cur(73) or state_cur(71) or state_cur(1);
out1081 <=
state_cur(330);
out980 <=
rtmcmp290;
out533 <=
state_cur(190);
out338 <=
state_cur(280) or state_cur(222) or state_cur(129);
out32 <=
state_cur(40);
out1080 <=
state_cur(329);
out27 <=
state_cur(31);
out893 <=
state_cur(238);
out397 <=
state_cur(143);
out1000 <=
state_cur(293);
out55 <=
state_cur(83);
out235 <=
state_cur(109);
out1198 <=
state_cur(462);
out12 <=
state_cur(7);
out1221 <=
state_cur(508);
out277 <=
state_cur(119);
out1205 <=
state_cur(476);
out321 <=
state_cur(338) or state_cur(322) or state_cur(319) or state_cur(298) or state_cur(289) or rtmcmp276 or state_cur(237) or state_cur(197) or
state_cur(151) or state_cur(145) or state_cur(143) or rtmcmp128;
out1216 <=
state_cur(498);
out999 <=
state_cur(292);
out1190 <=
state_cur(446);
out1078 <=
state_cur(327);
out17 <=
state_cur(521) or state_cur(520) or state_cur(519) or state_cur(517) or state_cur(515) or state_cur(513) or state_cur(511) or state_cur(509) or
state_cur(507) or state_cur(505) or state_cur(503) or state_cur(501) or state_cur(499) or state_cur(497) or state_cur(495) or state_cur(493) or
state_cur(491) or state_cur(489) or state_cur(487) or state_cur(485) or state_cur(483) or state_cur(481) or state_cur(479) or state_cur(477) or
state_cur(475) or state_cur(473) or state_cur(471) or state_cur(469) or state_cur(467) or state_cur(465) or state_cur(463) or state_cur(461) or
state_cur(459) or state_cur(457) or state_cur(455) or state_cur(453) or state_cur(451) or state_cur(449) or state_cur(447) or state_cur(445) or
state_cur(443) or state_cur(441) or state_cur(439) or state_cur(437) or state_cur(435) or state_cur(433) or state_cur(431) or state_cur(429) or
state_cur(427) or state_cur(425) or state_cur(423) or state_cur(421) or state_cur(419) or state_cur(417) or state_cur(415) or state_cur(413) or
state_cur(411) or state_cur(409) or state_cur(407) or state_cur(405) or state_cur(403) or state_cur(401) or state_cur(399) or state_cur(397) or
state_cur(395) or state_cur(393) or state_cur(391) or state_cur(389) or state_cur(387) or state_cur(385) or state_cur(383) or state_cur(381) or
state_cur(379) or state_cur(377) or state_cur(375) or state_cur(373) or state_cur(371) or state_cur(369) or state_cur(367) or state_cur(365) or
state_cur(363) or state_cur(361) or state_cur(359) or state_cur(357) or state_cur(355) or state_cur(353) or state_cur(351) or state_cur(349) or
state_cur(347) or state_cur(345) or state_cur(343) or state_cur(255) or state_cur(110) or state_cur(106) or state_cur(86) or state_cur(78) or
state_cur(72) or state_cur(42) or state_cur(29) or state_cur(11);
out1209 <=
state_cur(484);
out70 <=
state_cur(337) or state_cur(336) or state_cur(282) or state_cur(228) or state_cur(203) or state_cur(189) or state_cur(179) or state_cur(102) or
state_cur(100) or state_cur(98) or rtmcmp92 or state_cur(91);
out1077 <=
state_cur(326);
out1215 <=
state_cur(496);
out285 <=
state_cur(338) or state_cur(319) or state_cur(312) or state_cur(274) or state_cur(236) or state_cur(233) or state_cur(209) or state_cur(193) or
state_cur(174) or state_cur(172) or state_cur(134) or state_cur(119);
out1206 <=
state_cur(478);
out1175 <=
state_cur(416);
out1222 <=
state_cur(510);
out443 <=
state_cur(160);
out212 <=
state_cur(105);
out270 <=
state_cur(296) or state_cur(114);
out865 <=
state_cur(234);
out648 <=
state_cur(222) or state_cur(212);
out1176 <=
state_cur(418);
out1174 <=
state_cur(414);
out54 <=
state_cur(82);
out706 <=
state_cur(296) or state_cur(222);
out913 <=
state_cur(266);
out24 <=
state_cur(23);
out1164 <=
state_cur(394);
out729 <=
state_cur(341) or state_cur(273) or state_cur(222);
out1204 <=
state_cur(474);
out573 <=
state_cur(199);
out480 <=
state_cur(222) or state_cur(174);
out14 <=
state_cur(9);
out1073 <=
state_cur(325);
out974 <=
state_cur(284);
out358 <=
state_cur(222) or state_cur(132);
out504 <=
state_cur(180);
out21 <=
state_cur(19);
out37 <=
state_cur(54);
out541 <=
state_cur(222) or state_cur(191);
out1071 <=
state_cur(322);
out23 <=
state_cur(22);
out1122 <=
state_cur(337);
out8 <=
state_cur(4);
out839 <=
state_cur(225);
out35 <=
state_cur(47);
out988 <=
state_cur(291);
out419 <=
state_cur(147);
out976 <=
state_cur(289);
out973 <=
state_cur(283);
out58 <=
state_cur(89);
out424 <=
state_cur(306) or state_cur(148);
out450 <=
state_cur(222) or state_cur(170);
out1068 <=
state_cur(321);
out1170 <=
state_cur(406);
out1067 <=
state_cur(319);
out1225 <=
state_cur(516);
out1187 <=
state_cur(440);
out563 <=
state_cur(222) or state_cur(197);
out1178 <=
state_cur(422);
out31 <=
state_cur(39);
out51 <=
state_cur(76);
out1171 <=
state_cur(408);
out41 <=
state_cur(59);
out360 <=
state_cur(133);
out1162 <=
state_cur(390);
out403 <=
state_cur(144);
out1179 <=
state_cur(424);
out1212 <=
state_cur(490);
out1189 <=
state_cur(444);
out1166 <=
state_cur(398);
out42 <=
state_cur(60);
out1220 <=
state_cur(506);
out137 <=
state_cur(99);
out643 <=
state_cur(210);
out692 <=
rtmcmp276 or state_cur(222);
out43 <=
state_cur(62);
out972 <=
state_cur(282);
out472 <=
state_cur(173);
out505 <=
state_cur(181);
out934 <=
state_cur(274);
out1165 <=
state_cur(396);
out494 <=
state_cur(334) or state_cur(222) or state_cur(178);
out1208 <=
state_cur(482);
out1172 <=
state_cur(410);
out550 <=
state_cur(195);
out439 <=
state_cur(152);
out388 <=
rtmcmp290 or state_cur(270) or state_cur(190) or state_cur(186) or state_cur(144) or state_cur(142);
out1195 <=
state_cur(456);
out479 <=
state_cur(174);
out1193 <=
state_cur(452);
out105 <=
state_cur(94);
out903 <=
state_cur(249);
out697 <=
state_cur(300) or state_cur(222);
out1149 <=
state_cur(364);
out49 <=
state_cur(73);
out448 <=
state_cur(169);
out436 <=
state_cur(150);
out917 <=
state_cur(270);
out1064 <=
state_cur(315);
out912 <=
state_cur(265);
out592 <=
state_cur(208);
out1167 <=
state_cur(400);
out719 <=
state_cur(237) or state_cur(222);
out301 <=
state_cur(125);
out1152 <=
state_cur(370);
out1063 <=
state_cur(312);
out1230 <=
state_cur(523);
out46 <=
state_cur(69);
out47 <=
state_cur(70);
out351 <=
state_cur(222) or state_cur(184) or state_cur(129);
out1169 <=
state_cur(404);
out491 <=
state_cur(222) or state_cur(200) or state_cur(178);
out1061 <=
state_cur(311);
out434 <=
state_cur(150);
out76 <=
state_cur(337) or state_cur(336) or state_cur(326) or state_cur(322) or state_cur(303) or state_cur(296) or state_cur(291) or rtmcmp290 or
rtmcmp276 or state_cur(212) or state_cur(204) or state_cur(203) or state_cur(191) or state_cur(190) or state_cur(186) or state_cur(143) or
state_cur(132) or rtmcmp128 or state_cur(123) or state_cur(114) or state_cur(107) or state_cur(100) or rtmcmp92 or state_cur(91);
out840 <=
state_cur(227);
out88 <=
state_cur(336) or state_cur(296) or state_cur(291) or rtmcmp290 or rtmcmp276 or rtmcmp128 or state_cur(114) or rtmcmp92;
out356 <=
state_cur(131);
out442 <=
state_cur(158);
out1199 <=
state_cur(464);
out1043 <=
state_cur(300);
out11 <=
state_cur(324) or state_cur(323) or state_cur(320) or state_cur(318) or state_cur(317) or state_cur(316) or state_cur(314) or state_cur(313) or
state_cur(305) or state_cur(304) or state_cur(302) or state_cur(297) or state_cur(295) or state_cur(288) or state_cur(287) or state_cur(285) or
state_cur(279) or state_cur(278) or state_cur(272) or state_cur(269) or state_cur(264) or state_cur(263) or state_cur(259) or state_cur(258) or
state_cur(256) or state_cur(250) or state_cur(246) or state_cur(243) or state_cur(239) or state_cur(226) or state_cur(217) or state_cur(216) or
state_cur(215) or state_cur(211) or state_cur(207) or state_cur(202) or state_cur(201) or state_cur(194) or state_cur(192) or state_cur(188) or
state_cur(176) or state_cur(171) or state_cur(167) or state_cur(165) or state_cur(163) or state_cur(161) or state_cur(159) or state_cur(157) or
state_cur(155) or state_cur(153) or state_cur(140) or state_cur(136) or state_cur(135) or state_cur(130) or state_cur(127) or state_cur(124) or
state_cur(122) or state_cur(121) or state_cur(120) or state_cur(118) or state_cur(117) or state_cur(116) or state_cur(112) or state_cur(104) or
state_cur(101) or state_cur(97) or state_cur(90) or state_cur(87) or state_cur(84) or state_cur(80) or state_cur(77) or state_cur(75) or
state_cur(68) or state_cur(67) or state_cur(65) or state_cur(64) or state_cur(61) or state_cur(55) or state_cur(52) or state_cur(51) or
state_cur(50) or state_cur(49) or state_cur(48) or state_cur(46) or state_cur(44) or state_cur(41) or state_cur(37) or state_cur(35) or
state_cur(34) or state_cur(33) or state_cur(28) or state_cur(27) or state_cur(26) or state_cur(24) or state_cur(21) or state_cur(17) or
state_cur(14) or state_cur(13) or state_cur(12) or state_cur(10) or state_cur(6);
out591 <=
state_cur(206);
out1180 <=
state_cur(426);
out476 <=
state_cur(291) or state_cur(173);
out1059 <=
state_cur(310);
out92 <=
state_cur(222) or state_cur(138) or state_cur(93);
out418 <=
state_cur(146);
out1042 <=
state_cur(299);
out1057 <=
state_cur(309);
out213 <=
state_cur(273) or state_cur(222) or state_cur(105);
out444 <=
state_cur(162);
out1153 <=
state_cur(372);
out1056 <=
state_cur(336) or state_cur(308);
out957 <=
state_cur(277);
out344 <=
state_cur(222) or state_cur(183) or state_cur(129);
out545 <=
state_cur(212) or state_cur(210) or state_cur(204) or state_cur(193);
out1055 <=
state_cur(308);
out968 <=
state_cur(282);
out335 <=
state_cur(222) or rtmcmp128;
out226 <=
state_cur(273) or state_cur(222) or state_cur(108);
out905 <=
state_cur(252);
out1177 <=
state_cur(420);
out904 <=
state_cur(251);
out1053 <=
state_cur(307);
out1052 <=
state_cur(306);
out417 <=
state_cur(145);
out1201 <=
state_cur(468);
out1163 <=
state_cur(392);
out2 <=
state_cur(330) or state_cur(329) or state_cur(327) or state_cur(321) or state_cur(315) or state_cur(311) or state_cur(309) or state_cur(307) or
state_cur(299) or state_cur(293) or state_cur(286) or state_cur(284) or state_cur(283) or state_cur(277) or state_cur(275) or state_cur(271) or
state_cur(267) or state_cur(266) or state_cur(265) or state_cur(262) or state_cur(261) or state_cur(260) or state_cur(257) or state_cur(254) or
state_cur(253) or state_cur(252) or state_cur(251) or state_cur(249) or state_cur(248) or state_cur(244) or state_cur(238) or state_cur(230) or
state_cur(229) or state_cur(227) or state_cur(225) or state_cur(221) or state_cur(206) or state_cur(205) or state_cur(199) or state_cur(185) or
state_cur(181) or state_cur(177) or state_cur(168) or state_cur(166) or state_cur(164) or state_cur(162) or state_cur(160) or state_cur(158) or
state_cur(156) or state_cur(154) or state_cur(139) or state_cur(137) or state_cur(133) or state_cur(131) or state_cur(126) or state_cur(113) or
state_cur(111) or state_cur(89) or state_cur(88) or state_cur(82) or state_cur(81) or state_cur(76) or state_cur(74) or state_cur(70) or
state_cur(69) or state_cur(66) or state_cur(63) or state_cur(62) or state_cur(60) or state_cur(59) or state_cur(58) or state_cur(57) or
state_cur(56) or state_cur(54) or state_cur(53) or state_cur(47) or state_cur(45) or state_cur(43) or state_cur(40) or state_cur(39) or
state_cur(38) or state_cur(36) or state_cur(32) or state_cur(31) or state_cur(30) or state_cur(25) or state_cur(23) or state_cur(22) or
state_cur(20) or state_cur(19) or state_cur(18) or state_cur(16) or state_cur(15) or state_cur(9) or state_cur(8) or state_cur(7) or
state_cur(5) or state_cur(4) or state_cur(3) or state_cur(2) or state_cur(0);
out447 <=
state_cur(168);
out1202 <=
state_cur(470);
out1192 <=
state_cur(450);
out1050 <=
state_cur(303);
out1144 <=
state_cur(354);
out0 <=
state_cur(0);
out446 <=
state_cur(166);
out914 <=
state_cur(267);
out1194 <=
state_cur(454);
out906 <=
state_cur(253);
out1146 <=
state_cur(358);
out572 <=
state_cur(198);
out1223 <=
state_cur(512);
out53 <=
state_cur(81);
out36 <=
state_cur(53);
out355 <=
state_cur(222) or state_cur(187) or state_cur(129);
out1184 <=
state_cur(434);
out907 <=
state_cur(254);
out1207 <=
state_cur(480);
out18 <=
state_cur(15);
out108 <=
state_cur(222) or state_cur(178) or state_cur(95);
out1160 <=
state_cur(386);
out662 <=
state_cur(218);
out303 <=
state_cur(247) or state_cur(242) or state_cur(241) or state_cur(197) or state_cur(152) or state_cur(148) or state_cur(125);
out1214 <=
state_cur(494);
out1185 <=
state_cur(436);
out341 <=
state_cur(523) or state_cur(222) or state_cur(129);
out1151 <=
state_cur(368);
out652 <=
state_cur(214);
out390 <=
state_cur(222) or state_cur(143);
out523 <=
state_cur(185);
out686 <=
state_cur(222);
out155 <=
state_cur(100);
out682 <=
state_cur(221);
out680 <=
state_cur(222) or state_cur(220);
out679 <=
state_cur(220);
out678 <=
state_cur(222) or state_cur(219);
out677 <=
state_cur(219);
-- Assignment of buffered outputs
out386 <= out386_buf;
out404 <= out404_buf;
out457 <= out457_buf;
out841 <= out841_buf;
out276 <= out276_buf;
out67 <= out67_buf;
out239 <= out239_buf;
out259 <= out259_buf;
out416 <= out416_buf;
out646 <= out646_buf;
out485 <= out485_buf;
out935 <= out935_buf;
out463 <= out463_buf;
out120 <= out120_buf;
out293 <= out293_buf;
out216 <= out216_buf;
out319 <= out319_buf;
out230 <= out230_buf;
out1 <= out1_buf;
out93 <= out93_buf;
out89 <= out89_buf;
out539 <= out539_buf;
out62 <= out62_buf;
out856 <= out856_buf;
out451 <= out451_buf;
out287 <= out287_buf;
out315 <= out315_buf;
out536 <= out536_buf;
out209 <= out209_buf;
out221 <= out221_buf;
out283 <= out283_buf;
out368 <= out368_buf;
out516 <= out516_buf;
out393 <= out393_buf;
out1008 <= out1008_buf;
out392 <= out392_buf;
out261 <= out261_buf;
out559 <= out559_buf;
out543 <= out543_buf;
out895 <= out895_buf;
out82 <= out82_buf;
out220 <= out220_buf;
out95 <= out95_buf;
out943 <= out943_buf;
out465 <= out465_buf;
out238 <= out238_buf;
out1025 <= out1025_buf;
out132 <= out132_buf;
out79 <= out79_buf;
out500 <= out500_buf;
out65 <= out65_buf;
out111 <= out111_buf;
out420 <= out420_buf;
out1076 <= out1076_buf;
out101 <= out101_buf;
out106 <= out106_buf;
out68 <= out68_buf;
out1069 <= out1069_buf;
out77 <= out77_buf;
out102 <= out102_buf;
out394 <= out394_buf;
out342 <= out342_buf;
out104 <= out104_buf;
out361 <= out361_buf;
out116 <= out116_buf;
out595 <= out595_buf;
out1004 <= out1004_buf;
out227 <= out227_buf;
out109 <= out109_buf;
out619 <= out619_buf;
out410 <= out410_buf;
out989 <= out989_buf;
out431 <= out431_buf;
out938 <= out938_buf;
out525 <= out525_buf;
out73 <= out73_buf;
out837 <= out837_buf;
out860 <= out860_buf;
out228 <= out228_buf;
out421 <= out421_buf;
out409 <= out409_buf;
out473 <= out473_buf;
out509 <= out509_buf;
out94 <= out94_buf;
out1048 <= out1048_buf;
out98 <= out98_buf;
out945 <= out945_buf;
out156 <= out156_buf;
out152 <= out152_buf;
-- Retiming: the comparators
rtmcmp92 <= '1' when state_cur(92) = '1' and rtmcounter0 = 1 else '0';
rtmcmp128 <= '1' when state_cur(128) = '1' and rtmcounter0 = 1 else '0';
rtmcmp276 <= '1' when state_cur(276) = '1' and rtmcounter0 = 1 else '0';
rtmcmp290 <= '1' when state_cur(290) = '1' and rtmcounter0 = 1 else '0';
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity fsm_163 is
port (
clock : in std_logic;
reset : in std_logic;
out91 : out std_logic;
out92 : out std_logic;
out93 : out std_logic;
in7 : in std_logic;
out94 : out std_logic;
out95 : out std_logic;
out98 : out std_logic;
out100 : out std_logic;
out101 : out std_logic;
out102 : out std_logic;
out104 : out std_logic;
out105 : out std_logic;
out106 : out std_logic;
out107 : out std_logic;
out108 : out std_logic;
out109 : out std_logic;
out111 : out std_logic;
out114 : out std_logic;
out116 : out std_logic;
out118 : out std_logic;
out119 : out std_logic;
out120 : out std_logic;
out128 : out std_logic;
out130 : out std_logic;
out131 : out std_logic;
out132 : out std_logic;
out137 : out std_logic;
in8 : in std_logic;
out152 : out std_logic;
out155 : out std_logic;
out156 : out std_logic;
out31 : out std_logic;
in2 : in std_logic;
out28 : out std_logic;
out29 : out std_logic;
out30 : out std_logic;
out26 : out std_logic;
out27 : out std_logic;
out24 : out std_logic;
out25 : out std_logic;
out77 : out std_logic;
out79 : out std_logic;
out80 : out std_logic;
out82 : out std_logic;
out34 : out std_logic;
out35 : out std_logic;
out36 : out std_logic;
out32 : out std_logic;
out33 : out std_logic;
out40 : out std_logic;
out41 : out std_logic;
out88 : out std_logic;
out89 : out std_logic;
out21 : out std_logic;
out22 : out std_logic;
out23 : out std_logic;
out73 : out std_logic;
out76 : out std_logic;
in6 : in std_logic;
out70 : out std_logic;
out12 : out std_logic;
out13 : out std_logic;
out14 : out std_logic;
out17 : out std_logic;
out18 : out std_logic;
out19 : out std_logic;
out20 : out std_logic;
out9 : out std_logic;
out11 : out std_logic;
out8 : out std_logic;
out2 : out std_logic;
out4 : out std_logic;
out5 : out std_logic;
in1 : in std_logic;
out6 : out std_logic;
out7 : out std_logic;
out0 : out std_logic;
out1 : out std_logic;
out37 : out std_logic;
out38 : out std_logic;
out39 : out std_logic;
out1222 : out std_logic;
out1223 : out std_logic;
out1224 : out std_logic;
out1225 : out std_logic;
out1226 : out std_logic;
out1228 : out std_logic;
out1230 : out std_logic;
in0 : in std_logic;
out67 : out std_logic;
out68 : out std_logic;
out65 : out std_logic;
out66 : out std_logic;
in5 : in std_logic;
out62 : out std_logic;
out58 : out std_logic;
out56 : out std_logic;
in4 : in std_logic;
out57 : out std_logic;
out54 : out std_logic;
out55 : out std_logic;
out51 : out std_logic;
out52 : out std_logic;
out53 : out std_logic;
in3 : in std_logic;
out46 : out std_logic;
out47 : out std_logic;
out48 : out std_logic;
out49 : out std_logic;
out50 : out std_logic;
out42 : out std_logic;
out43 : out std_logic;
out44 : out std_logic;
out45 : out std_logic;
in9 : in std_logic;
in10 : in std_logic;
out171 : out std_logic;
in11 : in std_logic;
out191 : out std_logic;
out207 : out std_logic;
out208 : out std_logic;
out209 : out std_logic;
out212 : out std_logic;
out213 : out std_logic;
out216 : out std_logic;
out220 : out std_logic;
out221 : out std_logic;
out223 : out std_logic;
out224 : out std_logic;
out226 : out std_logic;
out227 : out std_logic;
out228 : out std_logic;
out229 : out std_logic;
out230 : out std_logic;
out233 : out std_logic;
out235 : out std_logic;
out236 : out std_logic;
out237 : out std_logic;
out238 : out std_logic;
out239 : out std_logic;
out241 : out std_logic;
out250 : out std_logic;
out258 : out std_logic;
out259 : out std_logic;
out261 : out std_logic;
out270 : out std_logic;
out276 : out std_logic;
out277 : out std_logic;
out283 : out std_logic;
out285 : out std_logic;
out287 : out std_logic;
out290 : out std_logic;
out291 : out std_logic;
out293 : out std_logic;
out301 : out std_logic;
out303 : out std_logic;
out304 : out std_logic;
out315 : out std_logic;
out319 : out std_logic;
out321 : out std_logic;
out330 : out std_logic;
out335 : out std_logic;
out338 : out std_logic;
out341 : out std_logic;
out342 : out std_logic;
out344 : out std_logic;
out347 : out std_logic;
out351 : out std_logic;
out354 : out std_logic;
out355 : out std_logic;
out356 : out std_logic;
out357 : out std_logic;
out358 : out std_logic;
out360 : out std_logic;
out361 : out std_logic;
out362 : out std_logic;
out365 : out std_logic;
out367 : out std_logic;
out368 : out std_logic;
out370 : out std_logic;
out375 : out std_logic;
out376 : out std_logic;
out378 : out std_logic;
out381 : out std_logic;
out382 : out std_logic;
out386 : out std_logic;
out387 : out std_logic;
out388 : out std_logic;
out390 : out std_logic;
out392 : out std_logic;
out393 : out std_logic;
out394 : out std_logic;
out397 : out std_logic;
out403 : out std_logic;
out404 : out std_logic;
out408 : out std_logic;
out409 : out std_logic;
out410 : out std_logic;
out412 : out std_logic;
out416 : out std_logic;
out417 : out std_logic;
out418 : out std_logic;
out419 : out std_logic;
out420 : out std_logic;
out421 : out std_logic;
out424 : out std_logic;
out425 : out std_logic;
out430 : out std_logic;
out431 : out std_logic;
out434 : out std_logic;
out436 : out std_logic;
out438 : out std_logic;
out439 : out std_logic;
out440 : out std_logic;
out441 : out std_logic;
out442 : out std_logic;
out443 : out std_logic;
out444 : out std_logic;
out445 : out std_logic;
out446 : out std_logic;
out447 : out std_logic;
out448 : out std_logic;
out450 : out std_logic;
out451 : out std_logic;
out454 : out std_logic;
out457 : out std_logic;
out460 : out std_logic;
out463 : out std_logic;
out465 : out std_logic;
out466 : out std_logic;
out472 : out std_logic;
out473 : out std_logic;
out475 : out std_logic;
out476 : out std_logic;
out479 : out std_logic;
out480 : out std_logic;
out481 : out std_logic;
out482 : out std_logic;
out484 : out std_logic;
out485 : out std_logic;
out489 : out std_logic;
out491 : out std_logic;
out494 : out std_logic;
out497 : out std_logic;
out500 : out std_logic;
out503 : out std_logic;
out504 : out std_logic;
out505 : out std_logic;
out508 : out std_logic;
out509 : out std_logic;
out513 : out std_logic;
out514 : out std_logic;
out516 : out std_logic;
out521 : out std_logic;
out523 : out std_logic;
out524 : out std_logic;
out525 : out std_logic;
out530 : out std_logic;
out532 : out std_logic;
out533 : out std_logic;
out535 : out std_logic;
out536 : out std_logic;
out539 : out std_logic;
out541 : out std_logic;
out543 : out std_logic;
out545 : out std_logic;
out547 : out std_logic;
out549 : out std_logic;
out550 : out std_logic;
out552 : out std_logic;
out558 : out std_logic;
out559 : out std_logic;
out563 : out std_logic;
out566 : out std_logic;
out572 : out std_logic;
out573 : out std_logic;
out576 : out std_logic;
out577 : out std_logic;
out581 : out std_logic;
out582 : out std_logic;
out590 : out std_logic;
out591 : out std_logic;
out592 : out std_logic;
out593 : out std_logic;
out595 : out std_logic;
out611 : out std_logic;
out619 : out std_logic;
out638 : out std_logic;
out643 : out std_logic;
out644 : out std_logic;
out645 : out std_logic;
out646 : out std_logic;
out648 : out std_logic;
out650 : out std_logic;
out652 : out std_logic;
out657 : out std_logic;
out659 : out std_logic;
out662 : out std_logic;
out677 : out std_logic;
out678 : out std_logic;
out679 : out std_logic;
out680 : out std_logic;
out682 : out std_logic;
out686 : out std_logic;
out692 : out std_logic;
out1218 : out std_logic;
out1219 : out std_logic;
out1220 : out std_logic;
out1221 : out std_logic;
out695 : out std_logic;
out697 : out std_logic;
out706 : out std_logic;
out719 : out std_logic;
out729 : out std_logic;
out744 : out std_logic;
out746 : out std_logic;
out748 : out std_logic;
out833 : out std_logic;
out834 : out std_logic;
out836 : out std_logic;
out837 : out std_logic;
out839 : out std_logic;
out840 : out std_logic;
out841 : out std_logic;
out844 : out std_logic;
out845 : out std_logic;
out846 : out std_logic;
out848 : out std_logic;
out850 : out std_logic;
out852 : out std_logic;
out854 : out std_logic;
out856 : out std_logic;
out858 : out std_logic;
out860 : out std_logic;
out863 : out std_logic;
out865 : out std_logic;
out866 : out std_logic;
out873 : out std_logic;
out877 : out std_logic;
out888 : out std_logic;
out891 : out std_logic;
out893 : out std_logic;
out895 : out std_logic;
out898 : out std_logic;
out900 : out std_logic;
out902 : out std_logic;
out903 : out std_logic;
out904 : out std_logic;
out905 : out std_logic;
out906 : out std_logic;
out907 : out std_logic;
out908 : out std_logic;
out909 : out std_logic;
out910 : out std_logic;
out912 : out std_logic;
out913 : out std_logic;
out914 : out std_logic;
out915 : out std_logic;
out917 : out std_logic;
out920 : out std_logic;
out921 : out std_logic;
out924 : out std_logic;
out934 : out std_logic;
out935 : out std_logic;
out937 : out std_logic;
out938 : out std_logic;
out940 : out std_logic;
out943 : out std_logic;
out945 : out std_logic;
out957 : out std_logic;
out958 : out std_logic;
out962 : out std_logic;
out968 : out std_logic;
out972 : out std_logic;
out973 : out std_logic;
out974 : out std_logic;
out975 : out std_logic;
out976 : out std_logic;
out980 : out std_logic;
out986 : out std_logic;
out988 : out std_logic;
out989 : out std_logic;
out990 : out std_logic;
out1004 : out std_logic;
out1008 : out std_logic;
out999 : out std_logic;
out1000 : out std_logic;
out1002 : out std_logic;
out1003 : out std_logic;
out1050 : out std_logic;
out1052 : out std_logic;
out1053 : out std_logic;
out1055 : out std_logic;
out1056 : out std_logic;
out1057 : out std_logic;
out1059 : out std_logic;
out1015 : out std_logic;
out1025 : out std_logic;
out1026 : out std_logic;
out1038 : out std_logic;
out1039 : out std_logic;
out1042 : out std_logic;
out1043 : out std_logic;
out1046 : out std_logic;
out1048 : out std_logic;
out1061 : out std_logic;
out1063 : out std_logic;
out1064 : out std_logic;
out1067 : out std_logic;
out1068 : out std_logic;
out1069 : out std_logic;
out1071 : out std_logic;
out1073 : out std_logic;
out1076 : out std_logic;
out1077 : out std_logic;
out1078 : out std_logic;
out1080 : out std_logic;
out1081 : out std_logic;
out1083 : out std_logic;
out1085 : out std_logic;
out1087 : out std_logic;
out1089 : out std_logic;
out1092 : out std_logic;
out1096 : out std_logic;
out1100 : out std_logic;
out1103 : out std_logic;
out1115 : out std_logic;
out1122 : out std_logic;
out1123 : out std_logic;
out1127 : out std_logic;
out1130 : out std_logic;
out1133 : out std_logic;
out1138 : out std_logic;
out1139 : out std_logic;
out1140 : out std_logic;
out1141 : out std_logic;
out1142 : out std_logic;
out1143 : out std_logic;
out1144 : out std_logic;
out1145 : out std_logic;
out1146 : out std_logic;
out1147 : out std_logic;
out1148 : out std_logic;
out1149 : out std_logic;
out1150 : out std_logic;
out1151 : out std_logic;
out1152 : out std_logic;
out1153 : out std_logic;
out1154 : out std_logic;
out1155 : out std_logic;
out1156 : out std_logic;
out1157 : out std_logic;
out1158 : out std_logic;
out1159 : out std_logic;
out1160 : out std_logic;
out1161 : out std_logic;
out1162 : out std_logic;
out1163 : out std_logic;
out1164 : out std_logic;
out1165 : out std_logic;
out1166 : out std_logic;
out1167 : out std_logic;
out1168 : out std_logic;
out1169 : out std_logic;
out1170 : out std_logic;
out1171 : out std_logic;
out1172 : out std_logic;
out1173 : out std_logic;
out1174 : out std_logic;
out1175 : out std_logic;
out1176 : out std_logic;
out1177 : out std_logic;
out1178 : out std_logic;
out1179 : out std_logic;
out1180 : out std_logic;
out1181 : out std_logic;
out1182 : out std_logic;
out1183 : out std_logic;
out1184 : out std_logic;
out1185 : out std_logic;
out1186 : out std_logic;
out1187 : out std_logic;
out1188 : out std_logic;
out1189 : out std_logic;
out1190 : out std_logic;
out1191 : out std_logic;
out1192 : out std_logic;
out1193 : out std_logic;
out1194 : out std_logic;
out1195 : out std_logic;
out1196 : out std_logic;
out1197 : out std_logic;
out1198 : out std_logic;
out1199 : out std_logic;
out1200 : out std_logic;
out1201 : out std_logic;
out1202 : out std_logic;
out1203 : out std_logic;
out1204 : out std_logic;
out1205 : out std_logic;
out1206 : out std_logic;
out1207 : out std_logic;
out1208 : out std_logic;
out1209 : out std_logic;
out1210 : out std_logic;
out1211 : out std_logic;
out1212 : out std_logic;
out1213 : out std_logic;
out1214 : out std_logic;
out1215 : out std_logic;
out1216 : out std_logic;
out1217 : out std_logic
);
end fsm_163;
architecture augh of fsm_163 is
signal state_cur : std_logic_vector(0 to 523) := (141 => '1', others => '0');
signal state_next : std_logic_vector(0 to 523) := (141 => '1', others => '0');
-- Buffers for outputs
signal out386_buf : std_logic := '0';
signal out386_bufn : std_logic;
signal out404_buf : std_logic := '0';
signal out404_bufn : std_logic;
signal out457_buf : std_logic := '0';
signal out457_bufn : std_logic;
signal out841_buf : std_logic := '0';
signal out841_bufn : std_logic;
signal out276_buf : std_logic := '0';
signal out276_bufn : std_logic;
signal out67_buf : std_logic := '0';
signal out67_bufn : std_logic;
signal out239_buf : std_logic := '0';
signal out239_bufn : std_logic;
signal out259_buf : std_logic := '0';
signal out259_bufn : std_logic;
signal out416_buf : std_logic := '0';
signal out416_bufn : std_logic;
signal out646_buf : std_logic := '0';
signal out646_bufn : std_logic;
signal out485_buf : std_logic := '0';
signal out485_bufn : std_logic;
signal out935_buf : std_logic := '0';
signal out935_bufn : std_logic;
signal out463_buf : std_logic := '0';
signal out463_bufn : std_logic;
signal out120_buf : std_logic := '0';
signal out120_bufn : std_logic;
signal out293_buf : std_logic := '0';
signal out293_bufn : std_logic;
signal out216_buf : std_logic := '0';
signal out216_bufn : std_logic;
signal out319_buf : std_logic := '0';
signal out319_bufn : std_logic;
signal out230_buf : std_logic := '0';
signal out230_bufn : std_logic;
signal out1_buf : std_logic := '0';
signal out1_bufn : std_logic;
signal out93_buf : std_logic := '0';
signal out93_bufn : std_logic;
signal out89_buf : std_logic := '0';
signal out89_bufn : std_logic;
signal out539_buf : std_logic := '0';
signal out539_bufn : std_logic;
signal out62_buf : std_logic := '0';
signal out62_bufn : std_logic;
signal out856_buf : std_logic := '0';
signal out856_bufn : std_logic;
signal out451_buf : std_logic := '0';
signal out451_bufn : std_logic;
signal out287_buf : std_logic := '0';
signal out287_bufn : std_logic;
signal out315_buf : std_logic := '0';
signal out315_bufn : std_logic;
signal out536_buf : std_logic := '0';
signal out536_bufn : std_logic;
signal out209_buf : std_logic := '0';
signal out209_bufn : std_logic;
signal out221_buf : std_logic := '0';
signal out221_bufn : std_logic;
signal out283_buf : std_logic := '0';
signal out283_bufn : std_logic;
signal out368_buf : std_logic := '0';
signal out368_bufn : std_logic;
signal out516_buf : std_logic := '0';
signal out516_bufn : std_logic;
signal out393_buf : std_logic := '0';
signal out393_bufn : std_logic;
signal out1008_buf : std_logic := '0';
signal out1008_bufn : std_logic;
signal out392_buf : std_logic := '0';
signal out392_bufn : std_logic;
signal out261_buf : std_logic := '0';
signal out261_bufn : std_logic;
signal out559_buf : std_logic := '0';
signal out559_bufn : std_logic;
signal out543_buf : std_logic := '0';
signal out543_bufn : std_logic;
signal out895_buf : std_logic := '0';
signal out895_bufn : std_logic;
signal out82_buf : std_logic := '0';
signal out82_bufn : std_logic;
signal out220_buf : std_logic := '0';
signal out220_bufn : std_logic;
signal out95_buf : std_logic := '0';
signal out95_bufn : std_logic;
signal out943_buf : std_logic := '0';
signal out943_bufn : std_logic;
signal out465_buf : std_logic := '0';
signal out465_bufn : std_logic;
signal out238_buf : std_logic := '0';
signal out238_bufn : std_logic;
signal out1025_buf : std_logic := '0';
signal out1025_bufn : std_logic;
signal out132_buf : std_logic := '0';
signal out132_bufn : std_logic;
signal out79_buf : std_logic := '0';
signal out79_bufn : std_logic;
signal out500_buf : std_logic := '0';
signal out500_bufn : std_logic;
signal out65_buf : std_logic := '0';
signal out65_bufn : std_logic;
signal out111_buf : std_logic := '0';
signal out111_bufn : std_logic;
signal out420_buf : std_logic := '0';
signal out420_bufn : std_logic;
signal out1076_buf : std_logic := '0';
signal out1076_bufn : std_logic;
signal out101_buf : std_logic := '0';
signal out101_bufn : std_logic;
signal out106_buf : std_logic := '0';
signal out106_bufn : std_logic;
signal out68_buf : std_logic := '0';
signal out68_bufn : std_logic;
signal out1069_buf : std_logic := '0';
signal out1069_bufn : std_logic;
signal out77_buf : std_logic := '0';
signal out77_bufn : std_logic;
signal out102_buf : std_logic := '0';
signal out102_bufn : std_logic;
signal out394_buf : std_logic := '0';
signal out394_bufn : std_logic;
signal out342_buf : std_logic := '0';
signal out342_bufn : std_logic;
signal out104_buf : std_logic := '0';
signal out104_bufn : std_logic;
signal out361_buf : std_logic := '0';
signal out361_bufn : std_logic;
signal out116_buf : std_logic := '0';
signal out116_bufn : std_logic;
signal out595_buf : std_logic := '0';
signal out595_bufn : std_logic;
signal out1004_buf : std_logic := '0';
signal out1004_bufn : std_logic;
signal out227_buf : std_logic := '0';
signal out227_bufn : std_logic;
signal out109_buf : std_logic := '0';
signal out109_bufn : std_logic;
signal out619_buf : std_logic := '0';
signal out619_bufn : std_logic;
signal out410_buf : std_logic := '0';
signal out410_bufn : std_logic;
signal out989_buf : std_logic := '0';
signal out989_bufn : std_logic;
signal out431_buf : std_logic := '0';
signal out431_bufn : std_logic;
signal out938_buf : std_logic := '0';
signal out938_bufn : std_logic;
signal out525_buf : std_logic := '0';
signal out525_bufn : std_logic;
signal out73_buf : std_logic := '0';
signal out73_bufn : std_logic;
signal out837_buf : std_logic := '0';
signal out837_bufn : std_logic;
signal out860_buf : std_logic := '0';
signal out860_bufn : std_logic;
signal out228_buf : std_logic := '0';
signal out228_bufn : std_logic;
signal out421_buf : std_logic := '0';
signal out421_bufn : std_logic;
signal out409_buf : std_logic := '0';
signal out409_bufn : std_logic;
signal out473_buf : std_logic := '0';
signal out473_bufn : std_logic;
signal out509_buf : std_logic := '0';
signal out509_bufn : std_logic;
signal out94_buf : std_logic := '0';
signal out94_bufn : std_logic;
signal out1048_buf : std_logic := '0';
signal out1048_bufn : std_logic;
signal out98_buf : std_logic := '0';
signal out98_bufn : std_logic;
signal out945_buf : std_logic := '0';
signal out945_bufn : std_logic;
signal out156_buf : std_logic := '0';
signal out156_bufn : std_logic;
signal out152_buf : std_logic := '0';
signal out152_bufn : std_logic;
-- Retiming: counters
signal rtmcounter0 : unsigned(4 downto 0) := (others => '0');
signal rtmcounter0_next : unsigned(4 downto 0);
-- Retiming: Output of comparators
signal rtmcmp92 : std_logic;
signal rtmcmp128 : std_logic;
signal rtmcmp276 : std_logic;
signal rtmcmp290 : std_logic;
-- Don't understand why these two function declarations are needed...
function "/=" (L, R: std_logic) return std_logic is
begin
if L /= R then
return '1';
end if;
return '0';
end function;
function "=" (L, R: std_logic) return std_logic is
begin
if L = R then
return '1';
end if;
return '0';
end function;
begin
-- Sequential process
-- Set the current state
process (clock)
begin
if rising_edge(clock) then
-- Next state
state_cur <= state_next;
-- Buffers for outputs
out386_buf <= out386_bufn;
out404_buf <= out404_bufn;
out457_buf <= out457_bufn;
out841_buf <= out841_bufn;
out276_buf <= out276_bufn;
out67_buf <= out67_bufn;
out239_buf <= out239_bufn;
out259_buf <= out259_bufn;
out416_buf <= out416_bufn;
out646_buf <= out646_bufn;
out485_buf <= out485_bufn;
out935_buf <= out935_bufn;
out463_buf <= out463_bufn;
out120_buf <= out120_bufn;
out293_buf <= out293_bufn;
out216_buf <= out216_bufn;
out319_buf <= out319_bufn;
out230_buf <= out230_bufn;
out1_buf <= out1_bufn;
out93_buf <= out93_bufn;
out89_buf <= out89_bufn;
out539_buf <= out539_bufn;
out62_buf <= out62_bufn;
out856_buf <= out856_bufn;
out451_buf <= out451_bufn;
out287_buf <= out287_bufn;
out315_buf <= out315_bufn;
out536_buf <= out536_bufn;
out209_buf <= out209_bufn;
out221_buf <= out221_bufn;
out283_buf <= out283_bufn;
out368_buf <= out368_bufn;
out516_buf <= out516_bufn;
out393_buf <= out393_bufn;
out1008_buf <= out1008_bufn;
out392_buf <= out392_bufn;
out261_buf <= out261_bufn;
out559_buf <= out559_bufn;
out543_buf <= out543_bufn;
out895_buf <= out895_bufn;
out82_buf <= out82_bufn;
out220_buf <= out220_bufn;
out95_buf <= out95_bufn;
out943_buf <= out943_bufn;
out465_buf <= out465_bufn;
out238_buf <= out238_bufn;
out1025_buf <= out1025_bufn;
out132_buf <= out132_bufn;
out79_buf <= out79_bufn;
out500_buf <= out500_bufn;
out65_buf <= out65_bufn;
out111_buf <= out111_bufn;
out420_buf <= out420_bufn;
out1076_buf <= out1076_bufn;
out101_buf <= out101_bufn;
out106_buf <= out106_bufn;
out68_buf <= out68_bufn;
out1069_buf <= out1069_bufn;
out77_buf <= out77_bufn;
out102_buf <= out102_bufn;
out394_buf <= out394_bufn;
out342_buf <= out342_bufn;
out104_buf <= out104_bufn;
out361_buf <= out361_bufn;
out116_buf <= out116_bufn;
out595_buf <= out595_bufn;
out1004_buf <= out1004_bufn;
out227_buf <= out227_bufn;
out109_buf <= out109_bufn;
out619_buf <= out619_bufn;
out410_buf <= out410_bufn;
out989_buf <= out989_bufn;
out431_buf <= out431_bufn;
out938_buf <= out938_bufn;
out525_buf <= out525_bufn;
out73_buf <= out73_bufn;
out837_buf <= out837_bufn;
out860_buf <= out860_bufn;
out228_buf <= out228_bufn;
out421_buf <= out421_bufn;
out409_buf <= out409_bufn;
out473_buf <= out473_bufn;
out509_buf <= out509_bufn;
out94_buf <= out94_bufn;
out1048_buf <= out1048_bufn;
out98_buf <= out98_bufn;
out945_buf <= out945_bufn;
out156_buf <= out156_bufn;
out152_buf <= out152_bufn;
-- Retiming: counters
rtmcounter0 <= rtmcounter0_next;
end if;
end process;
-- Retiming: the counters
rtmcounter0_next <= rtmcounter0 + 1 when (reset /= '1') and (
(state_cur(290) = '1' and rtmcmp290 = '0') or (state_cur(276) = '1' and rtmcmp276 = '0') or (state_cur(128) = '1' and rtmcmp128 = '0') or (state_cur(92) = '1' and rtmcmp92 = '0')
) else (others => '0');
-- Next state bits
state_next(0) <= (reset /= '1') and ( ( state_cur(90) and not ( (NOT(in0)) = '1' ) ) );
state_next(1) <= (reset /= '1') and ( ( state_cur(86) and not ( (NOT(in1)) = '1' ) ) );
state_next(2) <= (reset /= '1') and ( ( state_cur(44) and not ( (NOT(in0)) = '1' ) ) );
state_next(3) <= (reset /= '1') and ( ( state_cur(201) and not ( (NOT(in0)) = '1' ) ) );
state_next(4) <= (reset /= '1') and ( ( state_cur(48) and not ( (NOT(in0)) = '1' ) ) );
state_next(5) <= (reset /= '1') and ( ( state_cur(6) and not ( (NOT(in0)) = '1' ) ) );
state_next(6) <= (reset /= '1') and ( state_cur(32) or ( state_cur(6) and (NOT(in0)) = '1' ) );
state_next(7) <= (reset /= '1') and ( ( state_cur(207) and not ( (NOT(in0)) = '1' ) ) );
state_next(8) <= (reset /= '1') and ( ( state_cur(17) and not ( (NOT(in0)) = '1' ) ) );
state_next(9) <= (reset /= '1') and ( ( state_cur(13) and not ( (NOT(in0)) = '1' ) ) );
state_next(10) <= (reset /= '1') and ( state_cur(221) or ( state_cur(10) and (NOT(in0)) = '1' ) );
state_next(11) <= (reset /= '1') and ( state_cur(83) or ( state_cur(11) and (NOT(in1)) = '1' ) );
state_next(12) <= (reset /= '1') and ( state_cur(23) or ( state_cur(12) and (NOT(in0)) = '1' ) );
state_next(13) <= (reset /= '1') and ( state_cur(321) or ( state_cur(13) and (NOT(in0)) = '1' ) );
state_next(14) <= (reset /= '1') and ( state_cur(251) or ( state_cur(14) and (NOT(in0)) = '1' ) );
state_next(15) <= (reset /= '1') and ( ( state_cur(263) and not ( (NOT(in0)) = '1' ) ) );
state_next(16) <= (reset /= '1') and ( ( state_cur(188) and not ( (NOT(in0)) = '1' ) ) );
state_next(17) <= (reset /= '1') and ( ( state_cur(17) and (NOT(in0)) = '1' ) or state_cur(9) );
state_next(18) <= (reset /= '1') and ( ( state_cur(239) and not ( (NOT(in0)) = '1' ) ) );
state_next(19) <= (reset /= '1') and ( ( state_cur(14) and not ( (NOT(in0)) = '1' ) ) );
state_next(20) <= (reset /= '1') and ( ( state_cur(27) and not ( (NOT(in0)) = '1' ) ) );
state_next(21) <= (reset /= '1') and ( state_cur(22) or ( state_cur(21) and (NOT(in0)) = '1' ) );
state_next(22) <= (reset /= '1') and ( ( state_cur(26) and not ( (NOT(in0)) = '1' ) ) );
state_next(23) <= (reset /= '1') and ( ( state_cur(117) and not ( (NOT(in0)) = '1' ) ) );
state_next(24) <= (reset /= '1') and ( state_cur(254) or ( state_cur(24) and (NOT(in0)) = '1' ) );
state_next(25) <= (reset /= '1') and ( ( state_cur(320) and not ( (NOT(in0)) = '1' ) ) );
state_next(26) <= (reset /= '1') and ( ( state_cur(26) and (NOT(in0)) = '1' ) or state_cur(25) );
state_next(27) <= (reset /= '1') and ( state_cur(81) or ( state_cur(27) and (NOT(in0)) = '1' ) );
state_next(28) <= (reset /= '1') and ( state_cur(261) or ( state_cur(28) and (NOT(in0)) = '1' ) );
state_next(29) <= (reset /= '1') and ( state_cur(198) or ( state_cur(29) and (NOT(in1)) = '1' ) );
state_next(30) <= (reset /= '1') and ( ( state_cur(324) and not ( (NOT(in0)) = '1' ) ) );
state_next(31) <= (reset /= '1') and ( ( state_cur(33) and not ( (NOT(in0)) = '1' ) ) );
state_next(32) <= (reset /= '1') and ( ( state_cur(259) and not ( (NOT(in0)) = '1' ) ) );
state_next(33) <= (reset /= '1') and ( state_cur(267) or ( state_cur(33) and (NOT(in0)) = '1' ) );
state_next(34) <= (reset /= '1') and ( ( state_cur(34) and (NOT(in0)) = '1' ) or state_cur(31) );
state_next(35) <= (reset /= '1') and ( state_cur(36) or ( state_cur(35) and (NOT(in0)) = '1' ) );
state_next(36) <= (reset /= '1') and ( ( state_cur(34) and not ( (NOT(in0)) = '1' ) ) );
state_next(37) <= (reset /= '1') and ( state_cur(38) or ( state_cur(37) and (NOT(in0)) = '1' ) );
state_next(38) <= (reset /= '1') and ( ( state_cur(35) and not ( (NOT(in0)) = '1' ) ) );
state_next(39) <= (reset /= '1') and ( ( state_cur(323) and not ( (NOT(in0)) = '1' ) ) );
state_next(40) <= (reset /= '1') and ( ( state_cur(285) and not ( (NOT(in0)) = '1' ) ) );
state_next(41) <= (reset /= '1') and ( ( state_cur(41) and (NOT(in0)) = '1' ) or state_cur(8) );
state_next(42) <= (reset /= '1') and ( state_cur(180) or ( state_cur(42) and (NOT(in1)) = '1' ) );
state_next(43) <= (reset /= '1') and ( ( state_cur(41) and not ( (NOT(in0)) = '1' ) ) );
state_next(44) <= (reset /= '1') and ( state_cur(66) or ( state_cur(44) and (NOT(in0)) = '1' ) );
state_next(45) <= (reset /= '1') and ( ( state_cur(37) and not ( (NOT(in0)) = '1' ) ) );
state_next(46) <= (reset /= '1') and ( ( state_cur(46) and (NOT(in0)) = '1' ) or state_cur(43) );
state_next(47) <= (reset /= '1') and ( ( state_cur(46) and not ( (NOT(in0)) = '1' ) ) );
state_next(48) <= (reset /= '1') and ( ( state_cur(48) and (NOT(in0)) = '1' ) or state_cur(40) );
state_next(49) <= (reset /= '1') and ( ( state_cur(49) and (NOT(in0)) = '1' ) or state_cur(18) );
state_next(50) <= (reset /= '1') and ( ( state_cur(50) and (NOT(in0)) = '1' ) or state_cur(47) );
state_next(51) <= (reset /= '1') and ( state_cur(53) or ( state_cur(51) and (NOT(in0)) = '1' ) );
state_next(52) <= (reset /= '1') and ( state_cur(56) or ( state_cur(52) and (NOT(in0)) = '1' ) );
state_next(53) <= (reset /= '1') and ( ( state_cur(52) and not ( (NOT(in0)) = '1' ) ) );
state_next(54) <= (reset /= '1') and ( ( state_cur(51) and not ( (NOT(in0)) = '1' ) ) );
state_next(55) <= (reset /= '1') and ( ( state_cur(55) and (NOT(in0)) = '1' ) or state_cur(54) );
state_next(56) <= (reset /= '1') and ( ( state_cur(21) and not ( (NOT(in0)) = '1' ) ) );
state_next(57) <= (reset /= '1') and ( ( state_cur(104) and not ( (NOT(in0)) = '1' ) ) );
state_next(58) <= (reset /= '1') and ( ( state_cur(12) and not ( (NOT(in0)) = '1' ) ) );
state_next(59) <= (reset /= '1') and ( ( state_cur(61) and not ( (NOT(in0)) = '1' ) ) );
state_next(60) <= (reset /= '1') and ( ( state_cur(246) and not ( (NOT(in0)) = '1' ) ) );
state_next(61) <= (reset /= '1') and ( state_cur(260) or ( state_cur(61) and (NOT(in0)) = '1' ) );
state_next(62) <= (reset /= '1') and ( ( state_cur(65) and not ( (NOT(in0)) = '1' ) ) );
state_next(63) <= (reset /= '1') and ( ( state_cur(24) and not ( (NOT(in0)) = '1' ) ) );
state_next(64) <= (reset /= '1') and ( state_cur(277) or ( state_cur(64) and (NOT(in0)) = '1' ) );
state_next(65) <= (reset /= '1') and ( state_cur(329) or ( state_cur(65) and (NOT(in0)) = '1' ) );
state_next(66) <= (reset /= '1') and ( ( state_cur(256) and not ( (NOT(in0)) = '1' ) ) );
state_next(67) <= (reset /= '1') and ( ( state_cur(67) and (NOT(in0)) = '1' ) or state_cur(62) );
state_next(68) <= (reset /= '1') and ( ( state_cur(68) and (NOT(in0)) = '1' ) or state_cur(60) );
state_next(69) <= (reset /= '1') and ( ( state_cur(258) and not ( (NOT(in0)) = '1' ) ) );
state_next(70) <= (reset /= '1') and ( ( state_cur(278) and not ( (NOT(in0)) = '1' ) ) );
state_next(71) <= (reset /= '1') and ( ( state_cur(255) and not ( (NOT(in1)) = '1' ) ) );
state_next(72) <= (reset /= '1') and ( state_cur(85) or ( state_cur(72) and (NOT(in1)) = '1' ) );
state_next(73) <= (reset /= '1') and ( ( state_cur(106) and not ( (NOT(in1)) = '1' ) ) );
state_next(74) <= (reset /= '1') and ( ( state_cur(297) and not ( (NOT(in0)) = '1' ) ) );
state_next(75) <= (reset /= '1') and ( ( state_cur(75) and (NOT(in0)) = '1' ) or state_cur(57) );
state_next(76) <= (reset /= '1') and ( ( state_cur(272) and not ( (NOT(in0)) = '1' ) ) );
state_next(77) <= (reset /= '1') and ( state_cur(199) or ( state_cur(77) and (NOT(in0)) = '1' ) );
state_next(78) <= (reset /= '1') and ( state_cur(115) or ( state_cur(78) and (NOT(in1)) = '1' ) );
state_next(79) <= (reset /= '1') and ( ( state_cur(42) and not ( (NOT(in1)) = '1' ) ) );
state_next(80) <= (reset /= '1') and ( ( state_cur(80) and (NOT(in0)) = '1' ) or state_cur(7) );
state_next(81) <= (reset /= '1') and ( ( state_cur(80) and not ( (NOT(in0)) = '1' ) ) );
state_next(82) <= (reset /= '1') and ( ( state_cur(217) and not ( (NOT(in0)) = '1' ) ) );
state_next(83) <= (reset /= '1') and ( ( state_cur(72) and not ( (NOT(in1)) = '1' ) ) );
state_next(84) <= (reset /= '1') and ( ( state_cur(84) and (NOT(in0)) = '1' ) or state_cur(82) );
state_next(85) <= (reset /= '1') and ( ( state_cur(29) and not ( (NOT(in1)) = '1' ) ) );
state_next(86) <= (reset /= '1') and ( state_cur(195) or ( state_cur(86) and (NOT(in1)) = '1' ) );
state_next(87) <= (reset /= '1') and ( ( state_cur(87) and (NOT(in0)) = '1' ) or state_cur(20) );
state_next(88) <= (reset /= '1') and ( ( state_cur(288) and not ( (NOT(in0)) = '1' ) ) );
state_next(89) <= (reset /= '1') and ( ( state_cur(140) and not ( (NOT(in0)) = '1' ) ) );
state_next(90) <= (reset /= '1') and ( ( state_cur(90) and (NOT(in0)) = '1' ) or state_cur(89) );
state_next(91) <= (reset /= '1') and ( state_cur(337) );
state_next(92) <= (reset /= '1') and ( (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) );
state_next(93) <= (reset /= '1') and ( state_cur(339) );
state_next(94) <= (reset /= '1') and ( ( state_cur(175) and not ( (in4) = '1' ) ) );
state_next(95) <= (reset /= '1') and ( state_cur(334) );
state_next(96) <= (reset /= '1') and ( state_cur(333) );
state_next(97) <= (reset /= '1') and ( state_cur(244) or ( state_cur(97) and (NOT(in0)) = '1' ) );
state_next(98) <= (reset /= '1') and ( state_cur(228) );
state_next(99) <= (reset /= '1') and ( state_cur(273) or state_cur(105) );
state_next(100) <= (reset /= '1') and ( state_cur(203) );
state_next(101) <= (reset /= '1') and ( ( state_cur(101) and (NOT(in0)) = '1' ) or state_cur(5) );
state_next(102) <= (reset /= '1') and ( state_cur(98) );
state_next(103) <= (reset /= '1') and ( state_cur(200) );
state_next(104) <= (reset /= '1') and ( state_cur(111) or ( state_cur(104) and (NOT(in0)) = '1' ) );
state_next(105) <= (reset /= '1') and ( state_cur(301) );
state_next(106) <= (reset /= '1') and ( state_cur(214) or ( state_cur(106) and (NOT(in1)) = '1' ) );
state_next(107) <= (reset /= '1') and ( rtmcmp276 );
state_next(108) <= (reset /= '1') and ( state_cur(224) );
state_next(109) <= (reset /= '1') and ( ( state_cur(310) and (in9) = '1' ) );
state_next(110) <= (reset /= '1') and ( state_cur(222) or ( state_cur(110) and (NOT(in1)) = '1' ) );
state_next(111) <= (reset /= '1') and ( ( state_cur(112) and not ( (NOT(in0)) = '1' ) ) );
state_next(112) <= (reset /= '1') and ( state_cur(293) or ( state_cur(112) and (NOT(in0)) = '1' ) );
state_next(113) <= (reset /= '1') and ( ( state_cur(304) and not ( (NOT(in0)) = '1' ) ) );
state_next(114) <= (reset /= '1') and ( state_cur(523) or state_cur(129) );
state_next(115) <= (reset /= '1') and ( ( state_cur(110) and not ( (NOT(in1)) = '1' ) ) );
state_next(116) <= (reset /= '1') and ( state_cur(327) or ( state_cur(116) and (NOT(in0)) = '1' ) );
state_next(117) <= (reset /= '1') and ( ( state_cur(117) and (NOT(in0)) = '1' ) or state_cur(2) );
state_next(118) <= (reset /= '1') and ( state_cur(181) or ( state_cur(118) and (NOT(in0)) = '1' ) );
state_next(119) <= (reset /= '1') and ( state_cur(274) );
state_next(120) <= (reset /= '1') and ( ( state_cur(120) and (NOT(in0)) = '1' ) or state_cur(15) );
state_next(121) <= (reset /= '1') and ( state_cur(227) or ( state_cur(121) and (NOT(in0)) = '1' ) );
state_next(122) <= (reset /= '1') and ( ( state_cur(122) and (NOT(in0)) = '1' ) or state_cur(4) );
state_next(123) <= (reset /= '1') and ( state_cur(303) );
state_next(124) <= (reset /= '1') and ( state_cur(133) or ( state_cur(124) and (NOT(in0)) = '1' ) );
state_next(125) <= (reset /= '1') and ( ( state_cur(343) and not ( (NOT(in1)) = '1' ) ) );
state_next(126) <= (reset /= '1') and ( ( state_cur(314) and not ( (NOT(in0)) = '1' ) ) );
state_next(127) <= (reset /= '1') and ( ( state_cur(127) and (NOT(in0)) = '1' ) or state_cur(126) );
state_next(128) <= (reset /= '1') and ( (state_cur(128) = '1' and rtmcmp128 = '0') or state_cur(296) );
state_next(129) <= (reset /= '1') and ( ( state_cur(208) and (in5) = '1' ) );
state_next(130) <= (reset /= '1') and ( state_cur(137) or ( state_cur(130) and (NOT(in0)) = '1' ) );
state_next(131) <= (reset /= '1') and ( ( state_cur(127) and not ( (NOT(in0)) = '1' ) ) );
state_next(132) <= (reset /= '1') and ( state_cur(191) );
state_next(133) <= (reset /= '1') and ( ( state_cur(118) and not ( (NOT(in0)) = '1' ) ) );
state_next(134) <= (reset /= '1') and ( state_cur(172) );
state_next(135) <= (reset /= '1') and ( state_cur(284) or ( state_cur(135) and (NOT(in0)) = '1' ) );
state_next(136) <= (reset /= '1') and ( state_cur(230) or ( state_cur(136) and (NOT(in0)) = '1' ) );
state_next(137) <= (reset /= '1') and ( ( state_cur(116) and not ( (NOT(in0)) = '1' ) ) );
state_next(138) <= (reset /= '1') and ( ( state_cur(175) and (in4) = '1' ) );
state_next(139) <= (reset /= '1') and ( ( state_cur(101) and not ( (NOT(in0)) = '1' ) ) );
state_next(140) <= (reset /= '1') and ( ( state_cur(140) and (NOT(in0)) = '1' ) or state_cur(139) );
state_next(141) <= (reset = '1') or ( ( state_cur(141) and (NOT(in2)) = '1' ) );
state_next(142) <= (reset /= '1') and ( state_cur(270) );
state_next(143) <= (reset /= '1') and ( state_cur(204) );
state_next(144) <= (reset /= '1') and ( state_cur(173) );
state_next(145) <= (reset /= '1') and ( state_cur(322) );
state_next(146) <= (reset /= '1') and ( state_cur(331) );
state_next(147) <= (reset /= '1') and ( state_cur(197) );
state_next(148) <= (reset /= '1') and ( state_cur(306) );
state_next(149) <= (reset /= '1') and ( state_cur(187) );
state_next(150) <= (reset /= '1') and ( state_cur(294) );
state_next(151) <= (reset /= '1') and ( state_cur(289) );
state_next(152) <= (reset /= '1') and ( ( state_cur(153) and not ( (NOT(in0)) = '1' ) ) );
state_next(153) <= (reset /= '1') and ( state_cur(154) or ( state_cur(153) and (NOT(in0)) = '1' ) );
state_next(154) <= (reset /= '1') and ( ( state_cur(155) and not ( (NOT(in0)) = '1' ) ) );
state_next(155) <= (reset /= '1') and ( state_cur(156) or ( state_cur(155) and (NOT(in0)) = '1' ) );
state_next(156) <= (reset /= '1') and ( ( state_cur(157) and not ( (NOT(in0)) = '1' ) ) );
state_next(157) <= (reset /= '1') and ( state_cur(158) or ( state_cur(157) and (NOT(in0)) = '1' ) );
state_next(158) <= (reset /= '1') and ( ( state_cur(159) and not ( (NOT(in0)) = '1' ) ) );
state_next(159) <= (reset /= '1') and ( state_cur(160) or ( state_cur(159) and (NOT(in0)) = '1' ) );
state_next(160) <= (reset /= '1') and ( ( state_cur(161) and not ( (NOT(in0)) = '1' ) ) );
state_next(161) <= (reset /= '1') and ( state_cur(162) or ( state_cur(161) and (NOT(in0)) = '1' ) );
state_next(162) <= (reset /= '1') and ( ( state_cur(163) and not ( (NOT(in0)) = '1' ) ) );
state_next(163) <= (reset /= '1') and ( state_cur(164) or ( state_cur(163) and (NOT(in0)) = '1' ) );
state_next(164) <= (reset /= '1') and ( ( state_cur(165) and not ( (NOT(in0)) = '1' ) ) );
state_next(165) <= (reset /= '1') and ( state_cur(166) or ( state_cur(165) and (NOT(in0)) = '1' ) );
state_next(166) <= (reset /= '1') and ( ( state_cur(167) and not ( (NOT(in0)) = '1' ) ) );
state_next(167) <= (reset /= '1') and ( state_cur(168) or ( state_cur(167) and (NOT(in0)) = '1' ) );
state_next(168) <= (reset /= '1') and ( ( state_cur(55) and not ( (NOT(in0)) = '1' ) ) );
state_next(169) <= (reset /= '1') and ( state_cur(332) );
state_next(170) <= (reset /= '1') and ( state_cur(169) );
state_next(171) <= (reset /= '1') and ( ( state_cur(171) and (NOT(in0)) = '1' ) or state_cur(16) );
state_next(172) <= (reset /= '1') and ( state_cur(174) );
state_next(173) <= (reset /= '1') and ( ( state_cur(325) and (in10) = '1' ) or ( state_cur(310) and not ( (in9) = '1' ) ) );
state_next(174) <= (reset /= '1') and ( state_cur(319) );
state_next(175) <= (reset /= '1') and ( state_cur(170) );
state_next(176) <= (reset /= '1') and ( ( state_cur(176) and (NOT(in0)) = '1' ) or state_cur(70) );
state_next(177) <= (reset /= '1') and ( ( state_cur(279) and not ( (NOT(in0)) = '1' ) ) );
state_next(178) <= (reset /= '1') and ( ( state_cur(150) and (in3) = '1' ) );
state_next(179) <= (reset /= '1') and ( state_cur(282) );
state_next(180) <= (reset /= '1') and ( ( state_cur(520) and not ( (NOT(in1)) = '1' ) ) );
state_next(181) <= (reset /= '1') and ( ( state_cur(226) and not ( (NOT(in0)) = '1' ) ) );
state_next(182) <= (reset /= '1') and ( state_cur(223) );
state_next(183) <= (reset /= '1') and ( state_cur(280) );
state_next(184) <= (reset /= '1') and ( state_cur(183) );
state_next(185) <= (reset /= '1') and ( ( state_cur(135) and not ( (NOT(in0)) = '1' ) ) );
state_next(186) <= (reset /= '1') and ( rtmcmp290 );
state_next(187) <= (reset /= '1') and ( state_cur(184) );
state_next(188) <= (reset /= '1') and ( state_cur(206) or ( state_cur(188) and (NOT(in0)) = '1' ) );
state_next(189) <= (reset /= '1') and ( state_cur(179) );
state_next(190) <= (reset /= '1') and ( state_cur(186) );
state_next(191) <= (reset /= '1') and ( state_cur(190) );
state_next(192) <= (reset /= '1') and ( ( state_cur(192) and (NOT(in0)) = '1' ) or state_cur(76) );
state_next(193) <= (reset /= '1') and ( state_cur(233) );
state_next(194) <= (reset /= '1') and ( state_cur(252) or ( state_cur(194) and (NOT(in0)) = '1' ) );
state_next(195) <= (reset /= '1') and ( ( state_cur(521) and not ( (NOT(in1)) = '1' ) ) );
state_next(196) <= (reset /= '1') and ( state_cur(231) );
state_next(197) <= (reset /= '1') and ( state_cur(218) );
state_next(198) <= (reset /= '1') and ( ( state_cur(78) and not ( (NOT(in1)) = '1' ) ) );
state_next(199) <= (reset /= '1') and ( ( state_cur(120) and not ( (NOT(in0)) = '1' ) ) );
state_next(200) <= (reset /= '1') and ( state_cur(95) );
state_next(201) <= (reset /= '1') and ( state_cur(307) or ( state_cur(201) and (NOT(in0)) = '1' ) );
state_next(202) <= (reset /= '1') and ( state_cur(266) or ( state_cur(202) and (NOT(in0)) = '1' ) );
state_next(203) <= (reset /= '1') and ( state_cur(91) );
state_next(204) <= (reset /= '1') and ( state_cur(123) );
state_next(205) <= (reset /= '1') and ( ( state_cur(211) and not ( (NOT(in0)) = '1' ) ) );
state_next(206) <= (reset /= '1') and ( ( state_cur(136) and not ( (NOT(in0)) = '1' ) ) );
state_next(207) <= (reset /= '1') and ( ( state_cur(207) and (NOT(in0)) = '1' ) or state_cur(205) );
state_next(208) <= (reset /= '1') and ( state_cur(300) );
state_next(209) <= (reset /= '1') and ( state_cur(312) );
state_next(210) <= (reset /= '1') and ( state_cur(292) );
state_next(211) <= (reset /= '1') and ( ( state_cur(211) and (NOT(in0)) = '1' ) or state_cur(185) );
state_next(212) <= (reset /= '1') and ( state_cur(326) );
state_next(213) <= (reset /= '1') and ( state_cur(340) );
state_next(214) <= (reset /= '1') and ( ( state_cur(11) and not ( (NOT(in1)) = '1' ) ) );
state_next(215) <= (reset /= '1') and ( state_cur(229) or ( state_cur(215) and (NOT(in0)) = '1' ) );
state_next(216) <= (reset /= '1') and ( state_cur(248) or ( state_cur(216) and (NOT(in0)) = '1' ) );
state_next(217) <= (reset /= '1') and ( state_cur(271) or ( state_cur(217) and (NOT(in0)) = '1' ) );
state_next(218) <= (reset /= '1') and ( state_cur(146) or state_cur(138) );
state_next(219) <= (reset /= '1') and ( state_cur(151) );
state_next(220) <= (reset /= '1') and ( state_cur(298) );
state_next(221) <= (reset /= '1') and ( ( state_cur(318) and not ( (NOT(in0)) = '1' ) ) );
state_next(222) <= (reset /= '1') and ( state_cur(152) or ( state_cur(141) and not ( (NOT(in2)) = '1' ) ) );
state_next(223) <= (reset /= '1') and ( state_cur(232) );
state_next(224) <= (reset /= '1') and ( state_cur(342) );
state_next(225) <= (reset /= '1') and ( ( state_cur(202) and not ( (NOT(in0)) = '1' ) ) );
state_next(226) <= (reset /= '1') and ( state_cur(311) or ( state_cur(226) and (NOT(in0)) = '1' ) );
state_next(227) <= (reset /= '1') and ( ( state_cur(250) and not ( (NOT(in0)) = '1' ) ) );
state_next(228) <= (reset /= '1') and ( state_cur(189) );
state_next(229) <= (reset /= '1') and ( ( state_cur(216) and not ( (NOT(in0)) = '1' ) ) );
state_next(230) <= (reset /= '1') and ( ( state_cur(176) and not ( (NOT(in0)) = '1' ) ) );
state_next(231) <= (reset /= '1') and ( state_cur(234) );
state_next(232) <= (reset /= '1') and ( state_cur(145) );
state_next(233) <= (reset /= '1') and ( state_cur(236) );
state_next(234) <= (reset /= '1') and ( state_cur(235) );
state_next(235) <= (reset /= '1') and ( state_cur(102) );
state_next(236) <= (reset /= '1') and ( state_cur(237) );
state_next(237) <= (reset /= '1') and ( state_cur(99) );
state_next(238) <= (reset /= '1') and ( ( state_cur(287) and not ( (NOT(in0)) = '1' ) ) );
state_next(239) <= (reset /= '1') and ( ( state_cur(239) and (NOT(in0)) = '1' ) or state_cur(58) );
state_next(240) <= (reset /= '1') and ( state_cur(241) or state_cur(148) );
state_next(241) <= (reset /= '1') and ( ( state_cur(245) and not ( (in8) = '1' ) ) );
state_next(242) <= (reset /= '1') and ( ( state_cur(97) and not ( (NOT(in0)) = '1' ) ) );
state_next(243) <= (reset /= '1') and ( state_cur(275) or ( state_cur(243) and (NOT(in0)) = '1' ) );
state_next(244) <= (reset /= '1') and ( ( state_cur(245) and (in8) = '1' ) );
state_next(245) <= (reset /= '1') and ( state_cur(247) or state_cur(242) );
state_next(246) <= (reset /= '1') and ( state_cur(253) or ( state_cur(246) and (NOT(in0)) = '1' ) );
state_next(247) <= (reset /= '1') and ( ( state_cur(328) and not ( (in11) = '1' ) ) );
state_next(248) <= (reset /= '1') and ( ( state_cur(302) and not ( (NOT(in0)) = '1' ) ) );
state_next(249) <= (reset /= '1') and ( ( state_cur(77) and not ( (NOT(in0)) = '1' ) ) );
state_next(250) <= (reset /= '1') and ( ( state_cur(250) and (NOT(in0)) = '1' ) or state_cur(88) );
state_next(251) <= (reset /= '1') and ( ( state_cur(130) and not ( (NOT(in0)) = '1' ) ) );
state_next(252) <= (reset /= '1') and ( ( state_cur(171) and not ( (NOT(in0)) = '1' ) ) );
state_next(253) <= (reset /= '1') and ( ( state_cur(49) and not ( (NOT(in0)) = '1' ) ) );
state_next(254) <= (reset /= '1') and ( ( state_cur(68) and not ( (NOT(in0)) = '1' ) ) );
state_next(255) <= (reset /= '1') and ( ( state_cur(255) and (NOT(in1)) = '1' ) or state_cur(79) );
state_next(256) <= (reset /= '1') and ( ( state_cur(256) and (NOT(in0)) = '1' ) or state_cur(69) );
state_next(257) <= (reset /= '1') and ( ( state_cur(64) and not ( (NOT(in0)) = '1' ) ) );
state_next(258) <= (reset /= '1') and ( ( state_cur(258) and (NOT(in0)) = '1' ) or state_cur(249) );
state_next(259) <= (reset /= '1') and ( state_cur(283) or ( state_cur(259) and (NOT(in0)) = '1' ) );
state_next(260) <= (reset /= '1') and ( ( state_cur(50) and not ( (NOT(in0)) = '1' ) ) );
state_next(261) <= (reset /= '1') and ( ( state_cur(269) and not ( (NOT(in0)) = '1' ) ) );
state_next(262) <= (reset /= '1') and ( ( state_cur(240) and not ( (in7) = '1' ) ) );
state_next(263) <= (reset /= '1') and ( ( state_cur(263) and (NOT(in0)) = '1' ) or state_cur(19) );
state_next(264) <= (reset /= '1') and ( state_cur(315) or ( state_cur(264) and (NOT(in0)) = '1' ) );
state_next(265) <= (reset /= '1') and ( ( state_cur(124) and not ( (NOT(in0)) = '1' ) ) );
state_next(266) <= (reset /= '1') and ( ( state_cur(87) and not ( (NOT(in0)) = '1' ) ) );
state_next(267) <= (reset /= '1') and ( ( state_cur(243) and not ( (NOT(in0)) = '1' ) ) );
state_next(268) <= (reset /= '1') and ( state_cur(103) );
state_next(269) <= (reset /= '1') and ( ( state_cur(269) and (NOT(in0)) = '1' ) or state_cur(257) );
state_next(270) <= (reset /= '1') and ( state_cur(144) );
state_next(271) <= (reset /= '1') and ( ( state_cur(28) and not ( (NOT(in0)) = '1' ) ) );
state_next(272) <= (reset /= '1') and ( ( state_cur(272) and (NOT(in0)) = '1' ) or state_cur(225) );
state_next(273) <= (reset /= '1') and ( ( state_cur(220) and (in6) = '1' ) );
state_next(274) <= (reset /= '1') and ( state_cur(134) );
state_next(275) <= (reset /= '1') and ( ( state_cur(75) and not ( (NOT(in0)) = '1' ) ) );
state_next(276) <= (reset /= '1') and ( (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114) );
state_next(277) <= (reset /= '1') and ( ( state_cur(67) and not ( (NOT(in0)) = '1' ) ) );
state_next(278) <= (reset /= '1') and ( ( state_cur(278) and (NOT(in0)) = '1' ) or state_cur(265) );
state_next(279) <= (reset /= '1') and ( ( state_cur(279) and (NOT(in0)) = '1' ) or state_cur(3) );
state_next(280) <= (reset /= '1') and ( state_cur(281) );
state_next(281) <= (reset /= '1') and ( ( state_cur(208) and not ( (in5) = '1' ) ) );
state_next(282) <= (reset /= '1') and ( state_cur(100) );
state_next(283) <= (reset /= '1') and ( ( state_cur(10) and not ( (NOT(in0)) = '1' ) ) );
state_next(284) <= (reset /= '1') and ( ( state_cur(264) and not ( (NOT(in0)) = '1' ) ) );
state_next(285) <= (reset /= '1') and ( state_cur(286) or ( state_cur(285) and (NOT(in0)) = '1' ) );
state_next(286) <= (reset /= '1') and ( ( state_cur(313) and not ( (NOT(in0)) = '1' ) ) );
state_next(287) <= (reset /= '1') and ( ( state_cur(287) and (NOT(in0)) = '1' ) or state_cur(177) );
state_next(288) <= (reset /= '1') and ( ( state_cur(288) and (NOT(in0)) = '1' ) or state_cur(45) );
state_next(289) <= (reset /= '1') and ( state_cur(210) );
state_next(290) <= (reset /= '1') and ( (state_cur(290) = '1' and rtmcmp290 = '0') or state_cur(291) );
state_next(291) <= (reset /= '1') and ( ( state_cur(240) and (in7) = '1' ) );
state_next(292) <= (reset /= '1') and ( state_cur(147) );
state_next(293) <= (reset /= '1') and ( ( state_cur(295) and not ( (NOT(in0)) = '1' ) ) );
state_next(294) <= (reset /= '1') and ( state_cur(132) );
state_next(295) <= (reset /= '1') and ( ( state_cur(295) and (NOT(in0)) = '1' ) or state_cur(113) );
state_next(296) <= (reset /= '1') and ( state_cur(268) or state_cur(178) );
state_next(297) <= (reset /= '1') and ( ( state_cur(297) and (NOT(in0)) = '1' ) or state_cur(0) );
state_next(298) <= (reset /= '1') and ( state_cur(143) );
state_next(299) <= (reset /= '1') and ( ( state_cur(194) and not ( (NOT(in0)) = '1' ) ) );
state_next(300) <= (reset /= '1') and ( state_cur(142) );
state_next(301) <= (reset /= '1') and ( state_cur(108) );
state_next(302) <= (reset /= '1') and ( ( state_cur(302) and (NOT(in0)) = '1' ) or state_cur(299) );
state_next(303) <= (reset /= '1') and ( rtmcmp128 );
state_next(304) <= (reset /= '1') and ( ( state_cur(304) and (NOT(in0)) = '1' ) or state_cur(39) );
state_next(305) <= (reset /= '1') and ( ( state_cur(305) and (NOT(in0)) = '1' ) or state_cur(30) );
state_next(306) <= (reset /= '1') and ( state_cur(209) );
state_next(307) <= (reset /= '1') and ( ( state_cur(192) and not ( (NOT(in0)) = '1' ) ) );
state_next(308) <= (reset /= '1') and ( ( state_cur(325) and not ( (in10) = '1' ) ) );
state_next(309) <= (reset /= '1') and ( ( state_cur(122) and not ( (NOT(in0)) = '1' ) ) );
state_next(310) <= (reset /= '1') and ( state_cur(308) or state_cur(196) );
state_next(311) <= (reset /= '1') and ( ( state_cur(84) and not ( (NOT(in0)) = '1' ) ) );
state_next(312) <= (reset /= '1') and ( state_cur(119) );
state_next(313) <= (reset /= '1') and ( state_cur(330) or ( state_cur(313) and (NOT(in0)) = '1' ) );
state_next(314) <= (reset /= '1') and ( ( state_cur(314) and (NOT(in0)) = '1' ) or state_cur(59) );
state_next(315) <= (reset /= '1') and ( ( state_cur(121) and not ( (NOT(in0)) = '1' ) ) );
state_next(316) <= (reset /= '1') and ( ( state_cur(316) and (NOT(in0)) = '1' ) or state_cur(63) );
state_next(317) <= (reset /= '1') and ( ( state_cur(317) and (NOT(in0)) = '1' ) or state_cur(74) );
state_next(318) <= (reset /= '1') and ( ( state_cur(318) and (NOT(in0)) = '1' ) or state_cur(262) );
state_next(319) <= (reset /= '1') and ( state_cur(338) );
state_next(320) <= (reset /= '1') and ( ( state_cur(320) and (NOT(in0)) = '1' ) or state_cur(131) );
state_next(321) <= (reset /= '1') and ( ( state_cur(316) and not ( (NOT(in0)) = '1' ) ) );
state_next(322) <= (reset /= '1') and ( state_cur(212) );
state_next(323) <= (reset /= '1') and ( ( state_cur(323) and (NOT(in0)) = '1' ) or state_cur(309) );
state_next(324) <= (reset /= '1') and ( ( state_cur(324) and (NOT(in0)) = '1' ) or state_cur(238) );
state_next(325) <= (reset /= '1') and ( state_cur(109) );
state_next(326) <= (reset /= '1') and ( state_cur(107) );
state_next(327) <= (reset /= '1') and ( ( state_cur(215) and not ( (NOT(in0)) = '1' ) ) );
state_next(328) <= (reset /= '1') and ( state_cur(219) or state_cur(125) );
state_next(329) <= (reset /= '1') and ( ( state_cur(305) and not ( (NOT(in0)) = '1' ) ) );
state_next(330) <= (reset /= '1') and ( ( state_cur(317) and not ( (NOT(in0)) = '1' ) ) );
state_next(331) <= (reset /= '1') and ( state_cur(213) );
state_next(332) <= (reset /= '1') and ( state_cur(335) );
state_next(333) <= (reset /= '1') and ( ( state_cur(150) and not ( (in3) = '1' ) ) );
state_next(334) <= (reset /= '1') and ( state_cur(96) );
state_next(335) <= (reset /= '1') and ( state_cur(182) );
state_next(336) <= (reset /= '1') and ( ( state_cur(328) and (in11) = '1' ) );
state_next(337) <= (reset /= '1') and ( rtmcmp92 );
state_next(338) <= (reset /= '1') and ( state_cur(193) );
state_next(339) <= (reset /= '1') and ( state_cur(94) );
state_next(340) <= (reset /= '1') and ( state_cur(93) );
state_next(341) <= (reset /= '1') and ( state_cur(522) );
state_next(342) <= (reset /= '1') and ( state_cur(341) );
state_next(343) <= (reset /= '1') and ( state_cur(344) or ( state_cur(343) and (NOT(in1)) = '1' ) );
state_next(344) <= (reset /= '1') and ( ( state_cur(345) and not ( (NOT(in1)) = '1' ) ) );
state_next(345) <= (reset /= '1') and ( state_cur(346) or ( state_cur(345) and (NOT(in1)) = '1' ) );
state_next(346) <= (reset /= '1') and ( ( state_cur(347) and not ( (NOT(in1)) = '1' ) ) );
state_next(347) <= (reset /= '1') and ( state_cur(348) or ( state_cur(347) and (NOT(in1)) = '1' ) );
state_next(348) <= (reset /= '1') and ( ( state_cur(349) and not ( (NOT(in1)) = '1' ) ) );
state_next(349) <= (reset /= '1') and ( state_cur(350) or ( state_cur(349) and (NOT(in1)) = '1' ) );
state_next(350) <= (reset /= '1') and ( ( state_cur(351) and not ( (NOT(in1)) = '1' ) ) );
state_next(351) <= (reset /= '1') and ( state_cur(352) or ( state_cur(351) and (NOT(in1)) = '1' ) );
state_next(352) <= (reset /= '1') and ( ( state_cur(353) and not ( (NOT(in1)) = '1' ) ) );
state_next(353) <= (reset /= '1') and ( state_cur(354) or ( state_cur(353) and (NOT(in1)) = '1' ) );
state_next(354) <= (reset /= '1') and ( ( state_cur(355) and not ( (NOT(in1)) = '1' ) ) );
state_next(355) <= (reset /= '1') and ( state_cur(356) or ( state_cur(355) and (NOT(in1)) = '1' ) );
state_next(356) <= (reset /= '1') and ( ( state_cur(357) and not ( (NOT(in1)) = '1' ) ) );
state_next(357) <= (reset /= '1') and ( state_cur(358) or ( state_cur(357) and (NOT(in1)) = '1' ) );
state_next(358) <= (reset /= '1') and ( ( state_cur(359) and not ( (NOT(in1)) = '1' ) ) );
state_next(359) <= (reset /= '1') and ( state_cur(360) or ( state_cur(359) and (NOT(in1)) = '1' ) );
state_next(360) <= (reset /= '1') and ( ( state_cur(361) and not ( (NOT(in1)) = '1' ) ) );
state_next(361) <= (reset /= '1') and ( state_cur(362) or ( state_cur(361) and (NOT(in1)) = '1' ) );
state_next(362) <= (reset /= '1') and ( ( state_cur(363) and not ( (NOT(in1)) = '1' ) ) );
state_next(363) <= (reset /= '1') and ( state_cur(364) or ( state_cur(363) and (NOT(in1)) = '1' ) );
state_next(364) <= (reset /= '1') and ( ( state_cur(365) and not ( (NOT(in1)) = '1' ) ) );
state_next(365) <= (reset /= '1') and ( state_cur(366) or ( state_cur(365) and (NOT(in1)) = '1' ) );
state_next(366) <= (reset /= '1') and ( ( state_cur(367) and not ( (NOT(in1)) = '1' ) ) );
state_next(367) <= (reset /= '1') and ( state_cur(368) or ( state_cur(367) and (NOT(in1)) = '1' ) );
state_next(368) <= (reset /= '1') and ( ( state_cur(369) and not ( (NOT(in1)) = '1' ) ) );
state_next(369) <= (reset /= '1') and ( state_cur(370) or ( state_cur(369) and (NOT(in1)) = '1' ) );
state_next(370) <= (reset /= '1') and ( ( state_cur(371) and not ( (NOT(in1)) = '1' ) ) );
state_next(371) <= (reset /= '1') and ( state_cur(372) or ( state_cur(371) and (NOT(in1)) = '1' ) );
state_next(372) <= (reset /= '1') and ( ( state_cur(373) and not ( (NOT(in1)) = '1' ) ) );
state_next(373) <= (reset /= '1') and ( state_cur(374) or ( state_cur(373) and (NOT(in1)) = '1' ) );
state_next(374) <= (reset /= '1') and ( ( state_cur(375) and not ( (NOT(in1)) = '1' ) ) );
state_next(375) <= (reset /= '1') and ( state_cur(376) or ( state_cur(375) and (NOT(in1)) = '1' ) );
state_next(376) <= (reset /= '1') and ( ( state_cur(377) and not ( (NOT(in1)) = '1' ) ) );
state_next(377) <= (reset /= '1') and ( state_cur(378) or ( state_cur(377) and (NOT(in1)) = '1' ) );
state_next(378) <= (reset /= '1') and ( ( state_cur(379) and not ( (NOT(in1)) = '1' ) ) );
state_next(379) <= (reset /= '1') and ( state_cur(380) or ( state_cur(379) and (NOT(in1)) = '1' ) );
state_next(380) <= (reset /= '1') and ( ( state_cur(381) and not ( (NOT(in1)) = '1' ) ) );
state_next(381) <= (reset /= '1') and ( state_cur(382) or ( state_cur(381) and (NOT(in1)) = '1' ) );
state_next(382) <= (reset /= '1') and ( ( state_cur(383) and not ( (NOT(in1)) = '1' ) ) );
state_next(383) <= (reset /= '1') and ( state_cur(384) or ( state_cur(383) and (NOT(in1)) = '1' ) );
state_next(384) <= (reset /= '1') and ( ( state_cur(385) and not ( (NOT(in1)) = '1' ) ) );
state_next(385) <= (reset /= '1') and ( state_cur(386) or ( state_cur(385) and (NOT(in1)) = '1' ) );
state_next(386) <= (reset /= '1') and ( ( state_cur(387) and not ( (NOT(in1)) = '1' ) ) );
state_next(387) <= (reset /= '1') and ( state_cur(388) or ( state_cur(387) and (NOT(in1)) = '1' ) );
state_next(388) <= (reset /= '1') and ( ( state_cur(389) and not ( (NOT(in1)) = '1' ) ) );
state_next(389) <= (reset /= '1') and ( state_cur(390) or ( state_cur(389) and (NOT(in1)) = '1' ) );
state_next(390) <= (reset /= '1') and ( ( state_cur(391) and not ( (NOT(in1)) = '1' ) ) );
state_next(391) <= (reset /= '1') and ( state_cur(392) or ( state_cur(391) and (NOT(in1)) = '1' ) );
state_next(392) <= (reset /= '1') and ( ( state_cur(393) and not ( (NOT(in1)) = '1' ) ) );
state_next(393) <= (reset /= '1') and ( state_cur(394) or ( state_cur(393) and (NOT(in1)) = '1' ) );
state_next(394) <= (reset /= '1') and ( ( state_cur(395) and not ( (NOT(in1)) = '1' ) ) );
state_next(395) <= (reset /= '1') and ( state_cur(396) or ( state_cur(395) and (NOT(in1)) = '1' ) );
state_next(396) <= (reset /= '1') and ( ( state_cur(397) and not ( (NOT(in1)) = '1' ) ) );
state_next(397) <= (reset /= '1') and ( state_cur(398) or ( state_cur(397) and (NOT(in1)) = '1' ) );
state_next(398) <= (reset /= '1') and ( ( state_cur(399) and not ( (NOT(in1)) = '1' ) ) );
state_next(399) <= (reset /= '1') and ( state_cur(400) or ( state_cur(399) and (NOT(in1)) = '1' ) );
state_next(400) <= (reset /= '1') and ( ( state_cur(401) and not ( (NOT(in1)) = '1' ) ) );
state_next(401) <= (reset /= '1') and ( state_cur(402) or ( state_cur(401) and (NOT(in1)) = '1' ) );
state_next(402) <= (reset /= '1') and ( ( state_cur(403) and not ( (NOT(in1)) = '1' ) ) );
state_next(403) <= (reset /= '1') and ( state_cur(404) or ( state_cur(403) and (NOT(in1)) = '1' ) );
state_next(404) <= (reset /= '1') and ( ( state_cur(405) and not ( (NOT(in1)) = '1' ) ) );
state_next(405) <= (reset /= '1') and ( state_cur(406) or ( state_cur(405) and (NOT(in1)) = '1' ) );
state_next(406) <= (reset /= '1') and ( ( state_cur(407) and not ( (NOT(in1)) = '1' ) ) );
state_next(407) <= (reset /= '1') and ( state_cur(408) or ( state_cur(407) and (NOT(in1)) = '1' ) );
state_next(408) <= (reset /= '1') and ( ( state_cur(409) and not ( (NOT(in1)) = '1' ) ) );
state_next(409) <= (reset /= '1') and ( state_cur(410) or ( state_cur(409) and (NOT(in1)) = '1' ) );
state_next(410) <= (reset /= '1') and ( ( state_cur(411) and not ( (NOT(in1)) = '1' ) ) );
state_next(411) <= (reset /= '1') and ( state_cur(412) or ( state_cur(411) and (NOT(in1)) = '1' ) );
state_next(412) <= (reset /= '1') and ( ( state_cur(413) and not ( (NOT(in1)) = '1' ) ) );
state_next(413) <= (reset /= '1') and ( state_cur(414) or ( state_cur(413) and (NOT(in1)) = '1' ) );
state_next(414) <= (reset /= '1') and ( ( state_cur(415) and not ( (NOT(in1)) = '1' ) ) );
state_next(415) <= (reset /= '1') and ( state_cur(416) or ( state_cur(415) and (NOT(in1)) = '1' ) );
state_next(416) <= (reset /= '1') and ( ( state_cur(417) and not ( (NOT(in1)) = '1' ) ) );
state_next(417) <= (reset /= '1') and ( state_cur(418) or ( state_cur(417) and (NOT(in1)) = '1' ) );
state_next(418) <= (reset /= '1') and ( ( state_cur(419) and not ( (NOT(in1)) = '1' ) ) );
state_next(419) <= (reset /= '1') and ( state_cur(420) or ( state_cur(419) and (NOT(in1)) = '1' ) );
state_next(420) <= (reset /= '1') and ( ( state_cur(421) and not ( (NOT(in1)) = '1' ) ) );
state_next(421) <= (reset /= '1') and ( state_cur(422) or ( state_cur(421) and (NOT(in1)) = '1' ) );
state_next(422) <= (reset /= '1') and ( ( state_cur(423) and not ( (NOT(in1)) = '1' ) ) );
state_next(423) <= (reset /= '1') and ( state_cur(424) or ( state_cur(423) and (NOT(in1)) = '1' ) );
state_next(424) <= (reset /= '1') and ( ( state_cur(425) and not ( (NOT(in1)) = '1' ) ) );
state_next(425) <= (reset /= '1') and ( state_cur(426) or ( state_cur(425) and (NOT(in1)) = '1' ) );
state_next(426) <= (reset /= '1') and ( ( state_cur(427) and not ( (NOT(in1)) = '1' ) ) );
state_next(427) <= (reset /= '1') and ( state_cur(428) or ( state_cur(427) and (NOT(in1)) = '1' ) );
state_next(428) <= (reset /= '1') and ( ( state_cur(429) and not ( (NOT(in1)) = '1' ) ) );
state_next(429) <= (reset /= '1') and ( state_cur(430) or ( state_cur(429) and (NOT(in1)) = '1' ) );
state_next(430) <= (reset /= '1') and ( ( state_cur(431) and not ( (NOT(in1)) = '1' ) ) );
state_next(431) <= (reset /= '1') and ( state_cur(432) or ( state_cur(431) and (NOT(in1)) = '1' ) );
state_next(432) <= (reset /= '1') and ( ( state_cur(433) and not ( (NOT(in1)) = '1' ) ) );
state_next(433) <= (reset /= '1') and ( state_cur(434) or ( state_cur(433) and (NOT(in1)) = '1' ) );
state_next(434) <= (reset /= '1') and ( ( state_cur(435) and not ( (NOT(in1)) = '1' ) ) );
state_next(435) <= (reset /= '1') and ( state_cur(436) or ( state_cur(435) and (NOT(in1)) = '1' ) );
state_next(436) <= (reset /= '1') and ( ( state_cur(437) and not ( (NOT(in1)) = '1' ) ) );
state_next(437) <= (reset /= '1') and ( state_cur(438) or ( state_cur(437) and (NOT(in1)) = '1' ) );
state_next(438) <= (reset /= '1') and ( ( state_cur(439) and not ( (NOT(in1)) = '1' ) ) );
state_next(439) <= (reset /= '1') and ( state_cur(440) or ( state_cur(439) and (NOT(in1)) = '1' ) );
state_next(440) <= (reset /= '1') and ( ( state_cur(441) and not ( (NOT(in1)) = '1' ) ) );
state_next(441) <= (reset /= '1') and ( state_cur(442) or ( state_cur(441) and (NOT(in1)) = '1' ) );
state_next(442) <= (reset /= '1') and ( ( state_cur(443) and not ( (NOT(in1)) = '1' ) ) );
state_next(443) <= (reset /= '1') and ( state_cur(444) or ( state_cur(443) and (NOT(in1)) = '1' ) );
state_next(444) <= (reset /= '1') and ( ( state_cur(445) and not ( (NOT(in1)) = '1' ) ) );
state_next(445) <= (reset /= '1') and ( state_cur(446) or ( state_cur(445) and (NOT(in1)) = '1' ) );
state_next(446) <= (reset /= '1') and ( ( state_cur(447) and not ( (NOT(in1)) = '1' ) ) );
state_next(447) <= (reset /= '1') and ( state_cur(448) or ( state_cur(447) and (NOT(in1)) = '1' ) );
state_next(448) <= (reset /= '1') and ( ( state_cur(449) and not ( (NOT(in1)) = '1' ) ) );
state_next(449) <= (reset /= '1') and ( state_cur(450) or ( state_cur(449) and (NOT(in1)) = '1' ) );
state_next(450) <= (reset /= '1') and ( ( state_cur(451) and not ( (NOT(in1)) = '1' ) ) );
state_next(451) <= (reset /= '1') and ( state_cur(452) or ( state_cur(451) and (NOT(in1)) = '1' ) );
state_next(452) <= (reset /= '1') and ( ( state_cur(453) and not ( (NOT(in1)) = '1' ) ) );
state_next(453) <= (reset /= '1') and ( state_cur(454) or ( state_cur(453) and (NOT(in1)) = '1' ) );
state_next(454) <= (reset /= '1') and ( ( state_cur(455) and not ( (NOT(in1)) = '1' ) ) );
state_next(455) <= (reset /= '1') and ( state_cur(456) or ( state_cur(455) and (NOT(in1)) = '1' ) );
state_next(456) <= (reset /= '1') and ( ( state_cur(457) and not ( (NOT(in1)) = '1' ) ) );
state_next(457) <= (reset /= '1') and ( state_cur(458) or ( state_cur(457) and (NOT(in1)) = '1' ) );
state_next(458) <= (reset /= '1') and ( ( state_cur(459) and not ( (NOT(in1)) = '1' ) ) );
state_next(459) <= (reset /= '1') and ( state_cur(460) or ( state_cur(459) and (NOT(in1)) = '1' ) );
state_next(460) <= (reset /= '1') and ( ( state_cur(461) and not ( (NOT(in1)) = '1' ) ) );
state_next(461) <= (reset /= '1') and ( state_cur(462) or ( state_cur(461) and (NOT(in1)) = '1' ) );
state_next(462) <= (reset /= '1') and ( ( state_cur(463) and not ( (NOT(in1)) = '1' ) ) );
state_next(463) <= (reset /= '1') and ( state_cur(464) or ( state_cur(463) and (NOT(in1)) = '1' ) );
state_next(464) <= (reset /= '1') and ( ( state_cur(465) and not ( (NOT(in1)) = '1' ) ) );
state_next(465) <= (reset /= '1') and ( state_cur(466) or ( state_cur(465) and (NOT(in1)) = '1' ) );
state_next(466) <= (reset /= '1') and ( ( state_cur(467) and not ( (NOT(in1)) = '1' ) ) );
state_next(467) <= (reset /= '1') and ( state_cur(468) or ( state_cur(467) and (NOT(in1)) = '1' ) );
state_next(468) <= (reset /= '1') and ( ( state_cur(469) and not ( (NOT(in1)) = '1' ) ) );
state_next(469) <= (reset /= '1') and ( state_cur(470) or ( state_cur(469) and (NOT(in1)) = '1' ) );
state_next(470) <= (reset /= '1') and ( ( state_cur(471) and not ( (NOT(in1)) = '1' ) ) );
state_next(471) <= (reset /= '1') and ( state_cur(472) or ( state_cur(471) and (NOT(in1)) = '1' ) );
state_next(472) <= (reset /= '1') and ( ( state_cur(473) and not ( (NOT(in1)) = '1' ) ) );
state_next(473) <= (reset /= '1') and ( state_cur(474) or ( state_cur(473) and (NOT(in1)) = '1' ) );
state_next(474) <= (reset /= '1') and ( ( state_cur(475) and not ( (NOT(in1)) = '1' ) ) );
state_next(475) <= (reset /= '1') and ( state_cur(476) or ( state_cur(475) and (NOT(in1)) = '1' ) );
state_next(476) <= (reset /= '1') and ( ( state_cur(477) and not ( (NOT(in1)) = '1' ) ) );
state_next(477) <= (reset /= '1') and ( state_cur(478) or ( state_cur(477) and (NOT(in1)) = '1' ) );
state_next(478) <= (reset /= '1') and ( ( state_cur(479) and not ( (NOT(in1)) = '1' ) ) );
state_next(479) <= (reset /= '1') and ( state_cur(480) or ( state_cur(479) and (NOT(in1)) = '1' ) );
state_next(480) <= (reset /= '1') and ( ( state_cur(481) and not ( (NOT(in1)) = '1' ) ) );
state_next(481) <= (reset /= '1') and ( state_cur(482) or ( state_cur(481) and (NOT(in1)) = '1' ) );
state_next(482) <= (reset /= '1') and ( ( state_cur(483) and not ( (NOT(in1)) = '1' ) ) );
state_next(483) <= (reset /= '1') and ( state_cur(484) or ( state_cur(483) and (NOT(in1)) = '1' ) );
state_next(484) <= (reset /= '1') and ( ( state_cur(485) and not ( (NOT(in1)) = '1' ) ) );
state_next(485) <= (reset /= '1') and ( state_cur(486) or ( state_cur(485) and (NOT(in1)) = '1' ) );
state_next(486) <= (reset /= '1') and ( ( state_cur(487) and not ( (NOT(in1)) = '1' ) ) );
state_next(487) <= (reset /= '1') and ( state_cur(488) or ( state_cur(487) and (NOT(in1)) = '1' ) );
state_next(488) <= (reset /= '1') and ( ( state_cur(489) and not ( (NOT(in1)) = '1' ) ) );
state_next(489) <= (reset /= '1') and ( state_cur(490) or ( state_cur(489) and (NOT(in1)) = '1' ) );
state_next(490) <= (reset /= '1') and ( ( state_cur(491) and not ( (NOT(in1)) = '1' ) ) );
state_next(491) <= (reset /= '1') and ( state_cur(492) or ( state_cur(491) and (NOT(in1)) = '1' ) );
state_next(492) <= (reset /= '1') and ( ( state_cur(493) and not ( (NOT(in1)) = '1' ) ) );
state_next(493) <= (reset /= '1') and ( state_cur(494) or ( state_cur(493) and (NOT(in1)) = '1' ) );
state_next(494) <= (reset /= '1') and ( ( state_cur(495) and not ( (NOT(in1)) = '1' ) ) );
state_next(495) <= (reset /= '1') and ( state_cur(496) or ( state_cur(495) and (NOT(in1)) = '1' ) );
state_next(496) <= (reset /= '1') and ( ( state_cur(497) and not ( (NOT(in1)) = '1' ) ) );
state_next(497) <= (reset /= '1') and ( state_cur(498) or ( state_cur(497) and (NOT(in1)) = '1' ) );
state_next(498) <= (reset /= '1') and ( ( state_cur(499) and not ( (NOT(in1)) = '1' ) ) );
state_next(499) <= (reset /= '1') and ( state_cur(500) or ( state_cur(499) and (NOT(in1)) = '1' ) );
state_next(500) <= (reset /= '1') and ( ( state_cur(501) and not ( (NOT(in1)) = '1' ) ) );
state_next(501) <= (reset /= '1') and ( state_cur(502) or ( state_cur(501) and (NOT(in1)) = '1' ) );
state_next(502) <= (reset /= '1') and ( ( state_cur(503) and not ( (NOT(in1)) = '1' ) ) );
state_next(503) <= (reset /= '1') and ( state_cur(504) or ( state_cur(503) and (NOT(in1)) = '1' ) );
state_next(504) <= (reset /= '1') and ( ( state_cur(505) and not ( (NOT(in1)) = '1' ) ) );
state_next(505) <= (reset /= '1') and ( state_cur(506) or ( state_cur(505) and (NOT(in1)) = '1' ) );
state_next(506) <= (reset /= '1') and ( ( state_cur(507) and not ( (NOT(in1)) = '1' ) ) );
state_next(507) <= (reset /= '1') and ( state_cur(508) or ( state_cur(507) and (NOT(in1)) = '1' ) );
state_next(508) <= (reset /= '1') and ( ( state_cur(509) and not ( (NOT(in1)) = '1' ) ) );
state_next(509) <= (reset /= '1') and ( state_cur(510) or ( state_cur(509) and (NOT(in1)) = '1' ) );
state_next(510) <= (reset /= '1') and ( ( state_cur(511) and not ( (NOT(in1)) = '1' ) ) );
state_next(511) <= (reset /= '1') and ( state_cur(512) or ( state_cur(511) and (NOT(in1)) = '1' ) );
state_next(512) <= (reset /= '1') and ( ( state_cur(513) and not ( (NOT(in1)) = '1' ) ) );
state_next(513) <= (reset /= '1') and ( state_cur(514) or ( state_cur(513) and (NOT(in1)) = '1' ) );
state_next(514) <= (reset /= '1') and ( ( state_cur(515) and not ( (NOT(in1)) = '1' ) ) );
state_next(515) <= (reset /= '1') and ( state_cur(516) or ( state_cur(515) and (NOT(in1)) = '1' ) );
state_next(516) <= (reset /= '1') and ( ( state_cur(517) and not ( (NOT(in1)) = '1' ) ) );
state_next(517) <= (reset /= '1') and ( state_cur(518) or ( state_cur(517) and (NOT(in1)) = '1' ) );
state_next(518) <= (reset /= '1') and ( ( state_cur(519) and not ( (NOT(in1)) = '1' ) ) );
state_next(519) <= (reset /= '1') and ( ( state_cur(519) and (NOT(in1)) = '1' ) or state_cur(1) );
state_next(520) <= (reset /= '1') and ( ( state_cur(520) and (NOT(in1)) = '1' ) or state_cur(73) );
state_next(521) <= (reset /= '1') and ( ( state_cur(521) and (NOT(in1)) = '1' ) or state_cur(71) );
state_next(522) <= (reset /= '1') and ( ( state_cur(220) and not ( (in6) = '1' ) ) );
state_next(523) <= (reset /= '1') and ( state_cur(149) );
-- Assignment of buffers for buffered outputs
out386_bufn <= state_cur(186) or state_cur(270);
out404_bufn <= (state_cur(290) = '1' and rtmcmp290 = '0') or state_cur(291) or state_cur(173);
out457_bufn <= state_cur(142) or state_cur(190) or state_cur(169);
out841_bufn <= rtmcmp92 or state_cur(189);
out276_bufn <= state_cur(233) or state_cur(274);
out67_bufn <= state_cur(189) or state_cur(282) or state_cur(98) or state_cur(203) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) or state_cur(337);
out239_bufn <= ( state_cur(240) and (in7) = '1' ) or state_cur(523) or state_cur(129);
out259_bufn <= state_cur(268) or state_cur(178) or ( state_cur(220) and (in6) = '1' ) or ( state_cur(150) and (in3) = '1' ) or ( state_cur(175) and (in4) = '1' ) or ( state_cur(208) and (in5) = '1' ) or state_cur(523) or state_cur(129);
out416_bufn <= state_cur(338) or state_cur(143) or state_cur(289) or state_cur(322);
out646_bufn <= state_cur(340) or state_cur(326);
out485_bufn <= ( state_cur(240) and (in7) = '1' ) or ( state_cur(150) and (in3) = '1' );
out935_bufn <= state_cur(193) or state_cur(134);
out463_bufn <= state_cur(338) or state_cur(119) or state_cur(134) or state_cur(233) or state_cur(174);
out120_bufn <= rtmcmp92 or state_cur(100) or state_cur(91) or state_cur(179) or state_cur(228);
out293_bufn <= state_cur(342) or state_cur(303);
out216_bufn <= state_cur(107) or state_cur(212) or rtmcmp128 or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114) or state_cur(326) or state_cur(123) or state_cur(190) or state_cur(186) or rtmcmp290 or state_cur(204) or state_cur(191) or state_cur(303) or rtmcmp276;
out319_bufn <= (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114) or state_cur(99) or state_cur(218) or (state_cur(128) = '1' and rtmcmp128 = '0') or state_cur(296);
out230_bufn <= ( state_cur(220) and (in6) = '1' ) or state_cur(224);
out1_bufn <= ( state_cur(317) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(305) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(215) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(316) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(121) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(84) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(122) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(192) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(194) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(295) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(313) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(264) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(10) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(67) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(75) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(28) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(243) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(87) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(124) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(240) and not ( (in7) = '1' ) ) or ( state_cur(269) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(50) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(64) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(68) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(49) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(171) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(130) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(77) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(302) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(287) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(176) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(216) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(250) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(202) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(318) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(136) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(211) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(120) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(135) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(226) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(279) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(55) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(167) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(165) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(163) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(161) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(159) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(157) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(155) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(101) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(116) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(118) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(127) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(314) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(304) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(112) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(140) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(288) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(217) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(80) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(272) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(297) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(278) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(258) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(256) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(24) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(65) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(246) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(61) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(12) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(104) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(21) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(51) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(52) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(46) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(37) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(41) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(285) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(323) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(35) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(34) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(259) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(33) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(324) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(320) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(117) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(26) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(27) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(14) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(239) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(188) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(263) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(13) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(17) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(207) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(6) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(48) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(201) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(44) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(90) and not ( (NOT(in0)) = '1' ) );
out93_bufn <= state_cur(522) or state_cur(93) or state_cur(96) or state_cur(108) or ( state_cur(220) and (in6) = '1' ) or state_cur(342) or state_cur(340) or state_cur(95) or state_cur(184) or ( state_cur(150) and (in3) = '1' ) or state_cur(187) or ( state_cur(175) and (in4) = '1' ) or ( state_cur(208) and (in5) = '1' ) or state_cur(334) or state_cur(339);
out89_bufn <= state_cur(149) or state_cur(341) or state_cur(522) or state_cur(93) or state_cur(94) or state_cur(96) or state_cur(213) or state_cur(108) or state_cur(281) or state_cur(103) or state_cur(342) or state_cur(340) or state_cur(95) or state_cur(184) or state_cur(183) or state_cur(280) or state_cur(187) or state_cur(331) or state_cur(224) or state_cur(301) or state_cur(200) or state_cur(333) or state_cur(334) or state_cur(339);
out539_bufn <= state_cur(142) or state_cur(190);
out62_bufn <= state_cur(193) or rtmcmp92 or state_cur(107) or state_cur(212) or state_cur(338) or state_cur(119) or rtmcmp128 or state_cur(100) or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114) or state_cur(134) or state_cur(236) or state_cur(189) or state_cur(326) or state_cur(312) or state_cur(123) or state_cur(91) or state_cur(233) or state_cur(190) or state_cur(186) or state_cur(179) or rtmcmp290 or state_cur(282) or state_cur(319) or state_cur(174) or state_cur(204) or state_cur(172) or state_cur(191) or state_cur(303) or state_cur(274) or rtmcmp276 or state_cur(98) or state_cur(203) or state_cur(228) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) or state_cur(337);
out856_bufn <= state_cur(107) or state_cur(147) or state_cur(236);
out451_bufn <= state_cur(123) or state_cur(169);
out287_bufn <= state_cur(332) or state_cur(303);
out315_bufn <= state_cur(268) or state_cur(178) or (state_cur(128) = '1' and rtmcmp128 = '0') or state_cur(296);
out536_bufn <= state_cur(95) or state_cur(190);
out209_bufn <= state_cur(191) or state_cur(200);
out221_bufn <= rtmcmp128 or state_cur(237) or state_cur(197) or rtmcmp276;
out283_bufn <= state_cur(193) or state_cur(236) or state_cur(312) or state_cur(319) or state_cur(172) or state_cur(274);
out368_bufn <= state_cur(213) or ( state_cur(175) and (in4) = '1' );
out516_bufn <= ( state_cur(208) and not ( (in5) = '1' ) ) or state_cur(281) or state_cur(183) or state_cur(280);
out393_bufn <= state_cur(193) or state_cur(212) or state_cur(338) or state_cur(143) or state_cur(210) or state_cur(289) or state_cur(322) or state_cur(204);
out1008_bufn <= state_cur(182) or state_cur(268) or state_cur(178);
out392_bufn <= state_cur(108) or state_cur(204);
out261_bufn <= state_cur(268) or state_cur(178) or state_cur(523) or state_cur(129);
out559_bufn <= state_cur(99) or state_cur(218);
out543_bufn <= state_cur(326) or state_cur(292) or state_cur(123) or state_cur(233);
out895_bufn <= state_cur(219) or state_cur(125) or state_cur(247) or state_cur(242) or state_cur(241) or state_cur(148);
out82_bufn <= ( state_cur(208) and (in5) = '1' ) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336);
out220_bufn <= state_cur(107) or rtmcmp128 or state_cur(147) or state_cur(237) or state_cur(236) or state_cur(197) or rtmcmp276;
out95_bufn <= state_cur(522) or state_cur(93) or state_cur(96) or state_cur(108) or state_cur(342) or state_cur(340) or state_cur(95) or state_cur(184) or state_cur(187) or state_cur(334) or state_cur(339);
out943_bufn <= (state_cur(290) = '1' and rtmcmp290 = '0') or state_cur(291) or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114);
out465_bufn <= state_cur(319) or state_cur(174);
out238_bufn <= ( state_cur(175) and (in4) = '1' ) or state_cur(523) or state_cur(129);
out1025_bufn <= ( state_cur(328) and (in11) = '1' ) or state_cur(268) or state_cur(178);
out132_bufn <= state_cur(146) or state_cur(138) or state_cur(273) or state_cur(105);
out79_bufn <= ( state_cur(328) and (in11) = '1' ) or state_cur(98) or state_cur(228) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336);
out500_bufn <= state_cur(91) or state_cur(282);
out65_bufn <= state_cur(179) or state_cur(337);
out111_bufn <= state_cur(96) or state_cur(95) or state_cur(334);
out420_bufn <= ( state_cur(328) and (in11) = '1' ) or state_cur(306);
out1076_bufn <= state_cur(93) or state_cur(107);
out101_bufn <= state_cur(523) or state_cur(129) or ( state_cur(175) and not ( (in4) = '1' ) );
out106_bufn <= ( state_cur(220) and not ( (in6) = '1' ) ) or state_cur(341) or state_cur(94) or ( state_cur(150) and not ( (in3) = '1' ) ) or state_cur(213) or ( state_cur(208) and not ( (in5) = '1' ) ) or state_cur(281) or state_cur(183) or state_cur(280) or state_cur(224) or state_cur(200) or state_cur(333) or ( state_cur(175) and not ( (in4) = '1' ) );
out68_bufn <= state_cur(193) or rtmcmp92 or state_cur(338) or state_cur(119) or state_cur(100) or state_cur(134) or state_cur(236) or state_cur(189) or state_cur(312) or state_cur(91) or state_cur(233) or state_cur(179) or state_cur(282) or state_cur(319) or state_cur(174) or state_cur(172) or state_cur(274) or state_cur(98) or state_cur(203) or state_cur(228) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) or state_cur(337);
out1069_bufn <= state_cur(213) or state_cur(212);
out77_bufn <= state_cur(228) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336);
out102_bufn <= state_cur(94) or state_cur(213) or ( state_cur(175) and not ( (in4) = '1' ) );
out394_bufn <= state_cur(193) or state_cur(212) or state_cur(210) or state_cur(204);
out342_bufn <= ( state_cur(220) and (in6) = '1' ) or ( state_cur(150) and (in3) = '1' ) or ( state_cur(175) and (in4) = '1' ) or ( state_cur(208) and (in5) = '1' );
out104_bufn <= ( state_cur(220) and not ( (in6) = '1' ) ) or state_cur(341) or state_cur(94) or ( state_cur(150) and not ( (in3) = '1' ) ) or state_cur(213) or ( state_cur(208) and not ( (in5) = '1' ) ) or state_cur(281) or ( state_cur(220) and (in6) = '1' ) or state_cur(146) or state_cur(138) or state_cur(183) or state_cur(280) or ( state_cur(150) and (in3) = '1' ) or ( state_cur(175) and (in4) = '1' ) or ( state_cur(208) and (in5) = '1' ) or state_cur(224) or state_cur(200) or state_cur(273) or state_cur(105) or state_cur(333) or ( state_cur(175) and not ( (in4) = '1' ) );
out361_bufn <= state_cur(338) or state_cur(172);
out116_bufn <= ( state_cur(150) and not ( (in3) = '1' ) ) or state_cur(200) or state_cur(333);
out595_bufn <= state_cur(119) or state_cur(237) or state_cur(236) or state_cur(312);
out1004_bufn <= state_cur(143) or state_cur(132);
out227_bufn <= state_cur(123) or state_cur(224);
out109_bufn <= state_cur(186) or state_cur(334);
out619_bufn <= state_cur(237) or state_cur(312);
out410_bufn <= state_cur(335) or state_cur(143) or state_cur(132) or state_cur(322);
out989_bufn <= ( state_cur(150) and not ( (in3) = '1' ) ) or ( state_cur(240) and (in7) = '1' );
out431_bufn <= state_cur(184) or state_cur(187);
out938_bufn <= state_cur(94) or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114);
out525_bufn <= state_cur(96) or rtmcmp290;
out73_bufn <= rtmcmp92 or (state_cur(290) = '1' and rtmcmp290 = '0') or state_cur(291) or state_cur(91) or state_cur(203) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) or state_cur(337);
out837_bufn <= state_cur(522) or state_cur(108) or state_cur(342);
out860_bufn <= state_cur(119) or state_cur(236);
out228_bufn <= ( state_cur(220) and not ( (in6) = '1' ) ) or state_cur(341) or state_cur(224);
out421_bufn <= ( state_cur(328) and (in11) = '1' ) or ( state_cur(325) and not ( (in10) = '1' ) ) or ( state_cur(97) and not ( (NOT(in0)) = '1' ) ) or state_cur(306);
out409_bufn <= state_cur(132) or state_cur(322);
out473_bufn <= state_cur(99) or state_cur(218) or ( state_cur(325) and (in10) = '1' ) or ( state_cur(310) and not ( (in9) = '1' ) );
out509_bufn <= state_cur(123) or state_cur(223);
out94_bufn <= rtmcmp276 or state_cur(339);
out1048_bufn <= state_cur(341) or rtmcmp128;
out98_bufn <= state_cur(93) or state_cur(340) or state_cur(339);
out945_bufn <= ( state_cur(240) and (in7) = '1' ) or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114);
out156_bufn <= ( state_cur(328) and (in11) = '1' ) or state_cur(98);
out152_bufn <= state_cur(100) or state_cur(203);
-- Assignment of non-buffered outputs
out80 <=
state_cur(92);
out576 <=
state_cur(200);
out1103 <=
state_cur(336);
out438 <=
state_cur(151);
out171 <=
state_cur(222) or state_cur(102);
out378 <=
state_cur(340) or state_cur(222) or state_cur(138);
out940 <=
state_cur(276);
out131 <=
state_cur(99);
out376 <=
state_cur(138);
out891 <=
state_cur(237);
out611 <=
state_cur(209);
out638 <=
state_cur(222) or state_cur(209);
out354 <=
state_cur(129);
out7 <=
state_cur(3);
out1127 <=
state_cur(339);
out888 <=
state_cur(237);
out1141 <=
state_cur(348);
out6 <=
state_cur(2);
out1200 <=
state_cur(466);
out1148 <=
state_cur(362);
out250 <=
state_cur(114);
out1100 <=
state_cur(335);
out1168 <=
state_cur(402);
out1158 <=
state_cur(382);
out581 <=
state_cur(204);
out549 <=
state_cur(222) or state_cur(193);
out412 <=
state_cur(145);
out381 <=
state_cur(222) or state_cur(213) or state_cur(138);
out38 <=
state_cur(56);
out100 <=
state_cur(522) or state_cur(342) or state_cur(341) or state_cur(340) or state_cur(339) or state_cur(334) or state_cur(333) or state_cur(331) or
state_cur(301) or state_cur(281) or state_cur(280) or state_cur(224) or state_cur(213) or state_cur(200) or state_cur(187) or state_cur(184) or
state_cur(183) or state_cur(149) or state_cur(108) or state_cur(103) or state_cur(96) or state_cur(95) or state_cur(94) or state_cur(93);
out1181 <=
state_cur(428);
out22 <=
state_cur(20);
out56 <=
state_cur(85);
out224 <=
state_cur(326) or state_cur(303) or state_cur(292) or rtmcmp276 or state_cur(237) or state_cur(236) or state_cur(233) or state_cur(197) or
state_cur(147) or rtmcmp128 or state_cur(123) or state_cur(107);
out1115 <=
state_cur(336);
out191 <=
state_cur(102);
out290 <=
state_cur(123);
out1226 <=
state_cur(518);
out921 <=
state_cur(271);
out535 <=
state_cur(191);
out489 <=
state_cur(178);
out13 <=
state_cur(8);
out1161 <=
state_cur(388);
out408 <=
state_cur(144);
out1197 <=
state_cur(460);
out521 <=
state_cur(184);
out128 <=
state_cur(296) or state_cur(218) or state_cur(114) or state_cur(99);
out440 <=
state_cur(154);
out330 <=
state_cur(128);
out1003 <=
state_cur(294);
out1145 <=
state_cur(356);
out1156 <=
state_cur(378);
out497 <=
state_cur(268) or state_cur(222) or state_cur(178);
out52 <=
state_cur(79);
out659 <=
state_cur(218);
out566 <=
state_cur(197);
out850 <=
state_cur(231);
out1123 <=
state_cur(338);
out558 <=
state_cur(197);
out902 <=
state_cur(248);
out1217 <=
state_cur(500);
out357 <=
state_cur(132);
out229 <=
state_cur(108);
out1096 <=
state_cur(335);
out1188 <=
state_cur(442);
out39 <=
state_cur(57);
out118 <=
state_cur(96);
out387 <=
state_cur(142);
out514 <=
state_cur(183);
out425 <=
state_cur(148);
out508 <=
state_cur(182);
out1155 <=
state_cur(376);
out877 <=
state_cur(236);
out844 <=
state_cur(228);
out237 <=
state_cur(113);
out1133 <=
state_cur(341);
out1046 <=
state_cur(301);
out365 <=
state_cur(137);
out858 <=
state_cur(233);
out873 <=
state_cur(235);
out909 <=
state_cur(260);
out846 <=
state_cur(230);
out484 <=
state_cur(177);
out836 <=
state_cur(224);
out898 <=
state_cur(242);
out1196 <=
state_cur(458);
out26 <=
state_cur(30);
out1147 <=
state_cur(360);
out744 <=
state_cur(342) or state_cur(273) or state_cur(222);
out1026 <=
state_cur(296);
out430 <=
state_cur(149);
out962 <=
state_cur(281);
out45 <=
state_cur(66);
out9 <=
state_cur(5);
out1002 <=
state_cur(294);
out1139 <=
state_cur(344);
out1143 <=
state_cur(352);
out1173 <=
state_cur(412);
out28 <=
state_cur(32);
out1092 <=
state_cur(334);
out1140 <=
state_cur(346);
out40 <=
state_cur(58);
out119 <=
state_cur(98);
out382 <=
state_cur(139);
out241 <=
state_cur(114);
out91 <=
state_cur(93);
out920 <=
state_cur(270);
out986 <=
state_cur(290);
out657 <=
state_cur(222) or state_cur(218);
out375 <=
state_cur(331) or state_cur(222) or state_cur(138);
out866 <=
state_cur(235);
out577 <=
state_cur(203);
out1159 <=
state_cur(384);
out236 <=
state_cur(111);
out367 <=
state_cur(339) or state_cur(222) or state_cur(138);
out1130 <=
state_cur(340);
out25 <=
state_cur(25);
out258 <=
state_cur(222) or state_cur(114);
out990 <=
state_cur(291);
out900 <=
state_cur(244);
out748 <=
state_cur(273) or state_cur(224) or state_cur(222);
out1219 <=
state_cur(504);
out552 <=
state_cur(196);
out852 <=
state_cur(232);
out644 <=
state_cur(222) or state_cur(210);
out4 <=
state_cur(1);
out1142 <=
state_cur(350);
out1089 <=
state_cur(333);
out937 <=
state_cur(275);
out291 <=
state_cur(335) or state_cur(332) or state_cur(303) or state_cur(169) or rtmcmp128 or state_cur(123);
out482 <=
state_cur(222) or state_cur(175);
out924 <=
state_cur(273);
out1218 <=
state_cur(502);
out590 <=
state_cur(205);
out20 <=
state_cur(18);
out114 <=
state_cur(222) or state_cur(178) or state_cur(96);
out30 <=
state_cur(38);
out1224 <=
state_cur(514);
out107 <=
state_cur(95);
out915 <=
state_cur(268);
out34 <=
state_cur(45);
out1213 <=
state_cur(492);
out33 <=
state_cur(43);
out530 <=
state_cur(187);
out1191 <=
state_cur(448);
out223 <=
state_cur(107);
out834 <=
state_cur(231) or state_cur(223);
out1038 <=
state_cur(298);
out454 <=
state_cur(170);
out1087 <=
state_cur(332);
out233 <=
state_cur(109);
out66 <=
state_cur(91);
out347 <=
state_cur(222) or state_cur(149) or state_cur(129);
out848 <=
state_cur(231);
out746 <=
state_cur(301) or state_cur(273) or state_cur(222);
out695 <=
state_cur(232) or state_cur(222);
out1203 <=
state_cur(472);
out1085 <=
state_cur(332);
out1157 <=
state_cur(380);
out1039 <=
state_cur(298);
out532 <=
state_cur(189);
out1138 <=
state_cur(342);
out441 <=
state_cur(156);
out845 <=
state_cur(229);
out48 <=
state_cur(71);
out593 <=
state_cur(222) or state_cur(208);
out1182 <=
state_cur(430);
out57 <=
state_cur(88);
out44 <=
state_cur(63);
out1183 <=
state_cur(432);
out29 <=
state_cur(36);
out1015 <=
state_cur(296);
out910 <=
state_cur(261);
out524 <=
state_cur(186);
out958 <=
state_cur(280);
out460 <=
state_cur(300) or state_cur(204) or state_cur(191) or state_cur(170);
out50 <=
state_cur(74);
out304 <=
state_cur(126);
out130 <=
state_cur(222) or state_cur(99);
out833 <=
state_cur(223);
out513 <=
rtmcmp290 or state_cur(223) or state_cur(182);
out1210 <=
state_cur(486);
out370 <=
state_cur(222) or state_cur(146) or state_cur(138);
out481 <=
state_cur(175);
out207 <=
state_cur(103);
out445 <=
state_cur(164);
out362 <=
state_cur(134);
out908 <=
state_cur(257);
out1186 <=
state_cur(438);
out466 <=
state_cur(172);
out1083 <=
state_cur(331);
out475 <=
state_cur(173);
out19 <=
state_cur(16);
out645 <=
state_cur(212);
out582 <=
state_cur(222) or state_cur(204);
out547 <=
state_cur(193);
out1154 <=
state_cur(374);
out854 <=
state_cur(232);
out208 <=
state_cur(222) or state_cur(178) or state_cur(103);
out975 <=
state_cur(286);
out1150 <=
state_cur(366);
out503 <=
state_cur(179);
out650 <=
state_cur(213);
out863 <=
state_cur(234);
out1211 <=
state_cur(488);
out1228 <=
state_cur(522);
out5 <=
state_cur(518) or state_cur(516) or state_cur(514) or state_cur(512) or state_cur(510) or state_cur(508) or state_cur(506) or state_cur(504) or
state_cur(502) or state_cur(500) or state_cur(498) or state_cur(496) or state_cur(494) or state_cur(492) or state_cur(490) or state_cur(488) or
state_cur(486) or state_cur(484) or state_cur(482) or state_cur(480) or state_cur(478) or state_cur(476) or state_cur(474) or state_cur(472) or
state_cur(470) or state_cur(468) or state_cur(466) or state_cur(464) or state_cur(462) or state_cur(460) or state_cur(458) or state_cur(456) or
state_cur(454) or state_cur(452) or state_cur(450) or state_cur(448) or state_cur(446) or state_cur(444) or state_cur(442) or state_cur(440) or
state_cur(438) or state_cur(436) or state_cur(434) or state_cur(432) or state_cur(430) or state_cur(428) or state_cur(426) or state_cur(424) or
state_cur(422) or state_cur(420) or state_cur(418) or state_cur(416) or state_cur(414) or state_cur(412) or state_cur(410) or state_cur(408) or
state_cur(406) or state_cur(404) or state_cur(402) or state_cur(400) or state_cur(398) or state_cur(396) or state_cur(394) or state_cur(392) or
state_cur(390) or state_cur(388) or state_cur(386) or state_cur(384) or state_cur(382) or state_cur(380) or state_cur(378) or state_cur(376) or
state_cur(374) or state_cur(372) or state_cur(370) or state_cur(368) or state_cur(366) or state_cur(364) or state_cur(362) or state_cur(360) or
state_cur(358) or state_cur(356) or state_cur(354) or state_cur(352) or state_cur(350) or state_cur(348) or state_cur(346) or state_cur(344) or
state_cur(214) or state_cur(198) or state_cur(195) or state_cur(180) or state_cur(125) or state_cur(115) or state_cur(85) or state_cur(83) or
state_cur(79) or state_cur(73) or state_cur(71) or state_cur(1);
out1081 <=
state_cur(330);
out980 <=
rtmcmp290;
out533 <=
state_cur(190);
out338 <=
state_cur(280) or state_cur(222) or state_cur(129);
out32 <=
state_cur(40);
out1080 <=
state_cur(329);
out27 <=
state_cur(31);
out893 <=
state_cur(238);
out397 <=
state_cur(143);
out1000 <=
state_cur(293);
out55 <=
state_cur(83);
out235 <=
state_cur(109);
out1198 <=
state_cur(462);
out12 <=
state_cur(7);
out1221 <=
state_cur(508);
out277 <=
state_cur(119);
out1205 <=
state_cur(476);
out321 <=
state_cur(338) or state_cur(322) or state_cur(319) or state_cur(298) or state_cur(289) or rtmcmp276 or state_cur(237) or state_cur(197) or
state_cur(151) or state_cur(145) or state_cur(143) or rtmcmp128;
out1216 <=
state_cur(498);
out999 <=
state_cur(292);
out1190 <=
state_cur(446);
out1078 <=
state_cur(327);
out17 <=
state_cur(521) or state_cur(520) or state_cur(519) or state_cur(517) or state_cur(515) or state_cur(513) or state_cur(511) or state_cur(509) or
state_cur(507) or state_cur(505) or state_cur(503) or state_cur(501) or state_cur(499) or state_cur(497) or state_cur(495) or state_cur(493) or
state_cur(491) or state_cur(489) or state_cur(487) or state_cur(485) or state_cur(483) or state_cur(481) or state_cur(479) or state_cur(477) or
state_cur(475) or state_cur(473) or state_cur(471) or state_cur(469) or state_cur(467) or state_cur(465) or state_cur(463) or state_cur(461) or
state_cur(459) or state_cur(457) or state_cur(455) or state_cur(453) or state_cur(451) or state_cur(449) or state_cur(447) or state_cur(445) or
state_cur(443) or state_cur(441) or state_cur(439) or state_cur(437) or state_cur(435) or state_cur(433) or state_cur(431) or state_cur(429) or
state_cur(427) or state_cur(425) or state_cur(423) or state_cur(421) or state_cur(419) or state_cur(417) or state_cur(415) or state_cur(413) or
state_cur(411) or state_cur(409) or state_cur(407) or state_cur(405) or state_cur(403) or state_cur(401) or state_cur(399) or state_cur(397) or
state_cur(395) or state_cur(393) or state_cur(391) or state_cur(389) or state_cur(387) or state_cur(385) or state_cur(383) or state_cur(381) or
state_cur(379) or state_cur(377) or state_cur(375) or state_cur(373) or state_cur(371) or state_cur(369) or state_cur(367) or state_cur(365) or
state_cur(363) or state_cur(361) or state_cur(359) or state_cur(357) or state_cur(355) or state_cur(353) or state_cur(351) or state_cur(349) or
state_cur(347) or state_cur(345) or state_cur(343) or state_cur(255) or state_cur(110) or state_cur(106) or state_cur(86) or state_cur(78) or
state_cur(72) or state_cur(42) or state_cur(29) or state_cur(11);
out1209 <=
state_cur(484);
out70 <=
state_cur(337) or state_cur(336) or state_cur(282) or state_cur(228) or state_cur(203) or state_cur(189) or state_cur(179) or state_cur(102) or
state_cur(100) or state_cur(98) or rtmcmp92 or state_cur(91);
out1077 <=
state_cur(326);
out1215 <=
state_cur(496);
out285 <=
state_cur(338) or state_cur(319) or state_cur(312) or state_cur(274) or state_cur(236) or state_cur(233) or state_cur(209) or state_cur(193) or
state_cur(174) or state_cur(172) or state_cur(134) or state_cur(119);
out1206 <=
state_cur(478);
out1175 <=
state_cur(416);
out1222 <=
state_cur(510);
out443 <=
state_cur(160);
out212 <=
state_cur(105);
out270 <=
state_cur(296) or state_cur(114);
out865 <=
state_cur(234);
out648 <=
state_cur(222) or state_cur(212);
out1176 <=
state_cur(418);
out1174 <=
state_cur(414);
out54 <=
state_cur(82);
out706 <=
state_cur(296) or state_cur(222);
out913 <=
state_cur(266);
out24 <=
state_cur(23);
out1164 <=
state_cur(394);
out729 <=
state_cur(341) or state_cur(273) or state_cur(222);
out1204 <=
state_cur(474);
out573 <=
state_cur(199);
out480 <=
state_cur(222) or state_cur(174);
out14 <=
state_cur(9);
out1073 <=
state_cur(325);
out974 <=
state_cur(284);
out358 <=
state_cur(222) or state_cur(132);
out504 <=
state_cur(180);
out21 <=
state_cur(19);
out37 <=
state_cur(54);
out541 <=
state_cur(222) or state_cur(191);
out1071 <=
state_cur(322);
out23 <=
state_cur(22);
out1122 <=
state_cur(337);
out8 <=
state_cur(4);
out839 <=
state_cur(225);
out35 <=
state_cur(47);
out988 <=
state_cur(291);
out419 <=
state_cur(147);
out976 <=
state_cur(289);
out973 <=
state_cur(283);
out58 <=
state_cur(89);
out424 <=
state_cur(306) or state_cur(148);
out450 <=
state_cur(222) or state_cur(170);
out1068 <=
state_cur(321);
out1170 <=
state_cur(406);
out1067 <=
state_cur(319);
out1225 <=
state_cur(516);
out1187 <=
state_cur(440);
out563 <=
state_cur(222) or state_cur(197);
out1178 <=
state_cur(422);
out31 <=
state_cur(39);
out51 <=
state_cur(76);
out1171 <=
state_cur(408);
out41 <=
state_cur(59);
out360 <=
state_cur(133);
out1162 <=
state_cur(390);
out403 <=
state_cur(144);
out1179 <=
state_cur(424);
out1212 <=
state_cur(490);
out1189 <=
state_cur(444);
out1166 <=
state_cur(398);
out42 <=
state_cur(60);
out1220 <=
state_cur(506);
out137 <=
state_cur(99);
out643 <=
state_cur(210);
out692 <=
rtmcmp276 or state_cur(222);
out43 <=
state_cur(62);
out972 <=
state_cur(282);
out472 <=
state_cur(173);
out505 <=
state_cur(181);
out934 <=
state_cur(274);
out1165 <=
state_cur(396);
out494 <=
state_cur(334) or state_cur(222) or state_cur(178);
out1208 <=
state_cur(482);
out1172 <=
state_cur(410);
out550 <=
state_cur(195);
out439 <=
state_cur(152);
out388 <=
rtmcmp290 or state_cur(270) or state_cur(190) or state_cur(186) or state_cur(144) or state_cur(142);
out1195 <=
state_cur(456);
out479 <=
state_cur(174);
out1193 <=
state_cur(452);
out105 <=
state_cur(94);
out903 <=
state_cur(249);
out697 <=
state_cur(300) or state_cur(222);
out1149 <=
state_cur(364);
out49 <=
state_cur(73);
out448 <=
state_cur(169);
out436 <=
state_cur(150);
out917 <=
state_cur(270);
out1064 <=
state_cur(315);
out912 <=
state_cur(265);
out592 <=
state_cur(208);
out1167 <=
state_cur(400);
out719 <=
state_cur(237) or state_cur(222);
out301 <=
state_cur(125);
out1152 <=
state_cur(370);
out1063 <=
state_cur(312);
out1230 <=
state_cur(523);
out46 <=
state_cur(69);
out47 <=
state_cur(70);
out351 <=
state_cur(222) or state_cur(184) or state_cur(129);
out1169 <=
state_cur(404);
out491 <=
state_cur(222) or state_cur(200) or state_cur(178);
out1061 <=
state_cur(311);
out434 <=
state_cur(150);
out76 <=
state_cur(337) or state_cur(336) or state_cur(326) or state_cur(322) or state_cur(303) or state_cur(296) or state_cur(291) or rtmcmp290 or
rtmcmp276 or state_cur(212) or state_cur(204) or state_cur(203) or state_cur(191) or state_cur(190) or state_cur(186) or state_cur(143) or
state_cur(132) or rtmcmp128 or state_cur(123) or state_cur(114) or state_cur(107) or state_cur(100) or rtmcmp92 or state_cur(91);
out840 <=
state_cur(227);
out88 <=
state_cur(336) or state_cur(296) or state_cur(291) or rtmcmp290 or rtmcmp276 or rtmcmp128 or state_cur(114) or rtmcmp92;
out356 <=
state_cur(131);
out442 <=
state_cur(158);
out1199 <=
state_cur(464);
out1043 <=
state_cur(300);
out11 <=
state_cur(324) or state_cur(323) or state_cur(320) or state_cur(318) or state_cur(317) or state_cur(316) or state_cur(314) or state_cur(313) or
state_cur(305) or state_cur(304) or state_cur(302) or state_cur(297) or state_cur(295) or state_cur(288) or state_cur(287) or state_cur(285) or
state_cur(279) or state_cur(278) or state_cur(272) or state_cur(269) or state_cur(264) or state_cur(263) or state_cur(259) or state_cur(258) or
state_cur(256) or state_cur(250) or state_cur(246) or state_cur(243) or state_cur(239) or state_cur(226) or state_cur(217) or state_cur(216) or
state_cur(215) or state_cur(211) or state_cur(207) or state_cur(202) or state_cur(201) or state_cur(194) or state_cur(192) or state_cur(188) or
state_cur(176) or state_cur(171) or state_cur(167) or state_cur(165) or state_cur(163) or state_cur(161) or state_cur(159) or state_cur(157) or
state_cur(155) or state_cur(153) or state_cur(140) or state_cur(136) or state_cur(135) or state_cur(130) or state_cur(127) or state_cur(124) or
state_cur(122) or state_cur(121) or state_cur(120) or state_cur(118) or state_cur(117) or state_cur(116) or state_cur(112) or state_cur(104) or
state_cur(101) or state_cur(97) or state_cur(90) or state_cur(87) or state_cur(84) or state_cur(80) or state_cur(77) or state_cur(75) or
state_cur(68) or state_cur(67) or state_cur(65) or state_cur(64) or state_cur(61) or state_cur(55) or state_cur(52) or state_cur(51) or
state_cur(50) or state_cur(49) or state_cur(48) or state_cur(46) or state_cur(44) or state_cur(41) or state_cur(37) or state_cur(35) or
state_cur(34) or state_cur(33) or state_cur(28) or state_cur(27) or state_cur(26) or state_cur(24) or state_cur(21) or state_cur(17) or
state_cur(14) or state_cur(13) or state_cur(12) or state_cur(10) or state_cur(6);
out591 <=
state_cur(206);
out1180 <=
state_cur(426);
out476 <=
state_cur(291) or state_cur(173);
out1059 <=
state_cur(310);
out92 <=
state_cur(222) or state_cur(138) or state_cur(93);
out418 <=
state_cur(146);
out1042 <=
state_cur(299);
out1057 <=
state_cur(309);
out213 <=
state_cur(273) or state_cur(222) or state_cur(105);
out444 <=
state_cur(162);
out1153 <=
state_cur(372);
out1056 <=
state_cur(336) or state_cur(308);
out957 <=
state_cur(277);
out344 <=
state_cur(222) or state_cur(183) or state_cur(129);
out545 <=
state_cur(212) or state_cur(210) or state_cur(204) or state_cur(193);
out1055 <=
state_cur(308);
out968 <=
state_cur(282);
out335 <=
state_cur(222) or rtmcmp128;
out226 <=
state_cur(273) or state_cur(222) or state_cur(108);
out905 <=
state_cur(252);
out1177 <=
state_cur(420);
out904 <=
state_cur(251);
out1053 <=
state_cur(307);
out1052 <=
state_cur(306);
out417 <=
state_cur(145);
out1201 <=
state_cur(468);
out1163 <=
state_cur(392);
out2 <=
state_cur(330) or state_cur(329) or state_cur(327) or state_cur(321) or state_cur(315) or state_cur(311) or state_cur(309) or state_cur(307) or
state_cur(299) or state_cur(293) or state_cur(286) or state_cur(284) or state_cur(283) or state_cur(277) or state_cur(275) or state_cur(271) or
state_cur(267) or state_cur(266) or state_cur(265) or state_cur(262) or state_cur(261) or state_cur(260) or state_cur(257) or state_cur(254) or
state_cur(253) or state_cur(252) or state_cur(251) or state_cur(249) or state_cur(248) or state_cur(244) or state_cur(238) or state_cur(230) or
state_cur(229) or state_cur(227) or state_cur(225) or state_cur(221) or state_cur(206) or state_cur(205) or state_cur(199) or state_cur(185) or
state_cur(181) or state_cur(177) or state_cur(168) or state_cur(166) or state_cur(164) or state_cur(162) or state_cur(160) or state_cur(158) or
state_cur(156) or state_cur(154) or state_cur(139) or state_cur(137) or state_cur(133) or state_cur(131) or state_cur(126) or state_cur(113) or
state_cur(111) or state_cur(89) or state_cur(88) or state_cur(82) or state_cur(81) or state_cur(76) or state_cur(74) or state_cur(70) or
state_cur(69) or state_cur(66) or state_cur(63) or state_cur(62) or state_cur(60) or state_cur(59) or state_cur(58) or state_cur(57) or
state_cur(56) or state_cur(54) or state_cur(53) or state_cur(47) or state_cur(45) or state_cur(43) or state_cur(40) or state_cur(39) or
state_cur(38) or state_cur(36) or state_cur(32) or state_cur(31) or state_cur(30) or state_cur(25) or state_cur(23) or state_cur(22) or
state_cur(20) or state_cur(19) or state_cur(18) or state_cur(16) or state_cur(15) or state_cur(9) or state_cur(8) or state_cur(7) or
state_cur(5) or state_cur(4) or state_cur(3) or state_cur(2) or state_cur(0);
out447 <=
state_cur(168);
out1202 <=
state_cur(470);
out1192 <=
state_cur(450);
out1050 <=
state_cur(303);
out1144 <=
state_cur(354);
out0 <=
state_cur(0);
out446 <=
state_cur(166);
out914 <=
state_cur(267);
out1194 <=
state_cur(454);
out906 <=
state_cur(253);
out1146 <=
state_cur(358);
out572 <=
state_cur(198);
out1223 <=
state_cur(512);
out53 <=
state_cur(81);
out36 <=
state_cur(53);
out355 <=
state_cur(222) or state_cur(187) or state_cur(129);
out1184 <=
state_cur(434);
out907 <=
state_cur(254);
out1207 <=
state_cur(480);
out18 <=
state_cur(15);
out108 <=
state_cur(222) or state_cur(178) or state_cur(95);
out1160 <=
state_cur(386);
out662 <=
state_cur(218);
out303 <=
state_cur(247) or state_cur(242) or state_cur(241) or state_cur(197) or state_cur(152) or state_cur(148) or state_cur(125);
out1214 <=
state_cur(494);
out1185 <=
state_cur(436);
out341 <=
state_cur(523) or state_cur(222) or state_cur(129);
out1151 <=
state_cur(368);
out652 <=
state_cur(214);
out390 <=
state_cur(222) or state_cur(143);
out523 <=
state_cur(185);
out686 <=
state_cur(222);
out155 <=
state_cur(100);
out682 <=
state_cur(221);
out680 <=
state_cur(222) or state_cur(220);
out679 <=
state_cur(220);
out678 <=
state_cur(222) or state_cur(219);
out677 <=
state_cur(219);
-- Assignment of buffered outputs
out386 <= out386_buf;
out404 <= out404_buf;
out457 <= out457_buf;
out841 <= out841_buf;
out276 <= out276_buf;
out67 <= out67_buf;
out239 <= out239_buf;
out259 <= out259_buf;
out416 <= out416_buf;
out646 <= out646_buf;
out485 <= out485_buf;
out935 <= out935_buf;
out463 <= out463_buf;
out120 <= out120_buf;
out293 <= out293_buf;
out216 <= out216_buf;
out319 <= out319_buf;
out230 <= out230_buf;
out1 <= out1_buf;
out93 <= out93_buf;
out89 <= out89_buf;
out539 <= out539_buf;
out62 <= out62_buf;
out856 <= out856_buf;
out451 <= out451_buf;
out287 <= out287_buf;
out315 <= out315_buf;
out536 <= out536_buf;
out209 <= out209_buf;
out221 <= out221_buf;
out283 <= out283_buf;
out368 <= out368_buf;
out516 <= out516_buf;
out393 <= out393_buf;
out1008 <= out1008_buf;
out392 <= out392_buf;
out261 <= out261_buf;
out559 <= out559_buf;
out543 <= out543_buf;
out895 <= out895_buf;
out82 <= out82_buf;
out220 <= out220_buf;
out95 <= out95_buf;
out943 <= out943_buf;
out465 <= out465_buf;
out238 <= out238_buf;
out1025 <= out1025_buf;
out132 <= out132_buf;
out79 <= out79_buf;
out500 <= out500_buf;
out65 <= out65_buf;
out111 <= out111_buf;
out420 <= out420_buf;
out1076 <= out1076_buf;
out101 <= out101_buf;
out106 <= out106_buf;
out68 <= out68_buf;
out1069 <= out1069_buf;
out77 <= out77_buf;
out102 <= out102_buf;
out394 <= out394_buf;
out342 <= out342_buf;
out104 <= out104_buf;
out361 <= out361_buf;
out116 <= out116_buf;
out595 <= out595_buf;
out1004 <= out1004_buf;
out227 <= out227_buf;
out109 <= out109_buf;
out619 <= out619_buf;
out410 <= out410_buf;
out989 <= out989_buf;
out431 <= out431_buf;
out938 <= out938_buf;
out525 <= out525_buf;
out73 <= out73_buf;
out837 <= out837_buf;
out860 <= out860_buf;
out228 <= out228_buf;
out421 <= out421_buf;
out409 <= out409_buf;
out473 <= out473_buf;
out509 <= out509_buf;
out94 <= out94_buf;
out1048 <= out1048_buf;
out98 <= out98_buf;
out945 <= out945_buf;
out156 <= out156_buf;
out152 <= out152_buf;
-- Retiming: the comparators
rtmcmp92 <= '1' when state_cur(92) = '1' and rtmcounter0 = 1 else '0';
rtmcmp128 <= '1' when state_cur(128) = '1' and rtmcounter0 = 1 else '0';
rtmcmp276 <= '1' when state_cur(276) = '1' and rtmcounter0 = 1 else '0';
rtmcmp290 <= '1' when state_cur(290) = '1' and rtmcounter0 = 1 else '0';
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity debayer33 is
generic( CLK_PROC_FREQ : integer;
IM_WIDTH : integer := 1280;
IM_HEIGHT : integer := 960;
COLOR_CHANNELS : integer := 3;
DATA_SIZE : integer := 8
);
port(
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(DATA_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_fv : out std_logic;
out_dv : out std_logic;
out_data : out std_logic_vector((COLOR_CHANNELS*DATA_SIZE)-1 downto 0);
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0);
------------------------- for sim -------------------------
sim_en : in std_logic;
bayer_code_sim : in std_logic_vector(1 downto 0);
test_count_x_out : out std_logic_vector(integer(ceil(log2(real(IM_WIDTH))))-1 downto 0);
test_count_y_out : out std_logic_vector(integer(ceil(log2(real(IM_HEIGHT))))-1 downto 0)
);
end entity;
architecture structural of debayer33 is
component debayer33_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
bayer_code : out std_logic_vector(1 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
component debayer33_process is
generic( CLK_PROC_FREQ : integer;
IM_WIDTH : integer := 1280;
IM_HEIGHT : integer := 960;
COLOR_CHANNELS : integer := 3;
DATA_SIZE : integer := 8
);
port(
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- from slave -------------------------
bayer_code_slave : in std_logic_vector(1 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(DATA_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((COLOR_CHANNELS*DATA_SIZE)-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------- for sim -------------------------
sim_en : in std_logic;
bayer_code_sim : in std_logic_vector(1 downto 0);
test_count_x_out : out std_logic_vector(integer(ceil(log2(real(IM_WIDTH))))-1 downto 0);
test_count_y_out : out std_logic_vector(integer(ceil(log2(real(IM_HEIGHT))))-1 downto 0)
);
end component;
signal bayer_code_slave_int : std_logic_vector(1 downto 0);
begin
u0 : debayer33_slave
generic map(
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map(
clk_proc => clk_proc,
reset_n => reset_n,
---------------- dynamic parameters ports ---------------
status_reg_enable_bit => open,
bayer_code => bayer_code_slave_int,
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
u1 : debayer33_process
generic map(
CLK_PROC_FREQ => CLK_PROC_FREQ,
IM_WIDTH => IM_WIDTH,
IM_HEIGHT => IM_HEIGHT,
COLOR_CHANNELS => COLOR_CHANNELS,
DATA_SIZE => DATA_SIZE
)
port map(
clk_proc => clk_proc,
reset_n => reset_n,
------------------------- from slave -------------------------
bayer_code_slave=> bayer_code_slave_int,
------------------------- in flow -----------------------
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
------------------------ out flow -----------------------
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv,
------------------------- for sim -------------------------
sim_en => sim_en,
bayer_code_sim => bayer_code_sim,
test_count_x_out => test_count_x_out,
test_count_y_out => test_count_y_out
);
end architecture; |
entity test is
end test;
architecture only of test is
procedure iterate (
input : in bit_vector) is
variable j : integer := input'range'left;
begin -- iterate
for i in input'range loop
assert i = j report "TEST FAILED" severity failure;
j := j + 1;
end loop; -- i in 1 to 10
assert j = input'range'right + 1 report "TEST FAILED" severity failure;
end iterate;
begin -- only
doit: process
begin -- process doit
iterate("0000");
report "TEST PASSED";
wait;
end process doit;
end only;
|
entity test is
end test;
architecture only of test is
procedure iterate (
input : in bit_vector) is
variable j : integer := input'range'left;
begin -- iterate
for i in input'range loop
assert i = j report "TEST FAILED" severity failure;
j := j + 1;
end loop; -- i in 1 to 10
assert j = input'range'right + 1 report "TEST FAILED" severity failure;
end iterate;
begin -- only
doit: process
begin -- process doit
iterate("0000");
report "TEST PASSED";
wait;
end process doit;
end only;
|
entity test is
end test;
architecture only of test is
procedure iterate (
input : in bit_vector) is
variable j : integer := input'range'left;
begin -- iterate
for i in input'range loop
assert i = j report "TEST FAILED" severity failure;
j := j + 1;
end loop; -- i in 1 to 10
assert j = input'range'right + 1 report "TEST FAILED" severity failure;
end iterate;
begin -- only
doit: process
begin -- process doit
iterate("0000");
report "TEST PASSED";
wait;
end process doit;
end only;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_t
--
-- Generated
-- by: wig
-- on: Thu Oct 13 08:24:14 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../intra.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-conf-c.vhd,v 1.1 2005/10/13 09:09:44 wig Exp $
-- $Date: 2005/10/13 09:09:44 $
-- $Log: ent_t-rtl-conf-c.vhd,v $
-- Revision 1.1 2005/10/13 09:09:44 wig
-- Added intermediate CONN sheet split
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.59 2005/10/06 11:21:44 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.37 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_t_rtl_conf / ent_t
--
configuration ent_t_rtl_conf of ent_t is
for rtl
-- Generated Configuration
-- __I_NO_CONFIG_VERILOG --for inst_a : ent_a
-- __I_NO_CONFIG_VERILOG -- use configuration work.ent_a_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
for inst_b : ent_b
use configuration work.ent_b_rtl_conf;
end for;
end for;
end ent_t_rtl_conf;
--
-- End of Generated Configuration ent_t_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_172 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_172;
architecture augh of add_172 is
signal carry_inA : std_logic_vector(21 downto 0);
signal carry_inB : std_logic_vector(21 downto 0);
signal carry_res : std_logic_vector(21 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(20 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_172 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_172;
architecture augh of add_172 is
signal carry_inA : std_logic_vector(21 downto 0);
signal carry_inB : std_logic_vector(21 downto 0);
signal carry_res : std_logic_vector(21 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(20 downto 1);
end architecture;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_ch_08_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_08_01 is
end entity ch_08_01;
----------------------------------------------------------------
library ieee;
architecture test of ch_08_01 is
begin
process_08_1_a : process is
-- code from book:
variable stored_state : ieee.std_logic_1164.std_ulogic;
-- end of code from book
begin
wait;
end process process_08_1_a;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_ch_08_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_08_01 is
end entity ch_08_01;
----------------------------------------------------------------
library ieee;
architecture test of ch_08_01 is
begin
process_08_1_a : process is
-- code from book:
variable stored_state : ieee.std_logic_1164.std_ulogic;
-- end of code from book
begin
wait;
end process process_08_1_a;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_ch_08_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_08_01 is
end entity ch_08_01;
----------------------------------------------------------------
library ieee;
architecture test of ch_08_01 is
begin
process_08_1_a : process is
-- code from book:
variable stored_state : ieee.std_logic_1164.std_ulogic;
-- end of code from book
begin
wait;
end process process_08_1_a;
end architecture test;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 496;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800001";
when 16#00064# => romdata <= X"05000080";
when 16#00065# => romdata <= X"82100000";
when 16#00066# => romdata <= X"80A0E000";
when 16#00067# => romdata <= X"02800005";
when 16#00068# => romdata <= X"01000000";
when 16#00069# => romdata <= X"82004002";
when 16#0006A# => romdata <= X"10BFFFFC";
when 16#0006B# => romdata <= X"8620E001";
when 16#0006C# => romdata <= X"3D1003FF";
when 16#0006D# => romdata <= X"BC17A3E0";
when 16#0006E# => romdata <= X"BC278001";
when 16#0006F# => romdata <= X"9C27A060";
when 16#00070# => romdata <= X"03100000";
when 16#00071# => romdata <= X"81C04000";
when 16#00072# => romdata <= X"01000000";
when 16#00073# => romdata <= X"01000000";
when 16#00074# => romdata <= X"01000000";
when 16#00075# => romdata <= X"01000000";
when 16#00076# => romdata <= X"01000000";
when 16#00077# => romdata <= X"01000000";
when 16#00078# => romdata <= X"00000000";
when 16#00079# => romdata <= X"00000000";
when 16#0007A# => romdata <= X"00000000";
when 16#0007B# => romdata <= X"00000000";
when 16#0007C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 496;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800001";
when 16#00064# => romdata <= X"05000080";
when 16#00065# => romdata <= X"82100000";
when 16#00066# => romdata <= X"80A0E000";
when 16#00067# => romdata <= X"02800005";
when 16#00068# => romdata <= X"01000000";
when 16#00069# => romdata <= X"82004002";
when 16#0006A# => romdata <= X"10BFFFFC";
when 16#0006B# => romdata <= X"8620E001";
when 16#0006C# => romdata <= X"3D1003FF";
when 16#0006D# => romdata <= X"BC17A3E0";
when 16#0006E# => romdata <= X"BC278001";
when 16#0006F# => romdata <= X"9C27A060";
when 16#00070# => romdata <= X"03100000";
when 16#00071# => romdata <= X"81C04000";
when 16#00072# => romdata <= X"01000000";
when 16#00073# => romdata <= X"01000000";
when 16#00074# => romdata <= X"01000000";
when 16#00075# => romdata <= X"01000000";
when 16#00076# => romdata <= X"01000000";
when 16#00077# => romdata <= X"01000000";
when 16#00078# => romdata <= X"00000000";
when 16#00079# => romdata <= X"00000000";
when 16#0007A# => romdata <= X"00000000";
when 16#0007B# => romdata <= X"00000000";
when 16#0007C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT pcie_data_send_fifo_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal ssram_ce1n : std_logic;
signal ssram_ce2 : std_logic;
signal ssram_ce3n : std_logic;
signal ssram_wen : std_logic;
signal ssram_bw : std_logic_vector (0 to 3);
signal ssram_oen : std_ulogic;
signal ssaddr : std_logic_vector(20 downto 2);
signal ssdata : std_logic_vector(31 downto 0);
signal ssram_clk : std_ulogic;
signal ssram_adscn : std_ulogic;
signal ssram_adsp_n : std_ulogic;
signal ssram_adv_n : std_ulogic;
signal datazz : std_logic_vector(3 downto 0);
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clkin : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_dqs2 : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq, ddr_dq2 : std_logic_vector (15 downto 0); -- ddr data
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
-- for smc lan chip
signal eth_aen : std_ulogic; -- for smsc eth
signal eth_readn : std_ulogic; -- for smsc eth
signal eth_writen : std_ulogic; -- for smsc eth
signal eth_nbe : std_logic_vector(3 downto 0); -- for smsc eth
signal eth_datacsn : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
ddr_clkin <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
dqs2delay : delay_wire
generic map(data_width => ddr_dqs'length, delay_atob => 3.0, delay_btoa => 1.0)
port map(a => ddr_dqs, b => ddr_dqs2);
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 3.0, delay_btoa => 1.0)
port map(a => ddr_dq, b => ddr_dq2);
-- ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow )
port map (rst, clk, error,
address, data, romsn, oen, writen, open, open,
ssram_ce1n, ssram_ce2, ssram_ce3n, ssram_wen, ssram_bw, ssram_oen, ssaddr, ssdata,
ssram_clk, ssram_adscn, ssram_adsp_n, ssram_adv_n, iosn,
ddr_clkin, ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs2, ddr_ad, ddr_ba, ddr_dq2,
dsubren, dsuact, rxd1, txd1,
eth_aen, eth_readn, eth_writen, eth_nbe);
ddr2: ddrram
generic map (width => 16, abits => 13,
colbits => 9, rowbits => 12, implbanks => 1,
fname => sdramfile, igndqs => 1)
port map (
ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, dqs => ddr_dqs);
datazz <= "HHHH";
ssram0 : cy7c1380d generic map (fname => sramfile)
port map(
ioDq(35 downto 32) => datazz, ioDq(31 downto 0) => ssdata,
iAddr => ssaddr(20 downto 2), iMode => gnd,
inGW => vcc, inBWE => ssram_wen, inADV => ssram_adv_n,
inADSP => ssram_adsp_n, inADSC => ssram_adscn,
iClk => ssram_clk,
inBwa => ssram_bw(3), inBwb => ssram_bw(2),
inBwc => ssram_bw(1), inBwd => ssram_bw(0),
inOE => ssram_oen, inCE1 => ssram_ce1n,
iCE2 => ssram_ce2, inCE3 => ssram_ce3n, iZz => gnd);
-- 8 bit prom
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24),
romsn, writen, oen);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
----------------------------------------------------------------------------------
-- Author: Osowski Marcin
--
-- Description:
-- o Entity generates impulses required for managing
-- vga port in 1280x1024@60hz mode
--
-- o It requires 108 Mhz input clock
--
-- o It generates vblank signal. Whenever it's active,
-- vga color output should be set to "00000000" (all black).
-- It indicates an off-the-screen position.
--
-- o Sync pulses schema:
--
-- timing diagram for the horizontal synch signal (HS)
-- 0 1328 1440 1680 (pixels)
-- -------------------------|______|-------------------
-- timing diagram for the vertical synch signal (VS)
-- 0 1025 1028 1066 (lines)
-- -----------------------------------|______|---------
--
--
--
-- o For "next entities" (video signal generators), it generates signals line_change
-- and page_change. They are set to '1' for one clock cycle just before
-- there's a change in (appropriately) current line or current page.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vga_controller_1280_1024 is
port (
nrst : in std_logic;
clk108 : in std_logic;
hsync : out std_logic;
vsync : out std_logic;
vblank : out std_logic;
line_change : out std_logic;
page_change : out std_logic;
column : out integer range 0 to 1279;
column_change : out std_logic
);
end vga_controller_1280_1024;
architecture behavioral of vga_controller_1280_1024 is
constant HFrontPorch : integer := 1280;
constant HSyncPulse : integer := 1328;
constant HBackPorch : integer := 1440;
constant HTotal : integer := 1688;
constant VFrontPorch : integer := 1024;
constant VSyncPulse : integer := 1025;
constant VBackPorch : integer := 1028;
constant VTotal : integer := 1066;
signal hcount: integer range 0 to 1687 := 0;
signal vcount: integer range 0 to 1065 := 0;
signal next_hcount: integer range 0 to 1687;
signal next_vcount: integer range 0 to 1065;
signal internal_column : integer range 0 to 1279;
signal next_column : integer range 0 to 1279;
signal next_column_change : std_logic;
begin
-- Generating next_hcount.
next_hcount <= hcount + 1 when hcount < (HTotal - 1) else 0;
-- Generating next_vcount.
process (vcount, next_hcount) is
begin
if next_hcount = 0 then
if vcount < (VTotal - 1) then
next_vcount <= vcount + 1;
else
next_vcount <= 0;
end if;
else
next_vcount <= vcount;
end if;
end process;
-- Generating next_column and next_column_change.
process (next_hcount, internal_column, next_column) is
begin
if (next_hcount >= 1280) then
next_column <= 1279;
else
next_column <= next_hcount;
end if;
if next_column /= internal_column then
next_column_change <= '1';
else
next_column_change <= '0';
end if;
end process;
column <= internal_column;
-- Generating sync pulses and line_change, page_change signals.
process (nrst, clk108) is
begin
if nrst = '0' then
line_change <= '0';
page_change <= '0';
hsync <= '0';
vsync <= '0';
vblank <= '0';
internal_column <= 0;
column_change <= '0';
elsif rising_edge (clk108) then
if vcount /= next_vcount then
line_change <= '1';
else
line_change <= '0';
end if;
if vcount /= next_vcount and next_vcount = 0 then
page_change <= '1';
else
page_change <= '0';
end if;
hcount <= next_hcount;
if (next_hcount >= 1280) then
internal_column <= 1279;
else
internal_column <= next_hcount;
end if;
column_change <= next_column_change;
vcount <= next_vcount;
if next_hcount < HFrontPorch and next_vcount < VFrontPorch then
vblank <= '0';
else
vblank <= '1';
end if;
if next_hcount >= HSyncPulse and next_hcount < HBackPorch then
hsync <= '1';
else
hsync <= '0';
end if;
if next_vcount >= VSyncPulse and next_vcount < VBackPorch then
vsync <= '1';
else
vsync <= '0';
end if;
end if;
end process;
end architecture behavioral;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex7;
constant CFG_MEMTECH : integer := virtex7;
constant CFG_PADTECH : integer := virtex7;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex7;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (8);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- USB DSU
constant CFG_GRUSB_DCL : integer := 0;
constant CFG_GRUSB_DCL_UIFACE : integer := 1;
constant CFG_GRUSB_DCL_DW : integer := 8;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 16;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 0;
constant CFG_MIG_RANKS : integer := 1;
constant CFG_MIG_COLBITS : integer := 10;
constant CFG_MIG_ROWBITS : integer := 13;
constant CFG_MIG_BANKBITS: integer := 2;
constant CFG_MIG_HMASK : integer := 16#F00#;
-- Xilinx MIG Series 7
constant CFG_MIG_SERIES7 : integer := 1;
constant CFG_MIG_SERIES7_MODEL : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- USB Host Controller
constant CFG_GRUSBHC : integer := 0;
constant CFG_GRUSBHC_NPORTS : integer := 1;
constant CFG_GRUSBHC_EHC : integer := 0;
constant CFG_GRUSBHC_UHC : integer := 0;
constant CFG_GRUSBHC_NCC : integer := 1;
constant CFG_GRUSBHC_NPCC : integer := 1;
constant CFG_GRUSBHC_PRR : integer := 0;
constant CFG_GRUSBHC_PR1 : integer := 0*2**26 + 0*2**22 + 0*2**18 + 0*2**14 + 0*2**10 + 0*2**6 + 0*2**2 + (1/4);
constant CFG_GRUSBHC_PR2 : integer := 0*2**26 + 0*2**22 + 0*2**18 + 0*2**14 + 0*2**10 + 0*2**6 + 0*2**2 + (1 mod 4);
constant CFG_GRUSBHC_ENDIAN : integer := 1;
constant CFG_GRUSBHC_BEREGS : integer := 0;
constant CFG_GRUSBHC_BEDESC : integer := 0;
constant CFG_GRUSBHC_BLO : integer := 3;
constant CFG_GRUSBHC_BWRD : integer := 16;
constant CFG_GRUSBHC_UTM : integer := 2;
constant CFG_GRUSBHC_VBUSCONF : integer := 1;
-- GR USB 2.0 Device Controller
constant CFG_GRUSBDC : integer := 0;
constant CFG_GRUSBDC_AIFACE : integer := 0;
constant CFG_GRUSBDC_UIFACE : integer := 1;
constant CFG_GRUSBDC_DW : integer := 8;
constant CFG_GRUSBDC_NEPI : integer := 1;
constant CFG_GRUSBDC_NEPO : integer := 1;
constant CFG_GRUSBDC_I0 : integer := 1024;
constant CFG_GRUSBDC_I1 : integer := 1024;
constant CFG_GRUSBDC_I2 : integer := 1024;
constant CFG_GRUSBDC_I3 : integer := 1024;
constant CFG_GRUSBDC_I4 : integer := 1024;
constant CFG_GRUSBDC_I5 : integer := 1024;
constant CFG_GRUSBDC_I6 : integer := 1024;
constant CFG_GRUSBDC_I7 : integer := 1024;
constant CFG_GRUSBDC_I8 : integer := 1024;
constant CFG_GRUSBDC_I9 : integer := 1024;
constant CFG_GRUSBDC_I10 : integer := 1024;
constant CFG_GRUSBDC_I11 : integer := 1024;
constant CFG_GRUSBDC_I12 : integer := 1024;
constant CFG_GRUSBDC_I13 : integer := 1024;
constant CFG_GRUSBDC_I14 : integer := 1024;
constant CFG_GRUSBDC_I15 : integer := 1024;
constant CFG_GRUSBDC_O0 : integer := 1024;
constant CFG_GRUSBDC_O1 : integer := 1024;
constant CFG_GRUSBDC_O2 : integer := 1024;
constant CFG_GRUSBDC_O3 : integer := 1024;
constant CFG_GRUSBDC_O4 : integer := 1024;
constant CFG_GRUSBDC_O5 : integer := 1024;
constant CFG_GRUSBDC_O6 : integer := 1024;
constant CFG_GRUSBDC_O7 : integer := 1024;
constant CFG_GRUSBDC_O8 : integer := 1024;
constant CFG_GRUSBDC_O9 : integer := 1024;
constant CFG_GRUSBDC_O10 : integer := 1024;
constant CFG_GRUSBDC_O11 : integer := 1024;
constant CFG_GRUSBDC_O12 : integer := 1024;
constant CFG_GRUSBDC_O13 : integer := 1024;
constant CFG_GRUSBDC_O14 : integer := 1024;
constant CFG_GRUSBDC_O15 : integer := 1024;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 32;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (1);
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE is
port(
HCLK : in vl_logic;
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in vl_logic;
PWDATA : in vl_logic_vector(31 downto 0);
PRDATA : out vl_logic_vector(31 downto 0);
PREADY : out vl_logic;
PSLVERR : out vl_logic;
INTERRUPT : out vl_logic_vector(85 downto 0);
ADC0_TVC : out vl_logic_vector(7 downto 0);
ADC1_TVC : out vl_logic_vector(7 downto 0);
ADC2_TVC : out vl_logic_vector(7 downto 0);
ADC0_STC : out vl_logic_vector(7 downto 0);
ADC1_STC : out vl_logic_vector(7 downto 0);
ADC2_STC : out vl_logic_vector(7 downto 0);
ADC0_MODE : out vl_logic_vector(3 downto 0);
ADC1_MODE : out vl_logic_vector(3 downto 0);
ADC2_MODE : out vl_logic_vector(3 downto 0);
ADC_VAREFSEL : out vl_logic;
ABPOWERON : out vl_logic;
ADC0_CHNUMBER : out vl_logic_vector(4 downto 0);
ADC1_CHNUMBER : out vl_logic_vector(4 downto 0);
ADC2_CHNUMBER : out vl_logic_vector(4 downto 0);
ADC0_ADCSTART : out vl_logic;
ADC1_ADCSTART : out vl_logic;
ADC2_ADCSTART : out vl_logic;
ADC0_PWRDWN : out vl_logic;
ADC1_PWRDWN : out vl_logic;
ADC2_PWRDWN : out vl_logic;
ADC0_ADCRESET : out vl_logic;
ADC1_ADCRESET : out vl_logic;
ADC2_ADCRESET : out vl_logic;
ADC0_BUSY : in vl_logic;
ADC1_BUSY : in vl_logic;
ADC2_BUSY : in vl_logic;
ADC0_CALIBRATE : in vl_logic;
ADC1_CALIBRATE : in vl_logic;
ADC2_CALIBRATE : in vl_logic;
ADC0_DATAVALID : in vl_logic;
ADC1_DATAVALID : in vl_logic;
ADC2_DATAVALID : in vl_logic;
ADC0_SAMPLE : in vl_logic;
ADC1_SAMPLE : in vl_logic;
ADC2_SAMPLE : in vl_logic;
ADC0_RESULT : in vl_logic_vector(11 downto 0);
ADC1_RESULT : in vl_logic_vector(11 downto 0);
ADC2_RESULT : in vl_logic_vector(11 downto 0);
ACB_ADDR : out vl_logic_vector(7 downto 0);
ACB_WRE : out vl_logic;
ACB_WDATA : out vl_logic_vector(7 downto 0);
ACB_RDATA : in vl_logic_vector(7 downto 0);
ACB_RESETN : out vl_logic;
COMPARATOR : in vl_logic_vector(11 downto 0);
OBD_DOUT : out vl_logic_vector(2 downto 0);
OBD_CLKOUT : out vl_logic_vector(2 downto 0);
OBD_ENABLE : out vl_logic_vector(2 downto 0);
FPGA_OBD_DOUT : in vl_logic_vector(2 downto 0);
FPGA_OBD_CLKOUT : in vl_logic_vector(2 downto 0);
FPGA_TRIGGER : in vl_logic;
FPGA_FLAGS : out vl_logic_vector(31 downto 0);
ACE_INREADY : out vl_logic;
ACE_OUTREADY : out vl_logic;
TESTMODE : in vl_logic;
RB_TEST : in vl_logic;
PPE_CSBA : in vl_logic;
PPE_CSBB : in vl_logic;
PPE_RWBA : in vl_logic;
PPE_RWBB : in vl_logic;
PPE_ADA : in vl_logic_vector(8 downto 0);
PPE_ADB : in vl_logic_vector(8 downto 0);
PPE_WDA : in vl_logic_vector(31 downto 0);
PPE_WDB : in vl_logic_vector(31 downto 0);
PPE_RDA : out vl_logic_vector(31 downto 0);
PPE_RDB : out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE is
port(
HCLK : in vl_logic;
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in vl_logic;
PWDATA : in vl_logic_vector(31 downto 0);
PRDATA : out vl_logic_vector(31 downto 0);
PREADY : out vl_logic;
PSLVERR : out vl_logic;
INTERRUPT : out vl_logic_vector(85 downto 0);
ADC0_TVC : out vl_logic_vector(7 downto 0);
ADC1_TVC : out vl_logic_vector(7 downto 0);
ADC2_TVC : out vl_logic_vector(7 downto 0);
ADC0_STC : out vl_logic_vector(7 downto 0);
ADC1_STC : out vl_logic_vector(7 downto 0);
ADC2_STC : out vl_logic_vector(7 downto 0);
ADC0_MODE : out vl_logic_vector(3 downto 0);
ADC1_MODE : out vl_logic_vector(3 downto 0);
ADC2_MODE : out vl_logic_vector(3 downto 0);
ADC_VAREFSEL : out vl_logic;
ABPOWERON : out vl_logic;
ADC0_CHNUMBER : out vl_logic_vector(4 downto 0);
ADC1_CHNUMBER : out vl_logic_vector(4 downto 0);
ADC2_CHNUMBER : out vl_logic_vector(4 downto 0);
ADC0_ADCSTART : out vl_logic;
ADC1_ADCSTART : out vl_logic;
ADC2_ADCSTART : out vl_logic;
ADC0_PWRDWN : out vl_logic;
ADC1_PWRDWN : out vl_logic;
ADC2_PWRDWN : out vl_logic;
ADC0_ADCRESET : out vl_logic;
ADC1_ADCRESET : out vl_logic;
ADC2_ADCRESET : out vl_logic;
ADC0_BUSY : in vl_logic;
ADC1_BUSY : in vl_logic;
ADC2_BUSY : in vl_logic;
ADC0_CALIBRATE : in vl_logic;
ADC1_CALIBRATE : in vl_logic;
ADC2_CALIBRATE : in vl_logic;
ADC0_DATAVALID : in vl_logic;
ADC1_DATAVALID : in vl_logic;
ADC2_DATAVALID : in vl_logic;
ADC0_SAMPLE : in vl_logic;
ADC1_SAMPLE : in vl_logic;
ADC2_SAMPLE : in vl_logic;
ADC0_RESULT : in vl_logic_vector(11 downto 0);
ADC1_RESULT : in vl_logic_vector(11 downto 0);
ADC2_RESULT : in vl_logic_vector(11 downto 0);
ACB_ADDR : out vl_logic_vector(7 downto 0);
ACB_WRE : out vl_logic;
ACB_WDATA : out vl_logic_vector(7 downto 0);
ACB_RDATA : in vl_logic_vector(7 downto 0);
ACB_RESETN : out vl_logic;
COMPARATOR : in vl_logic_vector(11 downto 0);
OBD_DOUT : out vl_logic_vector(2 downto 0);
OBD_CLKOUT : out vl_logic_vector(2 downto 0);
OBD_ENABLE : out vl_logic_vector(2 downto 0);
FPGA_OBD_DOUT : in vl_logic_vector(2 downto 0);
FPGA_OBD_CLKOUT : in vl_logic_vector(2 downto 0);
FPGA_TRIGGER : in vl_logic;
FPGA_FLAGS : out vl_logic_vector(31 downto 0);
ACE_INREADY : out vl_logic;
ACE_OUTREADY : out vl_logic;
TESTMODE : in vl_logic;
RB_TEST : in vl_logic;
PPE_CSBA : in vl_logic;
PPE_CSBB : in vl_logic;
PPE_RWBA : in vl_logic;
PPE_RWBB : in vl_logic;
PPE_ADA : in vl_logic_vector(8 downto 0);
PPE_ADB : in vl_logic_vector(8 downto 0);
PPE_WDA : in vl_logic_vector(31 downto 0);
PPE_WDB : in vl_logic_vector(31 downto 0);
PPE_RDA : out vl_logic_vector(31 downto 0);
PPE_RDB : out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE is
port(
HCLK : in vl_logic;
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in vl_logic;
PWDATA : in vl_logic_vector(31 downto 0);
PRDATA : out vl_logic_vector(31 downto 0);
PREADY : out vl_logic;
PSLVERR : out vl_logic;
INTERRUPT : out vl_logic_vector(85 downto 0);
ADC0_TVC : out vl_logic_vector(7 downto 0);
ADC1_TVC : out vl_logic_vector(7 downto 0);
ADC2_TVC : out vl_logic_vector(7 downto 0);
ADC0_STC : out vl_logic_vector(7 downto 0);
ADC1_STC : out vl_logic_vector(7 downto 0);
ADC2_STC : out vl_logic_vector(7 downto 0);
ADC0_MODE : out vl_logic_vector(3 downto 0);
ADC1_MODE : out vl_logic_vector(3 downto 0);
ADC2_MODE : out vl_logic_vector(3 downto 0);
ADC_VAREFSEL : out vl_logic;
ABPOWERON : out vl_logic;
ADC0_CHNUMBER : out vl_logic_vector(4 downto 0);
ADC1_CHNUMBER : out vl_logic_vector(4 downto 0);
ADC2_CHNUMBER : out vl_logic_vector(4 downto 0);
ADC0_ADCSTART : out vl_logic;
ADC1_ADCSTART : out vl_logic;
ADC2_ADCSTART : out vl_logic;
ADC0_PWRDWN : out vl_logic;
ADC1_PWRDWN : out vl_logic;
ADC2_PWRDWN : out vl_logic;
ADC0_ADCRESET : out vl_logic;
ADC1_ADCRESET : out vl_logic;
ADC2_ADCRESET : out vl_logic;
ADC0_BUSY : in vl_logic;
ADC1_BUSY : in vl_logic;
ADC2_BUSY : in vl_logic;
ADC0_CALIBRATE : in vl_logic;
ADC1_CALIBRATE : in vl_logic;
ADC2_CALIBRATE : in vl_logic;
ADC0_DATAVALID : in vl_logic;
ADC1_DATAVALID : in vl_logic;
ADC2_DATAVALID : in vl_logic;
ADC0_SAMPLE : in vl_logic;
ADC1_SAMPLE : in vl_logic;
ADC2_SAMPLE : in vl_logic;
ADC0_RESULT : in vl_logic_vector(11 downto 0);
ADC1_RESULT : in vl_logic_vector(11 downto 0);
ADC2_RESULT : in vl_logic_vector(11 downto 0);
ACB_ADDR : out vl_logic_vector(7 downto 0);
ACB_WRE : out vl_logic;
ACB_WDATA : out vl_logic_vector(7 downto 0);
ACB_RDATA : in vl_logic_vector(7 downto 0);
ACB_RESETN : out vl_logic;
COMPARATOR : in vl_logic_vector(11 downto 0);
OBD_DOUT : out vl_logic_vector(2 downto 0);
OBD_CLKOUT : out vl_logic_vector(2 downto 0);
OBD_ENABLE : out vl_logic_vector(2 downto 0);
FPGA_OBD_DOUT : in vl_logic_vector(2 downto 0);
FPGA_OBD_CLKOUT : in vl_logic_vector(2 downto 0);
FPGA_TRIGGER : in vl_logic;
FPGA_FLAGS : out vl_logic_vector(31 downto 0);
ACE_INREADY : out vl_logic;
ACE_OUTREADY : out vl_logic;
TESTMODE : in vl_logic;
RB_TEST : in vl_logic;
PPE_CSBA : in vl_logic;
PPE_CSBB : in vl_logic;
PPE_RWBA : in vl_logic;
PPE_RWBB : in vl_logic;
PPE_ADA : in vl_logic_vector(8 downto 0);
PPE_ADB : in vl_logic_vector(8 downto 0);
PPE_WDA : in vl_logic_vector(31 downto 0);
PPE_WDB : in vl_logic_vector(31 downto 0);
PPE_RDA : out vl_logic_vector(31 downto 0);
PPE_RDB : out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE;
|
------------------------------------------------------------------------------------------------------------------------
-- RMII to MII converter
-- ex: openMAC - openHUB - RMII2MII - MII PHY
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: Used DPR is specific to Altera/Xilinx. Use one of the following files:
-- OpenMAC_DPR_Altera.vhd
-- OpenMAC_DPR_Xilinx.vhd
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-09-13 V0.01 first version
-- 2010-11-15 V0.02 bug fix: increased size of rx fifo, because of errors with marvel 88e1111 mii phy
-- 2010-11-30 V0.03 bug fix: in case of no link some phys confuse tx fifo during tx => aclr fifo
-- 2011-05-06 V0.10 bug fix: use the RX_ER signal, it has important meaning!
-- 2011-07-23 V0.11 forward RxErr to RMII
-- 2011-10-13 V0.20 abuse openMAC_DMAFifo for the converter to use it in Altera/Xilinx easily
-- 2011-11-07 V0.21 increased fifo word size to be on the save side
-- 2011-11-18 V0.22 forward of RxErr not necessary
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rmii2mii is
port (
clk50 : in std_logic; --used by RMII as well!!!
rst : in std_logic;
--RMII (MAC)
rTxEn : in std_logic;
rTxDat : in std_logic_vector(1 downto 0);
rRxDv : out std_logic;
rRxDat : out std_logic_vector(1 downto 0);
rRxEr : out std_logic;
--MII (PHY)
mTxEn : out std_logic;
mTxDat : out std_logic_vector(3 downto 0);
mTxClk : in std_logic;
mRxDv : in std_logic;
mRxEr : in std_logic;
mRxDat : in std_logic_vector(3 downto 0);
mRxClk : in std_logic
);
end rmii2mii;
architecture rtl of rmii2mii is
constant DIBIT_SIZE : integer := 2;
constant NIBBLE_SIZE : integer := 4;
begin
TX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_full, fifo_empty, fifo_valid, fifo_wrempty : std_logic;
signal fifo_wr, fifo_rd : std_logic;
signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0);
signal fifo_wrUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0);
--necessary for clr fifo
signal aclr, rTxEn_l : std_logic;
--convert dibits to nibble
signal sel_dibit : std_logic;
signal fifo_din_reg : std_logic_vector(rTxDat'range);
begin
fifo_din <= rTxDat & fifo_din_reg;
fifo_wr <= sel_dibit;
--convert dibits to nibble (to fit to fifo)
process(clk50, rst)
begin
if rst = '1' then
sel_dibit <= '0';
fifo_din_reg <= (others => '0');
elsif clk50 = '1' and clk50'event then
if rTxEn = '1' then
sel_dibit <= not sel_dibit;
if sel_dibit = '0' then
fifo_din_reg <= rTxDat;
end if;
else
sel_dibit <= '0';
end if;
end if;
end process;
mTxDat <= fifo_dout; --brauch ma net... when fifo_valid = '1' else (others => '0');
mTxEn <= fifo_valid;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
process(mTxClk, rst)
begin
if rst = '1' then
fifo_rd <= '0';
fifo_valid <= '0';
elsif mTxClk = '1' and mTxClk'event then
if fifo_rd = '0' and fifo_half = '1' then
fifo_rd <= '1';
elsif fifo_rd = '1' and fifo_empty = '1' then
fifo_rd <= '0';
end if;
if fifo_rd = '1' and fifo_rdUsedWord > conv_std_logic_vector(1, fifo_rdUsedWord'length) then
fifo_valid <= '1';
else
fifo_valid <= '0';
end if;
end if;
end process;
--abuse openMAC's DMA FIFO
theRMII2MII_TXFifo : entity work.openMAC_DMAfifo
generic map (
fifo_data_width_g => NIBBLE_SIZE,
fifo_word_size_g => 2**FIFO_NIBBLES_LOG2,
fifo_word_size_log2_g => FIFO_NIBBLES_LOG2
)
port map (
aclr => aclr,
rd_clk => mTxClk,
wr_clk => clk50,
--read port
rd_req => fifo_rd,
rd_data => fifo_dout,
rd_empty => fifo_empty,
rd_full => open,
rd_usedw => fifo_rdUsedWord,
--write port
wr_req => fifo_wr,
wr_data => fifo_din,
wr_empty => fifo_wrempty,
wr_full => fifo_full,
wr_usedw => fifo_wrUsedWord
);
--sync Mii Tx En (=fifo_valid) to wr clk
process(clk50, rst)
begin
if rst = '1' then
aclr <= '1'; --reset fifo
rTxEn_l <= '0';
elsif clk50 = '1' and clk50'event then
rTxEn_l <= rTxEn;
aclr <= '0'; --default
--clear the full fifo after TX on RMII side is done
if fifo_full = '1' and rTxEn_l = '1' and rTxEn = '0' then
aclr <= '1';
end if;
end if;
end process;
end block;
RX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_full, fifo_empty, fifo_valid : std_logic;
signal fifo_wr, fifo_rd : std_logic;
signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
signal fifo_wrUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
--convert nibble to dibits
signal sel_dibit : std_logic;
signal fifo_rd_s : std_logic;
begin
fifo_din <= mRxDat;
fifo_wr <= mRxDv and not mRxEr;
rRxDat <= fifo_dout(fifo_dout'right+1 downto 0) when sel_dibit = '1' else
fifo_dout(fifo_dout'left downto fifo_dout'left-1);
rRxDv <= fifo_valid;
fifo_rd <= fifo_rd_s and not sel_dibit;
process(clk50, rst)
begin
if rst = '1' then
sel_dibit <= '0';
elsif clk50 = '1' and clk50'event then
if fifo_rd_s = '1' or fifo_valid = '1' then
sel_dibit <= not sel_dibit;
else
sel_dibit <= '0';
end if;
end if;
end process;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
rRxEr <= '0';
process(clk50, rst)
begin
if rst = '1' then
fifo_rd_s <= '0';
fifo_valid <= '0';
elsif clk50 = '1' and clk50'event then
if fifo_rd_s = '0' and fifo_half = '1' then
fifo_rd_s <= '1';
elsif fifo_rd_s = '1' and fifo_empty = '1' then
fifo_rd_s <= '0';
end if;
if fifo_rd_s = '1' then
fifo_valid <= '1';
else
fifo_valid <= '0';
end if;
end if;
end process;
--abuse openMAC's DMA FIFO
theMII2RMII_RXFifo : entity work.openMAC_DMAfifo
generic map (
fifo_data_width_g => NIBBLE_SIZE,
fifo_word_size_g => 2**FIFO_NIBBLES_LOG2,
fifo_word_size_log2_g => FIFO_NIBBLES_LOG2
)
port map (
aclr => rst,
rd_clk => clk50,
wr_clk => mRxClk,
--read port
rd_req => fifo_rd,
rd_data => fifo_dout,
rd_empty => fifo_empty,
rd_full => open,
rd_usedw => fifo_rdUsedWord,
--write port
wr_req => fifo_wr,
wr_data => fifo_din,
wr_empty => open,
wr_full => fifo_full,
wr_usedw => fifo_wrUsedWord
);
end block;
end rtl;
|
------------------------------------------------------------------------------------------------------------------------
-- RMII to MII converter
-- ex: openMAC - openHUB - RMII2MII - MII PHY
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: Used DPR is specific to Altera/Xilinx. Use one of the following files:
-- OpenMAC_DPR_Altera.vhd
-- OpenMAC_DPR_Xilinx.vhd
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-09-13 V0.01 first version
-- 2010-11-15 V0.02 bug fix: increased size of rx fifo, because of errors with marvel 88e1111 mii phy
-- 2010-11-30 V0.03 bug fix: in case of no link some phys confuse tx fifo during tx => aclr fifo
-- 2011-05-06 V0.10 bug fix: use the RX_ER signal, it has important meaning!
-- 2011-07-23 V0.11 forward RxErr to RMII
-- 2011-10-13 V0.20 abuse openMAC_DMAFifo for the converter to use it in Altera/Xilinx easily
-- 2011-11-07 V0.21 increased fifo word size to be on the save side
-- 2011-11-18 V0.22 forward of RxErr not necessary
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rmii2mii is
port (
clk50 : in std_logic; --used by RMII as well!!!
rst : in std_logic;
--RMII (MAC)
rTxEn : in std_logic;
rTxDat : in std_logic_vector(1 downto 0);
rRxDv : out std_logic;
rRxDat : out std_logic_vector(1 downto 0);
rRxEr : out std_logic;
--MII (PHY)
mTxEn : out std_logic;
mTxDat : out std_logic_vector(3 downto 0);
mTxClk : in std_logic;
mRxDv : in std_logic;
mRxEr : in std_logic;
mRxDat : in std_logic_vector(3 downto 0);
mRxClk : in std_logic
);
end rmii2mii;
architecture rtl of rmii2mii is
constant DIBIT_SIZE : integer := 2;
constant NIBBLE_SIZE : integer := 4;
begin
TX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_full, fifo_empty, fifo_valid, fifo_wrempty : std_logic;
signal fifo_wr, fifo_rd : std_logic;
signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0);
signal fifo_wrUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0);
--necessary for clr fifo
signal aclr, rTxEn_l : std_logic;
--convert dibits to nibble
signal sel_dibit : std_logic;
signal fifo_din_reg : std_logic_vector(rTxDat'range);
begin
fifo_din <= rTxDat & fifo_din_reg;
fifo_wr <= sel_dibit;
--convert dibits to nibble (to fit to fifo)
process(clk50, rst)
begin
if rst = '1' then
sel_dibit <= '0';
fifo_din_reg <= (others => '0');
elsif clk50 = '1' and clk50'event then
if rTxEn = '1' then
sel_dibit <= not sel_dibit;
if sel_dibit = '0' then
fifo_din_reg <= rTxDat;
end if;
else
sel_dibit <= '0';
end if;
end if;
end process;
mTxDat <= fifo_dout; --brauch ma net... when fifo_valid = '1' else (others => '0');
mTxEn <= fifo_valid;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
process(mTxClk, rst)
begin
if rst = '1' then
fifo_rd <= '0';
fifo_valid <= '0';
elsif mTxClk = '1' and mTxClk'event then
if fifo_rd = '0' and fifo_half = '1' then
fifo_rd <= '1';
elsif fifo_rd = '1' and fifo_empty = '1' then
fifo_rd <= '0';
end if;
if fifo_rd = '1' and fifo_rdUsedWord > conv_std_logic_vector(1, fifo_rdUsedWord'length) then
fifo_valid <= '1';
else
fifo_valid <= '0';
end if;
end if;
end process;
--abuse openMAC's DMA FIFO
theRMII2MII_TXFifo : entity work.openMAC_DMAfifo
generic map (
fifo_data_width_g => NIBBLE_SIZE,
fifo_word_size_g => 2**FIFO_NIBBLES_LOG2,
fifo_word_size_log2_g => FIFO_NIBBLES_LOG2
)
port map (
aclr => aclr,
rd_clk => mTxClk,
wr_clk => clk50,
--read port
rd_req => fifo_rd,
rd_data => fifo_dout,
rd_empty => fifo_empty,
rd_full => open,
rd_usedw => fifo_rdUsedWord,
--write port
wr_req => fifo_wr,
wr_data => fifo_din,
wr_empty => fifo_wrempty,
wr_full => fifo_full,
wr_usedw => fifo_wrUsedWord
);
--sync Mii Tx En (=fifo_valid) to wr clk
process(clk50, rst)
begin
if rst = '1' then
aclr <= '1'; --reset fifo
rTxEn_l <= '0';
elsif clk50 = '1' and clk50'event then
rTxEn_l <= rTxEn;
aclr <= '0'; --default
--clear the full fifo after TX on RMII side is done
if fifo_full = '1' and rTxEn_l = '1' and rTxEn = '0' then
aclr <= '1';
end if;
end if;
end process;
end block;
RX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_full, fifo_empty, fifo_valid : std_logic;
signal fifo_wr, fifo_rd : std_logic;
signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
signal fifo_wrUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
--convert nibble to dibits
signal sel_dibit : std_logic;
signal fifo_rd_s : std_logic;
begin
fifo_din <= mRxDat;
fifo_wr <= mRxDv and not mRxEr;
rRxDat <= fifo_dout(fifo_dout'right+1 downto 0) when sel_dibit = '1' else
fifo_dout(fifo_dout'left downto fifo_dout'left-1);
rRxDv <= fifo_valid;
fifo_rd <= fifo_rd_s and not sel_dibit;
process(clk50, rst)
begin
if rst = '1' then
sel_dibit <= '0';
elsif clk50 = '1' and clk50'event then
if fifo_rd_s = '1' or fifo_valid = '1' then
sel_dibit <= not sel_dibit;
else
sel_dibit <= '0';
end if;
end if;
end process;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
rRxEr <= '0';
process(clk50, rst)
begin
if rst = '1' then
fifo_rd_s <= '0';
fifo_valid <= '0';
elsif clk50 = '1' and clk50'event then
if fifo_rd_s = '0' and fifo_half = '1' then
fifo_rd_s <= '1';
elsif fifo_rd_s = '1' and fifo_empty = '1' then
fifo_rd_s <= '0';
end if;
if fifo_rd_s = '1' then
fifo_valid <= '1';
else
fifo_valid <= '0';
end if;
end if;
end process;
--abuse openMAC's DMA FIFO
theMII2RMII_RXFifo : entity work.openMAC_DMAfifo
generic map (
fifo_data_width_g => NIBBLE_SIZE,
fifo_word_size_g => 2**FIFO_NIBBLES_LOG2,
fifo_word_size_log2_g => FIFO_NIBBLES_LOG2
)
port map (
aclr => rst,
rd_clk => clk50,
wr_clk => mRxClk,
--read port
rd_req => fifo_rd,
rd_data => fifo_dout,
rd_empty => fifo_empty,
rd_full => open,
rd_usedw => fifo_rdUsedWord,
--write port
wr_req => fifo_wr,
wr_data => fifo_din,
wr_empty => open,
wr_full => fifo_full,
wr_usedw => fifo_wrUsedWord
);
end block;
end rtl;
|
------------------------------------------------------------------------------------------------------------------------
-- RMII to MII converter
-- ex: openMAC - openHUB - RMII2MII - MII PHY
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: Used DPR is specific to Altera/Xilinx. Use one of the following files:
-- OpenMAC_DPR_Altera.vhd
-- OpenMAC_DPR_Xilinx.vhd
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-09-13 V0.01 first version
-- 2010-11-15 V0.02 bug fix: increased size of rx fifo, because of errors with marvel 88e1111 mii phy
-- 2010-11-30 V0.03 bug fix: in case of no link some phys confuse tx fifo during tx => aclr fifo
-- 2011-05-06 V0.10 bug fix: use the RX_ER signal, it has important meaning!
-- 2011-07-23 V0.11 forward RxErr to RMII
-- 2011-10-13 V0.20 abuse openMAC_DMAFifo for the converter to use it in Altera/Xilinx easily
-- 2011-11-07 V0.21 increased fifo word size to be on the save side
-- 2011-11-18 V0.22 forward of RxErr not necessary
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rmii2mii is
port (
clk50 : in std_logic; --used by RMII as well!!!
rst : in std_logic;
--RMII (MAC)
rTxEn : in std_logic;
rTxDat : in std_logic_vector(1 downto 0);
rRxDv : out std_logic;
rRxDat : out std_logic_vector(1 downto 0);
rRxEr : out std_logic;
--MII (PHY)
mTxEn : out std_logic;
mTxDat : out std_logic_vector(3 downto 0);
mTxClk : in std_logic;
mRxDv : in std_logic;
mRxEr : in std_logic;
mRxDat : in std_logic_vector(3 downto 0);
mRxClk : in std_logic
);
end rmii2mii;
architecture rtl of rmii2mii is
constant DIBIT_SIZE : integer := 2;
constant NIBBLE_SIZE : integer := 4;
begin
TX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_full, fifo_empty, fifo_valid, fifo_wrempty : std_logic;
signal fifo_wr, fifo_rd : std_logic;
signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0);
signal fifo_wrUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0);
--necessary for clr fifo
signal aclr, rTxEn_l : std_logic;
--convert dibits to nibble
signal sel_dibit : std_logic;
signal fifo_din_reg : std_logic_vector(rTxDat'range);
begin
fifo_din <= rTxDat & fifo_din_reg;
fifo_wr <= sel_dibit;
--convert dibits to nibble (to fit to fifo)
process(clk50, rst)
begin
if rst = '1' then
sel_dibit <= '0';
fifo_din_reg <= (others => '0');
elsif clk50 = '1' and clk50'event then
if rTxEn = '1' then
sel_dibit <= not sel_dibit;
if sel_dibit = '0' then
fifo_din_reg <= rTxDat;
end if;
else
sel_dibit <= '0';
end if;
end if;
end process;
mTxDat <= fifo_dout; --brauch ma net... when fifo_valid = '1' else (others => '0');
mTxEn <= fifo_valid;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
process(mTxClk, rst)
begin
if rst = '1' then
fifo_rd <= '0';
fifo_valid <= '0';
elsif mTxClk = '1' and mTxClk'event then
if fifo_rd = '0' and fifo_half = '1' then
fifo_rd <= '1';
elsif fifo_rd = '1' and fifo_empty = '1' then
fifo_rd <= '0';
end if;
if fifo_rd = '1' and fifo_rdUsedWord > conv_std_logic_vector(1, fifo_rdUsedWord'length) then
fifo_valid <= '1';
else
fifo_valid <= '0';
end if;
end if;
end process;
--abuse openMAC's DMA FIFO
theRMII2MII_TXFifo : entity work.openMAC_DMAfifo
generic map (
fifo_data_width_g => NIBBLE_SIZE,
fifo_word_size_g => 2**FIFO_NIBBLES_LOG2,
fifo_word_size_log2_g => FIFO_NIBBLES_LOG2
)
port map (
aclr => aclr,
rd_clk => mTxClk,
wr_clk => clk50,
--read port
rd_req => fifo_rd,
rd_data => fifo_dout,
rd_empty => fifo_empty,
rd_full => open,
rd_usedw => fifo_rdUsedWord,
--write port
wr_req => fifo_wr,
wr_data => fifo_din,
wr_empty => fifo_wrempty,
wr_full => fifo_full,
wr_usedw => fifo_wrUsedWord
);
--sync Mii Tx En (=fifo_valid) to wr clk
process(clk50, rst)
begin
if rst = '1' then
aclr <= '1'; --reset fifo
rTxEn_l <= '0';
elsif clk50 = '1' and clk50'event then
rTxEn_l <= rTxEn;
aclr <= '0'; --default
--clear the full fifo after TX on RMII side is done
if fifo_full = '1' and rTxEn_l = '1' and rTxEn = '0' then
aclr <= '1';
end if;
end if;
end process;
end block;
RX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_full, fifo_empty, fifo_valid : std_logic;
signal fifo_wr, fifo_rd : std_logic;
signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
signal fifo_wrUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
--convert nibble to dibits
signal sel_dibit : std_logic;
signal fifo_rd_s : std_logic;
begin
fifo_din <= mRxDat;
fifo_wr <= mRxDv and not mRxEr;
rRxDat <= fifo_dout(fifo_dout'right+1 downto 0) when sel_dibit = '1' else
fifo_dout(fifo_dout'left downto fifo_dout'left-1);
rRxDv <= fifo_valid;
fifo_rd <= fifo_rd_s and not sel_dibit;
process(clk50, rst)
begin
if rst = '1' then
sel_dibit <= '0';
elsif clk50 = '1' and clk50'event then
if fifo_rd_s = '1' or fifo_valid = '1' then
sel_dibit <= not sel_dibit;
else
sel_dibit <= '0';
end if;
end if;
end process;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
rRxEr <= '0';
process(clk50, rst)
begin
if rst = '1' then
fifo_rd_s <= '0';
fifo_valid <= '0';
elsif clk50 = '1' and clk50'event then
if fifo_rd_s = '0' and fifo_half = '1' then
fifo_rd_s <= '1';
elsif fifo_rd_s = '1' and fifo_empty = '1' then
fifo_rd_s <= '0';
end if;
if fifo_rd_s = '1' then
fifo_valid <= '1';
else
fifo_valid <= '0';
end if;
end if;
end process;
--abuse openMAC's DMA FIFO
theMII2RMII_RXFifo : entity work.openMAC_DMAfifo
generic map (
fifo_data_width_g => NIBBLE_SIZE,
fifo_word_size_g => 2**FIFO_NIBBLES_LOG2,
fifo_word_size_log2_g => FIFO_NIBBLES_LOG2
)
port map (
aclr => rst,
rd_clk => clk50,
wr_clk => mRxClk,
--read port
rd_req => fifo_rd,
rd_data => fifo_dout,
rd_empty => fifo_empty,
rd_full => open,
rd_usedw => fifo_rdUsedWord,
--write port
wr_req => fifo_wr,
wr_data => fifo_din,
wr_empty => open,
wr_full => fifo_full,
wr_usedw => fifo_wrUsedWord
);
end block;
end rtl;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_realign.vhd
--
-- Description:
-- This file implements the S2MM Data Realignment module. THe S2MM direction is
-- more complex than the MM2S direction since the DRE needs to be upstream from
-- the Write Data Controller. This requires the S2MM DRE to be running 2 to
-- 3 clocks ahead of the Write Data controller to minimize/eliminate xfer
-- bubble insertion.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_fifo;
use axi_datamover_v5_1.axi_datamover_s2mm_dre;
use axi_datamover_v5_1.axi_datamover_s2mm_scatter;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_realign is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the IBTT Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_INCLUDE_DRE : Integer range 0 to 1 := 1;
-- Includes/Omits the S2MM DRE
-- 0 = Omit
-- 1 = Include
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal command queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_SUPPORT_SCATTER : Integer range 0 to 1 := 1;
-- Includes/Omits the Scatter functionality
-- 0 = omit
-- 1 = include
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_BTT_USED : Integer range 8 to 23 := 16;
-- Indicates the width of the input command BTT that is actually
-- used
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Input and Output Stream Data ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the input command Tag port
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 ;
-- Sets the width of the Store and Forward Start offset ports
C_FAMILY : String := "virtex7"
-- specifies the target FPGA familiy
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------------
-- Write Data Controller or IBTT Indeterminate BTT I/O -------------------------
--
wdc2dre_wready : In std_logic; --
-- Write READY input from WDC or SF --
--
dre2wdc_wvalid : Out std_logic; --
-- Write VALID output to WDC or SF --
--
dre2wdc_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wlast : Out std_logic; --
-- Write LAST output to WDC or SF --
--
dre2wdc_eop : Out std_logic; --
-- End of Packet indicator for the Stream input to WDC or SF --
--------------------------------------------------------------------------------
-- Starting offset output for the Store and Forward Modules -------------------
--
dre2sf_strt_offset : Out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Command Calculator Interface ---------------------------------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2dre_cmd_cmplt : In std_logic; --
-- The last tranfer command of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- Premature TLAST assertion error flag -----------------------------
--
dre2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the DRE detected --
-- a Early/Late TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------
-- DRE Halted Status ------------------------------------------------
--
dre2all_halted : Out std_logic --
-- When asserted, this indicates the DRE has satisfied --
-- all pending transfers queued by the command calculator --
-- and is halted. --
---------------------------------------------------------------------
);
end entity axi_datamover_s2mm_realign;
architecture implementation of axi_datamover_s2mm_realign is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations --------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_realign_fifo
--
-- Function Description:
-- Assures that the Realigner cmd fifo depth is at least 4 deep else it
-- is equal to the pipe depth.
--
-------------------------------------------------------------------
function funct_size_realign_fifo (pipe_depth : integer) return integer is
Variable temp_fifo_depth : Integer := 4;
begin
If (pipe_depth < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := pipe_depth;
End if;
Return (temp_fifo_depth);
end function funct_size_realign_fifo;
-- Constant Declarations --------------------------------------------
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant BTT_WIDTH : integer := C_BTT_USED;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant BTT_OF_ZERO : std_logic_vector(BTT_WIDTH-1 downto 0)
:= (others => '0');
Constant DRECTL_FIFO_DEPTH : integer := funct_size_realign_fifo(C_DRE_CNTL_FIFO_DEPTH);
Constant DRECTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
BTT_WIDTH + -- BTT field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant BTT_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := BTT_STRT_INDEX + BTT_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
Constant INCLUDE_DRE : boolean := (C_INCLUDE_DRE = 1 and
C_STREAM_DWIDTH <= 64 and
C_STREAM_DWIDTH >= 16);
Constant OMIT_DRE : boolean := not(INCLUDE_DRE);
-- Type Declarations --------------------------------------------
type TYPE_CMD_CNTL_SM is (
INIT,
LD_DRE_SCATTER_FIRST,
CHK_POP_FIRST ,
LD_DRE_SCATTER_SECOND,
CHK_POP_SECOND,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_cmdcntl_sm_state : TYPE_CMD_CNTL_SM := INIT;
Signal sig_cmdcntl_sm_state_ns : TYPE_CMD_CNTL_SM := INIT;
signal sig_sm_ld_dre_cmd_ns : std_logic := '0';
signal sig_sm_ld_dre_cmd : std_logic := '0';
signal sig_sm_ld_scatter_cmd_ns : std_logic := '0';
signal sig_sm_ld_scatter_cmd : std_logic := '0';
signal sig_sm_pop_cmd_fifo_ns : std_logic := '0';
signal sig_sm_pop_cmd_fifo : std_logic := '0';
signal sig_cmd_fifo_data_in : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_btt_reg : std_logic_vector(BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_cmd_cmplt_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_dre2wdc_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2wdc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_dre2wdc_tlast : std_logic := '0';
signal sig_dre2wdc_tvalid : std_logic := '0';
signal sig_wdc2dre_tready : std_logic := '0';
signal sig_tlast_err0r : std_logic := '0';
signal sig_dre_halted : std_logic := '0';
signal sig_strm2scatter_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_strm2scatter_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm2scatter_tlast : std_logic := '0';
signal sig_strm2scatter_tvalid : std_logic := '0';
signal sig_scatter2strm_tready : std_logic := '0';
signal sig_scatter2dre_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_scatter2dre_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2dre_tlast : std_logic := '0';
signal sig_scatter2dre_tvalid : std_logic := '0';
signal sig_dre2scatter_tready : std_logic := '0';
signal sig_scatter2dre_flush : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_scatter2dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_cmd_ready : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic;
signal sig_drc2scatter_btt : std_logic_vector(BTT_WIDTH-1 downto 0);
signal sig_drc2scatter_eof : std_logic;
signal sig_scatter2all_tlast_error : std_logic := '0';
signal sig_need_cmd_flush : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_strt_offset : std_logic := '0';
signal sig_output_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2sf_strt_offset : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Port connections
-- Input Stream Attachment
s2mm_strm_wready <= sig_scatter2strm_tready ;
sig_strm2scatter_tvalid <= s2mm_strm_wvalid ;
sig_strm2scatter_tdata <= s2mm_strm_wdata ;
sig_strm2scatter_tstrb <= s2mm_strm_wstrb ;
sig_strm2scatter_tlast <= s2mm_strm_wlast ;
-- Write Data Controller Stream Attachment
sig_wdc2dre_tready <= wdc2dre_wready ;
dre2wdc_wvalid <= sig_dre2wdc_tvalid ;
dre2wdc_wdata <= sig_dre2wdc_tdata ;
dre2wdc_wstrb <= sig_dre2wdc_tstrb ;
dre2wdc_wlast <= sig_dre2wdc_tlast ;
-- Status/Error flags
dre2all_tlast_error <= sig_tlast_err0r ;
dre2all_halted <= sig_dre_halted ;
-- Store and Forward Starting Offset Output
dre2sf_strt_offset <= sig_dre2sf_strt_offset ;
-------------------------------------------------------------
-- Internal logic
sig_dre_halted <= sig_dre_align_ready;
-------------------------------------------------------------
-- DRE Handshake signals
sig_dre_src_align <= sig_curr_src_align_reg ;
sig_dre_dest_align <= sig_curr_dest_align_reg;
sig_dre_use_autodest <= '0'; -- not used
sig_dre_flush <= '0'; -- not used
-------------------------------------------------------------------------
-------- Realigner Command FIFO and controls
-------------------------------------------------------------------------
-- Command Calculator Handshake
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_cmd_cmplt &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_btt &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto DEST_ALIGN_STRT_INDEX);
sig_curr_btt_reg <= sig_cmd_fifo_data_out((BTT_STRT_INDEX+BTT_WIDTH)-1 downto BTT_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_cmd_cmplt_reg <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => DRECTL_FIFO_WIDTH ,
C_DEPTH => DRECTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_sm_pop_cmd_fifo ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-------- DRE and Scatter Command Loader State Machine
-------------------------------------------------------------------------
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CMDCNTL_SM_COMBINATIONAL
--
-- Process Description:
-- Command Controller State Machine combinational implementation
-- The design is based on the premise that for every parent
-- command loaded into the S2MM, the Realigner can be loaded with
-- 1 or 2 commands spawned from it. The first command is used to
-- align ensuing transfers (in MMap space) to a max burst address
-- boundary. Then, if the parent command's BTT value is not satisfied
-- after the first command completes, a second command is generated
-- and loaded in the Realigner for the remaining BTT value. The
-- command complete bit in the Realigner command indicates if the
-- first command the final command or the second command (if needed)
-- is the final command,
-------------------------------------------------------------
CMDCNTL_SM_COMBINATIONAL : process (sig_cmdcntl_sm_state ,
sig_fifo_rd_cmd_valid ,
sig_dre_align_ready ,
sig_scatter2drc_cmd_ready ,
sig_need_cmd_flush ,
sig_curr_cmd_cmplt_reg ,
sig_curr_calc_error_reg
)
begin
-- SM Defaults
sig_cmdcntl_sm_state_ns <= INIT;
sig_sm_ld_dre_cmd_ns <= '0';
sig_sm_ld_scatter_cmd_ns <= '0';
sig_sm_pop_cmd_fifo_ns <= '0';
case sig_cmdcntl_sm_state is
--------------------------------------------
when INIT =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
--------------------------------------------
when LD_DRE_SCATTER_FIRST =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
End if;
--------------------------------------------
when CHK_POP_FIRST =>
If (sig_curr_cmd_cmplt_reg = '1') Then
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
Else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when LD_DRE_SCATTER_SECOND =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_need_cmd_flush = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_SECOND ;
sig_sm_pop_cmd_fifo_ns <= '1';
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when CHK_POP_SECOND =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST ;
--------------------------------------------
when ERROR_TRAP =>
sig_cmdcntl_sm_state_ns <= ERROR_TRAP ;
--------------------------------------------
when others =>
sig_cmdcntl_sm_state_ns <= INIT;
end case;
end process CMDCNTL_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMDCNTL_SM_REGISTERED
--
-- Process Description:
-- Command Controller State Machine registered implementation
--
-------------------------------------------------------------
CMDCNTL_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_cmdcntl_sm_state <= INIT;
sig_sm_ld_dre_cmd <= '0' ;
sig_sm_ld_scatter_cmd <= '0' ;
sig_sm_pop_cmd_fifo <= '0' ;
else
sig_cmdcntl_sm_state <= sig_cmdcntl_sm_state_ns ;
sig_sm_ld_dre_cmd <= sig_sm_ld_dre_cmd_ns ;
sig_sm_ld_scatter_cmd <= sig_sm_ld_scatter_cmd_ns ;
sig_sm_pop_cmd_fifo <= sig_sm_pop_cmd_fifo_ns ;
end if;
end if;
end process CMDCNTL_SM_REGISTERED;
-------------------------------------------------------------------------
-------- DRE Instance and controls
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE
--
-- If Generate Description:
-- Includes the instance for the DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE : if (INCLUDE_DRE) generate
signal lsig_eop_reg : std_logic := '0';
signal lsig_dre_load_beat : std_logic := '0';
signal lsig_dre_tlast_output_beat : std_logic := '0';
signal lsig_set_eop : std_logic := '0';
signal lsig_tlast_err_reg1 : std_logic := '0';
signal lsig_tlast_err_reg2 : std_logic := '0';
signal lsig_push_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pushreg_full : std_logic := '0';
signal lsig_pushreg_empty : std_logic := '0';
signal lsig_pull_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pullreg_full : std_logic := '0';
signal lsig_pullreg_empty : std_logic := '0';
signal lsig_pull_new_offset : std_logic := '0';
signal lsig_push_new_offset : std_logic := '0';
begin
------------------------------------------------------------
-- Instance: I_S2MM_DRE_BLOCK
--
-- Description:
-- Instance for the S2MM Data Realignment Engine (DRE)
--
------------------------------------------------------------
I_S2MM_DRE_BLOCK : entity axi_datamover_v5_1.axi_datamover_s2mm_dre
generic map (
C_DWIDTH => C_STREAM_DWIDTH ,
C_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH
)
port map (
-- Clock and Reset
dre_clk => primary_aclk ,
dre_rst => mmap_reset ,
-- Alignment Control (Independent from Stream Input timing)
dre_align_ready => sig_dre_align_ready ,
dre_align_valid => sig_sm_ld_dre_cmd ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_scatter2dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
-- Flush Control (Aligned to input Stream timing)
dre_flush => sig_scatter2dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_scatter2dre_tstrb ,
dre_in_tdata => sig_scatter2dre_tdata ,
dre_in_tlast => sig_scatter2dre_tlast ,
dre_in_tvalid => sig_scatter2dre_tvalid ,
dre_in_tready => sig_dre2scatter_tready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2wdc_tstrb ,
dre_out_tdata => sig_dre2wdc_tdata ,
dre_out_tlast => sig_dre2wdc_tlast ,
dre_out_tvalid => sig_dre2wdc_tvalid ,
dre_out_tready => sig_wdc2dre_tready
);
lsig_dre_load_beat <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready;
lsig_set_eop <= sig_scatter2drc_eop and
lsig_dre_load_beat ;
lsig_dre_tlast_output_beat <= sig_dre2wdc_tvalid and
sig_wdc2dre_tready and
sig_dre2wdc_tlast;
dre2wdc_eop <= lsig_dre_tlast_output_beat and
lsig_eop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG
--
-- Process Description:
-- Implements a flop for holding the EOP from the Scatter
-- Engine until the corresponding packet clears out of the DRE.
-- THis is used to transfer the EOP marker to the DRE output
-- stream without the need for the DRE to pass it through.
--
-------------------------------------------------------------
IMP_EOP_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(lsig_dre_tlast_output_beat = '1' and
lsig_set_eop = '0')) then
lsig_eop_reg <= '0';
elsif (lsig_set_eop = '1') then
lsig_eop_reg <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_EOP_REG;
-- Delay TLAST Error by 2 clocks to compensate for DRE minimum
-- delay of 2 clocks for the stream data.
sig_tlast_err0r <= lsig_tlast_err_reg2;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_DELAY
--
-- Process Description:
-- Implements a 2 clock delay to better align the TLAST
-- error detection with the Stream output data to the WDC
-- which has a minimum 2 clock delay through the DRE.
--
-------------------------------------------------------------
IMP_TLAST_ERR_DELAY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_tlast_err_reg1 <= '0';
lsig_tlast_err_reg2 <= '0';
else
lsig_tlast_err_reg1 <= sig_scatter2all_tlast_error;
lsig_tlast_err_reg2 <= lsig_tlast_err_reg1;
end if;
end if;
end process IMP_TLAST_ERR_DELAY;
-------------------------------------------------------------------------
-- Store and Forward Start Address Offset Registers Logic
-- Push-pull register is used to to time align the starting address
-- offset (ripped from the Realigner command via parsing) to DRE
-- TLAST output timing. The offset output of the pull register must
-- be valid on the first output databeat of the DRE to the Store and
-- Forward module.
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= lsig_pull_strt_offset_reg;
-- lsig_push_new_offset <= sig_dre_align_ready and
-- sig_gated_dre_align_valid ;
lsig_push_new_offset <= sig_sm_ld_dre_cmd ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the input register for holding the starting address
-- offset sent to the external Store and Forward functions.
--
-------------------------------------------------------------
IMP_PUSH_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
elsif (lsig_push_new_offset = '1') then
lsig_push_strt_offset_reg <= sig_curr_strt_offset_reg;
lsig_pushreg_full <= '1';
lsig_pushreg_empty <= '0';
elsif (lsig_pull_new_offset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PUSH_STRT_OFFSET_REG;
-- Pull the next offset (if one exists) into the pull register
-- when the DRE outputs a TLAST. If the pull register is empty
-- and the push register has an offset, then push the new value
-- into the pull register.
lsig_pull_new_offset <= (sig_dre2wdc_tlast and
sig_dre2wdc_tvalid and
sig_wdc2dre_tready) or
(lsig_pushreg_full and
lsig_pullreg_empty);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PULL_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the output register for holding the starting
-- address offset sent to the Store and Forward modul's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_PULL_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '1') then
lsig_pull_strt_offset_reg <= lsig_push_strt_offset_reg;
lsig_pullreg_full <= '1';
lsig_pullreg_empty <= '0';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '0') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PULL_STRT_OFFSET_REG;
end generate GEN_INCLUDE_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_DRE
--
-- If Generate Description:
-- Omits the DRE from the Re-aligner.
--
--
------------------------------------------------------------
GEN_OMIT_DRE : if (OMIT_DRE) generate
begin
-- DRE always ready
sig_dre_align_ready <= '1';
-- -- Let the Scatter engine control the Realigner command
-- -- flow.
-- sig_dre_align_ready <= sig_scatter2drc_cmd_ready;
-- Pass through signal connections
sig_dre2wdc_tstrb <= sig_scatter2dre_tstrb ;
sig_dre2wdc_tdata <= sig_scatter2dre_tdata ;
sig_dre2wdc_tlast <= sig_scatter2dre_tlast ;
sig_dre2wdc_tvalid <= sig_scatter2dre_tvalid ;
sig_dre2scatter_tready <= sig_wdc2dre_tready ;
dre2wdc_eop <= sig_scatter2drc_eop ;
-- Just pass TLAST Error through when no DRE is present
sig_tlast_err0r <= sig_scatter2all_tlast_error;
-------------------------------------------------------------------------
-------- Store and Forward Start Address Offset Register Logic
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= sig_output_strt_offset_reg;
sig_ld_strt_offset <= sig_sm_ld_dre_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STRT_OFFSET_OUTPUT
--
-- Process Description:
-- Implements the register for holding the starting address
-- offset sent to the S2MM Store and Forward module's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_STRT_OFFSET_OUTPUT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_output_strt_offset_reg <= (others => '0');
elsif (sig_ld_strt_offset = '1') then
sig_output_strt_offset_reg <= sig_curr_strt_offset_reg;
else
null; -- Hold Current State
end if;
end if;
end process IMP_STRT_OFFSET_OUTPUT;
end generate GEN_OMIT_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_SCATTER
--
-- If Generate Description:
-- This IfGen implements the Scatter function which is a pre-
-- processor for the S2MM DRE. The scatter function breaks up
-- a continous input stream of data into constituant parts
-- as described by a set of loaded commands that together
-- describe an entire input packet.
--
------------------------------------------------------------
GEN_INCLUDE_SCATTER : if (C_SUPPORT_SCATTER = 1) generate
begin
-- Load the Scatter Engine command when the DRE command
-- is loaded
-- sig_drc2scatter_push_cmd <= sig_dre_align_ready and
-- sig_gated_dre_align_valid;
sig_drc2scatter_push_cmd <= sig_sm_ld_scatter_cmd ;
-- Assign the new Bytes to Transfer (BTT) qualifier for the
-- Scatter Engine
sig_drc2scatter_btt <= sig_curr_btt_reg;
-- Assign the new End of Frame (EOF) qualifier for the
-- Scatter Engine
sig_drc2scatter_eof <= sig_curr_eof_reg;
------------------------------------------------------------
-- Instance: I_S2MM_SCATTER
--
-- Description:
-- Instance for the Scatter Engine. This block breaks up a
-- input stream per commands loaded.
--
------------------------------------------------------------
I_S2MM_SCATTER : entity axi_datamover_v5_1.axi_datamover_s2mm_scatter
generic map (
C_ENABLE_INDET_BTT => C_ENABLE_INDET_BTT ,
C_DRE_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_BTT_USED => BTT_WIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock input & Reset input
primary_aclk => primary_aclk ,
mmap_reset => mmap_reset ,
-- DRE Realign Controller I/O ----------------------------
scatter2drc_cmd_ready => sig_scatter2drc_cmd_ready ,
drc2scatter_push_cmd => sig_drc2scatter_push_cmd ,
drc2scatter_btt => sig_drc2scatter_btt ,
drc2scatter_eof => sig_drc2scatter_eof ,
-- DRE Source Alignment -----------------------------------
scatter2drc_src_align => sig_scatter2dre_src_align ,
-- AXI Slave Stream In -----------------------------------
s2mm_strm_tready => sig_scatter2strm_tready ,
s2mm_strm_tvalid => sig_strm2scatter_tvalid ,
s2mm_strm_tdata => sig_strm2scatter_tdata ,
s2mm_strm_tstrb => sig_strm2scatter_tstrb ,
s2mm_strm_tlast => sig_strm2scatter_tlast ,
-- Stream Out to S2MM DRE ---------------------------------
drc2scatter_tready => sig_dre2scatter_tready ,
scatter2drc_tvalid => sig_scatter2dre_tvalid ,
scatter2drc_tdata => sig_scatter2dre_tdata ,
scatter2drc_tstrb => sig_scatter2dre_tstrb ,
scatter2drc_tlast => sig_scatter2dre_tlast ,
scatter2drc_flush => sig_scatter2dre_flush ,
scatter2drc_eop => sig_scatter2drc_eop ,
-- Premature TLAST assertion error flag
scatter2drc_tlast_error => sig_scatter2all_tlast_error
);
end generate GEN_INCLUDE_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_SCATTER
--
-- If Generate Description:
-- This IfGen omits the Scatter pre-processor.
--
--
------------------------------------------------------------
GEN_OMIT_SCATTER : if (C_SUPPORT_SCATTER = 0) generate
begin
-- Just housekeep the signaling
sig_scatter2drc_cmd_ready <= '1' ;
sig_scatter2drc_eop <= sig_strm2scatter_tlast ;
sig_scatter2dre_src_align <= sig_dre_src_align ;
sig_scatter2all_tlast_error <= '0' ;
sig_scatter2dre_flush <= sig_dre_flush ;
sig_scatter2dre_tstrb <= sig_strm2scatter_tstrb ;
sig_scatter2dre_tdata <= sig_strm2scatter_tdata ;
sig_scatter2dre_tlast <= sig_strm2scatter_tlast ;
sig_scatter2dre_tvalid <= sig_strm2scatter_tvalid ;
sig_scatter2strm_tready <= sig_dre2scatter_tready ;
end generate GEN_OMIT_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omit and special logic for Indeterminate BTT support.
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_need_cmd_flush <= '0' ; -- not needed without Indeterminate BTT
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Include logic for the case when Indeterminate BTT is
-- included as part of the S2MM. In this mode, the actual
-- length of input stream packets is not known when the S2MM
-- is loaded with a transfer command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
signal lsig_clr_cmd_flush : std_logic := '0';
signal lsig_set_cmd_flush : std_logic := '0';
signal lsig_cmd_set_fetch_pause : std_logic := '0';
signal lsig_cmd_clr_fetch_pause : std_logic := '0';
signal lsig_cmd_fetch_pause : std_logic := '0';
begin
lsig_cmd_set_fetch_pause <= sig_drc2scatter_push_cmd and
not(sig_curr_cmd_cmplt_reg) and
not(sig_need_cmd_flush);
lsig_cmd_clr_fetch_pause <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2dre_tlast;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FETCH_PAUSE
--
-- Process Description:
-- Implements the flop for the flag that causes the command
-- queue manager to pause fetching the next command if the
-- current command does not have the command complete bit set.
-- The pause remains set until the associated TLAST for the
-- command is output from the Scatter Engine. If the Tlast is
-- also accompanied by a EOP and the pause is set, then the
-- ensuing command (which will have the cmd cmplt bit set) must
-- be flushed from the queue and not loaded into the Scatter
-- Engine or DRE, This is normally associated with indeterminate
-- packets that are actually shorter than the intial align to
-- max burst child command sent to the Realigner, The next loaded
-- child command is to finish the remainder of the indeterminate
-- packet up to the full BTT value in the original parent command.
-- This child command becomes stranded in the Realigner command fifo
-- and has to be flushed.
--
-------------------------------------------------------------
IMP_CMD_FETCH_PAUSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_cmd_clr_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '0';
elsif (lsig_cmd_set_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FETCH_PAUSE;
-- Clear the flush needed flag when the command with the command
-- complete marker is popped off of the command queue.
lsig_clr_cmd_flush <= sig_need_cmd_flush and
sig_sm_pop_cmd_fifo;
-- The command queue has to be flushed if the stream EOP marker
-- is transfered out of the Scatter Engine when the corresponding
-- command being executed does not have the command complete
-- marker set.
lsig_set_cmd_flush <= lsig_cmd_fetch_pause and
sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2drc_eop;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLUSH_FLOP
--
-- Process Description:
-- Implements the flop for holding the command flush flag.
-- This is only needed in Indeterminate BTT mode.
--
-------------------------------------------------------------
IMP_CMD_FLUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_cmd_flush = '1') then
sig_need_cmd_flush <= '0';
elsif (lsig_set_cmd_flush = '1') then
sig_need_cmd_flush <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FLUSH_FLOP;
end generate GEN_ENABLE_INDET_BTT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- including negligence, or under any other theory of
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-- related to, arising under or in connection with these
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-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_realign.vhd
--
-- Description:
-- This file implements the S2MM Data Realignment module. THe S2MM direction is
-- more complex than the MM2S direction since the DRE needs to be upstream from
-- the Write Data Controller. This requires the S2MM DRE to be running 2 to
-- 3 clocks ahead of the Write Data controller to minimize/eliminate xfer
-- bubble insertion.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_fifo;
use axi_datamover_v5_1.axi_datamover_s2mm_dre;
use axi_datamover_v5_1.axi_datamover_s2mm_scatter;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_realign is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the IBTT Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_INCLUDE_DRE : Integer range 0 to 1 := 1;
-- Includes/Omits the S2MM DRE
-- 0 = Omit
-- 1 = Include
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal command queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_SUPPORT_SCATTER : Integer range 0 to 1 := 1;
-- Includes/Omits the Scatter functionality
-- 0 = omit
-- 1 = include
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_BTT_USED : Integer range 8 to 23 := 16;
-- Indicates the width of the input command BTT that is actually
-- used
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Input and Output Stream Data ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the input command Tag port
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 ;
-- Sets the width of the Store and Forward Start offset ports
C_FAMILY : String := "virtex7"
-- specifies the target FPGA familiy
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------------
-- Write Data Controller or IBTT Indeterminate BTT I/O -------------------------
--
wdc2dre_wready : In std_logic; --
-- Write READY input from WDC or SF --
--
dre2wdc_wvalid : Out std_logic; --
-- Write VALID output to WDC or SF --
--
dre2wdc_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wlast : Out std_logic; --
-- Write LAST output to WDC or SF --
--
dre2wdc_eop : Out std_logic; --
-- End of Packet indicator for the Stream input to WDC or SF --
--------------------------------------------------------------------------------
-- Starting offset output for the Store and Forward Modules -------------------
--
dre2sf_strt_offset : Out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Command Calculator Interface ---------------------------------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2dre_cmd_cmplt : In std_logic; --
-- The last tranfer command of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- Premature TLAST assertion error flag -----------------------------
--
dre2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the DRE detected --
-- a Early/Late TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------
-- DRE Halted Status ------------------------------------------------
--
dre2all_halted : Out std_logic --
-- When asserted, this indicates the DRE has satisfied --
-- all pending transfers queued by the command calculator --
-- and is halted. --
---------------------------------------------------------------------
);
end entity axi_datamover_s2mm_realign;
architecture implementation of axi_datamover_s2mm_realign is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations --------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_realign_fifo
--
-- Function Description:
-- Assures that the Realigner cmd fifo depth is at least 4 deep else it
-- is equal to the pipe depth.
--
-------------------------------------------------------------------
function funct_size_realign_fifo (pipe_depth : integer) return integer is
Variable temp_fifo_depth : Integer := 4;
begin
If (pipe_depth < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := pipe_depth;
End if;
Return (temp_fifo_depth);
end function funct_size_realign_fifo;
-- Constant Declarations --------------------------------------------
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant BTT_WIDTH : integer := C_BTT_USED;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant BTT_OF_ZERO : std_logic_vector(BTT_WIDTH-1 downto 0)
:= (others => '0');
Constant DRECTL_FIFO_DEPTH : integer := funct_size_realign_fifo(C_DRE_CNTL_FIFO_DEPTH);
Constant DRECTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
BTT_WIDTH + -- BTT field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant BTT_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := BTT_STRT_INDEX + BTT_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
Constant INCLUDE_DRE : boolean := (C_INCLUDE_DRE = 1 and
C_STREAM_DWIDTH <= 64 and
C_STREAM_DWIDTH >= 16);
Constant OMIT_DRE : boolean := not(INCLUDE_DRE);
-- Type Declarations --------------------------------------------
type TYPE_CMD_CNTL_SM is (
INIT,
LD_DRE_SCATTER_FIRST,
CHK_POP_FIRST ,
LD_DRE_SCATTER_SECOND,
CHK_POP_SECOND,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_cmdcntl_sm_state : TYPE_CMD_CNTL_SM := INIT;
Signal sig_cmdcntl_sm_state_ns : TYPE_CMD_CNTL_SM := INIT;
signal sig_sm_ld_dre_cmd_ns : std_logic := '0';
signal sig_sm_ld_dre_cmd : std_logic := '0';
signal sig_sm_ld_scatter_cmd_ns : std_logic := '0';
signal sig_sm_ld_scatter_cmd : std_logic := '0';
signal sig_sm_pop_cmd_fifo_ns : std_logic := '0';
signal sig_sm_pop_cmd_fifo : std_logic := '0';
signal sig_cmd_fifo_data_in : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_btt_reg : std_logic_vector(BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_cmd_cmplt_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_dre2wdc_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2wdc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_dre2wdc_tlast : std_logic := '0';
signal sig_dre2wdc_tvalid : std_logic := '0';
signal sig_wdc2dre_tready : std_logic := '0';
signal sig_tlast_err0r : std_logic := '0';
signal sig_dre_halted : std_logic := '0';
signal sig_strm2scatter_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_strm2scatter_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm2scatter_tlast : std_logic := '0';
signal sig_strm2scatter_tvalid : std_logic := '0';
signal sig_scatter2strm_tready : std_logic := '0';
signal sig_scatter2dre_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_scatter2dre_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2dre_tlast : std_logic := '0';
signal sig_scatter2dre_tvalid : std_logic := '0';
signal sig_dre2scatter_tready : std_logic := '0';
signal sig_scatter2dre_flush : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_scatter2dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_cmd_ready : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic;
signal sig_drc2scatter_btt : std_logic_vector(BTT_WIDTH-1 downto 0);
signal sig_drc2scatter_eof : std_logic;
signal sig_scatter2all_tlast_error : std_logic := '0';
signal sig_need_cmd_flush : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_strt_offset : std_logic := '0';
signal sig_output_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2sf_strt_offset : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Port connections
-- Input Stream Attachment
s2mm_strm_wready <= sig_scatter2strm_tready ;
sig_strm2scatter_tvalid <= s2mm_strm_wvalid ;
sig_strm2scatter_tdata <= s2mm_strm_wdata ;
sig_strm2scatter_tstrb <= s2mm_strm_wstrb ;
sig_strm2scatter_tlast <= s2mm_strm_wlast ;
-- Write Data Controller Stream Attachment
sig_wdc2dre_tready <= wdc2dre_wready ;
dre2wdc_wvalid <= sig_dre2wdc_tvalid ;
dre2wdc_wdata <= sig_dre2wdc_tdata ;
dre2wdc_wstrb <= sig_dre2wdc_tstrb ;
dre2wdc_wlast <= sig_dre2wdc_tlast ;
-- Status/Error flags
dre2all_tlast_error <= sig_tlast_err0r ;
dre2all_halted <= sig_dre_halted ;
-- Store and Forward Starting Offset Output
dre2sf_strt_offset <= sig_dre2sf_strt_offset ;
-------------------------------------------------------------
-- Internal logic
sig_dre_halted <= sig_dre_align_ready;
-------------------------------------------------------------
-- DRE Handshake signals
sig_dre_src_align <= sig_curr_src_align_reg ;
sig_dre_dest_align <= sig_curr_dest_align_reg;
sig_dre_use_autodest <= '0'; -- not used
sig_dre_flush <= '0'; -- not used
-------------------------------------------------------------------------
-------- Realigner Command FIFO and controls
-------------------------------------------------------------------------
-- Command Calculator Handshake
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_cmd_cmplt &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_btt &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto DEST_ALIGN_STRT_INDEX);
sig_curr_btt_reg <= sig_cmd_fifo_data_out((BTT_STRT_INDEX+BTT_WIDTH)-1 downto BTT_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_cmd_cmplt_reg <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => DRECTL_FIFO_WIDTH ,
C_DEPTH => DRECTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_sm_pop_cmd_fifo ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-------- DRE and Scatter Command Loader State Machine
-------------------------------------------------------------------------
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CMDCNTL_SM_COMBINATIONAL
--
-- Process Description:
-- Command Controller State Machine combinational implementation
-- The design is based on the premise that for every parent
-- command loaded into the S2MM, the Realigner can be loaded with
-- 1 or 2 commands spawned from it. The first command is used to
-- align ensuing transfers (in MMap space) to a max burst address
-- boundary. Then, if the parent command's BTT value is not satisfied
-- after the first command completes, a second command is generated
-- and loaded in the Realigner for the remaining BTT value. The
-- command complete bit in the Realigner command indicates if the
-- first command the final command or the second command (if needed)
-- is the final command,
-------------------------------------------------------------
CMDCNTL_SM_COMBINATIONAL : process (sig_cmdcntl_sm_state ,
sig_fifo_rd_cmd_valid ,
sig_dre_align_ready ,
sig_scatter2drc_cmd_ready ,
sig_need_cmd_flush ,
sig_curr_cmd_cmplt_reg ,
sig_curr_calc_error_reg
)
begin
-- SM Defaults
sig_cmdcntl_sm_state_ns <= INIT;
sig_sm_ld_dre_cmd_ns <= '0';
sig_sm_ld_scatter_cmd_ns <= '0';
sig_sm_pop_cmd_fifo_ns <= '0';
case sig_cmdcntl_sm_state is
--------------------------------------------
when INIT =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
--------------------------------------------
when LD_DRE_SCATTER_FIRST =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
End if;
--------------------------------------------
when CHK_POP_FIRST =>
If (sig_curr_cmd_cmplt_reg = '1') Then
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
Else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when LD_DRE_SCATTER_SECOND =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_need_cmd_flush = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_SECOND ;
sig_sm_pop_cmd_fifo_ns <= '1';
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when CHK_POP_SECOND =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST ;
--------------------------------------------
when ERROR_TRAP =>
sig_cmdcntl_sm_state_ns <= ERROR_TRAP ;
--------------------------------------------
when others =>
sig_cmdcntl_sm_state_ns <= INIT;
end case;
end process CMDCNTL_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMDCNTL_SM_REGISTERED
--
-- Process Description:
-- Command Controller State Machine registered implementation
--
-------------------------------------------------------------
CMDCNTL_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_cmdcntl_sm_state <= INIT;
sig_sm_ld_dre_cmd <= '0' ;
sig_sm_ld_scatter_cmd <= '0' ;
sig_sm_pop_cmd_fifo <= '0' ;
else
sig_cmdcntl_sm_state <= sig_cmdcntl_sm_state_ns ;
sig_sm_ld_dre_cmd <= sig_sm_ld_dre_cmd_ns ;
sig_sm_ld_scatter_cmd <= sig_sm_ld_scatter_cmd_ns ;
sig_sm_pop_cmd_fifo <= sig_sm_pop_cmd_fifo_ns ;
end if;
end if;
end process CMDCNTL_SM_REGISTERED;
-------------------------------------------------------------------------
-------- DRE Instance and controls
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE
--
-- If Generate Description:
-- Includes the instance for the DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE : if (INCLUDE_DRE) generate
signal lsig_eop_reg : std_logic := '0';
signal lsig_dre_load_beat : std_logic := '0';
signal lsig_dre_tlast_output_beat : std_logic := '0';
signal lsig_set_eop : std_logic := '0';
signal lsig_tlast_err_reg1 : std_logic := '0';
signal lsig_tlast_err_reg2 : std_logic := '0';
signal lsig_push_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pushreg_full : std_logic := '0';
signal lsig_pushreg_empty : std_logic := '0';
signal lsig_pull_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pullreg_full : std_logic := '0';
signal lsig_pullreg_empty : std_logic := '0';
signal lsig_pull_new_offset : std_logic := '0';
signal lsig_push_new_offset : std_logic := '0';
begin
------------------------------------------------------------
-- Instance: I_S2MM_DRE_BLOCK
--
-- Description:
-- Instance for the S2MM Data Realignment Engine (DRE)
--
------------------------------------------------------------
I_S2MM_DRE_BLOCK : entity axi_datamover_v5_1.axi_datamover_s2mm_dre
generic map (
C_DWIDTH => C_STREAM_DWIDTH ,
C_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH
)
port map (
-- Clock and Reset
dre_clk => primary_aclk ,
dre_rst => mmap_reset ,
-- Alignment Control (Independent from Stream Input timing)
dre_align_ready => sig_dre_align_ready ,
dre_align_valid => sig_sm_ld_dre_cmd ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_scatter2dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
-- Flush Control (Aligned to input Stream timing)
dre_flush => sig_scatter2dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_scatter2dre_tstrb ,
dre_in_tdata => sig_scatter2dre_tdata ,
dre_in_tlast => sig_scatter2dre_tlast ,
dre_in_tvalid => sig_scatter2dre_tvalid ,
dre_in_tready => sig_dre2scatter_tready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2wdc_tstrb ,
dre_out_tdata => sig_dre2wdc_tdata ,
dre_out_tlast => sig_dre2wdc_tlast ,
dre_out_tvalid => sig_dre2wdc_tvalid ,
dre_out_tready => sig_wdc2dre_tready
);
lsig_dre_load_beat <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready;
lsig_set_eop <= sig_scatter2drc_eop and
lsig_dre_load_beat ;
lsig_dre_tlast_output_beat <= sig_dre2wdc_tvalid and
sig_wdc2dre_tready and
sig_dre2wdc_tlast;
dre2wdc_eop <= lsig_dre_tlast_output_beat and
lsig_eop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG
--
-- Process Description:
-- Implements a flop for holding the EOP from the Scatter
-- Engine until the corresponding packet clears out of the DRE.
-- THis is used to transfer the EOP marker to the DRE output
-- stream without the need for the DRE to pass it through.
--
-------------------------------------------------------------
IMP_EOP_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(lsig_dre_tlast_output_beat = '1' and
lsig_set_eop = '0')) then
lsig_eop_reg <= '0';
elsif (lsig_set_eop = '1') then
lsig_eop_reg <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_EOP_REG;
-- Delay TLAST Error by 2 clocks to compensate for DRE minimum
-- delay of 2 clocks for the stream data.
sig_tlast_err0r <= lsig_tlast_err_reg2;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_DELAY
--
-- Process Description:
-- Implements a 2 clock delay to better align the TLAST
-- error detection with the Stream output data to the WDC
-- which has a minimum 2 clock delay through the DRE.
--
-------------------------------------------------------------
IMP_TLAST_ERR_DELAY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_tlast_err_reg1 <= '0';
lsig_tlast_err_reg2 <= '0';
else
lsig_tlast_err_reg1 <= sig_scatter2all_tlast_error;
lsig_tlast_err_reg2 <= lsig_tlast_err_reg1;
end if;
end if;
end process IMP_TLAST_ERR_DELAY;
-------------------------------------------------------------------------
-- Store and Forward Start Address Offset Registers Logic
-- Push-pull register is used to to time align the starting address
-- offset (ripped from the Realigner command via parsing) to DRE
-- TLAST output timing. The offset output of the pull register must
-- be valid on the first output databeat of the DRE to the Store and
-- Forward module.
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= lsig_pull_strt_offset_reg;
-- lsig_push_new_offset <= sig_dre_align_ready and
-- sig_gated_dre_align_valid ;
lsig_push_new_offset <= sig_sm_ld_dre_cmd ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the input register for holding the starting address
-- offset sent to the external Store and Forward functions.
--
-------------------------------------------------------------
IMP_PUSH_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
elsif (lsig_push_new_offset = '1') then
lsig_push_strt_offset_reg <= sig_curr_strt_offset_reg;
lsig_pushreg_full <= '1';
lsig_pushreg_empty <= '0';
elsif (lsig_pull_new_offset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PUSH_STRT_OFFSET_REG;
-- Pull the next offset (if one exists) into the pull register
-- when the DRE outputs a TLAST. If the pull register is empty
-- and the push register has an offset, then push the new value
-- into the pull register.
lsig_pull_new_offset <= (sig_dre2wdc_tlast and
sig_dre2wdc_tvalid and
sig_wdc2dre_tready) or
(lsig_pushreg_full and
lsig_pullreg_empty);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PULL_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the output register for holding the starting
-- address offset sent to the Store and Forward modul's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_PULL_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '1') then
lsig_pull_strt_offset_reg <= lsig_push_strt_offset_reg;
lsig_pullreg_full <= '1';
lsig_pullreg_empty <= '0';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '0') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PULL_STRT_OFFSET_REG;
end generate GEN_INCLUDE_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_DRE
--
-- If Generate Description:
-- Omits the DRE from the Re-aligner.
--
--
------------------------------------------------------------
GEN_OMIT_DRE : if (OMIT_DRE) generate
begin
-- DRE always ready
sig_dre_align_ready <= '1';
-- -- Let the Scatter engine control the Realigner command
-- -- flow.
-- sig_dre_align_ready <= sig_scatter2drc_cmd_ready;
-- Pass through signal connections
sig_dre2wdc_tstrb <= sig_scatter2dre_tstrb ;
sig_dre2wdc_tdata <= sig_scatter2dre_tdata ;
sig_dre2wdc_tlast <= sig_scatter2dre_tlast ;
sig_dre2wdc_tvalid <= sig_scatter2dre_tvalid ;
sig_dre2scatter_tready <= sig_wdc2dre_tready ;
dre2wdc_eop <= sig_scatter2drc_eop ;
-- Just pass TLAST Error through when no DRE is present
sig_tlast_err0r <= sig_scatter2all_tlast_error;
-------------------------------------------------------------------------
-------- Store and Forward Start Address Offset Register Logic
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= sig_output_strt_offset_reg;
sig_ld_strt_offset <= sig_sm_ld_dre_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STRT_OFFSET_OUTPUT
--
-- Process Description:
-- Implements the register for holding the starting address
-- offset sent to the S2MM Store and Forward module's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_STRT_OFFSET_OUTPUT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_output_strt_offset_reg <= (others => '0');
elsif (sig_ld_strt_offset = '1') then
sig_output_strt_offset_reg <= sig_curr_strt_offset_reg;
else
null; -- Hold Current State
end if;
end if;
end process IMP_STRT_OFFSET_OUTPUT;
end generate GEN_OMIT_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_SCATTER
--
-- If Generate Description:
-- This IfGen implements the Scatter function which is a pre-
-- processor for the S2MM DRE. The scatter function breaks up
-- a continous input stream of data into constituant parts
-- as described by a set of loaded commands that together
-- describe an entire input packet.
--
------------------------------------------------------------
GEN_INCLUDE_SCATTER : if (C_SUPPORT_SCATTER = 1) generate
begin
-- Load the Scatter Engine command when the DRE command
-- is loaded
-- sig_drc2scatter_push_cmd <= sig_dre_align_ready and
-- sig_gated_dre_align_valid;
sig_drc2scatter_push_cmd <= sig_sm_ld_scatter_cmd ;
-- Assign the new Bytes to Transfer (BTT) qualifier for the
-- Scatter Engine
sig_drc2scatter_btt <= sig_curr_btt_reg;
-- Assign the new End of Frame (EOF) qualifier for the
-- Scatter Engine
sig_drc2scatter_eof <= sig_curr_eof_reg;
------------------------------------------------------------
-- Instance: I_S2MM_SCATTER
--
-- Description:
-- Instance for the Scatter Engine. This block breaks up a
-- input stream per commands loaded.
--
------------------------------------------------------------
I_S2MM_SCATTER : entity axi_datamover_v5_1.axi_datamover_s2mm_scatter
generic map (
C_ENABLE_INDET_BTT => C_ENABLE_INDET_BTT ,
C_DRE_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_BTT_USED => BTT_WIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock input & Reset input
primary_aclk => primary_aclk ,
mmap_reset => mmap_reset ,
-- DRE Realign Controller I/O ----------------------------
scatter2drc_cmd_ready => sig_scatter2drc_cmd_ready ,
drc2scatter_push_cmd => sig_drc2scatter_push_cmd ,
drc2scatter_btt => sig_drc2scatter_btt ,
drc2scatter_eof => sig_drc2scatter_eof ,
-- DRE Source Alignment -----------------------------------
scatter2drc_src_align => sig_scatter2dre_src_align ,
-- AXI Slave Stream In -----------------------------------
s2mm_strm_tready => sig_scatter2strm_tready ,
s2mm_strm_tvalid => sig_strm2scatter_tvalid ,
s2mm_strm_tdata => sig_strm2scatter_tdata ,
s2mm_strm_tstrb => sig_strm2scatter_tstrb ,
s2mm_strm_tlast => sig_strm2scatter_tlast ,
-- Stream Out to S2MM DRE ---------------------------------
drc2scatter_tready => sig_dre2scatter_tready ,
scatter2drc_tvalid => sig_scatter2dre_tvalid ,
scatter2drc_tdata => sig_scatter2dre_tdata ,
scatter2drc_tstrb => sig_scatter2dre_tstrb ,
scatter2drc_tlast => sig_scatter2dre_tlast ,
scatter2drc_flush => sig_scatter2dre_flush ,
scatter2drc_eop => sig_scatter2drc_eop ,
-- Premature TLAST assertion error flag
scatter2drc_tlast_error => sig_scatter2all_tlast_error
);
end generate GEN_INCLUDE_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_SCATTER
--
-- If Generate Description:
-- This IfGen omits the Scatter pre-processor.
--
--
------------------------------------------------------------
GEN_OMIT_SCATTER : if (C_SUPPORT_SCATTER = 0) generate
begin
-- Just housekeep the signaling
sig_scatter2drc_cmd_ready <= '1' ;
sig_scatter2drc_eop <= sig_strm2scatter_tlast ;
sig_scatter2dre_src_align <= sig_dre_src_align ;
sig_scatter2all_tlast_error <= '0' ;
sig_scatter2dre_flush <= sig_dre_flush ;
sig_scatter2dre_tstrb <= sig_strm2scatter_tstrb ;
sig_scatter2dre_tdata <= sig_strm2scatter_tdata ;
sig_scatter2dre_tlast <= sig_strm2scatter_tlast ;
sig_scatter2dre_tvalid <= sig_strm2scatter_tvalid ;
sig_scatter2strm_tready <= sig_dre2scatter_tready ;
end generate GEN_OMIT_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omit and special logic for Indeterminate BTT support.
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_need_cmd_flush <= '0' ; -- not needed without Indeterminate BTT
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Include logic for the case when Indeterminate BTT is
-- included as part of the S2MM. In this mode, the actual
-- length of input stream packets is not known when the S2MM
-- is loaded with a transfer command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
signal lsig_clr_cmd_flush : std_logic := '0';
signal lsig_set_cmd_flush : std_logic := '0';
signal lsig_cmd_set_fetch_pause : std_logic := '0';
signal lsig_cmd_clr_fetch_pause : std_logic := '0';
signal lsig_cmd_fetch_pause : std_logic := '0';
begin
lsig_cmd_set_fetch_pause <= sig_drc2scatter_push_cmd and
not(sig_curr_cmd_cmplt_reg) and
not(sig_need_cmd_flush);
lsig_cmd_clr_fetch_pause <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2dre_tlast;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FETCH_PAUSE
--
-- Process Description:
-- Implements the flop for the flag that causes the command
-- queue manager to pause fetching the next command if the
-- current command does not have the command complete bit set.
-- The pause remains set until the associated TLAST for the
-- command is output from the Scatter Engine. If the Tlast is
-- also accompanied by a EOP and the pause is set, then the
-- ensuing command (which will have the cmd cmplt bit set) must
-- be flushed from the queue and not loaded into the Scatter
-- Engine or DRE, This is normally associated with indeterminate
-- packets that are actually shorter than the intial align to
-- max burst child command sent to the Realigner, The next loaded
-- child command is to finish the remainder of the indeterminate
-- packet up to the full BTT value in the original parent command.
-- This child command becomes stranded in the Realigner command fifo
-- and has to be flushed.
--
-------------------------------------------------------------
IMP_CMD_FETCH_PAUSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_cmd_clr_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '0';
elsif (lsig_cmd_set_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FETCH_PAUSE;
-- Clear the flush needed flag when the command with the command
-- complete marker is popped off of the command queue.
lsig_clr_cmd_flush <= sig_need_cmd_flush and
sig_sm_pop_cmd_fifo;
-- The command queue has to be flushed if the stream EOP marker
-- is transfered out of the Scatter Engine when the corresponding
-- command being executed does not have the command complete
-- marker set.
lsig_set_cmd_flush <= lsig_cmd_fetch_pause and
sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2drc_eop;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLUSH_FLOP
--
-- Process Description:
-- Implements the flop for holding the command flush flag.
-- This is only needed in Indeterminate BTT mode.
--
-------------------------------------------------------------
IMP_CMD_FLUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_cmd_flush = '1') then
sig_need_cmd_flush <= '0';
elsif (lsig_set_cmd_flush = '1') then
sig_need_cmd_flush <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FLUSH_FLOP;
end generate GEN_ENABLE_INDET_BTT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_realign.vhd
--
-- Description:
-- This file implements the S2MM Data Realignment module. THe S2MM direction is
-- more complex than the MM2S direction since the DRE needs to be upstream from
-- the Write Data Controller. This requires the S2MM DRE to be running 2 to
-- 3 clocks ahead of the Write Data controller to minimize/eliminate xfer
-- bubble insertion.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_fifo;
use axi_datamover_v5_1.axi_datamover_s2mm_dre;
use axi_datamover_v5_1.axi_datamover_s2mm_scatter;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_realign is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the IBTT Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_INCLUDE_DRE : Integer range 0 to 1 := 1;
-- Includes/Omits the S2MM DRE
-- 0 = Omit
-- 1 = Include
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal command queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_SUPPORT_SCATTER : Integer range 0 to 1 := 1;
-- Includes/Omits the Scatter functionality
-- 0 = omit
-- 1 = include
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_BTT_USED : Integer range 8 to 23 := 16;
-- Indicates the width of the input command BTT that is actually
-- used
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Input and Output Stream Data ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the input command Tag port
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 ;
-- Sets the width of the Store and Forward Start offset ports
C_FAMILY : String := "virtex7"
-- specifies the target FPGA familiy
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------------
-- Write Data Controller or IBTT Indeterminate BTT I/O -------------------------
--
wdc2dre_wready : In std_logic; --
-- Write READY input from WDC or SF --
--
dre2wdc_wvalid : Out std_logic; --
-- Write VALID output to WDC or SF --
--
dre2wdc_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wlast : Out std_logic; --
-- Write LAST output to WDC or SF --
--
dre2wdc_eop : Out std_logic; --
-- End of Packet indicator for the Stream input to WDC or SF --
--------------------------------------------------------------------------------
-- Starting offset output for the Store and Forward Modules -------------------
--
dre2sf_strt_offset : Out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Command Calculator Interface ---------------------------------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2dre_cmd_cmplt : In std_logic; --
-- The last tranfer command of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- Premature TLAST assertion error flag -----------------------------
--
dre2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the DRE detected --
-- a Early/Late TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------
-- DRE Halted Status ------------------------------------------------
--
dre2all_halted : Out std_logic --
-- When asserted, this indicates the DRE has satisfied --
-- all pending transfers queued by the command calculator --
-- and is halted. --
---------------------------------------------------------------------
);
end entity axi_datamover_s2mm_realign;
architecture implementation of axi_datamover_s2mm_realign is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations --------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_realign_fifo
--
-- Function Description:
-- Assures that the Realigner cmd fifo depth is at least 4 deep else it
-- is equal to the pipe depth.
--
-------------------------------------------------------------------
function funct_size_realign_fifo (pipe_depth : integer) return integer is
Variable temp_fifo_depth : Integer := 4;
begin
If (pipe_depth < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := pipe_depth;
End if;
Return (temp_fifo_depth);
end function funct_size_realign_fifo;
-- Constant Declarations --------------------------------------------
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant BTT_WIDTH : integer := C_BTT_USED;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant BTT_OF_ZERO : std_logic_vector(BTT_WIDTH-1 downto 0)
:= (others => '0');
Constant DRECTL_FIFO_DEPTH : integer := funct_size_realign_fifo(C_DRE_CNTL_FIFO_DEPTH);
Constant DRECTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
BTT_WIDTH + -- BTT field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant BTT_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := BTT_STRT_INDEX + BTT_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
Constant INCLUDE_DRE : boolean := (C_INCLUDE_DRE = 1 and
C_STREAM_DWIDTH <= 64 and
C_STREAM_DWIDTH >= 16);
Constant OMIT_DRE : boolean := not(INCLUDE_DRE);
-- Type Declarations --------------------------------------------
type TYPE_CMD_CNTL_SM is (
INIT,
LD_DRE_SCATTER_FIRST,
CHK_POP_FIRST ,
LD_DRE_SCATTER_SECOND,
CHK_POP_SECOND,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_cmdcntl_sm_state : TYPE_CMD_CNTL_SM := INIT;
Signal sig_cmdcntl_sm_state_ns : TYPE_CMD_CNTL_SM := INIT;
signal sig_sm_ld_dre_cmd_ns : std_logic := '0';
signal sig_sm_ld_dre_cmd : std_logic := '0';
signal sig_sm_ld_scatter_cmd_ns : std_logic := '0';
signal sig_sm_ld_scatter_cmd : std_logic := '0';
signal sig_sm_pop_cmd_fifo_ns : std_logic := '0';
signal sig_sm_pop_cmd_fifo : std_logic := '0';
signal sig_cmd_fifo_data_in : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_btt_reg : std_logic_vector(BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_cmd_cmplt_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_dre2wdc_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2wdc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_dre2wdc_tlast : std_logic := '0';
signal sig_dre2wdc_tvalid : std_logic := '0';
signal sig_wdc2dre_tready : std_logic := '0';
signal sig_tlast_err0r : std_logic := '0';
signal sig_dre_halted : std_logic := '0';
signal sig_strm2scatter_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_strm2scatter_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm2scatter_tlast : std_logic := '0';
signal sig_strm2scatter_tvalid : std_logic := '0';
signal sig_scatter2strm_tready : std_logic := '0';
signal sig_scatter2dre_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_scatter2dre_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2dre_tlast : std_logic := '0';
signal sig_scatter2dre_tvalid : std_logic := '0';
signal sig_dre2scatter_tready : std_logic := '0';
signal sig_scatter2dre_flush : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_scatter2dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_cmd_ready : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic;
signal sig_drc2scatter_btt : std_logic_vector(BTT_WIDTH-1 downto 0);
signal sig_drc2scatter_eof : std_logic;
signal sig_scatter2all_tlast_error : std_logic := '0';
signal sig_need_cmd_flush : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_strt_offset : std_logic := '0';
signal sig_output_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2sf_strt_offset : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Port connections
-- Input Stream Attachment
s2mm_strm_wready <= sig_scatter2strm_tready ;
sig_strm2scatter_tvalid <= s2mm_strm_wvalid ;
sig_strm2scatter_tdata <= s2mm_strm_wdata ;
sig_strm2scatter_tstrb <= s2mm_strm_wstrb ;
sig_strm2scatter_tlast <= s2mm_strm_wlast ;
-- Write Data Controller Stream Attachment
sig_wdc2dre_tready <= wdc2dre_wready ;
dre2wdc_wvalid <= sig_dre2wdc_tvalid ;
dre2wdc_wdata <= sig_dre2wdc_tdata ;
dre2wdc_wstrb <= sig_dre2wdc_tstrb ;
dre2wdc_wlast <= sig_dre2wdc_tlast ;
-- Status/Error flags
dre2all_tlast_error <= sig_tlast_err0r ;
dre2all_halted <= sig_dre_halted ;
-- Store and Forward Starting Offset Output
dre2sf_strt_offset <= sig_dre2sf_strt_offset ;
-------------------------------------------------------------
-- Internal logic
sig_dre_halted <= sig_dre_align_ready;
-------------------------------------------------------------
-- DRE Handshake signals
sig_dre_src_align <= sig_curr_src_align_reg ;
sig_dre_dest_align <= sig_curr_dest_align_reg;
sig_dre_use_autodest <= '0'; -- not used
sig_dre_flush <= '0'; -- not used
-------------------------------------------------------------------------
-------- Realigner Command FIFO and controls
-------------------------------------------------------------------------
-- Command Calculator Handshake
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_cmd_cmplt &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_btt &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto DEST_ALIGN_STRT_INDEX);
sig_curr_btt_reg <= sig_cmd_fifo_data_out((BTT_STRT_INDEX+BTT_WIDTH)-1 downto BTT_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_cmd_cmplt_reg <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => DRECTL_FIFO_WIDTH ,
C_DEPTH => DRECTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_sm_pop_cmd_fifo ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-------- DRE and Scatter Command Loader State Machine
-------------------------------------------------------------------------
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CMDCNTL_SM_COMBINATIONAL
--
-- Process Description:
-- Command Controller State Machine combinational implementation
-- The design is based on the premise that for every parent
-- command loaded into the S2MM, the Realigner can be loaded with
-- 1 or 2 commands spawned from it. The first command is used to
-- align ensuing transfers (in MMap space) to a max burst address
-- boundary. Then, if the parent command's BTT value is not satisfied
-- after the first command completes, a second command is generated
-- and loaded in the Realigner for the remaining BTT value. The
-- command complete bit in the Realigner command indicates if the
-- first command the final command or the second command (if needed)
-- is the final command,
-------------------------------------------------------------
CMDCNTL_SM_COMBINATIONAL : process (sig_cmdcntl_sm_state ,
sig_fifo_rd_cmd_valid ,
sig_dre_align_ready ,
sig_scatter2drc_cmd_ready ,
sig_need_cmd_flush ,
sig_curr_cmd_cmplt_reg ,
sig_curr_calc_error_reg
)
begin
-- SM Defaults
sig_cmdcntl_sm_state_ns <= INIT;
sig_sm_ld_dre_cmd_ns <= '0';
sig_sm_ld_scatter_cmd_ns <= '0';
sig_sm_pop_cmd_fifo_ns <= '0';
case sig_cmdcntl_sm_state is
--------------------------------------------
when INIT =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
--------------------------------------------
when LD_DRE_SCATTER_FIRST =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
End if;
--------------------------------------------
when CHK_POP_FIRST =>
If (sig_curr_cmd_cmplt_reg = '1') Then
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
Else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when LD_DRE_SCATTER_SECOND =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_need_cmd_flush = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_SECOND ;
sig_sm_pop_cmd_fifo_ns <= '1';
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when CHK_POP_SECOND =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST ;
--------------------------------------------
when ERROR_TRAP =>
sig_cmdcntl_sm_state_ns <= ERROR_TRAP ;
--------------------------------------------
when others =>
sig_cmdcntl_sm_state_ns <= INIT;
end case;
end process CMDCNTL_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMDCNTL_SM_REGISTERED
--
-- Process Description:
-- Command Controller State Machine registered implementation
--
-------------------------------------------------------------
CMDCNTL_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_cmdcntl_sm_state <= INIT;
sig_sm_ld_dre_cmd <= '0' ;
sig_sm_ld_scatter_cmd <= '0' ;
sig_sm_pop_cmd_fifo <= '0' ;
else
sig_cmdcntl_sm_state <= sig_cmdcntl_sm_state_ns ;
sig_sm_ld_dre_cmd <= sig_sm_ld_dre_cmd_ns ;
sig_sm_ld_scatter_cmd <= sig_sm_ld_scatter_cmd_ns ;
sig_sm_pop_cmd_fifo <= sig_sm_pop_cmd_fifo_ns ;
end if;
end if;
end process CMDCNTL_SM_REGISTERED;
-------------------------------------------------------------------------
-------- DRE Instance and controls
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE
--
-- If Generate Description:
-- Includes the instance for the DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE : if (INCLUDE_DRE) generate
signal lsig_eop_reg : std_logic := '0';
signal lsig_dre_load_beat : std_logic := '0';
signal lsig_dre_tlast_output_beat : std_logic := '0';
signal lsig_set_eop : std_logic := '0';
signal lsig_tlast_err_reg1 : std_logic := '0';
signal lsig_tlast_err_reg2 : std_logic := '0';
signal lsig_push_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pushreg_full : std_logic := '0';
signal lsig_pushreg_empty : std_logic := '0';
signal lsig_pull_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pullreg_full : std_logic := '0';
signal lsig_pullreg_empty : std_logic := '0';
signal lsig_pull_new_offset : std_logic := '0';
signal lsig_push_new_offset : std_logic := '0';
begin
------------------------------------------------------------
-- Instance: I_S2MM_DRE_BLOCK
--
-- Description:
-- Instance for the S2MM Data Realignment Engine (DRE)
--
------------------------------------------------------------
I_S2MM_DRE_BLOCK : entity axi_datamover_v5_1.axi_datamover_s2mm_dre
generic map (
C_DWIDTH => C_STREAM_DWIDTH ,
C_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH
)
port map (
-- Clock and Reset
dre_clk => primary_aclk ,
dre_rst => mmap_reset ,
-- Alignment Control (Independent from Stream Input timing)
dre_align_ready => sig_dre_align_ready ,
dre_align_valid => sig_sm_ld_dre_cmd ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_scatter2dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
-- Flush Control (Aligned to input Stream timing)
dre_flush => sig_scatter2dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_scatter2dre_tstrb ,
dre_in_tdata => sig_scatter2dre_tdata ,
dre_in_tlast => sig_scatter2dre_tlast ,
dre_in_tvalid => sig_scatter2dre_tvalid ,
dre_in_tready => sig_dre2scatter_tready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2wdc_tstrb ,
dre_out_tdata => sig_dre2wdc_tdata ,
dre_out_tlast => sig_dre2wdc_tlast ,
dre_out_tvalid => sig_dre2wdc_tvalid ,
dre_out_tready => sig_wdc2dre_tready
);
lsig_dre_load_beat <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready;
lsig_set_eop <= sig_scatter2drc_eop and
lsig_dre_load_beat ;
lsig_dre_tlast_output_beat <= sig_dre2wdc_tvalid and
sig_wdc2dre_tready and
sig_dre2wdc_tlast;
dre2wdc_eop <= lsig_dre_tlast_output_beat and
lsig_eop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG
--
-- Process Description:
-- Implements a flop for holding the EOP from the Scatter
-- Engine until the corresponding packet clears out of the DRE.
-- THis is used to transfer the EOP marker to the DRE output
-- stream without the need for the DRE to pass it through.
--
-------------------------------------------------------------
IMP_EOP_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(lsig_dre_tlast_output_beat = '1' and
lsig_set_eop = '0')) then
lsig_eop_reg <= '0';
elsif (lsig_set_eop = '1') then
lsig_eop_reg <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_EOP_REG;
-- Delay TLAST Error by 2 clocks to compensate for DRE minimum
-- delay of 2 clocks for the stream data.
sig_tlast_err0r <= lsig_tlast_err_reg2;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_DELAY
--
-- Process Description:
-- Implements a 2 clock delay to better align the TLAST
-- error detection with the Stream output data to the WDC
-- which has a minimum 2 clock delay through the DRE.
--
-------------------------------------------------------------
IMP_TLAST_ERR_DELAY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_tlast_err_reg1 <= '0';
lsig_tlast_err_reg2 <= '0';
else
lsig_tlast_err_reg1 <= sig_scatter2all_tlast_error;
lsig_tlast_err_reg2 <= lsig_tlast_err_reg1;
end if;
end if;
end process IMP_TLAST_ERR_DELAY;
-------------------------------------------------------------------------
-- Store and Forward Start Address Offset Registers Logic
-- Push-pull register is used to to time align the starting address
-- offset (ripped from the Realigner command via parsing) to DRE
-- TLAST output timing. The offset output of the pull register must
-- be valid on the first output databeat of the DRE to the Store and
-- Forward module.
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= lsig_pull_strt_offset_reg;
-- lsig_push_new_offset <= sig_dre_align_ready and
-- sig_gated_dre_align_valid ;
lsig_push_new_offset <= sig_sm_ld_dre_cmd ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the input register for holding the starting address
-- offset sent to the external Store and Forward functions.
--
-------------------------------------------------------------
IMP_PUSH_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
elsif (lsig_push_new_offset = '1') then
lsig_push_strt_offset_reg <= sig_curr_strt_offset_reg;
lsig_pushreg_full <= '1';
lsig_pushreg_empty <= '0';
elsif (lsig_pull_new_offset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PUSH_STRT_OFFSET_REG;
-- Pull the next offset (if one exists) into the pull register
-- when the DRE outputs a TLAST. If the pull register is empty
-- and the push register has an offset, then push the new value
-- into the pull register.
lsig_pull_new_offset <= (sig_dre2wdc_tlast and
sig_dre2wdc_tvalid and
sig_wdc2dre_tready) or
(lsig_pushreg_full and
lsig_pullreg_empty);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PULL_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the output register for holding the starting
-- address offset sent to the Store and Forward modul's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_PULL_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '1') then
lsig_pull_strt_offset_reg <= lsig_push_strt_offset_reg;
lsig_pullreg_full <= '1';
lsig_pullreg_empty <= '0';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '0') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PULL_STRT_OFFSET_REG;
end generate GEN_INCLUDE_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_DRE
--
-- If Generate Description:
-- Omits the DRE from the Re-aligner.
--
--
------------------------------------------------------------
GEN_OMIT_DRE : if (OMIT_DRE) generate
begin
-- DRE always ready
sig_dre_align_ready <= '1';
-- -- Let the Scatter engine control the Realigner command
-- -- flow.
-- sig_dre_align_ready <= sig_scatter2drc_cmd_ready;
-- Pass through signal connections
sig_dre2wdc_tstrb <= sig_scatter2dre_tstrb ;
sig_dre2wdc_tdata <= sig_scatter2dre_tdata ;
sig_dre2wdc_tlast <= sig_scatter2dre_tlast ;
sig_dre2wdc_tvalid <= sig_scatter2dre_tvalid ;
sig_dre2scatter_tready <= sig_wdc2dre_tready ;
dre2wdc_eop <= sig_scatter2drc_eop ;
-- Just pass TLAST Error through when no DRE is present
sig_tlast_err0r <= sig_scatter2all_tlast_error;
-------------------------------------------------------------------------
-------- Store and Forward Start Address Offset Register Logic
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= sig_output_strt_offset_reg;
sig_ld_strt_offset <= sig_sm_ld_dre_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STRT_OFFSET_OUTPUT
--
-- Process Description:
-- Implements the register for holding the starting address
-- offset sent to the S2MM Store and Forward module's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_STRT_OFFSET_OUTPUT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_output_strt_offset_reg <= (others => '0');
elsif (sig_ld_strt_offset = '1') then
sig_output_strt_offset_reg <= sig_curr_strt_offset_reg;
else
null; -- Hold Current State
end if;
end if;
end process IMP_STRT_OFFSET_OUTPUT;
end generate GEN_OMIT_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_SCATTER
--
-- If Generate Description:
-- This IfGen implements the Scatter function which is a pre-
-- processor for the S2MM DRE. The scatter function breaks up
-- a continous input stream of data into constituant parts
-- as described by a set of loaded commands that together
-- describe an entire input packet.
--
------------------------------------------------------------
GEN_INCLUDE_SCATTER : if (C_SUPPORT_SCATTER = 1) generate
begin
-- Load the Scatter Engine command when the DRE command
-- is loaded
-- sig_drc2scatter_push_cmd <= sig_dre_align_ready and
-- sig_gated_dre_align_valid;
sig_drc2scatter_push_cmd <= sig_sm_ld_scatter_cmd ;
-- Assign the new Bytes to Transfer (BTT) qualifier for the
-- Scatter Engine
sig_drc2scatter_btt <= sig_curr_btt_reg;
-- Assign the new End of Frame (EOF) qualifier for the
-- Scatter Engine
sig_drc2scatter_eof <= sig_curr_eof_reg;
------------------------------------------------------------
-- Instance: I_S2MM_SCATTER
--
-- Description:
-- Instance for the Scatter Engine. This block breaks up a
-- input stream per commands loaded.
--
------------------------------------------------------------
I_S2MM_SCATTER : entity axi_datamover_v5_1.axi_datamover_s2mm_scatter
generic map (
C_ENABLE_INDET_BTT => C_ENABLE_INDET_BTT ,
C_DRE_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_BTT_USED => BTT_WIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock input & Reset input
primary_aclk => primary_aclk ,
mmap_reset => mmap_reset ,
-- DRE Realign Controller I/O ----------------------------
scatter2drc_cmd_ready => sig_scatter2drc_cmd_ready ,
drc2scatter_push_cmd => sig_drc2scatter_push_cmd ,
drc2scatter_btt => sig_drc2scatter_btt ,
drc2scatter_eof => sig_drc2scatter_eof ,
-- DRE Source Alignment -----------------------------------
scatter2drc_src_align => sig_scatter2dre_src_align ,
-- AXI Slave Stream In -----------------------------------
s2mm_strm_tready => sig_scatter2strm_tready ,
s2mm_strm_tvalid => sig_strm2scatter_tvalid ,
s2mm_strm_tdata => sig_strm2scatter_tdata ,
s2mm_strm_tstrb => sig_strm2scatter_tstrb ,
s2mm_strm_tlast => sig_strm2scatter_tlast ,
-- Stream Out to S2MM DRE ---------------------------------
drc2scatter_tready => sig_dre2scatter_tready ,
scatter2drc_tvalid => sig_scatter2dre_tvalid ,
scatter2drc_tdata => sig_scatter2dre_tdata ,
scatter2drc_tstrb => sig_scatter2dre_tstrb ,
scatter2drc_tlast => sig_scatter2dre_tlast ,
scatter2drc_flush => sig_scatter2dre_flush ,
scatter2drc_eop => sig_scatter2drc_eop ,
-- Premature TLAST assertion error flag
scatter2drc_tlast_error => sig_scatter2all_tlast_error
);
end generate GEN_INCLUDE_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_SCATTER
--
-- If Generate Description:
-- This IfGen omits the Scatter pre-processor.
--
--
------------------------------------------------------------
GEN_OMIT_SCATTER : if (C_SUPPORT_SCATTER = 0) generate
begin
-- Just housekeep the signaling
sig_scatter2drc_cmd_ready <= '1' ;
sig_scatter2drc_eop <= sig_strm2scatter_tlast ;
sig_scatter2dre_src_align <= sig_dre_src_align ;
sig_scatter2all_tlast_error <= '0' ;
sig_scatter2dre_flush <= sig_dre_flush ;
sig_scatter2dre_tstrb <= sig_strm2scatter_tstrb ;
sig_scatter2dre_tdata <= sig_strm2scatter_tdata ;
sig_scatter2dre_tlast <= sig_strm2scatter_tlast ;
sig_scatter2dre_tvalid <= sig_strm2scatter_tvalid ;
sig_scatter2strm_tready <= sig_dre2scatter_tready ;
end generate GEN_OMIT_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omit and special logic for Indeterminate BTT support.
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_need_cmd_flush <= '0' ; -- not needed without Indeterminate BTT
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Include logic for the case when Indeterminate BTT is
-- included as part of the S2MM. In this mode, the actual
-- length of input stream packets is not known when the S2MM
-- is loaded with a transfer command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
signal lsig_clr_cmd_flush : std_logic := '0';
signal lsig_set_cmd_flush : std_logic := '0';
signal lsig_cmd_set_fetch_pause : std_logic := '0';
signal lsig_cmd_clr_fetch_pause : std_logic := '0';
signal lsig_cmd_fetch_pause : std_logic := '0';
begin
lsig_cmd_set_fetch_pause <= sig_drc2scatter_push_cmd and
not(sig_curr_cmd_cmplt_reg) and
not(sig_need_cmd_flush);
lsig_cmd_clr_fetch_pause <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2dre_tlast;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FETCH_PAUSE
--
-- Process Description:
-- Implements the flop for the flag that causes the command
-- queue manager to pause fetching the next command if the
-- current command does not have the command complete bit set.
-- The pause remains set until the associated TLAST for the
-- command is output from the Scatter Engine. If the Tlast is
-- also accompanied by a EOP and the pause is set, then the
-- ensuing command (which will have the cmd cmplt bit set) must
-- be flushed from the queue and not loaded into the Scatter
-- Engine or DRE, This is normally associated with indeterminate
-- packets that are actually shorter than the intial align to
-- max burst child command sent to the Realigner, The next loaded
-- child command is to finish the remainder of the indeterminate
-- packet up to the full BTT value in the original parent command.
-- This child command becomes stranded in the Realigner command fifo
-- and has to be flushed.
--
-------------------------------------------------------------
IMP_CMD_FETCH_PAUSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_cmd_clr_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '0';
elsif (lsig_cmd_set_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FETCH_PAUSE;
-- Clear the flush needed flag when the command with the command
-- complete marker is popped off of the command queue.
lsig_clr_cmd_flush <= sig_need_cmd_flush and
sig_sm_pop_cmd_fifo;
-- The command queue has to be flushed if the stream EOP marker
-- is transfered out of the Scatter Engine when the corresponding
-- command being executed does not have the command complete
-- marker set.
lsig_set_cmd_flush <= lsig_cmd_fetch_pause and
sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2drc_eop;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLUSH_FLOP
--
-- Process Description:
-- Implements the flop for holding the command flush flag.
-- This is only needed in Indeterminate BTT mode.
--
-------------------------------------------------------------
IMP_CMD_FLUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_cmd_flush = '1') then
sig_need_cmd_flush <= '0';
elsif (lsig_set_cmd_flush = '1') then
sig_need_cmd_flush <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FLUSH_FLOP;
end generate GEN_ENABLE_INDET_BTT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_realign.vhd
--
-- Description:
-- This file implements the S2MM Data Realignment module. THe S2MM direction is
-- more complex than the MM2S direction since the DRE needs to be upstream from
-- the Write Data Controller. This requires the S2MM DRE to be running 2 to
-- 3 clocks ahead of the Write Data controller to minimize/eliminate xfer
-- bubble insertion.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_fifo;
use axi_datamover_v5_1.axi_datamover_s2mm_dre;
use axi_datamover_v5_1.axi_datamover_s2mm_scatter;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_realign is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the IBTT Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_INCLUDE_DRE : Integer range 0 to 1 := 1;
-- Includes/Omits the S2MM DRE
-- 0 = Omit
-- 1 = Include
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal command queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_SUPPORT_SCATTER : Integer range 0 to 1 := 1;
-- Includes/Omits the Scatter functionality
-- 0 = omit
-- 1 = include
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_BTT_USED : Integer range 8 to 23 := 16;
-- Indicates the width of the input command BTT that is actually
-- used
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Input and Output Stream Data ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the input command Tag port
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 ;
-- Sets the width of the Store and Forward Start offset ports
C_FAMILY : String := "virtex7"
-- specifies the target FPGA familiy
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------------
-- Write Data Controller or IBTT Indeterminate BTT I/O -------------------------
--
wdc2dre_wready : In std_logic; --
-- Write READY input from WDC or SF --
--
dre2wdc_wvalid : Out std_logic; --
-- Write VALID output to WDC or SF --
--
dre2wdc_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wlast : Out std_logic; --
-- Write LAST output to WDC or SF --
--
dre2wdc_eop : Out std_logic; --
-- End of Packet indicator for the Stream input to WDC or SF --
--------------------------------------------------------------------------------
-- Starting offset output for the Store and Forward Modules -------------------
--
dre2sf_strt_offset : Out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Command Calculator Interface ---------------------------------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2dre_cmd_cmplt : In std_logic; --
-- The last tranfer command of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- Premature TLAST assertion error flag -----------------------------
--
dre2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the DRE detected --
-- a Early/Late TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------
-- DRE Halted Status ------------------------------------------------
--
dre2all_halted : Out std_logic --
-- When asserted, this indicates the DRE has satisfied --
-- all pending transfers queued by the command calculator --
-- and is halted. --
---------------------------------------------------------------------
);
end entity axi_datamover_s2mm_realign;
architecture implementation of axi_datamover_s2mm_realign is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations --------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_realign_fifo
--
-- Function Description:
-- Assures that the Realigner cmd fifo depth is at least 4 deep else it
-- is equal to the pipe depth.
--
-------------------------------------------------------------------
function funct_size_realign_fifo (pipe_depth : integer) return integer is
Variable temp_fifo_depth : Integer := 4;
begin
If (pipe_depth < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := pipe_depth;
End if;
Return (temp_fifo_depth);
end function funct_size_realign_fifo;
-- Constant Declarations --------------------------------------------
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant BTT_WIDTH : integer := C_BTT_USED;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant BTT_OF_ZERO : std_logic_vector(BTT_WIDTH-1 downto 0)
:= (others => '0');
Constant DRECTL_FIFO_DEPTH : integer := funct_size_realign_fifo(C_DRE_CNTL_FIFO_DEPTH);
Constant DRECTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
BTT_WIDTH + -- BTT field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant BTT_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := BTT_STRT_INDEX + BTT_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
Constant INCLUDE_DRE : boolean := (C_INCLUDE_DRE = 1 and
C_STREAM_DWIDTH <= 64 and
C_STREAM_DWIDTH >= 16);
Constant OMIT_DRE : boolean := not(INCLUDE_DRE);
-- Type Declarations --------------------------------------------
type TYPE_CMD_CNTL_SM is (
INIT,
LD_DRE_SCATTER_FIRST,
CHK_POP_FIRST ,
LD_DRE_SCATTER_SECOND,
CHK_POP_SECOND,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_cmdcntl_sm_state : TYPE_CMD_CNTL_SM := INIT;
Signal sig_cmdcntl_sm_state_ns : TYPE_CMD_CNTL_SM := INIT;
signal sig_sm_ld_dre_cmd_ns : std_logic := '0';
signal sig_sm_ld_dre_cmd : std_logic := '0';
signal sig_sm_ld_scatter_cmd_ns : std_logic := '0';
signal sig_sm_ld_scatter_cmd : std_logic := '0';
signal sig_sm_pop_cmd_fifo_ns : std_logic := '0';
signal sig_sm_pop_cmd_fifo : std_logic := '0';
signal sig_cmd_fifo_data_in : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_btt_reg : std_logic_vector(BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_cmd_cmplt_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_dre2wdc_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2wdc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_dre2wdc_tlast : std_logic := '0';
signal sig_dre2wdc_tvalid : std_logic := '0';
signal sig_wdc2dre_tready : std_logic := '0';
signal sig_tlast_err0r : std_logic := '0';
signal sig_dre_halted : std_logic := '0';
signal sig_strm2scatter_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_strm2scatter_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm2scatter_tlast : std_logic := '0';
signal sig_strm2scatter_tvalid : std_logic := '0';
signal sig_scatter2strm_tready : std_logic := '0';
signal sig_scatter2dre_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_scatter2dre_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2dre_tlast : std_logic := '0';
signal sig_scatter2dre_tvalid : std_logic := '0';
signal sig_dre2scatter_tready : std_logic := '0';
signal sig_scatter2dre_flush : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_scatter2dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_cmd_ready : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic;
signal sig_drc2scatter_btt : std_logic_vector(BTT_WIDTH-1 downto 0);
signal sig_drc2scatter_eof : std_logic;
signal sig_scatter2all_tlast_error : std_logic := '0';
signal sig_need_cmd_flush : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_strt_offset : std_logic := '0';
signal sig_output_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2sf_strt_offset : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Port connections
-- Input Stream Attachment
s2mm_strm_wready <= sig_scatter2strm_tready ;
sig_strm2scatter_tvalid <= s2mm_strm_wvalid ;
sig_strm2scatter_tdata <= s2mm_strm_wdata ;
sig_strm2scatter_tstrb <= s2mm_strm_wstrb ;
sig_strm2scatter_tlast <= s2mm_strm_wlast ;
-- Write Data Controller Stream Attachment
sig_wdc2dre_tready <= wdc2dre_wready ;
dre2wdc_wvalid <= sig_dre2wdc_tvalid ;
dre2wdc_wdata <= sig_dre2wdc_tdata ;
dre2wdc_wstrb <= sig_dre2wdc_tstrb ;
dre2wdc_wlast <= sig_dre2wdc_tlast ;
-- Status/Error flags
dre2all_tlast_error <= sig_tlast_err0r ;
dre2all_halted <= sig_dre_halted ;
-- Store and Forward Starting Offset Output
dre2sf_strt_offset <= sig_dre2sf_strt_offset ;
-------------------------------------------------------------
-- Internal logic
sig_dre_halted <= sig_dre_align_ready;
-------------------------------------------------------------
-- DRE Handshake signals
sig_dre_src_align <= sig_curr_src_align_reg ;
sig_dre_dest_align <= sig_curr_dest_align_reg;
sig_dre_use_autodest <= '0'; -- not used
sig_dre_flush <= '0'; -- not used
-------------------------------------------------------------------------
-------- Realigner Command FIFO and controls
-------------------------------------------------------------------------
-- Command Calculator Handshake
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_cmd_cmplt &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_btt &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto DEST_ALIGN_STRT_INDEX);
sig_curr_btt_reg <= sig_cmd_fifo_data_out((BTT_STRT_INDEX+BTT_WIDTH)-1 downto BTT_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_cmd_cmplt_reg <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => DRECTL_FIFO_WIDTH ,
C_DEPTH => DRECTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_sm_pop_cmd_fifo ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-------- DRE and Scatter Command Loader State Machine
-------------------------------------------------------------------------
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CMDCNTL_SM_COMBINATIONAL
--
-- Process Description:
-- Command Controller State Machine combinational implementation
-- The design is based on the premise that for every parent
-- command loaded into the S2MM, the Realigner can be loaded with
-- 1 or 2 commands spawned from it. The first command is used to
-- align ensuing transfers (in MMap space) to a max burst address
-- boundary. Then, if the parent command's BTT value is not satisfied
-- after the first command completes, a second command is generated
-- and loaded in the Realigner for the remaining BTT value. The
-- command complete bit in the Realigner command indicates if the
-- first command the final command or the second command (if needed)
-- is the final command,
-------------------------------------------------------------
CMDCNTL_SM_COMBINATIONAL : process (sig_cmdcntl_sm_state ,
sig_fifo_rd_cmd_valid ,
sig_dre_align_ready ,
sig_scatter2drc_cmd_ready ,
sig_need_cmd_flush ,
sig_curr_cmd_cmplt_reg ,
sig_curr_calc_error_reg
)
begin
-- SM Defaults
sig_cmdcntl_sm_state_ns <= INIT;
sig_sm_ld_dre_cmd_ns <= '0';
sig_sm_ld_scatter_cmd_ns <= '0';
sig_sm_pop_cmd_fifo_ns <= '0';
case sig_cmdcntl_sm_state is
--------------------------------------------
when INIT =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
--------------------------------------------
when LD_DRE_SCATTER_FIRST =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
End if;
--------------------------------------------
when CHK_POP_FIRST =>
If (sig_curr_cmd_cmplt_reg = '1') Then
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
Else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when LD_DRE_SCATTER_SECOND =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_need_cmd_flush = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_SECOND ;
sig_sm_pop_cmd_fifo_ns <= '1';
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when CHK_POP_SECOND =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST ;
--------------------------------------------
when ERROR_TRAP =>
sig_cmdcntl_sm_state_ns <= ERROR_TRAP ;
--------------------------------------------
when others =>
sig_cmdcntl_sm_state_ns <= INIT;
end case;
end process CMDCNTL_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMDCNTL_SM_REGISTERED
--
-- Process Description:
-- Command Controller State Machine registered implementation
--
-------------------------------------------------------------
CMDCNTL_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_cmdcntl_sm_state <= INIT;
sig_sm_ld_dre_cmd <= '0' ;
sig_sm_ld_scatter_cmd <= '0' ;
sig_sm_pop_cmd_fifo <= '0' ;
else
sig_cmdcntl_sm_state <= sig_cmdcntl_sm_state_ns ;
sig_sm_ld_dre_cmd <= sig_sm_ld_dre_cmd_ns ;
sig_sm_ld_scatter_cmd <= sig_sm_ld_scatter_cmd_ns ;
sig_sm_pop_cmd_fifo <= sig_sm_pop_cmd_fifo_ns ;
end if;
end if;
end process CMDCNTL_SM_REGISTERED;
-------------------------------------------------------------------------
-------- DRE Instance and controls
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE
--
-- If Generate Description:
-- Includes the instance for the DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE : if (INCLUDE_DRE) generate
signal lsig_eop_reg : std_logic := '0';
signal lsig_dre_load_beat : std_logic := '0';
signal lsig_dre_tlast_output_beat : std_logic := '0';
signal lsig_set_eop : std_logic := '0';
signal lsig_tlast_err_reg1 : std_logic := '0';
signal lsig_tlast_err_reg2 : std_logic := '0';
signal lsig_push_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pushreg_full : std_logic := '0';
signal lsig_pushreg_empty : std_logic := '0';
signal lsig_pull_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pullreg_full : std_logic := '0';
signal lsig_pullreg_empty : std_logic := '0';
signal lsig_pull_new_offset : std_logic := '0';
signal lsig_push_new_offset : std_logic := '0';
begin
------------------------------------------------------------
-- Instance: I_S2MM_DRE_BLOCK
--
-- Description:
-- Instance for the S2MM Data Realignment Engine (DRE)
--
------------------------------------------------------------
I_S2MM_DRE_BLOCK : entity axi_datamover_v5_1.axi_datamover_s2mm_dre
generic map (
C_DWIDTH => C_STREAM_DWIDTH ,
C_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH
)
port map (
-- Clock and Reset
dre_clk => primary_aclk ,
dre_rst => mmap_reset ,
-- Alignment Control (Independent from Stream Input timing)
dre_align_ready => sig_dre_align_ready ,
dre_align_valid => sig_sm_ld_dre_cmd ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_scatter2dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
-- Flush Control (Aligned to input Stream timing)
dre_flush => sig_scatter2dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_scatter2dre_tstrb ,
dre_in_tdata => sig_scatter2dre_tdata ,
dre_in_tlast => sig_scatter2dre_tlast ,
dre_in_tvalid => sig_scatter2dre_tvalid ,
dre_in_tready => sig_dre2scatter_tready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2wdc_tstrb ,
dre_out_tdata => sig_dre2wdc_tdata ,
dre_out_tlast => sig_dre2wdc_tlast ,
dre_out_tvalid => sig_dre2wdc_tvalid ,
dre_out_tready => sig_wdc2dre_tready
);
lsig_dre_load_beat <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready;
lsig_set_eop <= sig_scatter2drc_eop and
lsig_dre_load_beat ;
lsig_dre_tlast_output_beat <= sig_dre2wdc_tvalid and
sig_wdc2dre_tready and
sig_dre2wdc_tlast;
dre2wdc_eop <= lsig_dre_tlast_output_beat and
lsig_eop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG
--
-- Process Description:
-- Implements a flop for holding the EOP from the Scatter
-- Engine until the corresponding packet clears out of the DRE.
-- THis is used to transfer the EOP marker to the DRE output
-- stream without the need for the DRE to pass it through.
--
-------------------------------------------------------------
IMP_EOP_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(lsig_dre_tlast_output_beat = '1' and
lsig_set_eop = '0')) then
lsig_eop_reg <= '0';
elsif (lsig_set_eop = '1') then
lsig_eop_reg <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_EOP_REG;
-- Delay TLAST Error by 2 clocks to compensate for DRE minimum
-- delay of 2 clocks for the stream data.
sig_tlast_err0r <= lsig_tlast_err_reg2;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_DELAY
--
-- Process Description:
-- Implements a 2 clock delay to better align the TLAST
-- error detection with the Stream output data to the WDC
-- which has a minimum 2 clock delay through the DRE.
--
-------------------------------------------------------------
IMP_TLAST_ERR_DELAY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_tlast_err_reg1 <= '0';
lsig_tlast_err_reg2 <= '0';
else
lsig_tlast_err_reg1 <= sig_scatter2all_tlast_error;
lsig_tlast_err_reg2 <= lsig_tlast_err_reg1;
end if;
end if;
end process IMP_TLAST_ERR_DELAY;
-------------------------------------------------------------------------
-- Store and Forward Start Address Offset Registers Logic
-- Push-pull register is used to to time align the starting address
-- offset (ripped from the Realigner command via parsing) to DRE
-- TLAST output timing. The offset output of the pull register must
-- be valid on the first output databeat of the DRE to the Store and
-- Forward module.
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= lsig_pull_strt_offset_reg;
-- lsig_push_new_offset <= sig_dre_align_ready and
-- sig_gated_dre_align_valid ;
lsig_push_new_offset <= sig_sm_ld_dre_cmd ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the input register for holding the starting address
-- offset sent to the external Store and Forward functions.
--
-------------------------------------------------------------
IMP_PUSH_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
elsif (lsig_push_new_offset = '1') then
lsig_push_strt_offset_reg <= sig_curr_strt_offset_reg;
lsig_pushreg_full <= '1';
lsig_pushreg_empty <= '0';
elsif (lsig_pull_new_offset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PUSH_STRT_OFFSET_REG;
-- Pull the next offset (if one exists) into the pull register
-- when the DRE outputs a TLAST. If the pull register is empty
-- and the push register has an offset, then push the new value
-- into the pull register.
lsig_pull_new_offset <= (sig_dre2wdc_tlast and
sig_dre2wdc_tvalid and
sig_wdc2dre_tready) or
(lsig_pushreg_full and
lsig_pullreg_empty);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PULL_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the output register for holding the starting
-- address offset sent to the Store and Forward modul's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_PULL_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '1') then
lsig_pull_strt_offset_reg <= lsig_push_strt_offset_reg;
lsig_pullreg_full <= '1';
lsig_pullreg_empty <= '0';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '0') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PULL_STRT_OFFSET_REG;
end generate GEN_INCLUDE_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_DRE
--
-- If Generate Description:
-- Omits the DRE from the Re-aligner.
--
--
------------------------------------------------------------
GEN_OMIT_DRE : if (OMIT_DRE) generate
begin
-- DRE always ready
sig_dre_align_ready <= '1';
-- -- Let the Scatter engine control the Realigner command
-- -- flow.
-- sig_dre_align_ready <= sig_scatter2drc_cmd_ready;
-- Pass through signal connections
sig_dre2wdc_tstrb <= sig_scatter2dre_tstrb ;
sig_dre2wdc_tdata <= sig_scatter2dre_tdata ;
sig_dre2wdc_tlast <= sig_scatter2dre_tlast ;
sig_dre2wdc_tvalid <= sig_scatter2dre_tvalid ;
sig_dre2scatter_tready <= sig_wdc2dre_tready ;
dre2wdc_eop <= sig_scatter2drc_eop ;
-- Just pass TLAST Error through when no DRE is present
sig_tlast_err0r <= sig_scatter2all_tlast_error;
-------------------------------------------------------------------------
-------- Store and Forward Start Address Offset Register Logic
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= sig_output_strt_offset_reg;
sig_ld_strt_offset <= sig_sm_ld_dre_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STRT_OFFSET_OUTPUT
--
-- Process Description:
-- Implements the register for holding the starting address
-- offset sent to the S2MM Store and Forward module's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_STRT_OFFSET_OUTPUT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_output_strt_offset_reg <= (others => '0');
elsif (sig_ld_strt_offset = '1') then
sig_output_strt_offset_reg <= sig_curr_strt_offset_reg;
else
null; -- Hold Current State
end if;
end if;
end process IMP_STRT_OFFSET_OUTPUT;
end generate GEN_OMIT_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_SCATTER
--
-- If Generate Description:
-- This IfGen implements the Scatter function which is a pre-
-- processor for the S2MM DRE. The scatter function breaks up
-- a continous input stream of data into constituant parts
-- as described by a set of loaded commands that together
-- describe an entire input packet.
--
------------------------------------------------------------
GEN_INCLUDE_SCATTER : if (C_SUPPORT_SCATTER = 1) generate
begin
-- Load the Scatter Engine command when the DRE command
-- is loaded
-- sig_drc2scatter_push_cmd <= sig_dre_align_ready and
-- sig_gated_dre_align_valid;
sig_drc2scatter_push_cmd <= sig_sm_ld_scatter_cmd ;
-- Assign the new Bytes to Transfer (BTT) qualifier for the
-- Scatter Engine
sig_drc2scatter_btt <= sig_curr_btt_reg;
-- Assign the new End of Frame (EOF) qualifier for the
-- Scatter Engine
sig_drc2scatter_eof <= sig_curr_eof_reg;
------------------------------------------------------------
-- Instance: I_S2MM_SCATTER
--
-- Description:
-- Instance for the Scatter Engine. This block breaks up a
-- input stream per commands loaded.
--
------------------------------------------------------------
I_S2MM_SCATTER : entity axi_datamover_v5_1.axi_datamover_s2mm_scatter
generic map (
C_ENABLE_INDET_BTT => C_ENABLE_INDET_BTT ,
C_DRE_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_BTT_USED => BTT_WIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock input & Reset input
primary_aclk => primary_aclk ,
mmap_reset => mmap_reset ,
-- DRE Realign Controller I/O ----------------------------
scatter2drc_cmd_ready => sig_scatter2drc_cmd_ready ,
drc2scatter_push_cmd => sig_drc2scatter_push_cmd ,
drc2scatter_btt => sig_drc2scatter_btt ,
drc2scatter_eof => sig_drc2scatter_eof ,
-- DRE Source Alignment -----------------------------------
scatter2drc_src_align => sig_scatter2dre_src_align ,
-- AXI Slave Stream In -----------------------------------
s2mm_strm_tready => sig_scatter2strm_tready ,
s2mm_strm_tvalid => sig_strm2scatter_tvalid ,
s2mm_strm_tdata => sig_strm2scatter_tdata ,
s2mm_strm_tstrb => sig_strm2scatter_tstrb ,
s2mm_strm_tlast => sig_strm2scatter_tlast ,
-- Stream Out to S2MM DRE ---------------------------------
drc2scatter_tready => sig_dre2scatter_tready ,
scatter2drc_tvalid => sig_scatter2dre_tvalid ,
scatter2drc_tdata => sig_scatter2dre_tdata ,
scatter2drc_tstrb => sig_scatter2dre_tstrb ,
scatter2drc_tlast => sig_scatter2dre_tlast ,
scatter2drc_flush => sig_scatter2dre_flush ,
scatter2drc_eop => sig_scatter2drc_eop ,
-- Premature TLAST assertion error flag
scatter2drc_tlast_error => sig_scatter2all_tlast_error
);
end generate GEN_INCLUDE_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_SCATTER
--
-- If Generate Description:
-- This IfGen omits the Scatter pre-processor.
--
--
------------------------------------------------------------
GEN_OMIT_SCATTER : if (C_SUPPORT_SCATTER = 0) generate
begin
-- Just housekeep the signaling
sig_scatter2drc_cmd_ready <= '1' ;
sig_scatter2drc_eop <= sig_strm2scatter_tlast ;
sig_scatter2dre_src_align <= sig_dre_src_align ;
sig_scatter2all_tlast_error <= '0' ;
sig_scatter2dre_flush <= sig_dre_flush ;
sig_scatter2dre_tstrb <= sig_strm2scatter_tstrb ;
sig_scatter2dre_tdata <= sig_strm2scatter_tdata ;
sig_scatter2dre_tlast <= sig_strm2scatter_tlast ;
sig_scatter2dre_tvalid <= sig_strm2scatter_tvalid ;
sig_scatter2strm_tready <= sig_dre2scatter_tready ;
end generate GEN_OMIT_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omit and special logic for Indeterminate BTT support.
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_need_cmd_flush <= '0' ; -- not needed without Indeterminate BTT
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Include logic for the case when Indeterminate BTT is
-- included as part of the S2MM. In this mode, the actual
-- length of input stream packets is not known when the S2MM
-- is loaded with a transfer command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
signal lsig_clr_cmd_flush : std_logic := '0';
signal lsig_set_cmd_flush : std_logic := '0';
signal lsig_cmd_set_fetch_pause : std_logic := '0';
signal lsig_cmd_clr_fetch_pause : std_logic := '0';
signal lsig_cmd_fetch_pause : std_logic := '0';
begin
lsig_cmd_set_fetch_pause <= sig_drc2scatter_push_cmd and
not(sig_curr_cmd_cmplt_reg) and
not(sig_need_cmd_flush);
lsig_cmd_clr_fetch_pause <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2dre_tlast;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FETCH_PAUSE
--
-- Process Description:
-- Implements the flop for the flag that causes the command
-- queue manager to pause fetching the next command if the
-- current command does not have the command complete bit set.
-- The pause remains set until the associated TLAST for the
-- command is output from the Scatter Engine. If the Tlast is
-- also accompanied by a EOP and the pause is set, then the
-- ensuing command (which will have the cmd cmplt bit set) must
-- be flushed from the queue and not loaded into the Scatter
-- Engine or DRE, This is normally associated with indeterminate
-- packets that are actually shorter than the intial align to
-- max burst child command sent to the Realigner, The next loaded
-- child command is to finish the remainder of the indeterminate
-- packet up to the full BTT value in the original parent command.
-- This child command becomes stranded in the Realigner command fifo
-- and has to be flushed.
--
-------------------------------------------------------------
IMP_CMD_FETCH_PAUSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_cmd_clr_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '0';
elsif (lsig_cmd_set_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FETCH_PAUSE;
-- Clear the flush needed flag when the command with the command
-- complete marker is popped off of the command queue.
lsig_clr_cmd_flush <= sig_need_cmd_flush and
sig_sm_pop_cmd_fifo;
-- The command queue has to be flushed if the stream EOP marker
-- is transfered out of the Scatter Engine when the corresponding
-- command being executed does not have the command complete
-- marker set.
lsig_set_cmd_flush <= lsig_cmd_fetch_pause and
sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2drc_eop;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLUSH_FLOP
--
-- Process Description:
-- Implements the flop for holding the command flush flag.
-- This is only needed in Indeterminate BTT mode.
--
-------------------------------------------------------------
IMP_CMD_FLUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_cmd_flush = '1') then
sig_need_cmd_flush <= '0';
elsif (lsig_set_cmd_flush = '1') then
sig_need_cmd_flush <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FLUSH_FLOP;
end generate GEN_ENABLE_INDET_BTT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_realign.vhd
--
-- Description:
-- This file implements the S2MM Data Realignment module. THe S2MM direction is
-- more complex than the MM2S direction since the DRE needs to be upstream from
-- the Write Data Controller. This requires the S2MM DRE to be running 2 to
-- 3 clocks ahead of the Write Data controller to minimize/eliminate xfer
-- bubble insertion.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_fifo;
use axi_datamover_v5_1.axi_datamover_s2mm_dre;
use axi_datamover_v5_1.axi_datamover_s2mm_scatter;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_realign is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the IBTT Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_INCLUDE_DRE : Integer range 0 to 1 := 1;
-- Includes/Omits the S2MM DRE
-- 0 = Omit
-- 1 = Include
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal command queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_SUPPORT_SCATTER : Integer range 0 to 1 := 1;
-- Includes/Omits the Scatter functionality
-- 0 = omit
-- 1 = include
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_BTT_USED : Integer range 8 to 23 := 16;
-- Indicates the width of the input command BTT that is actually
-- used
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Input and Output Stream Data ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the input command Tag port
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 ;
-- Sets the width of the Store and Forward Start offset ports
C_FAMILY : String := "virtex7"
-- specifies the target FPGA familiy
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------------
-- Write Data Controller or IBTT Indeterminate BTT I/O -------------------------
--
wdc2dre_wready : In std_logic; --
-- Write READY input from WDC or SF --
--
dre2wdc_wvalid : Out std_logic; --
-- Write VALID output to WDC or SF --
--
dre2wdc_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wlast : Out std_logic; --
-- Write LAST output to WDC or SF --
--
dre2wdc_eop : Out std_logic; --
-- End of Packet indicator for the Stream input to WDC or SF --
--------------------------------------------------------------------------------
-- Starting offset output for the Store and Forward Modules -------------------
--
dre2sf_strt_offset : Out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Command Calculator Interface ---------------------------------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2dre_cmd_cmplt : In std_logic; --
-- The last tranfer command of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- Premature TLAST assertion error flag -----------------------------
--
dre2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the DRE detected --
-- a Early/Late TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------
-- DRE Halted Status ------------------------------------------------
--
dre2all_halted : Out std_logic --
-- When asserted, this indicates the DRE has satisfied --
-- all pending transfers queued by the command calculator --
-- and is halted. --
---------------------------------------------------------------------
);
end entity axi_datamover_s2mm_realign;
architecture implementation of axi_datamover_s2mm_realign is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations --------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_realign_fifo
--
-- Function Description:
-- Assures that the Realigner cmd fifo depth is at least 4 deep else it
-- is equal to the pipe depth.
--
-------------------------------------------------------------------
function funct_size_realign_fifo (pipe_depth : integer) return integer is
Variable temp_fifo_depth : Integer := 4;
begin
If (pipe_depth < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := pipe_depth;
End if;
Return (temp_fifo_depth);
end function funct_size_realign_fifo;
-- Constant Declarations --------------------------------------------
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant BTT_WIDTH : integer := C_BTT_USED;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant BTT_OF_ZERO : std_logic_vector(BTT_WIDTH-1 downto 0)
:= (others => '0');
Constant DRECTL_FIFO_DEPTH : integer := funct_size_realign_fifo(C_DRE_CNTL_FIFO_DEPTH);
Constant DRECTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
BTT_WIDTH + -- BTT field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant BTT_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := BTT_STRT_INDEX + BTT_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
Constant INCLUDE_DRE : boolean := (C_INCLUDE_DRE = 1 and
C_STREAM_DWIDTH <= 64 and
C_STREAM_DWIDTH >= 16);
Constant OMIT_DRE : boolean := not(INCLUDE_DRE);
-- Type Declarations --------------------------------------------
type TYPE_CMD_CNTL_SM is (
INIT,
LD_DRE_SCATTER_FIRST,
CHK_POP_FIRST ,
LD_DRE_SCATTER_SECOND,
CHK_POP_SECOND,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_cmdcntl_sm_state : TYPE_CMD_CNTL_SM := INIT;
Signal sig_cmdcntl_sm_state_ns : TYPE_CMD_CNTL_SM := INIT;
signal sig_sm_ld_dre_cmd_ns : std_logic := '0';
signal sig_sm_ld_dre_cmd : std_logic := '0';
signal sig_sm_ld_scatter_cmd_ns : std_logic := '0';
signal sig_sm_ld_scatter_cmd : std_logic := '0';
signal sig_sm_pop_cmd_fifo_ns : std_logic := '0';
signal sig_sm_pop_cmd_fifo : std_logic := '0';
signal sig_cmd_fifo_data_in : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_btt_reg : std_logic_vector(BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_cmd_cmplt_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_dre2wdc_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2wdc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_dre2wdc_tlast : std_logic := '0';
signal sig_dre2wdc_tvalid : std_logic := '0';
signal sig_wdc2dre_tready : std_logic := '0';
signal sig_tlast_err0r : std_logic := '0';
signal sig_dre_halted : std_logic := '0';
signal sig_strm2scatter_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_strm2scatter_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm2scatter_tlast : std_logic := '0';
signal sig_strm2scatter_tvalid : std_logic := '0';
signal sig_scatter2strm_tready : std_logic := '0';
signal sig_scatter2dre_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_scatter2dre_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2dre_tlast : std_logic := '0';
signal sig_scatter2dre_tvalid : std_logic := '0';
signal sig_dre2scatter_tready : std_logic := '0';
signal sig_scatter2dre_flush : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_scatter2dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_cmd_ready : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic;
signal sig_drc2scatter_btt : std_logic_vector(BTT_WIDTH-1 downto 0);
signal sig_drc2scatter_eof : std_logic;
signal sig_scatter2all_tlast_error : std_logic := '0';
signal sig_need_cmd_flush : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_strt_offset : std_logic := '0';
signal sig_output_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2sf_strt_offset : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Port connections
-- Input Stream Attachment
s2mm_strm_wready <= sig_scatter2strm_tready ;
sig_strm2scatter_tvalid <= s2mm_strm_wvalid ;
sig_strm2scatter_tdata <= s2mm_strm_wdata ;
sig_strm2scatter_tstrb <= s2mm_strm_wstrb ;
sig_strm2scatter_tlast <= s2mm_strm_wlast ;
-- Write Data Controller Stream Attachment
sig_wdc2dre_tready <= wdc2dre_wready ;
dre2wdc_wvalid <= sig_dre2wdc_tvalid ;
dre2wdc_wdata <= sig_dre2wdc_tdata ;
dre2wdc_wstrb <= sig_dre2wdc_tstrb ;
dre2wdc_wlast <= sig_dre2wdc_tlast ;
-- Status/Error flags
dre2all_tlast_error <= sig_tlast_err0r ;
dre2all_halted <= sig_dre_halted ;
-- Store and Forward Starting Offset Output
dre2sf_strt_offset <= sig_dre2sf_strt_offset ;
-------------------------------------------------------------
-- Internal logic
sig_dre_halted <= sig_dre_align_ready;
-------------------------------------------------------------
-- DRE Handshake signals
sig_dre_src_align <= sig_curr_src_align_reg ;
sig_dre_dest_align <= sig_curr_dest_align_reg;
sig_dre_use_autodest <= '0'; -- not used
sig_dre_flush <= '0'; -- not used
-------------------------------------------------------------------------
-------- Realigner Command FIFO and controls
-------------------------------------------------------------------------
-- Command Calculator Handshake
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_cmd_cmplt &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_btt &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto DEST_ALIGN_STRT_INDEX);
sig_curr_btt_reg <= sig_cmd_fifo_data_out((BTT_STRT_INDEX+BTT_WIDTH)-1 downto BTT_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_cmd_cmplt_reg <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => DRECTL_FIFO_WIDTH ,
C_DEPTH => DRECTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_sm_pop_cmd_fifo ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-------- DRE and Scatter Command Loader State Machine
-------------------------------------------------------------------------
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CMDCNTL_SM_COMBINATIONAL
--
-- Process Description:
-- Command Controller State Machine combinational implementation
-- The design is based on the premise that for every parent
-- command loaded into the S2MM, the Realigner can be loaded with
-- 1 or 2 commands spawned from it. The first command is used to
-- align ensuing transfers (in MMap space) to a max burst address
-- boundary. Then, if the parent command's BTT value is not satisfied
-- after the first command completes, a second command is generated
-- and loaded in the Realigner for the remaining BTT value. The
-- command complete bit in the Realigner command indicates if the
-- first command the final command or the second command (if needed)
-- is the final command,
-------------------------------------------------------------
CMDCNTL_SM_COMBINATIONAL : process (sig_cmdcntl_sm_state ,
sig_fifo_rd_cmd_valid ,
sig_dre_align_ready ,
sig_scatter2drc_cmd_ready ,
sig_need_cmd_flush ,
sig_curr_cmd_cmplt_reg ,
sig_curr_calc_error_reg
)
begin
-- SM Defaults
sig_cmdcntl_sm_state_ns <= INIT;
sig_sm_ld_dre_cmd_ns <= '0';
sig_sm_ld_scatter_cmd_ns <= '0';
sig_sm_pop_cmd_fifo_ns <= '0';
case sig_cmdcntl_sm_state is
--------------------------------------------
when INIT =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
--------------------------------------------
when LD_DRE_SCATTER_FIRST =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
End if;
--------------------------------------------
when CHK_POP_FIRST =>
If (sig_curr_cmd_cmplt_reg = '1') Then
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
Else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when LD_DRE_SCATTER_SECOND =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_need_cmd_flush = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_SECOND ;
sig_sm_pop_cmd_fifo_ns <= '1';
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when CHK_POP_SECOND =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST ;
--------------------------------------------
when ERROR_TRAP =>
sig_cmdcntl_sm_state_ns <= ERROR_TRAP ;
--------------------------------------------
when others =>
sig_cmdcntl_sm_state_ns <= INIT;
end case;
end process CMDCNTL_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMDCNTL_SM_REGISTERED
--
-- Process Description:
-- Command Controller State Machine registered implementation
--
-------------------------------------------------------------
CMDCNTL_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_cmdcntl_sm_state <= INIT;
sig_sm_ld_dre_cmd <= '0' ;
sig_sm_ld_scatter_cmd <= '0' ;
sig_sm_pop_cmd_fifo <= '0' ;
else
sig_cmdcntl_sm_state <= sig_cmdcntl_sm_state_ns ;
sig_sm_ld_dre_cmd <= sig_sm_ld_dre_cmd_ns ;
sig_sm_ld_scatter_cmd <= sig_sm_ld_scatter_cmd_ns ;
sig_sm_pop_cmd_fifo <= sig_sm_pop_cmd_fifo_ns ;
end if;
end if;
end process CMDCNTL_SM_REGISTERED;
-------------------------------------------------------------------------
-------- DRE Instance and controls
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE
--
-- If Generate Description:
-- Includes the instance for the DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE : if (INCLUDE_DRE) generate
signal lsig_eop_reg : std_logic := '0';
signal lsig_dre_load_beat : std_logic := '0';
signal lsig_dre_tlast_output_beat : std_logic := '0';
signal lsig_set_eop : std_logic := '0';
signal lsig_tlast_err_reg1 : std_logic := '0';
signal lsig_tlast_err_reg2 : std_logic := '0';
signal lsig_push_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pushreg_full : std_logic := '0';
signal lsig_pushreg_empty : std_logic := '0';
signal lsig_pull_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pullreg_full : std_logic := '0';
signal lsig_pullreg_empty : std_logic := '0';
signal lsig_pull_new_offset : std_logic := '0';
signal lsig_push_new_offset : std_logic := '0';
begin
------------------------------------------------------------
-- Instance: I_S2MM_DRE_BLOCK
--
-- Description:
-- Instance for the S2MM Data Realignment Engine (DRE)
--
------------------------------------------------------------
I_S2MM_DRE_BLOCK : entity axi_datamover_v5_1.axi_datamover_s2mm_dre
generic map (
C_DWIDTH => C_STREAM_DWIDTH ,
C_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH
)
port map (
-- Clock and Reset
dre_clk => primary_aclk ,
dre_rst => mmap_reset ,
-- Alignment Control (Independent from Stream Input timing)
dre_align_ready => sig_dre_align_ready ,
dre_align_valid => sig_sm_ld_dre_cmd ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_scatter2dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
-- Flush Control (Aligned to input Stream timing)
dre_flush => sig_scatter2dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_scatter2dre_tstrb ,
dre_in_tdata => sig_scatter2dre_tdata ,
dre_in_tlast => sig_scatter2dre_tlast ,
dre_in_tvalid => sig_scatter2dre_tvalid ,
dre_in_tready => sig_dre2scatter_tready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2wdc_tstrb ,
dre_out_tdata => sig_dre2wdc_tdata ,
dre_out_tlast => sig_dre2wdc_tlast ,
dre_out_tvalid => sig_dre2wdc_tvalid ,
dre_out_tready => sig_wdc2dre_tready
);
lsig_dre_load_beat <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready;
lsig_set_eop <= sig_scatter2drc_eop and
lsig_dre_load_beat ;
lsig_dre_tlast_output_beat <= sig_dre2wdc_tvalid and
sig_wdc2dre_tready and
sig_dre2wdc_tlast;
dre2wdc_eop <= lsig_dre_tlast_output_beat and
lsig_eop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG
--
-- Process Description:
-- Implements a flop for holding the EOP from the Scatter
-- Engine until the corresponding packet clears out of the DRE.
-- THis is used to transfer the EOP marker to the DRE output
-- stream without the need for the DRE to pass it through.
--
-------------------------------------------------------------
IMP_EOP_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(lsig_dre_tlast_output_beat = '1' and
lsig_set_eop = '0')) then
lsig_eop_reg <= '0';
elsif (lsig_set_eop = '1') then
lsig_eop_reg <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_EOP_REG;
-- Delay TLAST Error by 2 clocks to compensate for DRE minimum
-- delay of 2 clocks for the stream data.
sig_tlast_err0r <= lsig_tlast_err_reg2;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_DELAY
--
-- Process Description:
-- Implements a 2 clock delay to better align the TLAST
-- error detection with the Stream output data to the WDC
-- which has a minimum 2 clock delay through the DRE.
--
-------------------------------------------------------------
IMP_TLAST_ERR_DELAY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_tlast_err_reg1 <= '0';
lsig_tlast_err_reg2 <= '0';
else
lsig_tlast_err_reg1 <= sig_scatter2all_tlast_error;
lsig_tlast_err_reg2 <= lsig_tlast_err_reg1;
end if;
end if;
end process IMP_TLAST_ERR_DELAY;
-------------------------------------------------------------------------
-- Store and Forward Start Address Offset Registers Logic
-- Push-pull register is used to to time align the starting address
-- offset (ripped from the Realigner command via parsing) to DRE
-- TLAST output timing. The offset output of the pull register must
-- be valid on the first output databeat of the DRE to the Store and
-- Forward module.
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= lsig_pull_strt_offset_reg;
-- lsig_push_new_offset <= sig_dre_align_ready and
-- sig_gated_dre_align_valid ;
lsig_push_new_offset <= sig_sm_ld_dre_cmd ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the input register for holding the starting address
-- offset sent to the external Store and Forward functions.
--
-------------------------------------------------------------
IMP_PUSH_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
elsif (lsig_push_new_offset = '1') then
lsig_push_strt_offset_reg <= sig_curr_strt_offset_reg;
lsig_pushreg_full <= '1';
lsig_pushreg_empty <= '0';
elsif (lsig_pull_new_offset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PUSH_STRT_OFFSET_REG;
-- Pull the next offset (if one exists) into the pull register
-- when the DRE outputs a TLAST. If the pull register is empty
-- and the push register has an offset, then push the new value
-- into the pull register.
lsig_pull_new_offset <= (sig_dre2wdc_tlast and
sig_dre2wdc_tvalid and
sig_wdc2dre_tready) or
(lsig_pushreg_full and
lsig_pullreg_empty);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PULL_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the output register for holding the starting
-- address offset sent to the Store and Forward modul's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_PULL_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '1') then
lsig_pull_strt_offset_reg <= lsig_push_strt_offset_reg;
lsig_pullreg_full <= '1';
lsig_pullreg_empty <= '0';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '0') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PULL_STRT_OFFSET_REG;
end generate GEN_INCLUDE_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_DRE
--
-- If Generate Description:
-- Omits the DRE from the Re-aligner.
--
--
------------------------------------------------------------
GEN_OMIT_DRE : if (OMIT_DRE) generate
begin
-- DRE always ready
sig_dre_align_ready <= '1';
-- -- Let the Scatter engine control the Realigner command
-- -- flow.
-- sig_dre_align_ready <= sig_scatter2drc_cmd_ready;
-- Pass through signal connections
sig_dre2wdc_tstrb <= sig_scatter2dre_tstrb ;
sig_dre2wdc_tdata <= sig_scatter2dre_tdata ;
sig_dre2wdc_tlast <= sig_scatter2dre_tlast ;
sig_dre2wdc_tvalid <= sig_scatter2dre_tvalid ;
sig_dre2scatter_tready <= sig_wdc2dre_tready ;
dre2wdc_eop <= sig_scatter2drc_eop ;
-- Just pass TLAST Error through when no DRE is present
sig_tlast_err0r <= sig_scatter2all_tlast_error;
-------------------------------------------------------------------------
-------- Store and Forward Start Address Offset Register Logic
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= sig_output_strt_offset_reg;
sig_ld_strt_offset <= sig_sm_ld_dre_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STRT_OFFSET_OUTPUT
--
-- Process Description:
-- Implements the register for holding the starting address
-- offset sent to the S2MM Store and Forward module's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_STRT_OFFSET_OUTPUT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_output_strt_offset_reg <= (others => '0');
elsif (sig_ld_strt_offset = '1') then
sig_output_strt_offset_reg <= sig_curr_strt_offset_reg;
else
null; -- Hold Current State
end if;
end if;
end process IMP_STRT_OFFSET_OUTPUT;
end generate GEN_OMIT_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_SCATTER
--
-- If Generate Description:
-- This IfGen implements the Scatter function which is a pre-
-- processor for the S2MM DRE. The scatter function breaks up
-- a continous input stream of data into constituant parts
-- as described by a set of loaded commands that together
-- describe an entire input packet.
--
------------------------------------------------------------
GEN_INCLUDE_SCATTER : if (C_SUPPORT_SCATTER = 1) generate
begin
-- Load the Scatter Engine command when the DRE command
-- is loaded
-- sig_drc2scatter_push_cmd <= sig_dre_align_ready and
-- sig_gated_dre_align_valid;
sig_drc2scatter_push_cmd <= sig_sm_ld_scatter_cmd ;
-- Assign the new Bytes to Transfer (BTT) qualifier for the
-- Scatter Engine
sig_drc2scatter_btt <= sig_curr_btt_reg;
-- Assign the new End of Frame (EOF) qualifier for the
-- Scatter Engine
sig_drc2scatter_eof <= sig_curr_eof_reg;
------------------------------------------------------------
-- Instance: I_S2MM_SCATTER
--
-- Description:
-- Instance for the Scatter Engine. This block breaks up a
-- input stream per commands loaded.
--
------------------------------------------------------------
I_S2MM_SCATTER : entity axi_datamover_v5_1.axi_datamover_s2mm_scatter
generic map (
C_ENABLE_INDET_BTT => C_ENABLE_INDET_BTT ,
C_DRE_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_BTT_USED => BTT_WIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock input & Reset input
primary_aclk => primary_aclk ,
mmap_reset => mmap_reset ,
-- DRE Realign Controller I/O ----------------------------
scatter2drc_cmd_ready => sig_scatter2drc_cmd_ready ,
drc2scatter_push_cmd => sig_drc2scatter_push_cmd ,
drc2scatter_btt => sig_drc2scatter_btt ,
drc2scatter_eof => sig_drc2scatter_eof ,
-- DRE Source Alignment -----------------------------------
scatter2drc_src_align => sig_scatter2dre_src_align ,
-- AXI Slave Stream In -----------------------------------
s2mm_strm_tready => sig_scatter2strm_tready ,
s2mm_strm_tvalid => sig_strm2scatter_tvalid ,
s2mm_strm_tdata => sig_strm2scatter_tdata ,
s2mm_strm_tstrb => sig_strm2scatter_tstrb ,
s2mm_strm_tlast => sig_strm2scatter_tlast ,
-- Stream Out to S2MM DRE ---------------------------------
drc2scatter_tready => sig_dre2scatter_tready ,
scatter2drc_tvalid => sig_scatter2dre_tvalid ,
scatter2drc_tdata => sig_scatter2dre_tdata ,
scatter2drc_tstrb => sig_scatter2dre_tstrb ,
scatter2drc_tlast => sig_scatter2dre_tlast ,
scatter2drc_flush => sig_scatter2dre_flush ,
scatter2drc_eop => sig_scatter2drc_eop ,
-- Premature TLAST assertion error flag
scatter2drc_tlast_error => sig_scatter2all_tlast_error
);
end generate GEN_INCLUDE_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_SCATTER
--
-- If Generate Description:
-- This IfGen omits the Scatter pre-processor.
--
--
------------------------------------------------------------
GEN_OMIT_SCATTER : if (C_SUPPORT_SCATTER = 0) generate
begin
-- Just housekeep the signaling
sig_scatter2drc_cmd_ready <= '1' ;
sig_scatter2drc_eop <= sig_strm2scatter_tlast ;
sig_scatter2dre_src_align <= sig_dre_src_align ;
sig_scatter2all_tlast_error <= '0' ;
sig_scatter2dre_flush <= sig_dre_flush ;
sig_scatter2dre_tstrb <= sig_strm2scatter_tstrb ;
sig_scatter2dre_tdata <= sig_strm2scatter_tdata ;
sig_scatter2dre_tlast <= sig_strm2scatter_tlast ;
sig_scatter2dre_tvalid <= sig_strm2scatter_tvalid ;
sig_scatter2strm_tready <= sig_dre2scatter_tready ;
end generate GEN_OMIT_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omit and special logic for Indeterminate BTT support.
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_need_cmd_flush <= '0' ; -- not needed without Indeterminate BTT
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Include logic for the case when Indeterminate BTT is
-- included as part of the S2MM. In this mode, the actual
-- length of input stream packets is not known when the S2MM
-- is loaded with a transfer command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
signal lsig_clr_cmd_flush : std_logic := '0';
signal lsig_set_cmd_flush : std_logic := '0';
signal lsig_cmd_set_fetch_pause : std_logic := '0';
signal lsig_cmd_clr_fetch_pause : std_logic := '0';
signal lsig_cmd_fetch_pause : std_logic := '0';
begin
lsig_cmd_set_fetch_pause <= sig_drc2scatter_push_cmd and
not(sig_curr_cmd_cmplt_reg) and
not(sig_need_cmd_flush);
lsig_cmd_clr_fetch_pause <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2dre_tlast;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FETCH_PAUSE
--
-- Process Description:
-- Implements the flop for the flag that causes the command
-- queue manager to pause fetching the next command if the
-- current command does not have the command complete bit set.
-- The pause remains set until the associated TLAST for the
-- command is output from the Scatter Engine. If the Tlast is
-- also accompanied by a EOP and the pause is set, then the
-- ensuing command (which will have the cmd cmplt bit set) must
-- be flushed from the queue and not loaded into the Scatter
-- Engine or DRE, This is normally associated with indeterminate
-- packets that are actually shorter than the intial align to
-- max burst child command sent to the Realigner, The next loaded
-- child command is to finish the remainder of the indeterminate
-- packet up to the full BTT value in the original parent command.
-- This child command becomes stranded in the Realigner command fifo
-- and has to be flushed.
--
-------------------------------------------------------------
IMP_CMD_FETCH_PAUSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_cmd_clr_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '0';
elsif (lsig_cmd_set_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FETCH_PAUSE;
-- Clear the flush needed flag when the command with the command
-- complete marker is popped off of the command queue.
lsig_clr_cmd_flush <= sig_need_cmd_flush and
sig_sm_pop_cmd_fifo;
-- The command queue has to be flushed if the stream EOP marker
-- is transfered out of the Scatter Engine when the corresponding
-- command being executed does not have the command complete
-- marker set.
lsig_set_cmd_flush <= lsig_cmd_fetch_pause and
sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2drc_eop;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLUSH_FLOP
--
-- Process Description:
-- Implements the flop for holding the command flush flag.
-- This is only needed in Indeterminate BTT mode.
--
-------------------------------------------------------------
IMP_CMD_FLUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_cmd_flush = '1') then
sig_need_cmd_flush <= '0';
elsif (lsig_set_cmd_flush = '1') then
sig_need_cmd_flush <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FLUSH_FLOP;
end generate GEN_ENABLE_INDET_BTT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_realign.vhd
--
-- Description:
-- This file implements the S2MM Data Realignment module. THe S2MM direction is
-- more complex than the MM2S direction since the DRE needs to be upstream from
-- the Write Data Controller. This requires the S2MM DRE to be running 2 to
-- 3 clocks ahead of the Write Data controller to minimize/eliminate xfer
-- bubble insertion.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_fifo;
use axi_datamover_v5_1.axi_datamover_s2mm_dre;
use axi_datamover_v5_1.axi_datamover_s2mm_scatter;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_realign is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the IBTT Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_INCLUDE_DRE : Integer range 0 to 1 := 1;
-- Includes/Omits the S2MM DRE
-- 0 = Omit
-- 1 = Include
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal command queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_SUPPORT_SCATTER : Integer range 0 to 1 := 1;
-- Includes/Omits the Scatter functionality
-- 0 = omit
-- 1 = include
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_BTT_USED : Integer range 8 to 23 := 16;
-- Indicates the width of the input command BTT that is actually
-- used
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Input and Output Stream Data ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the input command Tag port
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 ;
-- Sets the width of the Store and Forward Start offset ports
C_FAMILY : String := "virtex7"
-- specifies the target FPGA familiy
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------------
-- Write Data Controller or IBTT Indeterminate BTT I/O -------------------------
--
wdc2dre_wready : In std_logic; --
-- Write READY input from WDC or SF --
--
dre2wdc_wvalid : Out std_logic; --
-- Write VALID output to WDC or SF --
--
dre2wdc_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wlast : Out std_logic; --
-- Write LAST output to WDC or SF --
--
dre2wdc_eop : Out std_logic; --
-- End of Packet indicator for the Stream input to WDC or SF --
--------------------------------------------------------------------------------
-- Starting offset output for the Store and Forward Modules -------------------
--
dre2sf_strt_offset : Out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Command Calculator Interface ---------------------------------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2dre_cmd_cmplt : In std_logic; --
-- The last tranfer command of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- Premature TLAST assertion error flag -----------------------------
--
dre2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the DRE detected --
-- a Early/Late TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------
-- DRE Halted Status ------------------------------------------------
--
dre2all_halted : Out std_logic --
-- When asserted, this indicates the DRE has satisfied --
-- all pending transfers queued by the command calculator --
-- and is halted. --
---------------------------------------------------------------------
);
end entity axi_datamover_s2mm_realign;
architecture implementation of axi_datamover_s2mm_realign is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations --------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_realign_fifo
--
-- Function Description:
-- Assures that the Realigner cmd fifo depth is at least 4 deep else it
-- is equal to the pipe depth.
--
-------------------------------------------------------------------
function funct_size_realign_fifo (pipe_depth : integer) return integer is
Variable temp_fifo_depth : Integer := 4;
begin
If (pipe_depth < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := pipe_depth;
End if;
Return (temp_fifo_depth);
end function funct_size_realign_fifo;
-- Constant Declarations --------------------------------------------
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant BTT_WIDTH : integer := C_BTT_USED;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant BTT_OF_ZERO : std_logic_vector(BTT_WIDTH-1 downto 0)
:= (others => '0');
Constant DRECTL_FIFO_DEPTH : integer := funct_size_realign_fifo(C_DRE_CNTL_FIFO_DEPTH);
Constant DRECTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
BTT_WIDTH + -- BTT field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant BTT_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := BTT_STRT_INDEX + BTT_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
Constant INCLUDE_DRE : boolean := (C_INCLUDE_DRE = 1 and
C_STREAM_DWIDTH <= 64 and
C_STREAM_DWIDTH >= 16);
Constant OMIT_DRE : boolean := not(INCLUDE_DRE);
-- Type Declarations --------------------------------------------
type TYPE_CMD_CNTL_SM is (
INIT,
LD_DRE_SCATTER_FIRST,
CHK_POP_FIRST ,
LD_DRE_SCATTER_SECOND,
CHK_POP_SECOND,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_cmdcntl_sm_state : TYPE_CMD_CNTL_SM := INIT;
Signal sig_cmdcntl_sm_state_ns : TYPE_CMD_CNTL_SM := INIT;
signal sig_sm_ld_dre_cmd_ns : std_logic := '0';
signal sig_sm_ld_dre_cmd : std_logic := '0';
signal sig_sm_ld_scatter_cmd_ns : std_logic := '0';
signal sig_sm_ld_scatter_cmd : std_logic := '0';
signal sig_sm_pop_cmd_fifo_ns : std_logic := '0';
signal sig_sm_pop_cmd_fifo : std_logic := '0';
signal sig_cmd_fifo_data_in : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_btt_reg : std_logic_vector(BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_cmd_cmplt_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_dre2wdc_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2wdc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_dre2wdc_tlast : std_logic := '0';
signal sig_dre2wdc_tvalid : std_logic := '0';
signal sig_wdc2dre_tready : std_logic := '0';
signal sig_tlast_err0r : std_logic := '0';
signal sig_dre_halted : std_logic := '0';
signal sig_strm2scatter_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_strm2scatter_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm2scatter_tlast : std_logic := '0';
signal sig_strm2scatter_tvalid : std_logic := '0';
signal sig_scatter2strm_tready : std_logic := '0';
signal sig_scatter2dre_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_scatter2dre_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2dre_tlast : std_logic := '0';
signal sig_scatter2dre_tvalid : std_logic := '0';
signal sig_dre2scatter_tready : std_logic := '0';
signal sig_scatter2dre_flush : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_scatter2dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_cmd_ready : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic;
signal sig_drc2scatter_btt : std_logic_vector(BTT_WIDTH-1 downto 0);
signal sig_drc2scatter_eof : std_logic;
signal sig_scatter2all_tlast_error : std_logic := '0';
signal sig_need_cmd_flush : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_strt_offset : std_logic := '0';
signal sig_output_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2sf_strt_offset : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Port connections
-- Input Stream Attachment
s2mm_strm_wready <= sig_scatter2strm_tready ;
sig_strm2scatter_tvalid <= s2mm_strm_wvalid ;
sig_strm2scatter_tdata <= s2mm_strm_wdata ;
sig_strm2scatter_tstrb <= s2mm_strm_wstrb ;
sig_strm2scatter_tlast <= s2mm_strm_wlast ;
-- Write Data Controller Stream Attachment
sig_wdc2dre_tready <= wdc2dre_wready ;
dre2wdc_wvalid <= sig_dre2wdc_tvalid ;
dre2wdc_wdata <= sig_dre2wdc_tdata ;
dre2wdc_wstrb <= sig_dre2wdc_tstrb ;
dre2wdc_wlast <= sig_dre2wdc_tlast ;
-- Status/Error flags
dre2all_tlast_error <= sig_tlast_err0r ;
dre2all_halted <= sig_dre_halted ;
-- Store and Forward Starting Offset Output
dre2sf_strt_offset <= sig_dre2sf_strt_offset ;
-------------------------------------------------------------
-- Internal logic
sig_dre_halted <= sig_dre_align_ready;
-------------------------------------------------------------
-- DRE Handshake signals
sig_dre_src_align <= sig_curr_src_align_reg ;
sig_dre_dest_align <= sig_curr_dest_align_reg;
sig_dre_use_autodest <= '0'; -- not used
sig_dre_flush <= '0'; -- not used
-------------------------------------------------------------------------
-------- Realigner Command FIFO and controls
-------------------------------------------------------------------------
-- Command Calculator Handshake
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_cmd_cmplt &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_btt &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto DEST_ALIGN_STRT_INDEX);
sig_curr_btt_reg <= sig_cmd_fifo_data_out((BTT_STRT_INDEX+BTT_WIDTH)-1 downto BTT_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_cmd_cmplt_reg <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => DRECTL_FIFO_WIDTH ,
C_DEPTH => DRECTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_sm_pop_cmd_fifo ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-------- DRE and Scatter Command Loader State Machine
-------------------------------------------------------------------------
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CMDCNTL_SM_COMBINATIONAL
--
-- Process Description:
-- Command Controller State Machine combinational implementation
-- The design is based on the premise that for every parent
-- command loaded into the S2MM, the Realigner can be loaded with
-- 1 or 2 commands spawned from it. The first command is used to
-- align ensuing transfers (in MMap space) to a max burst address
-- boundary. Then, if the parent command's BTT value is not satisfied
-- after the first command completes, a second command is generated
-- and loaded in the Realigner for the remaining BTT value. The
-- command complete bit in the Realigner command indicates if the
-- first command the final command or the second command (if needed)
-- is the final command,
-------------------------------------------------------------
CMDCNTL_SM_COMBINATIONAL : process (sig_cmdcntl_sm_state ,
sig_fifo_rd_cmd_valid ,
sig_dre_align_ready ,
sig_scatter2drc_cmd_ready ,
sig_need_cmd_flush ,
sig_curr_cmd_cmplt_reg ,
sig_curr_calc_error_reg
)
begin
-- SM Defaults
sig_cmdcntl_sm_state_ns <= INIT;
sig_sm_ld_dre_cmd_ns <= '0';
sig_sm_ld_scatter_cmd_ns <= '0';
sig_sm_pop_cmd_fifo_ns <= '0';
case sig_cmdcntl_sm_state is
--------------------------------------------
when INIT =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
--------------------------------------------
when LD_DRE_SCATTER_FIRST =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
End if;
--------------------------------------------
when CHK_POP_FIRST =>
If (sig_curr_cmd_cmplt_reg = '1') Then
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
Else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when LD_DRE_SCATTER_SECOND =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_need_cmd_flush = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_SECOND ;
sig_sm_pop_cmd_fifo_ns <= '1';
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when CHK_POP_SECOND =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST ;
--------------------------------------------
when ERROR_TRAP =>
sig_cmdcntl_sm_state_ns <= ERROR_TRAP ;
--------------------------------------------
when others =>
sig_cmdcntl_sm_state_ns <= INIT;
end case;
end process CMDCNTL_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMDCNTL_SM_REGISTERED
--
-- Process Description:
-- Command Controller State Machine registered implementation
--
-------------------------------------------------------------
CMDCNTL_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_cmdcntl_sm_state <= INIT;
sig_sm_ld_dre_cmd <= '0' ;
sig_sm_ld_scatter_cmd <= '0' ;
sig_sm_pop_cmd_fifo <= '0' ;
else
sig_cmdcntl_sm_state <= sig_cmdcntl_sm_state_ns ;
sig_sm_ld_dre_cmd <= sig_sm_ld_dre_cmd_ns ;
sig_sm_ld_scatter_cmd <= sig_sm_ld_scatter_cmd_ns ;
sig_sm_pop_cmd_fifo <= sig_sm_pop_cmd_fifo_ns ;
end if;
end if;
end process CMDCNTL_SM_REGISTERED;
-------------------------------------------------------------------------
-------- DRE Instance and controls
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE
--
-- If Generate Description:
-- Includes the instance for the DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE : if (INCLUDE_DRE) generate
signal lsig_eop_reg : std_logic := '0';
signal lsig_dre_load_beat : std_logic := '0';
signal lsig_dre_tlast_output_beat : std_logic := '0';
signal lsig_set_eop : std_logic := '0';
signal lsig_tlast_err_reg1 : std_logic := '0';
signal lsig_tlast_err_reg2 : std_logic := '0';
signal lsig_push_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pushreg_full : std_logic := '0';
signal lsig_pushreg_empty : std_logic := '0';
signal lsig_pull_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pullreg_full : std_logic := '0';
signal lsig_pullreg_empty : std_logic := '0';
signal lsig_pull_new_offset : std_logic := '0';
signal lsig_push_new_offset : std_logic := '0';
begin
------------------------------------------------------------
-- Instance: I_S2MM_DRE_BLOCK
--
-- Description:
-- Instance for the S2MM Data Realignment Engine (DRE)
--
------------------------------------------------------------
I_S2MM_DRE_BLOCK : entity axi_datamover_v5_1.axi_datamover_s2mm_dre
generic map (
C_DWIDTH => C_STREAM_DWIDTH ,
C_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH
)
port map (
-- Clock and Reset
dre_clk => primary_aclk ,
dre_rst => mmap_reset ,
-- Alignment Control (Independent from Stream Input timing)
dre_align_ready => sig_dre_align_ready ,
dre_align_valid => sig_sm_ld_dre_cmd ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_scatter2dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
-- Flush Control (Aligned to input Stream timing)
dre_flush => sig_scatter2dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_scatter2dre_tstrb ,
dre_in_tdata => sig_scatter2dre_tdata ,
dre_in_tlast => sig_scatter2dre_tlast ,
dre_in_tvalid => sig_scatter2dre_tvalid ,
dre_in_tready => sig_dre2scatter_tready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2wdc_tstrb ,
dre_out_tdata => sig_dre2wdc_tdata ,
dre_out_tlast => sig_dre2wdc_tlast ,
dre_out_tvalid => sig_dre2wdc_tvalid ,
dre_out_tready => sig_wdc2dre_tready
);
lsig_dre_load_beat <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready;
lsig_set_eop <= sig_scatter2drc_eop and
lsig_dre_load_beat ;
lsig_dre_tlast_output_beat <= sig_dre2wdc_tvalid and
sig_wdc2dre_tready and
sig_dre2wdc_tlast;
dre2wdc_eop <= lsig_dre_tlast_output_beat and
lsig_eop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG
--
-- Process Description:
-- Implements a flop for holding the EOP from the Scatter
-- Engine until the corresponding packet clears out of the DRE.
-- THis is used to transfer the EOP marker to the DRE output
-- stream without the need for the DRE to pass it through.
--
-------------------------------------------------------------
IMP_EOP_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(lsig_dre_tlast_output_beat = '1' and
lsig_set_eop = '0')) then
lsig_eop_reg <= '0';
elsif (lsig_set_eop = '1') then
lsig_eop_reg <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_EOP_REG;
-- Delay TLAST Error by 2 clocks to compensate for DRE minimum
-- delay of 2 clocks for the stream data.
sig_tlast_err0r <= lsig_tlast_err_reg2;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_DELAY
--
-- Process Description:
-- Implements a 2 clock delay to better align the TLAST
-- error detection with the Stream output data to the WDC
-- which has a minimum 2 clock delay through the DRE.
--
-------------------------------------------------------------
IMP_TLAST_ERR_DELAY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_tlast_err_reg1 <= '0';
lsig_tlast_err_reg2 <= '0';
else
lsig_tlast_err_reg1 <= sig_scatter2all_tlast_error;
lsig_tlast_err_reg2 <= lsig_tlast_err_reg1;
end if;
end if;
end process IMP_TLAST_ERR_DELAY;
-------------------------------------------------------------------------
-- Store and Forward Start Address Offset Registers Logic
-- Push-pull register is used to to time align the starting address
-- offset (ripped from the Realigner command via parsing) to DRE
-- TLAST output timing. The offset output of the pull register must
-- be valid on the first output databeat of the DRE to the Store and
-- Forward module.
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= lsig_pull_strt_offset_reg;
-- lsig_push_new_offset <= sig_dre_align_ready and
-- sig_gated_dre_align_valid ;
lsig_push_new_offset <= sig_sm_ld_dre_cmd ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the input register for holding the starting address
-- offset sent to the external Store and Forward functions.
--
-------------------------------------------------------------
IMP_PUSH_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
elsif (lsig_push_new_offset = '1') then
lsig_push_strt_offset_reg <= sig_curr_strt_offset_reg;
lsig_pushreg_full <= '1';
lsig_pushreg_empty <= '0';
elsif (lsig_pull_new_offset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PUSH_STRT_OFFSET_REG;
-- Pull the next offset (if one exists) into the pull register
-- when the DRE outputs a TLAST. If the pull register is empty
-- and the push register has an offset, then push the new value
-- into the pull register.
lsig_pull_new_offset <= (sig_dre2wdc_tlast and
sig_dre2wdc_tvalid and
sig_wdc2dre_tready) or
(lsig_pushreg_full and
lsig_pullreg_empty);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PULL_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the output register for holding the starting
-- address offset sent to the Store and Forward modul's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_PULL_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '1') then
lsig_pull_strt_offset_reg <= lsig_push_strt_offset_reg;
lsig_pullreg_full <= '1';
lsig_pullreg_empty <= '0';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '0') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PULL_STRT_OFFSET_REG;
end generate GEN_INCLUDE_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_DRE
--
-- If Generate Description:
-- Omits the DRE from the Re-aligner.
--
--
------------------------------------------------------------
GEN_OMIT_DRE : if (OMIT_DRE) generate
begin
-- DRE always ready
sig_dre_align_ready <= '1';
-- -- Let the Scatter engine control the Realigner command
-- -- flow.
-- sig_dre_align_ready <= sig_scatter2drc_cmd_ready;
-- Pass through signal connections
sig_dre2wdc_tstrb <= sig_scatter2dre_tstrb ;
sig_dre2wdc_tdata <= sig_scatter2dre_tdata ;
sig_dre2wdc_tlast <= sig_scatter2dre_tlast ;
sig_dre2wdc_tvalid <= sig_scatter2dre_tvalid ;
sig_dre2scatter_tready <= sig_wdc2dre_tready ;
dre2wdc_eop <= sig_scatter2drc_eop ;
-- Just pass TLAST Error through when no DRE is present
sig_tlast_err0r <= sig_scatter2all_tlast_error;
-------------------------------------------------------------------------
-------- Store and Forward Start Address Offset Register Logic
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= sig_output_strt_offset_reg;
sig_ld_strt_offset <= sig_sm_ld_dre_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STRT_OFFSET_OUTPUT
--
-- Process Description:
-- Implements the register for holding the starting address
-- offset sent to the S2MM Store and Forward module's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_STRT_OFFSET_OUTPUT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_output_strt_offset_reg <= (others => '0');
elsif (sig_ld_strt_offset = '1') then
sig_output_strt_offset_reg <= sig_curr_strt_offset_reg;
else
null; -- Hold Current State
end if;
end if;
end process IMP_STRT_OFFSET_OUTPUT;
end generate GEN_OMIT_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_SCATTER
--
-- If Generate Description:
-- This IfGen implements the Scatter function which is a pre-
-- processor for the S2MM DRE. The scatter function breaks up
-- a continous input stream of data into constituant parts
-- as described by a set of loaded commands that together
-- describe an entire input packet.
--
------------------------------------------------------------
GEN_INCLUDE_SCATTER : if (C_SUPPORT_SCATTER = 1) generate
begin
-- Load the Scatter Engine command when the DRE command
-- is loaded
-- sig_drc2scatter_push_cmd <= sig_dre_align_ready and
-- sig_gated_dre_align_valid;
sig_drc2scatter_push_cmd <= sig_sm_ld_scatter_cmd ;
-- Assign the new Bytes to Transfer (BTT) qualifier for the
-- Scatter Engine
sig_drc2scatter_btt <= sig_curr_btt_reg;
-- Assign the new End of Frame (EOF) qualifier for the
-- Scatter Engine
sig_drc2scatter_eof <= sig_curr_eof_reg;
------------------------------------------------------------
-- Instance: I_S2MM_SCATTER
--
-- Description:
-- Instance for the Scatter Engine. This block breaks up a
-- input stream per commands loaded.
--
------------------------------------------------------------
I_S2MM_SCATTER : entity axi_datamover_v5_1.axi_datamover_s2mm_scatter
generic map (
C_ENABLE_INDET_BTT => C_ENABLE_INDET_BTT ,
C_DRE_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_BTT_USED => BTT_WIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock input & Reset input
primary_aclk => primary_aclk ,
mmap_reset => mmap_reset ,
-- DRE Realign Controller I/O ----------------------------
scatter2drc_cmd_ready => sig_scatter2drc_cmd_ready ,
drc2scatter_push_cmd => sig_drc2scatter_push_cmd ,
drc2scatter_btt => sig_drc2scatter_btt ,
drc2scatter_eof => sig_drc2scatter_eof ,
-- DRE Source Alignment -----------------------------------
scatter2drc_src_align => sig_scatter2dre_src_align ,
-- AXI Slave Stream In -----------------------------------
s2mm_strm_tready => sig_scatter2strm_tready ,
s2mm_strm_tvalid => sig_strm2scatter_tvalid ,
s2mm_strm_tdata => sig_strm2scatter_tdata ,
s2mm_strm_tstrb => sig_strm2scatter_tstrb ,
s2mm_strm_tlast => sig_strm2scatter_tlast ,
-- Stream Out to S2MM DRE ---------------------------------
drc2scatter_tready => sig_dre2scatter_tready ,
scatter2drc_tvalid => sig_scatter2dre_tvalid ,
scatter2drc_tdata => sig_scatter2dre_tdata ,
scatter2drc_tstrb => sig_scatter2dre_tstrb ,
scatter2drc_tlast => sig_scatter2dre_tlast ,
scatter2drc_flush => sig_scatter2dre_flush ,
scatter2drc_eop => sig_scatter2drc_eop ,
-- Premature TLAST assertion error flag
scatter2drc_tlast_error => sig_scatter2all_tlast_error
);
end generate GEN_INCLUDE_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_SCATTER
--
-- If Generate Description:
-- This IfGen omits the Scatter pre-processor.
--
--
------------------------------------------------------------
GEN_OMIT_SCATTER : if (C_SUPPORT_SCATTER = 0) generate
begin
-- Just housekeep the signaling
sig_scatter2drc_cmd_ready <= '1' ;
sig_scatter2drc_eop <= sig_strm2scatter_tlast ;
sig_scatter2dre_src_align <= sig_dre_src_align ;
sig_scatter2all_tlast_error <= '0' ;
sig_scatter2dre_flush <= sig_dre_flush ;
sig_scatter2dre_tstrb <= sig_strm2scatter_tstrb ;
sig_scatter2dre_tdata <= sig_strm2scatter_tdata ;
sig_scatter2dre_tlast <= sig_strm2scatter_tlast ;
sig_scatter2dre_tvalid <= sig_strm2scatter_tvalid ;
sig_scatter2strm_tready <= sig_dre2scatter_tready ;
end generate GEN_OMIT_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omit and special logic for Indeterminate BTT support.
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_need_cmd_flush <= '0' ; -- not needed without Indeterminate BTT
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Include logic for the case when Indeterminate BTT is
-- included as part of the S2MM. In this mode, the actual
-- length of input stream packets is not known when the S2MM
-- is loaded with a transfer command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
signal lsig_clr_cmd_flush : std_logic := '0';
signal lsig_set_cmd_flush : std_logic := '0';
signal lsig_cmd_set_fetch_pause : std_logic := '0';
signal lsig_cmd_clr_fetch_pause : std_logic := '0';
signal lsig_cmd_fetch_pause : std_logic := '0';
begin
lsig_cmd_set_fetch_pause <= sig_drc2scatter_push_cmd and
not(sig_curr_cmd_cmplt_reg) and
not(sig_need_cmd_flush);
lsig_cmd_clr_fetch_pause <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2dre_tlast;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FETCH_PAUSE
--
-- Process Description:
-- Implements the flop for the flag that causes the command
-- queue manager to pause fetching the next command if the
-- current command does not have the command complete bit set.
-- The pause remains set until the associated TLAST for the
-- command is output from the Scatter Engine. If the Tlast is
-- also accompanied by a EOP and the pause is set, then the
-- ensuing command (which will have the cmd cmplt bit set) must
-- be flushed from the queue and not loaded into the Scatter
-- Engine or DRE, This is normally associated with indeterminate
-- packets that are actually shorter than the intial align to
-- max burst child command sent to the Realigner, The next loaded
-- child command is to finish the remainder of the indeterminate
-- packet up to the full BTT value in the original parent command.
-- This child command becomes stranded in the Realigner command fifo
-- and has to be flushed.
--
-------------------------------------------------------------
IMP_CMD_FETCH_PAUSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_cmd_clr_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '0';
elsif (lsig_cmd_set_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FETCH_PAUSE;
-- Clear the flush needed flag when the command with the command
-- complete marker is popped off of the command queue.
lsig_clr_cmd_flush <= sig_need_cmd_flush and
sig_sm_pop_cmd_fifo;
-- The command queue has to be flushed if the stream EOP marker
-- is transfered out of the Scatter Engine when the corresponding
-- command being executed does not have the command complete
-- marker set.
lsig_set_cmd_flush <= lsig_cmd_fetch_pause and
sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2drc_eop;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLUSH_FLOP
--
-- Process Description:
-- Implements the flop for holding the command flush flag.
-- This is only needed in Indeterminate BTT mode.
--
-------------------------------------------------------------
IMP_CMD_FLUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_cmd_flush = '1') then
sig_need_cmd_flush <= '0';
elsif (lsig_set_cmd_flush = '1') then
sig_need_cmd_flush <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FLUSH_FLOP;
end generate GEN_ENABLE_INDET_BTT;
end implementation;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pt_pci_master
-- File: pt_pci_master.vhd
-- Author: Nils Johan Wessman, Aeroflex Gaisler
-- Description: PCI Testbench Master
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
library gaisler;
use gaisler.pt_pkg.all;
library grlib;
use grlib.stdlib.xorv;
use grlib.stdlib.tost;
use grlib.testlib.print;
entity pt_pci_master is
generic (
slot : integer := 0;
tval : time := 7 ns);
port (
-- PCI signals
pciin : in pci_type;
pciout : out pci_type;
-- Debug interface signals
dbgi : in pt_pci_master_in_type;
dbgo : out pt_pci_master_out_type
);
end pt_pci_master;
architecture behav of pt_pci_master is
-- NEW =>
type access_element_type;
type access_element_ptr is access access_element_type;
type access_element_type is record
acc : pt_pci_access_type;
nxt : access_element_ptr;
end record;
constant idle_acc : pt_pci_access_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'),
0, 0, 0, 0, false, false, false, false, 0, 0);
signal pci_core : pt_pci_master_in_type;
signal core_pci : pt_pci_master_out_type;
-- Description: Insert a access at the "tail" of the linked list of accesses
procedure add_acc (
variable acc_head : inout access_element_ptr;
variable acc_tail : inout access_element_ptr;
signal acc : in pt_pci_access_type) is
variable elem : access_element_ptr;
begin -- insert_access
elem := acc_tail;
if elem /= NULL then
elem.nxt := new access_element_type'(acc, NULL);
acc_tail := elem.nxt;
else
acc_head := new access_element_type'(acc, NULL);
acc_tail := acc_head;
end if;
end add_acc;
-- Description: Get the access at the "head" of the linked list of accesses
-- and remove if from the list
procedure pop_acc (
variable acc_head : inout access_element_ptr;
variable acc_tail : inout access_element_ptr;
signal acc : out pt_pci_access_type;
variable found : out boolean) is
variable elem : access_element_ptr;
begin -- pop_access
elem := acc_head;
if elem /= NULL then
found := true;
acc <= elem.acc;
if elem = acc_tail then
acc_head := NULL;
acc_tail := NULL;
else
acc_head := elem.nxt;
end if;
deallocate(elem);
else
found := false;
acc <= idle_acc;
end if;
end pop_acc;
-- Description: Searches the list for a result to a particular id.
procedure get_res (
variable res_head : inout access_element_ptr;
variable res_tail : inout access_element_ptr;
signal accin : in pt_pci_access_type;
signal acc : out pt_pci_access_type;
variable found : out boolean) is
variable elem, prev : access_element_ptr;
variable lfound : boolean := false;
begin -- get_result
prev := res_head;
elem := res_head;
while elem /= NULL and not lfound loop
-- Check if result is a match for id
if accin.id = elem.acc.id then
acc <= elem.acc;
lfound := true;
if prev = res_head then
res_head := elem.nxt;
else
prev.nxt := elem.nxt;
end if;
if elem = res_tail then
res_tail := NULL;
end if;
deallocate(elem);
end if;
if not lfound then
prev := elem;
elem := elem.nxt;
end if;
end loop;
if lfound then found := true;
else found := false; acc <= idle_acc; end if;
end get_res;
-- Description:
procedure rm_acc (
variable acc_head : inout access_element_ptr;
variable acc_tail : inout access_element_ptr;
signal acc : in pt_pci_access_type;
constant rmall : in boolean )is
variable elem, prev : access_element_ptr;
variable lfound : boolean := false;
begin -- rm_access
prev := acc_head;
elem := acc_head;
while elem /= NULL and not lfound loop
if rmall = true then
prev := elem;
elem := elem.nxt;
deallocate(prev);
else
if acc.addr = elem.acc.addr then
if prev = acc_head then
acc_head := elem.nxt;
else
prev.nxt := elem.nxt;
end if;
if elem = acc_tail then
acc_tail := NULL;
end if;
deallocate(elem);
lfound := true;
else
prev := elem;
elem := elem.nxt;
end if;
end if;
end loop;
if rmall = true then
acc_head := NULL;
acc_tail := NULL;
end if;
end rm_acc;
-- <= NEW
type state_type is(idle, addr, data, turn, active, done);
type reg_type is record
state : state_type;
pcien : std_logic_vector(3 downto 0);
perren : std_logic_vector(1 downto 0);
read : std_logic;
grant : std_logic;
perr_ad : std_logic_vector(31 downto 0);
perr_cbe : std_logic_vector(3 downto 0);
devsel_timeout : integer range 0 to 3;
pci : pci_type;
acc : pt_pci_access_type;
parerr : std_logic;
end record;
signal r,rin : reg_type;
begin
-- NEW =>
core_acc : process
variable acc_head : access_element_ptr := NULL;
variable acc_tail : access_element_ptr := NULL;
variable res_head : access_element_ptr := NULL;
variable res_tail : access_element_ptr := NULL;
variable res_to_find : pt_pci_access_type := idle_acc;
variable found : boolean;
begin
if pci_core.req /= '1' and dbgi.req /= '1' then
wait until pci_core.req = '1' or dbgi.req = '1';
end if;
if dbgi.req = '1' then
dbgo.res_found <= '0';
if dbgi.add = true then
add_acc(acc_head, acc_tail, dbgi.acc);
elsif dbgi.remove = true then
rm_acc(acc_head, acc_tail, dbgi.acc, dbgi.rmall);
elsif dbgi.get_res = true then
dbgo.valid <= false;
get_res(res_head, res_tail, dbgi.acc, dbgo.acc, found);
if found = true then dbgo.valid <= true; res_to_find := idle_acc;
else res_to_find := dbgi.acc; end if;
else
dbgo.valid <= false;
pop_acc(acc_head, acc_tail, dbgo.acc, found);
if found = true then dbgo.valid <= true; end if;
end if;
dbgo.ack <= '1';
wait until dbgi.req = '0';
dbgo.ack <= '0';
end if;
if pci_core.req = '1' then
if pci_core.add = true then
add_acc(acc_head, acc_tail, pci_core.acc);
elsif pci_core.add_res = true then
add_acc(res_head, res_tail, pci_core.acc);
if res_to_find.valid = true and pci_core.acc.id = res_to_find.id then
dbgo.res_found <= '1';
end if;
else
core_pci.valid <= false;
pop_acc(acc_head, acc_tail, core_pci.acc, found);
if found = true then core_pci.valid <= true; end if;
end if;
core_pci.ack <= '1';
wait until pci_core.req = '0';
core_pci.ack <= '0';
end if;
end process;
-- <= NEW
pt_pci_core : process
procedure sync_with_core is
begin
pci_core.req <= '1';
wait until core_pci.ack = '1';
pci_core.req <= '0';
wait until core_pci.ack = '0';
end sync_with_core;
function check_data(
constant pci_data : std_logic_vector(31 downto 0);
constant comp_data : std_logic_vector(31 downto 0);
constant cbe : std_logic_vector(3 downto 0))
return boolean is
variable res : boolean := true;
variable data : std_logic_vector(31 downto 0);
begin
data := comp_data;
if cbe(0) = '1' then data(7 downto 0) := (others => '-'); end if;
if cbe(1) = '1' then data(15 downto 8) := (others => '-'); end if;
if cbe(2) = '1' then data(23 downto 16) := (others => '-'); end if;
if cbe(3) = '1' then data(31 downto 24) := (others => '-'); end if;
for i in 0 to 31 loop
if pci_data(i) /= data(i) and data(i) /= '-' then res := false; end if;
end loop;
return res;
end check_data;
variable v : reg_type;
begin
if to_x01(pciin.syst.rst) = '0' then
v.state := idle;
v.pcien := (others => '0');
v.pci := pci_idle;
v.pci.ifc.frame := '1';
v.pci.ifc.irdy := '1';
v.read := '0';
v.perren := (others => '0');
v.parerr := '0';
elsif rising_edge(pciin.syst.clk) then
v := r;
v.grant := to_x01(pciin.ifc.frame) and to_x01(pciin.ifc.irdy) and not r.pci.arb.req(slot) and not to_x01(pciin.arb.gnt(slot));
v.pcien(1) := r.pcien(0); v.pcien(2) := r.pcien(1);
v.pci.ad.par := xorv(r.pci.ad.ad & r.pci.ad.cbe & r.parerr);
v.perr_ad := pciin.ad.ad; v.perr_cbe := pciin.ad.cbe;
v.pci.err.perr := (not xorv(r.perr_ad & r.perr_cbe & to_x01(pciin.ad.par))) or not r.read;
v.perren(1) := r.perren(0);
case r.state is
when idle =>
if core_pci.valid = true then
if r.acc.idle = false then
v.pci.arb.req(slot) := '0';
if v.grant = '1' then
v.pcien(0) := '1';
v.pci.ifc.frame := '0';
v.pci.ad.ad := core_pci.acc.addr;
v.pci.ad.cbe := core_pci.acc.cbe_cmd;
if core_pci.acc.parerr = 2 then v.parerr := '1'; else v.parerr := '0'; end if;
v.state := addr;
v.read := '0';
v.perren := (others => '0');
end if;
else -- Idle cycle
if r.acc.ws <= 0 then
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc;
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
else
v.acc.ws := r.acc.ws - 1;
end if;
end if;
else
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
end if;
when addr =>
if r.acc.last = true and r.acc.ws <= 0 then v.pci.ifc.frame := '1'; v.pci.arb.req(slot) := '1'; end if;
if (r.acc.cbe_cmd = MEM_READ or r.acc.cbe_cmd = MEM_R_MULT or r.acc.cbe_cmd = MEM_R_LINE
or r.acc.cbe_cmd = IO_READ or r.acc.cbe_cmd = CONF_READ) then
v.read := '1';
end if;
if r.acc.ws <= 0 then v.pci.ifc.irdy := '0'; v.pci.ad.ad := r.acc.data;
else v.acc.ws := r.acc.ws - 1; v.pci.ad.ad := (others => '-'); end if;
v.pci.ad.cbe := r.acc.cbe_data;
if core_pci.acc.parerr = 1 then v.parerr := '1'; else v.parerr := '0'; end if;
v.state := data;
v.devsel_timeout := 0;
when data =>
if r.pci.ifc.irdy = '1' and r.acc.ws /= 0 then
v.acc.ws := r.acc.ws - 1;
else
v.pci.ifc.irdy := '0';
v.pci.ad.ad := r.acc.data;
if r.acc.last = true or to_x01(pciin.ifc.stop) = '0' then v.pci.ifc.frame := '1'; v.pci.arb.req(slot) := '1'; end if;
end if;
if to_x01(pciin.ifc.devsel) = '1' then
if r.devsel_timeout < 3 then
v.devsel_timeout := r.devsel_timeout + 1;
else
v.pci.ifc.frame := '1';
v.pci.ifc.irdy := '1';
if r.pci.ifc.frame = '1' then
v.pcien(0) := '0';
v.state := idle;
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc; -- FIXME: should set Master abort status in this response
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
if r.acc.debug >= 1 then
if r.read = '1' then
print("ERROR: PCITBM Read[" & tost(r.acc.addr) & "]: MASTER ABORT");
else
print("ERROR: PCITBM WRITE[" & tost(r.acc.addr) & "]: MASTER ABORT");
end if;
end if;
end if;
end if;
end if;
--if to_x01(pciin.ifc.trdy) = '0' and r.pci.ifc.irdy = '0' then
if (to_x01(pciin.ifc.trdy) = '0' or (r.acc.cod = 1 and to_x01(pciin.ifc.stop) = '0')) and r.pci.ifc.irdy = '0' then
if r.read = '1' then v.perren(0) := '1'; end if; -- only drive perr from read
if r.pci.ifc.frame = '1' then -- done
v.pcien(0) := '0'; v.pci.ifc.irdy := '1';
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc;
if r.read = '1' then pci_core.acc.data <= pciin.ad.ad; end if;
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
v.state := idle;
else
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc;
if r.read = '1' then pci_core.acc.data <= pciin.ad.ad; end if;
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
if core_pci.valid = true then
v.pci.ad.cbe := v.acc.cbe_data;
if core_pci.acc.parerr = 1 then v.parerr := '1'; else v.parerr := '0'; end if;
if v.acc.ws <= 0 then
v.pci.ad.ad := v.acc.data;
if v.acc.last = true or to_x01(pciin.ifc.stop) = '0' then v.pci.ifc.frame := '1'; v.pci.arb.req(slot) := '1'; end if;
else
v.pci.ad.ad := (others => '-');
if v.pci.ifc.frame = '0' then v.pci.ifc.irdy := '1'; end if; -- If frame => '1', do not add waitstates (irdey => '1')
v.acc.ws := v.acc.ws - 1;
end if;
else
assert false
report "No valid acces in list, access required! (no access is marked LAST)"
severity FAILURE;
end if;
end if;
if r.acc.debug >= 1 then
if r.acc.cod = 1 and to_x01(pciin.ifc.stop) = '0' and to_x01(pciin.ifc.trdy) = '1' then
if r.read = '1' then
print("PCITBM Read[" & tost(r.acc.addr) & "]: CANCELED ON DISCONNECT");
else
print("PCITBM WRITE[" & tost(r.acc.addr) & "]: CANCELED ON DISCONNECT");
end if;
else
if r.read = '1' then
if check_data(pciin.ad.ad, r.pci.ad.ad, r.pci.ad.cbe) = false then
print("ERROR: PCITBM Read[" & tost(r.acc.addr) & "]: " & tost(pciin.ad.ad) & " != " & tost(r.pci.ad.ad));
elsif r.acc.debug >= 2 then
print("PCITBM Read[" & tost(r.acc.addr) & "]: " & tost(pciin.ad.ad));
end if;
else
if r.acc.debug >= 2 then
print("PCITBM Write[" & tost(r.acc.addr) & "]: " & tost(pciin.ad.ad));
end if;
end if;
end if;
end if;
elsif to_x01(pciin.ifc.stop) = '0' and r.pci.ifc.frame = '1' then -- Disconnect
v.pcien(0) := '0';
v.pci.ifc.irdy := '1';
v.state := idle;
if to_x01(pciin.ifc.devsel) = '1' then
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc; -- FIXME: should set Master abort status in this response
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
if r.acc.debug >= 1 then
if r.read = '1' then
print("ERROR: PCITBM Read[" & tost(r.acc.addr) & "]: TARGET ABORT");
else
print("ERROR: PCITBM WRITE[" & tost(r.acc.addr) & "]: TARGET ABORT");
end if;
end if;
end if;
end if;
when turn =>
when active =>
when done =>
when others =>
end case;
end if;
r <= v;
wait on pciin.syst.clk, pciin.syst.rst;
end process;
pciout.ad.ad <= r.pci.ad.ad after tval when (r.pcien(0) and not r.read) = '1' else (others => 'Z') after tval;
pciout.ad.cbe <= r.pci.ad.cbe after tval when r.pcien(0) = '1' else (others => 'Z') after tval;
pciout.ad.par <= r.pci.ad.par after tval when (r.pcien(1) = '1' and (r.read = '0' or r.pcien(3 downto 0) = "0011")) else 'Z' after tval;
pciout.ifc.frame <= r.pci.ifc.frame after tval when r.pcien(0) = '1' else 'Z' after tval;
pciout.ifc.irdy <= r.pci.ifc.irdy after tval when r.pcien(1) = '1' else 'Z' after tval;
pciout.err.perr <= r.pci.err.perr after tval when (r.pcien(2) and r.perren(1)) = '1' else 'Z' after tval;
pciout.err.serr <= r.pci.err.serr after tval when r.pcien(2) = '1' else 'Z' after tval;
-- Unused signals
pciout.arb <= arb_const;
pciout.arb.req(slot) <= r.pci.arb.req(slot) after tval;
-- Unused signals
pciout.ifc.trdy <= 'Z';
pciout.ifc.stop <= 'Z';
pciout.ifc.devsel <= 'Z';
pciout.ifc.lock <= 'Z';
pciout.ifc.idsel <= (others => 'Z');
pciout.err.serr <= 'Z';
pciout.syst <= syst_const;
pciout.ext64 <= ext64_const;
pciout.cache <= cache_const;
pciout.int <= (others => 'Z');
end;
-- pragma translate_on
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY apll IS
generic (
freq : integer := 200;
mult : integer := 8;
div : integer := 5;
rskew : integer := 0
);
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
phasestep : IN STD_LOGIC := '0';
phaseupdown : IN STD_LOGIC := '0';
scanclk : IN STD_LOGIC := '1';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC;
phasedone : OUT STD_LOGIC
);
END apll;
ARCHITECTURE SYN OF apll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire9_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL scanclk_clk5 : STD_LOGIC ;
signal phasecounter_reg : std_logic_vector(3 downto 0);
attribute syn_keep : boolean;
attribute syn_keep of phasecounter_reg : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of phasecounter_reg : signal is true;
constant period : integer := 1000000/freq;
function set_phase(freq : in integer) return string is
variable s : string(1 to 4) := "0000";
variable f,r : integer;
begin
f := freq;
while f /= 0 loop
r := f mod 10;
case r is
when 0 => s := "0" & s(1 to 3);
when 1 => s := "1" & s(1 to 3);
when 2 => s := "2" & s(1 to 3);
when 3 => s := "3" & s(1 to 3);
when 4 => s := "4" & s(1 to 3);
when 5 => s := "5" & s(1 to 3);
when 6 => s := "6" & s(1 to 3);
when 7 => s := "7" & s(1 to 3);
when 8 => s := "8" & s(1 to 3);
when 9 => s := "9" & s(1 to 3);
when others =>
end case;
f := f / 10;
end loop;
return s;
end function;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 21) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769"), -- 120 & 130 MHz
("1786", "3571", "5357"), ("1667", "3333", "5000"), -- 140 & 150 MHz
("1563", "3125", "4688"), ("1471", "2941", "4412"), -- 160 & 170 MHz
("1389", "2778", "4167"), ("1316", "2632", "3947"), -- 180 & 190 MHz
("1250", "2500", "3750"), ("1190", "2381", "3571")); -- 200 & 210 MHz
--constant pshift_90 : string := phasearr((freq*mult)/(10*div))(1);
constant pshift_90 : string := set_phase(100000/((4*freq*mult)/(10*div)));
--constant pshift_180 : string := phasearr((freq*mult)/(10*div))(2);
constant pshift_180 : string := set_phase(100000/((2*freq*mult)/(10*div)));
--constant pshift_270 : string := phasearr((freq*mult)/(10*div))(3);
constant pshift_270 : string := set_phase(300000/((4*freq*mult)/(10*div)));
constant pshift_rclk : string := set_phase(rskew);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
clk5_divide_by : NATURAL;
clk5_duty_cycle : NATURAL;
clk5_multiply_by : NATURAL;
clk5_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_fbout : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clk6 : STRING;
port_clk7 : STRING;
port_clk8 : STRING;
port_clk9 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
self_reset_on_loss_lock : STRING;
using_fbmimicbidir_port : STRING;
width_clock : NATURAL
);
PORT (
phasestep : IN STD_LOGIC ;
phaseupdown : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
phasecounterselect : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
locked : OUT STD_LOGIC ;
phasedone : OUT STD_LOGIC ;
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
scanclk : IN STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire9_bv(0 DOWNTO 0) <= "0";
sub_wire9 <= To_stdlogicvector(sub_wire9_bv);
scanclk_clk5 <= sub_wire0(5);
sub_wire5 <= sub_wire0(4);
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
c3 <= sub_wire4;
c4 <= sub_wire5;
locked <= sub_wire6;
sub_wire7 <= inclk0;
sub_wire8 <= sub_wire9(0 DOWNTO 0) & sub_wire7;
-- quartus bug, cant be constant
--process(scanclk)
process(scanclk_clk5)
begin
--if rising_edge(scanclk) then
if rising_edge(scanclk_clk5) then -- use ddr clock/2 to not violate 100MHz max freq
phasecounter_reg <= "0110"; --phasecounter;
end if;
end process;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => div,--5,
clk0_duty_cycle => 50,
clk0_multiply_by => mult,--8,
clk0_phase_shift => "0",
clk1_divide_by => div,--5,
clk1_duty_cycle => 50,
clk1_multiply_by => mult,--8,
clk1_phase_shift => pshift_90,--"1250",
clk2_divide_by => div,--5,
clk2_duty_cycle => 50,
clk2_multiply_by => mult,--8,
clk2_phase_shift => pshift_180,--"2500",
clk3_divide_by => div,--5,
clk3_duty_cycle => 50,
clk3_multiply_by => mult,--8,
clk3_phase_shift => pshift_270,--"3750",
clk4_divide_by => div,
clk4_duty_cycle => 50,
clk4_multiply_by => mult,
clk4_phase_shift => pshift_rclk,--"0",
clk5_divide_by => div*2,
clk5_duty_cycle => 50,
clk5_multiply_by => mult,
clk5_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => period,--8000,
intended_device_family => "Stratix III",
lpm_hint => "CBX_MODULE_PREFIX=apll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_fbout => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_USED",
port_phasedone => "PORT_USED",
port_phasestep => "PORT_USED",
port_phaseupdown => "PORT_USED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_USED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_USED",
port_clk5 => "PORT_USED",
port_clk6 => "PORT_UNUSED",
port_clk7 => "PORT_UNUSED",
port_clk8 => "PORT_UNUSED",
port_clk9 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
using_fbmimicbidir_port => "OFF",
width_clock => 10
)
PORT MAP (
phasestep => phasestep,
phaseupdown => phaseupdown,
inclk => sub_wire8,
phasecounterselect => phasecounter_reg,
areset => areset,
--scanclk => scanclk,
scanclk => scanclk_clk5,
clk => sub_wire0,
locked => sub_wire6,
phasedone => phasedone
);
END SYN;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY apll IS
generic (
freq : integer := 200;
mult : integer := 8;
div : integer := 5;
rskew : integer := 0
);
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
phasestep : IN STD_LOGIC := '0';
phaseupdown : IN STD_LOGIC := '0';
scanclk : IN STD_LOGIC := '1';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC;
phasedone : OUT STD_LOGIC
);
END apll;
ARCHITECTURE SYN OF apll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire9_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL scanclk_clk5 : STD_LOGIC ;
signal phasecounter_reg : std_logic_vector(3 downto 0);
attribute syn_keep : boolean;
attribute syn_keep of phasecounter_reg : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of phasecounter_reg : signal is true;
constant period : integer := 1000000/freq;
function set_phase(freq : in integer) return string is
variable s : string(1 to 4) := "0000";
variable f,r : integer;
begin
f := freq;
while f /= 0 loop
r := f mod 10;
case r is
when 0 => s := "0" & s(1 to 3);
when 1 => s := "1" & s(1 to 3);
when 2 => s := "2" & s(1 to 3);
when 3 => s := "3" & s(1 to 3);
when 4 => s := "4" & s(1 to 3);
when 5 => s := "5" & s(1 to 3);
when 6 => s := "6" & s(1 to 3);
when 7 => s := "7" & s(1 to 3);
when 8 => s := "8" & s(1 to 3);
when 9 => s := "9" & s(1 to 3);
when others =>
end case;
f := f / 10;
end loop;
return s;
end function;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 21) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769"), -- 120 & 130 MHz
("1786", "3571", "5357"), ("1667", "3333", "5000"), -- 140 & 150 MHz
("1563", "3125", "4688"), ("1471", "2941", "4412"), -- 160 & 170 MHz
("1389", "2778", "4167"), ("1316", "2632", "3947"), -- 180 & 190 MHz
("1250", "2500", "3750"), ("1190", "2381", "3571")); -- 200 & 210 MHz
--constant pshift_90 : string := phasearr((freq*mult)/(10*div))(1);
constant pshift_90 : string := set_phase(100000/((4*freq*mult)/(10*div)));
--constant pshift_180 : string := phasearr((freq*mult)/(10*div))(2);
constant pshift_180 : string := set_phase(100000/((2*freq*mult)/(10*div)));
--constant pshift_270 : string := phasearr((freq*mult)/(10*div))(3);
constant pshift_270 : string := set_phase(300000/((4*freq*mult)/(10*div)));
constant pshift_rclk : string := set_phase(rskew);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
clk5_divide_by : NATURAL;
clk5_duty_cycle : NATURAL;
clk5_multiply_by : NATURAL;
clk5_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_fbout : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clk6 : STRING;
port_clk7 : STRING;
port_clk8 : STRING;
port_clk9 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
self_reset_on_loss_lock : STRING;
using_fbmimicbidir_port : STRING;
width_clock : NATURAL
);
PORT (
phasestep : IN STD_LOGIC ;
phaseupdown : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
phasecounterselect : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
locked : OUT STD_LOGIC ;
phasedone : OUT STD_LOGIC ;
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
scanclk : IN STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire9_bv(0 DOWNTO 0) <= "0";
sub_wire9 <= To_stdlogicvector(sub_wire9_bv);
scanclk_clk5 <= sub_wire0(5);
sub_wire5 <= sub_wire0(4);
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
c3 <= sub_wire4;
c4 <= sub_wire5;
locked <= sub_wire6;
sub_wire7 <= inclk0;
sub_wire8 <= sub_wire9(0 DOWNTO 0) & sub_wire7;
-- quartus bug, cant be constant
--process(scanclk)
process(scanclk_clk5)
begin
--if rising_edge(scanclk) then
if rising_edge(scanclk_clk5) then -- use ddr clock/2 to not violate 100MHz max freq
phasecounter_reg <= "0110"; --phasecounter;
end if;
end process;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => div,--5,
clk0_duty_cycle => 50,
clk0_multiply_by => mult,--8,
clk0_phase_shift => "0",
clk1_divide_by => div,--5,
clk1_duty_cycle => 50,
clk1_multiply_by => mult,--8,
clk1_phase_shift => pshift_90,--"1250",
clk2_divide_by => div,--5,
clk2_duty_cycle => 50,
clk2_multiply_by => mult,--8,
clk2_phase_shift => pshift_180,--"2500",
clk3_divide_by => div,--5,
clk3_duty_cycle => 50,
clk3_multiply_by => mult,--8,
clk3_phase_shift => pshift_270,--"3750",
clk4_divide_by => div,
clk4_duty_cycle => 50,
clk4_multiply_by => mult,
clk4_phase_shift => pshift_rclk,--"0",
clk5_divide_by => div*2,
clk5_duty_cycle => 50,
clk5_multiply_by => mult,
clk5_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => period,--8000,
intended_device_family => "Stratix III",
lpm_hint => "CBX_MODULE_PREFIX=apll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_fbout => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_USED",
port_phasedone => "PORT_USED",
port_phasestep => "PORT_USED",
port_phaseupdown => "PORT_USED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_USED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_USED",
port_clk5 => "PORT_USED",
port_clk6 => "PORT_UNUSED",
port_clk7 => "PORT_UNUSED",
port_clk8 => "PORT_UNUSED",
port_clk9 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
using_fbmimicbidir_port => "OFF",
width_clock => 10
)
PORT MAP (
phasestep => phasestep,
phaseupdown => phaseupdown,
inclk => sub_wire8,
phasecounterselect => phasecounter_reg,
areset => areset,
--scanclk => scanclk,
scanclk => scanclk_clk5,
clk => sub_wire0,
locked => sub_wire6,
phasedone => phasedone
);
END SYN;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY apll IS
generic (
freq : integer := 200;
mult : integer := 8;
div : integer := 5;
rskew : integer := 0
);
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
phasestep : IN STD_LOGIC := '0';
phaseupdown : IN STD_LOGIC := '0';
scanclk : IN STD_LOGIC := '1';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC;
phasedone : OUT STD_LOGIC
);
END apll;
ARCHITECTURE SYN OF apll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire9_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL scanclk_clk5 : STD_LOGIC ;
signal phasecounter_reg : std_logic_vector(3 downto 0);
attribute syn_keep : boolean;
attribute syn_keep of phasecounter_reg : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of phasecounter_reg : signal is true;
constant period : integer := 1000000/freq;
function set_phase(freq : in integer) return string is
variable s : string(1 to 4) := "0000";
variable f,r : integer;
begin
f := freq;
while f /= 0 loop
r := f mod 10;
case r is
when 0 => s := "0" & s(1 to 3);
when 1 => s := "1" & s(1 to 3);
when 2 => s := "2" & s(1 to 3);
when 3 => s := "3" & s(1 to 3);
when 4 => s := "4" & s(1 to 3);
when 5 => s := "5" & s(1 to 3);
when 6 => s := "6" & s(1 to 3);
when 7 => s := "7" & s(1 to 3);
when 8 => s := "8" & s(1 to 3);
when 9 => s := "9" & s(1 to 3);
when others =>
end case;
f := f / 10;
end loop;
return s;
end function;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 21) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769"), -- 120 & 130 MHz
("1786", "3571", "5357"), ("1667", "3333", "5000"), -- 140 & 150 MHz
("1563", "3125", "4688"), ("1471", "2941", "4412"), -- 160 & 170 MHz
("1389", "2778", "4167"), ("1316", "2632", "3947"), -- 180 & 190 MHz
("1250", "2500", "3750"), ("1190", "2381", "3571")); -- 200 & 210 MHz
--constant pshift_90 : string := phasearr((freq*mult)/(10*div))(1);
constant pshift_90 : string := set_phase(100000/((4*freq*mult)/(10*div)));
--constant pshift_180 : string := phasearr((freq*mult)/(10*div))(2);
constant pshift_180 : string := set_phase(100000/((2*freq*mult)/(10*div)));
--constant pshift_270 : string := phasearr((freq*mult)/(10*div))(3);
constant pshift_270 : string := set_phase(300000/((4*freq*mult)/(10*div)));
constant pshift_rclk : string := set_phase(rskew);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
clk5_divide_by : NATURAL;
clk5_duty_cycle : NATURAL;
clk5_multiply_by : NATURAL;
clk5_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_fbout : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clk6 : STRING;
port_clk7 : STRING;
port_clk8 : STRING;
port_clk9 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
self_reset_on_loss_lock : STRING;
using_fbmimicbidir_port : STRING;
width_clock : NATURAL
);
PORT (
phasestep : IN STD_LOGIC ;
phaseupdown : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
phasecounterselect : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
locked : OUT STD_LOGIC ;
phasedone : OUT STD_LOGIC ;
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
scanclk : IN STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire9_bv(0 DOWNTO 0) <= "0";
sub_wire9 <= To_stdlogicvector(sub_wire9_bv);
scanclk_clk5 <= sub_wire0(5);
sub_wire5 <= sub_wire0(4);
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
c3 <= sub_wire4;
c4 <= sub_wire5;
locked <= sub_wire6;
sub_wire7 <= inclk0;
sub_wire8 <= sub_wire9(0 DOWNTO 0) & sub_wire7;
-- quartus bug, cant be constant
--process(scanclk)
process(scanclk_clk5)
begin
--if rising_edge(scanclk) then
if rising_edge(scanclk_clk5) then -- use ddr clock/2 to not violate 100MHz max freq
phasecounter_reg <= "0110"; --phasecounter;
end if;
end process;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => div,--5,
clk0_duty_cycle => 50,
clk0_multiply_by => mult,--8,
clk0_phase_shift => "0",
clk1_divide_by => div,--5,
clk1_duty_cycle => 50,
clk1_multiply_by => mult,--8,
clk1_phase_shift => pshift_90,--"1250",
clk2_divide_by => div,--5,
clk2_duty_cycle => 50,
clk2_multiply_by => mult,--8,
clk2_phase_shift => pshift_180,--"2500",
clk3_divide_by => div,--5,
clk3_duty_cycle => 50,
clk3_multiply_by => mult,--8,
clk3_phase_shift => pshift_270,--"3750",
clk4_divide_by => div,
clk4_duty_cycle => 50,
clk4_multiply_by => mult,
clk4_phase_shift => pshift_rclk,--"0",
clk5_divide_by => div*2,
clk5_duty_cycle => 50,
clk5_multiply_by => mult,
clk5_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => period,--8000,
intended_device_family => "Stratix III",
lpm_hint => "CBX_MODULE_PREFIX=apll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_fbout => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_USED",
port_phasedone => "PORT_USED",
port_phasestep => "PORT_USED",
port_phaseupdown => "PORT_USED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_USED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_USED",
port_clk5 => "PORT_USED",
port_clk6 => "PORT_UNUSED",
port_clk7 => "PORT_UNUSED",
port_clk8 => "PORT_UNUSED",
port_clk9 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
using_fbmimicbidir_port => "OFF",
width_clock => 10
)
PORT MAP (
phasestep => phasestep,
phaseupdown => phaseupdown,
inclk => sub_wire8,
phasecounterselect => phasecounter_reg,
areset => areset,
--scanclk => scanclk,
scanclk => scanclk_clk5,
clk => sub_wire0,
locked => sub_wire6,
phasedone => phasedone
);
END SYN;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY apll IS
generic (
freq : integer := 200;
mult : integer := 8;
div : integer := 5;
rskew : integer := 0
);
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
phasestep : IN STD_LOGIC := '0';
phaseupdown : IN STD_LOGIC := '0';
scanclk : IN STD_LOGIC := '1';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC;
phasedone : OUT STD_LOGIC
);
END apll;
ARCHITECTURE SYN OF apll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire9_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL scanclk_clk5 : STD_LOGIC ;
signal phasecounter_reg : std_logic_vector(3 downto 0);
attribute syn_keep : boolean;
attribute syn_keep of phasecounter_reg : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of phasecounter_reg : signal is true;
constant period : integer := 1000000/freq;
function set_phase(freq : in integer) return string is
variable s : string(1 to 4) := "0000";
variable f,r : integer;
begin
f := freq;
while f /= 0 loop
r := f mod 10;
case r is
when 0 => s := "0" & s(1 to 3);
when 1 => s := "1" & s(1 to 3);
when 2 => s := "2" & s(1 to 3);
when 3 => s := "3" & s(1 to 3);
when 4 => s := "4" & s(1 to 3);
when 5 => s := "5" & s(1 to 3);
when 6 => s := "6" & s(1 to 3);
when 7 => s := "7" & s(1 to 3);
when 8 => s := "8" & s(1 to 3);
when 9 => s := "9" & s(1 to 3);
when others =>
end case;
f := f / 10;
end loop;
return s;
end function;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 21) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769"), -- 120 & 130 MHz
("1786", "3571", "5357"), ("1667", "3333", "5000"), -- 140 & 150 MHz
("1563", "3125", "4688"), ("1471", "2941", "4412"), -- 160 & 170 MHz
("1389", "2778", "4167"), ("1316", "2632", "3947"), -- 180 & 190 MHz
("1250", "2500", "3750"), ("1190", "2381", "3571")); -- 200 & 210 MHz
--constant pshift_90 : string := phasearr((freq*mult)/(10*div))(1);
constant pshift_90 : string := set_phase(100000/((4*freq*mult)/(10*div)));
--constant pshift_180 : string := phasearr((freq*mult)/(10*div))(2);
constant pshift_180 : string := set_phase(100000/((2*freq*mult)/(10*div)));
--constant pshift_270 : string := phasearr((freq*mult)/(10*div))(3);
constant pshift_270 : string := set_phase(300000/((4*freq*mult)/(10*div)));
constant pshift_rclk : string := set_phase(rskew);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
clk5_divide_by : NATURAL;
clk5_duty_cycle : NATURAL;
clk5_multiply_by : NATURAL;
clk5_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_fbout : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clk6 : STRING;
port_clk7 : STRING;
port_clk8 : STRING;
port_clk9 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
self_reset_on_loss_lock : STRING;
using_fbmimicbidir_port : STRING;
width_clock : NATURAL
);
PORT (
phasestep : IN STD_LOGIC ;
phaseupdown : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
phasecounterselect : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
locked : OUT STD_LOGIC ;
phasedone : OUT STD_LOGIC ;
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
scanclk : IN STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire9_bv(0 DOWNTO 0) <= "0";
sub_wire9 <= To_stdlogicvector(sub_wire9_bv);
scanclk_clk5 <= sub_wire0(5);
sub_wire5 <= sub_wire0(4);
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
c3 <= sub_wire4;
c4 <= sub_wire5;
locked <= sub_wire6;
sub_wire7 <= inclk0;
sub_wire8 <= sub_wire9(0 DOWNTO 0) & sub_wire7;
-- quartus bug, cant be constant
--process(scanclk)
process(scanclk_clk5)
begin
--if rising_edge(scanclk) then
if rising_edge(scanclk_clk5) then -- use ddr clock/2 to not violate 100MHz max freq
phasecounter_reg <= "0110"; --phasecounter;
end if;
end process;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => div,--5,
clk0_duty_cycle => 50,
clk0_multiply_by => mult,--8,
clk0_phase_shift => "0",
clk1_divide_by => div,--5,
clk1_duty_cycle => 50,
clk1_multiply_by => mult,--8,
clk1_phase_shift => pshift_90,--"1250",
clk2_divide_by => div,--5,
clk2_duty_cycle => 50,
clk2_multiply_by => mult,--8,
clk2_phase_shift => pshift_180,--"2500",
clk3_divide_by => div,--5,
clk3_duty_cycle => 50,
clk3_multiply_by => mult,--8,
clk3_phase_shift => pshift_270,--"3750",
clk4_divide_by => div,
clk4_duty_cycle => 50,
clk4_multiply_by => mult,
clk4_phase_shift => pshift_rclk,--"0",
clk5_divide_by => div*2,
clk5_duty_cycle => 50,
clk5_multiply_by => mult,
clk5_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => period,--8000,
intended_device_family => "Stratix III",
lpm_hint => "CBX_MODULE_PREFIX=apll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_fbout => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_USED",
port_phasedone => "PORT_USED",
port_phasestep => "PORT_USED",
port_phaseupdown => "PORT_USED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_USED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_USED",
port_clk5 => "PORT_USED",
port_clk6 => "PORT_UNUSED",
port_clk7 => "PORT_UNUSED",
port_clk8 => "PORT_UNUSED",
port_clk9 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
using_fbmimicbidir_port => "OFF",
width_clock => 10
)
PORT MAP (
phasestep => phasestep,
phaseupdown => phaseupdown,
inclk => sub_wire8,
phasecounterselect => phasecounter_reg,
areset => areset,
--scanclk => scanclk,
scanclk => scanclk_clk5,
clk => sub_wire0,
locked => sub_wire6,
phasedone => phasedone
);
END SYN;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_prime_fifo_plain_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE k7_prime_fifo_plain_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT k7_prime_fifo_plain_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_prime_fifo_plain_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_prime_fifo_plain_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT k7_prime_fifo_plain_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_prime_fifo_plain_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_prime_fifo_plain_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(72-1 DOWNTO 0);
DOUT : OUT std_logic_vector(72-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END k7_prime_fifo_plain_pkg;
PACKAGE BODY k7_prime_fifo_plain_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END k7_prime_fifo_plain_pkg;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_19.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_19 is
end entity ch_03_19;
architecture test of ch_03_19 is
subtype data_type is integer;
signal transmit_data : data_type := 0;
begin
-- code from book:
transmit_element : process (transmit_data) is
-- . . . -- variable declarations
begin
report "transmit_element: data = "
& data_type'image(transmit_data);
-- . . .
end process transmit_element;
-- end of code from book
stimulus : process is
begin
transmit_data <= 10 after 10 ns, 20 after 20 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_19.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_19 is
end entity ch_03_19;
architecture test of ch_03_19 is
subtype data_type is integer;
signal transmit_data : data_type := 0;
begin
-- code from book:
transmit_element : process (transmit_data) is
-- . . . -- variable declarations
begin
report "transmit_element: data = "
& data_type'image(transmit_data);
-- . . .
end process transmit_element;
-- end of code from book
stimulus : process is
begin
transmit_data <= 10 after 10 ns, 20 after 20 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_19.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_19 is
end entity ch_03_19;
architecture test of ch_03_19 is
subtype data_type is integer;
signal transmit_data : data_type := 0;
begin
-- code from book:
transmit_element : process (transmit_data) is
-- . . . -- variable declarations
begin
report "transmit_element: data = "
& data_type'image(transmit_data);
-- . . .
end process transmit_element;
-- end of code from book
stimulus : process is
begin
transmit_data <= 10 after 10 ns, 20 after 20 ns;
wait;
end process stimulus;
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity shifter is
port (
--clk: in std_logic;
--rst: in std_logic;
a: in unsigned(31 downto 0);
b: in unsigned(4 downto 0);
o: out unsigned(31 downto 0);
left: in std_logic;
arith:in std_logic
);
end entity shifter;
architecture behave of shifter is
signal ina: unsigned(31 downto 0);
begin
ina <= a;
process(ina,b,left,arith)
variable i: unsigned(63 downto 0);
variable cnt: unsigned(4 downto 0);
begin
i := x"00000000" & ina;
cnt := b;
if left='1' then
i(31 downto 0) := (others => '0');
i(63 downto 31) := '0' & ina;
cnt := not cnt;
elsif arith='1' then
if ina(31) = '1' then
i(63 downto 32) := (others => '1');
else
i(63 downto 32) := (others => '0');
end if;
end if;
-- Shift according to each bit.
if cnt(4)='1' then
i(47 downto 0) := i(63 downto 16);
end if;
if cnt(3)='1' then
i(39 downto 0) := i(47 downto 8);
end if;
if cnt(2) = '1' then
i(35 downto 0) := i(39 downto 4);
end if;
if cnt(1) = '1' then
i(33 downto 0) := i(35 downto 2);
end if;
if cnt(0) = '1' then
i(31 downto 0) := i(32 downto 1);
end if;
o <= i(31 downto 0);
end process;
end behave;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:06:19 10/24/2009
-- Design Name:
-- Module Name: mROM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mROM is
Port ( enable : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (4 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0));
end mROM;
architecture Behavioral of mROM is
begin
mROM: process (address) is
type mROM_array is array (31 downto 0) of
STD_LOGIC_VECTOR (7 downto 0);
variable mROM: mROM_array := (0 => "00111000",
1 => "00001111",
2 => "00000001",
3 => "01001001", --'I'
4 => "01110100", --'t'
5 => "00100000", --' '
6 => "01110111", --'w'
7 => "01101111", --'o'
8 => "01110010", --'r'
9 => "01101011", --'k'
10 => "01110011", --'s'
11 => "00100001", --'!'
12 => "00100000", --' '
13 => "00111010", --':'
14 => "01000100", --'D'
others => "00000000"); --Ready to begin write cycles
begin
data_out <= mROM(conv_integer(unsigned(address)));
end process;
end Behavioral;
|
constant I2CFSMLength : integer := 1295;
constant I2CFSMCfg : std_logic_vector(I2CFSMLength-1 downto 0) := "00011000000001000000000000010001010000000100000000001100110000000000001000000111001000000010000000000100000101000000000000010000000000100001000000000100000000000000000001000100011100001000000000000001000000011000001000000000000100000010000000101010000000000000001000001000000010100000000000000100000000101000000011000101000000000000001001010000000101010110000000000000010100100000100100011000000000010000001001000001000101001000000000100000010100000000011000100000000100000000001000000011001000010000000001000000000100000001100010100100000000100000001011000000001111000110010000000000000110000000000111100001000000000001000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000";
|
constant I2CFSMLength : integer := 1295;
constant I2CFSMCfg : std_logic_vector(I2CFSMLength-1 downto 0) := "00011000000001000000000000010001010000000100000000001100110000000000001000000111001000000010000000000100000101000000000000010000000000100001000000000100000000000000000001000100011100001000000000000001000000011000001000000000000100000010000000101010000000000000001000001000000010100000000000000100000000101000000011000101000000000000001001010000000101010110000000000000010100100000100100011000000000010000001001000001000101001000000000100000010100000000011000100000000100000000001000000011001000010000000001000000000100000001100010100100000000100000001011000000001111000110010000000000000110000000000111100001000000000001000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000";
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(6-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(6-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(6-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(6-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_dgen
GENERIC MAP (
C_DIN_WIDTH => 6,
C_DOUT_WIDTH => 6,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_dverif
GENERIC MAP (
C_DOUT_WIDTH => 6,
C_DIN_WIDTH => 6,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 6,
C_DIN_WIDTH => 6,
C_WR_PNTR_WIDTH => 5,
C_RD_PNTR_WIDTH => 5,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
--
-- Author: Pawel Szostek ([email protected])
-- Date: 27.07.2011
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity dummy is
port (o1: out std_logic_vector(7 downto 0);
o2: out std_logic_vector(7 downto 0);
o3: out std_logic_vector(7 downto 0)
);
end;
architecture behaviour of dummy is
begin
o1 <= (others => '0');
o2 <= (3 => '1', others => '0');
o3 <= (7=>'1', 6|5|4|3|2|1|0 => '0', others => '1'); --tricky
end;
|
--
-- Author: Pawel Szostek ([email protected])
-- Date: 27.07.2011
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity dummy is
port (o1: out std_logic_vector(7 downto 0);
o2: out std_logic_vector(7 downto 0);
o3: out std_logic_vector(7 downto 0)
);
end;
architecture behaviour of dummy is
begin
o1 <= (others => '0');
o2 <= (3 => '1', others => '0');
o3 <= (7=>'1', 6|5|4|3|2|1|0 => '0', others => '1'); --tricky
end;
|
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`protect end_protected
|
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
entity simple_car_alarm is
port (
clk, rst, remote, sensors: in std_logic;
siren: out std_logic);
end entity simple_car_alarm;
--------------------------------------
architecture circuit of simple_car_alarm is
type state is (disarmed, armed, intrusion);
signal pr_state, nx_state: state;
attribute enum_encoding: string;
attribute enum_encoding of state: type is "sequential";
signal flag: std_logic;
begin
-- flag generator
process (clk, rst)
--declarativepart
begin
if (rst = '1') then
flag <= '0';
elsif (clk'event and clk = '1') then
if (remote = '0') then
flag <= '1';
else
flag <= '0';
end if;
end if;
end process;
--------------------------------------
-- lower section of FSM
--------------------------------------
process (clk, rst)
--declarativepart
begin
if (rst = '1') then
pr_state <= disarmed;
elsif (clk'event and clk = '1') then
pr_state <= nx_state;
end if;
end process;
--------------------------------------
--------------------------------------
-- Upper section of FSM
--------------------------------------
process (pr_state, remote, sensors, flag)
--declarativepart
begin
case pr_state is
when disarmed =>
siren <= '0';
if (remote = '1' and flag = '1') then
nx_state <= armed;
else
nx_state <= disarmed;
end if;
when armed =>
siren <= '0';
if (sensors = '1') then
nx_state <= intrusion;
elsif (remote = '1' and flag = '1') then
nx_state <= disarmed;
else
nx_state <= armed;
end if;
when intrusion =>
siren <= '1';
if (remote = '1' and flag = '1') then
nx_state <= disarmed;
else
nx_state <= intrusion;
end if;
end case;
end process;
end architecture circuit;
--------------------------------------
|
--------------------------------------------------------------------------------
--
-- UART top module
--
-- 8 bit data, 1 stop bit, no parity. Intended for the Digilent Arty Artix-7
-- FPGA board, but can be easily used in other projects without modification.
--
-- Signals:
-- clk : Clock of frequency G_CLOCK_FREQ
-- rst : Active high synchronous reset
-- tx_data_in : Tx data
-- tx_data_wr_in : Tx data FIFO write enable
-- tx_fifo_full_out : Tx FIFO full
-- tx_out : Tx data line. Should be routed to the Rx pin
-- of the external UART device.
-- rx_in : Rx data line. Should be routed to the Tx pin
-- of the external UART device.
-- rx_data_rd_in : Rx FIFO read enable
-- rx_data_out : Rx data
-- rx_fifo_empty_out : Rx FIFO empty
--
-- Parameters:
-- G_BAUD_RATE : UART baud rate
-- G_CLOCK_FREQ : clk frequency. Can be fractional
--
-- Data tranasction is done through small (16 deep) FIFOs. rx_data_out
-- is valid 1 clk cycle after rx_data_rd_in is asserted. Any attempt
-- to read data when the Rx FIFO is empty is ignored (rx_data_out is
-- invalid). Any attempt to send more data while the Tx FIFO is full
-- is also ignored (data on tx_data_in is dropped).
--
-- Optimally, the baud rate must be an integer multiple of the clock
-- frequency. If not, it's rounded to the closest integer. In such cases
-- care must be taken to ensure sampling does not deviate significantly from
-- the center of the "eye"(ie. the middle of the received bit).
--
-- It is recommended to use sync flip-flops and a glitch filter before
-- connecting the rx input to the external UART device.
--
-- Arty FPGA board specific notes:
-- The FT2232H chip does not support baud rates of 7 Mbaud 9 Mbaud, 10 Mbaud
-- and 11 Mbaud.
-- http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf
--
--
--------------------------------------------------------------------------------
-- This work is licensed under the MIT License (see the LICENSE file for terms)
-- Copyright 2016 Lymperis Voudouris
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart is
generic(
G_BAUD_RATE : positive := 1250000;
G_CLOCK_FREQ : real := 100.0e6
);
port(
clk : in std_logic;
rst : in std_logic;
tx_data_in : in std_logic_vector(7 downto 0);
tx_data_wr_in : in std_logic;
tx_fifo_full_out : out std_logic;
tx_out : out std_logic;
rx_in : in std_logic;
rx_data_rd_in : in std_logic;
rx_data_out : out std_logic_vector(7 downto 0);
rx_fifo_empty_out : out std_logic
);
end entity uart;
architecture rtl of uart is
signal fifo_tx_dout_i : std_logic_vector(7 downto 0) := (others=>'0');
signal fifo_tx_full_i : std_logic := '0';
signal fifo_tx_rd_en_r : std_logic := '0';
signal fifo_tx_empty_i : std_logic := '0';
signal tx_en_r : std_logic := '0';
signal tx_ready_i : std_logic := '0';
signal fifo_rx_din_r : std_logic_vector(7 downto 0) := (others=>'0');
signal fifo_rx_wr_en_r : std_logic := '0';
signal fifo_rx_full_i : std_logic := '0';
signal fifo_rx_empty_i : std_logic := '0';
signal rx_data_i : std_logic_vector(7 downto 0) := (others=>'0');
signal rx_valid_i : std_logic := '0';
begin
---------------------------------------------
-- Tx
---------------------------------------------
tx_fifo_full_out <= fifo_tx_full_i;
fifo_tx_inst : entity work.fifo_srl(rtl)
generic map(
G_DATA_WIDTH => 8,
G_DEPTH => 16
)
port map(
clk => clk,
rst => rst,
din => tx_data_in,
wr_en => tx_data_wr_in,
full => fifo_tx_full_i,
dout => fifo_tx_dout_i,
rd_en => fifo_tx_rd_en_r,
empty => fifo_tx_empty_i
);
proc_fifo_tx:
process(clk)
begin
if rising_edge(clk) then
tx_en_r <= fifo_tx_rd_en_r;
if (rst = '1') then
fifo_tx_rd_en_r <= '0';
else
-- Fetch new data from the FIFO only when the FIFO is not empty and
-- the Tx is not busy. Allow one clk cycle for the data to be fetched and
-- one more for tx_ready to update.
fifo_tx_rd_en_r <= '0';
if (tx_ready_i = '1') and (fifo_tx_empty_i = '0') and (fifo_tx_rd_en_r='0') and (tx_en_r='0') then
fifo_tx_rd_en_r <= '1';
end if;
end if;
end if;
end process;
uart_tx_inst : entity work.uart_tx(rtl)
generic map(
G_BAUD_RATE => G_BAUD_RATE,
G_CLOCK_FREQ => G_CLOCK_FREQ
)
port map(
clk => clk,
rst => rst,
tx_data_in => fifo_tx_dout_i,
tx_en_in => tx_en_r,
tx_ready_out => tx_ready_i,
tx_out => tx_out
);
---------------------------------------------
-- Rx
---------------------------------------------
rx_fifo_empty_out <= fifo_rx_empty_i;
fifo_rx_inst : entity work.fifo_srl(rtl)
generic map(
G_DATA_WIDTH => 8,
G_DEPTH => 16
)
port map(
clk => clk,
rst => rst,
din => fifo_rx_din_r,
wr_en => fifo_rx_wr_en_r,
full => fifo_rx_full_i,
dout => rx_data_out,
rd_en => rx_data_rd_in,
empty => fifo_rx_empty_i
);
proc_fifo_rx:
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
fifo_rx_wr_en_r <= '0';
else
fifo_rx_din_r <= rx_data_i;
-- Write data to the FIFO only when the FIFO is not full and
-- the Rx has valid data.
fifo_rx_wr_en_r <= '0';
if (rx_valid_i = '1') and (fifo_rx_full_i = '0') then
fifo_rx_wr_en_r <= '1';
end if;
end if;
end if;
end process;
uart_rx_inst: entity work.uart_rx(rtl)
generic map(
G_BAUD_RATE => G_BAUD_RATE,
G_CLOCK_FREQ => G_CLOCK_FREQ
)
port map(
clk => clk,
rst => rst,
rx_in => rx_in,
rx_data_out => rx_data_i,
rx_valid_out => rx_valid_i
);
end architecture rtl; |
entity reprook is
generic (
BUS_WIDTH : integer := 8;
ARRAY_WIDTH : integer := 2);
end entity reprook;
architecture behavioural of reprook is
type test_array_btype is array (integer range <>) of
bit_vector (BUS_WIDTH-1 downto 0);
subtype test_array_type is test_array_btype (ARRAY_WIDTH-1 downto 0);
signal s : test_array_type := (others => (others => '0'));
begin
failing_process : process
begin
assert s'left = 1;
assert s'right = 0;
wait;
end process failing_process;
end architecture behavioural;
|
entity reprook is
generic (
BUS_WIDTH : integer := 8;
ARRAY_WIDTH : integer := 2);
end entity reprook;
architecture behavioural of reprook is
type test_array_btype is array (integer range <>) of
bit_vector (BUS_WIDTH-1 downto 0);
subtype test_array_type is test_array_btype (ARRAY_WIDTH-1 downto 0);
signal s : test_array_type := (others => (others => '0'));
begin
failing_process : process
begin
assert s'left = 1;
assert s'right = 0;
wait;
end process failing_process;
end architecture behavioural;
|
entity reprook is
generic (
BUS_WIDTH : integer := 8;
ARRAY_WIDTH : integer := 2);
end entity reprook;
architecture behavioural of reprook is
type test_array_btype is array (integer range <>) of
bit_vector (BUS_WIDTH-1 downto 0);
subtype test_array_type is test_array_btype (ARRAY_WIDTH-1 downto 0);
signal s : test_array_type := (others => (others => '0'));
begin
failing_process : process
begin
assert s'left = 1;
assert s'right = 0;
wait;
end process failing_process;
end architecture behavioural;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.types_pkg.all;
library sys;
use sys.sys_pkg.all;
use work.cpu_or1knd_i5_mmu_inst_pkg.all;
use work.cpu_or1knd_i5_mmu_data_pkg.all;
use work.cpu_l1mem_inst_pkg.all;
use work.cpu_l1mem_data_pkg.all;
use work.cpu_or1knd_i5_pipe_pkg.all;
architecture rtl of cpu_or1knd_i5_core is
type comb_type is record
sys_master_ctrl_out_master : sys_master_ctrl_out_vector_type(1 downto 0);
sys_master_dp_out_master : sys_master_dp_out_vector_type(1 downto 0);
sys_slave_ctrl_out_master : sys_slave_ctrl_out_vector_type(1 downto 0);
sys_master_ctrl_out : sys_master_ctrl_out_type;
sys_master_dp_out : sys_master_dp_out_type;
cpu_l1mem_inst_ctrl_in : cpu_l1mem_inst_ctrl_in_type;
cpu_l1mem_inst_dp_in : cpu_l1mem_inst_dp_in_type;
cpu_l1mem_inst_ctrl_out : cpu_l1mem_inst_ctrl_out_type;
cpu_l1mem_inst_dp_out : cpu_l1mem_inst_dp_out_type;
cpu_l1mem_data_ctrl_in : cpu_l1mem_data_ctrl_in_type;
cpu_l1mem_data_dp_in : cpu_l1mem_data_dp_in_type;
cpu_l1mem_data_ctrl_out : cpu_l1mem_data_ctrl_out_type;
cpu_l1mem_data_dp_out : cpu_l1mem_data_dp_out_type;
cpu_or1knd_i5_mmu_inst_ctrl_in : cpu_or1knd_i5_mmu_inst_ctrl_in_type;
cpu_or1knd_i5_mmu_inst_dp_in : cpu_or1knd_i5_mmu_inst_dp_in_type;
cpu_or1knd_i5_mmu_inst_ctrl_out : cpu_or1knd_i5_mmu_inst_ctrl_out_type;
cpu_or1knd_i5_mmu_inst_dp_out : cpu_or1knd_i5_mmu_inst_dp_out_type;
cpu_or1knd_i5_mmu_data_ctrl_in : cpu_or1knd_i5_mmu_data_ctrl_in_type;
cpu_or1knd_i5_mmu_data_dp_in : cpu_or1knd_i5_mmu_data_dp_in_type;
cpu_or1knd_i5_mmu_data_ctrl_out : cpu_or1knd_i5_mmu_data_ctrl_out_type;
cpu_or1knd_i5_mmu_data_dp_out : cpu_or1knd_i5_mmu_data_dp_out_type;
cpu_or1knd_i5_mmu_inst_ctrl_in_pipe : cpu_or1knd_i5_mmu_inst_ctrl_in_pipe_type;
cpu_or1knd_i5_mmu_inst_dp_in_pipe : cpu_or1knd_i5_mmu_inst_dp_in_pipe_type;
cpu_or1knd_i5_mmu_inst_ctrl_out_pipe : cpu_or1knd_i5_mmu_inst_ctrl_out_pipe_type;
cpu_or1knd_i5_mmu_inst_dp_out_pipe : cpu_or1knd_i5_mmu_inst_dp_out_pipe_type;
cpu_or1knd_i5_mmu_data_ctrl_in_pipe : cpu_or1knd_i5_mmu_data_ctrl_in_pipe_type;
cpu_or1knd_i5_mmu_data_dp_in_pipe : cpu_or1knd_i5_mmu_data_dp_in_pipe_type;
cpu_or1knd_i5_mmu_data_ctrl_out_pipe : cpu_or1knd_i5_mmu_data_ctrl_out_pipe_type;
cpu_or1knd_i5_mmu_data_dp_out_pipe : cpu_or1knd_i5_mmu_data_dp_out_pipe_type;
end record;
signal c : comb_type;
begin
pipe : entity work.cpu_or1knd_i5_pipe(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_l1mem_inst_ctrl_out => c.cpu_l1mem_inst_ctrl_out,
cpu_l1mem_data_ctrl_out => c.cpu_l1mem_data_ctrl_out,
cpu_l1mem_inst_dp_out => c.cpu_l1mem_inst_dp_out,
cpu_l1mem_data_dp_out => c.cpu_l1mem_data_dp_out,
cpu_l1mem_inst_ctrl_in => c.cpu_l1mem_inst_ctrl_in,
cpu_l1mem_data_ctrl_in => c.cpu_l1mem_data_ctrl_in,
cpu_l1mem_inst_dp_in => c.cpu_l1mem_inst_dp_in,
cpu_l1mem_data_dp_in => c.cpu_l1mem_data_dp_in,
cpu_or1knd_i5_mmu_inst_ctrl_in_pipe => c.cpu_or1knd_i5_mmu_inst_ctrl_in_pipe,
cpu_or1knd_i5_mmu_inst_dp_in_pipe => c.cpu_or1knd_i5_mmu_inst_dp_in_pipe,
cpu_or1knd_i5_mmu_inst_ctrl_out_pipe => c.cpu_or1knd_i5_mmu_inst_ctrl_out_pipe,
cpu_or1knd_i5_mmu_inst_dp_out_pipe => c.cpu_or1knd_i5_mmu_inst_dp_out_pipe,
cpu_or1knd_i5_mmu_data_ctrl_in_pipe => c.cpu_or1knd_i5_mmu_data_ctrl_in_pipe,
cpu_or1knd_i5_mmu_data_dp_in_pipe => c.cpu_or1knd_i5_mmu_data_dp_in_pipe,
cpu_or1knd_i5_mmu_data_ctrl_out_pipe => c.cpu_or1knd_i5_mmu_data_ctrl_out_pipe,
cpu_or1knd_i5_mmu_data_dp_out_pipe => c.cpu_or1knd_i5_mmu_data_dp_out_pipe
);
l1mem_inst : entity work.cpu_l1mem_inst(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_mmu_inst_ctrl_in => c.cpu_or1knd_i5_mmu_inst_ctrl_in,
cpu_mmu_inst_dp_in => c.cpu_or1knd_i5_mmu_inst_dp_in,
cpu_mmu_inst_ctrl_out => c.cpu_or1knd_i5_mmu_inst_ctrl_out,
cpu_mmu_inst_dp_out => c.cpu_or1knd_i5_mmu_inst_dp_out,
cpu_l1mem_inst_ctrl_in => c.cpu_l1mem_inst_ctrl_in,
cpu_l1mem_inst_dp_in => c.cpu_l1mem_inst_dp_in,
cpu_l1mem_inst_ctrl_out => c.cpu_l1mem_inst_ctrl_out,
cpu_l1mem_inst_dp_out => c.cpu_l1mem_inst_dp_out,
sys_master_ctrl_out => c.sys_master_ctrl_out_master(0),
sys_master_dp_out => c.sys_master_dp_out_master(0),
sys_slave_ctrl_out => c.sys_slave_ctrl_out_master(0),
sys_slave_dp_out => sys_slave_dp_out
);
l1mem_data : entity work.cpu_l1mem_data(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_mmu_data_ctrl_in => c.cpu_or1knd_i5_mmu_data_ctrl_in,
cpu_mmu_data_dp_in => c.cpu_or1knd_i5_mmu_data_dp_in,
cpu_mmu_data_ctrl_out => c.cpu_or1knd_i5_mmu_data_ctrl_out,
cpu_mmu_data_dp_out => c.cpu_or1knd_i5_mmu_data_dp_out,
cpu_l1mem_data_ctrl_in => c.cpu_l1mem_data_ctrl_in,
cpu_l1mem_data_dp_in => c.cpu_l1mem_data_dp_in,
cpu_l1mem_data_ctrl_out => c.cpu_l1mem_data_ctrl_out,
cpu_l1mem_data_dp_out => c.cpu_l1mem_data_dp_out,
sys_master_ctrl_out => c.sys_master_ctrl_out_master(1),
sys_master_dp_out => c.sys_master_dp_out_master(1),
sys_slave_ctrl_out => c.sys_slave_ctrl_out_master(1),
sys_slave_dp_out => sys_slave_dp_out
);
mmu_inst : entity work.cpu_or1knd_i5_mmu_inst(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_or1knd_i5_mmu_inst_ctrl_in => c.cpu_or1knd_i5_mmu_inst_ctrl_in,
cpu_or1knd_i5_mmu_inst_dp_in => c.cpu_or1knd_i5_mmu_inst_dp_in,
cpu_or1knd_i5_mmu_inst_ctrl_out => c.cpu_or1knd_i5_mmu_inst_ctrl_out,
cpu_or1knd_i5_mmu_inst_dp_out => c.cpu_or1knd_i5_mmu_inst_dp_out,
cpu_or1knd_i5_mmu_inst_ctrl_in_pipe => c.cpu_or1knd_i5_mmu_inst_ctrl_in_pipe,
cpu_or1knd_i5_mmu_inst_dp_in_pipe => c.cpu_or1knd_i5_mmu_inst_dp_in_pipe,
cpu_or1knd_i5_mmu_inst_ctrl_out_pipe => c.cpu_or1knd_i5_mmu_inst_ctrl_out_pipe,
cpu_or1knd_i5_mmu_inst_dp_out_pipe => c.cpu_or1knd_i5_mmu_inst_dp_out_pipe
);
mmu_data : entity work.cpu_or1knd_i5_mmu_data(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_or1knd_i5_mmu_data_ctrl_in => c.cpu_or1knd_i5_mmu_data_ctrl_in,
cpu_or1knd_i5_mmu_data_dp_in => c.cpu_or1knd_i5_mmu_data_dp_in,
cpu_or1knd_i5_mmu_data_ctrl_out => c.cpu_or1knd_i5_mmu_data_ctrl_out,
cpu_or1knd_i5_mmu_data_dp_out => c.cpu_or1knd_i5_mmu_data_dp_out,
cpu_or1knd_i5_mmu_data_ctrl_in_pipe => c.cpu_or1knd_i5_mmu_data_ctrl_in_pipe,
cpu_or1knd_i5_mmu_data_dp_in_pipe => c.cpu_or1knd_i5_mmu_data_dp_in_pipe,
cpu_or1knd_i5_mmu_data_ctrl_out_pipe => c.cpu_or1knd_i5_mmu_data_ctrl_out_pipe,
cpu_or1knd_i5_mmu_data_dp_out_pipe => c.cpu_or1knd_i5_mmu_data_dp_out_pipe
);
arb : entity sys.sys_master_arb(rtl)
generic map (
masters => 2
)
port map (
clk => clk,
rstn => rstn,
sys_master_ctrl_out_master => c.sys_master_ctrl_out_master,
sys_master_dp_out_master => c.sys_master_dp_out_master,
sys_slave_ctrl_out_master => c.sys_slave_ctrl_out_master,
sys_slave_ctrl_out_sys => sys_slave_ctrl_out,
sys_master_ctrl_out_sys => c.sys_master_ctrl_out,
sys_master_dp_out_sys => c.sys_master_dp_out
);
sys_master_ctrl_out <= c.sys_master_ctrl_out;
sys_master_dp_out <= c.sys_master_dp_out;
-- pragma translate_off
process (clk) is
begin
if rising_edge(clk) and rstn = '1' then
assert not is_x(sys_slave_ctrl_out.ready)
report "sys_slave_ctrl_out.ready invalid"
severity failure;
if sys_slave_ctrl_out.ready = '1' then
assert not is_x(sys_slave_ctrl_out.error)
report "sys_slave_ctrl_out.error invalid"
severity failure;
end if;
assert not is_x(c.sys_master_ctrl_out.request)
report "sys_master_ctrl_out.request invalid"
severity failure;
if c.sys_master_ctrl_out.request = '1' then
assert not is_x(c.sys_master_ctrl_out.be)
report "sys_master_ctrl_out.be invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.write)
report "sys_master_ctrl_out.write invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.cacheable)
report "sys_master_ctrl_out.cacheable invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.inst)
report "sys_master_ctrl_out.inst invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.burst)
report "sys_master_ctrl_out.burst invalid"
severity failure;
if c.sys_master_ctrl_out.burst = '1' then
assert not is_x(c.sys_master_ctrl_out.bwrap)
report "sys_master_ctrl_out.bwrap invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.bcycles)
report "sys_master_ctrl_out.bcycles invalid"
severity failure;
end if;
assert not is_x(c.sys_master_dp_out.paddr)
report "sys_master_dp_out.paddr invalid"
severity failure;
for n in sys_transfer_size_bits-1 downto 2 loop
assert c.sys_master_dp_out.size(n) = '0'
report "sys_master_dp_out.size invalid"
severity failure;
end loop;
--case c.sys_master_dp_out.size(1 downto 0) is
-- when "00" =>
-- if c.sys_master_ctrl_out.write = '1' then
-- assert not is_x(c.sys_master_dp_out.data(7 downto 0))
-- report "sys_master_dp_out.data invalid"
-- severity failure;
-- end if;
-- when "01" =>
-- if c.sys_master_ctrl_out.write = '1' then
-- assert not is_x(c.sys_master_dp_out.data(15 downto 0))
-- report "sys_master_dp_out.data invalid"
-- severity failure;
-- end if;
-- when "10" =>
-- if c.sys_master_ctrl_out.write = '1' then
-- assert not is_x(c.sys_master_dp_out.data(31 downto 0))
-- report "sys_master_dp_out.data invalid"
-- severity failure;
-- end if;
-- when others =>
-- assert not false
-- report "sys_master_dp_out.size invalid"
-- severity failure;
--end case;
end if;
end if;
end process;
-- pragma translate_on
end;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY grlib;
USE grlib.amba.all;
USE grlib.stdlib.all;
LIBRARY gaisler;
USE grlib.devices.all;
USE gaisler.memctrl.all;
LIBRARY techmap;
USE techmap.gencomp.all;
ENTITY ddrsp64a IS
GENERIC (
memtech : integer := 0;
hindex : integer := 3;
haddr : integer := 1024;
hmask : integer := 3072;
ioaddr : integer := 1;
iomask : integer := 4095;
MHz : integer := 90;
col : integer := 9;
Mbyte : integer := 256;
fast : integer := 0;
pwron : integer := 1;
oepol : integer := 0
);
PORT (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
END ENTITY;
ARCHITECTURE rtl OF ddrsp64a IS
CONSTANT REVISION : integer := 0;
CONSTANT CMD_PRE : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT CMD_REF : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT CMD_LMR : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT CMD_EMR : std_logic_vector ( 2 downto 0 ) := "111";
CONSTANT abuf : integer := 6;
CONSTANT hconfig : ahb_config_type := ( 0 => ahb_device_reg ( VENDOR_GAISLER , GAISLER_DDRSP , 0 , 0 , 0 ) , 4 => ahb_membar ( 1024 , '1' , '1' , 3072 ) , 5 => ahb_iobar ( 1 , 4095 ) , OTHERS => zero32 );
TYPE mcycletype IS ( midle , active , ext , leadout );
TYPE ahb_state_type IS ( midle , rhold , dread , dwrite , whold1 , whold2 );
TYPE sdcycletype IS ( act1 , act2 , act3 , rd1 , rd2 , rd3 , rd4 , rd5 , rd6 , rd7 , rd8 , wr1 , wr2 , wr3 , wr4a , wr4 , wr5 , sidle , ioreg1 , ioreg2 );
TYPE icycletype IS ( iidle , pre , ref1 , ref2 , emode , lmode , finish );
CONSTANT NAHBMST : integer := 16;
CONSTANT NAHBSLV : integer := 16;
CONSTANT NAPBSLV : integer := 16;
CONSTANT NAHBIRQ : integer := 32;
CONSTANT NAHBAMR : integer := 4;
CONSTANT NAHBIR : integer := 4;
CONSTANT NAHBCFG : integer := 4 + 4;
CONSTANT NAPBIR : integer := 1;
CONSTANT NAPBAMR : integer := 1;
CONSTANT NAPBCFG : integer := 1 + 1;
CONSTANT NBUS : integer := 4;
SUBTYPE amba_config_word IS std_logic_vector ( 31 downto 0 );
TYPE ahb_config_type IS ARRAY ( 0 to 4 + 4 - 1 ) OF amba_config_word;
TYPE apb_config_type IS ARRAY ( 0 to 1 + 1 - 1 ) OF amba_config_word;
TYPE ahb_mst_in_type IS RECORD
hgrant : std_logic_vector ( 0 to 16 - 1 );
hready : std_ulogic;
hresp : std_logic_vector ( 1 downto 0 );
hrdata : std_logic_vector ( 31 downto 0 );
hcache : std_ulogic;
hirq : std_logic_vector ( 32 - 1 downto 0 );
testen : std_ulogic;
testrst : std_ulogic;
scanen : std_ulogic;
testoen : std_ulogic;
END RECORD;
TYPE ahb_mst_out_type IS RECORD
hbusreq : std_ulogic;
hlock : std_ulogic;
htrans : std_logic_vector ( 1 downto 0 );
haddr : std_logic_vector ( 31 downto 0 );
hwrite : std_ulogic;
hsize : std_logic_vector ( 2 downto 0 );
hburst : std_logic_vector ( 2 downto 0 );
hprot : std_logic_vector ( 3 downto 0 );
hwdata : std_logic_vector ( 31 downto 0 );
hirq : std_logic_vector ( 32 - 1 downto 0 );
hconfig : ahb_config_type;
hindex : integer RANGE 0 to 16 - 1;
END RECORD;
TYPE ahb_slv_in_type IS RECORD
hsel : std_logic_vector ( 0 to 16 - 1 );
haddr : std_logic_vector ( 31 downto 0 );
hwrite : std_ulogic;
htrans : std_logic_vector ( 1 downto 0 );
hsize : std_logic_vector ( 2 downto 0 );
hburst : std_logic_vector ( 2 downto 0 );
hwdata : std_logic_vector ( 31 downto 0 );
hprot : std_logic_vector ( 3 downto 0 );
hready : std_ulogic;
hmaster : std_logic_vector ( 3 downto 0 );
hmastlock : std_ulogic;
hmbsel : std_logic_vector ( 0 to 4 - 1 );
hcache : std_ulogic;
hirq : std_logic_vector ( 32 - 1 downto 0 );
testen : std_ulogic;
testrst : std_ulogic;
scanen : std_ulogic;
testoen : std_ulogic;
END RECORD;
TYPE ahb_slv_out_type IS RECORD
hready : std_ulogic;
hresp : std_logic_vector ( 1 downto 0 );
hrdata : std_logic_vector ( 31 downto 0 );
hsplit : std_logic_vector ( 15 downto 0 );
hcache : std_ulogic;
hirq : std_logic_vector ( 32 - 1 downto 0 );
hconfig : ahb_config_type;
hindex : integer RANGE 0 to 16 - 1;
END RECORD;
TYPE ahb_mst_out_vector_type IS ARRAY ( natural RANGE <> ) OF ahb_mst_out_type;
TYPE ahb_slv_out_vector_type IS ARRAY ( natural RANGE <> ) OF ahb_slv_out_type;
SUBTYPE ahb_mst_out_vector IS ahb_mst_out_vector_type ( 16 - 1 downto 0 );
SUBTYPE ahb_slv_out_vector IS ahb_slv_out_vector_type ( 16 - 1 downto 0 );
TYPE ahb_mst_out_bus_vector IS ARRAY ( 0 to 4 - 1 ) OF ahb_mst_out_vector;
TYPE ahb_slv_out_bus_vector IS ARRAY ( 0 to 4 - 1 ) OF ahb_slv_out_vector;
CONSTANT HTRANS_IDLE : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT HTRANS_BUSY : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT HTRANS_NONSEQ : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT HTRANS_SEQ : std_logic_vector ( 1 downto 0 ) := "11";
CONSTANT HBURST_SINGLE : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT HBURST_INCR : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT HBURST_WRAP4 : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT HBURST_INCR4 : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT HBURST_WRAP8 : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT HBURST_INCR8 : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT HBURST_WRAP16 : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT HBURST_INCR16 : std_logic_vector ( 2 downto 0 ) := "111";
CONSTANT HSIZE_BYTE : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT HSIZE_HWORD : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT HSIZE_WORD : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT HSIZE_DWORD : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT HSIZE_4WORD : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT HSIZE_8WORD : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT HSIZE_16WORD : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT HSIZE_32WORD : std_logic_vector ( 2 downto 0 ) := "111";
CONSTANT HRESP_OKAY : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT HRESP_ERROR : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT HRESP_RETRY : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT HRESP_SPLIT : std_logic_vector ( 1 downto 0 ) := "11";
TYPE apb_slv_in_type IS RECORD
psel : std_logic_vector ( 0 to 16 - 1 );
penable : std_ulogic;
paddr : std_logic_vector ( 31 downto 0 );
pwrite : std_ulogic;
pwdata : std_logic_vector ( 31 downto 0 );
pirq : std_logic_vector ( 32 - 1 downto 0 );
testen : std_ulogic;
testrst : std_ulogic;
scanen : std_ulogic;
testoen : std_ulogic;
END RECORD;
TYPE apb_slv_out_type IS RECORD
prdata : std_logic_vector ( 31 downto 0 );
pirq : std_logic_vector ( 32 - 1 downto 0 );
pconfig : apb_config_type;
pindex : integer RANGE 0 to 16 - 1;
END RECORD;
TYPE apb_slv_out_vector IS ARRAY ( 0 to 16 - 1 ) OF apb_slv_out_type;
CONSTANT AMBA_CONFIG_VER0 : std_logic_vector ( 1 downto 0 ) := "00";
SUBTYPE amba_vendor_type IS integer RANGE 0 to 16#ff#;
SUBTYPE amba_device_type IS integer RANGE 0 to 16#3ff#;
SUBTYPE amba_version_type IS integer RANGE 0 to 16#3f#;
SUBTYPE amba_cfgver_type IS integer RANGE 0 to 3;
SUBTYPE amba_irq_type IS integer RANGE 0 to 32 - 1;
SUBTYPE ahb_addr_type IS integer RANGE 0 to 16#fff#;
CONSTANT zx : std_logic_vector ( 31 downto 0 ) := ( OTHERS => '0' );
CONSTANT zxirq : std_logic_vector ( 32 - 1 downto 0 ) := ( OTHERS => '0' );
CONSTANT zy : std_logic_vector ( 0 to 31 ) := ( OTHERS => '0' );
TYPE memory_in_type IS RECORD
data : std_logic_vector ( 31 downto 0 );
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector ( 3 downto 0 );
bwidth : std_logic_vector ( 1 downto 0 );
sd : std_logic_vector ( 63 downto 0 );
cb : std_logic_vector ( 7 downto 0 );
scb : std_logic_vector ( 7 downto 0 );
edac : std_logic;
END RECORD;
TYPE memory_out_type IS RECORD
address : std_logic_vector ( 31 downto 0 );
data : std_logic_vector ( 31 downto 0 );
sddata : std_logic_vector ( 63 downto 0 );
ramsn : std_logic_vector ( 7 downto 0 );
ramoen : std_logic_vector ( 7 downto 0 );
ramn : std_ulogic;
romn : std_ulogic;
mben : std_logic_vector ( 3 downto 0 );
iosn : std_logic;
romsn : std_logic_vector ( 7 downto 0 );
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector ( 3 downto 0 );
bdrive : std_logic_vector ( 3 downto 0 );
vbdrive : std_logic_vector ( 31 downto 0 );
svbdrive : std_logic_vector ( 63 downto 0 );
read : std_logic;
sa : std_logic_vector ( 14 downto 0 );
cb : std_logic_vector ( 7 downto 0 );
scb : std_logic_vector ( 7 downto 0 );
vcdrive : std_logic_vector ( 7 downto 0 );
svcdrive : std_logic_vector ( 7 downto 0 );
ce : std_ulogic;
END RECORD;
TYPE sdctrl_in_type IS RECORD
wprot : std_ulogic;
data : std_logic_vector ( 127 downto 0 );
cb : std_logic_vector ( 15 downto 0 );
END RECORD;
TYPE sdctrl_out_type IS RECORD
sdcke : std_logic_vector ( 1 downto 0 );
sdcsn : std_logic_vector ( 1 downto 0 );
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector ( 15 downto 0 );
bdrive : std_ulogic;
qdrive : std_ulogic;
vbdrive : std_logic_vector ( 31 downto 0 );
address : std_logic_vector ( 16 downto 2 );
data : std_logic_vector ( 127 downto 0 );
cb : std_logic_vector ( 15 downto 0 );
ce : std_ulogic;
ba : std_logic_vector ( 1 downto 0 );
cal_en : std_logic_vector ( 7 downto 0 );
cal_inc : std_logic_vector ( 7 downto 0 );
cal_rst : std_logic;
odt : std_logic_vector ( 1 downto 0 );
END RECORD;
TYPE sdram_out_type IS RECORD
sdcke : std_logic_vector ( 1 downto 0 );
sdcsn : std_logic_vector ( 1 downto 0 );
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector ( 7 downto 0 );
END RECORD;
TYPE sdram_cfg_type IS RECORD
command : std_logic_vector ( 2 downto 0 );
csize : std_logic_vector ( 1 downto 0 );
bsize : std_logic_vector ( 2 downto 0 );
trcd : std_ulogic;
trfc : std_logic_vector ( 2 downto 0 );
trp : std_ulogic;
refresh : std_logic_vector ( 11 downto 0 );
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
END RECORD;
TYPE access_param IS RECORD
haddr : std_logic_vector ( 31 downto 0 );
size : std_logic_vector ( 1 downto 0 );
hwrite : std_ulogic;
hio : std_ulogic;
END RECORD;
TYPE ahb_reg_type IS RECORD
hready : std_ulogic;
hsel : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
ready : std_ulogic;
ready2 : std_ulogic;
write : std_logic_vector ( 3 downto 0 );
state : ahb_state_type;
haddr : std_logic_vector ( 31 downto 0 );
hrdata : std_logic_vector ( 31 downto 0 );
hwdata : std_logic_vector ( 31 downto 0 );
hwrite : std_ulogic;
htrans : std_logic_vector ( 1 downto 0 );
hresp : std_logic_vector ( 1 downto 0 );
raddr : std_logic_vector ( 6 - 1 downto 0 );
size : std_logic_vector ( 1 downto 0 );
acc : access_param;
END RECORD;
TYPE ddr_reg_type IS RECORD
startsd : std_ulogic;
startsdold : std_ulogic;
burst : std_ulogic;
hready : std_ulogic;
bdrive : std_ulogic;
qdrive : std_ulogic;
nbdrive : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
trfc : std_logic_vector ( 2 downto 0 );
refresh : std_logic_vector ( 11 downto 0 );
sdcsn : std_logic_vector ( 1 downto 0 );
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector ( 15 downto 0 );
address : std_logic_vector ( 15 downto 2 );
ba : std_logic_vector ( 1 downto 0 );
waddr : std_logic_vector ( 6 - 1 downto 0 );
cfg : sdram_cfg_type;
hrdata : std_logic_vector ( 127 downto 0 );
END RECORD;
SIGNAL vcc : std_ulogic;
SIGNAL r : ddr_reg_type;
SIGNAL ri : ddr_reg_type;
SIGNAL ra : ahb_reg_type;
SIGNAL rai : ahb_reg_type;
SIGNAL rbdrive : std_logic_vector ( 31 downto 0 );
SIGNAL ribdrive : std_logic_vector ( 31 downto 0 );
SIGNAL rdata : std_logic_vector ( 127 downto 0 );
SIGNAL wdata : std_logic_vector ( 127 downto 0 );
ATTRIBUTE syn_preserve : boolean;
ATTRIBUTE syn_preserve OF rbdrive : signal IS true;
BEGIN
vcc <= '1';
ahb_ctrl : PROCESS ( rst , ahbsi , r , ra , rdata )
VARIABLE v : ahb_reg_type;
VARIABLE startsd : std_ulogic;
VARIABLE dout : std_logic_vector ( 31 downto 0 );
BEGIN
v := ra;
v.hresp := "00";
v.write := "0000";
CASE ra.raddr ( 1 downto 0 ) IS
WHEN "00" =>
v.hrdata := rdata ( 127 downto 96 );
WHEN "01" =>
v.hrdata := rdata ( 95 downto 64 );
WHEN "10" =>
v.hrdata := rdata ( 63 downto 32 );
WHEN OTHERS =>
v.hrdata := rdata ( 31 downto 0 );
END CASE;
v.ready := not ( ra.startsd xor r.startsdold );
v.ready2 := ra.ready;
IF ( ( ahbsi.hready and ahbsi.hsel ( 3 ) ) = '1' ) THEN
v.htrans := ahbsi.htrans;
v.haddr := ahbsi.haddr;
v.size := ahbsi.hsize ( 1 downto 0 );
v.hwrite := ahbsi.hwrite;
IF ahbsi.htrans ( 1 ) = '1' THEN
v.hio := ahbsi.hmbsel ( 1 );
v.hsel := '1';
v.hready := '0';
END IF;
END IF;
IF ahbsi.hready = '1' THEN
v.hsel := ahbsi.hsel ( 3 );
END IF;
CASE ra.state IS
WHEN midle =>
IF ( ( v.hsel and v.htrans ( 1 ) ) = '1' ) THEN
IF v.hwrite = '0' THEN
v.state := rhold;
v.startsd := not ra.startsd;
ELSE
v.state := dwrite;
v.hready := '1';
v.write := decode ( v.haddr ( 3 downto 2 ) );
END IF;
END IF;
v.raddr := ra.haddr ( 7 downto 2 );
v.ready := '0';
v.ready2 := '0';
IF ahbsi.hready = '1' THEN
v.acc := ( v.haddr , v.size , v.hwrite , v.hio );
END IF;
WHEN rhold =>
v.raddr := ra.haddr ( 7 downto 2 );
IF ra.ready2 = '1' THEN
v.state := dread;
v.hready := '1';
v.raddr := ra.raddr + 1;
END IF;
WHEN dread =>
v.raddr := ra.raddr + 1;
v.hready := '1';
IF ( ( v.hsel and v.htrans ( 1 ) and v.htrans ( 0 ) ) = '0' ) or ( ra.raddr ( 2 downto 0 ) = "000" ) THEN
v.state := midle;
v.hready := '0';
END IF;
v.acc := ( v.haddr , v.size , v.hwrite , v.hio );
WHEN dwrite =>
v.raddr := ra.haddr ( 7 downto 2 );
v.hready := '1';
v.write := decode ( v.haddr ( 3 downto 2 ) );
IF ( ( v.hsel and v.htrans ( 1 ) and v.htrans ( 0 ) ) = '0' ) or ( ra.haddr ( 4 downto 2 ) = "111" ) THEN
v.startsd := not ra.startsd;
v.state := whold1;
v.write := "0000";
v.hready := '0';
END IF;
WHEN whold1 =>
v.state := whold2;
v.ready := '0';
WHEN whold2 =>
IF ra.ready = '1' THEN
v.state := midle;
v.acc := ( v.haddr , v.size , v.hwrite , v.hio );
END IF;
END CASE;
v.hwdata := ahbsi.hwdata;
IF ( ahbsi.hready and ahbsi.hsel ( 3 ) ) = '1' THEN
IF ahbsi.htrans ( 1 ) = '0' THEN
v.hready := '1';
END IF;
END IF;
dout := ra.hrdata ( 31 downto 0 );
IF rst = '0' THEN
v.hsel := '0';
v.hready := '1';
v.state := midle;
v.startsd := '0';
v.hio := '0';
END IF;
rai <= v;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not ra.hio;
END PROCESS;
ddr_ctrl : PROCESS ( rst , r , ra , sdi , rbdrive , wdata )
VARIABLE v : ddr_reg_type;
VARIABLE startsd : std_ulogic;
VARIABLE dqm : std_logic_vector ( 15 downto 0 );
VARIABLE raddr : std_logic_vector ( 13 downto 0 );
VARIABLE adec : std_ulogic;
VARIABLE rams : std_logic_vector ( 1 downto 0 );
VARIABLE ba : std_logic_vector ( 1 downto 0 );
VARIABLE haddr : std_logic_vector ( 31 downto 0 );
VARIABLE hsize : std_logic_vector ( 1 downto 0 );
VARIABLE hwrite : std_ulogic;
VARIABLE htrans : std_logic_vector ( 1 downto 0 );
VARIABLE hready : std_ulogic;
VARIABLE vbdrive : std_logic_vector ( 31 downto 0 );
VARIABLE bdrive : std_ulogic;
VARIABLE writecfg : std_ulogic;
VARIABLE regsd1 : std_logic_vector ( 31 downto 0 );
VARIABLE regsd2 : std_logic_vector ( 31 downto 0 );
BEGIN
v := r;
v.hready := '0';
writecfg := '0';
vbdrive := rbdrive;
v.hrdata := sdi.data;
v.qdrive := '0';
regsd1 := ( OTHERS => '0' );
regsd1 ( 31 downto 15 ) := r.cfg.refon & r.cfg.trp & r.cfg.trfc & r.cfg.trcd & r.cfg.bsize & r.cfg.csize & r.cfg.command & r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
regsd1 ( 11 downto 0 ) := r.cfg.refresh;
regsd2 := ( OTHERS => '0' );
regsd2 ( 8 downto 0 ) := conv_std_logic_vector ( 90 , 9 );
regsd2 ( 14 downto 12 ) := conv_std_logic_vector ( 3 , 3 );
CASE ra.acc.size IS
WHEN "00" =>
CASE ra.acc.haddr ( 3 downto 0 ) IS
WHEN "0000" =>
dqm := "0111111111111111";
WHEN "0001" =>
dqm := "1011111111111111";
WHEN "0010" =>
dqm := "1101111111111111";
WHEN "0011" =>
dqm := "1110111111111111";
WHEN "0100" =>
dqm := "1111011111111111";
WHEN "0101" =>
dqm := "1111101111111111";
WHEN "0110" =>
dqm := "1111110111111111";
WHEN "0111" =>
dqm := "1111111011111111";
WHEN "1000" =>
dqm := "1111111101111111";
WHEN "1001" =>
dqm := "1111111110111111";
WHEN "1010" =>
dqm := "1111111111011111";
WHEN "1011" =>
dqm := "1111111111101111";
WHEN "1100" =>
dqm := "1111111111110111";
WHEN "1101" =>
dqm := "1111111111111011";
WHEN "1110" =>
dqm := "1111111111111101";
WHEN OTHERS =>
dqm := "1111111111111110";
END CASE;
WHEN "01" =>
CASE ra.acc.haddr ( 3 downto 1 ) IS
WHEN "000" =>
dqm := "0011111111111111";
WHEN "001" =>
dqm := "1100111111111111";
WHEN "010" =>
dqm := "1111001111111111";
WHEN "011" =>
dqm := "1111110011111111";
WHEN "100" =>
dqm := "1111111100111111";
WHEN "101" =>
dqm := "1111111111001111";
WHEN "110" =>
dqm := "1111111111110011";
WHEN OTHERS =>
dqm := "1111111111111100";
END CASE;
WHEN OTHERS =>
dqm := "0000000000000000";
END CASE;
v.startsd := ra.startsd;
CASE r.mstate IS
WHEN midle =>
IF r.startsd = '1' THEN
IF ( r.sdstate = sidle ) and ( r.cfg.command = "000" ) and ( r.cmstate = midle ) THEN
startsd := '1';
v.mstate := active;
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
startsd := r.startsd xor r.startsdold;
haddr := ra.acc.haddr;
CASE r.cfg.csize IS
WHEN "00" =>
WHEN "01" =>
WHEN "10" =>
WHEN OTHERS =>
END CASE;
rams := adec & not adec;
IF r.trfc /= "000" THEN
v.trfc := r.trfc - 1;
END IF;
CASE r.sdstate IS
WHEN sidle =>
IF ( startsd = '1' ) and ( r.cfg.command = "000" ) and ( r.cmstate = midle ) and ( r.istate = finish ) THEN
v.address := raddr;
v.ba := ba;
IF ra.acc.hio = '0' THEN
v.sdcsn := not rams ( 1 downto 0 );
v.rasn := '0';
v.sdstate := act1;
ELSE
v.sdstate := ioreg1;
END IF;
END IF;
v.waddr := ra.acc.haddr ( 7 downto 2 );
WHEN act1 =>
v.rasn := '1';
v.trfc := r.cfg.trfc;
IF r.cfg.trcd = '1' THEN
v.sdstate := act2;
ELSE
v.sdstate := act3;
v.hready := ra.acc.hwrite;
END IF;
v.waddr := ra.acc.haddr ( 7 downto 2 );
WHEN act2 =>
v.sdstate := act3;
v.hready := ra.acc.hwrite;
WHEN act3 =>
v.casn := '0';
v.address := ra.acc.haddr ( 15 downto 13 ) & '0' & ra.acc.haddr ( 12 downto 4 ) & '0';
v.dqm := dqm;
IF ra.acc.hwrite = '1' THEN
v.waddr := r.waddr + 4;
v.waddr ( 1 downto 0 ) := "00";
v.sdstate := wr1;
v.sdwen := '0';
v.bdrive := '0';
v.qdrive := '1';
IF ( r.waddr /= ra.raddr ) THEN
v.hready := '1';
IF ( r.waddr ( 5 downto 2 ) = ra.raddr ( 5 downto 2 ) ) THEN
IF r.waddr ( 1 ) = '1' THEN
v.dqm ( 15 downto 8 ) := ( OTHERS => '1' );
ELSE
CASE ra.raddr ( 1 downto 0 ) IS
WHEN "01" =>
v.dqm ( 7 downto 0 ) := ( OTHERS => '1' );
WHEN "10" =>
v.dqm ( 3 downto 0 ) := ( OTHERS => '1' );
v.dqm ( 15 downto 12 ) := ( OTHERS => r.waddr ( 0 ) );
WHEN OTHERS =>
v.dqm ( 15 downto 12 ) := ( OTHERS => r.waddr ( 0 ) );
END CASE;
END IF;
ELSE
CASE r.waddr ( 1 downto 0 ) IS
WHEN "01" =>
v.dqm ( 15 downto 12 ) := ( OTHERS => '1' );
WHEN "10" =>
v.dqm ( 15 downto 8 ) := ( OTHERS => '1' );
WHEN "11" =>
v.dqm ( 15 downto 4 ) := ( OTHERS => '1' );
WHEN OTHERS =>
NULL;
END CASE;
END IF;
ELSE
CASE r.waddr ( 1 downto 0 ) IS
WHEN "00" =>
v.dqm ( 11 downto 0 ) := ( OTHERS => '1' );
WHEN "01" =>
v.dqm ( 15 downto 12 ) := ( OTHERS => '1' );
v.dqm ( 7 downto 0 ) := ( OTHERS => '1' );
WHEN "10" =>
v.dqm ( 15 downto 8 ) := ( OTHERS => '1' );
v.dqm ( 3 downto 0 ) := ( OTHERS => '1' );
WHEN OTHERS =>
v.dqm ( 15 downto 4 ) := ( OTHERS => '1' );
END CASE;
END IF;
ELSE
v.sdstate := rd1;
END IF;
WHEN wr1 =>
v.sdwen := '1';
v.casn := '1';
v.qdrive := '1';
v.waddr := r.waddr + 4;
v.dqm := ( OTHERS => '0' );
v.address ( 8 downto 3 ) := r.waddr;
IF ( r.waddr <= ra.raddr ) and ( r.waddr ( 5 downto 2 ) /= "0000" ) and ( r.hready = '1' ) THEN
v.hready := '1';
IF ( r.hready = '1' ) and ( r.waddr ( 2 downto 0 ) = "000" ) THEN
v.sdwen := '0';
v.casn := '0';
END IF;
IF ( r.waddr ( 5 downto 2 ) = ra.raddr ( 5 downto 2 ) ) and ( r.waddr /= "000000" ) THEN
CASE ra.raddr ( 1 downto 0 ) IS
WHEN "00" =>
v.dqm ( 11 downto 0 ) := ( OTHERS => '1' );
WHEN "01" =>
v.dqm ( 7 downto 0 ) := ( OTHERS => '1' );
WHEN "10" =>
v.dqm ( 3 downto 0 ) := ( OTHERS => '1' );
WHEN OTHERS =>
NULL;
END CASE;
END IF;
ELSE
v.sdstate := wr2;
v.dqm := ( OTHERS => '1' );
v.startsdold := r.startsd;
END IF;
WHEN wr2 =>
v.sdstate := wr3;
v.qdrive := '1';
WHEN wr3 =>
v.sdstate := wr4a;
v.qdrive := '1';
WHEN wr4a =>
v.bdrive := '1';
v.rasn := '0';
v.sdwen := '0';
v.sdstate := wr4;
v.qdrive := '1';
WHEN wr4 =>
v.sdcsn := "11";
v.rasn := '1';
v.sdwen := '1';
v.qdrive := '0';
v.sdstate := wr5;
WHEN wr5 =>
v.sdstate := sidle;
WHEN rd1 =>
v.casn := '1';
v.sdstate := rd7;
WHEN rd7 =>
v.casn := '1';
v.sdstate := rd2;
WHEN rd2 =>
v.casn := '1';
v.sdstate := rd3;
WHEN rd3 =>
IF 0 = 0 THEN
v.startsdold := r.startsd;
END IF;
v.sdstate := rd4;
v.hready := '1';
v.casn := '1';
IF v.hready = '1' THEN
v.waddr := r.waddr + 4;
END IF;
WHEN rd4 =>
v.hready := '1';
v.casn := '1';
IF ( r.sdcsn = "11" ) or ( r.waddr ( 2 downto 2 ) = "1" ) THEN
v.dqm := ( OTHERS => '1' );
v.burst := '0';
IF 0 /= 0 THEN
v.startsdold := r.startsd;
END IF;
IF ( r.sdcsn /= "11" ) THEN
v.rasn := '0';
v.sdwen := '0';
v.sdstate := rd5;
ELSE
IF r.cfg.trp = '1' THEN
v.sdstate := rd6;
ELSE
v.sdstate := sidle;
END IF;
END IF;
END IF;
IF v.hready = '1' THEN
v.waddr := r.waddr + 4;
END IF;
WHEN rd5 =>
IF r.cfg.trp = '1' THEN
v.sdstate := rd6;
ELSE
v.sdstate := sidle;
END IF;
v.sdcsn := ( OTHERS => '1' );
v.rasn := '1';
v.sdwen := '1';
v.dqm := ( OTHERS => '1' );
WHEN rd6 =>
v.sdstate := sidle;
v.dqm := ( OTHERS => '1' );
v.sdcsn := ( OTHERS => '1' );
v.rasn := '1';
v.sdwen := '1';
WHEN ioreg1 =>
v.hrdata ( 127 downto 64 ) := regsd1 & regsd2;
v.sdstate := ioreg2;
IF ra.acc.hwrite = '0' THEN
v.hready := '1';
END IF;
WHEN ioreg2 =>
writecfg := ra.acc.hwrite and not r.waddr ( 0 );
v.startsdold := r.startsd;
v.sdstate := sidle;
WHEN OTHERS =>
v.sdstate := sidle;
END CASE;
CASE r.cmstate IS
WHEN midle =>
IF r.sdstate = sidle THEN
CASE r.cfg.command IS
WHEN "010" =>
v.sdcsn := ( OTHERS => '0' );
v.rasn := '0';
v.sdwen := '0';
v.address ( 12 ) := '1';
v.cmstate := active;
WHEN "100" =>
v.sdcsn := ( OTHERS => '0' );
v.rasn := '0';
v.casn := '0';
v.cmstate := active;
WHEN "111" =>
v.sdcsn := ( OTHERS => '0' );
v.rasn := '0';
v.casn := '0';
v.sdwen := '0';
v.cmstate := active;
v.ba := "01";
v.address := "00000000000000";
WHEN "110" =>
v.sdcsn := ( OTHERS => '0' );
v.rasn := '0';
v.casn := '0';
v.sdwen := '0';
v.cmstate := active;
v.ba := "00";
v.address := "00000" & r.cfg.dllrst & "0" & "01" & "00010";
WHEN OTHERS =>
NULL;
END CASE;
END IF;
WHEN active =>
v.sdcsn := ( OTHERS => '1' );
v.rasn := '1';
v.casn := '1';
v.sdwen := '1';
v.cfg.command := "000";
v.cmstate := leadout;
v.trfc := r.cfg.trfc;
WHEN OTHERS =>
IF r.trfc = "000" THEN
v.cmstate := midle;
END IF;
END CASE;
CASE r.istate IS
WHEN iidle =>
IF r.cfg.renable = '1' THEN
v.cfg.cke := '1';
v.cfg.dllrst := '1';
IF r.cfg.cke = '1' THEN
v.istate := pre;
v.cfg.command := "010";
END IF;
v.ba := "00";
END IF;
WHEN pre =>
IF r.cfg.command = "000" THEN
v.cfg.command := "11" & r.cfg.dllrst;
IF r.cfg.dllrst = '1' THEN
v.istate := emode;
ELSE
v.istate := lmode;
END IF;
END IF;
WHEN emode =>
IF r.cfg.command = "000" THEN
v.istate := lmode;
v.cfg.command := "110";
END IF;
WHEN lmode =>
IF r.cfg.command = "000" THEN
IF r.cfg.dllrst = '1' THEN
IF r.refresh ( 9 downto 8 ) = "00" THEN
v.cfg.command := "010";
v.istate := ref1;
END IF;
ELSE
v.istate := finish;
v.cfg.refon := '1';
v.cfg.renable := '0';
END IF;
END IF;
WHEN ref1 =>
IF r.cfg.command = "000" THEN
v.cfg.command := "100";
v.cfg.dllrst := '0';
v.istate := ref2;
END IF;
WHEN ref2 =>
IF r.cfg.command = "000" THEN
v.cfg.command := "100";
v.istate := pre;
END IF;
WHEN OTHERS =>
IF r.cfg.renable = '1' THEN
v.istate := iidle;
v.cfg.dllrst := '1';
END IF;
END CASE;
CASE r.mstate IS
WHEN active =>
IF v.hready = '1' THEN
v.mstate := midle;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
IF ( ( r.cfg.refon = '1' ) and ( r.istate = finish ) ) or ( r.cfg.dllrst = '1' ) THEN
v.refresh := r.refresh - 1;
IF ( v.refresh ( 11 ) and not r.refresh ( 11 ) ) = '1' THEN
v.refresh := r.cfg.refresh;
IF r.cfg.dllrst = '0' THEN
v.cfg.command := "100";
END IF;
END IF;
END IF;
IF ( ra.acc.hio and ra.acc.hwrite and writecfg ) = '1' THEN
v.cfg.refresh := wdata ( 11 + 96 downto 0 + 96 );
v.cfg.cke := wdata ( 15 + 96 );
v.cfg.renable := wdata ( 16 + 96 );
v.cfg.dllrst := wdata ( 17 + 96 );
v.cfg.command := wdata ( 20 + 96 downto 18 + 96 );
v.cfg.csize := wdata ( 22 + 96 downto 21 + 96 );
v.cfg.bsize := wdata ( 25 + 96 downto 23 + 96 );
v.cfg.trcd := wdata ( 26 + 96 );
v.cfg.trfc := wdata ( 29 + 96 downto 27 + 96 );
v.cfg.trp := wdata ( 30 + 96 );
v.cfg.refon := wdata ( 31 + 96 );
END IF;
v.nbdrive := not v.bdrive;
IF 0 = 1 THEN
bdrive := r.nbdrive;
vbdrive := ( OTHERS => v.nbdrive );
ELSE
bdrive := r.bdrive;
vbdrive := ( OTHERS => v.bdrive );
END IF;
IF rst = '0' THEN
v.sdstate := sidle;
v.mstate := midle;
v.istate := finish;
v.cmstate := midle;
v.cfg.command := "000";
v.cfg.csize := conv_std_logic_vector ( 9 - 9 , 2 );
v.cfg.bsize := conv_std_logic_vector ( log2 ( 256 / 8 ) , 3 );
IF 90 > 100 THEN
v.cfg.trcd := '1';
ELSE
v.cfg.trcd := '0';
END IF;
v.cfg.refon := '0';
v.cfg.trfc := conv_std_logic_vector ( 75 * 90 / 1000 - 2 , 3 );
v.cfg.refresh := conv_std_logic_vector ( 7800 * 90 / 1000 , 12 );
v.refresh := ( OTHERS => '0' );
IF 1 = 1 THEN
v.cfg.renable := '1';
ELSE
v.cfg.renable := '0';
END IF;
IF 90 > 100 THEN
v.cfg.trp := '1';
ELSE
v.cfg.trp := '0';
END IF;
v.dqm := ( OTHERS => '1' );
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '0';
v.startsd := '0';
v.startsdold := '0';
v.cfg.dllrst := '0';
v.cfg.cke := '0';
END IF;
ri <= v;
ribdrive <= vbdrive;
END PROCESS;
sdo.sdcke <= ( OTHERS => r.cfg.cke );
ahbso.hconfig <= ( 0 => AHB_DEVICE_REG ( VENDOR_GAISLER , GAISLER_DDRSP , 0 , 0 , 0 ) , 4 => AHB_MEMBAR ( 1024 , '1' , '1' , 3072 ) , 5 => AHB_IOBAR ( 1 , 4095 ) , OTHERS => ZERO32 );
ahbso.hirq <= ( OTHERS => '0' );
ahbso.hindex <= 3;
ahbregs : PROCESS ( clk_ahb )
BEGIN
IF rising_edge ( clk_ahb ) THEN
ra <= rai;
END IF;
END PROCESS;
ddrregs : PROCESS ( clk_ddr , rst )
BEGIN
IF rising_edge ( clk_ddr ) THEN
r <= ri;
rbdrive <= ribdrive;
END IF;
IF ( rst = '0' ) THEN
r.sdcsn <= ( OTHERS => '1' );
r.bdrive <= '1';
r.nbdrive <= '0';
IF 0 = 0 THEN
rbdrive <= ( OTHERS => '1' );
ELSE
rbdrive <= ( OTHERS => '0' );
END IF;
r.cfg.cke <= '0';
END IF;
END PROCESS;
sdo.address <= '0' & ri.address;
sdo.ba <= ri.ba;
sdo.bdrive <= r.nbdrive WHEN 0 = 1 ELSE r.bdrive;
sdo.qdrive <= not ( ri.qdrive or r.nbdrive );
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= ri.sdcsn;
sdo.sdwen <= ri.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= ri.rasn;
sdo.casn <= ri.casn;
sdo.data <= wdata;
read_buff : COMPONENT syncram_2p
GENERIC MAP (
tech => 0 , abits => 4 , dbits => 128 , sepclk => 1 , wrfst => 0
) PORT MAP (
rclk => clk_ahb , renable => vcc , raddress => rai.raddr ( 5 downto 2 ) , dataout => rdata , wclk => clk_ddr , write => ri.hready , waddress => r.waddr ( 5 downto 2 ) , datain => ri.hrdata
)
;
write_buff1 : COMPONENT syncram_2p
GENERIC MAP (
tech => 0 , abits => 4 , dbits => 32 , sepclk => 1 , wrfst => 0
) PORT MAP (
rclk => clk_ddr , renable => vcc , raddress => r.waddr ( 5 downto 2 ) , dataout => wdata ( 127 downto 96 ) , wclk => clk_ahb , write => ra.write ( 0 ) , waddress => ra.haddr ( 7 downto 4 ) , datain => ahbsi.hwdata
)
;
write_buff2 : COMPONENT syncram_2p
GENERIC MAP (
tech => 0 , abits => 4 , dbits => 32 , sepclk => 1 , wrfst => 0
) PORT MAP (
rclk => clk_ddr , renable => vcc , raddress => r.waddr ( 5 downto 2 ) , dataout => wdata ( 95 downto 64 ) , wclk => clk_ahb , write => ra.write ( 1 ) , waddress => ra.haddr ( 7 downto 4 ) , datain => ahbsi.hwdata
)
;
write_buff3 : COMPONENT syncram_2p
GENERIC MAP (
tech => 0 , abits => 4 , dbits => 32 , sepclk => 1 , wrfst => 0
) PORT MAP (
rclk => clk_ddr , renable => vcc , raddress => r.waddr ( 5 downto 2 ) , dataout => wdata ( 63 downto 32 ) , wclk => clk_ahb , write => ra.write ( 2 ) , waddress => ra.haddr ( 7 downto 4 ) , datain => ahbsi.hwdata
)
;
write_buff4 : COMPONENT syncram_2p
GENERIC MAP (
tech => 0 , abits => 4 , dbits => 32 , sepclk => 1 , wrfst => 0
) PORT MAP (
rclk => clk_ddr , renable => vcc , raddress => r.waddr ( 5 downto 2 ) , dataout => wdata ( 31 downto 0 ) , wclk => clk_ahb , write => ra.write ( 3 ) , waddress => ra.haddr ( 7 downto 4 ) , datain => ahbsi.hwdata
)
;
bootmsg : COMPONENT report_version
GENERIC MAP (
msg1 => "ddrsp" & tost ( 3 ) & ": 64-bit DDR266 controller rev " & tost ( 0 ) & ", " & tost ( 256 ) & " Mbyte, " & tost ( 90 ) & " MHz DDR clock"
)
;
END ARCHITECTURE;
|
entity case4 is
end entity;
architecture test of case4 is
constant c1 : bit_vector(7 downto 0) := X"ab";
constant c2 : bit_vector(7 downto 0) := X"62";
signal s : bit_vector(7 downto 0);
signal x, y : natural;
begin
process (s) is
begin
case s is
when c1 =>
x <= x + 1;
when c2 | X"50" =>
y <= y + 1;
when others =>
null;
end case;
end process;
process is
variable v : bit_vector(1 to 6);
begin
s <= c1;
wait for 1 ns;
s <= c2;
wait for 1 ns;
s <= X"63";
wait for 1 ns;
s <= X"50";
wait for 1 ns;
assert x = 1;
assert y = 2;
v := "000100";
case v is
when "000100" =>
null;
when others =>
assert false;
end case;
wait;
end process;
end architecture;
|
entity case4 is
end entity;
architecture test of case4 is
constant c1 : bit_vector(7 downto 0) := X"ab";
constant c2 : bit_vector(7 downto 0) := X"62";
signal s : bit_vector(7 downto 0);
signal x, y : natural;
begin
process (s) is
begin
case s is
when c1 =>
x <= x + 1;
when c2 | X"50" =>
y <= y + 1;
when others =>
null;
end case;
end process;
process is
variable v : bit_vector(1 to 6);
begin
s <= c1;
wait for 1 ns;
s <= c2;
wait for 1 ns;
s <= X"63";
wait for 1 ns;
s <= X"50";
wait for 1 ns;
assert x = 1;
assert y = 2;
v := "000100";
case v is
when "000100" =>
null;
when others =>
assert false;
end case;
wait;
end process;
end architecture;
|
entity case4 is
end entity;
architecture test of case4 is
constant c1 : bit_vector(7 downto 0) := X"ab";
constant c2 : bit_vector(7 downto 0) := X"62";
signal s : bit_vector(7 downto 0);
signal x, y : natural;
begin
process (s) is
begin
case s is
when c1 =>
x <= x + 1;
when c2 | X"50" =>
y <= y + 1;
when others =>
null;
end case;
end process;
process is
variable v : bit_vector(1 to 6);
begin
s <= c1;
wait for 1 ns;
s <= c2;
wait for 1 ns;
s <= X"63";
wait for 1 ns;
s <= X"50";
wait for 1 ns;
assert x = 1;
assert y = 2;
v := "000100";
case v is
when "000100" =>
null;
when others =>
assert false;
end case;
wait;
end process;
end architecture;
|
entity case4 is
end entity;
architecture test of case4 is
constant c1 : bit_vector(7 downto 0) := X"ab";
constant c2 : bit_vector(7 downto 0) := X"62";
signal s : bit_vector(7 downto 0);
signal x, y : natural;
begin
process (s) is
begin
case s is
when c1 =>
x <= x + 1;
when c2 | X"50" =>
y <= y + 1;
when others =>
null;
end case;
end process;
process is
variable v : bit_vector(1 to 6);
begin
s <= c1;
wait for 1 ns;
s <= c2;
wait for 1 ns;
s <= X"63";
wait for 1 ns;
s <= X"50";
wait for 1 ns;
assert x = 1;
assert y = 2;
v := "000100";
case v is
when "000100" =>
null;
when others =>
assert false;
end case;
wait;
end process;
end architecture;
|
entity case4 is
end entity;
architecture test of case4 is
constant c1 : bit_vector(7 downto 0) := X"ab";
constant c2 : bit_vector(7 downto 0) := X"62";
signal s : bit_vector(7 downto 0);
signal x, y : natural;
begin
process (s) is
begin
case s is
when c1 =>
x <= x + 1;
when c2 | X"50" =>
y <= y + 1;
when others =>
null;
end case;
end process;
process is
variable v : bit_vector(1 to 6);
begin
s <= c1;
wait for 1 ns;
s <= c2;
wait for 1 ns;
s <= X"63";
wait for 1 ns;
s <= X"50";
wait for 1 ns;
assert x = 1;
assert y = 2;
v := "000100";
case v is
when "000100" =>
null;
when others =>
assert false;
end case;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity ip is port
(
ct : in std_logic_vector(1 TO 64);
l0x : out std_logic_vector(1 TO 32);
r0x : out std_logic_vector(1 TO 32)
);
end ip;
architecture behavior of ip is
begin
l0x(1)<=ct(58); l0x(2)<=ct(50); l0x(3)<=ct(42); l0x(4)<=ct(34); l0x(5)<=ct(26); l0x(6)<=ct(18); l0x(7)<=ct(10); l0x(8)<=ct(2);
l0x(9)<=ct(60); l0x(10)<=ct(52); l0x(11)<=ct(44); l0x(12)<=ct(36); l0x(13)<=ct(28); l0x(14)<=ct(20); l0x(15)<=ct(12); l0x(16)<=ct(4);
l0x(17)<=ct(62); l0x(18)<=ct(54); l0x(19)<=ct(46); l0x(20)<=ct(38); l0x(21)<=ct(30); l0x(22)<=ct(22); l0x(23)<=ct(14); l0x(24)<=ct(6);
l0x(25)<=ct(64); l0x(26)<=ct(56); l0x(27)<=ct(48); l0x(28)<=ct(40); l0x(29)<=ct(32); l0x(30)<=ct(24); l0x(31)<=ct(16); l0x(32)<=ct(8);
r0x(1)<=ct(57); r0x(2)<=ct(49); r0x(3)<=ct(41); r0x(4)<=ct(33); r0x(5)<=ct(25); r0x(6)<=ct(17); r0x(7)<=ct(9); r0x(8)<=ct(1);
r0x(9)<=ct(59); r0x(10)<=ct(51); r0x(11)<=ct(43); r0x(12)<=ct(35); r0x(13)<=ct(27); r0x(14)<=ct(19); r0x(15)<=ct(11); r0x(16)<=ct(3);
r0x(17)<=ct(61); r0x(18)<=ct(53); r0x(19)<=ct(45); r0x(20)<=ct(37); r0x(21)<=ct(29); r0x(22)<=ct(21); r0x(23)<=ct(13); r0x(24)<=ct(5);
r0x(25)<=ct(63); r0x(26)<=ct(55); r0x(27)<=ct(47); r0x(28)<=ct(39); r0x(29)<=ct(31); r0x(30)<=ct(23); r0x(31)<=ct(15); r0x(32)<=ct(7);
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
entity ip is port
(
ct : in std_logic_vector(1 TO 64);
l0x : out std_logic_vector(1 TO 32);
r0x : out std_logic_vector(1 TO 32)
);
end ip;
architecture behavior of ip is
begin
l0x(1)<=ct(58); l0x(2)<=ct(50); l0x(3)<=ct(42); l0x(4)<=ct(34); l0x(5)<=ct(26); l0x(6)<=ct(18); l0x(7)<=ct(10); l0x(8)<=ct(2);
l0x(9)<=ct(60); l0x(10)<=ct(52); l0x(11)<=ct(44); l0x(12)<=ct(36); l0x(13)<=ct(28); l0x(14)<=ct(20); l0x(15)<=ct(12); l0x(16)<=ct(4);
l0x(17)<=ct(62); l0x(18)<=ct(54); l0x(19)<=ct(46); l0x(20)<=ct(38); l0x(21)<=ct(30); l0x(22)<=ct(22); l0x(23)<=ct(14); l0x(24)<=ct(6);
l0x(25)<=ct(64); l0x(26)<=ct(56); l0x(27)<=ct(48); l0x(28)<=ct(40); l0x(29)<=ct(32); l0x(30)<=ct(24); l0x(31)<=ct(16); l0x(32)<=ct(8);
r0x(1)<=ct(57); r0x(2)<=ct(49); r0x(3)<=ct(41); r0x(4)<=ct(33); r0x(5)<=ct(25); r0x(6)<=ct(17); r0x(7)<=ct(9); r0x(8)<=ct(1);
r0x(9)<=ct(59); r0x(10)<=ct(51); r0x(11)<=ct(43); r0x(12)<=ct(35); r0x(13)<=ct(27); r0x(14)<=ct(19); r0x(15)<=ct(11); r0x(16)<=ct(3);
r0x(17)<=ct(61); r0x(18)<=ct(53); r0x(19)<=ct(45); r0x(20)<=ct(37); r0x(21)<=ct(29); r0x(22)<=ct(21); r0x(23)<=ct(13); r0x(24)<=ct(5);
r0x(25)<=ct(63); r0x(26)<=ct(55); r0x(27)<=ct(47); r0x(28)<=ct(39); r0x(29)<=ct(31); r0x(30)<=ct(23); r0x(31)<=ct(15); r0x(32)<=ct(7);
end behavior; |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.types.all;
ENTITY test_types IS
END test_types;
ARCHITECTURE behavior OF test_types IS
signal tested_num : integer range 0 to 127;
signal tested_num2 : integer range 0 to 127;
signal tested_short_char : short_character;
BEGIN
stim_proc: process
begin
for i in 0 to 127 loop
tested_num <= i;
tested_short_char <= character_conv_table (i);
wait for 1 ns;
tested_num2 <= short_character'pos (tested_short_char);
wait for 1 ns;
assert tested_num = tested_num2;
assert tested_short_char = short_character'val (i);
end loop;
wait;
end process;
END;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_shadow_ok_8_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_ok_8_e-rtl-a.vhd,v 1.1 2006/11/22 10:40:10 wig Exp $
-- $Date: 2006/11/22 10:40:10 $
-- $Log: inst_shadow_ok_8_e-rtl-a.vhd,v $
-- Revision 1.1 2006/11/22 10:40:10 wig
-- Detect missing directories and flag that as error.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.99 2006/11/02 15:37:48 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_shadow_ok_8_e
--
architecture rtl of inst_shadow_ok_8_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad
-- File: iopad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: io pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iopad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iopad is
signal oen : std_ulogic;
begin
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_pads(tech) = 0 generate
pad <= i after 2 ns when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z' after 2 ns;
o <= to_X01(pad) after 1 ns;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or
(tech = virtex4) or (tech = spartan3e) or (tech = virtex5)
generate
x0 : virtex_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
axc : if (tech = axcel) or (tech = proasic) or (tech = apa3) generate
x0 : axcel_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
um : if (tech = umc) generate
x0 : umc_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (pad, i, oen, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (level, slew, voltage, strength)
port map(pad, i, oen, o);
end generate;
nex : if (tech = easic90) generate
x0 : nextreme_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopadv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en, o(j));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopadvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en(j), o(j));
end generate;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad
-- File: iopad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: io pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iopad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iopad is
signal oen : std_ulogic;
begin
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_pads(tech) = 0 generate
pad <= i after 2 ns when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z' after 2 ns;
o <= to_X01(pad) after 1 ns;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or
(tech = virtex4) or (tech = spartan3e) or (tech = virtex5)
generate
x0 : virtex_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
axc : if (tech = axcel) or (tech = proasic) or (tech = apa3) generate
x0 : axcel_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
um : if (tech = umc) generate
x0 : umc_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (pad, i, oen, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (level, slew, voltage, strength)
port map(pad, i, oen, o);
end generate;
nex : if (tech = easic90) generate
x0 : nextreme_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopadv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en, o(j));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopadvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en(j), o(j));
end generate;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity ent is
generic (
g : natural := 8
);
port (
o1 : out std_logic;
o2 : out std_logic
);
end;
architecture a of ent is
constant x : real := real(g);
constant a : natural := g;
constant y : real := real(a);
begin
o1 <= '1' when integer(x) = 8 else '0';
o2 <= '1' when integer(y) = 8 else '0';
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 1;
constant CFG_AHB_MONERR : integer := 1;
constant CFG_AHB_MONWAR : integer := 1;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#02007A#;
constant CFG_ETH_ENL : integer := 16#CC0001#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (200);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (512);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 64;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpuino_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
entity zpuino_spi is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
enabled: out std_logic
);
end entity zpuino_spi;
architecture behave of zpuino_spi is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
begin
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
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`protect end_protected
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:51:42 01/14/2015
-- Design Name:
-- Module Name: sseg_4x - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_utils_pack.all ;
entity sseg_4x is
generic(
clock_freq_hz : natural := 100_000_000;
refresh_rate_hz : natural := 100
);
port(
clk, reset : in std_logic ;
bcd_in : in std_logic_vector(15 downto 0);
-- SSEG to EDU from Host
sseg_cathode_out : out std_logic_vector(4 downto 0); -- common cathode
sseg_anode_out : out std_logic_vector(7 downto 0) -- sseg anode
);
end sseg_4x;
architecture Behavioral of sseg_4x is
constant clk_divider : positive := clock_freq_hz/(refresh_rate_hz*5);
signal divider_counter : std_logic_vector(nbit(clk_divider)-1 downto 0);
signal divider_end : std_logic ;
signal cathode_buffer : std_logic_vector(4 downto 0);
signal segs : slv8_array(0 to 3) ;
begin
gen_seg_decoder : for i in 0 to 3 generate
with bcd_in(((i+1)*4)-1 downto (i*4)) select
segs(i) <= X"3F" when "0000",
X"06" when "0001",
X"5B" when "0010",
X"4F" when "0011",
X"66" when "0100",
X"6D" when "0101",
X"7D" when "0110",
X"07" when "0111",
X"7F" when "1000",
X"6F" when "1001",
X"77" when "1010",
X"7C" when "1011",
X"39" when "1100",
X"5E" when "1101",
X"79" when "1110",
X"71" when others;
end generate ;
-- sseg logic
process(clk, reset)
begin
if reset = '1' then
divider_counter <= std_logic_vector(to_unsigned(clk_divider, nbit(clk_divider)));
elsif clk'event and clk = '1' then
if divider_counter = 0 then
divider_counter <= std_logic_vector(to_unsigned(clk_divider, nbit(clk_divider)));
else
divider_counter <= divider_counter - 1 ;
end if ;
end if ;
end process ;
divider_end <= '1' when divider_counter = 0 else
'0' ;
process(clk, reset)
begin
if reset = '1' then
cathode_buffer(0) <= '1' ;
cathode_buffer(4 downto 1) <= (others => '0');
elsif clk'event and clk = '1' then
if divider_end = '1' then
cathode_buffer(4 downto 1) <= cathode_buffer(3 downto 0);
cathode_buffer(0) <= cathode_buffer(4);
end if ;
end if ;
end process ;
with cathode_buffer select
sseg_anode_out <= segs(0) when "01000",
segs(1) when "00100",
segs(2) when "00010",
segs(3) when "00001",
(others => '0') when others ;
sseg_cathode_out <= cathode_buffer ;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:51:42 01/14/2015
-- Design Name:
-- Module Name: sseg_4x - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_utils_pack.all ;
entity sseg_4x is
generic(
clock_freq_hz : natural := 100_000_000;
refresh_rate_hz : natural := 100
);
port(
clk, reset : in std_logic ;
bcd_in : in std_logic_vector(15 downto 0);
-- SSEG to EDU from Host
sseg_cathode_out : out std_logic_vector(4 downto 0); -- common cathode
sseg_anode_out : out std_logic_vector(7 downto 0) -- sseg anode
);
end sseg_4x;
architecture Behavioral of sseg_4x is
constant clk_divider : positive := clock_freq_hz/(refresh_rate_hz*5);
signal divider_counter : std_logic_vector(nbit(clk_divider)-1 downto 0);
signal divider_end : std_logic ;
signal cathode_buffer : std_logic_vector(4 downto 0);
signal segs : slv8_array(0 to 3) ;
begin
gen_seg_decoder : for i in 0 to 3 generate
with bcd_in(((i+1)*4)-1 downto (i*4)) select
segs(i) <= X"3F" when "0000",
X"06" when "0001",
X"5B" when "0010",
X"4F" when "0011",
X"66" when "0100",
X"6D" when "0101",
X"7D" when "0110",
X"07" when "0111",
X"7F" when "1000",
X"6F" when "1001",
X"77" when "1010",
X"7C" when "1011",
X"39" when "1100",
X"5E" when "1101",
X"79" when "1110",
X"71" when others;
end generate ;
-- sseg logic
process(clk, reset)
begin
if reset = '1' then
divider_counter <= std_logic_vector(to_unsigned(clk_divider, nbit(clk_divider)));
elsif clk'event and clk = '1' then
if divider_counter = 0 then
divider_counter <= std_logic_vector(to_unsigned(clk_divider, nbit(clk_divider)));
else
divider_counter <= divider_counter - 1 ;
end if ;
end if ;
end process ;
divider_end <= '1' when divider_counter = 0 else
'0' ;
process(clk, reset)
begin
if reset = '1' then
cathode_buffer(0) <= '1' ;
cathode_buffer(4 downto 1) <= (others => '0');
elsif clk'event and clk = '1' then
if divider_end = '1' then
cathode_buffer(4 downto 1) <= cathode_buffer(3 downto 0);
cathode_buffer(0) <= cathode_buffer(4);
end if ;
end if ;
end process ;
with cathode_buffer select
sseg_anode_out <= segs(0) when "01000",
segs(1) when "00100",
segs(2) when "00010",
segs(3) when "00001",
(others => '0') when others ;
sseg_cathode_out <= cathode_buffer ;
end Behavioral;
|
component nios_design is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component nios_design;
u0 : component nios_design
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
);
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------------------------------------
entity Gate_XNOR is
Port
(
A : in STD_LOGIC;
B : in STD_LOGIC;
Z : out STD_LOGIC
);
end Gate_XNOR;
----------------------------------------------------------------------------------
architecture Behavioral of Gate_XNOR is
begin
Z <= A xnor B;
end Behavioral;
|
-- SIMON 64/128
-- key scheduling function
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- r: round index
-- k_0..k_3: key
-- subkey_out: round subkey
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity key_schedule is
port (
k_in_0 : in std_logic_vector(31 downto 0);
k_in_1 : in std_logic_vector(31 downto 0);
k_in_2 : in std_logic_vector(31 downto 0);
k_in_3 : in std_logic_vector(31 downto 0);
k_0 : out std_logic_vector(31 downto 0);
k_1 : out std_logic_vector(31 downto 0);
k_2 : out std_logic_vector(31 downto 0);
k_3 : out std_logic_vector(31 downto 0);
k_4 : out std_logic_vector(31 downto 0);
k_5 : out std_logic_vector(31 downto 0);
k_6 : out std_logic_vector(31 downto 0);
k_7 : out std_logic_vector(31 downto 0);
k_8 : out std_logic_vector(31 downto 0);
k_9 : out std_logic_vector(31 downto 0);
k_10 : out std_logic_vector(31 downto 0);
k_11 : out std_logic_vector(31 downto 0);
k_12 : out std_logic_vector(31 downto 0);
k_13 : out std_logic_vector(31 downto 0);
k_14 : out std_logic_vector(31 downto 0);
k_15 : out std_logic_vector(31 downto 0);
k_16 : out std_logic_vector(31 downto 0);
k_17 : out std_logic_vector(31 downto 0);
k_18 : out std_logic_vector(31 downto 0);
k_19 : out std_logic_vector(31 downto 0);
k_20 : out std_logic_vector(31 downto 0);
k_21 : out std_logic_vector(31 downto 0);
k_22 : out std_logic_vector(31 downto 0);
k_23 : out std_logic_vector(31 downto 0);
k_24 : out std_logic_vector(31 downto 0);
k_25 : out std_logic_vector(31 downto 0);
k_26 : out std_logic_vector(31 downto 0);
k_27 : out std_logic_vector(31 downto 0);
k_28 : out std_logic_vector(31 downto 0);
k_29 : out std_logic_vector(31 downto 0);
k_30 : out std_logic_vector(31 downto 0);
k_31 : out std_logic_vector(31 downto 0);
k_32 : out std_logic_vector(31 downto 0);
k_33 : out std_logic_vector(31 downto 0);
k_34 : out std_logic_vector(31 downto 0);
k_35 : out std_logic_vector(31 downto 0);
k_36 : out std_logic_vector(31 downto 0);
k_37 : out std_logic_vector(31 downto 0);
k_38 : out std_logic_vector(31 downto 0);
k_39 : out std_logic_vector(31 downto 0);
k_40 : out std_logic_vector(31 downto 0);
k_41 : out std_logic_vector(31 downto 0);
k_42 : out std_logic_vector(31 downto 0);
k_43 : out std_logic_vector(31 downto 0));
end key_schedule;
architecture Behavioral of key_schedule is
signal int_0 : std_logic_vector(31 downto 0);
signal int_1 : std_logic_vector(31 downto 0);
signal int_2 : std_logic_vector(31 downto 0);
signal int_3 : std_logic_vector(31 downto 0);
signal int_4 : std_logic_vector(31 downto 0);
signal int_5 : std_logic_vector(31 downto 0);
signal int_6 : std_logic_vector(31 downto 0);
signal int_7 : std_logic_vector(31 downto 0);
signal int_8 : std_logic_vector(31 downto 0);
signal int_9 : std_logic_vector(31 downto 0);
signal int_10 : std_logic_vector(31 downto 0);
signal int_11 : std_logic_vector(31 downto 0);
signal int_12 : std_logic_vector(31 downto 0);
signal int_13 : std_logic_vector(31 downto 0);
signal int_14 : std_logic_vector(31 downto 0);
signal int_15 : std_logic_vector(31 downto 0);
signal int_16 : std_logic_vector(31 downto 0);
signal int_17 : std_logic_vector(31 downto 0);
signal int_18 : std_logic_vector(31 downto 0);
signal int_19 : std_logic_vector(31 downto 0);
signal int_20 : std_logic_vector(31 downto 0);
signal int_21 : std_logic_vector(31 downto 0);
signal int_22 : std_logic_vector(31 downto 0);
signal int_23 : std_logic_vector(31 downto 0);
signal int_24 : std_logic_vector(31 downto 0);
signal int_25 : std_logic_vector(31 downto 0);
signal int_26 : std_logic_vector(31 downto 0);
signal int_27 : std_logic_vector(31 downto 0);
signal int_28 : std_logic_vector(31 downto 0);
signal int_29 : std_logic_vector(31 downto 0);
signal int_30 : std_logic_vector(31 downto 0);
signal int_31 : std_logic_vector(31 downto 0);
signal int_32 : std_logic_vector(31 downto 0);
signal int_33 : std_logic_vector(31 downto 0);
signal int_34 : std_logic_vector(31 downto 0);
signal int_35 : std_logic_vector(31 downto 0);
signal int_36 : std_logic_vector(31 downto 0);
signal int_37 : std_logic_vector(31 downto 0);
signal int_38 : std_logic_vector(31 downto 0);
signal int_39 : std_logic_vector(31 downto 0);
signal int_40 : std_logic_vector(31 downto 0);
signal int_41 : std_logic_vector(31 downto 0);
signal int_42 : std_logic_vector(31 downto 0);
signal int_43 : std_logic_vector(31 downto 0);
signal op_3_s : std_logic_vector(31 downto 0);
signal op_xor_0 : std_logic_vector(31 downto 0);
signal op_1_s : std_logic_vector(31 downto 0);
signal c_const : std_logic_vector(30 downto 0);
signal sequence : std_logic_vector(61 downto 0);
begin
-- C ^ sequence[(r-4) % 62]
sequence <= "11110000101100111001010001001000000111101001100011010111011011"; -- z3
c_const <= "1111111111111111111111111111110";
-- Round 0 to 3
k_0 <= k_in_0;
int_0 <= k_in_0;
k_1 <= k_in_1;
int_1 <= k_in_1;
k_2 <= k_in_2;
int_2 <= k_in_2;
k_3 <= k_in_3;
int_3 <= k_in_3;
-- Round 4
int_4 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_3), 3)) xor int_1)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_3), 3)) xor int_1)
xor int_0 xor (c_const & sequence(0)));
k_4 <= int_4;
-- Round 5
int_5 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_4), 3)) xor int_2)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_4), 3)) xor int_2)
xor int_1 xor (c_const & sequence(1)));
k_5 <= int_5;
-- Round 6
int_6 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_5), 3)) xor int_3)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_5), 3)) xor int_3)
xor int_2 xor (c_const & sequence(2)));
k_6 <= int_6;
-- Round 7
int_7 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_6), 3)) xor int_4)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_6), 3)) xor int_4)
xor int_3 xor (c_const & sequence(3)));
k_7 <= int_7;
-- Round 8
int_8 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_7), 3)) xor int_5)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_7), 3)) xor int_5)
xor int_4 xor (c_const & sequence(4)));
k_8 <= int_8;
-- Round 9
int_9 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_8), 3)) xor int_6)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_8), 3)) xor int_6)
xor int_5 xor (c_const & sequence(5)));
k_9 <= int_9;
-- Round 10
int_10 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_9), 3)) xor int_7)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_9), 3)) xor int_7)
xor int_6 xor (c_const & sequence(6)));
k_10 <= int_10;
-- Round 11
int_11 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_10), 3)) xor int_8)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_10), 3)) xor int_8)
xor int_7 xor (c_const & sequence(7)));
k_11 <= int_11;
-- Round 12
int_12 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_11), 3)) xor int_9)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_11), 3)) xor int_9)
xor int_8 xor (c_const & sequence(8)));
k_12 <= int_12;
-- Round 13
int_13 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_12), 3)) xor int_10)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_12), 3)) xor int_10)
xor int_9 xor (c_const & sequence(9)));
k_13 <= int_13;
-- Round 14
int_14 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_13), 3)) xor int_11)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_13), 3)) xor int_11)
xor int_10 xor (c_const & sequence(10)));
k_14 <= int_14;
-- Round 15
int_15 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_14), 3)) xor int_12)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_14), 3)) xor int_12)
xor int_11 xor (c_const & sequence(11)));
k_15 <= int_15;
-- Round 16
int_16 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_15), 3)) xor int_13)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_15), 3)) xor int_13)
xor int_12 xor (c_const & sequence(12)));
k_16 <= int_16;
-- Round 17
int_17 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_16), 3)) xor int_14)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_16), 3)) xor int_14)
xor int_13 xor (c_const & sequence(13)));
k_17 <= int_17;
-- Round 18
int_18 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_17), 3)) xor int_15)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_17), 3)) xor int_15)
xor int_14 xor (c_const & sequence(14)));
k_18 <= int_18;
-- Round 19
int_19 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_18), 3)) xor int_16)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_18), 3)) xor int_16)
xor int_15 xor (c_const & sequence(15)));
k_19 <= int_19;
-- Round 20
int_20 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_19), 3)) xor int_17)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_19), 3)) xor int_17)
xor int_16 xor (c_const & sequence(16)));
k_20 <= int_20;
-- Round 21
int_21 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_20), 3)) xor int_18)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_20), 3)) xor int_18)
xor int_17 xor (c_const & sequence(17)));
k_21 <= int_21;
-- Round 22
int_22 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_21), 3)) xor int_19)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_21), 3)) xor int_19)
xor int_18 xor (c_const & sequence(18)));
k_22 <= int_22;
-- Round 23
int_23 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_22), 3)) xor int_20)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_22), 3)) xor int_20)
xor int_19 xor (c_const & sequence(19)));
k_23 <= int_23;
-- Round 24
int_24 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_23), 3)) xor int_21)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_23), 3)) xor int_21)
xor int_20 xor (c_const & sequence(20)));
k_24 <= int_24;
-- Round 25
int_25 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_24), 3)) xor int_22)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_24), 3)) xor int_22)
xor int_21 xor (c_const & sequence(21)));
k_25 <= int_25;
-- Round 26
int_26 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_25), 3)) xor int_23)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_25), 3)) xor int_23)
xor int_22 xor (c_const & sequence(22)));
k_26 <= int_26;
-- Round 27
int_27 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_26), 3)) xor int_24)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_26), 3)) xor int_24)
xor int_23 xor (c_const & sequence(23)));
k_27 <= int_27;
-- Round 28
int_28 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_27), 3)) xor int_25)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_27), 3)) xor int_25)
xor int_24 xor (c_const & sequence(24)));
k_28 <= int_28;
-- Round 29
int_29 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_28), 3)) xor int_26)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_28), 3)) xor int_26)
xor int_25 xor (c_const & sequence(25)));
k_29 <= int_29;
-- Round 30
int_30 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_29), 3)) xor int_27)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_29), 3)) xor int_27)
xor int_26 xor (c_const & sequence(26)));
k_30 <= int_30;
-- Round 31
int_31 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_30), 3)) xor int_28)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_30), 3)) xor int_28)
xor int_27 xor (c_const & sequence(27)));
k_31 <= int_31;
-- Round 32
int_32 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_31), 3)) xor int_29)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_31), 3)) xor int_29)
xor int_28 xor (c_const & sequence(28)));
k_32 <= int_32;
-- Round 33
int_33 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_32), 3)) xor int_30)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_32), 3)) xor int_30)
xor int_29 xor (c_const & sequence(29)));
k_33 <= int_33;
-- Round 34
int_34 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_33), 3)) xor int_31)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_33), 3)) xor int_31)
xor int_30 xor (c_const & sequence(30)));
k_34 <= int_34;
-- Round 35
int_35 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_34), 3)) xor int_32)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_34), 3)) xor int_32)
xor int_31 xor (c_const & sequence(31)));
k_35 <= int_35;
-- Round 36
int_36 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_35), 3)) xor int_33)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_35), 3)) xor int_33)
xor int_32 xor (c_const & sequence(32)));
k_36 <= int_36;
-- Round 37
int_37 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_36), 3)) xor int_34)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_36), 3)) xor int_34)
xor int_33 xor (c_const & sequence(33)));
k_37 <= int_37;
-- Round 38
int_38 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_37), 3)) xor int_35)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_37), 3)) xor int_35)
xor int_34 xor (c_const & sequence(34)));
k_38 <= int_38;
-- Round 39
int_39 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_38), 3)) xor int_36)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_38), 3)) xor int_36)
xor int_35 xor (c_const & sequence(35)));
k_39 <= int_39;
-- Round 40
int_40 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_39), 3)) xor int_37)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_39), 3)) xor int_37)
xor int_36 xor (c_const & sequence(36)));
k_40 <= int_40;
-- Round 41
int_41 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_40), 3)) xor int_38)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_40), 3)) xor int_38)
xor int_37 xor (c_const & sequence(37)));
k_41 <= int_41;
-- Round 42
int_42 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_41), 3)) xor int_39)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_41), 3)) xor int_39)
xor int_38 xor (c_const & sequence(38)));
k_42 <= int_42;
-- Round 43
int_43 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_42), 3)) xor int_40)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_42), 3)) xor int_40)
xor int_39 xor (c_const & sequence(39)));
k_43 <= int_43;
end Behavioral; |
-- SIMON 64/128
-- key scheduling function
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- r: round index
-- k_0..k_3: key
-- subkey_out: round subkey
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity key_schedule is
port (
k_in_0 : in std_logic_vector(31 downto 0);
k_in_1 : in std_logic_vector(31 downto 0);
k_in_2 : in std_logic_vector(31 downto 0);
k_in_3 : in std_logic_vector(31 downto 0);
k_0 : out std_logic_vector(31 downto 0);
k_1 : out std_logic_vector(31 downto 0);
k_2 : out std_logic_vector(31 downto 0);
k_3 : out std_logic_vector(31 downto 0);
k_4 : out std_logic_vector(31 downto 0);
k_5 : out std_logic_vector(31 downto 0);
k_6 : out std_logic_vector(31 downto 0);
k_7 : out std_logic_vector(31 downto 0);
k_8 : out std_logic_vector(31 downto 0);
k_9 : out std_logic_vector(31 downto 0);
k_10 : out std_logic_vector(31 downto 0);
k_11 : out std_logic_vector(31 downto 0);
k_12 : out std_logic_vector(31 downto 0);
k_13 : out std_logic_vector(31 downto 0);
k_14 : out std_logic_vector(31 downto 0);
k_15 : out std_logic_vector(31 downto 0);
k_16 : out std_logic_vector(31 downto 0);
k_17 : out std_logic_vector(31 downto 0);
k_18 : out std_logic_vector(31 downto 0);
k_19 : out std_logic_vector(31 downto 0);
k_20 : out std_logic_vector(31 downto 0);
k_21 : out std_logic_vector(31 downto 0);
k_22 : out std_logic_vector(31 downto 0);
k_23 : out std_logic_vector(31 downto 0);
k_24 : out std_logic_vector(31 downto 0);
k_25 : out std_logic_vector(31 downto 0);
k_26 : out std_logic_vector(31 downto 0);
k_27 : out std_logic_vector(31 downto 0);
k_28 : out std_logic_vector(31 downto 0);
k_29 : out std_logic_vector(31 downto 0);
k_30 : out std_logic_vector(31 downto 0);
k_31 : out std_logic_vector(31 downto 0);
k_32 : out std_logic_vector(31 downto 0);
k_33 : out std_logic_vector(31 downto 0);
k_34 : out std_logic_vector(31 downto 0);
k_35 : out std_logic_vector(31 downto 0);
k_36 : out std_logic_vector(31 downto 0);
k_37 : out std_logic_vector(31 downto 0);
k_38 : out std_logic_vector(31 downto 0);
k_39 : out std_logic_vector(31 downto 0);
k_40 : out std_logic_vector(31 downto 0);
k_41 : out std_logic_vector(31 downto 0);
k_42 : out std_logic_vector(31 downto 0);
k_43 : out std_logic_vector(31 downto 0));
end key_schedule;
architecture Behavioral of key_schedule is
signal int_0 : std_logic_vector(31 downto 0);
signal int_1 : std_logic_vector(31 downto 0);
signal int_2 : std_logic_vector(31 downto 0);
signal int_3 : std_logic_vector(31 downto 0);
signal int_4 : std_logic_vector(31 downto 0);
signal int_5 : std_logic_vector(31 downto 0);
signal int_6 : std_logic_vector(31 downto 0);
signal int_7 : std_logic_vector(31 downto 0);
signal int_8 : std_logic_vector(31 downto 0);
signal int_9 : std_logic_vector(31 downto 0);
signal int_10 : std_logic_vector(31 downto 0);
signal int_11 : std_logic_vector(31 downto 0);
signal int_12 : std_logic_vector(31 downto 0);
signal int_13 : std_logic_vector(31 downto 0);
signal int_14 : std_logic_vector(31 downto 0);
signal int_15 : std_logic_vector(31 downto 0);
signal int_16 : std_logic_vector(31 downto 0);
signal int_17 : std_logic_vector(31 downto 0);
signal int_18 : std_logic_vector(31 downto 0);
signal int_19 : std_logic_vector(31 downto 0);
signal int_20 : std_logic_vector(31 downto 0);
signal int_21 : std_logic_vector(31 downto 0);
signal int_22 : std_logic_vector(31 downto 0);
signal int_23 : std_logic_vector(31 downto 0);
signal int_24 : std_logic_vector(31 downto 0);
signal int_25 : std_logic_vector(31 downto 0);
signal int_26 : std_logic_vector(31 downto 0);
signal int_27 : std_logic_vector(31 downto 0);
signal int_28 : std_logic_vector(31 downto 0);
signal int_29 : std_logic_vector(31 downto 0);
signal int_30 : std_logic_vector(31 downto 0);
signal int_31 : std_logic_vector(31 downto 0);
signal int_32 : std_logic_vector(31 downto 0);
signal int_33 : std_logic_vector(31 downto 0);
signal int_34 : std_logic_vector(31 downto 0);
signal int_35 : std_logic_vector(31 downto 0);
signal int_36 : std_logic_vector(31 downto 0);
signal int_37 : std_logic_vector(31 downto 0);
signal int_38 : std_logic_vector(31 downto 0);
signal int_39 : std_logic_vector(31 downto 0);
signal int_40 : std_logic_vector(31 downto 0);
signal int_41 : std_logic_vector(31 downto 0);
signal int_42 : std_logic_vector(31 downto 0);
signal int_43 : std_logic_vector(31 downto 0);
signal op_3_s : std_logic_vector(31 downto 0);
signal op_xor_0 : std_logic_vector(31 downto 0);
signal op_1_s : std_logic_vector(31 downto 0);
signal c_const : std_logic_vector(30 downto 0);
signal sequence : std_logic_vector(61 downto 0);
begin
-- C ^ sequence[(r-4) % 62]
sequence <= "11110000101100111001010001001000000111101001100011010111011011"; -- z3
c_const <= "1111111111111111111111111111110";
-- Round 0 to 3
k_0 <= k_in_0;
int_0 <= k_in_0;
k_1 <= k_in_1;
int_1 <= k_in_1;
k_2 <= k_in_2;
int_2 <= k_in_2;
k_3 <= k_in_3;
int_3 <= k_in_3;
-- Round 4
int_4 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_3), 3)) xor int_1)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_3), 3)) xor int_1)
xor int_0 xor (c_const & sequence(0)));
k_4 <= int_4;
-- Round 5
int_5 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_4), 3)) xor int_2)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_4), 3)) xor int_2)
xor int_1 xor (c_const & sequence(1)));
k_5 <= int_5;
-- Round 6
int_6 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_5), 3)) xor int_3)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_5), 3)) xor int_3)
xor int_2 xor (c_const & sequence(2)));
k_6 <= int_6;
-- Round 7
int_7 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_6), 3)) xor int_4)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_6), 3)) xor int_4)
xor int_3 xor (c_const & sequence(3)));
k_7 <= int_7;
-- Round 8
int_8 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_7), 3)) xor int_5)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_7), 3)) xor int_5)
xor int_4 xor (c_const & sequence(4)));
k_8 <= int_8;
-- Round 9
int_9 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_8), 3)) xor int_6)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_8), 3)) xor int_6)
xor int_5 xor (c_const & sequence(5)));
k_9 <= int_9;
-- Round 10
int_10 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_9), 3)) xor int_7)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_9), 3)) xor int_7)
xor int_6 xor (c_const & sequence(6)));
k_10 <= int_10;
-- Round 11
int_11 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_10), 3)) xor int_8)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_10), 3)) xor int_8)
xor int_7 xor (c_const & sequence(7)));
k_11 <= int_11;
-- Round 12
int_12 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_11), 3)) xor int_9)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_11), 3)) xor int_9)
xor int_8 xor (c_const & sequence(8)));
k_12 <= int_12;
-- Round 13
int_13 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_12), 3)) xor int_10)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_12), 3)) xor int_10)
xor int_9 xor (c_const & sequence(9)));
k_13 <= int_13;
-- Round 14
int_14 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_13), 3)) xor int_11)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_13), 3)) xor int_11)
xor int_10 xor (c_const & sequence(10)));
k_14 <= int_14;
-- Round 15
int_15 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_14), 3)) xor int_12)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_14), 3)) xor int_12)
xor int_11 xor (c_const & sequence(11)));
k_15 <= int_15;
-- Round 16
int_16 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_15), 3)) xor int_13)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_15), 3)) xor int_13)
xor int_12 xor (c_const & sequence(12)));
k_16 <= int_16;
-- Round 17
int_17 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_16), 3)) xor int_14)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_16), 3)) xor int_14)
xor int_13 xor (c_const & sequence(13)));
k_17 <= int_17;
-- Round 18
int_18 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_17), 3)) xor int_15)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_17), 3)) xor int_15)
xor int_14 xor (c_const & sequence(14)));
k_18 <= int_18;
-- Round 19
int_19 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_18), 3)) xor int_16)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_18), 3)) xor int_16)
xor int_15 xor (c_const & sequence(15)));
k_19 <= int_19;
-- Round 20
int_20 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_19), 3)) xor int_17)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_19), 3)) xor int_17)
xor int_16 xor (c_const & sequence(16)));
k_20 <= int_20;
-- Round 21
int_21 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_20), 3)) xor int_18)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_20), 3)) xor int_18)
xor int_17 xor (c_const & sequence(17)));
k_21 <= int_21;
-- Round 22
int_22 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_21), 3)) xor int_19)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_21), 3)) xor int_19)
xor int_18 xor (c_const & sequence(18)));
k_22 <= int_22;
-- Round 23
int_23 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_22), 3)) xor int_20)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_22), 3)) xor int_20)
xor int_19 xor (c_const & sequence(19)));
k_23 <= int_23;
-- Round 24
int_24 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_23), 3)) xor int_21)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_23), 3)) xor int_21)
xor int_20 xor (c_const & sequence(20)));
k_24 <= int_24;
-- Round 25
int_25 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_24), 3)) xor int_22)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_24), 3)) xor int_22)
xor int_21 xor (c_const & sequence(21)));
k_25 <= int_25;
-- Round 26
int_26 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_25), 3)) xor int_23)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_25), 3)) xor int_23)
xor int_22 xor (c_const & sequence(22)));
k_26 <= int_26;
-- Round 27
int_27 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_26), 3)) xor int_24)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_26), 3)) xor int_24)
xor int_23 xor (c_const & sequence(23)));
k_27 <= int_27;
-- Round 28
int_28 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_27), 3)) xor int_25)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_27), 3)) xor int_25)
xor int_24 xor (c_const & sequence(24)));
k_28 <= int_28;
-- Round 29
int_29 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_28), 3)) xor int_26)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_28), 3)) xor int_26)
xor int_25 xor (c_const & sequence(25)));
k_29 <= int_29;
-- Round 30
int_30 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_29), 3)) xor int_27)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_29), 3)) xor int_27)
xor int_26 xor (c_const & sequence(26)));
k_30 <= int_30;
-- Round 31
int_31 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_30), 3)) xor int_28)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_30), 3)) xor int_28)
xor int_27 xor (c_const & sequence(27)));
k_31 <= int_31;
-- Round 32
int_32 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_31), 3)) xor int_29)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_31), 3)) xor int_29)
xor int_28 xor (c_const & sequence(28)));
k_32 <= int_32;
-- Round 33
int_33 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_32), 3)) xor int_30)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_32), 3)) xor int_30)
xor int_29 xor (c_const & sequence(29)));
k_33 <= int_33;
-- Round 34
int_34 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_33), 3)) xor int_31)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_33), 3)) xor int_31)
xor int_30 xor (c_const & sequence(30)));
k_34 <= int_34;
-- Round 35
int_35 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_34), 3)) xor int_32)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_34), 3)) xor int_32)
xor int_31 xor (c_const & sequence(31)));
k_35 <= int_35;
-- Round 36
int_36 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_35), 3)) xor int_33)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_35), 3)) xor int_33)
xor int_32 xor (c_const & sequence(32)));
k_36 <= int_36;
-- Round 37
int_37 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_36), 3)) xor int_34)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_36), 3)) xor int_34)
xor int_33 xor (c_const & sequence(33)));
k_37 <= int_37;
-- Round 38
int_38 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_37), 3)) xor int_35)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_37), 3)) xor int_35)
xor int_34 xor (c_const & sequence(34)));
k_38 <= int_38;
-- Round 39
int_39 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_38), 3)) xor int_36)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_38), 3)) xor int_36)
xor int_35 xor (c_const & sequence(35)));
k_39 <= int_39;
-- Round 40
int_40 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_39), 3)) xor int_37)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_39), 3)) xor int_37)
xor int_36 xor (c_const & sequence(36)));
k_40 <= int_40;
-- Round 41
int_41 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_40), 3)) xor int_38)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_40), 3)) xor int_38)
xor int_37 xor (c_const & sequence(37)));
k_41 <= int_41;
-- Round 42
int_42 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_41), 3)) xor int_39)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_41), 3)) xor int_39)
xor int_38 xor (c_const & sequence(38)));
k_42 <= int_42;
-- Round 43
int_43 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_42), 3)) xor int_40)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_42), 3)) xor int_40)
xor int_39 xor (c_const & sequence(39)));
k_43 <= int_43;
end Behavioral; |
----------------------------------------------------------------------------------------------------
-- ENTITY - Serial In Parallel Out Register
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 29.06.2017
----------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.tld_ecdsa_package.all;
ENTITY e_nm_sipo_register IS
PORT (
clk_i : IN std_logic;
rst_i : IN std_logic;
enable_i : IN std_logic;
data_i : IN std_logic_vector(U-1 DOWNTO 0);
data_o : OUT std_logic_vector(M-1 DOWNTO 0)
);
END e_nm_sipo_register;
ARCHITECTURE rtl OF e_nm_sipo_register IS
SIGNAL temp: std_logic_vector(M-1 DOWNTO 0);
BEGIN
PROCESS(clk_i,rst_i,enable_i)
BEGIN
IF rst_i = '1' THEN
temp <= (OTHERS => '0');
ELSIF(clk_i'event and clk_i='1' and enable_i='1') THEN
temp(M-1 DOWNTO U) <= temp(M-U-1 DOWNTO 0);
temp(U-1 DOWNTO 0) <= data_i(U-1 DOWNTO 0);
END IF;
END PROCESS;
data_o <= temp;
END rtl;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: memmory_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY memmory_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END memmory_exdes;
ARCHITECTURE xilinx OF memmory_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT memmory IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : memmory
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
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