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-- ****
-- T80(c) core. Attempt to finish all undocumented features and provide
-- accurate timings.
-- Version 350.
-- Copyright (c) 2018 Sorgelig
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
-- correct implementation is still unclear.
--
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- Z80 compatible microprocessor core
--
-- Version : 0242
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
-- 0211 : Fixed IM 1
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
-- 0235 : Added IM 2 fix by Mike Johnson
-- 0238 : Added NoRead signal
-- 0238b: Fixed instruction timing for POP and DJNZ
-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
-- 0242 : Fixed I/O instruction timing, cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_MCode is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetWZ : out std_logic_vector(1 downto 0);
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end T80_MCode;
architecture rtl of T80_MCode is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
function is_cc_true(
F : std_logic_vector(7 downto 0);
cc : bit_vector(2 downto 0)
) return boolean is
begin
if Mode = 3 then
case cc is
when "000" => return F(Flag_S) = '0'; -- NZ
when "001" => return F(Flag_S) = '1'; -- Z
when "010" => return F(Flag_H) = '0'; -- NC
when "011" => return F(Flag_H) = '1'; -- C
when "100" => return false;
when "101" => return false;
when "110" => return false;
when "111" => return false;
end case;
else
case cc is
when "000" => return F(Flag_Z) = '0'; -- NZ
when "001" => return F(Flag_Z) = '1'; -- Z
when "010" => return F(Flag_C) = '0'; -- NC
when "011" => return F(Flag_C) = '1'; -- C
when "100" => return F(Flag_P) = '0'; -- PO
when "101" => return F(Flag_P) = '1'; -- PE
when "110" => return F(Flag_S) = '0'; -- P
when "111" => return F(Flag_S) = '1'; -- M
end case;
end if;
end;
begin
process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
variable DDD : std_logic_vector(2 downto 0);
variable SSS : std_logic_vector(2 downto 0);
variable DPair : std_logic_vector(1 downto 0);
variable IRB : bit_vector(7 downto 0);
begin
DDD := IR(5 downto 3);
SSS := IR(2 downto 0);
DPair := IR(5 downto 4);
IRB := to_bitvector(IR);
MCycles <= "001";
if MCycle = "001" then
TStates <= "100";
else
TStates <= "011";
end if;
Prefix <= "00";
Inc_PC <= '0';
Inc_WZ <= '0';
IncDec_16 <= "0000";
Read_To_Acc <= '0';
Read_To_Reg <= '0';
Set_BusB_To <= "0000";
Set_BusA_To <= "0000";
ALU_Op <= "0" & IR(5 downto 3);
Save_ALU <= '0';
PreserveC <= '0';
Arith16 <= '0';
IORQ <= '0';
Set_Addr_To <= aNone;
Jump <= '0';
JumpE <= '0';
JumpXY <= '0';
Call <= '0';
RstP <= '0';
LDZ <= '0';
LDW <= '0';
LDSPHL <= '0';
Special_LD <= "000";
ExchangeDH <= '0';
ExchangeRp <= '0';
ExchangeAF <= '0';
ExchangeRS <= '0';
I_DJNZ <= '0';
I_CPL <= '0';
I_CCF <= '0';
I_SCF <= '0';
I_RETN <= '0';
I_BT <= '0';
I_BC <= '0';
I_BTR <= '0';
I_RLD <= '0';
I_RRD <= '0';
I_INRC <= '0';
SetDI <= '0';
SetEI <= '0';
IMode <= "11";
Halt <= '0';
NoRead <= '0';
Write <= '0';
XYbit_undoc <= '0';
SetWZ <= "00";
case ISet is
when "00" =>
------------------------------------------------------------------------------
--
-- Unprefixed instructions
--
------------------------------------------------------------------------------
case IRB is
-- 8 BIT LOAD GROUP
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-- LD r,r'
Set_BusB_To(2 downto 0) <= SSS;
ExchangeRp <= '1';
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-- LD r,n
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when others => null;
end case;
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-- LD r,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when others => null;
end case;
when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-- LD (HL),r
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
when 2 =>
Write <= '1';
when others => null;
end case;
when "00110110" =>
-- LD (HL),n
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aXY;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
when 3 =>
Write <= '1';
when others => null;
end case;
when "00001010" =>
-- LD A,(BC)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "00011010" =>
-- LD A,(DE)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aDE;
when 2 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "00111010" =>
if Mode = 3 then
-- LDD A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Acc <= '1';
IncDec_16 <= "1110";
when others => null;
end case;
else
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
end if;
when "00000010" =>
-- LD (BC),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "0111";
SetWZ <= "10";
when 2 =>
Write <= '1';
when others => null;
end case;
when "00010010" =>
-- LD (DE),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aDE;
Set_BusB_To <= "0111";
SetWZ <= "10";
when 2 =>
Write <= '1';
when others => null;
end case;
when "00110010" =>
if Mode = 3 then
-- LDD (HL),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IncDec_16 <= "1110";
when others => null;
end case;
else
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
SetWZ <= "10";
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
end if;
-- 16 BIT LOAD GROUP
when "00000001"|"00010001"|"00100001"|"00110001" =>
-- LD dd,nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1000";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '1';
end if;
when 3 =>
Inc_PC <= '1';
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1001";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
when "00101010" =>
if Mode = 3 then
-- LDI A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Acc <= '1';
IncDec_16 <= "0110";
when others => null;
end case;
else
-- LD HL,(nn)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
when others => null;
end case;
end if;
when "00100010" =>
if Mode = 3 then
-- LDI (HL),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IncDec_16 <= "0110";
when others => null;
end case;
else
-- LD (nn),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "0101"; -- L
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "0100"; -- H
when 5 =>
Write <= '1';
when others => null;
end case;
end if;
when "11111001" =>
-- LD SP,HL
TStates <= "110";
LDSPHL <= '1';
when "11000101"|"11010101"|"11100101"|"11110101" =>
-- PUSH qq
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
if DPAIR = "11" then
Set_BusB_To <= "0111";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '0';
Set_BusB_To(3) <= '0';
end if;
when 2 =>
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
if DPAIR = "11" then
Set_BusB_To <= "1011";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '1';
Set_BusB_To(3) <= '0';
end if;
Write <= '1';
when 3 =>
Write <= '1';
when others => null;
end case;
when "11000001"|"11010001"|"11100001"|"11110001" =>
-- POP qq
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1011";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '1';
end if;
when 3 =>
IncDec_16 <= "0111";
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "0111";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
when "11101011" =>
if Mode /= 3 then
-- EX DE,HL
ExchangeDH <= '1';
end if;
when "00001000" =>
if Mode = 3 then
-- LD (nn),SP
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "1000";
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "1001";
when 5 =>
Write <= '1';
when others => null;
end case;
elsif Mode < 2 then
-- EX AF,AF'
ExchangeAF <= '1';
end if;
when "11011001" =>
if Mode = 3 then
-- RETI
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
I_RETN <= '1';
SetEI <= '1';
when others => null;
end case;
elsif Mode < 2 then
-- EXX
ExchangeRS <= '1';
end if;
when "11100011" =>
if Mode /= 3 then
-- EX (SP),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aSP;
when 2 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0101"; -- L, target of Read_To_Reg
Set_BusB_To <= "0101"; -- L, input of ALU
Set_Addr_To <= aSP;
LDZ <= '1'; -- also load Z
when 3 =>
IncDec_16 <= "0111"; -- Increment SP
Set_Addr_To <= aSP;
TStates <= "100";
Write <= '1';
when 4 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0100"; -- H, target of Read_To_Reg
Set_BusB_To <= "0100"; -- H, input of ALU
Set_Addr_To <= aSP;
LDW <= '1'; -- also load Z
when 5 =>
IncDec_16 <= "1111"; -- Decrement SP
TStates <= "101";
Write <= '1';
when others => null;
end case;
end if;
-- The T80 implementation does:
--
-- (4) M1 fetch
-- (3) M2 Read (SP) -> L, Z
-- L -> ALU
-- (4) M3 Write ALU result -> (SP)
-- SP++
-- (3) M4 Read (SP) -> H, W
-- H -> ALU
-- (5) M5 Write ALU result -> (SP)
-- SP--
--
-- The Z80 does
-- (4) M1 fetch
-- (3) M2 Read (SP) -> Z
-- SP++
-- (4) M3 Read (SP) -> W
-- (3) M4 Write H -> (SP)
-- SP--
-- (5) M5 Write L -> (SP)
--
-- and somehow WZ -> HL at the end!
--
-- Attempt at a new version.
--
-- case to_integer(unsigned(MCycle)) is
-- when 1 =>
-- Set_Addr_To <= aSP;
-- when 2 =>
-- IncDec_16 <= "0111";
-- Read_To_Reg <= '1';
-- Set_BusA_To <= "0101";
-- Set_BusB_To <= "0101";
-- Set_Addr_To <= aSP;
-- LDZ <= '1';
-- when 3 =>
-- Read_To_Reg <= '1';
-- Set_BusA_To <= "0100";
-- Set_BusB_To <= "0100";
-- Set_Addr_To <= aSP;
-- TStates <= "100";
-- LDW <= '1';
-- when 4 =>
-- IncDec_16 <= "1111";
-- Set_Addr_To <= aSP;
-- Write <= '1';
-- when 5 =>
-- TStates <= "101";
-- Write <= '1';
-- when others => null;
-- end case;
-- end if;
-- 8 BIT ARITHMETIC AND LOGICAL GROUP
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-- ADD A,r
-- ADC A,r
-- SUB A,r
-- SBC A,r
-- AND A,r
-- OR A,r
-- XOR A,r
-- CP A,r
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
Read_To_Reg <= '1';
Save_ALU <= '1';
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-- ADD A,(HL)
-- ADC A,(HL)
-- SUB A,(HL)
-- SBC A,(HL)
-- AND A,(HL)
-- OR A,(HL)
-- XOR A,(HL)
-- CP A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
when others => null;
end case;
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-- ADD A,n
-- ADC A,n
-- SUB A,n
-- SBC A,n
-- AND A,n
-- OR A,n
-- XOR A,n
-- CP A,n
MCycles <= "010";
if MCycle = "010" then
Inc_PC <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
end if;
when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-- INC r
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0000";
when "00110100" =>
-- INC (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
TStates <= "100";
Set_Addr_To <= aXY;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0000";
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
when 3 =>
Write <= '1';
when others => null;
end case;
when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-- DEC r
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0010";
when "00110101" =>
-- DEC (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
TStates <= "100";
Set_Addr_To <= aXY;
ALU_Op <= "0010";
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
when 3 =>
Write <= '1';
when others => null;
end case;
-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
when "00100111" =>
-- DAA
Set_BusA_To(2 downto 0) <= "111";
Read_To_Reg <= '1';
ALU_Op <= "1100";
Save_ALU <= '1';
when "00101111" =>
-- CPL
I_CPL <= '1';
when "00111111" =>
-- CCF
I_CCF <= '1';
when "00110111" =>
-- SCF
I_SCF <= '1';
when "00000000" =>
if NMICycle = '1' then
-- NMI
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
Write <= '1';
when others => null;
end case;
elsif IntCycle = '1' then
-- INT (IM 2)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
LDZ <= '1';
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
--TStates <= "100";
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
--TStates <= "100";
Write <= '1';
when 4 =>
Inc_PC <= '1';
LDZ <= '1';
when 5 =>
Jump <= '1';
when others => null;
end case;
else
-- NOP
end if;
when "01110110" =>
-- HALT
Halt <= '1';
when "11110011" =>
-- DI
SetDI <= '1';
when "11111011" =>
-- EI
SetEI <= '1';
-- 16 BIT ARITHMETIC GROUP
when "00001001"|"00011001"|"00101001"|"00111001" =>
-- ADD HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
Arith16 <= '1';
SetWZ <= "11";
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
when others =>
Set_BusB_To <= "1001";
end case;
Arith16 <= '1';
when others =>
end case;
when "00000011"|"00010011"|"00100011"|"00110011" =>
-- INC ss
TStates <= "110";
IncDec_16(3 downto 2) <= "01";
IncDec_16(1 downto 0) <= DPair;
when "00001011"|"00011011"|"00101011"|"00111011" =>
-- DEC ss
TStates <= "110";
IncDec_16(3 downto 2) <= "11";
IncDec_16(1 downto 0) <= DPair;
-- ROTATE AND SHIFT GROUP
when "00000111"
-- RLCA
|"00010111"
-- RLA
|"00001111"
-- RRCA
|"00011111" =>
-- RRA
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
-- JUMP GROUP
when "11000011" =>
-- JP nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
Jump <= '1';
LDW <= '1';
when others => null;
end case;
when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
if IR(5) = '1' and Mode = 3 then
case IRB(4 downto 3) is
when "00" =>
-- LD ($FF00+C),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IORQ <= '1';
when others =>
end case;
when "01" =>
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
when "10" =>
-- LD A,($FF00+C)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
Read_To_Acc <= '1';
IORQ <= '1';
when others =>
end case;
when "11" =>
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
end case;
else
-- JP cc,nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
LDW <= '1';
Inc_PC <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Jump <= '1';
end if;
when others => null;
end case;
end if;
when "00011000" =>
if Mode /= 2 then
-- JR e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00111000" =>
if Mode /= 2 then
-- JR C,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_C) = '0' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00110000" =>
if Mode /= 2 then
-- JR NC,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_C) = '1' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00101000" =>
if Mode /= 2 then
-- JR Z,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_Z) = '0' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00100000" =>
if Mode /= 2 then
-- JR NZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_Z) = '1' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "11101001" =>
-- JP (HL)
JumpXY <= '1';
when "00010000" =>
if Mode = 3 then
I_DJNZ <= '1';
elsif Mode < 2 then
-- DJNZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
I_DJNZ <= '1';
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= "000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
I_DJNZ <= '1';
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
-- CALL AND RETURN GROUP
when "11001101" =>
-- CALL nn
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
IncDec_16 <= "1111";
Inc_PC <= '1';
TStates <= "100";
Set_Addr_To <= aSP;
LDW <= '1';
Set_BusB_To <= "1101";
when 4 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 5 =>
Write <= '1';
Call <= '1';
when others => null;
end case;
when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
if IR(5) = '0' or Mode /= 3 then
-- CALL cc,nn
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
LDW <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
TStates <= "100";
Set_BusB_To <= "1101";
else
MCycles <= "011";
end if;
when 4 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 5 =>
Write <= '1';
Call <= '1';
when others => null;
end case;
end if;
when "11001001" =>
-- RET
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
--TStates <= "101";
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
if IR(5) = '1' and Mode = 3 then
case IRB(4 downto 3) is
when "00" =>
-- LD ($FF00+nn),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
when others => null;
end case;
when "01" =>
-- ADD SP,n
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
ALU_Op <= "0000";
Inc_PC <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To <= "1000";
Set_BusB_To <= "0110";
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To <= "1001";
Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
when others =>
end case;
when "10" =>
-- LD A,($FF00+nn)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "11" =>
-- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
when others => null;
end case;
end case;
else
-- RET cc
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Set_Addr_TO <= aSP;
else
MCycles <= "001";
end if;
TStates <= "101";
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
end if;
when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-- RST p
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
Write <= '1';
RstP <= '1';
when others => null;
end case;
-- INPUT AND OUTPUT GROUP
when "11011011" =>
if Mode /= 3 then
-- IN A,(n)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
IORQ <= '1';
when others => null;
end case;
end if;
when "11010011" =>
if Mode /= 3 then
-- OUT (n),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
IORQ <= '1';
when others => null;
end case;
end if;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- MULTIBYTE INSTRUCTIONS
------------------------------------------------------------------------------
------------------------------------------------------------------------------
when "11001011" =>
if Mode /= 2 then
Prefix <= "01";
end if;
when "11101101" =>
if Mode < 2 then
Prefix <= "10";
end if;
when "11011101"|"11111101" =>
if Mode < 2 then
Prefix <= "11";
end if;
end case;
when "01" =>
------------------------------------------------------------------------------
--
-- CB prefixed instructions
--
------------------------------------------------------------------------------
Set_BusA_To(2 downto 0) <= IR(2 downto 0);
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
case IRB is
when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-- RLC r
-- RL r
-- RRC r
-- RR r
-- SLA r
-- SRA r
-- SRL r
-- SLL r (Undocumented) / SWAP r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- R/S (IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-- RLC (HL)
-- RL (HL)
-- RRC (HL)
-- RR (HL)
-- SRA (HL)
-- SRL (HL)
-- SLA (HL)
-- SLL (HL) (Undocumented) / SWAP (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others =>
end case;
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-- BIT b,r
if XY_State="00" then
if MCycle = "001" then
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
ALU_Op <= "1001";
end if;
else
-- BIT b,(IX+d), undocumented
MCycles <= "010";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1001";
TStates <= "100";
when others => null;
end case;
end if;
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-- BIT b,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1001";
TStates <= "100";
when others => null;
end case;
when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-- SET b,r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- SET b,(IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-- SET b,(HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-- RES b,r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- RES b,(IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-- RES b,(HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end case;
when others =>
------------------------------------------------------------------------------
--
-- ED prefixed instructions
--
------------------------------------------------------------------------------
case IRB is
when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
| "10100100"|"10100101"|"10100110"|"10100111"
| "10101100"|"10101101"|"10101110"|"10101111"
| "10110100"|"10110101"|"10110110"|"10110111"
| "10111100"|"10111101"|"10111110"|"10111111"
|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
null; -- NOP, undocumented
when "01111110"|"01111111" =>
-- NOP, undocumented
null;
-- 8 BIT LOAD GROUP
when "01010111" =>
-- LD A,I
Special_LD <= "100";
TStates <= "101";
when "01011111" =>
-- LD A,R
Special_LD <= "101";
TStates <= "101";
when "01000111" =>
-- LD I,A
Special_LD <= "110";
TStates <= "101";
when "01001111" =>
-- LD R,A
Special_LD <= "111";
TStates <= "101";
-- 16 BIT LOAD GROUP
when "01001011"|"01011011"|"01101011"|"01111011" =>
-- LD dd,(nn)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Read_To_Reg <= '1';
if IR(5 downto 4) = "11" then
Set_BusA_To <= "1000";
else
Set_BusA_To(2 downto 1) <= IR(5 downto 4);
Set_BusA_To(0) <= '1';
end if;
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Read_To_Reg <= '1';
if IR(5 downto 4) = "11" then
Set_BusA_To <= "1001";
else
Set_BusA_To(2 downto 1) <= IR(5 downto 4);
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
when "01000011"|"01010011"|"01100011"|"01110011" =>
-- LD (nn),dd
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
if IR(5 downto 4) = "11" then
Set_BusB_To <= "1000";
else
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
Set_BusB_To(3) <= '0';
end if;
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
if IR(5 downto 4) = "11" then
Set_BusB_To <= "1001";
else
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '0';
Set_BusB_To(3) <= '0';
end if;
when 5 =>
Write <= '1';
when others => null;
end case;
when "10100000" | "10101000" | "10110000" | "10111000" =>
-- LDI, LDD, LDIR, LDDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
IncDec_16 <= "1100"; -- BC
when 2 =>
Set_BusB_To <= "0110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "0000";
Set_Addr_To <= aDE;
if IR(3) = '0' then
IncDec_16 <= "0110"; -- IX
else
IncDec_16 <= "1110";
end if;
when 3 =>
I_BT <= '1';
TStates <= "101";
Write <= '1';
if IR(3) = '0' then
IncDec_16 <= "0101"; -- DE
else
IncDec_16 <= "1101";
end if;
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "10100001" | "10101001" | "10110001" | "10111001" =>
-- CPI, CPD, CPIR, CPDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
IncDec_16 <= "1100"; -- BC
when 2 =>
Set_BusB_To <= "0110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "0111";
Save_ALU <= '1';
PreserveC <= '1';
if IR(3) = '0' then
IncDec_16 <= "0110";
else
IncDec_16 <= "1110";
end if;
when 3 =>
NoRead <= '1';
I_BC <= '1';
TStates <= "101";
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-- NEG
Alu_OP <= "0010";
Set_BusB_To <= "0111";
Set_BusA_To <= "1010";
Read_To_Acc <= '1';
Save_ALU <= '1';
when "01000110"|"01001110"|"01100110"|"01101110" =>
-- IM 0
IMode <= "00";
when "01010110"|"01110110" =>
-- IM 1
IMode <= "01";
when "01011110"|"01110111" =>
-- IM 2
IMode <= "10";
-- 16 bit arithmetic
when "01001010"|"01011010"|"01101010"|"01111010" =>
-- ADC HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0001";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
SetWZ <= "11";
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '0';
when others =>
Set_BusB_To <= "1001";
end case;
when others =>
end case;
when "01000010"|"01010010"|"01100010"|"01110010" =>
-- SBC HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
SetWZ <= "11";
when 3 =>
NoRead <= '1';
ALU_Op <= "0011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
when others =>
Set_BusB_To <= "1001";
end case;
when others =>
end case;
when "01101111" =>
-- RLD -- Read in M2, not M3! fixed by Sorgelig
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Reg <= '1';
Set_BusB_To(2 downto 0) <= "110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1101";
Save_ALU <= '1';
when 3 =>
TStates <= "100";
I_RLD <= '1';
NoRead <= '1';
Set_Addr_To <= aXY;
when 4 =>
Write <= '1';
when others =>
end case;
when "01100111" =>
-- RRD -- Read in M2, not M3! fixed by Sorgelig
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Reg <= '1';
Set_BusB_To(2 downto 0) <= "110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1110";
Save_ALU <= '1';
when 3 =>
TStates <= "100";
I_RRD <= '1';
NoRead <= '1';
Set_Addr_To <= aXY;
when 4 =>
Write <= '1';
when others =>
end case;
when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-- RETI/RETN
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
LDW <= '1';
I_RETN <= '1';
when others => null;
end case;
when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-- IN r,(C)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
SetWZ <= "01";
when 2 =>
IORQ <= '1';
if IR(5 downto 3) /= "110" then
Read_To_Reg <= '1';
Set_BusA_To(2 downto 0) <= IR(5 downto 3);
end if;
I_INRC <= '1';
when others =>
end case;
when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-- OUT (C),r
-- OUT (C),0
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
SetWZ <= "01";
Set_BusB_To(2 downto 0) <= IR(5 downto 3);
if IR(5 downto 3) = "110" then
Set_BusB_To(3) <= '1';
end if;
when 2 =>
Write <= '1';
IORQ <= '1';
when others =>
end case;
when "10100010" | "10101010" | "10110010" | "10111010" =>
-- INI, IND, INIR, INDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
Set_Addr_To <= aBC;
Set_BusB_To <= "1010";
Set_BusA_To <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
SetWZ <= "11";
IncDec_16(3) <= IR(3);
when 2 =>
IORQ <= '1';
Set_BusB_To <= "0110";
Set_Addr_To <= aXY;
when 3 =>
if IR(3) = '0' then
IncDec_16 <= "0110";
else
IncDec_16 <= "1110";
end if;
Write <= '1';
I_BTR <= '1';
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "10100011" | "10101011" | "10110011" | "10111011" =>
-- OUTI, OUTD, OTIR, OTDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
Set_Addr_To <= aXY;
Set_BusB_To <= "1010";
Set_BusA_To <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
Set_BusB_To <= "0110";
Set_Addr_To <= aBC;
SetWZ <= "11";
IncDec_16(3) <= IR(3);
when 3 =>
if IR(3) = '0' then
IncDec_16 <= "0110";
else
IncDec_16 <= "1110";
end if;
IORQ <= '1';
Write <= '1';
I_BTR <= '1';
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
end case;
end case;
if Mode = 1 then
if MCycle = "001" then
-- TStates <= "100";
else
TStates <= "011";
end if;
end if;
if Mode = 3 then
if MCycle = "001" then
-- TStates <= "100";
else
TStates <= "100";
end if;
end if;
if Mode < 2 then
if MCycle = "110" then
Inc_PC <= '1';
if Mode = 1 then
Set_Addr_To <= aXY;
TStates <= "100";
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
end if;
if IRB = "00110110" or IRB = "11001011" then
Set_Addr_To <= aNone;
end if;
end if;
if MCycle = "111" then
if Mode = 0 then
TStates <= "101";
end if;
if ISet /= "01" then
Set_Addr_To <= aXY;
end if;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
if IRB = "00110110" or ISet = "01" then
-- LD (HL),n
Inc_PC <= '1';
else
NoRead <= '1';
end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity test5 is
port (led: out std_logic_vector (7 downto 0));
end test5;
architecture synth of test5 is
begin
led(7) <= '1';
-- led(6) <= '1';
-- led(5) <= '0';
-- led(3 downto 0) <= x"9";
end synth;
|
--
-- frame.vhd: VHDL module for Zapata Telephony PCI Radio Card, Rev. A
-- Authors: Jim Dixon, Stephen A. Rodgers
--
-- Copyright (c) 2004, Jim Dixon
-- Copyright (c) 2004, Stephen A. Rodgers
--
-- Jim Dixon <[email protected]>
-- Steve Rodgers <[email protected]>
--
-- This program is free software, and the design, schematics, layout,
-- and artwork for the hardware on which it runs is free, and all are
-- distributed under the terms of the GNU General Public License.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity frame is
port
(
arn : in std_logic;
clk : in std_logic;
clk2048 : out std_logic;
tjfsc : out std_logic;
ledpwm : out std_logic;
fsync : out std_logic_vector(3 downto 0)
);
end frame;
architecture rtl of frame is
--
-- Signals
--
signal framephase : std_logic_vector(8 downto 0);
begin
--
-- Processes
--
-- 9 bit frame phase counter
framectr : process(arn, clk)
begin
if(arn = '0') then
framephase <= "000000000";
elsif(clk'event) and (clk = '0') then
framephase <= framephase + 1;
end if;
end process framectr;
-- frame phase decoder
framedec : process(framephase)
begin
tjfsc <= '0';
fsync <= "0000";
if (framephase = "00000000") then -- is this really ok?
tjfsc <= '1';
elsif (framephase = "111111110") then
fsync <= "0001";
elsif (framephase = "000001110")then
fsync <= "0010";
elsif (framephase = "000011110") then
fsync <= "0100";
elsif (framephase = "000101110") then
fsync <= "1000";
end if;
end process framedec;
--
-- concurrent statements
--
clk2048 <= not framephase(0);
ledpwm <= framephase(7);
end rtl;
|
----------------------------------------------------------------------------------------------
--
-- Input file : fetch.vhd
-- Design name : fetch
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Instruction Fetch Stage inserts instruction into the pipeline. It
-- uses a single port Random Access Memory component which holds
-- the instructions. The next instruction is computed in the decode
-- stage.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity fetch is port
(
fetch_o : out fetch_out_type;
imem_o : out imem_out_type;
fetch_i : in fetch_in_type;
imem_i : in imem_in_type;
rst_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
);
end fetch;
architecture arch of fetch is
signal r, rin : fetch_out_type;
signal rst_d : std_logic;
signal ena_o : std_logic;
signal possibly_valid : std_logic;
begin
fetch_o.program_counter <= r.program_counter;
fetch_o.instruction <= imem_i.dat_i;
fetch_o.inst_valid <= possibly_valid and imem_i.ena_i;
ena_o <= ena_i and imem_i.ena_i and not rst_i;
imem_o.adr_o <= rin.program_counter;
imem_o.ena_o <= ena_o;
fetch_comb: process(fetch_i, imem_i, r, rst_d)
variable v : fetch_out_type;
begin
v := r;
if rst_d = '1' then
v.program_counter := (OTHERS => '0');
elsif fetch_i.hazard = '1' or imem_i.ena_i = '0' then
v.program_counter := r.program_counter;
elsif fetch_i.branch = '1' then
v.program_counter := fetch_i.branch_target;
else
v.program_counter := increment(r.program_counter(CFG_IMEM_SIZE - 1 downto 2)) & "00";
end if;
rin <= v;
end process;
fetch_seq: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
r.program_counter <= (others => '0');
rst_d <= '1';
possibly_valid <= '0';
elsif ena_i = '1' then
r <= rin;
rst_d <= '0';
if imem_i.ena_i = '1' then
possibly_valid <= ena_o;
end if;
end if;
end if;
end process;
end arch; |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(34-1 DOWNTO 0);
DOUT : OUT std_logic_vector(34-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes;
architecture xilinx of system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component system_axi_vdma_0_wrapper_fifo_generator_v9_1 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(34-1 DOWNTO 0);
DOUT : OUT std_logic_vector(34-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_1
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(34-1 DOWNTO 0);
DOUT : OUT std_logic_vector(34-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes;
architecture xilinx of system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component system_axi_vdma_0_wrapper_fifo_generator_v9_1 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(34-1 DOWNTO 0);
DOUT : OUT std_logic_vector(34-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_1
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(34-1 DOWNTO 0);
DOUT : OUT std_logic_vector(34-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes;
architecture xilinx of system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component system_axi_vdma_0_wrapper_fifo_generator_v9_1 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(34-1 DOWNTO 0);
DOUT : OUT std_logic_vector(34-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_1
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity dff03 is
port (q : out std_logic;
d : std_logic;
en1 : std_logic;
en2 : std_logic;
clk : std_logic);
end dff03;
architecture behav of dff03 is
begin
process (clk) is
begin
if (rising_edge (clk) and en1 = '1') and en2 = '1' then
q <= d;
end if;
end process;
end behav;
|
architecture test of test2 is
signal foo : bar;
begin end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Multiplexer_2x1 is
Port ( Selector : in STD_LOGIC_VECTOR (1 downto 0);
input_A, input_B, input_C, input_D: in STD_LOGIC;
output : out STD_LOGIC);
end Multiplexer_2x1;
architecture skeleton of Multiplexer_2x1 is
begin
with Selector select
output <= input_A when "00",
input_B when "01",
input_C when "10",
input_D when others;
end skeleton; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: uart
-- File: uart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UART types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package uart is
type uart_in_type is record
rxd : std_ulogic;
ctsn : std_ulogic;
extclk : std_ulogic;
end record;
type uart_out_type is record
rtsn : std_ulogic;
txd : std_ulogic;
scaler : std_logic_vector(31 downto 0);
txen : std_ulogic;
flow : std_ulogic;
rxen : std_ulogic;
end record;
component apbuart
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
parity : integer := 1;
flow : integer := 1;
fifosize : integer range 1 to 32 := 1;
abits : integer := 8;
sbits : integer range 12 to 32 := 12);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in uart_in_type;
uarto : out uart_out_type);
end component;
component ahbuart
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
uarti : in uart_in_type;
uarto : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type);
end component;
end;
|
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity cdc_out is
port
(
-- in signals
fdata : in std_logic_vector(7 downto 0);
flag_empty : in std_logic;
faddr : in std_logic_vector(1 downto 0);
cdcout : in std_logic_vector(1 downto 0);
-- out signals
slrd : out std_logic;
cmd : out std_logic_vector(7 downto 0);
cmd_en : out std_logic;
cdc_out_free: out std_logic;
-- ifclk,rst
rst : in std_logic;
ifclk : in std_logic
);
end entity cdc_out;
architecture rtl of cdc_out is
type states is (s_wait_for_cdc,s_reset,s_read_data,s_free_cdc,s_skip);
signal ps : states;
begin -- architecture
process(ifclk,rst)
begin
if rst = '1' then
slrd <= '1';
cmd <= (others => '0');
cmd_en <= '0';
cdc_out_free <= '1';
ps <= s_reset;
elsif falling_edge(ifclk) then
slrd <= '1';
cmd <= (others => '0');
cmd_en <= '0';
case ps is
when s_reset =>
slrd <= '1';
cmd <= (others => '0');
cmd_en <= '0';
cdc_out_free <= '1';
ps <= s_wait_for_cdc;
when s_wait_for_cdc =>
if faddr = cdcout then
ps <= s_read_data;
cdc_out_free <= '0';
end if;
when s_read_data =>
ps <= s_free_cdc;
if flag_empty = '1' then -- some data in fifo
slrd <= '0';
cmd_en <= '1';
cmd <= fdata;
end if;
when s_free_cdc =>
ps <= s_skip;
cdc_out_free <= '1';
when s_skip =>
ps <= s_wait_for_cdc;
when others =>
ps <= s_reset;
end case;
end if;
end process;
end architecture;
|
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity cdc_out is
port
(
-- in signals
fdata : in std_logic_vector(7 downto 0);
flag_empty : in std_logic;
faddr : in std_logic_vector(1 downto 0);
cdcout : in std_logic_vector(1 downto 0);
-- out signals
slrd : out std_logic;
cmd : out std_logic_vector(7 downto 0);
cmd_en : out std_logic;
cdc_out_free: out std_logic;
-- ifclk,rst
rst : in std_logic;
ifclk : in std_logic
);
end entity cdc_out;
architecture rtl of cdc_out is
type states is (s_wait_for_cdc,s_reset,s_read_data,s_free_cdc,s_skip);
signal ps : states;
begin -- architecture
process(ifclk,rst)
begin
if rst = '1' then
slrd <= '1';
cmd <= (others => '0');
cmd_en <= '0';
cdc_out_free <= '1';
ps <= s_reset;
elsif falling_edge(ifclk) then
slrd <= '1';
cmd <= (others => '0');
cmd_en <= '0';
case ps is
when s_reset =>
slrd <= '1';
cmd <= (others => '0');
cmd_en <= '0';
cdc_out_free <= '1';
ps <= s_wait_for_cdc;
when s_wait_for_cdc =>
if faddr = cdcout then
ps <= s_read_data;
cdc_out_free <= '0';
end if;
when s_read_data =>
ps <= s_free_cdc;
if flag_empty = '1' then -- some data in fifo
slrd <= '0';
cmd_en <= '1';
cmd <= fdata;
end if;
when s_free_cdc =>
ps <= s_skip;
cdc_out_free <= '1';
when s_skip =>
ps <= s_wait_for_cdc;
when others =>
ps <= s_reset;
end case;
end if;
end process;
end architecture;
|
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity cdc_out is
port
(
-- in signals
fdata : in std_logic_vector(7 downto 0);
flag_empty : in std_logic;
faddr : in std_logic_vector(1 downto 0);
cdcout : in std_logic_vector(1 downto 0);
-- out signals
slrd : out std_logic;
cmd : out std_logic_vector(7 downto 0);
cmd_en : out std_logic;
cdc_out_free: out std_logic;
-- ifclk,rst
rst : in std_logic;
ifclk : in std_logic
);
end entity cdc_out;
architecture rtl of cdc_out is
type states is (s_wait_for_cdc,s_reset,s_read_data,s_free_cdc,s_skip);
signal ps : states;
begin -- architecture
process(ifclk,rst)
begin
if rst = '1' then
slrd <= '1';
cmd <= (others => '0');
cmd_en <= '0';
cdc_out_free <= '1';
ps <= s_reset;
elsif falling_edge(ifclk) then
slrd <= '1';
cmd <= (others => '0');
cmd_en <= '0';
case ps is
when s_reset =>
slrd <= '1';
cmd <= (others => '0');
cmd_en <= '0';
cdc_out_free <= '1';
ps <= s_wait_for_cdc;
when s_wait_for_cdc =>
if faddr = cdcout then
ps <= s_read_data;
cdc_out_free <= '0';
end if;
when s_read_data =>
ps <= s_free_cdc;
if flag_empty = '1' then -- some data in fifo
slrd <= '0';
cmd_en <= '1';
cmd <= fdata;
end if;
when s_free_cdc =>
ps <= s_skip;
cdc_out_free <= '1';
when s_skip =>
ps <= s_wait_for_cdc;
when others =>
ps <= s_reset;
end case;
end if;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2015.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p11n02i02015ent IS
END c07s02b02x00p11n02i02015ent;
ARCHITECTURE c07s02b02x00p11n02i02015arch OF c07s02b02x00p11n02i02015ent IS
BEGIN
TESTING: PROCESS
type array_three is array (1 to 6) of integer;
variable array_1 : array_three := (6,5,4,3,2,1);
variable array_2 : array_three := (6,5,4,4,3,2);
variable k : integer;
BEGIN
if array_1 < array_2 then -- No_failure_here
k := 5;
end if;
wait for 5 ns;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p11n02i02015"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c07s02b02x00p11n02i02015 - The relation < returns TRUE if the left operand is a null array and the right operand is a non-null array."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p11n02i02015arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2015.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p11n02i02015ent IS
END c07s02b02x00p11n02i02015ent;
ARCHITECTURE c07s02b02x00p11n02i02015arch OF c07s02b02x00p11n02i02015ent IS
BEGIN
TESTING: PROCESS
type array_three is array (1 to 6) of integer;
variable array_1 : array_three := (6,5,4,3,2,1);
variable array_2 : array_three := (6,5,4,4,3,2);
variable k : integer;
BEGIN
if array_1 < array_2 then -- No_failure_here
k := 5;
end if;
wait for 5 ns;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p11n02i02015"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c07s02b02x00p11n02i02015 - The relation < returns TRUE if the left operand is a null array and the right operand is a non-null array."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p11n02i02015arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2015.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p11n02i02015ent IS
END c07s02b02x00p11n02i02015ent;
ARCHITECTURE c07s02b02x00p11n02i02015arch OF c07s02b02x00p11n02i02015ent IS
BEGIN
TESTING: PROCESS
type array_three is array (1 to 6) of integer;
variable array_1 : array_three := (6,5,4,3,2,1);
variable array_2 : array_three := (6,5,4,4,3,2);
variable k : integer;
BEGIN
if array_1 < array_2 then -- No_failure_here
k := 5;
end if;
wait for 5 ns;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p11n02i02015"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c07s02b02x00p11n02i02015 - The relation < returns TRUE if the left operand is a null array and the right operand is a non-null array."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p11n02i02015arch;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := altera;
constant CFG_MEMTECH : integer := altera;
constant CFG_PADTECH : integer := altera;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 1 + 64*0;
constant CFG_ATBSZ : integer := 1;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := 1;
constant CFG_GRETH21G : integer := 0;
constant CFG_ETH2_FIFO : integer := 8;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#000F#;
constant CFG_GRGPIO_WIDTH : integer := (2);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
configuration notch_filter_down_to_device_level of notch_filter is
for opamp_based
for all : simple_opamp
use configuration work.opamp_mosfets;
end for;
-- ... -- bindings for other component instances
end for; -- end of architecture opamp_based
end configuration notch_filter_down_to_device_level;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
configuration notch_filter_down_to_device_level of notch_filter is
for opamp_based
for all : simple_opamp
use configuration work.opamp_mosfets;
end for;
-- ... -- bindings for other component instances
end for; -- end of architecture opamp_based
end configuration notch_filter_down_to_device_level;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
configuration notch_filter_down_to_device_level of notch_filter is
for opamp_based
for all : simple_opamp
use configuration work.opamp_mosfets;
end for;
-- ... -- bindings for other component instances
end for; -- end of architecture opamp_based
end configuration notch_filter_down_to_device_level;
|
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
library work ;
use work.cordic_p.all ;
entity cordic_tb is
end entity ; -- cordic_tb
architecture arch of cordic_tb is
signal clock : std_logic := '1' ;
signal reset : std_logic := '1' ;
signal inputs : cordic_xyz_t := ( x => (others =>'0'), y => (others =>'0'), z => (others =>'0'), valid => '0' );
signal outputs : cordic_xyz_t ;
signal outputs2 : cordic_xyz_t ;
procedure nop( signal clock : in std_logic ; count : in natural ) is
begin
for i in 1 to count loop
wait until rising_edge( clock ) ;
end loop ;
end procedure ; -- nop
begin
-- Generate clock
clock <= not clock after 1 ns ;
-- Magnitude/phase to cos+isin
U_cordic : entity work.cordic
port map (
clock => clock,
reset => reset,
mode => CORDIC_ROTATION,
inputs => inputs,
outputs => outputs
) ;
-- cos+isin to magnitude/phase
U_cordic2 : entity work.cordic
port map (
clock => clock,
reset => reset,
mode => CORDIC_VECTORING,
inputs => outputs,
outputs => outputs2
) ;
tb : process
variable ang : integer := 0 ;
variable dang : integer := integer(round(0.01*4096.0)) ;
begin
reset <= '1' ;
nop( clock, 10 ) ;
reset <= '0' ;
nop( clock, 10 ) ;
ang := 0 ;
inputs.x <= to_signed( integer(round(4096.0/1.66)), inputs.x'length ) ;
inputs.y <= to_signed( 0, inputs.y'length ) ;
for i in 0 to 10000 loop
inputs.z <= to_signed( ang, inputs.z'length ) ;
inputs.valid <= '1' ;
wait until rising_edge( clock ) ;
inputs.valid <= '0' ;
nop( clock, 20 ) ;
ang := ang + dang ;
if( ang > 4096 ) then
ang := ang - 8192 ;
elsif( ang < -4096 ) then
ang := ang + 8192 ;
end if ;
end loop ;
report "-- End of Simulation --" severity failure ;
end process ;
end architecture ; -- arch |
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : icon_5_port.vhd
-- /___/ /\ Timestamp : Wed Jul 02 12:03:04 BRT 2014
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY icon_5_port IS
port (
CONTROL0: inout std_logic_vector(35 downto 0);
CONTROL1: inout std_logic_vector(35 downto 0);
CONTROL2: inout std_logic_vector(35 downto 0);
CONTROL3: inout std_logic_vector(35 downto 0);
CONTROL4: inout std_logic_vector(35 downto 0));
END icon_5_port;
ARCHITECTURE icon_5_port_a OF icon_5_port IS
BEGIN
END icon_5_port_a;
|
-------------------------------------------------------------------------------
-- axi_ipif_ssp1.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: axi_ipif_ssp1.vhd
-- Version: v1.01.b
--
-- Description: AXI IPIF Slave Services Package 1
-- This block provides the following services:
-- - wraps the axi_lite_ipif interface to IPIC block and
-- sets up its address decoding.
-- - Provides the Software Reset register
-- - Provides interrupt servicing
-- - IPIC multiplexing service between the external IIC
-- register block IP2Bus data path and the internal
-- Interrupt controller's IP2Bus data path.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
-- NLR 01/07/11
-- ^^^^^^
-- - Updated the version to v1_01_b
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.or_reduce;
library axi_iic_v2_0;
library axi_lite_ipif_v3_0;
-- axi_lite_ipif refered from axi_lite_ipif_v2_0
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
library interrupt_control_v3_1;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_IIC_REGS -- Number of IIC registers
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
-- C_FAMILY -- Target FPGA architecture
-------------------------------------------------------------------------------
-- Definition of Ports:
-- System Signals
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- IP2INTC_Irpt -- System interrupt output
--
-- AXI signals
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
--
-- IP interconnect port signals
-- Bus2IP_Clk -- Bus to IIC clock
-- Bus2IP_Reset -- Bus to IIC reset
-- Bus2IIC_Addr -- Bus to IIC address
-- Bus2IIC_Data -- Bus to IIC data bus
-- Bus2IIC_RNW -- Bus to IIC read not write
-- Bus2IIC_RdCE -- Bus to IIC read chip enable
-- Bus2IIC_WrCE -- Bus to IIC write chip enable
-- IIC2Bus_Data -- IIC to Bus data bus
-- IIC2Bus_IntrEvent -- IIC Interrupt events
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity axi_ipif_ssp1 is
generic
(
C_NUM_IIC_REGS : integer := 10;
-- Number of IIC Registers
C_S_AXI_ADDR_WIDTH : integer := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_FAMILY : string := "virtex7"
-- Select the target architecture type
);
port
(
-- System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
IIC2Bus_IntrEvent : in std_logic_vector (0 to 7);
-- IIC Interrupt events
IIC2INTC_Irpt : out std_logic; -- IP-2-interrupt controller
-- AXI signals
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- IP Interconnect (IPIC) port signals used by the IIC registers.
Bus2IIC_Clk : out std_logic;
Bus2IIC_Reset : out std_logic;
Bus2IIC_Addr : out std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
Bus2IIC_Data : out std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
Bus2IIC_RNW : out std_logic;
Bus2IIC_RdCE : out std_logic_vector(0 to C_NUM_IIC_REGS-1);
Bus2IIC_WrCE : out std_logic_vector(0 to C_NUM_IIC_REGS-1);
IIC2Bus_Data : in std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1)
);
end entity axi_ipif_ssp1;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of axi_ipif_ssp1 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ZEROES : std_logic_vector(0 to 31) := X"00000000";
constant INTR_BASEADDR : std_logic_vector := X"00000000";
constant INTR_HIGHADDR : std_logic_vector
:= X"0000003F";
constant RST_BASEADDR : std_logic_vector
:= X"00000040";
constant RST_HIGHADDR : std_logic_vector
:= X"00000043";
constant IIC_REG_BASEADDR : std_logic_vector
:= X"00000100";
constant IIC_REG_HIGHADDR : std_logic_vector
:= X"000001FF";
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZEROES & INTR_BASEADDR, -- Interrupt controller
ZEROES & INTR_HIGHADDR,
ZEROES & RST_BASEADDR, -- Software reset register
ZEROES & RST_HIGHADDR,
ZEROES & IIC_REG_BASEADDR, -- IIC registers
ZEROES & IIC_REG_HIGHADDR
);
constant C_ARD_IDX_INTERRUPT : integer := 0;
constant C_ARD_IDX_RESET : integer := 1;
constant C_ARD_IDX_IIC_REGS : integer := 2;
-- The C_IP_INTR_MODE_ARRAY must have the same width as the IP2Bus_IntrEvent
-- entity port.
constant C_IP_INTR_MODE_ARRAY : integer_array_type
:= (3, 3, 3, 3, 3, 3, 3, 3);
constant C_INCLUDE_DEV_PENCODER : boolean := FALSE;
constant C_INCLUDE_DEV_ISC : boolean := FALSE;
constant C_NUM_INTERRUPT_REGS : integer := 16;
constant C_NUM_RESET_REGS : integer := 1;
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
C_ARD_IDX_INTERRUPT => C_NUM_INTERRUPT_REGS,
C_ARD_IDX_RESET => C_NUM_RESET_REGS,
C_ARD_IDX_IIC_REGS => C_NUM_IIC_REGS
);
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0)
:= X"000001FF";
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 8;
SUBTYPE INTERRUPT_CE_RNG is integer
range calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 0)
to calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 0)+C_ARD_NUM_CE_ARRAY(0)-1;
SUBTYPE RESET_CE_RNG is integer
range calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 1)
to calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 1)+C_ARD_NUM_CE_ARRAY(1)-1;
SUBTYPE IIC_CE_RNG is integer
range calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 2)
to calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 2)+C_ARD_NUM_CE_ARRAY(2)-1;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- IPIC Signals
signal AXI_Bus2IP_Clk : std_logic;
signal AXI_Bus2IP_Resetn: std_logic;
signal AXI_Bus2IP_Reset : std_logic;
signal AXI_IP2Bus_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
signal AXI_IP2Bus_WrAck : std_logic;
signal AXI_IP2Bus_RdAck : std_logic;
signal AXI_IP2Bus_WrAck1 : std_logic;
signal AXI_IP2Bus_RdAck1 : std_logic;
signal AXI_IP2Bus_WrAck2 : std_logic;
signal AXI_IP2Bus_RdAck2 : std_logic;
signal Intr2Bus_WrAck : std_logic;
signal Intr2Bus_RdAck : std_logic;
signal AXI_IP2Bus_Error : std_logic;
signal AXI_Bus2IP_Addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
signal AXI_Bus2IP_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
signal AXI_Bus2IP_RNW : std_logic;
signal AXI_Bus2IP_CS : std_logic_vector(0 to
((C_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal AXI_Bus2IP_RdCE : std_logic_vector(0 to
calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
signal AXI_Bus2IP_WrCE : std_logic_vector(0 to
calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
-- Derived IPIC signals for use with the reset register functionality
signal reset2Bus_Error : std_logic;
signal reset2IP_Reset : std_logic;
-- Derived IPIC signals for use with the interrupt controller
signal Intr2Bus_DevIntr : std_logic;
signal Intr2Bus_DBus : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- RESET signal assignment - IPIC RESET is active low
--------------------------------------------------------------------------
AXI_Bus2IP_Reset <= not AXI_Bus2IP_Resetn;
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map
(
-- System signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
-- AXI Interface signals
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => AXI_Bus2IP_Clk,
Bus2IP_Resetn => AXI_Bus2IP_Resetn,
IP2Bus_Data => AXI_IP2Bus_Data,
IP2Bus_WrAck => AXI_IP2Bus_WrAck,
IP2Bus_RdAck => AXI_IP2Bus_RdAck,
IP2Bus_Error => AXI_IP2Bus_Error,
Bus2IP_Addr => AXI_Bus2IP_Addr,
Bus2IP_Data => AXI_Bus2IP_Data,
Bus2IP_RNW => AXI_Bus2IP_RNW,
Bus2IP_BE => open,
Bus2IP_CS => AXI_Bus2IP_CS,
Bus2IP_RdCE => AXI_Bus2IP_RdCE,
Bus2IP_WrCE => AXI_Bus2IP_WrCE
);
-------------------------------------------------------------------------------
-- INTERRUPT DEVICE
-------------------------------------------------------------------------------
X_INTERRUPT_CONTROL : entity interrupt_control_v3_1.interrupt_control
generic map (
C_NUM_CE => C_NUM_INTERRUPT_REGS, -- [integer range 4 to 16]
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC => 1, -- [integer range 1 to 29]
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY, -- [INTEGER_ARRAY_TYPE]
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER => C_INCLUDE_DEV_PENCODER, -- [boolean]
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC => C_INCLUDE_DEV_ISC, -- [boolean]
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH -- [integer range 32 to 128]
)
port map (
-- Inputs From the IPIF Bus
Bus2IP_Clk => AXI_Bus2IP_Clk,
Bus2IP_Reset => reset2IP_Reset,
Bus2IP_Data => AXI_Bus2IP_Data,
Bus2IP_BE => "1111",
Interrupt_RdCE => AXI_Bus2IP_RdCE(INTERRUPT_CE_RNG),
Interrupt_WrCE => AXI_Bus2IP_WrCE(INTERRUPT_CE_RNG),
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts => "00",
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts => "0",
-- Inputs from the IP Interface
IP2Bus_IntrEvent => IIC2Bus_IntrEvent,
-- Final Device Interrupt Output
Intr2Bus_DevIntr => IIC2INTC_Irpt,
-- Status Reply Outputs to the Bus
Intr2Bus_DBus => Intr2Bus_DBus,
Intr2Bus_WrAck => open,
Intr2Bus_RdAck => open,
Intr2Bus_Error => open,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-------------------------------------------------------------------------------
-- SOFT RESET REGISTER
-------------------------------------------------------------------------------
X_SOFT_RESET : entity axi_iic_v2_0.soft_reset
generic map (
C_SIPIF_DWIDTH => C_S_AXI_DATA_WIDTH, -- [integer]
-- Width of the write data bus
C_RESET_WIDTH => 4)
port map (
-- Inputs From the IPIF Bus
Bus2IP_Reset => AXI_Bus2IP_Reset,
Bus2IP_Clk => AXI_Bus2IP_Clk,
Bus2IP_WrCE => AXI_Bus2IP_WrCE(RESET_CE_RNG'LEFT),
Bus2IP_Data => AXI_Bus2IP_Data,
Bus2IP_BE => "1111",
-- Final Device Reset Output
reset2IP_Reset => reset2IP_Reset,
-- Status Reply Outputs to the Bus
reset2Bus_WrAck => open,
reset2Bus_Error => reset2Bus_Error,
Reset2Bus_ToutSup => open);
-------------------------------------------------------------------------------
-- IIC Register (External) Connections
-------------------------------------------------------------------------------
Bus2IIC_Clk <= AXI_Bus2IP_Clk;
Bus2IIC_Reset <= reset2IP_Reset;
Bus2IIC_Addr <= AXI_Bus2IP_Addr;
Bus2IIC_Data <= AXI_Bus2IP_Data;
Bus2IIC_RNW <= AXI_Bus2IP_RNW;
Bus2IIC_RdCE <= AXI_Bus2IP_RdCE(IIC_CE_RNG);
Bus2IIC_WrCE <= AXI_Bus2IP_WrCE(IIC_CE_RNG);
-------------------------------------------------------------------------------
-- Read Ack/Write Ack generation
-------------------------------------------------------------------------------
process(AXI_Bus2IP_Clk)
begin
if(AXI_Bus2IP_Clk'event and AXI_Bus2IP_Clk = '1') then
AXI_IP2Bus_RdAck2 <= or_reduce(AXI_Bus2IP_CS) and AXI_Bus2IP_RNW;
AXI_IP2Bus_RdAck1 <= AXI_IP2Bus_RdAck2;
end if;
end process;
AXI_IP2Bus_RdAck <= (not (AXI_IP2Bus_RdAck1)) and AXI_IP2Bus_RdAck2;
process(AXI_Bus2IP_Clk)
begin
if(AXI_Bus2IP_Clk'event and AXI_Bus2IP_Clk = '1') then
AXI_IP2Bus_WrAck2 <= (or_reduce(AXI_Bus2IP_CS) and not AXI_Bus2IP_RNW);
AXI_IP2Bus_WrAck1 <= AXI_IP2Bus_WrAck2;
end if;
end process;
AXI_IP2Bus_WrAck <= (not AXI_IP2Bus_WrAck1) and AXI_IP2Bus_WrAck2;
-------------------------------------------------------------------------------
-- Data and Error generation
-------------------------------------------------------------------------------
AXI_IP2Bus_Data <= Intr2Bus_DBus or IIC2Bus_Data;
AXI_IP2Bus_Error <= reset2Bus_Error;
end architecture RTL;
|
-------------------------------------------------------------------------------
-- axi_ipif_ssp1.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: axi_ipif_ssp1.vhd
-- Version: v1.01.b
--
-- Description: AXI IPIF Slave Services Package 1
-- This block provides the following services:
-- - wraps the axi_lite_ipif interface to IPIC block and
-- sets up its address decoding.
-- - Provides the Software Reset register
-- - Provides interrupt servicing
-- - IPIC multiplexing service between the external IIC
-- register block IP2Bus data path and the internal
-- Interrupt controller's IP2Bus data path.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
-- NLR 01/07/11
-- ^^^^^^
-- - Updated the version to v1_01_b
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.or_reduce;
library axi_iic_v2_0;
library axi_lite_ipif_v3_0;
-- axi_lite_ipif refered from axi_lite_ipif_v2_0
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
library interrupt_control_v3_1;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_IIC_REGS -- Number of IIC registers
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
-- C_FAMILY -- Target FPGA architecture
-------------------------------------------------------------------------------
-- Definition of Ports:
-- System Signals
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- IP2INTC_Irpt -- System interrupt output
--
-- AXI signals
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
--
-- IP interconnect port signals
-- Bus2IP_Clk -- Bus to IIC clock
-- Bus2IP_Reset -- Bus to IIC reset
-- Bus2IIC_Addr -- Bus to IIC address
-- Bus2IIC_Data -- Bus to IIC data bus
-- Bus2IIC_RNW -- Bus to IIC read not write
-- Bus2IIC_RdCE -- Bus to IIC read chip enable
-- Bus2IIC_WrCE -- Bus to IIC write chip enable
-- IIC2Bus_Data -- IIC to Bus data bus
-- IIC2Bus_IntrEvent -- IIC Interrupt events
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity axi_ipif_ssp1 is
generic
(
C_NUM_IIC_REGS : integer := 10;
-- Number of IIC Registers
C_S_AXI_ADDR_WIDTH : integer := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_FAMILY : string := "virtex7"
-- Select the target architecture type
);
port
(
-- System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
IIC2Bus_IntrEvent : in std_logic_vector (0 to 7);
-- IIC Interrupt events
IIC2INTC_Irpt : out std_logic; -- IP-2-interrupt controller
-- AXI signals
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- IP Interconnect (IPIC) port signals used by the IIC registers.
Bus2IIC_Clk : out std_logic;
Bus2IIC_Reset : out std_logic;
Bus2IIC_Addr : out std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
Bus2IIC_Data : out std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
Bus2IIC_RNW : out std_logic;
Bus2IIC_RdCE : out std_logic_vector(0 to C_NUM_IIC_REGS-1);
Bus2IIC_WrCE : out std_logic_vector(0 to C_NUM_IIC_REGS-1);
IIC2Bus_Data : in std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1)
);
end entity axi_ipif_ssp1;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of axi_ipif_ssp1 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ZEROES : std_logic_vector(0 to 31) := X"00000000";
constant INTR_BASEADDR : std_logic_vector := X"00000000";
constant INTR_HIGHADDR : std_logic_vector
:= X"0000003F";
constant RST_BASEADDR : std_logic_vector
:= X"00000040";
constant RST_HIGHADDR : std_logic_vector
:= X"00000043";
constant IIC_REG_BASEADDR : std_logic_vector
:= X"00000100";
constant IIC_REG_HIGHADDR : std_logic_vector
:= X"000001FF";
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZEROES & INTR_BASEADDR, -- Interrupt controller
ZEROES & INTR_HIGHADDR,
ZEROES & RST_BASEADDR, -- Software reset register
ZEROES & RST_HIGHADDR,
ZEROES & IIC_REG_BASEADDR, -- IIC registers
ZEROES & IIC_REG_HIGHADDR
);
constant C_ARD_IDX_INTERRUPT : integer := 0;
constant C_ARD_IDX_RESET : integer := 1;
constant C_ARD_IDX_IIC_REGS : integer := 2;
-- The C_IP_INTR_MODE_ARRAY must have the same width as the IP2Bus_IntrEvent
-- entity port.
constant C_IP_INTR_MODE_ARRAY : integer_array_type
:= (3, 3, 3, 3, 3, 3, 3, 3);
constant C_INCLUDE_DEV_PENCODER : boolean := FALSE;
constant C_INCLUDE_DEV_ISC : boolean := FALSE;
constant C_NUM_INTERRUPT_REGS : integer := 16;
constant C_NUM_RESET_REGS : integer := 1;
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
C_ARD_IDX_INTERRUPT => C_NUM_INTERRUPT_REGS,
C_ARD_IDX_RESET => C_NUM_RESET_REGS,
C_ARD_IDX_IIC_REGS => C_NUM_IIC_REGS
);
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0)
:= X"000001FF";
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 8;
SUBTYPE INTERRUPT_CE_RNG is integer
range calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 0)
to calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 0)+C_ARD_NUM_CE_ARRAY(0)-1;
SUBTYPE RESET_CE_RNG is integer
range calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 1)
to calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 1)+C_ARD_NUM_CE_ARRAY(1)-1;
SUBTYPE IIC_CE_RNG is integer
range calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 2)
to calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 2)+C_ARD_NUM_CE_ARRAY(2)-1;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- IPIC Signals
signal AXI_Bus2IP_Clk : std_logic;
signal AXI_Bus2IP_Resetn: std_logic;
signal AXI_Bus2IP_Reset : std_logic;
signal AXI_IP2Bus_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
signal AXI_IP2Bus_WrAck : std_logic;
signal AXI_IP2Bus_RdAck : std_logic;
signal AXI_IP2Bus_WrAck1 : std_logic;
signal AXI_IP2Bus_RdAck1 : std_logic;
signal AXI_IP2Bus_WrAck2 : std_logic;
signal AXI_IP2Bus_RdAck2 : std_logic;
signal Intr2Bus_WrAck : std_logic;
signal Intr2Bus_RdAck : std_logic;
signal AXI_IP2Bus_Error : std_logic;
signal AXI_Bus2IP_Addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
signal AXI_Bus2IP_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
signal AXI_Bus2IP_RNW : std_logic;
signal AXI_Bus2IP_CS : std_logic_vector(0 to
((C_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal AXI_Bus2IP_RdCE : std_logic_vector(0 to
calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
signal AXI_Bus2IP_WrCE : std_logic_vector(0 to
calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
-- Derived IPIC signals for use with the reset register functionality
signal reset2Bus_Error : std_logic;
signal reset2IP_Reset : std_logic;
-- Derived IPIC signals for use with the interrupt controller
signal Intr2Bus_DevIntr : std_logic;
signal Intr2Bus_DBus : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- RESET signal assignment - IPIC RESET is active low
--------------------------------------------------------------------------
AXI_Bus2IP_Reset <= not AXI_Bus2IP_Resetn;
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map
(
-- System signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
-- AXI Interface signals
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => AXI_Bus2IP_Clk,
Bus2IP_Resetn => AXI_Bus2IP_Resetn,
IP2Bus_Data => AXI_IP2Bus_Data,
IP2Bus_WrAck => AXI_IP2Bus_WrAck,
IP2Bus_RdAck => AXI_IP2Bus_RdAck,
IP2Bus_Error => AXI_IP2Bus_Error,
Bus2IP_Addr => AXI_Bus2IP_Addr,
Bus2IP_Data => AXI_Bus2IP_Data,
Bus2IP_RNW => AXI_Bus2IP_RNW,
Bus2IP_BE => open,
Bus2IP_CS => AXI_Bus2IP_CS,
Bus2IP_RdCE => AXI_Bus2IP_RdCE,
Bus2IP_WrCE => AXI_Bus2IP_WrCE
);
-------------------------------------------------------------------------------
-- INTERRUPT DEVICE
-------------------------------------------------------------------------------
X_INTERRUPT_CONTROL : entity interrupt_control_v3_1.interrupt_control
generic map (
C_NUM_CE => C_NUM_INTERRUPT_REGS, -- [integer range 4 to 16]
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC => 1, -- [integer range 1 to 29]
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY, -- [INTEGER_ARRAY_TYPE]
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER => C_INCLUDE_DEV_PENCODER, -- [boolean]
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC => C_INCLUDE_DEV_ISC, -- [boolean]
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH -- [integer range 32 to 128]
)
port map (
-- Inputs From the IPIF Bus
Bus2IP_Clk => AXI_Bus2IP_Clk,
Bus2IP_Reset => reset2IP_Reset,
Bus2IP_Data => AXI_Bus2IP_Data,
Bus2IP_BE => "1111",
Interrupt_RdCE => AXI_Bus2IP_RdCE(INTERRUPT_CE_RNG),
Interrupt_WrCE => AXI_Bus2IP_WrCE(INTERRUPT_CE_RNG),
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts => "00",
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts => "0",
-- Inputs from the IP Interface
IP2Bus_IntrEvent => IIC2Bus_IntrEvent,
-- Final Device Interrupt Output
Intr2Bus_DevIntr => IIC2INTC_Irpt,
-- Status Reply Outputs to the Bus
Intr2Bus_DBus => Intr2Bus_DBus,
Intr2Bus_WrAck => open,
Intr2Bus_RdAck => open,
Intr2Bus_Error => open,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-------------------------------------------------------------------------------
-- SOFT RESET REGISTER
-------------------------------------------------------------------------------
X_SOFT_RESET : entity axi_iic_v2_0.soft_reset
generic map (
C_SIPIF_DWIDTH => C_S_AXI_DATA_WIDTH, -- [integer]
-- Width of the write data bus
C_RESET_WIDTH => 4)
port map (
-- Inputs From the IPIF Bus
Bus2IP_Reset => AXI_Bus2IP_Reset,
Bus2IP_Clk => AXI_Bus2IP_Clk,
Bus2IP_WrCE => AXI_Bus2IP_WrCE(RESET_CE_RNG'LEFT),
Bus2IP_Data => AXI_Bus2IP_Data,
Bus2IP_BE => "1111",
-- Final Device Reset Output
reset2IP_Reset => reset2IP_Reset,
-- Status Reply Outputs to the Bus
reset2Bus_WrAck => open,
reset2Bus_Error => reset2Bus_Error,
Reset2Bus_ToutSup => open);
-------------------------------------------------------------------------------
-- IIC Register (External) Connections
-------------------------------------------------------------------------------
Bus2IIC_Clk <= AXI_Bus2IP_Clk;
Bus2IIC_Reset <= reset2IP_Reset;
Bus2IIC_Addr <= AXI_Bus2IP_Addr;
Bus2IIC_Data <= AXI_Bus2IP_Data;
Bus2IIC_RNW <= AXI_Bus2IP_RNW;
Bus2IIC_RdCE <= AXI_Bus2IP_RdCE(IIC_CE_RNG);
Bus2IIC_WrCE <= AXI_Bus2IP_WrCE(IIC_CE_RNG);
-------------------------------------------------------------------------------
-- Read Ack/Write Ack generation
-------------------------------------------------------------------------------
process(AXI_Bus2IP_Clk)
begin
if(AXI_Bus2IP_Clk'event and AXI_Bus2IP_Clk = '1') then
AXI_IP2Bus_RdAck2 <= or_reduce(AXI_Bus2IP_CS) and AXI_Bus2IP_RNW;
AXI_IP2Bus_RdAck1 <= AXI_IP2Bus_RdAck2;
end if;
end process;
AXI_IP2Bus_RdAck <= (not (AXI_IP2Bus_RdAck1)) and AXI_IP2Bus_RdAck2;
process(AXI_Bus2IP_Clk)
begin
if(AXI_Bus2IP_Clk'event and AXI_Bus2IP_Clk = '1') then
AXI_IP2Bus_WrAck2 <= (or_reduce(AXI_Bus2IP_CS) and not AXI_Bus2IP_RNW);
AXI_IP2Bus_WrAck1 <= AXI_IP2Bus_WrAck2;
end if;
end process;
AXI_IP2Bus_WrAck <= (not AXI_IP2Bus_WrAck1) and AXI_IP2Bus_WrAck2;
-------------------------------------------------------------------------------
-- Data and Error generation
-------------------------------------------------------------------------------
AXI_IP2Bus_Data <= Intr2Bus_DBus or IIC2Bus_Data;
AXI_IP2Bus_Error <= reset2Bus_Error;
end architecture RTL;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLMULT_SDNF1_3_block3.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLMULT_SDNF1_3_block3
-- Source Path: hdl_ofdm_tx/ifft/TWDLMULT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TWDLMULT_SDNF1_3_block3 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_9_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_9_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_11_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_11_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_2_vld : IN std_logic;
twdl_3_9_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_9_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_9_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_9_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_10_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_10_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_9_vld : OUT std_logic
);
END TWDLMULT_SDNF1_3_block3;
ARCHITECTURE rtl OF TWDLMULT_SDNF1_3_block3 IS
-- Component Declarations
COMPONENT Complex3Multiply_block5
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din2_re_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
din2_im_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
di2_vld_dly3 : IN std_logic;
twdl_3_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_10_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_10_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin2_vld : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Complex3Multiply_block5
USE ENTITY work.Complex3Multiply_block5(rtl);
-- Signals
SIGNAL dout_9_re_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_re : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly4 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly5 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly6 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly7 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly8 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly9 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_9_im_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_im : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly4 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly5 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly6 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly7 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly8 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly9 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_11_re_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_re_1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_11_im_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_im_1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL di2_vld_dly1 : std_logic;
SIGNAL di2_vld_dly2 : std_logic;
SIGNAL di2_vld_dly3 : std_logic;
SIGNAL twdlXdin_10_re_tmp : std_logic_vector(18 DOWNTO 0); -- ufix19
SIGNAL twdlXdin_10_im_tmp : std_logic_vector(18 DOWNTO 0); -- ufix19
BEGIN
u_MUL3_2 : Complex3Multiply_block5
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
din2_re_dly3 => std_logic_vector(din2_re_dly3), -- sfix19_En13
din2_im_dly3 => std_logic_vector(din2_im_dly3), -- sfix19_En13
di2_vld_dly3 => di2_vld_dly3,
twdl_3_10_re => twdl_3_10_re, -- sfix16_En14
twdl_3_10_im => twdl_3_10_im, -- sfix16_En14
softReset => softReset,
twdlXdin_10_re => twdlXdin_10_re_tmp, -- sfix19_En13
twdlXdin_10_im => twdlXdin_10_im_tmp, -- sfix19_En13
twdlXdin2_vld => twdlXdin_9_vld
);
dout_9_re_signed <= signed(dout_9_re);
din_re <= resize(dout_9_re_signed, 19);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly1 <= din_re;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly2 <= din1_re_dly1;
END IF;
END IF;
END PROCESS intdelay_1_process;
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly3 <= din1_re_dly2;
END IF;
END IF;
END PROCESS intdelay_2_process;
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly4 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly4 <= din1_re_dly3;
END IF;
END IF;
END PROCESS intdelay_3_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly5 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly5 <= din1_re_dly4;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly6 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly6 <= din1_re_dly5;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly7 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly7 <= din1_re_dly6;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly8 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly8 <= din1_re_dly7;
END IF;
END IF;
END PROCESS intdelay_7_process;
intdelay_8_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly9 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly9 <= din1_re_dly8;
END IF;
END IF;
END PROCESS intdelay_8_process;
twdlXdin_9_re <= std_logic_vector(din1_re_dly9);
dout_9_im_signed <= signed(dout_9_im);
din_im <= resize(dout_9_im_signed, 19);
intdelay_9_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly1 <= din_im;
END IF;
END IF;
END PROCESS intdelay_9_process;
intdelay_10_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly2 <= din1_im_dly1;
END IF;
END IF;
END PROCESS intdelay_10_process;
intdelay_11_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly3 <= din1_im_dly2;
END IF;
END IF;
END PROCESS intdelay_11_process;
intdelay_12_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly4 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly4 <= din1_im_dly3;
END IF;
END IF;
END PROCESS intdelay_12_process;
intdelay_13_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly5 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly5 <= din1_im_dly4;
END IF;
END IF;
END PROCESS intdelay_13_process;
intdelay_14_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly6 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly6 <= din1_im_dly5;
END IF;
END IF;
END PROCESS intdelay_14_process;
intdelay_15_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly7 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly7 <= din1_im_dly6;
END IF;
END IF;
END PROCESS intdelay_15_process;
intdelay_16_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly8 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly8 <= din1_im_dly7;
END IF;
END IF;
END PROCESS intdelay_16_process;
intdelay_17_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly9 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly9 <= din1_im_dly8;
END IF;
END IF;
END PROCESS intdelay_17_process;
twdlXdin_9_im <= std_logic_vector(din1_im_dly9);
dout_11_re_signed <= signed(dout_11_re);
din_re_1 <= resize(dout_11_re_signed, 19);
intdelay_18_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly1 <= din_re_1;
END IF;
END IF;
END PROCESS intdelay_18_process;
intdelay_19_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly2 <= din2_re_dly1;
END IF;
END IF;
END PROCESS intdelay_19_process;
dout_11_im_signed <= signed(dout_11_im);
din_im_1 <= resize(dout_11_im_signed, 19);
intdelay_20_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly1 <= din_im_1;
END IF;
END IF;
END PROCESS intdelay_20_process;
intdelay_21_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly2 <= din2_im_dly1;
END IF;
END IF;
END PROCESS intdelay_21_process;
intdelay_22_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly3 <= din2_re_dly2;
END IF;
END IF;
END PROCESS intdelay_22_process;
intdelay_23_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly3 <= din2_im_dly2;
END IF;
END IF;
END PROCESS intdelay_23_process;
intdelay_24_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_24_process;
intdelay_25_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly2 <= di2_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_25_process;
intdelay_26_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly3 <= di2_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_26_process;
twdlXdin_10_re <= twdlXdin_10_re_tmp;
twdlXdin_10_im <= twdlXdin_10_im_tmp;
END rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_icache
-- File: mmu_icache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Edvin Catovic - Gaisler Research
-- Description: This unit implements the instruction cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.leon3.all;
entity mmu_icache is
generic (
memtech : integer := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
lram : integer range 0 to 1 := 0;
lramsize : integer range 1 to 512 := 1;
lramstart : integer range 0 to 255 := 16#8e#;
mmuen : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : in dcache_out_type;
mcii : out memory_ic_in_type;
mcio : in memory_ic_out_type;
icrami : out icram_in_type;
icramo : in icram_out_type;
fpuholdn : in std_ulogic;
mmudci : in mmudc_in_type;
mmuici : out mmuic_in_type;
mmuico : in mmuic_out_type
);
end;
architecture rtl of mmu_icache is
constant MUXDATA : boolean := (is_fpga(memtech) = 1);
constant M_EN : boolean := (mmuen = 1);
constant ILINE_BITS : integer := log2(ilinesize);
constant IOFFSET_BITS : integer := 8 +log2(isetsize) - ILINE_BITS;
constant TAG_LOW : integer := IOFFSET_BITS + ILINE_BITS + 2;
constant OFFSET_HIGH : integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := ILINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant lline : std_logic_vector((ILINE_BITS -1) downto 0) := (others => '1');
constant fline : std_logic_vector((ILINE_BITS -1) downto 0) := (others => '0');
constant SETBITS : integer := log2x(ISETS);
constant ILRUBITS : integer := lru_table(ISETS);
constant LRAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(lramstart, 8);
constant LRAM_BITS : integer := log2(lramsize) + 10;
constant LRAMCS_EN : boolean := false;
subtype lru_type is std_logic_vector(ILRUBITS-1 downto 0);
type lru_array is array (0 to 2**IOFFSET_BITS-1) of lru_type; -- lru registers
type rdatatype is (itag, idata, memory); -- sources during cache read
type lru_table_vector_type is array(0 to 3) of std_logic_vector(4 downto 0);
type lru_table_type is array (0 to 2**IOFFSET_BITS-1) of lru_table_vector_type;
type valid_type is array (0 to ISETS-1) of std_logic_vector(ilinesize - 1 downto 0);
subtype lock_type is std_logic_vector(0 to ISETS-1);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to ISETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(ILRUBITS-1 downto 0) := lru;
if isetlock = 1 then
unlocked := ISETS-1;
for i in ISETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case ISETS is
when 2 =>
if isetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else xset(0) := xlru(0); end if;
when 3 =>
if isetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
-- xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
xset := xlru(2) & (xlru(1) and not xlru(2));
end if;
when 4 =>
if isetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
-- xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
xset := xlru(4 downto 3);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; xset : std_logic_vector) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
variable vset : std_logic_vector(SETBITS-1 downto 0);
variable set: integer;
begin
vset := xset; set := conv_integer(vset);
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(ILRUBITS-1 downto 0) := lru;
case ISETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
xnew_lru(SETBITS-1 downto 0) := vset;
when others =>
end case;
new_lru := xnew_lru(ILRUBITS-1 downto 0);
return(new_lru);
end;
type istatetype is (idle, trans, streaming, stop);
type icache_control_type is record -- all registers
req, burst, holdn : std_ulogic;
overrun : std_ulogic;
underrun : std_ulogic;
istate : istatetype; -- FSM vector
waddress : std_logic_vector(31 downto 2); -- write address buffer
vaddress : std_logic_vector(31 downto 2); -- virtual address buffer
valid : valid_type; --std_logic_vector(ilinesize-1 downto 0); -- valid bits
hit : std_ulogic;
su : std_ulogic;
flush : std_ulogic; -- flush in progress
flush2 : std_ulogic; -- flush in progress
faddr : std_logic_vector(IOFFSET_BITS - 1 downto 0); -- flush address
diagrdy : std_ulogic;
rndcnt : std_logic_vector(log2x(ISETS)-1 downto 0); -- replace counter
lrr : std_ulogic;
setrepl : std_logic_vector(log2x(ISETS)-1 downto 0); -- set to replace
diagset : std_logic_vector(log2x(ISETS)-1 downto 0);
lock : std_ulogic;
pflush : std_logic;
pflushr : std_logic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_logic;
cache : std_logic;
trans_op : std_logic;
cmiss : std_ulogic;
bpmiss : std_ulogic;
eocl : std_ulogic;
end record;
type lru_reg_type is record
write : std_ulogic;
waddr : std_logic_vector(IOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0); --integer range 0 to ISETS-1;
lru : lru_array;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : icache_control_type := (
req => '0',
burst => '0',
holdn => '1',
overrun => '0',
underrun => '0',
istate => idle,
waddress => (others => '0'), -- has special handling
vaddress => (others => '0'), -- has special handling
valid => (others => (others => '0')),
hit => '0',
su => '0',
flush => '0',
flush2 => '0',
faddr => (others => '0'),
diagrdy => '0',
rndcnt => (others => '0'),
lrr => '0',
setrepl => (others => '0'),
diagset => (others => '0'),
lock => '0',
pflush => '0',
pflushr => '0',
pflushaddr => (others => '0'),
pflushtyp => '0',
cache => '0',
trans_op => '0',
cmiss => '0',
bpmiss => '0',
eocl => '0'
);
constant LRES : lru_reg_type := (
write => '0',
waddr => (others => '0'),
set => (others => '0'),
lru => (others => (others => '0'))
);
signal r, c : icache_control_type; -- r is registers, c is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
constant icfg : std_logic_vector(31 downto 0) :=
cache_cfg(irepl, isets, ilinesize, isetsize, isetlock, 0,
lram, lramsize, lramstart, mmuen);
begin
ictrl : process(rst, r, rl, mcio, ici, dci, dco, icramo, fpuholdn, mmuico, mmudci)
variable rdatasel : rdatatype;
variable twrite, diagen, dwrite : std_ulogic;
variable taddr : std_logic_vector(TAG_HIGH downto LINE_LOW); -- tag address
variable wtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- write tag value
variable ddatain : std_logic_vector(31 downto 0);
variable rdata : cdatatype;
variable diagdata : std_logic_vector(31 downto 0);
variable vmaskraw : std_logic_vector((ilinesize -1) downto 0);
variable vmask : valid_type;
variable xaddr_inc : std_logic_vector((ILINE_BITS -1) downto 0);
variable lastline, nlastline, nnlastline : std_ulogic;
variable enable : std_ulogic;
variable error : std_ulogic;
variable whit, hit, valid, nvalid : std_ulogic;
variable cacheon : std_ulogic;
variable v : icache_control_type;
variable branch : std_ulogic;
variable eholdn : std_ulogic;
variable mds, write : std_ulogic;
variable memaddr : std_logic_vector(31 downto 2);
variable set : integer range 0 to MAXSETS-1;
variable setrepl : std_logic_vector(log2x(ISETS)-1 downto 0); -- set to replace
variable ctwrite, cdwrite, validv, nvalidv : std_logic_vector(0 to MAXSETS-1);
variable wlrr : std_ulogic;
variable vl : lru_reg_type;
variable vdiagset, rdiagset : integer range 0 to ISETS-1;
variable lock : std_logic_vector(0 to ISETS-1);
variable wlock : std_ulogic;
variable tag : cdatatype;
variable lramacc, ilramwr, lramcs : std_ulogic;
variable pftag : std_logic_vector(31 downto 2);
variable mmuici_trans_op : std_logic;
variable mmuici_su : std_logic;
variable mhold : std_ulogic;
variable shtag : std_logic_vector(ilinesize-1 downto 0);
begin
-- init local variables
v := r; vl := rl; vl.write := '0'; vl.set := r.setrepl;
vl.waddr := r.waddress(OFFSET_HIGH downto OFFSET_LOW);
v.cmiss := '0'; mhold := '0';
mds := '1'; dwrite := '0'; twrite := '0'; diagen := '0'; error := '0';
write := mcio.ready; v.diagrdy := '0'; v.holdn := '1';
if icen /= 0 then
cacheon := dco.icdiag.cctrl.ics(0) and not (r.flush
);
else cacheon := '0'; end if;
enable := '1'; branch := '0';
eholdn := dco.hold and fpuholdn;
rdatasel := idata; -- read data from cache as default
ddatain := mcio.data; -- load full word from memory
wtag(TAG_HIGH downto TAG_LOW) := r.vaddress(TAG_HIGH downto TAG_LOW);
wlrr := r.lrr; wlock := r.lock;
set := 0; ctwrite := (others => '0'); cdwrite := (others => '0');
vdiagset := 0; rdiagset := 0; lock := (others => '0'); ilramwr := '0';
lramacc := '0'; lramcs := '0';
vdiagset := 0; rdiagset := 0; lock := (others => '0');
pftag := (others => '0'); validv := (others => '0');
v.trans_op := r.trans_op and (not mmuico.grant);
mmuici_trans_op := r.trans_op;
mmuici_su := ici.su;
-- random replacement counter
if ISETS > 1 then
if conv_integer(r.rndcnt) = (ISETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
if isetlock = 1 then
for i in 0 to ISETS-1 loop lock(i) := icramo.tag(i)(CTAG_LOCKPOS); end loop;
end if;
--local ram access
if (lram = 1) and (ici.fpc(31 downto 24) = LRAM_START) then lramacc := '1'; end if;
-- generate cache hit and valid bits
hit := '0';
if irepl = dir then
set := conv_integer(ici.fpc(OFFSET_HIGH + SETBITS downto OFFSET_HIGH+1));
if (icramo.tag(set)(TAG_HIGH downto TAG_LOW) = ici.fpc(TAG_HIGH downto TAG_LOW))
and ((icramo.ctx(set) = mmudci.mmctrl1.ctx) or (mmudci.mmctrl1.e = '0') or not M_EN)
then hit := not r.flush; end if;
validv(set) := genmux(ici.fpc(LINE_HIGH downto LINE_LOW),
icramo.tag(set)(ilinesize -1 downto 0));
else
for i in ISETS-1 downto 0 loop
if (icramo.tag(i)(TAG_HIGH downto TAG_LOW) = ici.fpc(TAG_HIGH downto TAG_LOW))
and ((icramo.ctx(i) = mmudci.mmctrl1.ctx) or (mmudci.mmctrl1.e = '0') or not M_EN)
then hit := not r.flush; set := i; end if;
validv(i) := genmux(ici.fpc(LINE_HIGH downto LINE_LOW),
icramo.tag(i)(ilinesize -1 downto 0));
end loop;
end if;
for i in ISETS-1 downto 0 loop
shtag := (others => '0');
shtag(ilinesize-2 downto 0) := icramo.tag(i)(ilinesize-1 downto 1);
nvalidv(i) := genmux(ici.fpc(LINE_HIGH downto LINE_LOW), shtag);
end loop;
if (lramacc = '1') and (ISETS > 1) then set := 1; end if;
if ici.fpc(LINE_HIGH downto LINE_LOW) = lline then lastline := '1';
else lastline := '0'; end if;
if r.waddress(LINE_HIGH downto LINE_LOW) = lline((ILINE_BITS -1) downto 0) then
nlastline := '1';
else nlastline := '0'; end if;
if r.waddress(LINE_HIGH downto LINE_LOW+1) = lline((ILINE_BITS -1) downto 1) then
nnlastline := '1';
else nnlastline := '0'; end if;
valid := validv(set);
nvalid := nvalidv(set);
xaddr_inc := r.waddress(LINE_HIGH downto LINE_LOW) + 1;
if mcio.ready = '1' then
v.waddress(LINE_HIGH downto LINE_LOW) := xaddr_inc;
end if;
xaddr_inc := r.vaddress(LINE_HIGH downto LINE_LOW) + 1;
if mcio.ready = '1' then
v.vaddress(LINE_HIGH downto LINE_LOW) := xaddr_inc;
end if;
taddr := ici.rpc(TAG_HIGH downto LINE_LOW);
-- main state machine
case r.istate is
when idle => -- main state and cache hit
for i in 0 to ISETS-1 loop
v.valid(i) := icramo.tag(i)(ilinesize-1 downto 0);
end loop;
--v.hit := '0';
v.hit := hit;
v.su := ici.su;
-- if (ici.inull or eholdn) = '0' then
if eholdn = '0' then
taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
else taddr := ici.rpc(TAG_HIGH downto LINE_LOW); end if;
v.burst := dco.icdiag.cctrl.burst and not lastline;
if (eholdn and not (ici.inull or lramacc)) = '1' then
v.bpmiss := not (cacheon and hit and valid) and ici.nobpmiss;
v.eocl := not nvalid;
if not (cacheon and hit and valid) = '1' and ici.nobpmiss='0' then
v.istate := streaming;
v.holdn := '0'; v.overrun := '1'; v.cmiss := '1';
if M_EN and (mmudci.mmctrl1.e = '1') then
v.istate := trans;
mmuici_trans_op := '1';
v.trans_op := not mmuico.grant;
v.cache := '0';
--v.req := '0';
else
v.req := '1';
v.cache := '1';
end if;
else
if (ISETS > 1) and (irepl = lru) then vl.write := '1'; end if;
end if;
v.waddress := ici.fpc(31 downto 2);
v.vaddress := ici.fpc(31 downto 2);
end if;
if dco.icdiag.enable = '1' then
diagen := '1';
end if;
ddatain := dci.maddress;
if (ISETS > 1) then
if (irepl = lru) then
vl.set := conv_std_logic_vector(set, SETBITS);
vl.waddr := ici.fpc(OFFSET_HIGH downto OFFSET_LOW);
end if;
v.setrepl := conv_std_logic_vector(set, SETBITS);
if (((not hit) and (not r.flush)) = '1') then
case irepl is
when rnd =>
if isetlock = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(ISETS-1, SETBITS);
for i in ISETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when dir =>
v.setrepl := ici.fpc(OFFSET_HIGH+SETBITS downto OFFSET_HIGH+1);
when lru =>
v.setrepl := lru_set(rl.lru(conv_integer(ici.fpc(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to ISETS-1));
when lrr =>
v.setrepl := (others => '0');
if isetlock = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := icramo.tag(0)(CTAG_LRRPOS) xor icramo.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := icramo.tag(0)(CTAG_LRRPOS) xor icramo.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then v.lrr := not icramo.tag(0)(CTAG_LRRPOS);
else v.lrr := icramo.tag(0)(CTAG_LRRPOS); end if;
end case;
end if;
if (isetlock = 1) then
if (hit and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
when trans =>
if M_EN then
v.holdn := '0';
if (mmuico.transdata.finish = '1') then
if mmuico.transdata.accexc = '1' then
-- if su then always do mexc
error := r.su or not mmudci.mmctrl1.nf; mds := '0';
v.holdn := '0'; v.istate := stop; v.burst := '0';
else
v.cache := mmuico.transdata.cache;
v.waddress := mmuico.transdata.data(31 downto 2);
v.istate := streaming; v.req := '1';
end if;
end if;
mhold := '1';
end if;
when streaming => -- streaming: update cache and send data to IU
rdatasel := memory;
taddr(TAG_HIGH downto LINE_LOW) := r.vaddress(TAG_HIGH downto LINE_LOW);
branch := (ici.fbranch and r.overrun) or
(ici.rbranch and (not r.overrun));
v.underrun := r.underrun or
(write and ((ici.inull or not eholdn) and (mcio.ready and not (r.overrun and not r.underrun))));
v.overrun := (r.overrun or (eholdn and not ici.inull)) and
not (write or r.underrun);
if mcio.ready = '1' then
-- mds := not (v.overrun and not r.underrun);
mds := not (r.overrun and not r.underrun);
-- v.req := r.burst;
v.burst := v.req and not (nnlastline and mcio.ready);
end if;
if mcio.grant = '1' then
v.req := dco.icdiag.cctrl.burst and r.burst and
(not (nnlastline and mcio.ready)) and (dco.icdiag.cctrl.burst or (not branch)) and
not (v.underrun and not cacheon);
v.burst := v.req and not (nnlastline and mcio.ready);
end if;
v.underrun := (v.underrun or branch) and not v.overrun;
v.holdn := not (v.overrun or v.underrun);
if (mcio.ready = '1') and (r.req = '0') then --(v.burst = '0') then
v.underrun := '0'; v.overrun := '0';
v.istate := stop; v.holdn := '0';
end if;
when stop => -- return to main
taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
v.istate := idle; v.flush := r.flush2;
when others => v.istate := idle;
end case;
if mcio.retry = '1' then v.req := '1'; end if;
if lram = 1 then
if LRAMCS_EN then
if taddr(31 downto 24) = LRAM_START then lramcs := '1'; else lramcs := '0'; end if;
else
lramcs := '1';
end if;
end if;
-- Generate new valid bits write strobe
vmaskraw := decode(r.waddress(LINE_HIGH downto LINE_LOW));
twrite := write;
if cacheon = '0' then
twrite := '0'; vmask := (others => (others => '0'));
elsif (dco.icdiag.cctrl.ics = "01") then
twrite := twrite and r.hit;
for i in 0 to ISETS-1 loop
vmask(i) := icramo.tag(i)(ilinesize-1 downto 0) or vmaskraw;
end loop;
else
for i in 0 to ISETS-1 loop
if r.hit = '1' then vmask(i) := r.valid(i) or vmaskraw;
else vmask(i) := vmaskraw; end if;
end loop;
end if;
if (mcio.mexc or not mcio.cache) = '1' then
twrite := '0'; dwrite := '0';
else dwrite := twrite; end if;
if twrite = '1' then
v.valid := vmask; v.hit := '1';
if (ISETS > 1) and (irepl = lru) then vl.write := '1'; end if;
end if;
if (ISETS > 1) and (irepl = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), rl.set);
end if;
-- cache write signals
if ISETS > 1 then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
if twrite = '1' then ctwrite(conv_integer(setrepl)) := '1'; end if;
if dwrite = '1' then cdwrite(conv_integer(setrepl)) := '1'; end if;
-- diagnostic cache access
if diagen = '1' then
if (ISETS /= 1) then
if (dco.icdiag.ilramen = '1') and (lram = 1) then
v.diagset := conv_std_logic_vector(1, SETBITS);
else
v.diagset := dco.icdiag.addr(SETBITS -1 + TAG_LOW downto TAG_LOW);
end if;
end if;
end if;
case ISETS is
when 1 =>
vdiagset := 0; rdiagset := 0;
when 3 =>
if conv_integer(v.diagset) < 3 then vdiagset := conv_integer(v.diagset); end if;
if conv_integer(r.diagset) < 3 then rdiagset := conv_integer(r.diagset); end if;
when others =>
vdiagset := conv_integer(v.diagset);
rdiagset := conv_integer(r.diagset);
end case;
diagdata := icramo.data(rdiagset);
if diagen = '1' then -- diagnostic or local ram access
taddr(TAG_HIGH downto LINE_LOW) := dco.icdiag.addr(TAG_HIGH downto LINE_LOW);
wtag(TAG_HIGH downto TAG_LOW) := dci.maddress(TAG_HIGH downto TAG_LOW);
wlrr := dci.maddress(CTAG_LRRPOS);
wlock := dci.maddress(CTAG_LOCKPOS);
if (dco.icdiag.ilramen = '1') and (lram = 1) then
ilramwr := not dco.icdiag.read;
elsif dco.icdiag.tag = '1' then
twrite := not dco.icdiag.read; dwrite := '0';
ctwrite := (others => '0'); cdwrite := (others => '0');
ctwrite(vdiagset) := not dco.icdiag.read;
diagdata := icramo.tag(rdiagset);
else
dwrite := not dco.icdiag.read; twrite := '0';
cdwrite := (others => '0'); cdwrite(vdiagset) := not dco.icdiag.read;
ctwrite := (others => '0');
end if;
vmask := (others => dci.maddress(ilinesize -1 downto 0));
v.diagrdy := '1';
end if;
-- select data to return on read access
rdata := icramo.data;
case rdatasel is
when memory => rdata(0) := mcio.data; set := 0;
when others =>
end case;
if MUXDATA then
rdata(0) := rdata(set); set := 0;
end if;
-- cache flush
if ((ici.flush or
dco.icdiag.flush) = '1') and (icen /= 0)
then
v.flush := '1'; v.flush2 := '1'; v.faddr := (others => '0');
v.pflush := dco.icdiag.pflush; wtag := (others => '0');
v.pflushr := '1';
v.pflushaddr := dco.icdiag.pflushaddr;
v.pflushtyp := dco.icdiag.pflushtyp;
end if;
if (r.flush2 = '1') and (icen /= 0) then
twrite := '1'; ctwrite := (others => '1'); vmask := (others => (others => '0'));
v.faddr := r.faddr + 1;
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
wlrr := '0'; wlock := '0'; wtag := (others => '0'); v.lrr := '0';
if ((r.faddr(IOFFSET_BITS -1) and not v.faddr(IOFFSET_BITS -1))
) = '1' then
v.flush2 := '0';
end if;
-- precise flush, ASI_FLUSH_PAGE & ASI_FLUSH_CTX
if M_EN then
if r.pflush = '1' then
twrite := '0'; ctwrite := (others => '0');
v.pflushr := not r.pflushr;
if r.pflushr = '0' then
for i in ISETS-1 downto 0 loop
pftag(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
pftag(TAG_HIGH downto TAG_LOW) := icramo.tag(i)(TAG_HIGH downto TAG_LOW); --icramo.itramout(i).tag;
--if (icramo.itramout(i).ctx = mmudci.mmctrl1.ctx) and
-- ((pftag(VA_I_U downto VA_I_D) = r.pflushaddr(VA_I_U downto VA_I_D)) or
-- (r.pflushtyp = '1')) then
ctwrite(i) := '1';
--end if;
end loop;
end if;
end if;
end if;
end if;
-- reset
if (not RESET_ALL) and (rst = '0') then
v.istate := idle; v.req := '0'; v.burst := '0'; v.holdn := '1';
v.flush := '0'; v.flush2 := '0'; v.overrun := '0'; v.underrun := '0';
v.rndcnt := (others => '0'); v.lrr := '0'; v.setrepl := (others => '0');
v.diagset := (others => '0'); v.lock := '0';
v.waddress := ici.fpc(31 downto 2);
v.vaddress := ici.fpc(31 downto 2);
v.trans_op := '0';
v.bpmiss := '0';
end if;
if (not RESET_ALL and rst = '0') or (r.flush = '1') then
vl.lru := (others => (others => '0'));
end if;
-- Drive signals
c <= v; -- register inputs
cl <= vl; -- lru register inputs
-- tag ram inputs
enable := enable;
for i in 0 to ISETS-1 loop
tag(i) := (others => '0');
tag(i)(ilinesize-1 downto 0) := vmask(i);
tag(i)(TAG_HIGH downto TAG_LOW) := wtag;
tag(i)(CTAG_LRRPOS) := wlrr;
tag(i)(CTAG_LOCKPOS) := wlock;
end loop;
icrami.tag <= tag;
icrami.tenable <= enable;
icrami.twrite <= ctwrite;
icrami.flush <= r.flush2;
icrami.ctx <= mmudci.mmctrl1.ctx;
-- data ram inputs
icrami.denable <= enable;
icrami.address <= taddr(19+LINE_LOW downto LINE_LOW);
icrami.data <= ddatain;
icrami.dwrite <= cdwrite;
-- local ram inputs
icrami.ldramin.enable <= (dco.icdiag.ilramen or lramcs or lramacc);
icrami.ldramin.read <= dco.icdiag.ilramen or lramacc;
icrami.ldramin.write <= ilramwr;
-- memory controller inputs
mcii.address(31 downto 2) <= r.waddress(31 downto 2);
mcii.address(1 downto 0) <= "00";
mcii.su <= r.su;
mcii.burst <= r.burst and r.req;
mcii.req <= r.req;
mcii.flush <= r.flush;
-- mmu <-> icache
mmuici.trans_op <= mmuici_trans_op;
mmuici.transdata.data <= r.waddress(31 downto 2) & "00";
mmuici.transdata.su <= r.su;
mmuici.transdata.isid <= id_icache;
mmuici.transdata.read <= '1';
mmuici.transdata.wb_data <= (others => '0');
-- IU data cache inputs
ico.data <= rdata;
ico.mexc <= mcio.mexc or error;
ico.hold <= r.holdn;
ico.mds <= mds;
ico.flush <= r.flush;
ico.diagdata <= diagdata;
ico.diagrdy <= r.diagrdy;
ico.set <= conv_std_logic_vector(set, 2);
ico.cfg <= icfg;
ico.bpmiss <= r.bpmiss;
ico.eocl <= r.eocl;
ico.cstat.chold <= not r.holdn;
ico.cstat.mhold <= mhold;
ico.cstat.tmiss <= mmuico.tlbmiss;
ico.cstat.cmiss <= r.cmiss;
if r.istate = idle then ico.idle <= '1'; else ico.idle <= '0'; end if;
end process;
-- Local registers
regs1 : process(clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
r.waddress <= ici.fpc(31 downto 2);
r.vaddress <= ici.fpc(31 downto 2);
end if;
end if;
end process;
regs2 : if (ISETS > 1) and (irepl = lru) generate
regs2 : process(clk)
begin
if rising_edge(clk) then
rl <= cl;
if RESET_ALL and (rst = '0') then
rl <= LRES;
end if;
end if;
end process;
end generate;
nolru : if (ISETS = 1) or (irepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((ISETS > 2) and (irepl = lrr)) report
"Wrong instruction cache configuration detected: LRR replacement requires 2 sets"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00514
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 5.2 (2)
-- 5.2.1 (1)
-- 5.2.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00514(ARCH00514)
-- ENT00514_Test_Bench(ARCH00514_Test_Bench)
--
-- REVISION HISTORY:
--
-- 11-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00514 is
generic ( G : boolean ) ;
port ( P : in boolean ;
Q : out boolean := G) ;
end ENT00514 ;
architecture ARCH00514 of ENT00514 is
begin
process ( P )
variable First_Time : boolean := true ;
begin
if First_Time then
First_Time := false ;
else
Q <= transport Not P after 10 ns ;
end if ;
end process ;
end ARCH00514 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00514_Test_Bench is
function To_Bit ( p : boolean ) return bit is
begin
case p is
when false => return '0' ;
when true => return '1' ;
end case ;
end To_Bit ;
function To_Boolean ( p : bit ) return boolean is
begin
case p is
when '0' => return false ;
when '1' => return true ;
end case ;
end To_Boolean ;
end ENT00514_Test_Bench ;
architecture ARCH00514_Test_Bench of ENT00514_Test_Bench is
begin
L1:
block
component UUT generic ( G : boolean ) ;
port ( P : in boolean ;
Q : out boolean ) ;
end component ;
signal S : bit_vector ( 1 to 5 )
:= (2|4 => To_Bit(True), others => To_Bit(False)) ;
alias S1 : bit is S(1) ;
alias S2 : bit is S(2) ;
alias S3 : bit is S(3) ;
alias S4 : bit is S(4) ;
alias S5 : bit is S(5) ;
for CIS2 : UUT use entity WORK.ENT00514 ( ARCH00514 ) ;
for others : UUT use entity WORK.ENT00514 ( ARCH00514 ) ;
begin
S(1) <= transport To_Bit (True) after 0 ns ;
CIS1 : UUT generic map(true)
port map (p => To_Boolean (s1),
To_Bit (q) => s2) ;
CIS2 : UUT generic map(false)
port map (p => To_Boolean (s2),
To_Bit (q) => s3) ;
CIS3 : UUT generic map(true)
port map (p => To_Boolean (s3),
To_Bit (q) => s4) ;
CIS4 : UUT generic map(false)
port map (p => To_Boolean (s4),
To_Bit (q) => s5) ;
Check_It :
process
begin
wait for 100 ns ;
test_report ( "ARCH00514" ,
"Others applies to each instance not previously "&
"in an instantiation list of a configuration spec" ,
To_Boolean (s1 and (Not s2) and
s3 and (Not s4) and s5
)
) ;
wait ;
end process Check_It ;
end block L1 ;
end ARCH00514_Test_Bench ;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_96x512_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_96x512_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(96-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(96-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_96x512_top_wrapper;
architecture xilinx of fifo_96x512_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_96x512_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(96-1 DOWNTO 0);
DOUT : OUT std_logic_vector(96-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_96x512_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : integer := 0;
begin -- process
x := 1 + 2;
assert x = 3 report "TEST FAILED - x does not equal 1" severity failure;
assert x /= 3 report "TEST PASSED" severity NOTE;
wait;
end process;
end only;
|
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : integer := 0;
begin -- process
x := 1 + 2;
assert x = 3 report "TEST FAILED - x does not equal 1" severity failure;
assert x /= 3 report "TEST PASSED" severity NOTE;
wait;
end process;
end only;
|
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : integer := 0;
begin -- process
x := 1 + 2;
assert x = 3 report "TEST FAILED - x does not equal 1" severity failure;
assert x /= 3 report "TEST PASSED" severity NOTE;
wait;
end process;
end only;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1728.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s03b00x00p02n01i01728ent IS
END c09s03b00x00p02n01i01728ent;
ARCHITECTURE c09s03b00x00p02n01i01728arch OF c09s03b00x00p02n01i01728ent IS
procedure check (x: in integer; y: in boolean) is
begin
assert NOT( x=3 and y=true )
report "***PASSED TEST: c09s03b00x00p02n01i01728"
severity NOTE;
assert ( x=3 and y=true )
report "***FAILED TEST: c09s03b00x00p02n01i01728 - Procedure call statement syntax diagram did not pass."
severity ERROR;
end;
signal p: integer := 3;
signal q: boolean := true;
BEGIN
check (p,q); -- No_failure_here
END c09s03b00x00p02n01i01728arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1728.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s03b00x00p02n01i01728ent IS
END c09s03b00x00p02n01i01728ent;
ARCHITECTURE c09s03b00x00p02n01i01728arch OF c09s03b00x00p02n01i01728ent IS
procedure check (x: in integer; y: in boolean) is
begin
assert NOT( x=3 and y=true )
report "***PASSED TEST: c09s03b00x00p02n01i01728"
severity NOTE;
assert ( x=3 and y=true )
report "***FAILED TEST: c09s03b00x00p02n01i01728 - Procedure call statement syntax diagram did not pass."
severity ERROR;
end;
signal p: integer := 3;
signal q: boolean := true;
BEGIN
check (p,q); -- No_failure_here
END c09s03b00x00p02n01i01728arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1728.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s03b00x00p02n01i01728ent IS
END c09s03b00x00p02n01i01728ent;
ARCHITECTURE c09s03b00x00p02n01i01728arch OF c09s03b00x00p02n01i01728ent IS
procedure check (x: in integer; y: in boolean) is
begin
assert NOT( x=3 and y=true )
report "***PASSED TEST: c09s03b00x00p02n01i01728"
severity NOTE;
assert ( x=3 and y=true )
report "***FAILED TEST: c09s03b00x00p02n01i01728 - Procedure call statement syntax diagram did not pass."
severity ERROR;
end;
signal p: integer := 3;
signal q: boolean := true;
BEGIN
check (p,q); -- No_failure_here
END c09s03b00x00p02n01i01728arch;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:14:26 10/18/2014
-- Design Name:
-- Module Name: D:/Documents/Xilinx Projects/multi_cycle_cpu/src/MIPS_ALU_ctrl_tb.vhd
-- Project Name: multi_cycle_cpu
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MIPS_ALU_ctrl
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY MIPS_ALU_ctrl_tb IS
END MIPS_ALU_ctrl_tb;
ARCHITECTURE behavior OF MIPS_ALU_ctrl_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MIPS_ALU_ctrl
PORT(
funct_code : IN std_logic_vector(5 downto 0);
ALU_op : IN std_logic_vector(1 downto 0);
ALU_ctrl : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal funct_code : std_logic_vector(5 downto 0) := (others => '0');
signal ALU_op : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal ALU_ctrl : std_logic_vector(3 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
signal clock : std_logic;
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MIPS_ALU_ctrl PORT MAP (
funct_code => funct_code,
ALU_op => ALU_op,
ALU_ctrl => ALU_ctrl
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clock_period*10;
-- insert stimulus here
--LW/SW
ALU_op <= "00";
wait for 10 ns;
assert ALU_ctrl = "0010" report "ALU_op 00 failed" severity error;
-- BEQ
ALU_op <= "01";
wait for 10 ns;
assert ALU_ctrl = "0110" report "ALU_op 01 failed" severity error;
--R TYPE
ALU_op <= "10";
funct_code <= "000000";
wait for 10 ns;
assert ALU_ctrl = "0010" report "ALU_op 10 failed" severity error;
-- R TYPE with don't care bits COVERAGE test FOR ADD
ALU_op <= "10";
funct_code <= "010000";
wait for 10 ns;
assert ALU_ctrl = "0010" report "ALU_op 10 failed" severity error;
funct_code <= "110000";
wait for 10 ns;
assert ALU_ctrl = "0010" report "ALU_op 10 failed" severity error;
funct_code <= "100000";
wait for 10 ns;
assert ALU_ctrl = "0010" report "ALU_op 10 failed" severity error;
-- R TYPE with don't care bits COVERAGE test FOR SUB
ALU_op <= "10";
funct_code <= "010010";
wait for 10 ns;
assert ALU_ctrl = "0110" report "ALU_ctrl = 0110 failed" severity error;
funct_code <= "110010";
wait for 10 ns;
assert ALU_ctrl = "0110" report "ALU_ctrl = 0110 failed" severity error;
funct_code <= "100010";
wait for 10 ns;
assert ALU_ctrl = "0110" report "ALU_ctrl = 0110 failed" severity error;
-- and
funct_code <= "100100";
wait for 10 ns;
assert ALU_ctrl = "0000" report "ALU_ctrl = 0110 failed" severity error;
-- or
funct_code <= "100101";
wait for 10 ns;
assert ALU_ctrl = "0001" report "ALU_ctrl = 0110 failed" severity error;
-- slt
funct_code <= "101010";
wait for 10 ns;
assert ALU_ctrl = "0111" report "ALU_ctrl = 0110 failed" severity error;
wait;
end process;
END;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ebb_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ebb_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:26 wig Exp $
-- $Date: 2004/04/06 10:50:26 $
-- $Log: inst_ebb_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:26 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ebb_e
--
architecture rtl of inst_ebb_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, type, subtype, case, enumerations, array, for-loop, function, Attributes-of-the-array-type-or-objects-of-the-array-type
use work.std_logic_1164_for_tst.all;
entity ENT00024_Test_Bench is
end ENT00024_Test_Bench;
architecture ARCH00024_Test_Bench of ENT00024_Test_Bench is
subtype byte is bit_vector(0 to 7);
type IntArray is array (integer range <>) of integer;
type ArrayOfIntArray is array (1 to 5) of IntArray(1 to 6);
type ArrayOfIntArray_ForRange is array (1 to 6) of IntArray(-3 to 20);
type ArrayOfArrayOfIntArray_ForRange is array (1 to 12) of ArrayOfIntArray_ForRange;
type ArrayOfArrayOfIntArray is array (1 to 12) of ArrayOfIntArray;
type std_array is array (0 to 3) of std_logic;
signal I_sa : std_array := "1010";
type enum is (a_v, b_v, c_v, d_v, e_v, f_v);
type rec is record
f1 : integer;
f2 : boolean;
f3 : bit;
end record;
type BooleanVector is array (integer range <>) of boolean;
type cond_type is array (1 to 12) of BooleanVector(1 to 8);
type ArrayOfBooleanVector is array (1 to 12) of BooleanVector(1 to 6);
type StateType is (init, assign, analize, waiting);
signal state : StateType := init;
type std_logic_array_dem_5 is array (integer range <>, integer range <>, integer range <>, integer range <>, integer range <>) of std_logic;
type bit_array_dem_5 is array (integer range <>, integer range <>, integer range <>, integer range <>, integer range <>) of bit;
type integer_array_dem_5 is array (integer range <>, integer range <>, integer range <>, integer range <>, integer range <>) of integer;
type boolean_array_dem_5 is array (integer range <>, integer range <>, integer range <>, integer range <>, integer range <>) of boolean;
type enum_array_dem_5 is array (integer range <>, integer range <>, integer range <>, integer range <>, integer range <>) of enum;
type rec_array_dem_5 is array (integer range <>, integer range <>, integer range <>, integer range <>, integer range <>) of rec;
subtype std_logic_array_dem_5_sub is std_logic_array_dem_5(1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
type bit_array_dem_5_boarded is array (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3) of bit;
subtype integer_array_dem_5_sub is integer_array_dem_5 (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
subtype boolean_array_dem_5_sub is boolean_array_dem_5 (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
type enum_array_dem_5_boarded is array (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3) of enum;
subtype rec_array_dem_5_sub is rec_array_dem_5 (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
signal stdl_a_d5 : std_logic_array_dem_5(1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
signal bit_a_d5 : bit_array_dem_5 (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
signal int_a_d5 : integer_array_dem_5 (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
signal bool_a_d5 : boolean_array_dem_5 (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
signal enum_a_d5 : enum_array_dem_5 (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
signal rec_a_d5 : rec_array_dem_5 (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
function all100 (i : IntArray) return boolean is
variable v : IntArray(i'range);
variable r : boolean;
begin
v := i;
r := true;
l1: for i in v'range loop
r := r and (v(i) = 100);
end loop;
return r;
end function;
begin
process (state)
variable vv : ArrayOfArrayOfIntArray_ForRange := (others => (others => (others => 100)));
variable vv_reverse : ArrayOfArrayOfIntArray_ForRange := (others => (others => (others => 100)));
variable int : ArrayOfArrayOfIntArray := (others => (others => (others => 0)));
variable bool : ArrayOfBooleanVector := (others => (others => false));
variable cond : cond_type := (others => (others => false));
begin
case state is
when init =>
state <= assign;
when assign =>
state <= analize;
-- std_logic_array
int(1)(1)(1) := stdl_a_d5'Low;
int(1)(1)(2) := stdl_a_d5'Low(1);
int(1)(1)(3) := stdl_a_d5'Low(2);
int(1)(1)(4) := stdl_a_d5'Low(3);
int(1)(1)(5) := stdl_a_d5'Low(4);
int(1)(1)(6) := stdl_a_d5'Low(5);
int(1)(2)(1) := stdl_a_d5'High;
int(1)(2)(2) := stdl_a_d5'High(1);
int(1)(2)(3) := stdl_a_d5'High(2);
int(1)(2)(4) := stdl_a_d5'High(3);
int(1)(2)(5) := stdl_a_d5'High(4);
int(1)(2)(6) := stdl_a_d5'High(5);
int(1)(3)(1) := stdl_a_d5'Left;
int(1)(3)(2) := stdl_a_d5'Left(1);
int(1)(3)(3) := stdl_a_d5'Left(2);
int(1)(3)(4) := stdl_a_d5'Left(3);
int(1)(3)(5) := stdl_a_d5'Left(4);
int(1)(3)(6) := stdl_a_d5'Left(5);
int(1)(4)(1) := stdl_a_d5'Right;
int(1)(4)(2) := stdl_a_d5'Right(1);
int(1)(4)(3) := stdl_a_d5'Right(2);
int(1)(4)(4) := stdl_a_d5'Right(3);
int(1)(4)(5) := stdl_a_d5'Right(4);
int(1)(4)(6) := stdl_a_d5'Right(5);
int(1)(5)(1) := stdl_a_d5'Length;
int(1)(5)(2) := stdl_a_d5'Length(1);
int(1)(5)(3) := stdl_a_d5'Length(2);
int(1)(5)(4) := stdl_a_d5'Length(3);
int(1)(5)(5) := stdl_a_d5'Length(4);
int(1)(5)(6) := stdl_a_d5'Length(5);
int(2)(1)(1) := std_logic_array_dem_5_sub'Low;
int(2)(1)(2) := std_logic_array_dem_5_sub'Low(1);
int(2)(1)(3) := std_logic_array_dem_5_sub'Low(2);
int(2)(1)(4) := std_logic_array_dem_5_sub'Low(3);
int(2)(1)(5) := std_logic_array_dem_5_sub'Low(4);
int(2)(1)(6) := std_logic_array_dem_5_sub'Low(5);
int(2)(2)(1) := std_logic_array_dem_5_sub'High;
int(2)(2)(2) := std_logic_array_dem_5_sub'High(1);
int(2)(2)(3) := std_logic_array_dem_5_sub'High(2);
int(2)(2)(4) := std_logic_array_dem_5_sub'High(3);
int(2)(2)(5) := std_logic_array_dem_5_sub'High(4);
int(2)(2)(6) := std_logic_array_dem_5_sub'High(5);
int(2)(3)(1) := std_logic_array_dem_5_sub'Left;
int(2)(3)(2) := std_logic_array_dem_5_sub'Left(1);
int(2)(3)(3) := std_logic_array_dem_5_sub'Left(2);
int(2)(3)(4) := std_logic_array_dem_5_sub'Left(3);
int(2)(3)(5) := std_logic_array_dem_5_sub'Left(4);
int(2)(3)(6) := std_logic_array_dem_5_sub'Left(5);
int(2)(4)(1) := std_logic_array_dem_5_sub'Right;
int(2)(4)(2) := std_logic_array_dem_5_sub'Right(1);
int(2)(4)(3) := std_logic_array_dem_5_sub'Right(2);
int(2)(4)(4) := std_logic_array_dem_5_sub'Right(3);
int(2)(4)(5) := std_logic_array_dem_5_sub'Right(4);
int(2)(4)(6) := std_logic_array_dem_5_sub'Right(5);
int(2)(5)(1) := std_logic_array_dem_5_sub'Length;
int(2)(5)(2) := std_logic_array_dem_5_sub'Length(1);
int(2)(5)(3) := std_logic_array_dem_5_sub'Length(2);
int(2)(5)(4) := std_logic_array_dem_5_sub'Length(3);
int(2)(5)(5) := std_logic_array_dem_5_sub'Length(4);
int(2)(5)(6) := std_logic_array_dem_5_sub'Length(5);
bool(1)(1) := stdl_a_d5'Ascending;
bool(1)(2) := stdl_a_d5'Ascending(1);
bool(1)(3) := stdl_a_d5'Ascending(2);
bool(1)(4) := stdl_a_d5'Ascending(3);
bool(1)(5) := stdl_a_d5'Ascending(4);
bool(1)(6) := stdl_a_d5'Ascending(5);
bool(2)(1) := std_logic_array_dem_5_sub'Ascending;
bool(2)(2) := std_logic_array_dem_5_sub'Ascending(1);
bool(2)(3) := std_logic_array_dem_5_sub'Ascending(2);
bool(2)(4) := std_logic_array_dem_5_sub'Ascending(3);
bool(2)(5) := std_logic_array_dem_5_sub'Ascending(4);
bool(2)(6) := std_logic_array_dem_5_sub'Ascending(5);
-- bit_array
int(3)(1)(1) := bit_a_d5'Low;
int(3)(1)(2) := bit_a_d5'Low(1);
int(3)(1)(3) := bit_a_d5'Low(2);
int(3)(1)(4) := bit_a_d5'Low(3);
int(3)(1)(5) := bit_a_d5'Low(4);
int(3)(1)(6) := bit_a_d5'Low(5);
int(3)(2)(1) := bit_a_d5'High;
int(3)(2)(2) := bit_a_d5'High(1);
int(3)(2)(3) := bit_a_d5'High(2);
int(3)(2)(4) := bit_a_d5'High(3);
int(3)(2)(5) := bit_a_d5'High(4);
int(3)(2)(6) := bit_a_d5'High(5);
int(3)(3)(1) := bit_a_d5'Left;
int(3)(3)(2) := bit_a_d5'Left(1);
int(3)(3)(3) := bit_a_d5'Left(2);
int(3)(3)(4) := bit_a_d5'Left(3);
int(3)(3)(5) := bit_a_d5'Left(4);
int(3)(3)(6) := bit_a_d5'Left(5);
int(3)(4)(1) := bit_a_d5'Right;
int(3)(4)(2) := bit_a_d5'Right(1);
int(3)(4)(3) := bit_a_d5'Right(2);
int(3)(4)(4) := bit_a_d5'Right(3);
int(3)(4)(5) := bit_a_d5'Right(4);
int(3)(4)(6) := bit_a_d5'Right(5);
int(3)(5)(1) := bit_a_d5'Length;
int(3)(5)(2) := bit_a_d5'Length(1);
int(3)(5)(3) := bit_a_d5'Length(2);
int(3)(5)(4) := bit_a_d5'Length(3);
int(3)(5)(5) := bit_a_d5'Length(4);
int(3)(5)(6) := bit_a_d5'Length(5);
int(4)(1)(1) := bit_array_dem_5_boarded'Low;
int(4)(1)(2) := bit_array_dem_5_boarded'Low(1);
int(4)(1)(3) := bit_array_dem_5_boarded'Low(2);
int(4)(1)(4) := bit_array_dem_5_boarded'Low(3);
int(4)(1)(5) := bit_array_dem_5_boarded'Low(4);
int(4)(1)(6) := bit_array_dem_5_boarded'Low(5);
int(4)(2)(1) := bit_array_dem_5_boarded'High;
int(4)(2)(2) := bit_array_dem_5_boarded'High(1);
int(4)(2)(3) := bit_array_dem_5_boarded'High(2);
int(4)(2)(4) := bit_array_dem_5_boarded'High(3);
int(4)(2)(5) := bit_array_dem_5_boarded'High(4);
int(4)(2)(6) := bit_array_dem_5_boarded'High(5);
int(4)(3)(1) := bit_array_dem_5_boarded'Left;
int(4)(3)(2) := bit_array_dem_5_boarded'Left(1);
int(4)(3)(3) := bit_array_dem_5_boarded'Left(2);
int(4)(3)(4) := bit_array_dem_5_boarded'Left(3);
int(4)(3)(5) := bit_array_dem_5_boarded'Left(4);
int(4)(3)(6) := bit_array_dem_5_boarded'Left(5);
int(4)(4)(1) := bit_array_dem_5_boarded'Right;
int(4)(4)(2) := bit_array_dem_5_boarded'Right(1);
int(4)(4)(3) := bit_array_dem_5_boarded'Right(2);
int(4)(4)(4) := bit_array_dem_5_boarded'Right(3);
int(4)(4)(5) := bit_array_dem_5_boarded'Right(4);
int(4)(4)(6) := bit_array_dem_5_boarded'Right(5);
int(4)(5)(1) := bit_array_dem_5_boarded'Length;
int(4)(5)(2) := bit_array_dem_5_boarded'Length(1);
int(4)(5)(3) := bit_array_dem_5_boarded'Length(2);
int(4)(5)(4) := bit_array_dem_5_boarded'Length(3);
int(4)(5)(5) := bit_array_dem_5_boarded'Length(4);
int(4)(5)(6) := bit_array_dem_5_boarded'Length(5);
bool(3)(1) := bit_a_d5'Ascending;
bool(3)(2) := bit_a_d5'Ascending(1);
bool(3)(3) := bit_a_d5'Ascending(2);
bool(3)(4) := bit_a_d5'Ascending(3);
bool(3)(5) := bit_a_d5'Ascending(4);
bool(3)(6) := bit_a_d5'Ascending(5);
bool(4)(1) := bit_array_dem_5_boarded'Ascending;
bool(4)(2) := bit_array_dem_5_boarded'Ascending(1);
bool(4)(3) := bit_array_dem_5_boarded'Ascending(2);
bool(4)(4) := bit_array_dem_5_boarded'Ascending(3);
bool(4)(5) := bit_array_dem_5_boarded'Ascending(4);
bool(4)(6) := bit_array_dem_5_boarded'Ascending(5);
-- integer_array
int(5)(1)(1) := int_a_d5'Low;
int(5)(1)(2) := int_a_d5'Low(1);
int(5)(1)(3) := int_a_d5'Low(2);
int(5)(1)(4) := int_a_d5'Low(3);
int(5)(1)(5) := int_a_d5'Low(4);
int(5)(1)(6) := int_a_d5'Low(5);
int(5)(2)(1) := int_a_d5'High;
int(5)(2)(2) := int_a_d5'High(1);
int(5)(2)(3) := int_a_d5'High(2);
int(5)(2)(4) := int_a_d5'High(3);
int(5)(2)(5) := int_a_d5'High(4);
int(5)(2)(6) := int_a_d5'High(5);
int(5)(3)(1) := int_a_d5'Left;
int(5)(3)(2) := int_a_d5'Left(1);
int(5)(3)(3) := int_a_d5'Left(2);
int(5)(3)(4) := int_a_d5'Left(3);
int(5)(3)(5) := int_a_d5'Left(4);
int(5)(3)(6) := int_a_d5'Left(5);
int(5)(4)(1) := int_a_d5'Right;
int(5)(4)(2) := int_a_d5'Right(1);
int(5)(4)(3) := int_a_d5'Right(2);
int(5)(4)(4) := int_a_d5'Right(3);
int(5)(4)(5) := int_a_d5'Right(4);
int(5)(4)(6) := int_a_d5'Right(5);
int(5)(5)(1) := int_a_d5'Length;
int(5)(5)(2) := int_a_d5'Length(1);
int(5)(5)(3) := int_a_d5'Length(2);
int(5)(5)(4) := int_a_d5'Length(3);
int(5)(5)(5) := int_a_d5'Length(4);
int(5)(5)(6) := int_a_d5'Length(5);
int(6)(1)(1) := integer_array_dem_5_sub'Low;
int(6)(1)(2) := integer_array_dem_5_sub'Low(1);
int(6)(1)(3) := integer_array_dem_5_sub'Low(2);
int(6)(1)(4) := integer_array_dem_5_sub'Low(3);
int(6)(1)(5) := integer_array_dem_5_sub'Low(4);
int(6)(1)(6) := integer_array_dem_5_sub'Low(5);
int(6)(2)(1) := integer_array_dem_5_sub'High;
int(6)(2)(2) := integer_array_dem_5_sub'High(1);
int(6)(2)(3) := integer_array_dem_5_sub'High(2);
int(6)(2)(4) := integer_array_dem_5_sub'High(3);
int(6)(2)(5) := integer_array_dem_5_sub'High(4);
int(6)(2)(6) := integer_array_dem_5_sub'High(5);
int(6)(3)(1) := integer_array_dem_5_sub'Left;
int(6)(3)(2) := integer_array_dem_5_sub'Left(1);
int(6)(3)(3) := integer_array_dem_5_sub'Left(2);
int(6)(3)(4) := integer_array_dem_5_sub'Left(3);
int(6)(3)(5) := integer_array_dem_5_sub'Left(4);
int(6)(3)(6) := integer_array_dem_5_sub'Left(5);
int(6)(4)(1) := integer_array_dem_5_sub'Right;
int(6)(4)(2) := integer_array_dem_5_sub'Right(1);
int(6)(4)(3) := integer_array_dem_5_sub'Right(2);
int(6)(4)(4) := integer_array_dem_5_sub'Right(3);
int(6)(4)(5) := integer_array_dem_5_sub'Right(4);
int(6)(4)(6) := integer_array_dem_5_sub'Right(5);
int(6)(5)(1) := integer_array_dem_5_sub'Length;
int(6)(5)(2) := integer_array_dem_5_sub'Length(1);
int(6)(5)(3) := integer_array_dem_5_sub'Length(2);
int(6)(5)(4) := integer_array_dem_5_sub'Length(3);
int(6)(5)(5) := integer_array_dem_5_sub'Length(4);
int(6)(5)(6) := integer_array_dem_5_sub'Length(5);
bool(5)(1) := int_a_d5'Ascending;
bool(5)(2) := int_a_d5'Ascending(1);
bool(5)(3) := int_a_d5'Ascending(2);
bool(5)(4) := int_a_d5'Ascending(3);
bool(5)(5) := int_a_d5'Ascending(4);
bool(5)(6) := int_a_d5'Ascending(5);
bool(6)(1) := integer_array_dem_5_sub'Ascending;
bool(6)(2) := integer_array_dem_5_sub'Ascending(1);
bool(6)(3) := integer_array_dem_5_sub'Ascending(2);
bool(6)(4) := integer_array_dem_5_sub'Ascending(3);
bool(6)(5) := integer_array_dem_5_sub'Ascending(4);
bool(6)(6) := integer_array_dem_5_sub'Ascending(5);
-- boolean_array
int(7)(1)(1) := bool_a_d5'Low;
int(7)(1)(2) := bool_a_d5'Low(1);
int(7)(1)(3) := bool_a_d5'Low(2);
int(7)(1)(4) := bool_a_d5'Low(3);
int(7)(1)(5) := bool_a_d5'Low(4);
int(7)(1)(6) := bool_a_d5'Low(5);
int(7)(2)(1) := bool_a_d5'High;
int(7)(2)(2) := bool_a_d5'High(1);
int(7)(2)(3) := bool_a_d5'High(2);
int(7)(2)(4) := bool_a_d5'High(3);
int(7)(2)(5) := bool_a_d5'High(4);
int(7)(2)(6) := bool_a_d5'High(5);
int(7)(3)(1) := bool_a_d5'Left;
int(7)(3)(2) := bool_a_d5'Left(1);
int(7)(3)(3) := bool_a_d5'Left(2);
int(7)(3)(4) := bool_a_d5'Left(3);
int(7)(3)(5) := bool_a_d5'Left(4);
int(7)(3)(6) := bool_a_d5'Left(5);
int(7)(4)(1) := bool_a_d5'Right;
int(7)(4)(2) := bool_a_d5'Right(1);
int(7)(4)(3) := bool_a_d5'Right(2);
int(7)(4)(4) := bool_a_d5'Right(3);
int(7)(4)(5) := bool_a_d5'Right(4);
int(7)(4)(6) := bool_a_d5'Right(5);
int(7)(5)(1) := bool_a_d5'Length;
int(7)(5)(2) := bool_a_d5'Length(1);
int(7)(5)(3) := bool_a_d5'Length(2);
int(7)(5)(4) := bool_a_d5'Length(3);
int(7)(5)(5) := bool_a_d5'Length(4);
int(7)(5)(6) := bool_a_d5'Length(5);
int(8)(1)(1) := boolean_array_dem_5_sub'Low;
int(8)(1)(2) := boolean_array_dem_5_sub'Low(1);
int(8)(1)(3) := boolean_array_dem_5_sub'Low(2);
int(8)(1)(4) := boolean_array_dem_5_sub'Low(3);
int(8)(1)(5) := boolean_array_dem_5_sub'Low(4);
int(8)(1)(6) := boolean_array_dem_5_sub'Low(5);
int(8)(2)(1) := boolean_array_dem_5_sub'High;
int(8)(2)(2) := boolean_array_dem_5_sub'High(1);
int(8)(2)(3) := boolean_array_dem_5_sub'High(2);
int(8)(2)(4) := boolean_array_dem_5_sub'High(3);
int(8)(2)(5) := boolean_array_dem_5_sub'High(4);
int(8)(2)(6) := boolean_array_dem_5_sub'High(5);
int(8)(3)(1) := boolean_array_dem_5_sub'Left;
int(8)(3)(2) := boolean_array_dem_5_sub'Left(1);
int(8)(3)(3) := boolean_array_dem_5_sub'Left(2);
int(8)(3)(4) := boolean_array_dem_5_sub'Left(3);
int(8)(3)(5) := boolean_array_dem_5_sub'Left(4);
int(8)(3)(6) := boolean_array_dem_5_sub'Left(5);
int(8)(4)(1) := boolean_array_dem_5_sub'Right;
int(8)(4)(2) := boolean_array_dem_5_sub'Right(1);
int(8)(4)(3) := boolean_array_dem_5_sub'Right(2);
int(8)(4)(4) := boolean_array_dem_5_sub'Right(3);
int(8)(4)(5) := boolean_array_dem_5_sub'Right(4);
int(8)(4)(6) := boolean_array_dem_5_sub'Right(5);
int(8)(5)(1) := boolean_array_dem_5_sub'Length;
int(8)(5)(2) := boolean_array_dem_5_sub'Length(1);
int(8)(5)(3) := boolean_array_dem_5_sub'Length(2);
int(8)(5)(4) := boolean_array_dem_5_sub'Length(3);
int(8)(5)(5) := boolean_array_dem_5_sub'Length(4);
int(8)(5)(6) := boolean_array_dem_5_sub'Length(5);
bool(7)(1) := bool_a_d5'Ascending;
bool(7)(2) := bool_a_d5'Ascending(1);
bool(7)(3) := bool_a_d5'Ascending(2);
bool(7)(4) := bool_a_d5'Ascending(3);
bool(7)(5) := bool_a_d5'Ascending(4);
bool(7)(6) := bool_a_d5'Ascending(5);
bool(8)(1) := boolean_array_dem_5_sub'Ascending;
bool(8)(2) := boolean_array_dem_5_sub'Ascending(1);
bool(8)(3) := boolean_array_dem_5_sub'Ascending(2);
bool(8)(4) := boolean_array_dem_5_sub'Ascending(3);
bool(8)(5) := boolean_array_dem_5_sub'Ascending(4);
bool(8)(6) := boolean_array_dem_5_sub'Ascending(5);
-- enum_array
int(9)(1)(1) := enum_a_d5'Low;
int(9)(1)(2) := enum_a_d5'Low(1);
int(9)(1)(3) := enum_a_d5'Low(2);
int(9)(1)(4) := enum_a_d5'Low(3);
int(9)(1)(5) := enum_a_d5'Low(4);
int(9)(1)(6) := enum_a_d5'Low(5);
int(9)(2)(1) := enum_a_d5'High;
int(9)(2)(2) := enum_a_d5'High(1);
int(9)(2)(3) := enum_a_d5'High(2);
int(9)(2)(4) := enum_a_d5'High(3);
int(9)(2)(5) := enum_a_d5'High(4);
int(9)(2)(6) := enum_a_d5'High(5);
int(9)(3)(1) := enum_a_d5'Left;
int(9)(3)(2) := enum_a_d5'Left(1);
int(9)(3)(3) := enum_a_d5'Left(2);
int(9)(3)(4) := enum_a_d5'Left(3);
int(9)(3)(5) := enum_a_d5'Left(4);
int(9)(3)(6) := enum_a_d5'Left(5);
int(9)(4)(1) := enum_a_d5'Right;
int(9)(4)(2) := enum_a_d5'Right(1);
int(9)(4)(3) := enum_a_d5'Right(2);
int(9)(4)(4) := enum_a_d5'Right(3);
int(9)(4)(5) := enum_a_d5'Right(4);
int(9)(4)(6) := enum_a_d5'Right(5);
int(9)(5)(1) := enum_a_d5'Length;
int(9)(5)(2) := enum_a_d5'Length(1);
int(9)(5)(3) := enum_a_d5'Length(2);
int(9)(5)(4) := enum_a_d5'Length(3);
int(9)(5)(5) := enum_a_d5'Length(4);
int(9)(5)(6) := enum_a_d5'Length(5);
int(10)(1)(1) := enum_array_dem_5_boarded'Low;
int(10)(1)(2) := enum_array_dem_5_boarded'Low(1);
int(10)(1)(3) := enum_array_dem_5_boarded'Low(2);
int(10)(1)(4) := enum_array_dem_5_boarded'Low(3);
int(10)(1)(5) := enum_array_dem_5_boarded'Low(4);
int(10)(1)(6) := enum_array_dem_5_boarded'Low(5);
int(10)(2)(1) := enum_array_dem_5_boarded'High;
int(10)(2)(2) := enum_array_dem_5_boarded'High(1);
int(10)(2)(3) := enum_array_dem_5_boarded'High(2);
int(10)(2)(4) := enum_array_dem_5_boarded'High(3);
int(10)(2)(5) := enum_array_dem_5_boarded'High(4);
int(10)(2)(6) := enum_array_dem_5_boarded'High(5);
int(10)(3)(1) := enum_array_dem_5_boarded'Left;
int(10)(3)(2) := enum_array_dem_5_boarded'Left(1);
int(10)(3)(3) := enum_array_dem_5_boarded'Left(2);
int(10)(3)(4) := enum_array_dem_5_boarded'Left(3);
int(10)(3)(5) := enum_array_dem_5_boarded'Left(4);
int(10)(3)(6) := enum_array_dem_5_boarded'Left(5);
int(10)(4)(1) := enum_array_dem_5_boarded'Right;
int(10)(4)(2) := enum_array_dem_5_boarded'Right(1);
int(10)(4)(3) := enum_array_dem_5_boarded'Right(2);
int(10)(4)(4) := enum_array_dem_5_boarded'Right(3);
int(10)(4)(5) := enum_array_dem_5_boarded'Right(4);
int(10)(4)(6) := enum_array_dem_5_boarded'Right(5);
int(10)(5)(1) := enum_array_dem_5_boarded'Length;
int(10)(5)(2) := enum_array_dem_5_boarded'Length(1);
int(10)(5)(3) := enum_array_dem_5_boarded'Length(2);
int(10)(5)(4) := enum_array_dem_5_boarded'Length(3);
int(10)(5)(5) := enum_array_dem_5_boarded'Length(4);
int(10)(5)(6) := enum_array_dem_5_boarded'Length(5);
bool(9)(1) := enum_a_d5'Ascending;
bool(9)(2) := enum_a_d5'Ascending(1);
bool(9)(3) := enum_a_d5'Ascending(2);
bool(9)(4) := enum_a_d5'Ascending(3);
bool(9)(5) := enum_a_d5'Ascending(4);
bool(9)(6) := enum_a_d5'Ascending(5);
bool(10)(1) := enum_array_dem_5_boarded'Ascending;
bool(10)(2) := enum_array_dem_5_boarded'Ascending(1);
bool(10)(3) := enum_array_dem_5_boarded'Ascending(2);
bool(10)(4) := enum_array_dem_5_boarded'Ascending(3);
bool(10)(5) := enum_array_dem_5_boarded'Ascending(4);
bool(10)(6) := enum_array_dem_5_boarded'Ascending(5);
-- rec_array
int(11)(1)(1) := rec_a_d5'Low;
int(11)(1)(2) := rec_a_d5'Low(1);
int(11)(1)(3) := rec_a_d5'Low(2);
int(11)(1)(4) := rec_a_d5'Low(3);
int(11)(1)(5) := rec_a_d5'Low(4);
int(11)(1)(6) := rec_a_d5'Low(5);
int(11)(2)(1) := rec_a_d5'High;
int(11)(2)(2) := rec_a_d5'High(1);
int(11)(2)(3) := rec_a_d5'High(2);
int(11)(2)(4) := rec_a_d5'High(3);
int(11)(2)(5) := rec_a_d5'High(4);
int(11)(2)(6) := rec_a_d5'High(5);
int(11)(3)(1) := rec_a_d5'Left;
int(11)(3)(2) := rec_a_d5'Left(1);
int(11)(3)(3) := rec_a_d5'Left(2);
int(11)(3)(4) := rec_a_d5'Left(3);
int(11)(3)(5) := rec_a_d5'Left(4);
int(11)(3)(6) := rec_a_d5'Left(5);
int(11)(4)(1) := rec_a_d5'Right;
int(11)(4)(2) := rec_a_d5'Right(1);
int(11)(4)(3) := rec_a_d5'Right(2);
int(11)(4)(4) := rec_a_d5'Right(3);
int(11)(4)(5) := rec_a_d5'Right(4);
int(11)(4)(6) := rec_a_d5'Right(5);
int(11)(5)(1) := rec_a_d5'Length;
int(11)(5)(2) := rec_a_d5'Length(1);
int(11)(5)(3) := rec_a_d5'Length(2);
int(11)(5)(4) := rec_a_d5'Length(3);
int(11)(5)(5) := rec_a_d5'Length(4);
int(11)(5)(6) := rec_a_d5'Length(5);
int(12)(1)(1) := rec_array_dem_5_sub'Low;
int(12)(1)(2) := rec_array_dem_5_sub'Low(1);
int(12)(1)(3) := rec_array_dem_5_sub'Low(2);
int(12)(1)(4) := rec_array_dem_5_sub'Low(3);
int(12)(1)(5) := rec_array_dem_5_sub'Low(4);
int(12)(1)(6) := rec_array_dem_5_sub'Low(5);
int(12)(2)(1) := rec_array_dem_5_sub'High;
int(12)(2)(2) := rec_array_dem_5_sub'High(1);
int(12)(2)(3) := rec_array_dem_5_sub'High(2);
int(12)(2)(4) := rec_array_dem_5_sub'High(3);
int(12)(2)(5) := rec_array_dem_5_sub'High(4);
int(12)(2)(6) := rec_array_dem_5_sub'High(5);
int(12)(3)(1) := rec_array_dem_5_sub'Left;
int(12)(3)(2) := rec_array_dem_5_sub'Left(1);
int(12)(3)(3) := rec_array_dem_5_sub'Left(2);
int(12)(3)(4) := rec_array_dem_5_sub'Left(3);
int(12)(3)(5) := rec_array_dem_5_sub'Left(4);
int(12)(3)(6) := rec_array_dem_5_sub'Left(5);
int(12)(4)(1) := rec_array_dem_5_sub'Right;
int(12)(4)(2) := rec_array_dem_5_sub'Right(1);
int(12)(4)(3) := rec_array_dem_5_sub'Right(2);
int(12)(4)(4) := rec_array_dem_5_sub'Right(3);
int(12)(4)(5) := rec_array_dem_5_sub'Right(4);
int(12)(4)(6) := rec_array_dem_5_sub'Right(5);
int(12)(5)(1) := rec_array_dem_5_sub'Length;
int(12)(5)(2) := rec_array_dem_5_sub'Length(1);
int(12)(5)(3) := rec_array_dem_5_sub'Length(2);
int(12)(5)(4) := rec_array_dem_5_sub'Length(3);
int(12)(5)(5) := rec_array_dem_5_sub'Length(4);
int(12)(5)(6) := rec_array_dem_5_sub'Length(5);
bool(11)(1) := rec_a_d5'Ascending;
bool(11)(2) := rec_a_d5'Ascending(1);
bool(11)(3) := rec_a_d5'Ascending(2);
bool(11)(4) := rec_a_d5'Ascending(3);
bool(11)(5) := rec_a_d5'Ascending(4);
bool(11)(6) := rec_a_d5'Ascending(5);
bool(12)(1) := rec_array_dem_5_sub'Ascending;
bool(12)(2) := rec_array_dem_5_sub'Ascending(1);
bool(12)(3) := rec_array_dem_5_sub'Ascending(2);
bool(12)(4) := rec_array_dem_5_sub'Ascending(3);
bool(12)(5) := rec_array_dem_5_sub'Ascending(4);
bool(12)(6) := rec_array_dem_5_sub'Ascending(5);
-- range
-- std_logic_array
l1_1: for i in stdl_a_d5'range loop vv(1)(1)(i) := i; end loop l1_1;
l1_2: for i in stdl_a_d5'range(1) loop vv(1)(2)(i) := i; end loop l1_2;
l1_3: for i in stdl_a_d5'range(2) loop vv(1)(3)(i) := i; end loop l1_3;
l1_4: for i in stdl_a_d5'range(3) loop vv(1)(4)(i) := i; end loop l1_4;
l1_5: for i in stdl_a_d5'range(4) loop vv(1)(5)(i) := i; end loop l1_5;
l1_6: for i in stdl_a_d5'range(5) loop vv(1)(6)(i) := i; end loop l1_6;
l2_1: for i in std_logic_array_dem_5_sub'range loop vv(2)(1)(i) := i; end loop l2_1;
l2_2: for i in std_logic_array_dem_5_sub'range(1) loop vv(2)(2)(i) := i; end loop l2_2;
l2_3: for i in std_logic_array_dem_5_sub'range(2) loop vv(2)(3)(i) := i; end loop l2_3;
l2_4: for i in std_logic_array_dem_5_sub'range(3) loop vv(2)(4)(i) := i; end loop l2_4;
l2_5: for i in std_logic_array_dem_5_sub'range(4) loop vv(2)(5)(i) := i; end loop l2_5;
l2_6: for i in std_logic_array_dem_5_sub'range(5) loop vv(2)(6)(i) := i; end loop l2_6;
lr1_1: for i in stdl_a_d5'Reverse_range loop vv_reverse(1)(1)(i) := i; end loop lr1_1;
lr1_2: for i in stdl_a_d5'Reverse_range(1) loop vv_reverse(1)(2)(i) := i; end loop lr1_2;
lr1_3: for i in stdl_a_d5'Reverse_range(2) loop vv_reverse(1)(3)(i) := i; end loop lr1_3;
lr1_4: for i in stdl_a_d5'Reverse_range(3) loop vv_reverse(1)(4)(i) := i; end loop lr1_4;
lr1_5: for i in stdl_a_d5'Reverse_range(4) loop vv_reverse(1)(5)(i) := i; end loop lr1_5;
lr1_6: for i in stdl_a_d5'Reverse_range(5) loop vv_reverse(1)(6)(i) := i; end loop lr1_6;
lr2_1: for i in std_logic_array_dem_5_sub'Reverse_range loop vv_reverse(2)(1)(i) := i; end loop lr2_1;
lr2_2: for i in std_logic_array_dem_5_sub'Reverse_range(1) loop vv_reverse(2)(2)(i) := i; end loop lr2_2;
lr2_3: for i in std_logic_array_dem_5_sub'Reverse_range(2) loop vv_reverse(2)(3)(i) := i; end loop lr2_3;
lr2_4: for i in std_logic_array_dem_5_sub'Reverse_range(3) loop vv_reverse(2)(4)(i) := i; end loop lr2_4;
lr2_5: for i in std_logic_array_dem_5_sub'Reverse_range(4) loop vv_reverse(2)(5)(i) := i; end loop lr2_5;
lr2_6: for i in std_logic_array_dem_5_sub'Reverse_range(5) loop vv_reverse(2)(6)(i) := i; end loop lr2_6;
-- bit array
l3_1: for i in bit_a_d5'range loop vv(3)(1)(i) := i; end loop l3_1;
l3_2: for i in bit_a_d5'range(1) loop vv(3)(2)(i) := i; end loop l3_2;
l3_3: for i in bit_a_d5'range(2) loop vv(3)(3)(i) := i; end loop l3_3;
l3_4: for i in bit_a_d5'range(3) loop vv(3)(4)(i) := i; end loop l3_4;
l3_5: for i in bit_a_d5'range(4) loop vv(3)(5)(i) := i; end loop l3_5;
l3_6: for i in bit_a_d5'range(5) loop vv(3)(6)(i) := i; end loop l3_6;
l4_1: for i in bit_array_dem_5_boarded'range loop vv(4)(1)(i) := i; end loop l4_1;
l4_2: for i in bit_array_dem_5_boarded'range(1) loop vv(4)(2)(i) := i; end loop l4_2;
l4_3: for i in bit_array_dem_5_boarded'range(2) loop vv(4)(3)(i) := i; end loop l4_3;
l4_4: for i in bit_array_dem_5_boarded'range(3) loop vv(4)(4)(i) := i; end loop l4_4;
l4_5: for i in bit_array_dem_5_boarded'range(4) loop vv(4)(5)(i) := i; end loop l4_5;
l4_6: for i in bit_array_dem_5_boarded'range(5) loop vv(4)(6)(i) := i; end loop l4_6;
lr3_1: for i in bit_a_d5'Reverse_range loop vv_reverse(3)(1)(i) := i; end loop lr3_1;
lr3_2: for i in bit_a_d5'Reverse_range(1) loop vv_reverse(3)(2)(i) := i; end loop lr3_2;
lr3_3: for i in bit_a_d5'Reverse_range(2) loop vv_reverse(3)(3)(i) := i; end loop lr3_3;
lr3_4: for i in bit_a_d5'Reverse_range(3) loop vv_reverse(3)(4)(i) := i; end loop lr3_4;
lr3_5: for i in bit_a_d5'Reverse_range(4) loop vv_reverse(3)(5)(i) := i; end loop lr3_5;
lr3_6: for i in bit_a_d5'Reverse_range(5) loop vv_reverse(3)(6)(i) := i; end loop lr3_6;
lr4_1: for i in bit_array_dem_5_boarded'Reverse_range loop vv_reverse(4)(1)(i) := i; end loop lr4_1;
lr4_2: for i in bit_array_dem_5_boarded'Reverse_range(1) loop vv_reverse(4)(2)(i) := i; end loop lr4_2;
lr4_3: for i in bit_array_dem_5_boarded'Reverse_range(2) loop vv_reverse(4)(3)(i) := i; end loop lr4_3;
lr4_4: for i in bit_array_dem_5_boarded'Reverse_range(3) loop vv_reverse(4)(4)(i) := i; end loop lr4_4;
lr4_5: for i in bit_array_dem_5_boarded'Reverse_range(4) loop vv_reverse(4)(5)(i) := i; end loop lr4_5;
lr4_6: for i in bit_array_dem_5_boarded'Reverse_range(5) loop vv_reverse(4)(6)(i) := i; end loop lr4_6;
-- integer array
l5_1: for i in int_a_d5'range loop vv(5)(1)(i) := i; end loop l5_1;
l5_2: for i in int_a_d5'range(1) loop vv(5)(2)(i) := i; end loop l5_2;
l5_3: for i in int_a_d5'range(2) loop vv(5)(3)(i) := i; end loop l5_3;
l5_4: for i in int_a_d5'range(3) loop vv(5)(4)(i) := i; end loop l5_4;
l5_5: for i in int_a_d5'range(4) loop vv(5)(5)(i) := i; end loop l5_5;
l5_6: for i in int_a_d5'range(5) loop vv(5)(6)(i) := i; end loop l5_6;
l6_1: for i in integer_array_dem_5_sub'range loop vv(6)(1)(i) := i; end loop l6_1;
l6_2: for i in integer_array_dem_5_sub'range(1) loop vv(6)(2)(i) := i; end loop l6_2;
l6_3: for i in integer_array_dem_5_sub'range(2) loop vv(6)(3)(i) := i; end loop l6_3;
l6_4: for i in integer_array_dem_5_sub'range(3) loop vv(6)(4)(i) := i; end loop l6_4;
l6_5: for i in integer_array_dem_5_sub'range(4) loop vv(6)(5)(i) := i; end loop l6_5;
l6_6: for i in integer_array_dem_5_sub'range(5) loop vv(6)(6)(i) := i; end loop l6_6;
lr5_1: for i in int_a_d5'Reverse_range loop vv_reverse(5)(1)(i) := i; end loop lr5_1;
lr5_2: for i in int_a_d5'Reverse_range(1) loop vv_reverse(5)(2)(i) := i; end loop lr5_2;
lr5_3: for i in int_a_d5'Reverse_range(2) loop vv_reverse(5)(3)(i) := i; end loop lr5_3;
lr5_4: for i in int_a_d5'Reverse_range(3) loop vv_reverse(5)(4)(i) := i; end loop lr5_4;
lr5_5: for i in int_a_d5'Reverse_range(4) loop vv_reverse(5)(5)(i) := i; end loop lr5_5;
lr5_6: for i in int_a_d5'Reverse_range(5) loop vv_reverse(5)(6)(i) := i; end loop lr5_6;
lr6_1: for i in integer_array_dem_5_sub'Reverse_range loop vv_reverse(6)(1)(i) := i; end loop lr6_1;
lr6_2: for i in integer_array_dem_5_sub'Reverse_range(1) loop vv_reverse(6)(2)(i) := i; end loop lr6_2;
lr6_3: for i in integer_array_dem_5_sub'Reverse_range(2) loop vv_reverse(6)(3)(i) := i; end loop lr6_3;
lr6_4: for i in integer_array_dem_5_sub'Reverse_range(3) loop vv_reverse(6)(4)(i) := i; end loop lr6_4;
lr6_5: for i in integer_array_dem_5_sub'Reverse_range(4) loop vv_reverse(6)(5)(i) := i; end loop lr6_5;
lr6_6: for i in integer_array_dem_5_sub'Reverse_range(5) loop vv_reverse(6)(6)(i) := i; end loop lr6_6;
-- boolean array
l7_1: for i in bool_a_d5'range loop vv(7)(1)(i) := i; end loop l7_1;
l7_2: for i in bool_a_d5'range(1) loop vv(7)(2)(i) := i; end loop l7_2;
l7_3: for i in bool_a_d5'range(2) loop vv(7)(3)(i) := i; end loop l7_3;
l7_4: for i in bool_a_d5'range(3) loop vv(7)(4)(i) := i; end loop l7_4;
l7_5: for i in bool_a_d5'range(4) loop vv(7)(5)(i) := i; end loop l7_5;
l7_6: for i in bool_a_d5'range(5) loop vv(7)(6)(i) := i; end loop l7_6;
l8_1: for i in boolean_array_dem_5_sub'range loop vv(8)(1)(i) := i; end loop l8_1;
l8_2: for i in boolean_array_dem_5_sub'range(1) loop vv(8)(2)(i) := i; end loop l8_2;
l8_3: for i in boolean_array_dem_5_sub'range(2) loop vv(8)(3)(i) := i; end loop l8_3;
l8_4: for i in boolean_array_dem_5_sub'range(3) loop vv(8)(4)(i) := i; end loop l8_4;
l8_5: for i in boolean_array_dem_5_sub'range(4) loop vv(8)(5)(i) := i; end loop l8_5;
l8_6: for i in boolean_array_dem_5_sub'range(5) loop vv(8)(6)(i) := i; end loop l8_6;
lr7_1: for i in bool_a_d5'Reverse_range loop vv_reverse(7)(1)(i) := i; end loop lr7_1;
lr7_2: for i in bool_a_d5'Reverse_range(1) loop vv_reverse(7)(2)(i) := i; end loop lr7_2;
lr7_3: for i in bool_a_d5'Reverse_range(2) loop vv_reverse(7)(3)(i) := i; end loop lr7_3;
lr7_4: for i in bool_a_d5'Reverse_range(3) loop vv_reverse(7)(4)(i) := i; end loop lr7_4;
lr7_5: for i in bool_a_d5'Reverse_range(4) loop vv_reverse(7)(5)(i) := i; end loop lr7_5;
lr7_6: for i in bool_a_d5'Reverse_range(5) loop vv_reverse(7)(6)(i) := i; end loop lr7_6;
lr8_1: for i in boolean_array_dem_5_sub'Reverse_range loop vv_reverse(8)(1)(i) := i; end loop lr8_1;
lr8_2: for i in boolean_array_dem_5_sub'Reverse_range(1) loop vv_reverse(8)(2)(i) := i; end loop lr8_2;
lr8_3: for i in boolean_array_dem_5_sub'Reverse_range(2) loop vv_reverse(8)(3)(i) := i; end loop lr8_3;
lr8_4: for i in boolean_array_dem_5_sub'Reverse_range(3) loop vv_reverse(8)(4)(i) := i; end loop lr8_4;
lr8_5: for i in boolean_array_dem_5_sub'Reverse_range(4) loop vv_reverse(8)(5)(i) := i; end loop lr8_5;
lr8_6: for i in boolean_array_dem_5_sub'Reverse_range(5) loop vv_reverse(8)(6)(i) := i; end loop lr8_6;
-- enum array
l9_1: for i in enum_a_d5'range loop vv(9)(1)(i) := i; end loop l9_1;
l9_2: for i in enum_a_d5'range(1) loop vv(9)(2)(i) := i; end loop l9_2;
l9_3: for i in enum_a_d5'range(2) loop vv(9)(3)(i) := i; end loop l9_3;
l9_4: for i in enum_a_d5'range(3) loop vv(9)(4)(i) := i; end loop l9_4;
l9_5: for i in enum_a_d5'range(4) loop vv(9)(5)(i) := i; end loop l9_5;
l9_6: for i in enum_a_d5'range(5) loop vv(9)(6)(i) := i; end loop l9_6;
l10_1: for i in enum_array_dem_5_boarded'range loop vv(10)(1)(i) := i; end loop l10_1;
l10_2: for i in enum_array_dem_5_boarded'range(1) loop vv(10)(2)(i) := i; end loop l10_2;
l10_3: for i in enum_array_dem_5_boarded'range(2) loop vv(10)(3)(i) := i; end loop l10_3;
l10_4: for i in enum_array_dem_5_boarded'range(3) loop vv(10)(4)(i) := i; end loop l10_4;
l10_5: for i in enum_array_dem_5_boarded'range(4) loop vv(10)(5)(i) := i; end loop l10_5;
l10_6: for i in enum_array_dem_5_boarded'range(5) loop vv(10)(6)(i) := i; end loop l10_6;
lr9_1: for i in enum_a_d5'Reverse_range loop vv_reverse(9)(1)(i) := i; end loop lr9_1;
lr9_2: for i in enum_a_d5'Reverse_range(1) loop vv_reverse(9)(2)(i) := i; end loop lr9_2;
lr9_3: for i in enum_a_d5'Reverse_range(2) loop vv_reverse(9)(3)(i) := i; end loop lr9_3;
lr9_4: for i in enum_a_d5'Reverse_range(3) loop vv_reverse(9)(4)(i) := i; end loop lr9_4;
lr9_5: for i in enum_a_d5'Reverse_range(4) loop vv_reverse(9)(5)(i) := i; end loop lr9_5;
lr9_6: for i in enum_a_d5'Reverse_range(5) loop vv_reverse(9)(6)(i) := i; end loop lr9_6;
lr10_1: for i in enum_array_dem_5_boarded'Reverse_range loop vv_reverse(10)(1)(i) := i; end loop lr10_1;
lr10_2: for i in enum_array_dem_5_boarded'Reverse_range(1) loop vv_reverse(10)(2)(i) := i; end loop lr10_2;
lr10_3: for i in enum_array_dem_5_boarded'Reverse_range(2) loop vv_reverse(10)(3)(i) := i; end loop lr10_3;
lr10_4: for i in enum_array_dem_5_boarded'Reverse_range(3) loop vv_reverse(10)(4)(i) := i; end loop lr10_4;
lr10_5: for i in enum_array_dem_5_boarded'Reverse_range(4) loop vv_reverse(10)(5)(i) := i; end loop lr10_5;
lr10_6: for i in enum_array_dem_5_boarded'Reverse_range(5) loop vv_reverse(10)(6)(i) := i; end loop lr10_6;
-- rec array
l11_1: for i in rec_a_d5'range loop vv(11)(1)(i) := i; end loop l11_1;
l11_2: for i in rec_a_d5'range(1) loop vv(11)(2)(i) := i; end loop l11_2;
l11_3: for i in rec_a_d5'range(2) loop vv(11)(3)(i) := i; end loop l11_3;
l11_4: for i in rec_a_d5'range(3) loop vv(11)(4)(i) := i; end loop l11_4;
l11_5: for i in rec_a_d5'range(4) loop vv(11)(5)(i) := i; end loop l11_5;
l11_6: for i in rec_a_d5'range(5) loop vv(11)(6)(i) := i; end loop l11_6;
l12_1: for i in rec_array_dem_5_sub'range loop vv(12)(1)(i) := i; end loop l12_1;
l12_2: for i in rec_array_dem_5_sub'range(1) loop vv(12)(2)(i) := i; end loop l12_2;
l12_3: for i in rec_array_dem_5_sub'range(2) loop vv(12)(3)(i) := i; end loop l12_3;
l12_4: for i in rec_array_dem_5_sub'range(3) loop vv(12)(4)(i) := i; end loop l12_4;
l12_5: for i in rec_array_dem_5_sub'range(4) loop vv(12)(5)(i) := i; end loop l12_5;
l12_6: for i in rec_array_dem_5_sub'range(5) loop vv(12)(6)(i) := i; end loop l12_6;
lr11_1: for i in rec_a_d5'Reverse_range loop vv_reverse(11)(1)(i) := i; end loop lr11_1;
lr11_2: for i in rec_a_d5'Reverse_range(1) loop vv_reverse(11)(2)(i) := i; end loop lr11_2;
lr11_3: for i in rec_a_d5'Reverse_range(2) loop vv_reverse(11)(3)(i) := i; end loop lr11_3;
lr11_4: for i in rec_a_d5'Reverse_range(3) loop vv_reverse(11)(4)(i) := i; end loop lr11_4;
lr11_5: for i in rec_a_d5'Reverse_range(4) loop vv_reverse(11)(5)(i) := i; end loop lr11_5;
lr11_6: for i in rec_a_d5'Reverse_range(5) loop vv_reverse(11)(6)(i) := i; end loop lr11_6;
lr12_1: for i in rec_array_dem_5_sub'Reverse_range loop vv_reverse(12)(1)(i) := i; end loop lr12_1;
lr12_2: for i in rec_array_dem_5_sub'Reverse_range(1) loop vv_reverse(12)(2)(i) := i; end loop lr12_2;
lr12_3: for i in rec_array_dem_5_sub'Reverse_range(2) loop vv_reverse(12)(3)(i) := i; end loop lr12_3;
lr12_4: for i in rec_array_dem_5_sub'Reverse_range(3) loop vv_reverse(12)(4)(i) := i; end loop lr12_4;
lr12_5: for i in rec_array_dem_5_sub'Reverse_range(4) loop vv_reverse(12)(5)(i) := i; end loop lr12_5;
lr12_6: for i in rec_array_dem_5_sub'Reverse_range(5) loop vv_reverse(12)(6)(i) := i; end loop lr12_6;
cond_loop: for i in 1 to 12 loop
-- low
cond(i)(1) := int(i)(1)(1) = 1 and int(i)(1)(2) = 1 and int(i)(1)(3) = 0 and int(i)(1)(4) = -1 and int(i)(1)(5) = 10 and int(i)(1)(6) = -3;
-- high
cond(i)(2) := int(i)(2)(1) = 3 and int(i)(2)(2) = 3 and int(i)(2)(3) = 7 and int(i)(2)(4) = 1 and int(i)(2)(5) = 20 and int(i)(2)(6) = 3;
-- left
cond(i)(3) := int(i)(3)(1) = 1 and int(i)(3)(2) = 1 and int(i)(3)(3) = 7 and int(i)(3)(4) = 1 and int(i)(3)(5) = 10 and int(i)(3)(6) = -3;
-- right
cond(i)(4) := int(i)(4)(1) = 3 and int(i)(4)(2) = 3 and int(i)(4)(3) = 0 and int(i)(4)(4) = -1 and int(i)(4)(5) = 20 and int(i)(4)(6) = 3;
-- length
cond(i)(5) := int(i)(5)(1) = 3 and int(i)(5)(2) = 3 and int(i)(5)(3) = 8 and int(i)(5)(4) = 3 and int(i)(5)(5) = 11 and int(i)(5)(6) = 7;
-- Ascending
cond(i)(6) := bool(i)(1) and bool(i)(2) and not(bool(i)(3)) and not(bool(i)(4)) and bool(i)(5) and bool(i)(6);
-- range
cond(i)(7) := all100(vv(i)(1)(-3 to 0)) and vv(i)(1)(1 to 3) = 1 & 2 & 3 and all100(vv(i)(1)(4 to 20)) and
all100(vv(i)(2)(-3 to 0)) and vv(i)(2)(1 to 3) = 1 & 2 & 3 and all100(vv(i)(2)(4 to 20)) and
all100(vv(i)(3)(-3 to -1)) and vv(i)(3)(0 to 7) = 0 & 1 & 2 & 3 & 4 & 5 & 6 & 7 and all100(vv(i)(3)(8 to 20)) and
all100(vv(i)(4)(-3 to -2)) and vv(i)(4)(-1 to 1) = -1 & 0 & 1 and all100(vv(i)(4)(2 to 20)) and
all100(vv(i)(5)(-3 to 9)) and vv(i)(5)(10 to 20) = 10 & 11 & 12 & 13 & 14 & 15 & 16 & 17 & 18 & 19 & 20 and
vv(i)(6)(-3 to 3) = (-3) & (-2) & (-1) & 0 & 1 & 2 & 3 and all100(vv(i)(6)(4 to 20));
-- reverse range
cond(i)(8) := all100(vv_reverse(i)(1)(-3 to 0)) and vv_reverse(i)(1)(1 to 3) = 1 & 2 & 3 and all100(vv_reverse(i)(1)(4 to 20)) and
all100(vv_reverse(i)(2)(-3 to 0)) and vv_reverse(i)(2)(1 to 3) = 1 & 2 & 3 and all100(vv_reverse(i)(2)(4 to 20)) and
all100(vv_reverse(i)(3)(-3 to -1)) and vv_reverse(i)(3)(0 to 7) = 0 & 1 & 2 & 3 & 4 & 5 & 6 & 7 and all100(vv_reverse(i)(3)(8 to 20)) and
all100(vv_reverse(i)(4)(-3 to -2)) and vv_reverse(i)(4)(-1 to 1) = -1 & 0 & 1 and all100(vv_reverse(i)(4)(2 to 20)) and
all100(vv_reverse(i)(5)(-3 to 9)) and vv_reverse(i)(5)(10 to 20) = 10 & 11 & 12 & 13 & 14 & 15 & 16 & 17 & 18 & 19 & 20 and
vv_reverse(i)(6)(-3 to 3) = (-3) & (-2) & (-1) & 0 & 1 & 2 & 3 and all100(vv_reverse(i)(6)(4 to 20));
end loop cond_loop;
-- std_logic_array
-- obj = 1
-- type = 2
-- bit array
-- obj = 3
-- type = 4
-- integer array
-- obj = 5
-- type = 6
-- boolean array
-- obj = 7
-- type = 8
-- enum array
-- obj = 9
-- type = 10
-- rec array
-- obj = 11
-- type = 12
when analize =>
state <= waiting;
-- std_logic array
-- Obj
assert not cond(1)(1)
report "Attribute A'Low(n) worked with the object of the type std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(1)(1)
report "Attribute A'Low(n) does not work with the object of the type std_logic array of demention up to 5"
severity NOTE;
assert not cond(1)(2)
report "Attribute A'High(n) worked with the object of the type std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(1)(2)
report "Attribute A'High(n) does not work with the object of the type std_logic array of demention up to 5"
severity NOTE;
assert not cond(1)(3)
report "Attribute A'Left(n) worked with the object of the type std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(1)(3)
report "Attribute A'Left(n) does not work with the object of the type std_logic array of demention up to 5"
severity NOTE;
assert not cond(1)(4)
report "Attribute A'Right(n) worked with the object of the type std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(1)(4)
report "Attribute A'Right(n) does not work with the object of the type std_logic array of demention up to 5"
severity NOTE;
assert not cond(1)(5)
report "Attribute A'Length(n) worked with the object of the type std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(1)(5)
report "Attribute A'Length(n) does not work with the object of the type std_logic array of demention up to 5"
severity NOTE;
assert not cond(1)(6)
report "Attribute A'Ascending(n) worked with the object of the type std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(1)(6)
report "Attribute A'Ascending(n) does not work with the object of the type std_logic array of demention up to 5"
severity NOTE;
assert not cond(1)(7)
report "Attribute A'Range(n) worked with the object of the type std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(1)(7)
report "Attribute A'Range(n) does not work with the object of the type std_logic array of demention up to 5"
severity NOTE;
assert not cond(1)(8)
report "Attribute A'Reverse_range(n) worked with the object of the type std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(1)(8)
report "Attribute A'Reverse_range(n) does not work with the object of the type std_logic array of demention up to 5"
severity NOTE;
-- subtype
assert not cond(2)(1)
report "Attribute A'Low(n) worked with the subtype std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(2)(1)
report "Attribute A'Low(n) does not work with the subtype std_logic array of demention up to 5"
severity NOTE;
assert not cond(2)(2)
report "Attribute A'High(n) worked with the subtype std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(2)(2)
report "Attribute A'High(n) does not work with the subtype std_logic array of demention up to 5"
severity NOTE;
assert not cond(2)(3)
report "Attribute A'Left(n) worked with the subtype std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(2)(3)
report "Attribute A'Left(n) does not work with the subtype std_logic array of demention up to 5"
severity NOTE;
assert not cond(2)(4)
report "Attribute A'Right(n) worked with the subtype std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(2)(4)
report "Attribute A'Right(n) does not work with the subtype std_logic array of demention up to 5"
severity NOTE;
assert not cond(2)(5)
report "Attribute A'Length(n) worked with the subtype std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(2)(5)
report "Attribute A'Length(n) does not work with the subtype std_logic array of demention up to 5"
severity NOTE;
assert not cond(2)(6)
report "Attribute A'Ascending(n) worked with the subtype std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(2)(6)
report "Attribute A'Ascending(n) does not work with the subtype std_logic array of demention up to 5"
severity NOTE;
assert not cond(2)(7)
report "Attribute A'Range(n) worked with the subtype std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(2)(7)
report "Attribute A'Range(n) does not work with the subtype std_logic array of demention up to 5"
severity NOTE;
assert not cond(2)(8)
report "Attribute A'Reverse_range(n) worked with the subtype std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(2)(8)
report "Attribute A'Reverse_range(n) does not work with the subtype std_logic array of demention up to 5"
severity NOTE;
-- bit array
-- Obj
assert not cond(3)(1)
report "Attribute A'Low(n) worked with the object of the type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(3)(1)
report "Attribute A'Low(n) does not work with the object of the type bit array of demention up to 5"
severity NOTE;
assert not cond(3)(2)
report "Attribute A'High(n) worked with the object of the type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(3)(2)
report "Attribute A'High(n) does not work with the object of the type bit array of demention up to 5"
severity NOTE;
assert not cond(3)(3)
report "Attribute A'Left(n) worked with the object of the type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(3)(3)
report "Attribute A'Left(n) does not work with the object of the type bit array of demention up to 5"
severity NOTE;
assert not cond(3)(4)
report "Attribute A'Right(n) worked with the object of the type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(3)(4)
report "Attribute A'Right(n) does not work with the object of the type bit array of demention up to 5"
severity NOTE;
assert not cond(3)(5)
report "Attribute A'Length(n) worked with the object of the type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(3)(5)
report "Attribute A'Length(n) does not work with the object of the type bit array of demention up to 5"
severity NOTE;
assert not cond(3)(6)
report "Attribute A'Ascending(n) worked with the object of the type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(3)(6)
report "Attribute A'Ascending(n) does not work with the object of the type bit array of demention up to 5"
severity NOTE;
assert not cond(3)(7)
report "Attribute A'Range(n) worked with the object of the type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(3)(7)
report "Attribute A'Range(n) does not work with the object of the type bit array of demention up to 5"
severity NOTE;
assert not cond(3)(8)
report "Attribute A'Reverse_range(n) worked with the object of the type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(3)(8)
report "Attribute A'Reverse_range(n) does not work with the object of the type bit array of demention up to 5"
severity NOTE;
-- subtype
assert not cond(4)(1)
report "Attribute A'Low(n) worked with the boarded type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(4)(1)
report "Attribute A'Low(n) does not work with the boarded type bit array of demention up to 5"
severity NOTE;
assert not cond(4)(2)
report "Attribute A'High(n) worked with the boarded type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(4)(2)
report "Attribute A'High(n) does not work with the boarded type bit array of demention up to 5"
severity NOTE;
assert not cond(4)(3)
report "Attribute A'Left(n) worked with the boarded type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(4)(3)
report "Attribute A'Left(n) does not work with the boarded type bit array of demention up to 5"
severity NOTE;
assert not cond(4)(4)
report "Attribute A'Right(n) worked with the boarded type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(4)(4)
report "Attribute A'Right(n) does not work with the boarded type bit array of demention up to 5"
severity NOTE;
assert not cond(4)(5)
report "Attribute A'Length(n) worked with the boarded type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(4)(5)
report "Attribute A'Length(n) does not work with the boarded type bit array of demention up to 5"
severity NOTE;
assert not cond(4)(6)
report "Attribute A'Ascending(n) worked with the boarded type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(4)(6)
report "Attribute A'Ascending(n) does not work with the boarded type bit array of demention up to 5"
severity NOTE;
assert not cond(4)(7)
report "Attribute A'Range(n) worked with the boarded type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(4)(7)
report "Attribute A'Range(n) does not work with the boarded type bit array of demention up to 5"
severity NOTE;
assert not cond(4)(8)
report "Attribute A'Reverse_range(n) worked with the boarded type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(4)(8)
report "Attribute A'Reverse_range(n) does not work with the boarded type bit array of demention up to 5"
severity NOTE;
-- integer array
-- Obj
assert not cond(5)(1)
report "Attribute A'Low(n) worked with the object of the type integer array of demention up to 5 correctly"
severity NOTE;
assert cond(5)(1)
report "Attribute A'Low(n) does not work with the object of the type integer array of demention up to 5"
severity NOTE;
assert not cond(5)(2)
report "Attribute A'High(n) worked with the object of the type integer array of demention up to 5 correctly"
severity NOTE;
assert cond(5)(2)
report "Attribute A'High(n) does not work with the object of the type integer array of demention up to 5"
severity NOTE;
assert not cond(5)(3)
report "Attribute A'Left(n) worked with the object of the type integer array of demention up to 5 correctly"
severity NOTE;
assert cond(5)(3)
report "Attribute A'Left(n) does not work with the object of the type integer array of demention up to 5"
severity NOTE;
assert not cond(5)(4)
report "Attribute A'Right(n) worked with the object of the type integer array of demention up to 5 correctly"
severity NOTE;
assert cond(5)(4)
report "Attribute A'Right(n) does not work with the object of the type integer array of demention up to 5"
severity NOTE;
assert not cond(5)(5)
report "Attribute A'Length(n) worked with the object of the type integer array of demention up to 5 correctly"
severity NOTE;
assert cond(5)(5)
report "Attribute A'Length(n) does not work with the object of the type integer array of demention up to 5"
severity NOTE;
assert not cond(5)(6)
report "Attribute A'Ascending(n) worked with the object of the type integer array of demention up to 5 correctly"
severity NOTE;
assert cond(5)(6)
report "Attribute A'Ascending(n) does not work with the object of the type integer array of demention up to 5"
severity NOTE;
assert not cond(5)(7)
report "Attribute A'Range(n) worked with the object of the type integer array of demention up to 5 correctly"
severity NOTE;
assert cond(5)(7)
report "Attribute A'Range(n) does not work with the object of the type integer array of demention up to 5"
severity NOTE;
assert not cond(5)(8)
report "Attribute A'Reverse_range(n) worked with the object of the type integer array of demention up to 5 correctly"
severity NOTE;
assert cond(5)(8)
report "Attribute A'Reverse_range(n) does not work with the object of the type integer array of demention up to 5"
severity NOTE;
-- subtype
assert not cond(6)(1)
report "Attribute A'Low(n) worked with the subtype integer array of demention up to 5 correctly"
severity NOTE;
assert cond(6)(1)
report "Attribute A'Low(n) does not work with the subtype integer array of demention up to 5"
severity NOTE;
assert not cond(6)(2)
report "Attribute A'High(n) worked with the subtype integer array of demention up to 5 correctly"
severity NOTE;
assert cond(6)(2)
report "Attribute A'High(n) does not work with the subtype integer array of demention up to 5"
severity NOTE;
assert not cond(6)(3)
report "Attribute A'Left(n) worked with the subtype integer array of demention up to 5 correctly"
severity NOTE;
assert cond(6)(3)
report "Attribute A'Left(n) does not work with the subtype integer array of demention up to 5"
severity NOTE;
assert not cond(6)(4)
report "Attribute A'Right(n) worked with the subtype integer array of demention up to 5 correctly"
severity NOTE;
assert cond(6)(4)
report "Attribute A'Right(n) does not work with the subtype integer array of demention up to 5"
severity NOTE;
assert not cond(6)(5)
report "Attribute A'Length(n) worked with the subtype integer array of demention up to 5 correctly"
severity NOTE;
assert cond(6)(5)
report "Attribute A'Length(n) does not work with the subtype integer array of demention up to 5"
severity NOTE;
assert not cond(6)(6)
report "Attribute A'Ascending(n) worked with the subtype integer array of demention up to 5 correctly"
severity NOTE;
assert cond(6)(6)
report "Attribute A'Ascending(n) does not work with the subtype integer array of demention up to 5"
severity NOTE;
assert not cond(6)(7)
report "Attribute A'Range(n) worked with the subtype integer array of demention up to 5 correctly"
severity NOTE;
assert cond(6)(7)
report "Attribute A'Range(n) does not work with the subtype integer array of demention up to 5"
severity NOTE;
assert not cond(6)(8)
report "Attribute A'Reverse_range(n) worked with the subtype integer array of demention up to 5 correctly"
severity NOTE;
assert cond(6)(8)
report "Attribute A'Reverse_range(n) does not work with the subtype integer array of demention up to 5"
severity NOTE;
-- boolean array
-- Obj
assert not cond(7)(1)
report "Attribute A'Low(n) worked with the object of the type boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(7)(1)
report "Attribute A'Low(n) does not work with the object of the type boolean array of demention up to 5"
severity NOTE;
assert not cond(7)(2)
report "Attribute A'High(n) worked with the object of the type boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(7)(2)
report "Attribute A'High(n) does not work with the object of the type boolean array of demention up to 5"
severity NOTE;
assert not cond(7)(3)
report "Attribute A'Left(n) worked with the object of the type boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(7)(3)
report "Attribute A'Left(n) does not work with the object of the type boolean array of demention up to 5"
severity NOTE;
assert not cond(7)(4)
report "Attribute A'Right(n) worked with the object of the type boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(7)(4)
report "Attribute A'Right(n) does not work with the object of the type boolean array of demention up to 5"
severity NOTE;
assert not cond(7)(5)
report "Attribute A'Length(n) worked with the object of the type boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(7)(5)
report "Attribute A'Length(n) does not work with the object of the type boolean array of demention up to 5"
severity NOTE;
assert not cond(7)(6)
report "Attribute A'Ascending(n) worked with the object of the type boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(7)(6)
report "Attribute A'Ascending(n) does not work with the object of the type boolean array of demention up to 5"
severity NOTE;
assert not cond(7)(7)
report "Attribute A'Range(n) worked with the object of the type boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(7)(7)
report "Attribute A'Range(n) does not work with the object of the type boolean array of demention up to 5"
severity NOTE;
assert not cond(7)(8)
report "Attribute A'Reverse_range(n) worked with the object of the type boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(7)(8)
report "Attribute A'Reverse_range(n) does not work with the object of the type boolean array of demention up to 5"
severity NOTE;
-- subtype
assert not cond(8)(1)
report "Attribute A'Low(n) worked with the subtype boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(8)(1)
report "Attribute A'Low(n) does not work with the subtype boolean array of demention up to 5"
severity NOTE;
assert not cond(8)(2)
report "Attribute A'High(n) worked with the subtype boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(8)(2)
report "Attribute A'High(n) does not work with the subtype boolean array of demention up to 5"
severity NOTE;
assert not cond(8)(3)
report "Attribute A'Left(n) worked with the subtype boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(8)(3)
report "Attribute A'Left(n) does not work with the subtype boolean array of demention up to 5"
severity NOTE;
assert not cond(8)(4)
report "Attribute A'Right(n) worked with the subtype boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(8)(4)
report "Attribute A'Right(n) does not work with the subtype boolean array of demention up to 5"
severity NOTE;
assert not cond(8)(5)
report "Attribute A'Length(n) worked with the subtype boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(8)(5)
report "Attribute A'Length(n) does not work with the subtype boolean array of demention up to 5"
severity NOTE;
assert not cond(8)(6)
report "Attribute A'Ascending(n) worked with the subtype boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(8)(6)
report "Attribute A'Ascending(n) does not work with the subtype boolean array of demention up to 5"
severity NOTE;
assert not cond(8)(7)
report "Attribute A'Range(n) worked with the subtype boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(8)(7)
report "Attribute A'Range(n) does not work with the subtype boolean array of demention up to 5"
severity NOTE;
assert not cond(8)(8)
report "Attribute A'Reverse_range(n) worked with the subtype boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(8)(8)
report "Attribute A'Reverse_range(n) does not work with the subtype boolean array of demention up to 5"
severity NOTE;
-- enum array
-- Obj
assert not cond(9)(1)
report "Attribute A'Low(n) worked with the object of the type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(9)(1)
report "Attribute A'Low(n) does not work with the object of the type enum array of demention up to 5"
severity NOTE;
assert not cond(9)(2)
report "Attribute A'High(n) worked with the object of the type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(9)(2)
report "Attribute A'High(n) does not work with the object of the type enum array of demention up to 5"
severity NOTE;
assert not cond(9)(3)
report "Attribute A'Left(n) worked with the object of the type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(9)(3)
report "Attribute A'Left(n) does not work with the object of the type enum array of demention up to 5"
severity NOTE;
assert not cond(9)(4)
report "Attribute A'Right(n) worked with the object of the type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(9)(4)
report "Attribute A'Right(n) does not work with the object of the type enum array of demention up to 5"
severity NOTE;
assert not cond(9)(5)
report "Attribute A'Length(n) worked with the object of the type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(9)(5)
report "Attribute A'Length(n) does not work with the object of the type enum array of demention up to 5"
severity NOTE;
assert not cond(9)(6)
report "Attribute A'Ascending(n) worked with the object of the type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(9)(6)
report "Attribute A'Ascending(n) does not work with the object of the type enum array of demention up to 5"
severity NOTE;
assert not cond(9)(7)
report "Attribute A'Range(n) worked with the object of the type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(9)(7)
report "Attribute A'Range(n) does not work with the object of the type enum array of demention up to 5"
severity NOTE;
assert not cond(9)(8)
report "Attribute A'Reverse_range(n) worked with the object of the type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(9)(8)
report "Attribute A'Reverse_range(n) does not work with the object of the type enum array of demention up to 5"
severity NOTE;
-- subtype
assert not cond(10)(1)
report "Attribute A'Low(n) worked with the boarded type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(10)(1)
report "Attribute A'Low(n) does not work with the boarded type enum array of demention up to 5"
severity NOTE;
assert not cond(10)(2)
report "Attribute A'High(n) worked with the boarded type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(10)(2)
report "Attribute A'High(n) does not work with the boarded type enum array of demention up to 5"
severity NOTE;
assert not cond(10)(3)
report "Attribute A'Left(n) worked with the boarded type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(10)(3)
report "Attribute A'Left(n) does not work with the boarded type enum array of demention up to 5"
severity NOTE;
assert not cond(10)(4)
report "Attribute A'Right(n) worked with the boarded type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(10)(4)
report "Attribute A'Right(n) does not work with the boarded type enum array of demention up to 5"
severity NOTE;
assert not cond(10)(5)
report "Attribute A'Length(n) worked with the boarded type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(10)(5)
report "Attribute A'Length(n) does not work with the boarded type enum array of demention up to 5"
severity NOTE;
assert not cond(10)(6)
report "Attribute A'Ascending(n) worked with the boarded type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(10)(6)
report "Attribute A'Ascending(n) does not work with the boarded type enum array of demention up to 5"
severity NOTE;
assert not cond(10)(7)
report "Attribute A'Range(n) worked with the boarded type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(10)(7)
report "Attribute A'Range(n) does not work with the boarded type enum array of demention up to 5"
severity NOTE;
assert not cond(10)(8)
report "Attribute A'Reverse_range(n) worked with the boarded type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(10)(8)
report "Attribute A'Reverse_range(n) does not work with the boarded type enum array of demention up to 5"
severity NOTE;
-- rec array
-- Obj
assert not cond(11)(1)
report "Attribute A'Low(n) worked with the object of the type record array of demention up to 5 correctly"
severity NOTE;
assert cond(11)(1)
report "Attribute A'Low(n) does not work with the object of the type record array of demention up to 5"
severity NOTE;
assert not cond(11)(2)
report "Attribute A'High(n) worked with the object of the type record array of demention up to 5 correctly"
severity NOTE;
assert cond(11)(2)
report "Attribute A'High(n) does not work with the object of the type record array of demention up to 5"
severity NOTE;
assert not cond(11)(3)
report "Attribute A'Left(n) worked with the object of the type record array of demention up to 5 correctly"
severity NOTE;
assert cond(11)(3)
report "Attribute A'Left(n) does not work with the object of the type record array of demention up to 5"
severity NOTE;
assert not cond(11)(4)
report "Attribute A'Right(n) worked with the object of the type record array of demention up to 5 correctly"
severity NOTE;
assert cond(11)(4)
report "Attribute A'Right(n) does not work with the object of the type record array of demention up to 5"
severity NOTE;
assert not cond(11)(5)
report "Attribute A'Length(n) worked with the object of the type record array of demention up to 5 correctly"
severity NOTE;
assert cond(11)(5)
report "Attribute A'Length(n) does not work with the object of the type record array of demention up to 5"
severity NOTE;
assert not cond(11)(6)
report "Attribute A'Ascending(n) worked with the object of the type record array of demention up to 5 correctly"
severity NOTE;
assert cond(11)(6)
report "Attribute A'Ascending(n) does not work with the object of the type record array of demention up to 5"
severity NOTE;
assert not cond(11)(7)
report "Attribute A'Range(n) worked with the object of the type record array of demention up to 5 correctly"
severity NOTE;
assert cond(11)(7)
report "Attribute A'Range(n) does not work with the object of the type record array of demention up to 5"
severity NOTE;
assert not cond(11)(8)
report "Attribute A'Reverse_range(n) worked with the object of the type record array of demention up to 5 correctly"
severity NOTE;
assert cond(11)(8)
report "Attribute A'Reverse_range(n) does not work with the object of the type record array of demention up to 5"
severity NOTE;
-- subtype
assert not cond(12)(1)
report "Attribute A'Low(n) worked with the subtype record array of demention up to 5 correctly"
severity NOTE;
assert cond(12)(1)
report "Attribute A'Low(n) does not work with the subtype record array of demention up to 5"
severity NOTE;
assert not cond(12)(2)
report "Attribute A'High(n) worked with the subtype record array of demention up to 5 correctly"
severity NOTE;
assert cond(12)(2)
report "Attribute A'High(n) does not work with the subtype record array of demention up to 5"
severity NOTE;
assert not cond(12)(3)
report "Attribute A'Left(n) worked with the subtype record array of demention up to 5 correctly"
severity NOTE;
assert cond(12)(3)
report "Attribute A'Left(n) does not work with the subtype record array of demention up to 5"
severity NOTE;
assert not cond(12)(4)
report "Attribute A'Right(n) worked with the subtype record array of demention up to 5 correctly"
severity NOTE;
assert cond(12)(4)
report "Attribute A'Right(n) does not work with the subtype record array of demention up to 5"
severity NOTE;
assert not cond(12)(5)
report "Attribute A'Length(n) worked with the subtype record array of demention up to 5 correctly"
severity NOTE;
assert cond(12)(5)
report "Attribute A'Length(n) does not work with the subtype record array of demention up to 5"
severity NOTE;
assert not cond(12)(6)
report "Attribute A'Ascending(n) worked with the subtype record array of demention up to 5 correctly"
severity NOTE;
assert cond(12)(6)
report "Attribute A'Ascending(n) does not work with the subtype record array of demention up to 5"
severity NOTE;
assert not cond(12)(7)
report "Attribute A'Range(n) worked with the subtype record array of demention up to 5 correctly"
severity NOTE;
assert cond(12)(7)
report "Attribute A'Range(n) does not work with the subtype record array of demention up to 5"
severity NOTE;
assert not cond(12)(8)
report "Attribute A'Reverse_range(n) worked with the subtype record array of demention up to 5 correctly"
severity NOTE;
assert cond(12)(8)
report "Attribute A'Reverse_range(n) does not work with the subtype record array of demention up to 5"
severity NOTE;
when waiting =>
null;
end case;
end process;
end ARCH00024_Test_Bench ; |
-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.10.0.111.2
-- Module Version: 5.8
-- Fri May 3 16:22:14 2019
-- parameterized module component declaration
component fmexg_fifo_3
port (Data: in std_logic_vector(11 downto 0);
WrClock: in std_logic; RdClock: in std_logic;
WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
RPReset: in std_logic; Q: out std_logic_vector(11 downto 0);
Empty: out std_logic; Full: out std_logic;
AlmostEmpty: out std_logic; AlmostFull: out std_logic);
end component;
-- parameterized module component instance
__ : fmexg_fifo_3
port map (Data(11 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
RdEn=>__, Reset=>__, RPReset=>__, Q(11 downto 0)=>__, Empty=>__,
Full=>__, AlmostEmpty=>__, AlmostFull=>__);
|
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: transport_commit_buffer - Behavioral
--
-- Description: Somewhere to hold the data outbound packet while waiting to
-- be granted access to the TX interface.
-- If the buffer gets over-run with data (e.g. if the TX interface is
-- busy) then it drops the packet.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity transport_commit_buffer is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic;
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end transport_commit_buffer;
architecture Behavioral of transport_commit_buffer is
type a_data_buffer is array(0 to 2047) of std_logic_vector(8 downto 0);
signal data_buffer : a_data_buffer := (others => (others => '0'));
attribute ram_style : string;
attribute ram_style of data_buffer : signal is "block";
signal read_addr : unsigned(10 downto 0) := (others => '1');
signal write_addr : unsigned(10 downto 0) := (others => '0');
signal committed_addr : unsigned(10 downto 0) := (others => '1');
type s_read_state is (read_idle, read_reading1, read_reading, read_waiting);
signal read_state : s_read_state := read_idle;
type s_write_state is (write_idle, write_writing, write_aborted);
signal write_state : s_write_state := write_idle;
signal i_packet_out_valid : std_logic := '0';
signal i_packet_out_valid_last : std_logic := '0';
signal i_packet_out_data : std_logic_vector(7 downto 0) := (others => '0');
constant fcs_length : integer := 4;
constant interpacket_gap : integer := 12;
constant for_next_preamble : integer := 8;
-- counter for the delay between packets
signal read_pause : unsigned(5 downto 0) := to_unsigned(fcs_length + interpacket_gap + for_next_preamble-1,6);
signal write_data : std_logic_vector(8 downto 0);
signal read_data : std_logic_vector(8 downto 0);
begin
with data_valid_in select write_data <= data_valid_in & data_in when '1',
(others => '0') when others;
i_packet_out_valid <= read_data(8);
i_packet_out_data <= read_data(7 downto 0);
packet_out_valid <= i_packet_out_valid;
packet_out_data <= i_packet_out_data;
infer_dp_mem_process: process(clk)
variable this_read_addr : unsigned(10 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if write_state = write_writing or data_valid_in = '1' then
data_buffer(to_integer(write_addr)) <= write_data;
end if;
this_read_addr := read_addr;
if i_packet_out_valid = '0' then
if read_addr = committed_addr or i_packet_out_valid_last = '1' then
packet_out_request <= '0';
else
packet_out_request <= '1';
if packet_out_granted = '1' then
this_read_addr := read_addr + 1;
end if;
end if;
else
this_read_addr := read_addr + 1;
end if;
i_packet_out_valid_last <= i_packet_out_valid;
read_data <= data_buffer(to_integer(this_read_addr));
read_addr <= this_read_addr;
end if;
end process;
process(clk)
variable write_data : std_logic_vector(8 downto 0);
begin
if rising_edge(clk) then
-------------------------------------------------
-- Writing the data into the buffer. If the buffer
-- would overrun the then packet is dropped (i.e.
-- committed_addr will not be updated).
------------------------------------------------
case write_state is
when write_writing =>
if write_addr+1 = read_addr then
-------------------------------------------------------
-- If we would wrap around? Is so then abort the packet
-------------------------------------------------------
write_addr <= committed_addr;
write_state <= write_aborted;
else
write_addr <= write_addr + 1;
if data_valid_in = '0' then
committed_addr <= write_addr;
write_state <= write_idle;
end if;
end if;
when write_aborted =>
---------------------------------------------------------
-- Wait until the data_valid_in drop at the end of packet
---------------------------------------------------------
if data_valid_in = '0' then
write_state <= write_idle;
end if;
when others => -- write_idle state
if data_valid_in = '1' then
write_addr <= write_addr + 1;
write_state <= write_writing;
end if;
end case;
end if;
end process;
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.flink_definitions.all;
use work.watchdog_pkg.all;
entity watchdogDevice_v1_0_S00_AXI is
generic (
-- Users to add parameters here
base_clk : INTEGER := 100000000;
unique_id : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of ID for for write address, write data, read address and read data
C_S_AXI_ID_WIDTH : integer := 1;
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 12;
-- Width of optional user defined signal in write address channel
C_S_AXI_AWUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in read address channel
C_S_AXI_ARUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in write data channel
C_S_AXI_WUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in read data channel
C_S_AXI_RUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in write response channel
C_S_AXI_BUSER_WIDTH : integer := 0
);
port (
-- Users to add ports here
osl_watchdog_pwm : OUT STD_LOGIC;
osl_granted : OUT STD_LOGIC;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write Address ID
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Write address
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
-- Lock type. Provides additional information about the
-- atomic characteristics of the transfer.
S_AXI_AWLOCK : in std_logic;
-- Memory type. This signal indicates how transactions
-- are required to progress through a system.
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Quality of Service, QoS identifier sent for each
-- write transaction.
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
-- Region identifier. Permits a single physical interface
-- on a slave to be used for multiple logical interfaces.
S_AXI_AWREGION : in std_logic_vector(3 downto 0);
-- Optional User-defined signal in the write address channel.
S_AXI_AWUSER : in std_logic_vector(C_S_AXI_AWUSER_WIDTH-1 downto 0);
-- Write address valid. This signal indicates that
-- the channel is signaling valid write address and
-- control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that
-- the slave is ready to accept an address and associated
-- control signals.
S_AXI_AWREADY : out std_logic;
-- Write Data
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte
-- lanes hold valid data. There is one write strobe
-- bit for each eight bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write last. This signal indicates the last transfer
-- in a write burst.
S_AXI_WLAST : in std_logic;
-- Optional User-defined signal in the write data channel.
S_AXI_WUSER : in std_logic_vector(C_S_AXI_WUSER_WIDTH-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Response ID tag. This signal is the ID tag of the
-- write response.
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Optional User-defined signal in the write response channel.
S_AXI_BUSER : out std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0);
-- Write response valid. This signal indicates that the
-- channel is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address ID. This signal is the identification
-- tag for the read address group of signals.
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Read address. This signal indicates the initial
-- address of a read burst transaction.
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
-- Lock type. Provides additional information about the
-- atomic characteristics of the transfer.
S_AXI_ARLOCK : in std_logic;
-- Memory type. This signal indicates how transactions
-- are required to progress through a system.
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Quality of Service, QoS identifier sent for each
-- read transaction.
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
-- Region identifier. Permits a single physical interface
-- on a slave to be used for multiple logical interfaces.
S_AXI_ARREGION : in std_logic_vector(3 downto 0);
-- Optional User-defined signal in the read address channel.
S_AXI_ARUSER : in std_logic_vector(C_S_AXI_ARUSER_WIDTH-1 downto 0);
-- Write address valid. This signal indicates that
-- the channel is signaling valid read address and
-- control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that
-- the slave is ready to accept an address and associated
-- control signals.
S_AXI_ARREADY : out std_logic;
-- Read ID tag. This signal is the identification tag
-- for the read data group of signals generated by the slave.
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Read Data
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of
-- the read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read last. This signal indicates the last transfer
-- in a read burst.
S_AXI_RLAST : out std_logic;
-- Optional User-defined signal in the read address channel.
S_AXI_RUSER : out std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0);
-- Read valid. This signal indicates that the channel
-- is signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end watchdogDevice_v1_0_S00_AXI;
architecture arch_imp of watchdogDevice_v1_0_S00_AXI is
-- AXI4FULL signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_buser : std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rlast : std_logic;
signal axi_ruser : std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0);
signal axi_rvalid : std_logic;
-- aw_wrap_en determines wrap boundary and enables wrapping
signal aw_wrap_en : std_logic;
-- ar_wrap_en determines wrap boundary and enables wrapping
signal ar_wrap_en : std_logic;
-- aw_wrap_size is the size of the write transfer, the
-- write address wraps to a lower address if upper address
-- limit is reached
signal aw_wrap_size : integer;
-- ar_wrap_size is the size of the read transfer, the
-- read address wraps to a lower address if upper address
-- limit is reached
signal ar_wrap_size : integer;
-- The axi_awv_awr_flag flag marks the presence of write address valid
signal axi_awv_awr_flag : std_logic;
--The axi_arv_arr_flag flag marks the presence of read address valid
signal axi_arv_arr_flag : std_logic;
-- The axi_awlen_cntr internal write address counter to keep track of beats in a burst transaction
signal axi_awlen_cntr : std_logic_vector(7 downto 0);
--The axi_arlen_cntr internal read address counter to keep track of beats in a burst transaction
signal axi_arlen_cntr : std_logic_vector(7 downto 0);
signal axi_arburst : std_logic_vector(2-1 downto 0);
signal axi_awburst : std_logic_vector(2-1 downto 0);
signal axi_arlen : std_logic_vector(8-1 downto 0);
signal axi_awlen : std_logic_vector(8-1 downto 0);
--local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
--ADDR_LSB is used for addressing 32/64 bit registers/memories
--ADDR_LSB = 2 for 32 bits (n downto 2)
--ADDR_LSB = 3 for 42 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
constant USER_NUM_MEM: integer := 1;
constant low : std_logic_vector (C_S_AXI_ADDR_WIDTH - 1 downto 0) := (OTHERS => '0');
CONSTANT c_usig_typdef_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_typdef_address, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_mem_size_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_mem_size_address*4, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_number_of_channels_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_channels_address*4, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_unique_id_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_unique_id_address*4, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_status_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_status_address*4, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_configuration_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_configuration_address*4, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_base_clk_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_std_registers*4, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_counter_val_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(unsigned(c_usig_base_clk_address)+4);
CONSTANT c_usig_max_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(unsigned(c_usig_counter_val_address)+4);
CONSTANT id : STD_LOGIC_VECTOR(15 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_watchdog_id, 16));
CONSTANT subtype_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
CONSTANT interface_version : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
TYPE t_internal_reg IS RECORD
counter_set_reg : UNSIGNED(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
reset_n : STD_LOGIC;
rearm : STD_LOGIC;
counter_changed : STD_LOGIC;
pwm_state : STD_LOGIC;
granted : STD_LOGIC;
END RECORD;
CONSTANT INTERNAL_REG_RESET : t_internal_reg := (
counter_set_reg => (OTHERS => '0'),
reset_n => '0',
rearm => '0',
counter_changed => '0',
pwm_state => '0',
granted => '0'
);
SIGNAL ri, ri_next : t_internal_reg := INTERNAL_REG_RESET;
SIGNAL granted : STD_LOGIC;
SIGNAL counter_val : UNSIGNED(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
------------------------------------------------
---- Signals for user logic memory space example
--------------------------------------------------
signal mem_address : std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
signal mem_select : std_logic_vector(USER_NUM_MEM-1 downto 0);
type word_array is array (0 to USER_NUM_MEM-1) of std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal mem_data_out : word_array;
signal i : integer;
signal j : integer;
signal mem_byte_index : integer;
type BYTE_RAM_TYPE is array (0 to 15) of std_logic_vector(7 downto 0);
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BUSER <= axi_buser;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RLAST <= axi_rlast;
S_AXI_RUSER <= axi_ruser;
S_AXI_RVALID <= axi_rvalid;
S_AXI_BID <= S_AXI_AWID;
S_AXI_RID <= S_AXI_ARID;
aw_wrap_size <= ((C_S_AXI_DATA_WIDTH)/8 * to_integer(unsigned(axi_awlen)));
ar_wrap_size <= ((C_S_AXI_DATA_WIDTH)/8 * to_integer(unsigned(axi_arlen)));
aw_wrap_en <= '1' when (((axi_awaddr AND std_logic_vector(to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH))) XOR std_logic_vector(to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH))) = low) else '0';
ar_wrap_en <= '1' when (((axi_araddr AND std_logic_vector(to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH))) XOR std_logic_vector(to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH))) = low) else '0';
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
axi_awv_awr_flag <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and axi_awv_awr_flag = '0' and axi_arv_arr_flag = '0') then
-- slave is ready to accept an address and
-- associated control signals
axi_awv_awr_flag <= '1'; -- used for generation of bresp() and bvalid
axi_awready <= '1';
elsif (S_AXI_WLAST = '1' and axi_wready = '1') then
-- preparing to accept next address after current write burst tx completion
axi_awv_awr_flag <= '0';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
axi_awburst <= (others => '0');
axi_awlen <= (others => '0');
axi_awlen_cntr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and axi_awv_awr_flag = '0') then
-- address latching
axi_awaddr <= S_AXI_AWADDR(C_S_AXI_ADDR_WIDTH - 1 downto 0); ---- start address of transfer
axi_awlen_cntr <= (others => '0');
axi_awburst <= S_AXI_AWBURST;
axi_awlen <= S_AXI_AWLEN;
elsif((axi_awlen_cntr <= axi_awlen) and axi_wready = '1' and S_AXI_WVALID = '1') then
axi_awlen_cntr <= std_logic_vector (unsigned(axi_awlen_cntr) + 1);
case (axi_awburst) is
when "00" => -- fixed burst
-- The write address for all the beats in the transaction are fixed
axi_awaddr <= axi_awaddr; ----for awsize = 4 bytes (010)
when "01" => --incremental burst
-- The write address for all the beats in the transaction are increments by awsize
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--awaddr aligned to 4 byte boundary
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
when "10" => --Wrapping burst
-- The write address wraps when the address reaches wrap boundary
if (aw_wrap_en = '1') then
axi_awaddr <= std_logic_vector (unsigned(axi_awaddr) - (to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH)));
else
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--awaddr aligned to 4 byte boundary
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
end if;
when others => --reserved (incremental burst for example)
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--for awsize = 4 bytes (010)
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and axi_awv_awr_flag = '1') then
axi_wready <= '1';
-- elsif (axi_awv_awr_flag = '0') then
elsif (S_AXI_WLAST = '1' and axi_wready = '1') then
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
axi_buser <= (others => '0');
else
if (axi_awv_awr_flag = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' and S_AXI_WLAST = '1' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
--check if bready is asserted while bvalid is high)
axi_bvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_arv_arr_flag <= '0';
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and axi_awv_awr_flag = '0' and axi_arv_arr_flag = '0') then
axi_arready <= '1';
axi_arv_arr_flag <= '1';
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1' and (axi_arlen_cntr = axi_arlen)) then
-- preparing to accept next address after current read completion
axi_arv_arr_flag <= '0';
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_araddr latching
--This process is used to latch the address when both
--S_AXI_ARVALID and S_AXI_RVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_araddr <= (others => '0');
axi_arburst <= (others => '0');
axi_arlen <= (others => '0');
axi_arlen_cntr <= (others => '0');
axi_rlast <= '0';
axi_ruser <= (others => '0');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and axi_arv_arr_flag = '0') then
-- address latching
axi_araddr <= S_AXI_ARADDR(C_S_AXI_ADDR_WIDTH - 1 downto 0); ---- start address of transfer
axi_arlen_cntr <= (others => '0');
axi_rlast <= '0';
axi_arburst <= S_AXI_ARBURST;
axi_arlen <= S_AXI_ARLEN;
elsif((axi_arlen_cntr <= axi_arlen) and axi_rvalid = '1' and S_AXI_RREADY = '1') then
axi_arlen_cntr <= std_logic_vector (unsigned(axi_arlen_cntr) + 1);
axi_rlast <= '0';
case (axi_arburst) is
when "00" => -- fixed burst
-- The read address for all the beats in the transaction are fixed
axi_araddr <= axi_araddr; ----for arsize = 4 bytes (010)
when "01" => --incremental burst
-- The read address for all the beats in the transaction are increments by awsize
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1); --araddr aligned to 4 byte boundary
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
when "10" => --Wrapping burst
-- The read address wraps when the address reaches wrap boundary
if (ar_wrap_en = '1') then
axi_araddr <= std_logic_vector (unsigned(axi_araddr) - (to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH)));
else
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1); --araddr aligned to 4 byte boundary
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
end if;
when others => --reserved (incremental burst for example)
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--for arsize = 4 bytes (010)
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0');
end case;
elsif((axi_arlen_cntr = axi_arlen) and axi_rlast = '0' and axi_arv_arr_flag = '1') then
axi_rlast <= '1';
elsif (S_AXI_RREADY = '1') then
axi_rlast <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
ri <= ri_next;
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arv_arr_flag = '1' and axi_rvalid = '0') then
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- ------------------------------------------
-- -- Example code to access user logic memory region
-- ------------------------------------------
--read data
process( axi_rvalid,axi_araddr,ri ) is
begin
if (axi_rvalid = '1') then
-- output the read dada
IF(axi_araddr = c_usig_typdef_address) THEN
axi_rdata(31 DOWNTO 16) <= id;
axi_rdata(15 DOWNTO 8) <= subtype_id;
axi_rdata(7 DOWNTO 0) <= interface_version;
ELSIF(axi_araddr = c_usig_mem_size_address)THEN
axi_rdata <= (others => '0');
axi_rdata(C_S_AXI_ADDR_WIDTH) <= '1';
ELSIF(axi_araddr = c_usig_number_of_channels_address)THEN
axi_rdata <= std_logic_vector(to_unsigned(1,C_S_AXI_DATA_WIDTH));
ELSIF(axi_araddr = c_usig_unique_id_address) THEN
axi_rdata <= unique_id;
ELSIF(axi_araddr = c_usig_status_address) THEN
axi_rdata <= (OTHERS => '0');
axi_rdata(0) <= ri.granted;
ELSIF(axi_araddr = c_usig_configuration_address) THEN
axi_rdata <= (OTHERS => '0');
ELSIF(axi_araddr = c_usig_base_clk_address) THEN
axi_rdata <= STD_LOGIC_VECTOR(to_unsigned(base_clk,axi_rdata'length));
ELSIF (axi_araddr >= c_usig_counter_val_address AND axi_araddr < c_usig_max_address) THEN
axi_rdata <= STD_LOGIC_VECTOR(counter_val);
ELSE
axi_rdata <= (others => '0');
END IF;
else
axi_rdata <= (others => '0');
end if;
end process;
--write
process( axi_wready,S_AXI_WVALID,S_AXI_WDATA,axi_awaddr,S_AXI_WSTRB,ri,S_AXI_ARESETN,granted)
VARIABLE vi: t_internal_reg := INTERNAL_REG_RESET;
BEGIN
-- keep variables stable
vi := ri;
vi.granted := granted;
--standard values
vi.reset_n := '1';
vi.rearm := '0';
vi.counter_changed := '0';
IF(axi_wready = '1') THEN
IF(axi_awaddr >= c_usig_configuration_address AND axi_awaddr < c_usig_counter_val_address) THEN
IF(S_AXI_WSTRB(0) = '1')THEN
vi.rearm := S_AXI_WDATA(0);
END IF;
ELSIF(axi_awaddr >= c_usig_counter_val_address AND axi_awaddr < c_usig_max_address) THEN
IF(S_AXI_WSTRB(0) = '1')THEN
vi.counter_set_reg(7 DOWNTO 0) := unsigned(S_AXI_WDATA(7 DOWNTO 0));
vi.counter_changed := '1';
END IF;
IF(S_AXI_WSTRB(1) = '1')THEN
vi.counter_set_reg(15 DOWNTO 8) := unsigned(S_AXI_WDATA(15 DOWNTO 8));
vi.counter_changed := '1';
END IF;
IF(S_AXI_WSTRB(2) = '1')THEN
vi.counter_set_reg(23 DOWNTO 16) := unsigned(S_AXI_WDATA(23 DOWNTO 16));
vi.counter_changed := '1';
END IF;
IF(S_AXI_WSTRB(3) = '1')THEN
vi.counter_set_reg(31 DOWNTO 24) := unsigned(S_AXI_WDATA(31 DOWNTO 24));
vi.counter_changed := '1';
END IF;
vi.counter_changed := '1';
IF granted = '1' THEN
vi.pwm_state := NOT vi.pwm_state;
END IF;
END IF;
END IF;
IF(S_AXI_ARESETN = '0')THEN
vi := INTERNAL_REG_RESET;
END IF;
ri_next <= vi;
END PROCESS;
gen_wd: watchdog GENERIC MAP(gi_counter_resolution => C_S_AXI_DATA_WIDTH)
PORT MAP(S_AXI_ACLK, ri.reset_n, ri.counter_set_reg, ri.counter_changed, ri.rearm, counter_val, granted);
-- Add user logic here
osl_watchdog_pwm <= ri.pwm_state;
osl_granted <= ri.granted;
-- User logic ends
end arch_imp;
|
-- $Id: tb_c7_sram_memctl.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_c7_sram_memctl - sim
-- Description: Test bench for c7_sram_memctl
--
-- Dependencies: vlib/simlib/simclk
-- vlib/simlib/simclkcnt
-- bplib/issi/is61wv5128bll
-- c7_sram_memctl [UUT]
--
-- To test: c7_sram_memctl
--
-- Verified (with tb_c7_sram_memctl_stim.dat):
-- Date Rev Code ghdl viv Target Comment
-- 2017-06-11 912 _ssim 0.34 2017.1 xx xx
--
-- Target Devices: generic
-- Tool versions: viv 2017.1; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-13 913 1.0 Initial version (derived from tb_s3_sram_memctl)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.cmoda7lib.all;
use work.simlib.all;
entity tb_c7_sram_memctl is
end tb_c7_sram_memctl;
architecture sim of tb_c7_sram_memctl is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal REQ : slbit := '0';
signal WE : slbit := '0';
signal BUSY : slbit := '0';
signal ACK_R : slbit := '0';
signal ACK_W : slbit := '0';
signal ACT_R : slbit := '0';
signal ACT_W : slbit := '0';
signal ADDR : slv17 := (others=>'0');
signal BE : slv4 := (others=>'0');
signal DI : slv32 := (others=>'0');
signal DO : slv32 := (others=>'0');
signal O_MEM_CE_N : slbit := '0';
signal O_MEM_WE_N : slbit := '0';
signal O_MEM_OE_N : slbit := '0';
signal O_MEM_ADDR : slv19 := (others=>'0');
signal IO_MEM_DATA : slv8 := (others=>'0');
signal R_MEMON : slbit := '0';
signal N_CHK_DATA : slbit := '0';
signal N_REF_DATA : slv32 := (others=>'0');
signal N_REF_ADDR : slv17 := (others=>'0');
signal R_CHK_DATA_AL : slbit := '0';
signal R_REF_DATA_AL : slv32 := (others=>'0');
signal R_REF_ADDR_AL : slv17 := (others=>'0');
signal R_CHK_DATA_DL : slbit := '0';
signal R_REF_DATA_DL : slv32 := (others=>'0');
signal R_REF_ADDR_DL : slv17 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
MEM : entity work.is61wv5128bll
port map (
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
UUT : c7_sram_memctl
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR,
BE => BE,
DI => DI,
DO => DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
proc_stim: process
file fstim : text open read_mode is "tb_c7_sram_memctl_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable iaddr : slv17 := (others=>'0');
variable idata : slv32 := (others=>'0');
variable ibe : slv4 := (others=>'0');
variable ival : slbit := '0';
variable nbusy : integer := 0;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".memon" => -- .memon
read_ea(iline, ival);
R_MEMON <= ival;
wait for 2*clock_period;
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when "read " => -- read
readgen_ea(iline, iaddr, 16);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
REQ <= '1';
WE <= '0';
writetimestamp(oline, CLK_CYCLE, ": stim read ");
writegen(oline, iaddr, right, 6, 16);
write(oline, string'(" "));
writegen(oline, idata, right, 9, 16);
wait for clock_period;
REQ <= '0';
N_CHK_DATA <= '1', '0' after clock_period;
N_REF_DATA <= idata;
N_REF_ADDR <= iaddr;
nbusy := 0;
while BUSY = '1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
when "write " => -- write
readgen_ea(iline, iaddr, 16);
read_ea(iline, ibe);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
BE <= ibe;
DI <= idata;
REQ <= '1';
WE <= '1';
writetimestamp(oline, CLK_CYCLE, ": stim write");
writegen(oline, iaddr, right, 6, 16);
writegen(oline, ibe , right, 5, 2);
writegen(oline, idata, right, 9, 16);
wait for clock_period;
REQ <= '0';
WE <= '0';
nbusy := 0;
while BUSY = '1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
when others => -- bad directive
write(oline, string'("?? unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file fstim
wait for 10*clock_period;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if ACK_R = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
writegen(oline, DO, right, 9, 16);
if R_CHK_DATA_DL = '1' then
write(oline, string'(" CHECK"));
if R_REF_DATA_DL = DO then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
writegen(oline, R_REF_DATA_DL, right, 9, 16);
write(oline, string'(" for a="));
writegen(oline, R_REF_ADDR_DL, right, 5, 16);
end if;
R_CHK_DATA_DL <= '0';
end if;
writeline(output, oline);
end if;
if R_CHK_DATA_AL = '1' then
R_CHK_DATA_DL <= R_CHK_DATA_AL;
R_REF_DATA_DL <= R_REF_DATA_AL;
R_REF_ADDR_DL <= R_REF_ADDR_AL;
R_CHK_DATA_AL <= '0';
end if;
if N_CHK_DATA = '1' then
R_CHK_DATA_AL <= N_CHK_DATA;
R_REF_DATA_AL <= N_REF_DATA;
R_REF_ADDR_AL <= N_REF_ADDR;
end if;
end loop;
end process proc_moni;
proc_memon: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if R_MEMON = '1' then
writetimestamp(oline, CLK_CYCLE, ": mem ");
write(oline, string'(" ce="));
write(oline, not O_MEM_CE_N, right, 2);
write(oline, string'(" we="));
write(oline, not O_MEM_WE_N, right);
write(oline, string'(" oe="));
write(oline, not O_MEM_OE_N, right);
write(oline, string'(" a="));
writegen(oline, O_MEM_ADDR, right, 5, 16);
write(oline, string'(" d="));
writegen(oline, IO_MEM_DATA, right, 8, 16);
writeline(output, oline);
end if;
end loop;
end process proc_memon;
end sim;
|
library ieee;
use ieee.std_logic_1164.all;
entity onebitvoter_solution_example_tb is
end onebitvoter_solution_example_tb;
architecture TB_ARCHITECTURE of onebitvoter_solution_example_tb is
signal clk : std_logic := '0';
signal reset : std_logic;
signal data_in : std_logic_vector(3 downto 0);
signal y : std_logic;
signal status : std_logic_vector (2 downto 0);
type testvec_t is array(0 to 1, 0 to 8) of std_logic_vector(7 downto 0);
constant testvec : testvec_t := ((
-- input & y & status
0 => "1111" & "1" & "000",
1 => "1111" & "1" & "000",
2 => "0000" & "0" & "000",
3 => "0100" & "0" & "001", -- First fail.
4 => "1000" & "0" & "010", -- Second fail.
5 => "0011" & "1" & "010",
6 => "1100" & "0" & "010",
7 => "1110" & "0" & "111", -- Third fail.
8 => "1111" & "0" & "111"
),(
-- input & y & status
0 => "0000" & "0" & "000",
1 => "0000" & "0" & "000",
2 => "1111" & "1" & "000",
3 => "1110" & "1" & "001", -- First fail.
4 => "1101" & "1" & "010", -- Second fail.
5 => "0011" & "0" & "010",
6 => "1100" & "1" & "010",
7 => "1000" & "0" & "111", -- Third fail.
8 => "1111" & "0" & "111"
));
begin
-- Change this to your entity and architecture name.
dut: entity onebitvoter
port map (
clk => clk, reset => reset,
a => data_in(3), b => data_in(2), c => data_in(1), d => data_in(0),
y => y, status => status
);
clk <= not clk after 5ns;
process is begin
for i in testvec'range(1) loop
-- Reset:
reset <= '1';
wait until falling_edge(clk);
reset <= '0';
for j in testvec'range(2) loop
-- Update inputs.
data_in <= testvec(i, j)(7 downto 4);
-- Wait one clock cycle, then check ouputs.
wait until falling_edge(clk);
assert y = testvec(i, j)(3) report "Output 'y' wrong at vector " & integer'image(i) & ", " & integer'image(j) severity error;
assert status = testvec(i, j)(2 downto 0) report "Output 'status' wrong at vector " & integer'image(i) & ", " & integer'image(j) severity error;
end loop;
end loop;
wait; -- Testbench completed.
end process;
end architecture; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--MIPI CSI-2 Rx 4 lane link layer
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This combines the clock and data PHYs; byte aligners and word aligner to
--form the lower levels of the CSI Rx link layer
entity csi_rx_4_lane_link is
generic(
fpga_series : string := "7SERIES";
dphy_term_en : boolean := true;
d0_invert : boolean := false;
d1_invert : boolean := false;
d2_invert : boolean := false;
d3_invert : boolean := false;
d0_skew : natural := 0;
d1_skew : natural := 0;
d2_skew : natural := 0;
d3_skew : natural := 0;
generate_idelayctrl : boolean := false
);
port(
dphy_clk : in STD_LOGIC_VECTOR (1 downto 0); --clock lane (1 is P, 0 is N)
dphy_d0 : in STD_LOGIC_VECTOR (1 downto 0); --data lanes (1 is P, 0 is N)
dphy_d1 : in STD_LOGIC_VECTOR (1 downto 0);
dphy_d2 : in STD_LOGIC_VECTOR (1 downto 0);
dphy_d3 : in STD_LOGIC_VECTOR (1 downto 0);
ref_clock : in STD_LOGIC; --reference clock for clock detection and IDELAYCTRLs (nominally ~200MHz)
reset : in STD_LOGIC; --active high synchronous reset in
enable : in STD_LOGIC; --active high enable out
wait_for_sync : in STD_LOGIC; --sync wait signal from packet handler
packet_done : in STD_LOGIC; --packet done signal from packet handler
reset_out : out STD_LOGIC; --reset output based on clock detection
word_clock : out STD_LOGIC; --divided word clock output
word_data : out STD_LOGIC_VECTOR (31 downto 0); --aligned word data output
word_valid : out STD_LOGIC --whether or not above data is synced and aligned
);
end csi_rx_4_lane_link;
architecture Behavioral of csi_rx_4_lane_link is
signal ddr_bit_clock : std_logic;
signal ddr_bit_clock_b : std_logic;
signal word_clock_int : std_logic;
signal serdes_reset : std_logic;
signal deser_data : std_logic_vector(31 downto 0);
signal deser_data_rev : std_logic_vector(31 downto 0);
signal byte_align_data : std_logic_vector(31 downto 0);
signal byte_valid : std_logic_vector(3 downto 0);
signal word_align_data : std_logic_vector(31 downto 0);
signal byte_packet_done : std_logic;
begin
clkphy : entity work.csi_rx_hs_clk_phy
generic map(
series => fpga_series,
term_en => dphy_term_en)
port map(
dphy_clk => dphy_clk,
reset => reset,
ddr_bit_clock => ddr_bit_clock,
ddr_bit_clock_b => ddr_bit_clock_b,
byte_clock => word_clock_int);
clkdet : entity work.csi_rx_clock_det
port map(
ref_clock => ref_clock,
ext_clock => word_clock_int,
enable => enable,
reset_in => reset,
reset_out => serdes_reset);
d0phy : entity work.csi_rx_hs_lane_phy
generic map(
series => fpga_series,
invert => d0_invert,
term_en => dphy_term_en,
delay => d0_skew)
port map (
ddr_bit_clock => ddr_bit_clock,
ddr_bit_clock_b => ddr_bit_clock_b,
byte_clock => word_clock_int,
enable => enable,
reset => serdes_reset,
dphy_hs => dphy_d0,
deser_out => deser_data(7 downto 0));
d1phy : entity work.csi_rx_hs_lane_phy
generic map(
series => fpga_series,
invert => d1_invert,
term_en => dphy_term_en,
delay => d1_skew)
port map (
ddr_bit_clock => ddr_bit_clock,
ddr_bit_clock_b => ddr_bit_clock_b,
byte_clock => word_clock_int,
enable => enable,
reset => serdes_reset,
dphy_hs => dphy_d1,
deser_out => deser_data(15 downto 8));
d2phy : entity work.csi_rx_hs_lane_phy
generic map(
series => fpga_series,
invert => d2_invert,
term_en => dphy_term_en,
delay => d2_skew)
port map (
ddr_bit_clock => ddr_bit_clock,
ddr_bit_clock_b => ddr_bit_clock_b,
byte_clock => word_clock_int,
enable => enable,
reset => serdes_reset,
dphy_hs => dphy_d2,
deser_out => deser_data(23 downto 16));
d3phy : entity work.csi_rx_hs_lane_phy
generic map(
series => fpga_series,
invert => d3_invert,
term_en => dphy_term_en,
delay => d3_skew)
port map (
ddr_bit_clock => ddr_bit_clock,
ddr_bit_clock_b => ddr_bit_clock_b,
byte_clock => word_clock_int,
enable => enable,
reset => serdes_reset,
dphy_hs => dphy_d3,
deser_out => deser_data(31 downto 24));
gen_bytealign : for i in 0 to 3 generate
ba : entity work.csi_rx_byte_align
port map (
clock => word_clock_int,
reset => serdes_reset,
enable => enable,
deser_in => deser_data((8*i) + 7 downto 8 * i),
wait_for_sync => wait_for_sync,
packet_done => byte_packet_done,
valid_data => byte_valid(i),
data_out => byte_align_data((8*i) + 7 downto 8 * i));
end generate;
wordalign : entity work.csi_rx_word_align
port map (
word_clock => word_clock_int,
reset => serdes_reset,
enable => enable,
packet_done => packet_done,
wait_for_sync => wait_for_sync,
packet_done_out => byte_packet_done,
word_in => byte_align_data,
valid_in => byte_valid,
word_out => word_align_data,
valid_out => word_valid);
word_clock <= word_clock_int;
word_data <= word_align_data;
reset_out <= serdes_reset;
gen_idctl : if generate_idelayctrl generate
idctrl : entity work.csi_rx_idelayctrl_gen
port map(
ref_clock => ref_clock,
reset => reset);
end generate;
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: wr_fifo32to256_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.wr_fifo32to256_pkg.ALL;
ENTITY wr_fifo32to256_tb IS
END ENTITY;
ARCHITECTURE wr_fifo32to256_arch OF wr_fifo32to256_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from wr_fifo32to256_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of wr_fifo32to256_synth
wr_fifo32to256_synth_inst:wr_fifo32to256_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 4
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
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`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.std_logic_unsigned.all;
entity clk_gen is
port(
clk : in std_logic;
sck : in std_logic;
data : in std_logic;
cs_n : in std_logic;
output : out std_logic
);
end clk_gen;
architecture logic of clk_gen is
component spi_receiver is
port(
clk : in std_logic;
sck : in std_logic;
data : in std_logic;
cs_n : in std_logic;
irq : out std_logic;
parallel_out : out std_logic_vector(7 downto 0)
);
end component;
component clk_divider is
port(
clk : in std_logic;
setting : in std_logic_vector(7 downto 0);
wrt : in std_logic;
clk_out : out std_logic
);
end component;
signal irq : std_logic := '0';
signal setting : std_logic_vector(7 downto 0) := (others => '1');
begin
spi_recvr:spi_receiver
port map(
clk => clk,
sck => sck,
data => data,
cs_n => cs_n,
irq => irq,
parallel_out => setting
);
clk_div:clk_divider
port map(
clk => clk,
setting => setting,
wrt => irq,
clk_out => output
);
end logic; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Package: grusb
-- File: grusb.vhd
-- Author: Marko Isomaki, Jonas Ekergarn
-- Description: Package for GRUSBHC, GRUSBDC, and GRUSB_DCL
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package grusb is
-----------------------------------------------------------------------------
-- USB in/out types
-----------------------------------------------------------------------------
type grusb_in_type is record
datain : std_logic_vector(15 downto 0);
rxactive : std_ulogic;
rxvalid : std_ulogic;
rxvalidh : std_ulogic;
rxerror : std_ulogic;
txready : std_ulogic;
linestate : std_logic_vector(1 downto 0);
nxt : std_ulogic;
dir : std_ulogic;
vbusvalid : std_ulogic;
hostdisconnect : std_ulogic;
functesten : std_ulogic;
urstdrive : std_ulogic;
end record;
constant grusb_in_none : grusb_in_type :=
((others => '0'), '0', '0', '0', '0', '0', (others => '0'),
'0', '0', '0', '0', '0', '0');
type grusb_out_type is record
dataout : std_logic_vector(15 downto 0);
txvalid : std_ulogic;
txvalidh : std_ulogic;
opmode : std_logic_vector(1 downto 0);
xcvrselect : std_logic_vector(1 downto 0);
termselect : std_ulogic;
suspendm : std_ulogic;
reset : std_ulogic;
stp : std_ulogic;
oen : std_ulogic;
databus16_8 : std_ulogic;
dppulldown : std_ulogic;
dmpulldown : std_ulogic;
idpullup : std_ulogic;
drvvbus : std_ulogic;
dischrgvbus : std_ulogic;
chrgvbus : std_ulogic;
txbitstuffenable : std_ulogic;
txbitstuffenableh : std_ulogic;
fslsserialmode : std_ulogic;
tx_enable_n : std_ulogic;
tx_dat : std_ulogic;
tx_se0 : std_ulogic;
end record;
constant grusb_out_none : grusb_out_type :=
((others => '0'), '0', '0', (others => '0'), (others => '0'),
'0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0');
type grusb_in_vector is array (natural range <>) of grusb_in_type;
type grusb_out_vector is array (natural range <>) of grusb_out_type;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component grusbhc is
generic (
ehchindex : integer range 0 to NAHBMST-1 := 0;
ehcpindex : integer range 0 to NAPBSLV-1 := 0;
ehcpaddr : integer range 0 to 16#FFF# := 0;
ehcpirq : integer range 0 to NAHBIRQ-1 := 0;
ehcpmask : integer range 0 to 16#FFF# := 16#FFF#;
uhchindex : integer range 0 to NAHBMST-1 := 0;
uhchsindex : integer range 0 to NAHBSLV-1 := 0;
uhchaddr : integer range 0 to 16#FFF# := 0;
uhchmask : integer range 0 to 16#FFF# := 16#FFF#;
uhchirq : integer range 0 to NAHBIRQ-1 := 0;
tech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer := 3;
netlist : integer range 0 to 1 := 0;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 0;
oepol : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
memsel : integer := 0;
syncprst : integer range 0 to 1 := 0;
sysfreq : integer := 65000;
pcidev : integer range 0 to 1 := 0;
debug : integer := 0;
debugsize : integer := 8192);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
apbi : in apb_slv_in_type;
ehc_apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ehc_ahbmo : out ahb_mst_out_type;
uhc_ahbmo : out ahb_mst_out_vector_type(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso : out ahb_slv_out_vector_type(n_cc*uhcgen downto 1*uhcgen);
o : out grusb_out_vector((nports-1) downto 0);
i : in grusb_in_vector((nports-1) downto 0));
end component;
component grusbdc is
generic (
hsindex : integer range 0 to NAHBSLV-1 := 0;
hirq : integer range 0 to NAHBIRQ-1 := 0;
haddr : integer := 0;
hmask : integer := 16#FFF#;
hmindex : integer range 0 to NAHBMST-1 := 0;
aiface : integer range 0 to 1 := 0;
memtech : integer range 0 to NTECH := DEFMEMTECH;
uiface : integer range 0 to 1 := 0;
dwidth : integer range 8 to 16 := 8;
blen : integer range 4 to 128 := 16;
nepi : integer range 1 to 16 := 1;
nepo : integer range 1 to 16 := 1;
i0 : integer range 8 to 3072 := 1024;
i1 : integer range 8 to 3072 := 1024;
i2 : integer range 8 to 3072 := 1024;
i3 : integer range 8 to 3072 := 1024;
i4 : integer range 8 to 3072 := 1024;
i5 : integer range 8 to 3072 := 1024;
i6 : integer range 8 to 3072 := 1024;
i7 : integer range 8 to 3072 := 1024;
i8 : integer range 8 to 3072 := 1024;
i9 : integer range 8 to 3072 := 1024;
i10 : integer range 8 to 3072 := 1024;
i11 : integer range 8 to 3072 := 1024;
i12 : integer range 8 to 3072 := 1024;
i13 : integer range 8 to 3072 := 1024;
i14 : integer range 8 to 3072 := 1024;
i15 : integer range 8 to 3072 := 1024;
o0 : integer range 8 to 3072 := 1024;
o1 : integer range 8 to 3072 := 1024;
o2 : integer range 8 to 3072 := 1024;
o3 : integer range 8 to 3072 := 1024;
o4 : integer range 8 to 3072 := 1024;
o5 : integer range 8 to 3072 := 1024;
o6 : integer range 8 to 3072 := 1024;
o7 : integer range 8 to 3072 := 1024;
o8 : integer range 8 to 3072 := 1024;
o9 : integer range 8 to 3072 := 1024;
o10 : integer range 8 to 3072 := 1024;
o11 : integer range 8 to 3072 := 1024;
o12 : integer range 8 to 3072 := 1024;
o13 : integer range 8 to 3072 := 1024;
o14 : integer range 8 to 3072 := 1024;
o15 : integer range 8 to 3072 := 1024;
oepol : integer range 0 to 1 := 0;
syncprst : integer range 0 to 1 := 0;
prsttime : integer range 0 to 512 := 0;
sysfreq : integer := 50000;
keepclk : integer range 0 to 1 := 0;
sepirq : integer range 0 to 1 := 0;
irqi : integer range 0 to NAHBIRQ-1 := 1;
irqo : integer range 0 to NAHBIRQ-1 := 2;
functesten : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 1);
port (
uclk : in std_ulogic;
usbi : in grusb_in_type;
usbo : out grusb_out_type;
hclk : in std_ulogic;
hrst : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component grusb_dcl is
generic (
hindex : integer := 0;
memtech : integer := DEFMEMTECH;
uiface : integer range 0 to 1 := 0;
dwidth : integer range 8 to 16 := 8;
oepol : integer range 0 to 1 := 0;
syncprst : integer range 0 to 1 := 0;
prsttime : integer range 0 to 512 := 0;
sysfreq : integer := 50000;
keepclk : integer range 0 to 1 := 0;
functesten : integer range 0 to 1 := 0;
burstlength: integer range 1 to 512 := 8;
scantest : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 1
);
port (
uclk : in std_ulogic;
usbi : in grusb_in_type;
usbo : out grusb_out_type;
hclk : in std_ulogic;
hrst : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component grusb_dcl;
component grusbhc_gen is
generic (
tech : integer := 0;
memtech : integer := 0;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer := 3;
netlist : integer range 0 to 1 := 0;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 0;
oepol : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
memsel : integer := 0;
syncprst : integer range 0 to 1 := 0;
sysfreq : integer := 65000;
pcidev : integer range 0 to 1 := 0;
debug : integer := 0;
debugsize : integer := 8192);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
-- EHC APB slave input signals
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
-- EHC APB slave output signals
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_irq : out std_ulogic;
-- EHC/UHC(s) AHB master input signals
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
-- UHC(s) AHB slave input signals
uhc_ahbsi_hsel : in std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
-- EHC AHB master output signals
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC(s) AHB master output signals
uhc_ahbmo_hbusreq : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbmo_hlock : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbmo_htrans : out std_logic_vector(((n_cc*2)-1)*uhcgen downto 0);
uhc_ahbmo_haddr : out std_logic_vector(((n_cc*32)-1)*uhcgen downto 0);
uhc_ahbmo_hwrite : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbmo_hsize : out std_logic_vector(((n_cc*3)-1)*uhcgen downto 0);
uhc_ahbmo_hburst : out std_logic_vector(((n_cc*3)-1)*uhcgen downto 0);
uhc_ahbmo_hprot : out std_logic_vector(((n_cc*4)-1)*uhcgen downto 0);
uhc_ahbmo_hwdata : out std_logic_vector(((n_cc*32)-1)*uhcgen downto 0);
-- UHC(s) AHB slave output signals
uhc_ahbso_hready : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbso_hresp : out std_logic_vector(((n_cc*2)-1)*uhcgen downto 0);
uhc_ahbso_hrdata : out std_logic_vector(((n_cc*32)-1)*uhcgen downto 0);
uhc_ahbso_hsplit : out std_logic_vector(((n_cc*NAHBMST)-1)*uhcgen downto 0);
uhc_irq : out std_logic_vector((n_cc-1)*uhcgen downto 0);
-- ULPI/UTMI+ output signals
xcvrselect : out std_logic_vector(((nports*2)-1) downto 0);
termselect : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataout : out std_logic_vector(((nports*16)-1) downto 0);
txvalidh : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
reset : out std_logic_vector((nports-1) downto 0);
oen : out std_logic_vector((nports-1) downto 0);
suspendm : out std_ulogic;
databus16_8 : out std_ulogic;
dppulldown : out std_ulogic;
dmpulldown : out std_ulogic;
idpullup : out std_ulogic;
dischrgvbus : out std_ulogic;
chrgvbus : out std_ulogic;
txbitstuffenable : out std_ulogic;
txbitstuffenableh : out std_ulogic;
fslsserialmode : out std_ulogic;
tx_enable_n : out std_ulogic;
tx_dat : out std_ulogic;
tx_se0 : out std_ulogic;
-- ULPI/UTMI+ input signals
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datain : in std_logic_vector(((nports*16)-1) downto 0);
rxvalidh : in std_logic_vector((nports-1) downto 0);
hostdisconnect : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
urstdrive : in std_logic_vector((nports-1) downto 0);
-- scan signals
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component grusbdc_gen is
generic (
aiface : integer range 0 to 1 := 0;
memtech : integer range 0 to NTECH := DEFMEMTECH;
uiface : integer range 0 to 1 := 0;
dwidth : integer range 8 to 16 := 8;
blen : integer range 4 to 128 := 16;
nepi : integer range 1 to 16 := 1;
nepo : integer range 1 to 16 := 1;
i0 : integer range 8 to 3072 := 1024;
i1 : integer range 8 to 3072 := 1024;
i2 : integer range 8 to 3072 := 1024;
i3 : integer range 8 to 3072 := 1024;
i4 : integer range 8 to 3072 := 1024;
i5 : integer range 8 to 3072 := 1024;
i6 : integer range 8 to 3072 := 1024;
i7 : integer range 8 to 3072 := 1024;
i8 : integer range 8 to 3072 := 1024;
i9 : integer range 8 to 3072 := 1024;
i10 : integer range 8 to 3072 := 1024;
i11 : integer range 8 to 3072 := 1024;
i12 : integer range 8 to 3072 := 1024;
i13 : integer range 8 to 3072 := 1024;
i14 : integer range 8 to 3072 := 1024;
i15 : integer range 8 to 3072 := 1024;
o0 : integer range 8 to 3072 := 1024;
o1 : integer range 8 to 3072 := 1024;
o2 : integer range 8 to 3072 := 1024;
o3 : integer range 8 to 3072 := 1024;
o4 : integer range 8 to 3072 := 1024;
o5 : integer range 8 to 3072 := 1024;
o6 : integer range 8 to 3072 := 1024;
o7 : integer range 8 to 3072 := 1024;
o8 : integer range 8 to 3072 := 1024;
o9 : integer range 8 to 3072 := 1024;
o10 : integer range 8 to 3072 := 1024;
o11 : integer range 8 to 3072 := 1024;
o12 : integer range 8 to 3072 := 1024;
o13 : integer range 8 to 3072 := 1024;
o14 : integer range 8 to 3072 := 1024;
o15 : integer range 8 to 3072 := 1024;
oepol : integer range 0 to 1 := 0;
syncprst : integer range 0 to 1 := 0;
prsttime : integer range 0 to 512 := 0;
sysfreq : integer := 50000;
keepclk : integer range 0 to 1 := 0;
sepirq : integer range 0 to 1 := 0;
functesten : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 1);
port (
-- usb clock
uclk : in std_ulogic;
--usb in signals
datain : in std_logic_vector(15 downto 0);
rxactive : in std_ulogic;
rxvalid : in std_ulogic;
rxvalidh : in std_ulogic;
rxerror : in std_ulogic;
txready : in std_ulogic;
linestate : in std_logic_vector(1 downto 0);
nxt : in std_ulogic;
dir : in std_ulogic;
vbusvalid : in std_ulogic;
urstdrive : in std_ulogic;
--usb out signals
dataout : out std_logic_vector(15 downto 0);
txvalid : out std_ulogic;
txvalidh : out std_ulogic;
opmode : out std_logic_vector(1 downto 0);
xcvrselect : out std_logic_vector(1 downto 0);
termselect : out std_ulogic;
suspendm : out std_ulogic;
reset : out std_ulogic;
stp : out std_ulogic;
oen : out std_ulogic;
databus16_8 : out std_ulogic;
dppulldown : out std_ulogic;
dmpulldown : out std_ulogic;
idpullup : out std_ulogic;
drvvbus : out std_ulogic;
dischrgvbus : out std_ulogic;
chrgvbus : out std_ulogic;
txbitstuffenable : out std_ulogic;
txbitstuffenableh : out std_ulogic;
fslsserialmode : out std_ulogic;
tx_enable_n : out std_ulogic;
tx_dat : out std_ulogic;
tx_se0 : out std_ulogic;
-- amba clock/rst
hclk : in std_ulogic;
hrst : in std_ulogic;
--ahb master in signals
ahbmi_hgrant : in std_ulogic;
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
--ahb master out signals
ahbmo_hbusreq : out std_ulogic;
ahbmo_hlock : out std_ulogic;
ahbmo_htrans : out std_logic_vector(1 downto 0);
ahbmo_haddr : out std_logic_vector(31 downto 0);
ahbmo_hwrite : out std_ulogic;
ahbmo_hsize : out std_logic_vector(2 downto 0);
ahbmo_hburst : out std_logic_vector(2 downto 0);
ahbmo_hprot : out std_logic_vector(3 downto 0);
ahbmo_hwdata : out std_logic_vector(31 downto 0);
--ahb slave in signals
ahbsi_hsel : in std_ulogic;
ahbsi_haddr : in std_logic_vector(31 downto 0);
ahbsi_hwrite : in std_ulogic;
ahbsi_htrans : in std_logic_vector(1 downto 0);
ahbsi_hsize : in std_logic_vector(2 downto 0);
ahbsi_hburst : in std_logic_vector(2 downto 0);
ahbsi_hwdata : in std_logic_vector(31 downto 0);
ahbsi_hprot : in std_logic_vector(3 downto 0);
ahbsi_hready : in std_ulogic;
ahbsi_hmaster : in std_logic_vector(3 downto 0);
ahbsi_hmastlock : in std_ulogic;
--ahb slave out signals
ahbso_hready : out std_ulogic;
ahbso_hresp : out std_logic_vector(1 downto 0);
ahbso_hrdata : out std_logic_vector(31 downto 0);
ahbso_hsplit : out std_logic_vector(NAHBMST-1 downto 0);
-- misc
irq : out std_logic_vector(2*sepirq downto 0);
-- scan signals
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
end grusb;
|
-- loopfilter.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity loopfilter is
port(clk, reset: in std_logic;
mult_error_op:in signed(38 downto 0);
f_desired: in unsigned(5 downto 0);
f_word_output: out unsigned(5 downto 0));
end loopfilter;
architecture loopfilter_arch of loopfilter is
signal beta_e, alpha_e: signed(45 downto 0);
constant alpha: signed(7 downto 0) := "01110011";
constant beta: signed(7 downto 0) := "00011010";
constant plus_one: signed(alpha_e'range) := ('0', others => '1');
component q_one_dot_fp_multiplier is
generic (a_word_size, b_word_size:integer);
port(a: in signed(a_word_size-1 downto 0);
b: in signed(b_word_size-1 downto 0);
mult_out: out signed(a_word_size + b_word_size -2 downto 0));
end component;
begin
M0: q_one_dot_fp_multiplier generic map(a_word_size => beta'length, b_word_size => mult_error_op'length)
port map(beta, mult_error_op,beta_e );
M1: q_one_dot_fp_multiplier generic map(a_word_size => alpha'length, b_word_size => mult_error_op'length)
port map(alpha, mult_error_op, alpha_e);
ADDERS : process(clk, reset)
variable freq_add_var : signed(beta_e'range);
variable n_total_var: signed(alpha_e'range);
variable temp: signed(n_total_var'range);
begin
if reset = '1' then
freq_add_var := (others => '0');
freq_add_var(42 downto 37) := signed(std_logic_vector(f_desired));
n_total_var := (others => '0');
elsif rising_edge(clk) then
freq_add_var := freq_add_var + beta_e;
n_total_var := freq_add_var + alpha_e;
end if;
if n_total_var(n_total_var'length -1) = '1' then
temp := plus_one + n_total_var;
else
temp := n_total_var;
end if;
f_word_output <= unsigned(temp(42 downto 37));
end process;
end loopfilter_arch;
|
-- loopfilter.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity loopfilter is
port(clk, reset: in std_logic;
mult_error_op:in signed(38 downto 0);
f_desired: in unsigned(5 downto 0);
f_word_output: out unsigned(5 downto 0));
end loopfilter;
architecture loopfilter_arch of loopfilter is
signal beta_e, alpha_e: signed(45 downto 0);
constant alpha: signed(7 downto 0) := "01110011";
constant beta: signed(7 downto 0) := "00011010";
constant plus_one: signed(alpha_e'range) := ('0', others => '1');
component q_one_dot_fp_multiplier is
generic (a_word_size, b_word_size:integer);
port(a: in signed(a_word_size-1 downto 0);
b: in signed(b_word_size-1 downto 0);
mult_out: out signed(a_word_size + b_word_size -2 downto 0));
end component;
begin
M0: q_one_dot_fp_multiplier generic map(a_word_size => beta'length, b_word_size => mult_error_op'length)
port map(beta, mult_error_op,beta_e );
M1: q_one_dot_fp_multiplier generic map(a_word_size => alpha'length, b_word_size => mult_error_op'length)
port map(alpha, mult_error_op, alpha_e);
ADDERS : process(clk, reset)
variable freq_add_var : signed(beta_e'range);
variable n_total_var: signed(alpha_e'range);
variable temp: signed(n_total_var'range);
begin
if reset = '1' then
freq_add_var := (others => '0');
freq_add_var(42 downto 37) := signed(std_logic_vector(f_desired));
n_total_var := (others => '0');
elsif rising_edge(clk) then
freq_add_var := freq_add_var + beta_e;
n_total_var := freq_add_var + alpha_e;
end if;
if n_total_var(n_total_var'length -1) = '1' then
temp := plus_one + n_total_var;
else
temp := n_total_var;
end if;
f_word_output <= unsigned(temp(42 downto 37));
end process;
end loopfilter_arch;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 24 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 32,
C_DOUT_WIDTH => 32,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : TX_SEND_FIFO_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (0 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(0 DOWNTO 0):= hex_to_std_logic_vector("0",1);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (24319 downto 0) of std_logic_vector(0 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(0 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"char_mem.mif",
DEFAULT_DATA,
1,
24320);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>24320 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(14 DOWNTO 0) <= READ_ADDR(14 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 24320 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (0 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(0 DOWNTO 0):= hex_to_std_logic_vector("0",1);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (24319 downto 0) of std_logic_vector(0 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(0 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"char_mem.mif",
DEFAULT_DATA,
1,
24320);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>24320 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(14 DOWNTO 0) <= READ_ADDR(14 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 24320 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "encoder_module"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.encoder_module_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity encoder_module_tb is
end encoder_module_tb;
-------------------------------------------------------------------------------
architecture tb of encoder_module_tb is
-- component generics
constant BASE_ADDRESS : positive := 16#0100#;
-- component ports
signal encoder : encoder_type := ('0', '0');
signal index : std_logic := '0';
signal load : std_logic := '0';
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal clk : std_logic := '0';
begin
-- component instantiation
DUT : encoder_module
generic map (
BASE_ADDRESS => BASE_ADDRESS)
port map (
encoder_p => encoder,
index_p => index,
load_p => load,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- clock generation
clk <= not clk after 10 NS;
waveform : process
begin
wait for 20 NS;
for i in 1 to 3 loop
wait until rising_edge(clk);
encoder.a <= '1';
wait until rising_edge(clk);
encoder.b <= '1';
wait until rising_edge(clk);
encoder.a <= '0';
wait until rising_edge(clk);
encoder.b <= '0';
wait until rising_edge(clk);
end loop; -- i
wait for 50 NS;
-- wrong address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0020", bus_i.addr'length)));
bus_i.data <= x"0000";
bus_i.re <= '1';
wait until rising_edge(clk);
bus_i.re <= '0';
wait for 30 NS;
-- correct address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"0000";
bus_i.re <= '1';
wait until rising_edge(clk);
bus_i.re <= '0';
wait for 30 NS;
wait until rising_edge(clk);
load <= '1';
wait until rising_edge(clk);
load <= '0';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"0000";
bus_i.re <= '1';
wait until rising_edge(clk);
bus_i.re <= '0';
wait until rising_edge(clk);
-- generate two read cycles directly following each other
bus_i.re <= '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
bus_i.re <= '0';
-- wrong address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0110", bus_i.addr'length)));
bus_i.data <= x"0000";
bus_i.re <= '1';
wait until rising_edge(clk);
bus_i.re <= '0';
end process waveform;
end tb;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "encoder_module"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.encoder_module_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity encoder_module_tb is
end encoder_module_tb;
-------------------------------------------------------------------------------
architecture tb of encoder_module_tb is
-- component generics
constant BASE_ADDRESS : positive := 16#0100#;
-- component ports
signal encoder : encoder_type := ('0', '0');
signal index : std_logic := '0';
signal load : std_logic := '0';
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal clk : std_logic := '0';
begin
-- component instantiation
DUT : encoder_module
generic map (
BASE_ADDRESS => BASE_ADDRESS)
port map (
encoder_p => encoder,
index_p => index,
load_p => load,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- clock generation
clk <= not clk after 10 NS;
waveform : process
begin
wait for 20 NS;
for i in 1 to 3 loop
wait until rising_edge(clk);
encoder.a <= '1';
wait until rising_edge(clk);
encoder.b <= '1';
wait until rising_edge(clk);
encoder.a <= '0';
wait until rising_edge(clk);
encoder.b <= '0';
wait until rising_edge(clk);
end loop; -- i
wait for 50 NS;
-- wrong address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0020", bus_i.addr'length)));
bus_i.data <= x"0000";
bus_i.re <= '1';
wait until rising_edge(clk);
bus_i.re <= '0';
wait for 30 NS;
-- correct address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"0000";
bus_i.re <= '1';
wait until rising_edge(clk);
bus_i.re <= '0';
wait for 30 NS;
wait until rising_edge(clk);
load <= '1';
wait until rising_edge(clk);
load <= '0';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"0000";
bus_i.re <= '1';
wait until rising_edge(clk);
bus_i.re <= '0';
wait until rising_edge(clk);
-- generate two read cycles directly following each other
bus_i.re <= '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
bus_i.re <= '0';
-- wrong address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0110", bus_i.addr'length)));
bus_i.data <= x"0000";
bus_i.re <= '1';
wait until rising_edge(clk);
bus_i.re <= '0';
end process waveform;
end tb;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Mon May 22 02:50:48 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
clk_100 : in STD_LOGIC;
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
resend : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=5,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_vga_color_test_0_0 is
port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_color_test_0_0;
component system_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_xlconstant_0_0;
component system_vga_pll_0_0 is
port (
clk_100 : in STD_LOGIC;
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC
);
end component system_vga_pll_0_0;
component system_vga_sync_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_0_0;
component system_zed_hdmi_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
end component system_zed_hdmi_0_0;
signal Net : STD_LOGIC;
signal clk_100_1 : STD_LOGIC;
signal resend_1 : STD_LOGIC;
signal vdd_dout : STD_LOGIC_VECTOR ( 0 to 0 );
signal vga_color_test_0_rgb : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_pll_0_clk_25 : STD_LOGIC;
signal vga_pll_0_clk_50 : STD_LOGIC;
signal vga_sync_0_active : STD_LOGIC;
signal vga_sync_0_hsync : STD_LOGIC;
signal vga_sync_0_vsync : STD_LOGIC;
signal vga_sync_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal zed_hdmi_0_hdmi_clk : STD_LOGIC;
signal zed_hdmi_0_hdmi_d : STD_LOGIC_VECTOR ( 15 downto 0 );
signal zed_hdmi_0_hdmi_de : STD_LOGIC;
signal zed_hdmi_0_hdmi_hsync : STD_LOGIC;
signal zed_hdmi_0_hdmi_scl : STD_LOGIC;
signal zed_hdmi_0_hdmi_vsync : STD_LOGIC;
signal NLW_vga_pll_0_clk_12_5_UNCONNECTED : STD_LOGIC;
signal NLW_vga_pll_0_clk_6_25_UNCONNECTED : STD_LOGIC;
begin
clk_100_1 <= clk_100;
hdmi_clk <= zed_hdmi_0_hdmi_clk;
hdmi_d(15 downto 0) <= zed_hdmi_0_hdmi_d(15 downto 0);
hdmi_de <= zed_hdmi_0_hdmi_de;
hdmi_hsync <= zed_hdmi_0_hdmi_hsync;
hdmi_scl <= zed_hdmi_0_hdmi_scl;
hdmi_vsync <= zed_hdmi_0_hdmi_vsync;
resend_1 <= resend;
vdd: component system_xlconstant_0_0
port map (
dout(0) => vdd_dout(0)
);
vga_color_test_0: component system_vga_color_test_0_0
port map (
clk_25 => vga_pll_0_clk_25,
rgb(23 downto 0) => vga_color_test_0_rgb(23 downto 0),
xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0)
);
vga_pll_0: component system_vga_pll_0_0
port map (
clk_100 => clk_100_1,
clk_12_5 => NLW_vga_pll_0_clk_12_5_UNCONNECTED,
clk_25 => vga_pll_0_clk_25,
clk_50 => vga_pll_0_clk_50,
clk_6_25 => NLW_vga_pll_0_clk_6_25_UNCONNECTED
);
vga_sync_0: component system_vga_sync_0_0
port map (
active => vga_sync_0_active,
clk => vga_pll_0_clk_25,
hsync => vga_sync_0_hsync,
rst => vdd_dout(0),
vsync => vga_sync_0_vsync,
xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0)
);
zed_hdmi_0: component system_zed_hdmi_0_0
port map (
active => vga_sync_0_active,
clk => vga_pll_0_clk_25,
clk_100 => clk_100_1,
clk_x2 => vga_pll_0_clk_50,
hdmi_clk => zed_hdmi_0_hdmi_clk,
hdmi_d(15 downto 0) => zed_hdmi_0_hdmi_d(15 downto 0),
hdmi_de => zed_hdmi_0_hdmi_de,
hdmi_hsync => zed_hdmi_0_hdmi_hsync,
hdmi_scl => zed_hdmi_0_hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => zed_hdmi_0_hdmi_vsync,
hsync => vga_sync_0_hsync,
rgb888(23 downto 0) => vga_color_test_0_rgb(23 downto 0),
vsync => vga_sync_0_vsync
);
end STRUCTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2383.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p06n02i02383ent IS
END c07s03b02x00p06n02i02383ent;
ARCHITECTURE c07s03b02x00p06n02i02383arch OF c07s03b02x00p06n02i02383ent IS
BEGIN
TESTING: PROCESS
-- Declare ascending and descending ranges.
subtype BYTE is BIT_VECTOR( 0 to 7 );
type NIBBLE is ARRAY ( 3 downto 0 ) of BIT;
-- Declare array variables of these types.
variable BYTEV1 : BYTE;
variable BYTEV2 : BYTE;
variable NIBV1 : NIBBLE;
variable NIBV2 : NIBBLE;
BEGIN
-- Set their values with aggregates and check them.
-- 1. Ascending first.
BYTEV1 := BYTE'( 7 => '0', others => '1' );
assert( BYTEV1( 0 ) = '1' );
assert( BYTEV1( 1 ) = '1' );
assert( BYTEV1( 2 ) = '1' );
assert( BYTEV1( 3 ) = '1' );
assert( BYTEV1( 4 ) = '1' );
assert( BYTEV1( 5 ) = '1' );
assert( BYTEV1( 6 ) = '1' );
assert( BYTEV1( 7 ) = '0' );
BYTEV2 := BYTE'( 7 => '1', 0 to 6 => '0' );
assert( BYTEV2( 0 ) = '0' );
assert( BYTEV2( 1 ) = '0' );
assert( BYTEV2( 2 ) = '0' );
assert( BYTEV2( 3 ) = '0' );
assert( BYTEV2( 4 ) = '0' );
assert( BYTEV2( 5 ) = '0' );
assert( BYTEV2( 6 ) = '0' );
assert( BYTEV2( 7 ) = '1' );
-- 2. Descending next.
NIBV1 := NIBBLE'( 3 downto 1 => '1', 0 downto 0 => '0' );
assert( NIBV1( 3 ) = '1' );
assert( NIBV1( 2 ) = '1' );
assert( NIBV1( 1 ) = '1' );
assert( NIBV1( 0 ) = '0' );
NIBV2 := NIBBLE'( 1 to 3 => '0', 0 downto 0 => '1' );
assert( NIBV2( 3 ) = '0' );
assert( NIBV2( 2 ) = '0' );
assert( NIBV2( 1 ) = '0' );
assert( NIBV2( 0 ) = '1' );
wait for 5 ns;
assert NOT( ( BYTEV1( 0 ) = '1' ) and
( BYTEV1( 1 ) = '1' ) and
( BYTEV1( 2 ) = '1' ) and
( BYTEV1( 3 ) = '1' ) and
( BYTEV1( 4 ) = '1' ) and
( BYTEV1( 5 ) = '1' ) and
( BYTEV1( 6 ) = '1' ) and
( BYTEV1( 7 ) = '0' ) and
( BYTEV2( 0 ) = '0' ) and
( BYTEV2( 1 ) = '0' ) and
( BYTEV2( 2 ) = '0' ) and
( BYTEV2( 3 ) = '0' ) and
( BYTEV2( 4 ) = '0' ) and
( BYTEV2( 5 ) = '0' ) and
( BYTEV2( 6 ) = '0' ) and
( BYTEV2( 7 ) = '1' ) and
( NIBV1( 3 ) = '1' ) and
( NIBV1( 2 ) = '1' ) and
( NIBV1( 1 ) = '1' ) and
( NIBV1( 0 ) = '0' ) and
( NIBV2( 3 ) = '0' ) and
( NIBV2( 2 ) = '0' ) and
( NIBV2( 1 ) = '0' ) and
( NIBV2( 0 ) = '1' ) )
report "***PASSED TEST: c07s03b02x00p06n02i02383"
severity NOTE;
assert ( ( BYTEV1( 0 ) = '1' ) and
( BYTEV1( 1 ) = '1' ) and
( BYTEV1( 2 ) = '1' ) and
( BYTEV1( 3 ) = '1' ) and
( BYTEV1( 4 ) = '1' ) and
( BYTEV1( 5 ) = '1' ) and
( BYTEV1( 6 ) = '1' ) and
( BYTEV1( 7 ) = '0' ) and
( BYTEV2( 0 ) = '0' ) and
( BYTEV2( 1 ) = '0' ) and
( BYTEV2( 2 ) = '0' ) and
( BYTEV2( 3 ) = '0' ) and
( BYTEV2( 4 ) = '0' ) and
( BYTEV2( 5 ) = '0' ) and
( BYTEV2( 6 ) = '0' ) and
( BYTEV2( 7 ) = '1' ) and
( NIBV1( 3 ) = '1' ) and
( NIBV1( 2 ) = '1' ) and
( NIBV1( 1 ) = '1' ) and
( NIBV1( 0 ) = '0' ) and
( NIBV2( 3 ) = '0' ) and
( NIBV2( 2 ) = '0' ) and
( NIBV2( 1 ) = '0' ) and
( NIBV2( 0 ) = '1' ) )
report "***FAILED TEST: c07s03b02x00p06n02i02383 - Named association assignment test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p06n02i02383arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2383.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p06n02i02383ent IS
END c07s03b02x00p06n02i02383ent;
ARCHITECTURE c07s03b02x00p06n02i02383arch OF c07s03b02x00p06n02i02383ent IS
BEGIN
TESTING: PROCESS
-- Declare ascending and descending ranges.
subtype BYTE is BIT_VECTOR( 0 to 7 );
type NIBBLE is ARRAY ( 3 downto 0 ) of BIT;
-- Declare array variables of these types.
variable BYTEV1 : BYTE;
variable BYTEV2 : BYTE;
variable NIBV1 : NIBBLE;
variable NIBV2 : NIBBLE;
BEGIN
-- Set their values with aggregates and check them.
-- 1. Ascending first.
BYTEV1 := BYTE'( 7 => '0', others => '1' );
assert( BYTEV1( 0 ) = '1' );
assert( BYTEV1( 1 ) = '1' );
assert( BYTEV1( 2 ) = '1' );
assert( BYTEV1( 3 ) = '1' );
assert( BYTEV1( 4 ) = '1' );
assert( BYTEV1( 5 ) = '1' );
assert( BYTEV1( 6 ) = '1' );
assert( BYTEV1( 7 ) = '0' );
BYTEV2 := BYTE'( 7 => '1', 0 to 6 => '0' );
assert( BYTEV2( 0 ) = '0' );
assert( BYTEV2( 1 ) = '0' );
assert( BYTEV2( 2 ) = '0' );
assert( BYTEV2( 3 ) = '0' );
assert( BYTEV2( 4 ) = '0' );
assert( BYTEV2( 5 ) = '0' );
assert( BYTEV2( 6 ) = '0' );
assert( BYTEV2( 7 ) = '1' );
-- 2. Descending next.
NIBV1 := NIBBLE'( 3 downto 1 => '1', 0 downto 0 => '0' );
assert( NIBV1( 3 ) = '1' );
assert( NIBV1( 2 ) = '1' );
assert( NIBV1( 1 ) = '1' );
assert( NIBV1( 0 ) = '0' );
NIBV2 := NIBBLE'( 1 to 3 => '0', 0 downto 0 => '1' );
assert( NIBV2( 3 ) = '0' );
assert( NIBV2( 2 ) = '0' );
assert( NIBV2( 1 ) = '0' );
assert( NIBV2( 0 ) = '1' );
wait for 5 ns;
assert NOT( ( BYTEV1( 0 ) = '1' ) and
( BYTEV1( 1 ) = '1' ) and
( BYTEV1( 2 ) = '1' ) and
( BYTEV1( 3 ) = '1' ) and
( BYTEV1( 4 ) = '1' ) and
( BYTEV1( 5 ) = '1' ) and
( BYTEV1( 6 ) = '1' ) and
( BYTEV1( 7 ) = '0' ) and
( BYTEV2( 0 ) = '0' ) and
( BYTEV2( 1 ) = '0' ) and
( BYTEV2( 2 ) = '0' ) and
( BYTEV2( 3 ) = '0' ) and
( BYTEV2( 4 ) = '0' ) and
( BYTEV2( 5 ) = '0' ) and
( BYTEV2( 6 ) = '0' ) and
( BYTEV2( 7 ) = '1' ) and
( NIBV1( 3 ) = '1' ) and
( NIBV1( 2 ) = '1' ) and
( NIBV1( 1 ) = '1' ) and
( NIBV1( 0 ) = '0' ) and
( NIBV2( 3 ) = '0' ) and
( NIBV2( 2 ) = '0' ) and
( NIBV2( 1 ) = '0' ) and
( NIBV2( 0 ) = '1' ) )
report "***PASSED TEST: c07s03b02x00p06n02i02383"
severity NOTE;
assert ( ( BYTEV1( 0 ) = '1' ) and
( BYTEV1( 1 ) = '1' ) and
( BYTEV1( 2 ) = '1' ) and
( BYTEV1( 3 ) = '1' ) and
( BYTEV1( 4 ) = '1' ) and
( BYTEV1( 5 ) = '1' ) and
( BYTEV1( 6 ) = '1' ) and
( BYTEV1( 7 ) = '0' ) and
( BYTEV2( 0 ) = '0' ) and
( BYTEV2( 1 ) = '0' ) and
( BYTEV2( 2 ) = '0' ) and
( BYTEV2( 3 ) = '0' ) and
( BYTEV2( 4 ) = '0' ) and
( BYTEV2( 5 ) = '0' ) and
( BYTEV2( 6 ) = '0' ) and
( BYTEV2( 7 ) = '1' ) and
( NIBV1( 3 ) = '1' ) and
( NIBV1( 2 ) = '1' ) and
( NIBV1( 1 ) = '1' ) and
( NIBV1( 0 ) = '0' ) and
( NIBV2( 3 ) = '0' ) and
( NIBV2( 2 ) = '0' ) and
( NIBV2( 1 ) = '0' ) and
( NIBV2( 0 ) = '1' ) )
report "***FAILED TEST: c07s03b02x00p06n02i02383 - Named association assignment test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p06n02i02383arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2383.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p06n02i02383ent IS
END c07s03b02x00p06n02i02383ent;
ARCHITECTURE c07s03b02x00p06n02i02383arch OF c07s03b02x00p06n02i02383ent IS
BEGIN
TESTING: PROCESS
-- Declare ascending and descending ranges.
subtype BYTE is BIT_VECTOR( 0 to 7 );
type NIBBLE is ARRAY ( 3 downto 0 ) of BIT;
-- Declare array variables of these types.
variable BYTEV1 : BYTE;
variable BYTEV2 : BYTE;
variable NIBV1 : NIBBLE;
variable NIBV2 : NIBBLE;
BEGIN
-- Set their values with aggregates and check them.
-- 1. Ascending first.
BYTEV1 := BYTE'( 7 => '0', others => '1' );
assert( BYTEV1( 0 ) = '1' );
assert( BYTEV1( 1 ) = '1' );
assert( BYTEV1( 2 ) = '1' );
assert( BYTEV1( 3 ) = '1' );
assert( BYTEV1( 4 ) = '1' );
assert( BYTEV1( 5 ) = '1' );
assert( BYTEV1( 6 ) = '1' );
assert( BYTEV1( 7 ) = '0' );
BYTEV2 := BYTE'( 7 => '1', 0 to 6 => '0' );
assert( BYTEV2( 0 ) = '0' );
assert( BYTEV2( 1 ) = '0' );
assert( BYTEV2( 2 ) = '0' );
assert( BYTEV2( 3 ) = '0' );
assert( BYTEV2( 4 ) = '0' );
assert( BYTEV2( 5 ) = '0' );
assert( BYTEV2( 6 ) = '0' );
assert( BYTEV2( 7 ) = '1' );
-- 2. Descending next.
NIBV1 := NIBBLE'( 3 downto 1 => '1', 0 downto 0 => '0' );
assert( NIBV1( 3 ) = '1' );
assert( NIBV1( 2 ) = '1' );
assert( NIBV1( 1 ) = '1' );
assert( NIBV1( 0 ) = '0' );
NIBV2 := NIBBLE'( 1 to 3 => '0', 0 downto 0 => '1' );
assert( NIBV2( 3 ) = '0' );
assert( NIBV2( 2 ) = '0' );
assert( NIBV2( 1 ) = '0' );
assert( NIBV2( 0 ) = '1' );
wait for 5 ns;
assert NOT( ( BYTEV1( 0 ) = '1' ) and
( BYTEV1( 1 ) = '1' ) and
( BYTEV1( 2 ) = '1' ) and
( BYTEV1( 3 ) = '1' ) and
( BYTEV1( 4 ) = '1' ) and
( BYTEV1( 5 ) = '1' ) and
( BYTEV1( 6 ) = '1' ) and
( BYTEV1( 7 ) = '0' ) and
( BYTEV2( 0 ) = '0' ) and
( BYTEV2( 1 ) = '0' ) and
( BYTEV2( 2 ) = '0' ) and
( BYTEV2( 3 ) = '0' ) and
( BYTEV2( 4 ) = '0' ) and
( BYTEV2( 5 ) = '0' ) and
( BYTEV2( 6 ) = '0' ) and
( BYTEV2( 7 ) = '1' ) and
( NIBV1( 3 ) = '1' ) and
( NIBV1( 2 ) = '1' ) and
( NIBV1( 1 ) = '1' ) and
( NIBV1( 0 ) = '0' ) and
( NIBV2( 3 ) = '0' ) and
( NIBV2( 2 ) = '0' ) and
( NIBV2( 1 ) = '0' ) and
( NIBV2( 0 ) = '1' ) )
report "***PASSED TEST: c07s03b02x00p06n02i02383"
severity NOTE;
assert ( ( BYTEV1( 0 ) = '1' ) and
( BYTEV1( 1 ) = '1' ) and
( BYTEV1( 2 ) = '1' ) and
( BYTEV1( 3 ) = '1' ) and
( BYTEV1( 4 ) = '1' ) and
( BYTEV1( 5 ) = '1' ) and
( BYTEV1( 6 ) = '1' ) and
( BYTEV1( 7 ) = '0' ) and
( BYTEV2( 0 ) = '0' ) and
( BYTEV2( 1 ) = '0' ) and
( BYTEV2( 2 ) = '0' ) and
( BYTEV2( 3 ) = '0' ) and
( BYTEV2( 4 ) = '0' ) and
( BYTEV2( 5 ) = '0' ) and
( BYTEV2( 6 ) = '0' ) and
( BYTEV2( 7 ) = '1' ) and
( NIBV1( 3 ) = '1' ) and
( NIBV1( 2 ) = '1' ) and
( NIBV1( 1 ) = '1' ) and
( NIBV1( 0 ) = '0' ) and
( NIBV2( 3 ) = '0' ) and
( NIBV2( 2 ) = '0' ) and
( NIBV2( 1 ) = '0' ) and
( NIBV2( 0 ) = '1' ) )
report "***FAILED TEST: c07s03b02x00p06n02i02383 - Named association assignment test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p06n02i02383arch;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : floppy.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity floppy is
generic (
g_big_endian : boolean;
g_tag : std_logic_vector(7 downto 0) := X"01" );
port (
clock : in std_logic;
reset : in std_logic;
tick_16MHz : in std_logic;
-- signals from MOS 6522 VIA
motor_on : in std_logic;
stepper_en : in std_logic;
mode : in std_logic;
write_prot_n : in std_logic;
side : in std_logic := '0';
step : in std_logic_vector(1 downto 0);
rate_ctrl : in std_logic_vector(1 downto 0);
byte_ready : out std_logic;
sync : out std_logic;
track : out unsigned(6 downto 0);
track_is_0 : out std_logic;
read_data : out std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
-- signals connected to sd-cpu
io_req_param : in t_io_req;
io_resp_param : out t_io_resp;
io_req_dirty : in t_io_req;
io_resp_dirty : out t_io_resp;
floppy_inserted : in std_logic := '0';
do_head_bang : out std_logic;
do_track_out : out std_logic;
do_track_in : out std_logic;
en_hum : out std_logic;
en_slip : out std_logic;
dirty_led_n : out std_logic;
---
mem_req : out t_mem_req;
mem_resp : in t_mem_resp );
end floppy;
architecture structural of floppy is
signal mem_rdata : std_logic_vector(7 downto 0);
signal do_read : std_logic;
signal do_write : std_logic;
signal do_advance : std_logic;
signal track_start : std_logic_vector(25 downto 0);
signal max_offset : std_logic_vector(13 downto 0);
signal track_i : unsigned(6 downto 0);
signal bit_time : unsigned(9 downto 0);
begin
en_hum <= motor_on and not floppy_inserted;
en_slip <= motor_on and floppy_inserted;
track <= track_i;
stream: entity work.floppy_stream
port map (
clock => clock,
reset => reset,
tick_16MHz => tick_16MHz,
mem_rdata => mem_rdata,
do_read => do_read,
do_write => do_write,
do_advance => do_advance,
floppy_inserted => floppy_inserted,
track => track_i,
track_is_0 => track_is_0,
do_head_bang => do_head_bang,
do_track_in => do_track_in,
do_track_out => do_track_out,
motor_on => motor_on,
stepper_en => stepper_en,
sync => sync,
mode => mode,
write_prot_n => write_prot_n,
step => step,
byte_ready => byte_ready,
rate_ctrl => rate_ctrl,
bit_time => bit_time,
read_data => read_data );
params: entity work.floppy_param_mem
generic map (
g_big_endian => g_big_endian )
port map (
clock => clock,
reset => reset,
io_req => io_req_param,
io_resp => io_resp_param,
track => track_i,
side => side,
track_start => track_start,
max_offset => max_offset,
bit_time => bit_time );
fetch_wb: entity work.floppy_mem
generic map (
g_tag => g_tag )
port map (
clock => clock,
reset => reset,
drv_rdata => mem_rdata,
drv_wdata => write_data,
do_read => do_read,
do_write => do_write,
do_advance => do_advance,
track_start => track_start,
max_offset => max_offset,
mem_req => mem_req,
mem_resp => mem_resp );
b_dirty: block
signal any_dirty : std_logic;
signal dirty_bits : std_logic_vector(127 downto 0) := (others => '0');
signal wa : integer range 0 to 127 := 0;
signal wr, wd : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
wa <= to_integer(unsigned(side & track_i(6 downto 1)));
wd <= '1';
wr <= '0';
if mode = '0' and motor_on='1' and floppy_inserted='1' then
wr <= '1';
any_dirty <= '1';
end if;
io_resp_dirty <= c_io_resp_init;
if io_req_dirty.read = '1' then
io_resp_dirty.ack <= '1';
io_resp_dirty.data(7) <= any_dirty;
io_resp_dirty.data(0) <= dirty_bits(to_integer(io_req_dirty.address(6 downto 0)));
end if;
if io_req_dirty.write = '1' then
io_resp_dirty.ack <= '1';
if io_req_dirty.data(7) = '1' then
any_dirty <= '0';
else
wa <= to_integer(io_req_dirty.address(6 downto 0));
wr <= '1';
wd <= '0';
end if;
end if;
if wr = '1' then
dirty_bits(wa) <= wd;
end if;
if reset = '1' then
any_dirty <= '0';
end if;
end if;
end process;
dirty_led_n <= not any_dirty;
end block;
end structural;
|
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY memoryBank IS
GENERIC
(
adressWidth : integer;
memorySize : integer;
wordLength : integer
);
PORT
(
adress : IN std_logic_vector(adressWidth-1 downto 0);
writeBit : IN std_logic; -- if 1 then write input to adressed dword
input : IN std_logic_vector(wordLength-1 downto 0);
output : OUT std_logic_vector(wordLength-1 downto 0) -- value of the selected dword
);
END memoryBank;
ARCHITECTURE behaviour OF memoryBank IS
COMPONENT reg IS
GENERIC
(
width : integer
);
PORT
(
clock : IN std_logic;
change : IN std_logic_vector(width-1 downto 0);
state : OUT std_logic_vector(width-1 downto 0)
);
END COMPONENT;
SUBTYPE cellLane IS std_logic_vector(wordLength-1 downto 0);
TYPE memoryLane IS ARRAY(integer RANGE 0 TO memorySize-1) OF cellLane;
SIGNAL outputLane : memoryLane;
SIGNAL cellWrite : std_logic_vector(memorySize-1 downto 0);
BEGIN
gen0 : FOR X IN 0 TO memorySize-1 GENERATE
regx : reg GENERIC MAP (wordLength) PORT MAP (cellWrite(X),input,outputLane(X)); -- create cells
output <= outputLane(X) WHEN (adress = std_logic_vector(to_unsigned(X, adressWidth))) ELSE (OTHERS => 'Z');
cellWrite(X) <= writeBit WHEN adress = std_logic_vector(to_unsigned(X, adressWidth)) ELSE '0';
END GENERATE;
END behaviour;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "cache_line_streamer"
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : cache_line_streamer_tb.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-12-22
-- Last update: 2016-12-26
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-22 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cache_defs.all;
-------------------------------------------------------------------------------
entity cache_line_streamer_tb is
end entity cache_line_streamer_tb;
-------------------------------------------------------------------------------
architecture test of cache_line_streamer_tb is
-- component generics
constant ADDR_WIDTH : natural := 32;
constant DATA_WIDTH : natural := 32;
constant DATAS_PER_LINE_WIDTH : natural := 3;
constant MEMORY_LATENCY : natural := 3;
-- component ports
signal clk : std_logic := '1';
signal rst : std_logic := '1';
signal i_req : cls_op;
signal creq : cache_request_t;
signal cresp : cache_response_t;
signal o_memory_req : std_logic;
signal o_memory_we : std_logic;
signal o_memory_addr : addr_t;
signal i_memory_rdata : data_t;
signal o_memory_wdata : data_t;
signal i_memory_done : std_logic;
-- clock
signal clkena : std_logic := '1';
signal test_refill_done : boolean := false;
function get_ireq_str(req : cls_op) return string is
begin
case req is
when cls_none => return "none";
when cls_refill => return "refill";
when cls_flush => return "flush";
end case;
end function get_ireq_str;
function cline_to_hstring(cline : cache_line_t;
i : natural) return string is
begin
if i = 0 then
return to_hstring(cline(i));
else
return to_hstring(cline(i)) & ":" & cline_to_hstring(cline, i - 1);
end if;
end function cline_to_hstring;
begin -- architecture test
-- component instantiation
DUT : entity work.cache_line_streamer
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH,
DATAS_PER_LINE_WIDTH => DATAS_PER_LINE_WIDTH)
port map (
clk => clk,
rst => rst,
i_creq => creq,
o_cresp => cresp,
o_memory_req => o_memory_req,
o_memory_we => o_memory_we,
o_memory_addr => o_memory_addr,
i_memory_rdata => i_memory_rdata,
o_memory_wdata => o_memory_wdata,
i_memory_done => i_memory_done);
-- memory simulator
Simulated_Memory_1 : entity work.Simulated_Memory
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH,
MEMORY_ADDR_WIDTH => 16,
MEMORY_LATENCY => MEMORY_LATENCY)
port map (
clk => clk,
rst => rst,
i_memory_req => o_memory_req,
i_memory_we => o_memory_we,
i_memory_addr => o_memory_addr,
i_memory_write_data => o_memory_wdata,
o_memory_read_data => i_memory_rdata,
o_memory_valid => i_memory_done);
-- clock generation
rst <= '0' after 12 ps;
clk <= (clkena and not clk) after 5 ps;
clkena <= '0' after 340 ps;
creq.req <= cls_refill after 28 ps,
cls_none after 35 ps,
cls_flush after 198 ps,
cls_none after 207 ps;
creq.addr <= std_logic_vector(to_unsigned(16#0060#, ADDR_WIDTH)) after 21 ps;
creq.sel <= (6 => '1', 4 => '1', 2 => '1', 0 => '1', others => '0');
creq.cline(6) <= x"66666666";
creq.cline(4) <= x"44444444";
creq.cline(2) <= x"22222222";
creq.cline(0) <= x"00000000";
-- waveform generation
WaveGen_Proc : process
begin
wait until Clk = '1';
if not test_refill_done then
report "i_req=" & get_ireq_str(creq.req) &
", cresp.rdy=" & std_logic'image(cresp.rdy) &
", cresp.done=" & std_logic'image(cresp.done) &
", cresp.cline = " & cline_to_hstring(cresp.cline, cresp.cline'length - 1);
else
report "i_req=" & get_ireq_str(creq.req) &
", cresp.rdy=" & std_logic'image(cresp.rdy) &
", cresp.done=" & std_logic'image(cresp.done) &
", o_memory_req=" & std_logic'image(o_memory_req) &
", o_memory_addr=" & to_hstring(o_memory_addr) &
", o_memory_wdata=" & to_hstring(o_memory_wdata) &
", i_memory_done=" & std_logic'image(i_memory_done);
end if;
end process WaveGen_Proc;
refill_watch : process
begin
wait for 1 ps;
-- wait until NOW = 1 ps;
assert cresp.rdy = '0' report "During reset ready must be 0";
wait until rst = '0';
wait until clk = '1';
wait until clk = '1';
assert cresp.rdy = '1' report "after reset ready must be 1";
wait until clk = '1';
assert cresp.rdy = '0' report "after request ready must be 0";
assert cresp.done = '0' report "after request done must be 0";
wait for (MEMORY_LATENCY * 4 + 2) * 10 ps;
assert cresp.rdy = '1' report "after refilling, ready must be 1";
assert cresp.done = '1' report "after refilling, done must be 1";
-- Expected data: 0x160 + idx * 4
assert cresp.cline(6) = x"00000178"
report "Data at index 7 not refilled correctly";
assert cresp.cline(4) = x"00000170"
report "Data at index 4 not refilled correctly";
assert cresp.cline(2) = x"00000168"
report "Data at index 2 not refilled correctly";
assert cresp.cline(0) = x"00000160"
report "Data at index 0 not refilled correctly";
wait until clk = '1';
assert cresp.rdy = '1' report "while idling, ready must be 1";
wait until clk = '1';
assert cresp.rdy = '1' report "while idling, ready must be 1";
test_refill_done <= true;
wait on rst;
end process refill_watch;
flush_watch : process
begin
wait until test_refill_done = true;
wait until clk = '1';
-- wait until NOW = 1 ps;
assert o_memory_req = '1' report "memory request should be asserted";
assert o_memory_addr = x"00000078" report "memory request target address incorrect";
assert o_memory_wdata = x"66666666" report "memory request wrong data sent";
assert cresp.rdy = '0' report "after request ready must be 1";
assert cresp.done = '0' report "after request done must be 0";
wait for MEMORY_LATENCY * 10 ps;
assert cresp.rdy = '0' report "after request ready must be 1";
assert cresp.done = '0' report "after request done must be 0";
assert o_memory_req = '1' report "memory request should be asserted";
assert o_memory_addr = x"00000070" report "memory request target address incorrect";
assert o_memory_wdata = x"44444444" report "memory request wrong data sent";
wait for MEMORY_LATENCY * 10 ps;
assert cresp.rdy = '0' report "after request ready must be 1";
assert cresp.done = '0' report "after request done must be 0";
assert o_memory_req = '1' report "memory request should be asserted";
assert o_memory_addr = x"00000068" report "memory request target address incorrect";
assert o_memory_wdata = x"22222222" report "memory request wrong data sent";
wait for MEMORY_LATENCY * 10 ps;
assert cresp.rdy = '0' report "after request ready must be 1";
assert cresp.done = '0' report "after request done must be 0";
assert o_memory_req = '1' report "memory request should be asserted";
assert o_memory_addr = x"00000060" report "memory request target address incorrect";
assert o_memory_wdata = x"00000000" report "memory request wrong data sent";
wait for MEMORY_LATENCY * 10 ps;
wait until clk = '1';
wait until clk = '1';
assert cresp.done = '1' report "last request has not completed";
assert cresp.rdy = '1' report "after flushing ready must be 1";
assert cresp.done = '1' report "after flushing, done must be 1";
wait until clk = '1';
wait on rst;
end process flush_watch;
end architecture test;
-------------------------------------------------------------------------------
configuration cache_line_streamer_tb_test_cfg of cache_line_streamer_tb is
for test
end for;
end cache_line_streamer_tb_test_cfg;
-------------------------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1873.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01873ent IS
END c07s01b00x00p08n01i01873ent;
ARCHITECTURE c07s01b00x00p08n01i01873arch OF c07s01b00x00p08n01i01873ent IS
type small_int is range 0 to 7;
BEGIN
TESTING : PROCESS
function value return small_int is
variable tmp : small_int := 0;
begin
case tmp is
when 0 => tmp := 0;
when others => tmp := 1;
end case;
return TESTING; -- process labels illegal here
end value;
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01873d - Process labels are not permitted as primaries in a function return expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01873arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1873.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01873ent IS
END c07s01b00x00p08n01i01873ent;
ARCHITECTURE c07s01b00x00p08n01i01873arch OF c07s01b00x00p08n01i01873ent IS
type small_int is range 0 to 7;
BEGIN
TESTING : PROCESS
function value return small_int is
variable tmp : small_int := 0;
begin
case tmp is
when 0 => tmp := 0;
when others => tmp := 1;
end case;
return TESTING; -- process labels illegal here
end value;
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01873d - Process labels are not permitted as primaries in a function return expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01873arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1873.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01873ent IS
END c07s01b00x00p08n01i01873ent;
ARCHITECTURE c07s01b00x00p08n01i01873arch OF c07s01b00x00p08n01i01873ent IS
type small_int is range 0 to 7;
BEGIN
TESTING : PROCESS
function value return small_int is
variable tmp : small_int := 0;
begin
case tmp is
when 0 => tmp := 0;
when others => tmp := 1;
end case;
return TESTING; -- process labels illegal here
end value;
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01873d - Process labels are not permitted as primaries in a function return expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01873arch;
|
entity tb_ram1 is
end tb_ram1;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ram1 is
signal clk : std_logic;
signal en : std_logic;
signal we : std_logic;
signal addr : std_logic_vector(5 downto 0);
signal rdat : std_logic_vector(31 downto 0);
signal wdat : std_logic_vector(31 downto 0);
begin
dut: entity work.ram1
port map (clkB => clk, enB => en, weB => we, addrB => addr,
diB => wdat, doB => rdat);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
en <= '1';
we <= '1';
addr <= b"00_0000";
wdat <= x"11_22_33_f0";
pulse;
assert rdat = x"11_22_33_f0" severity failure;
addr <= b"00_0001";
wdat <= x"11_22_33_f1";
pulse;
assert rdat = x"11_22_33_f1" severity failure;
-- Read.
we <= '0';
addr <= b"00_0000";
wdat <= x"ff_22_33_f1";
pulse;
assert rdat = x"11_22_33_f0" severity failure;
addr <= b"00_0001";
wdat <= x"ff_22_33_f1";
pulse;
assert rdat = x"11_22_33_f1" severity failure;
-- Disable.
en <= '0';
we <= '1';
addr <= b"00_0000";
wdat <= x"11_22_33_f0";
pulse;
assert rdat = x"11_22_33_f1" severity failure;
wait;
end process;
end behav;
|
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port( clk: in std_logic;
reset: in std_logic;
enable: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture behav of counter is
signal pre_count: std_logic_vector(3 downto 0);
begin
process(clk, enable, reset)
begin
if reset = '1' then
pre_count <= "0000";
elsif (clk='1' and clk'event) then
if enable = '1' then
pre_count <= pre_count + "1";
end if;
end if;
end process;
count <= pre_count;
end behav;
|
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port( clk: in std_logic;
reset: in std_logic;
enable: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture behav of counter is
signal pre_count: std_logic_vector(3 downto 0);
begin
process(clk, enable, reset)
begin
if reset = '1' then
pre_count <= "0000";
elsif (clk='1' and clk'event) then
if enable = '1' then
pre_count <= pre_count + "1";
end if;
end if;
end process;
count <= pre_count;
end behav;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1176.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s00b00x00p01n02i01176ent IS
END c08s00b00x00p01n02i01176ent;
ARCHITECTURE c08s00b00x00p01n02i01176arch OF c08s00b00x00p01n02i01176ent IS
signal k : integer := 0;
BEGIN
L1 : process
begin
k <= 5;
wait for 1 ns;
-- Avoid infinite simulation
wait;
end process L1;
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT(k = 5)
report "***PASSED TEST: c08s00b00x00p01n02i01176"
severity NOTE;
assert (k = 5)
report "***FAILED TEST: c08s00b00x00p01n02i01176 - Sequential statement are executed in the order in which they appear."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s00b00x00p01n02i01176arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1176.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s00b00x00p01n02i01176ent IS
END c08s00b00x00p01n02i01176ent;
ARCHITECTURE c08s00b00x00p01n02i01176arch OF c08s00b00x00p01n02i01176ent IS
signal k : integer := 0;
BEGIN
L1 : process
begin
k <= 5;
wait for 1 ns;
-- Avoid infinite simulation
wait;
end process L1;
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT(k = 5)
report "***PASSED TEST: c08s00b00x00p01n02i01176"
severity NOTE;
assert (k = 5)
report "***FAILED TEST: c08s00b00x00p01n02i01176 - Sequential statement are executed in the order in which they appear."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s00b00x00p01n02i01176arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1176.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s00b00x00p01n02i01176ent IS
END c08s00b00x00p01n02i01176ent;
ARCHITECTURE c08s00b00x00p01n02i01176arch OF c08s00b00x00p01n02i01176ent IS
signal k : integer := 0;
BEGIN
L1 : process
begin
k <= 5;
wait for 1 ns;
-- Avoid infinite simulation
wait;
end process L1;
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT(k = 5)
report "***PASSED TEST: c08s00b00x00p01n02i01176"
severity NOTE;
assert (k = 5)
report "***FAILED TEST: c08s00b00x00p01n02i01176 - Sequential statement are executed in the order in which they appear."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s00b00x00p01n02i01176arch;
|
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 51072)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 51072)
`protect data_block
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect data_block
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|
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_datalink_layer
---- Version: 1.0.0
---- Description:
---- TM (TeleMetry) Space Data Link Protocol
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
---- 2016/10/21: rework based on TX final architecture
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx datalink layer inputs and outputs
--=============================================================================
entity ccsds_tx_datalink_layer is
generic (
constant CCSDS_TX_DATALINK_ASM_LENGTH: integer := 4; -- Attached Synchronization Marker length / in Bytes
constant CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_ENABLED: boolean := false; -- Enable differential coder
constant CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer; -- Number of bits per codeword from differential coder
constant CCSDS_TX_DATALINK_DATA_BUS_SIZE: integer; -- in bits
constant CCSDS_TX_DATALINK_DATA_LENGTH: integer := 12; -- datagram data size (Bytes) / (has to be a multiple of CCSDS_TX_DATALINK_DATA_BUS_SIZE)
constant CCSDS_TX_DATALINK_FOOTER_LENGTH: integer := 2; -- datagram footer length (Bytes)
constant CCSDS_TX_DATALINK_HEADER_LENGTH: integer := 6 -- datagram header length (Bytes)
);
port(
-- inputs
clk_bit_i: in std_logic;
clk_dat_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
dat_nxt_o: out std_logic;
dat_val_o: out std_logic;
idl_o: out std_logic
);
end ccsds_tx_datalink_layer;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_tx_datalink_layer is
component ccsds_tx_framer is
generic(
CCSDS_TX_FRAMER_DATA_BUS_SIZE : integer;
CCSDS_TX_FRAMER_DATA_LENGTH : integer;
CCSDS_TX_FRAMER_FOOTER_LENGTH : integer;
CCSDS_TX_FRAMER_HEADER_LENGTH : integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_FRAMER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
dat_o: out std_logic_vector((CCSDS_TX_FRAMER_DATA_LENGTH+CCSDS_TX_FRAMER_HEADER_LENGTH+CCSDS_TX_FRAMER_FOOTER_LENGTH)*8-1 downto 0);
dat_val_o: out std_logic;
dat_nxt_o: out std_logic;
idl_o: out std_logic
);
end component;
component ccsds_tx_coder is
generic(
CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer;
CCSDS_TX_CODER_DIFFERENTIAL_ENABLED: boolean;
CCSDS_TX_CODER_DATA_BUS_SIZE : integer;
CCSDS_TX_CODER_ASM_LENGTH: integer
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
dat_val_o: out std_logic
);
end component;
-- internal constants
constant FRAME_OUTPUT_SIZE: integer := (CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH+CCSDS_TX_DATALINK_ASM_LENGTH)*8;
constant FRAME_OUTPUT_WORDS: integer := FRAME_OUTPUT_SIZE/CCSDS_TX_DATALINK_DATA_BUS_SIZE;
-- interconnection signals
signal wire_framer_data: std_logic_vector((CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH)*8-1 downto 0);
signal wire_framer_data_valid: std_logic;
signal wire_coder_data: std_logic_vector(FRAME_OUTPUT_SIZE-1 downto 0);
signal wire_coder_data_valid: std_logic;
-- components instanciation and mapping
begin
tx_datalink_framer_0: ccsds_tx_framer
generic map(
CCSDS_TX_FRAMER_HEADER_LENGTH => CCSDS_TX_DATALINK_HEADER_LENGTH,
CCSDS_TX_FRAMER_DATA_LENGTH => CCSDS_TX_DATALINK_DATA_LENGTH,
CCSDS_TX_FRAMER_FOOTER_LENGTH => CCSDS_TX_DATALINK_FOOTER_LENGTH,
CCSDS_TX_FRAMER_DATA_BUS_SIZE => CCSDS_TX_DATALINK_DATA_BUS_SIZE
)
port map(
clk_i => clk_dat_i,
rst_i => rst_i,
dat_val_i => dat_val_i,
dat_i => dat_i,
dat_val_o => wire_framer_data_valid,
dat_nxt_o => dat_nxt_o,
dat_o => wire_framer_data,
idl_o => idl_o
);
tx_datalink_coder_0: ccsds_tx_coder
generic map(
CCSDS_TX_CODER_ASM_LENGTH => CCSDS_TX_DATALINK_ASM_LENGTH,
CCSDS_TX_CODER_DATA_BUS_SIZE => (CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH)*8,
CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD => CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD,
CCSDS_TX_CODER_DIFFERENTIAL_ENABLED => CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_ENABLED
)
port map(
clk_i => clk_dat_i,
dat_i => wire_framer_data,
dat_val_i => wire_framer_data_valid,
rst_i => rst_i,
dat_val_o => wire_coder_data_valid,
dat_o => wire_coder_data
);
-- presynthesis checks
-- internal processing
--=============================================================================
-- Begin of bitsoutputp
-- Generate valid bits output word by word on coder data_valid signal
--=============================================================================
-- read: rst_i, wire_coder_data_valid
-- write: dat_val_o
-- r/w:
BITSVALIDP: process (clk_dat_i)
begin
-- on each clock rising edge
if rising_edge(clk_dat_i) then
-- reset signal received
if (rst_i = '1') then
dat_val_o <= '0';
else
if (wire_coder_data_valid = '1') then
dat_val_o <= '1';
end if;
end if;
end if;
end process;
--=============================================================================
-- Begin of bitsoutputp
-- Generate bits output word by word based on coder output
--=============================================================================
-- read: rst_i, wire_coder_data
-- write: dat_o
-- r/w:
BITSOUTPUTP: process (clk_bit_i)
variable next_word_pointer : integer range 0 to FRAME_OUTPUT_WORDS := FRAME_OUTPUT_WORDS - 1;
variable current_frame: std_logic_vector(FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0) := (others => '0');
begin
-- on each clock rising edge
if rising_edge(clk_bit_i) then
-- reset signal received
if (rst_i = '1') then
next_word_pointer := FRAME_OUTPUT_WORDS - 1;
dat_o <= (others => '0');
else
-- generating valid bits output words
if (next_word_pointer = FRAME_OUTPUT_WORDS - 1) then
current_frame := wire_coder_data(FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
dat_o <= wire_coder_data(FRAME_OUTPUT_SIZE-1 downto FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE);
next_word_pointer := FRAME_OUTPUT_WORDS - 2;
else
dat_o <= current_frame((next_word_pointer+1)*CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto next_word_pointer*CCSDS_TX_DATALINK_DATA_BUS_SIZE);
if (next_word_pointer = 0) then
next_word_pointer := FRAME_OUTPUT_WORDS - 1;
else
next_word_pointer := next_word_pointer - 1;
end if;
end if;
end if;
end if;
end process;
end structure;
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`protect end_protected
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_virage_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for Virage rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library virage;
use virage.hdss1_128x32cm4sw0ab;
use virage.hdss1_256x32cm4sw0ab;
use virage.hdss1_512x32cm4sw0ab;
use virage.hdss1_512x38cm4sw0ab;
use virage.hdss1_1024x32cm4sw0ab;
use virage.hdss1_2048x32cm8sw0ab;
use virage.hdss1_4096x36cm8sw0ab;
use virage.hdss1_16384x8cm16sw0;
-- pragma translate_on
entity virage_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of virage_syncram is
component hdss1_128x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(6 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_256x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(7 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_512x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_512x38cm4sw0ab
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(37 downto 0);
do : out std_logic_vector(37 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_1024x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(9 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_2048x32cm8sw0ab
port (
addr, taddr : in std_logic_vector(10 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_4096x36cm8sw0ab is
port (
addr, taddr : in std_logic_vector(11 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(35 downto 0);
do : out std_logic_vector(35 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_16384x8cm16sw0 is
port (
addr : in std_logic_vector(13 downto 0);
clk : in std_logic;
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
me, oe, we : in std_logic
);
end component;
signal d, q, gnd : std_logic_vector(40 downto 0);
signal a : std_logic_vector(17 downto 0);
signal vcc : std_ulogic;
constant synopsys_bug : std_logic_vector(40 downto 0) := (others => '0');
begin
gnd <= (others => '0'); vcc <= '1';
a(abits -1 downto 0) <= address;
d(dbits -1 downto 0) <= datain(dbits -1 downto 0);
a(17 downto abits) <= synopsys_bug(17 downto abits);
d(40 downto dbits) <= synopsys_bug(40 downto dbits);
dataout <= q(dbits -1 downto 0);
a7d32 : if (abits <= 7) and (dbits <= 32) generate
id0 : hdss1_128x32cm4sw0ab
port map (a(6 downto 0), gnd(6 downto 0),clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a8d32 : if (abits = 8) and (dbits <= 32) generate
id0 : hdss1_256x32cm4sw0ab
port map (a(7 downto 0), gnd(7 downto 0),clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d32 : if (abits = 9) and (dbits <= 32) generate
id0 : hdss1_512x32cm4sw0ab
port map (address(8 downto 0), gnd(8 downto 0),clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d38 : if (abits = 9) and (dbits > 32) and (dbits <= 38) generate
id0 : hdss1_512x38cm4sw0ab
port map (address(8 downto 0), gnd(8 downto 0),clk,
d(37 downto 0), gnd(37 downto 0), q(37 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a10d32 : if (abits = 10) and (dbits <= 32) generate
id0 : hdss1_1024x32cm4sw0ab
port map (address(9 downto 0), gnd(9 downto 0), clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a11d32 : if (abits = 11) and (dbits <= 32) generate
id0 : hdss1_2048x32cm8sw0ab
port map (address(10 downto 0), gnd(10 downto 0), clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a12d36 : if (abits = 12) and (dbits <= 36) generate
id0 : hdss1_4096x36cm8sw0ab
port map (address(11 downto 0), gnd(11 downto 0), clk,
d(35 downto 0), gnd(35 downto 0), q(35 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a14d8 : if (abits = 14) and (dbits <= 8) generate
id0 : hdss1_16384x8cm16sw0
port map (address(13 downto 0), clk,
d(7 downto 0), q(7 downto 0),
enable, vcc, Write);
end generate;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library virage;
use virage.hdss2_64x32cm4sw0ab;
use virage.hdss2_128x32cm4sw0ab;
use virage.hdss2_256x32cm4sw0ab;
use virage.hdss2_512x32cm4sw0ab;
use virage.hdss2_512x38cm4sw0ab;
use virage.hdss2_8192x8cm16sw0ab;
-- pragma translate_on
entity virage_syncram_dp is
generic ( abits : integer := 10; dbits : integer := 8);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end;
architecture rtl of virage_syncram_dp is
component hdss2_64x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(5 downto 0);
addrb, taddrb : in std_logic_vector(5 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_128x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(6 downto 0);
addrb, taddrb : in std_logic_vector(6 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_256x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_512x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_512x38cm4sw0ab
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(37 downto 0);
dib, tdib : in std_logic_vector(37 downto 0);
doa, dob : out std_logic_vector(37 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_8192x8cm16sw0ab
port (
addra, taddra : in std_logic_vector(12 downto 0);
addrb, taddrb : in std_logic_vector(12 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(7 downto 0);
dib, tdib : in std_logic_vector(7 downto 0);
doa, dob : out std_logic_vector(7 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
signal vcc : std_ulogic;
signal d1, d2, a1, a2, q1, q2, gnd : std_logic_vector(40 downto 0);
begin
vcc <= '1'; gnd <= (others => '0');
d1(dbits-1 downto 0) <= datain1; d1(40 downto dbits) <= (others => '0');
d2(dbits-1 downto 0) <= datain2; d2(40 downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= address1; a1(40 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= address2; a2(40 downto abits) <= (others => '0');
dataout1 <= q1(dbits-1 downto 0); dataout2 <= q2(dbits-1 downto 0);
a6d32 : if (abits <= 6) and (dbits <= 32) generate
id0 : hdss2_64x32cm4sw0ab
port map (a1(5 downto 0), gnd(5 downto 0), a2(5 downto 0),
gnd(5 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a7d32 : if (abits = 7) and (dbits <= 32) generate
id0 : hdss2_128x32cm4sw0ab
port map (a1(6 downto 0), gnd(6 downto 0), a2(6 downto 0),
gnd(6 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a8d32 : if (abits = 8) and (dbits <= 32) generate
id0 : hdss2_256x32cm4sw0ab
port map (a1(7 downto 0), gnd(7 downto 0), a2(7 downto 0),
gnd(7 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d32 : if (abits = 9) and (dbits <= 32) generate
id0 : hdss2_512x32cm4sw0ab
port map (a1(8 downto 0), gnd(8 downto 0), a2(8 downto 0),
gnd(8 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d38 : if (abits = 9) and (dbits > 32) and (dbits <= 38) generate
id0 : hdss2_512x38cm4sw0ab
port map (a1(8 downto 0), gnd(8 downto 0), a2(8 downto 0),
gnd(8 downto 0), clk1, clk2,
d1(37 downto 0), gnd(37 downto 0), d2(37 downto 0), gnd(37 downto 0),
q1(37 downto 0), q2(37 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library virage;
use virage.rfss2_136x32cm2sw0ab;
use virage.rfss2_136x40cm2sw0ab;
use virage.rfss2_168x32cm2sw0ab;
use virage.hdss2_64x32cm4sw0ab;
use virage.hdss2_128x32cm4sw0ab;
use virage.hdss2_256x32cm4sw0ab;
use virage.hdss2_512x32cm4sw0ab;
use virage.hdss2_8192x8cm16sw0ab;
-- pragma translate_on
entity virage_syncram_2p is
generic ( abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end;
architecture rtl of virage_syncram_2p is
component rfss2_136x32cm2sw0ab
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end component;
component rfss2_136x40cm2sw0ab
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(39 downto 0);
dob : out std_logic_vector(39 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end component;
signal vcc : std_ulogic;
signal d1, a1, a2, q1, gnd : std_logic_vector(40 downto 0);
begin
vcc <= '1'; gnd <= (others => '0');
d1(dbits-1 downto 0) <= datain; d1(40 downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= waddress; a1(40 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= raddress; a2(40 downto abits) <= (others => '0');
dataout <= q1(dbits-1 downto 0);
id0 : rfss2_136x40cm2sw0ab
port map (
a1(7 downto 0), gnd(7 downto 0), a2(7 downto 0), gnd(7 downto 0),
wclk, rclk, d1(39 downto 0), gnd(39 downto 0),
q1(39 downto 0),
vcc, write, gnd(0), gnd(0), gnd(0),
renable, vcc, gnd(0), gnd(0), gnd(0), gnd(0));
end;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_data_stream_2_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_img_0_data_stream_2_V_shiftReg;
architecture rtl of FIFO_image_filter_img_0_data_stream_2_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_data_stream_2_V is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_img_0_data_stream_2_V is
component FIFO_image_filter_img_0_data_stream_2_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_img_0_data_stream_2_V_shiftReg : FIFO_image_filter_img_0_data_stream_2_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_data_stream_2_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_img_0_data_stream_2_V_shiftReg;
architecture rtl of FIFO_image_filter_img_0_data_stream_2_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_data_stream_2_V is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_img_0_data_stream_2_V is
component FIFO_image_filter_img_0_data_stream_2_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_img_0_data_stream_2_V_shiftReg : FIFO_image_filter_img_0_data_stream_2_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_data_stream_2_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_img_0_data_stream_2_V_shiftReg;
architecture rtl of FIFO_image_filter_img_0_data_stream_2_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_data_stream_2_V is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_img_0_data_stream_2_V is
component FIFO_image_filter_img_0_data_stream_2_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_img_0_data_stream_2_V_shiftReg : FIFO_image_filter_img_0_data_stream_2_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_data_stream_2_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_img_0_data_stream_2_V_shiftReg;
architecture rtl of FIFO_image_filter_img_0_data_stream_2_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_data_stream_2_V is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_img_0_data_stream_2_V is
component FIFO_image_filter_img_0_data_stream_2_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_img_0_data_stream_2_V_shiftReg : FIFO_image_filter_img_0_data_stream_2_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
package pack_sum is
component eTopSumCompleto is
port(
acarreoI_tsc: in std_logic;
entrada1_tsc: in std_logic;
entrada2_tsc: in std_logic;
resultado_tsc: out std_logic;
acarreoO_tsc: out std_logic);
end component;
component eXnor
port(
entrada1_xnor: in std_logic;
entrada2_xnor: in std_logic;
salida_xnor: out std_logic);
end component;
component eAnd
port(
entrada1_and: in std_logic;
entrada2_and: in std_logic;
salida_and: out std_logic);
end component;
component eXor
port(
entrada1_xor: in std_logic;
entrada2_xor: in std_logic;
salida_xor: out std_logic);
end component;
end pack_sum;
|
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the entity and architecture of the
--! Crossbar's Read Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.plasoc_crossbar_pack.all;
entity plasoc_crossbar_axi4_read_cntrl is
generic (
axi_slave_amount : integer := 2;
axi_master_amount : integer := 4);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_read_master_iden : in std_logic_vector(axi_slave_amount*clogb2(axi_master_amount)-1 downto 0);
axi_read_slave_iden : in std_logic_vector(axi_master_amount*clogb2(axi_slave_amount)-1 downto 0);
axi_address_read_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
axi_data_read_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
s_axi_arvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_rready : in std_logic_vector(axi_slave_amount*1-1 downto 0);
m_axi_arready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_rvalid : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_rlast : in std_logic_vector(axi_master_amount*1-1 downto 0));
end plasoc_crossbar_axi4_read_cntrl;
architecture Behavioral of plasoc_crossbar_axi4_read_cntrl is
constant axi_slave_iden_width : integer := clogb2(axi_slave_amount);
constant axi_master_iden_width : integer := clogb2(axi_master_amount);
function reduce_enables_master(
enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return
std_logic_vector is
variable or_reduced : std_logic;
variable reduce_enables : std_logic_vector(axi_master_amount-1 downto 0);
begin
for each_master in 0 to axi_master_amount-1 loop
or_reduced := '0';
for each_slave in 0 to axi_slave_amount-1 loop
or_reduced := or_reduced or enables(each_slave+each_master*axi_slave_amount);
end loop;
reduce_enables(each_master) := or_reduced;
end loop;
return reduce_enables;
end;
function get_slave_handshakes (
valid : in std_logic_vector(axi_slave_amount-1 downto 0);
ready : in std_logic_vector(axi_master_amount-1 downto 0);
master_iden : in std_logic_vector(axi_slave_amount*axi_master_iden_width-1 downto 0) )
return std_logic_vector is
variable master_iden_buff : integer range 0 to axi_master_amount-1;
variable slave_handshakes : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0');
begin
for each_slave in 0 to axi_slave_amount-1 loop
master_iden_buff := to_integer(unsigned(master_iden((1+each_slave)*axi_master_iden_width-1 downto each_slave*axi_master_iden_width)));
if valid(each_slave)='1' and ready(master_iden_buff)='1' then
slave_handshakes(each_slave) := '1';
end if;
end loop;
return slave_handshakes;
end;
function get_slave_permissions (
slave_valid : in std_logic_vector(axi_slave_amount-1 downto 0);
master_iden : in std_logic_vector(axi_slave_amount*axi_master_iden_width-1 downto 0);
reduced_address_enables : in std_logic_vector(axi_master_amount-1 downto 0) ) return
std_logic_vector is
variable master_iden_buff : integer range 0 to axi_master_amount-1;
variable slave_permissions : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0');
begin
for each_master in 0 to axi_master_amount-1 loop
for each_slave in 0 to axi_slave_amount-1 loop
master_iden_buff := to_integer(unsigned(master_iden((1+each_slave)*axi_master_iden_width-1 downto each_slave*axi_master_iden_width)));
if each_master=master_iden_buff and slave_valid(each_slave)='1' and reduced_address_enables(master_iden_buff)='0' then
slave_permissions(each_slave) := '1';
exit;
end if;
end loop;
end loop;
return slave_permissions;
end;
function set_slave_enables_ff(
slave_permissions : in std_logic_vector(axi_slave_amount-1 downto 0);
slave_handshakes : in std_logic_vector(axi_slave_amount-1 downto 0);
master_iden : in std_logic_vector(axi_slave_amount*axi_master_iden_width-1 downto 0);
slave_enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return
std_logic_vector is
variable master_iden_buff : integer range 0 to axi_master_amount-1;
variable slave_enables_buff : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
begin
slave_enables_buff := slave_enables;
for each_slave in 0 to axi_slave_amount-1 loop
master_iden_buff := to_integer(unsigned(master_iden((1+each_slave)*axi_master_iden_width-1 downto each_slave*axi_master_iden_width)));
if slave_permissions(each_slave)='1' then
slave_enables_buff(each_slave+master_iden_buff*axi_slave_amount) := '1';
elsif slave_handshakes(each_slave)='1' then
for each_master in 0 to axi_master_amount-1 loop
slave_enables_buff(each_slave+each_master*axi_slave_amount) := '0';
end loop;
end if;
end loop;
return slave_enables_buff;
end;
function reduce_enables_slave(
enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return
std_logic_vector is
variable or_reduced : std_logic;
variable reduce_enables : std_logic_vector(axi_slave_amount-1 downto 0);
begin
for each_slave in 0 to axi_slave_amount-1 loop
or_reduced := '0';
for each_master in 0 to axi_master_amount-1 loop
or_reduced := or_reduced or enables(each_slave+each_master*axi_slave_amount);
end loop;
reduce_enables(each_slave) := or_reduced;
end loop;
return reduce_enables;
end;
function get_master_handshakes (
valid : in std_logic_vector(axi_master_amount-1 downto 0);
ready : in std_logic_vector(axi_slave_amount-1 downto 0);
slave_iden : in std_logic_vector(axi_master_amount*axi_slave_iden_width-1 downto 0) )
return std_logic_vector is
variable slave_iden_buff : integer range 0 to axi_slave_amount-1;
variable master_handshakes : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0');
begin
for each_master in 0 to axi_master_amount-1 loop
slave_iden_buff := to_integer(unsigned(slave_iden((1+each_master)*axi_slave_iden_width-1 downto each_master*axi_slave_iden_width)));
if valid(each_master)='1' and ready(slave_iden_buff)='1' then
master_handshakes(each_master) := '1';
end if;
end loop;
return master_handshakes;
end;
function get_master_permissions (
master_valid : in std_logic_vector(axi_master_amount-1 downto 0);
slave_iden : in std_logic_vector(axi_master_amount*axi_slave_iden_width-1 downto 0);
reduced_data_enables : in std_logic_vector(axi_slave_amount-1 downto 0) ) return
std_logic_vector is
variable slave_iden_buff : integer range 0 to axi_slave_amount-1;
variable master_permissions : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0');
begin
for each_slave in 0 to axi_slave_amount-1 loop
for each_master in 0 to axi_master_amount-1 loop
slave_iden_buff := to_integer(unsigned(slave_iden((1+each_master)*axi_slave_iden_width-1 downto each_master*axi_slave_iden_width)));
if each_slave=slave_iden_buff and master_valid(each_master)='1' and reduced_data_enables(slave_iden_buff)='0' then
master_permissions(each_master) := '1';
exit;
end if;
end loop;
end loop;
return master_permissions;
end;
function set_master_enables_ff (
master_permissions : in std_logic_vector(axi_master_amount-1 downto 0);
master_handshakes : in std_logic_vector(axi_master_amount-1 downto 0);
master_last : in std_logic_vector(axi_master_amount-1 downto 0);
slave_iden : in std_logic_vector(axi_master_amount*axi_slave_iden_width-1 downto 0);
master_enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return
std_logic_vector is
variable slave_iden_buff : integer range 0 to axi_slave_amount-1;
variable master_enables_buff : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
begin
master_enables_buff := master_enables;
for each_master in 0 to axi_master_amount-1 loop
slave_iden_buff := to_integer(unsigned(slave_iden((1+each_master)*axi_slave_iden_width-1 downto each_master*axi_slave_iden_width)));
if master_permissions(each_master)='1' then
master_enables_buff(slave_iden_buff+each_master*axi_slave_amount) := '1';
elsif master_handshakes(each_master)='1' and master_last(each_master)='1' then
for each_slave in 0 to axi_slave_amount-1 loop
master_enables_buff(each_slave+each_master*axi_slave_amount) := '0';
end loop;
end if;
end loop;
return master_enables_buff;
end;
signal address_slave_handshakes : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0');
signal axi_address_read_enables_buff : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) := (others=>'0');
signal reduced_address_read_enables : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0');
signal slave_permissions : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0');
signal data_master_handshakes : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0');
signal axi_data_read_enables_buff : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) := (others=>'0');
signal reduced_data_read_enables : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0');
signal master_permissions : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0');
begin
axi_address_read_enables <= axi_address_read_enables_buff;
axi_data_read_enables <= axi_data_read_enables_buff;
process (s_axi_arvalid,m_axi_arready,axi_read_master_iden)
begin
address_slave_handshakes <= get_slave_handshakes(s_axi_arvalid,m_axi_arready,axi_read_master_iden);
end process;
process (axi_address_read_enables_buff)
begin
reduced_address_read_enables <= reduce_enables_master(axi_address_read_enables_buff);
end process;
process (s_axi_arvalid,axi_read_master_iden,reduced_address_read_enables)
begin
slave_permissions <= get_slave_permissions(s_axi_arvalid,axi_read_master_iden,reduced_address_read_enables);
end process;
process (m_axi_rvalid,s_axi_rready,axi_read_slave_iden)
begin
data_master_handshakes <= get_master_handshakes(m_axi_rvalid,s_axi_rready,axi_read_slave_iden);
end process;
process (axi_data_read_enables_buff)
begin
reduced_data_read_enables <= reduce_enables_slave(axi_data_read_enables_buff);
end process;
process (m_axi_rvalid,axi_read_slave_iden,reduced_data_read_enables)
begin
master_permissions <= get_master_permissions(m_axi_rvalid,axi_read_slave_iden,reduced_data_read_enables);
end process;
process (aclk)
begin
if rising_edge(aclk) then
if aresetn='0' then
axi_address_read_enables_buff <= (others=>'0');
axi_data_read_enables_buff <= (others=>'0');
else
axi_address_read_enables_buff <= set_slave_enables_ff(slave_permissions,address_slave_handshakes,axi_read_master_iden,axi_address_read_enables_buff);
axi_data_read_enables_buff <= set_master_enables_ff(master_permissions,data_master_handshakes,m_axi_rlast,axi_read_slave_iden,axi_data_read_enables_buff);
end if;
end if;
end process;
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity LX9CoPro6502fast is
generic (
UseAlanDCore : boolean := false;
UseArletCore : boolean := true
);
port (
-- GOP Signals
fastclk : in std_logic;
test : inout std_logic_vector(8 downto 1);
sw : in std_logic_vector(3 downto 0);
-- Tube signals
h_phi2 : in std_logic;
h_addr : in std_logic_vector(2 downto 0);
h_data : inout std_logic_vector(7 downto 0);
h_rdnw : in std_logic;
h_cs_b : in std_logic;
h_rst_b : in std_logic;
h_irq_b : inout std_logic;
-- Ram Signals
ram_ub_b : out std_logic;
ram_lb_b : out std_logic;
ram_cs : out std_logic;
ram_oe : out std_logic;
ram_wr : out std_logic;
ram_addr : out std_logic_vector (18 downto 0);
ram_data : inout std_logic_vector (15 downto 0)
);
end LX9CoPro6502fast;
architecture BEHAVIORAL of LX9CoPro6502fast is
-------------------------------------------------
-- clock and reset signals
-------------------------------------------------
signal clk_cpu : std_logic;
signal cpu_clken : std_logic;
signal bootmode : std_logic;
signal RSTn : std_logic;
signal RSTn_sync : std_logic;
signal clken_counter : std_logic_vector (4 downto 0);
signal reset_counter : std_logic_vector (8 downto 0);
-------------------------------------------------
-- parasite signals
-------------------------------------------------
signal p_cs_b : std_logic;
signal bank_cs_b : std_logic;
signal p_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- ram/rom signals
-------------------------------------------------
signal ram_cs_b : std_logic;
signal rom_cs_b : std_logic;
signal rom_data_out : std_logic_vector (7 downto 0);
signal int_ram_data_out : std_logic_vector (7 downto 0);
signal ext_ram_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- bank registers and physical address bus
-------------------------------------------------
signal ext_ram : std_logic;
signal ext_ram_next : std_logic;
signal ext_ram_we : std_logic;
signal ext_ram_we_next : std_logic;
signal int_ram : std_logic;
signal int_ram_next : std_logic;
signal int_ram_we_next : std_logic;
signal physical_addr : std_logic_vector (20 downto 0);
signal physical_addr_next : std_logic_vector (20 downto 0);
-- bit 7 = 0 for internal RAM, 1 for external RAM
type bank_reg_type is array (0 to 7) of std_logic_vector (7 downto 0);
signal bank_reg : bank_reg_type;
-------------------------------------------------
-- cpu signals
-------------------------------------------------
signal debug_clk : std_logic;
signal cpu_R_W_n : std_logic;
signal cpu_addr : std_logic_vector (15 downto 0);
signal cpu_addr_us: unsigned (15 downto 0);
signal cpu_din : std_logic_vector (7 downto 0);
signal cpu_dout : std_logic_vector (7 downto 0);
signal cpu_dout_us: unsigned (7 downto 0);
signal cpu_IRQ_n : std_logic;
signal cpu_NMI_n : std_logic;
signal cpu_IRQ_n_sync : std_logic;
signal cpu_NMI_n_sync : std_logic;
signal sync : std_logic;
-- Lookahead (unregistered) signals
signal p_cs_b_next : std_logic;
signal bank_cs_b_next : std_logic;
signal ram_cs_b_next : std_logic;
signal rom_cs_b_next : std_logic;
signal cpu_dout_next : std_logic_vector (7 downto 0);
signal cpu_dout_next_us : unsigned (7 downto 0);
signal cpu_addr_next : std_logic_vector (15 downto 0);
signal cpu_addr_next_us : unsigned (15 downto 0);
signal cpu_we_next : std_logic;
signal cpu_R_W_n_next : std_logic;
signal digit1_cs_b : std_logic;
signal digit2_cs_b : std_logic;
signal digit1 : std_logic_vector (7 downto 0);
signal digit2 : std_logic_vector (7 downto 0);
signal sw_out : std_logic_vector (3 downto 0);
begin
---------------------------------------------------------------------
-- instantiated components
---------------------------------------------------------------------
inst_ICAP_config : entity work.ICAP_config port map (
fastclk => fastclk,
sw_in => sw,
sw_out => sw_out,
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b
);
inst_dcm_cpu_clk : entity work.dcm_32_64 port map (
CLKIN_IN => fastclk,
CLK0_OUT => clk_cpu,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
inst_tuberom : entity work.tuberom_65c102_banner port map (
CLK => clk_cpu,
ADDR => cpu_addr(10 downto 0),
DATA => rom_data_out
);
GenAlanDCore: if UseAlanDCore generate
inst_r65c02: entity work.r65c02 port map(
reset => RSTn_sync,
clk => clk_cpu,
enable => cpu_clken,
nmi_n => cpu_NMI_n_sync,
irq_n => cpu_IRQ_n_sync,
di => unsigned(cpu_din),
do_next => cpu_dout_next_us,
do => cpu_dout_us,
addr_next => cpu_addr_next_us,
addr => cpu_addr_us,
nwe_next => cpu_R_W_n_next,
nwe => cpu_R_W_n,
sync => sync,
sync_irq => open
);
cpu_dout <= std_logic_vector(cpu_dout_us);
cpu_addr <= std_logic_vector(cpu_addr_us);
cpu_dout_next <= std_logic_vector(cpu_dout_next_us);
cpu_addr_next <= std_logic_vector(cpu_addr_next_us);
end generate;
GenArletCore: if UseArletCore generate
inst_arlet_6502: entity work.cpu_65c02 port map(
clk => clk_cpu,
reset => not RSTn_sync,
AB => cpu_addr_next,
DI => cpu_din,
DO => cpu_dout_next,
WE => cpu_we_next,
IRQ => not cpu_IRQ_n_sync,
NMI => not cpu_NMI_n_sync,
RDY => cpu_clken
);
cpu_R_W_n_next <= not cpu_we_next;
process(clk_cpu)
begin
if rising_edge(clk_cpu) then
if cpu_clken = '1' then
cpu_addr <= cpu_addr_next;
cpu_dout <= cpu_dout_next;
cpu_R_W_n <= cpu_R_W_n_next;
end if;
end if;
end process;
end generate;
inst_tube: entity work.tube port map (
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b,
h_irq_b => h_irq_b,
p_addr => cpu_addr(2 downto 0),
p_cs_b => not((not p_cs_b) and cpu_clken),
p_data_in => cpu_dout,
p_data_out => p_data_out,
p_rdnw => cpu_R_W_n,
p_phi2 => clk_cpu,
p_rst_b => RSTn,
p_nmi_b => cpu_NMI_n,
p_irq_b => cpu_IRQ_n
);
Inst_RAM_64K: entity work.RAM_64K PORT MAP(
clk => clk_cpu,
we_uP => int_ram_we_next,
ce => cpu_clken,
addr_uP => physical_addr_next(15 downto 0),
D_uP => cpu_dout_next,
Q_uP => int_ram_data_out
);
p_cs_b <= '0' when cpu_addr(15 downto 3) = 2#1111_1110_1111_1# else '1';
bank_cs_b <= '0' when cpu_addr(15 downto 3) = 2#1111_1110_1110_0# else '1';
rom_cs_b <= '0' when cpu_addr(15 downto 11) = "11111" and cpu_R_W_n = '1' and bootmode = '1' else '1';
digit1_cs_b <= '0' when rom_cs_b = '0' and cpu_addr(11 downto 0) = x"86F" else '1';
digit2_cs_b <= '0' when rom_cs_b = '0' and cpu_addr(11 downto 0) = x"870" else '1';
-- Original: Acorn TUBE 65C102 Co-Processor
-- Updated: Acorn TUBE 64MHz 65C102 Co-Pro
digit1 <= x"36" when sw_out(1 downto 0) = "11" else
x"31" when sw_out(1 downto 0) = "10" else
x"30";
digit2 <= x"33" when sw_out(1 downto 0) = "00" else
x"36" when sw_out(1 downto 0) = "10" else
x"34";
ram_cs_b <= '0' when bank_cs_b = '1' and p_cs_b = '1' and rom_cs_b = '1' else '1';
-- Look ahead versions of the chip selects
p_cs_b_next <= '0' when cpu_addr_next(15 downto 3) = 2#1111_1110_1111_1# else '1';
bank_cs_b_next <= '0' when cpu_addr_next(15 downto 3) = 2#1111_1110_1110_0# else '1';
rom_cs_b_next <= '0' when cpu_addr_next(15 downto 11) = "11111" and cpu_R_W_n_next = '1' and bootmode = '1' else '1';
ram_cs_b_next <= '0' when p_cs_b_next = '1' and bank_cs_b_next = '1' and rom_cs_b_next = '1' else '1';
cpu_din <=
p_data_out when p_cs_b = '0' else
digit1 when digit1_cs_b = '0' else
digit2 when digit2_cs_b = '0' else
rom_data_out when rom_cs_b = '0' else
int_ram_data_out when int_ram = '1' else
ext_ram_data_out when ext_ram = '1' else
x"f1";
--------------------------------------------------------
-- bank registers
--------------------------------------------------------
process (clk_cpu, RSTn_sync)
begin
if RSTn_sync = '0' then
bank_reg(0) <= x"00";
bank_reg(1) <= x"01";
bank_reg(2) <= x"02";
bank_reg(3) <= x"03";
bank_reg(4) <= x"04";
bank_reg(5) <= x"05";
bank_reg(6) <= x"06";
bank_reg(7) <= x"07";
elsif rising_edge(clk_cpu) then
if cpu_clken = '1' then
int_ram <= int_ram_next;
ext_ram <= ext_ram_next;
if bank_cs_b = '0' and cpu_R_W_n = '0' and bootmode = '0' then
bank_reg(conv_integer(cpu_addr(2 downto 0))) <= cpu_dout;
end if;
end if;
end if;
end process;
physical_addr_next <= bank_reg(conv_integer(cpu_addr_next(15 downto 13))) & cpu_addr_next(12 downto 0);
int_ram_next <= '1' when ram_cs_b_next = '0' and physical_addr_next(20) = '0' else
'0';
ext_ram_next <= '1' when ram_cs_b_next = '0' and physical_addr_next(20) = '1' else
'0';
int_ram_we_next <= '1' when int_ram_next = '1' and cpu_R_W_n_next = '0' else
'0';
ext_ram_we_next <= '1' when ext_ram_next = '1' and cpu_R_W_n_next = '0' else
'0';
--------------------------------------------------------
-- external Ram
--
-- note: dispite the naming, all control signals are active low
--------------------------------------------------------
process (clk_cpu)
begin
if rising_edge(clk_cpu) then
if cpu_clken = '1' then
ext_ram_we <= ext_ram_we_next;
physical_addr <= physical_addr_next;
end if;
end if;
end process;
-- With 4 wait states, an external RAM cycle lasts ~80ns
-- To provide some address setup/hold margin we generate
-- a gated write signal off the falling edge of the clock
-- which gives half a cycle of setup/hold margin
process (clk_cpu)
begin
if falling_edge(clk_cpu) then
if ext_ram_we = '1' and clken_counter > 0 then
ram_wr <= '0';
else
ram_wr <= '1';
end if;
end if;
end process;
ram_ub_b <= not physical_addr(19);
ram_lb_b <= physical_addr(19);
ram_cs <= not ext_ram;
ram_oe <= ext_ram_we;
ram_addr <= physical_addr(18 downto 0);
ram_data <= (cpu_dout & cpu_dout) when ext_ram_we = '1' else (others => 'Z');
ext_ram_data_out <= ram_data(15 downto 8) when physical_addr(19) = '1' else ram_data(7 downto 0);
--------------------------------------------------------
-- test signals
--------------------------------------------------------
-- default to hi-impedence, to avoid conflicts with
-- a Raspberry Pi connected to the test connector
test <= (others => 'Z');
--------------------------------------------------------
-- boot mode generator
--------------------------------------------------------
boot_gen : process(clk_cpu, RSTn_sync)
begin
if RSTn_sync = '0' then
bootmode <= '1';
elsif rising_edge(clk_cpu) then
if p_cs_b = '0' then
bootmode <= '0';
end if;
end if;
end process;
--------------------------------------------------------
-- power up reset
--------------------------------------------------------
reset_gen : process(clk_cpu)
begin
if rising_edge(clk_cpu) then
if (reset_counter(8) = '0') then
reset_counter <= reset_counter + 1;
end if;
RSTn_sync <= RSTn AND reset_counter(8);
end if;
end process;
--------------------------------------------------------
-- interrupt synchronization
--------------------------------------------------------
sync_gen : process(clk_cpu, RSTn_sync)
begin
if RSTn_sync = '0' then
cpu_NMI_n_sync <= '1';
cpu_IRQ_n_sync <= '1';
elsif rising_edge(clk_cpu) then
if (cpu_clken = '1') then
cpu_NMI_n_sync <= cpu_NMI_n;
cpu_IRQ_n_sync <= cpu_IRQ_n;
end if;
end if;
end process;
--------------------------------------------------------
-- clock enable generator
--------------------------------------------------------
clk_gen : process(clk_cpu)
begin
if rising_edge(clk_cpu) then
if clken_counter = 0 then
case sw_out(1 downto 0) is
when "11" =>
-- 64MHz
if rom_cs_b_next = '0' then
-- Add one wait state for ROM accesses
clken_counter <= "0" & x"1";
elsif ext_ram_next = '1' then
-- Add four wait states for external RAM accesses
clken_counter <= "0" & x"4";
else
-- Full speed ahead!
clken_counter <= "0" & x"0";
end if;
when "10" =>
-- 16MHz
if ext_ram_next = '1' then
-- Add four wait states for external RAM accesses
clken_counter <= "0" & x"4";
else
-- Quarter speed ahead!
clken_counter <= "0" & x"3";
end if;
when "01" =>
-- 4MHz
-- Running so slowly there is need to special case external RAM accesses
clken_counter <= "0" & x"F";
when "00" =>
-- 2.91MHz
-- Running so slowly there is need to special case external RAM accesses
clken_counter <= "1" & x"5";
when others =>
-- there are no others
end case;
else
clken_counter <= clken_counter - 1;
end if;
end if;
end process;
cpu_clken <= '1' when clken_counter = 0 else '0';
end BEHAVIORAL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:49:26 12/20/2015
-- Design Name:
-- Module Name: counter_modulo_n - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.math_real.ceil;
use IEEE.math_real.log2;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter_modulo_n is
generic ( n : natural := 16 );
Port ( clock : in STD_LOGIC;
count_en : in STD_LOGIC;
reset_n : in STD_LOGIC;
up_down : in STD_LOGIC;
load_conteggio : in STD_LOGIC;
conteggio_in : in STD_LOGIC_VECTOR (natural(ceil(log2(real(n))))-1 downto 0);
conteggio_out : out STD_LOGIC_VECTOR ((natural(ceil(log2(real(n)))))-1 downto 0);
count_hit : out STD_LOGIC);
end counter_modulo_n;
architecture Behavioral of counter_modulo_n is
signal pre_conteggio_out : std_logic_vector (natural(ceil(log2(real(n))))-1 downto 0);
begin
contatore : process(clock, reset_n, up_down)
begin
if (reset_n = '0') then
count_hit <= '0';
if(up_down = '0') then
pre_conteggio_out <= (others => '0');
else
pre_conteggio_out <= conv_STD_LOGIC_VECTOR(n-1, natural(ceil(log2(real(n)))));
end if;
elsif (rising_edge(clock)) then
if (load_conteggio = '1') then
pre_conteggio_out <= conteggio_in;
elsif (count_en = '1') then
if (up_down = '0') then
if (pre_conteggio_out = n-1) then
count_hit <= '1';
pre_conteggio_out <= (others => '0');
else
count_hit <= '0';
pre_conteggio_out <= pre_conteggio_out + 1;
end if;
else
if (pre_conteggio_out = 0) then
count_hit <= '1';
pre_conteggio_out <= conv_STD_LOGIC_VECTOR(n-1, natural(ceil(log2(real(n)))));
else
count_hit <= '0';
pre_conteggio_out <= pre_conteggio_out - 1;
end if;
end if;
end if;
end if;
end process;
conteggio_out <= pre_conteggio_out;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Wave package
-------------------------------------------------------------------------------
-- File : wave_pkg.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This package provides ways to write (and maybe in future read)
-- .wav files.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.tl_file_io_pkg.all;
package wave_pkg is
type t_wave_channel is record
number_of_samples : integer;
memory : h_mem_object;
end record;
type t_wave_channel_array is array(natural range <>) of t_wave_channel;
procedure open_channel(chan : out t_wave_channel);
procedure push_sample(chan : inout t_wave_channel; sample : integer);
procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array);
end package;
package body wave_pkg is
procedure open_channel(chan : out t_wave_channel) is
variable ch : t_wave_channel;
begin
register_mem_model("path", "channel", ch.memory);
ch.number_of_samples := 0;
chan := ch;
end procedure;
procedure push_sample(chan : inout t_wave_channel; sample : integer) is
variable s : integer;
begin
s := sample;
if s > 32767 then s := 32767; end if;
if s < -32768 then s := -32768; end if;
write_memory_int(chan.memory, chan.number_of_samples, s);
chan.number_of_samples := chan.number_of_samples + 1;
end procedure;
procedure write_vector_le(x : std_logic_vector; file f : t_binary_file; r : inout t_binary_file_rec) is
variable bytes : integer := (x'length + 7) / 8;
variable xa : std_logic_vector(7+bytes*8 downto 0);
begin
xa := (others => '0');
xa(x'length-1 downto 0) := x;
for i in 0 to bytes-1 loop
write_byte(f, xa(i*8+7 downto i*8), r);
end loop;
end procedure;
procedure write_int_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is
variable x_slv : std_logic_vector(31 downto 0);
begin
x_slv := std_logic_vector(to_signed(x, 32));
write_vector_le(x_slv, f, r);
end procedure;
procedure write_short_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is
variable x_slv : std_logic_vector(15 downto 0);
begin
x_slv := std_logic_vector(to_signed(x, 16));
write_vector_le(x_slv, f, r);
end procedure;
procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array) is
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
variable stat : file_open_status;
variable file_size : integer;
variable data_size : integer;
variable max_length : integer;
begin
-- open file
file_open(stat, myfile, name, write_mode);
assert (stat = open_ok)
report "Could not open file " & name & " for writing."
severity failure;
init_record(myrec);
max_length := 0;
for i in channels'range loop
if channels(i).number_of_samples > max_length then
max_length := channels(i).number_of_samples;
end if;
end loop;
data_size := (max_length * channels'length * 2);
file_size := 12 + 16 + 8 + data_size;
-- header
write_vector_le(X"46464952", myfile, myrec); -- "RIFF"
write_int_le (file_size-8, myfile, myrec);
write_vector_le(X"45564157", myfile, myrec); -- "WAVE"
-- chunk header
write_vector_le(X"20746D66", myfile, myrec); -- "fmt "
write_int_le (16, myfile, myrec);
write_short_le (1, myfile, myrec); -- compression code = uncompressed
write_short_le (channels'length, myfile, myrec);
write_int_le (rate, myfile, myrec); -- sample rate
write_int_le (rate * channels'length * 2, myfile, myrec); -- Bps
write_short_le (channels'length * 2, myfile, myrec); -- alignment
write_short_le (16, myfile, myrec); -- bits per sample
write_vector_le(X"61746164", myfile, myrec); -- "data"
write_int_le (data_size, myfile, myrec);
-- now write out all data!
for i in 0 to max_length-1 loop
for j in channels'range loop
write_short_le(read_memory_int(channels(j).memory, i), myfile, myrec);
end loop;
end loop;
purge(myfile, myrec);
file_close(myfile);
end procedure;
end;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Wave package
-------------------------------------------------------------------------------
-- File : wave_pkg.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This package provides ways to write (and maybe in future read)
-- .wav files.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.tl_file_io_pkg.all;
package wave_pkg is
type t_wave_channel is record
number_of_samples : integer;
memory : h_mem_object;
end record;
type t_wave_channel_array is array(natural range <>) of t_wave_channel;
procedure open_channel(chan : out t_wave_channel);
procedure push_sample(chan : inout t_wave_channel; sample : integer);
procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array);
end package;
package body wave_pkg is
procedure open_channel(chan : out t_wave_channel) is
variable ch : t_wave_channel;
begin
register_mem_model("path", "channel", ch.memory);
ch.number_of_samples := 0;
chan := ch;
end procedure;
procedure push_sample(chan : inout t_wave_channel; sample : integer) is
variable s : integer;
begin
s := sample;
if s > 32767 then s := 32767; end if;
if s < -32768 then s := -32768; end if;
write_memory_int(chan.memory, chan.number_of_samples, s);
chan.number_of_samples := chan.number_of_samples + 1;
end procedure;
procedure write_vector_le(x : std_logic_vector; file f : t_binary_file; r : inout t_binary_file_rec) is
variable bytes : integer := (x'length + 7) / 8;
variable xa : std_logic_vector(7+bytes*8 downto 0);
begin
xa := (others => '0');
xa(x'length-1 downto 0) := x;
for i in 0 to bytes-1 loop
write_byte(f, xa(i*8+7 downto i*8), r);
end loop;
end procedure;
procedure write_int_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is
variable x_slv : std_logic_vector(31 downto 0);
begin
x_slv := std_logic_vector(to_signed(x, 32));
write_vector_le(x_slv, f, r);
end procedure;
procedure write_short_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is
variable x_slv : std_logic_vector(15 downto 0);
begin
x_slv := std_logic_vector(to_signed(x, 16));
write_vector_le(x_slv, f, r);
end procedure;
procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array) is
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
variable stat : file_open_status;
variable file_size : integer;
variable data_size : integer;
variable max_length : integer;
begin
-- open file
file_open(stat, myfile, name, write_mode);
assert (stat = open_ok)
report "Could not open file " & name & " for writing."
severity failure;
init_record(myrec);
max_length := 0;
for i in channels'range loop
if channels(i).number_of_samples > max_length then
max_length := channels(i).number_of_samples;
end if;
end loop;
data_size := (max_length * channels'length * 2);
file_size := 12 + 16 + 8 + data_size;
-- header
write_vector_le(X"46464952", myfile, myrec); -- "RIFF"
write_int_le (file_size-8, myfile, myrec);
write_vector_le(X"45564157", myfile, myrec); -- "WAVE"
-- chunk header
write_vector_le(X"20746D66", myfile, myrec); -- "fmt "
write_int_le (16, myfile, myrec);
write_short_le (1, myfile, myrec); -- compression code = uncompressed
write_short_le (channels'length, myfile, myrec);
write_int_le (rate, myfile, myrec); -- sample rate
write_int_le (rate * channels'length * 2, myfile, myrec); -- Bps
write_short_le (channels'length * 2, myfile, myrec); -- alignment
write_short_le (16, myfile, myrec); -- bits per sample
write_vector_le(X"61746164", myfile, myrec); -- "data"
write_int_le (data_size, myfile, myrec);
-- now write out all data!
for i in 0 to max_length-1 loop
for j in channels'range loop
write_short_le(read_memory_int(channels(j).memory, i), myfile, myrec);
end loop;
end loop;
purge(myfile, myrec);
file_close(myfile);
end procedure;
end;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Wave package
-------------------------------------------------------------------------------
-- File : wave_pkg.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This package provides ways to write (and maybe in future read)
-- .wav files.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.tl_file_io_pkg.all;
package wave_pkg is
type t_wave_channel is record
number_of_samples : integer;
memory : h_mem_object;
end record;
type t_wave_channel_array is array(natural range <>) of t_wave_channel;
procedure open_channel(chan : out t_wave_channel);
procedure push_sample(chan : inout t_wave_channel; sample : integer);
procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array);
end package;
package body wave_pkg is
procedure open_channel(chan : out t_wave_channel) is
variable ch : t_wave_channel;
begin
register_mem_model("path", "channel", ch.memory);
ch.number_of_samples := 0;
chan := ch;
end procedure;
procedure push_sample(chan : inout t_wave_channel; sample : integer) is
variable s : integer;
begin
s := sample;
if s > 32767 then s := 32767; end if;
if s < -32768 then s := -32768; end if;
write_memory_int(chan.memory, chan.number_of_samples, s);
chan.number_of_samples := chan.number_of_samples + 1;
end procedure;
procedure write_vector_le(x : std_logic_vector; file f : t_binary_file; r : inout t_binary_file_rec) is
variable bytes : integer := (x'length + 7) / 8;
variable xa : std_logic_vector(7+bytes*8 downto 0);
begin
xa := (others => '0');
xa(x'length-1 downto 0) := x;
for i in 0 to bytes-1 loop
write_byte(f, xa(i*8+7 downto i*8), r);
end loop;
end procedure;
procedure write_int_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is
variable x_slv : std_logic_vector(31 downto 0);
begin
x_slv := std_logic_vector(to_signed(x, 32));
write_vector_le(x_slv, f, r);
end procedure;
procedure write_short_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is
variable x_slv : std_logic_vector(15 downto 0);
begin
x_slv := std_logic_vector(to_signed(x, 16));
write_vector_le(x_slv, f, r);
end procedure;
procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array) is
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
variable stat : file_open_status;
variable file_size : integer;
variable data_size : integer;
variable max_length : integer;
begin
-- open file
file_open(stat, myfile, name, write_mode);
assert (stat = open_ok)
report "Could not open file " & name & " for writing."
severity failure;
init_record(myrec);
max_length := 0;
for i in channels'range loop
if channels(i).number_of_samples > max_length then
max_length := channels(i).number_of_samples;
end if;
end loop;
data_size := (max_length * channels'length * 2);
file_size := 12 + 16 + 8 + data_size;
-- header
write_vector_le(X"46464952", myfile, myrec); -- "RIFF"
write_int_le (file_size-8, myfile, myrec);
write_vector_le(X"45564157", myfile, myrec); -- "WAVE"
-- chunk header
write_vector_le(X"20746D66", myfile, myrec); -- "fmt "
write_int_le (16, myfile, myrec);
write_short_le (1, myfile, myrec); -- compression code = uncompressed
write_short_le (channels'length, myfile, myrec);
write_int_le (rate, myfile, myrec); -- sample rate
write_int_le (rate * channels'length * 2, myfile, myrec); -- Bps
write_short_le (channels'length * 2, myfile, myrec); -- alignment
write_short_le (16, myfile, myrec); -- bits per sample
write_vector_le(X"61746164", myfile, myrec); -- "data"
write_int_le (data_size, myfile, myrec);
-- now write out all data!
for i in 0 to max_length-1 loop
for j in channels'range loop
write_short_le(read_memory_int(channels(j).memory, i), myfile, myrec);
end loop;
end loop;
purge(myfile, myrec);
file_close(myfile);
end procedure;
end;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Wave package
-------------------------------------------------------------------------------
-- File : wave_pkg.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This package provides ways to write (and maybe in future read)
-- .wav files.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.tl_file_io_pkg.all;
package wave_pkg is
type t_wave_channel is record
number_of_samples : integer;
memory : h_mem_object;
end record;
type t_wave_channel_array is array(natural range <>) of t_wave_channel;
procedure open_channel(chan : out t_wave_channel);
procedure push_sample(chan : inout t_wave_channel; sample : integer);
procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array);
end package;
package body wave_pkg is
procedure open_channel(chan : out t_wave_channel) is
variable ch : t_wave_channel;
begin
register_mem_model("path", "channel", ch.memory);
ch.number_of_samples := 0;
chan := ch;
end procedure;
procedure push_sample(chan : inout t_wave_channel; sample : integer) is
variable s : integer;
begin
s := sample;
if s > 32767 then s := 32767; end if;
if s < -32768 then s := -32768; end if;
write_memory_int(chan.memory, chan.number_of_samples, s);
chan.number_of_samples := chan.number_of_samples + 1;
end procedure;
procedure write_vector_le(x : std_logic_vector; file f : t_binary_file; r : inout t_binary_file_rec) is
variable bytes : integer := (x'length + 7) / 8;
variable xa : std_logic_vector(7+bytes*8 downto 0);
begin
xa := (others => '0');
xa(x'length-1 downto 0) := x;
for i in 0 to bytes-1 loop
write_byte(f, xa(i*8+7 downto i*8), r);
end loop;
end procedure;
procedure write_int_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is
variable x_slv : std_logic_vector(31 downto 0);
begin
x_slv := std_logic_vector(to_signed(x, 32));
write_vector_le(x_slv, f, r);
end procedure;
procedure write_short_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is
variable x_slv : std_logic_vector(15 downto 0);
begin
x_slv := std_logic_vector(to_signed(x, 16));
write_vector_le(x_slv, f, r);
end procedure;
procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array) is
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
variable stat : file_open_status;
variable file_size : integer;
variable data_size : integer;
variable max_length : integer;
begin
-- open file
file_open(stat, myfile, name, write_mode);
assert (stat = open_ok)
report "Could not open file " & name & " for writing."
severity failure;
init_record(myrec);
max_length := 0;
for i in channels'range loop
if channels(i).number_of_samples > max_length then
max_length := channels(i).number_of_samples;
end if;
end loop;
data_size := (max_length * channels'length * 2);
file_size := 12 + 16 + 8 + data_size;
-- header
write_vector_le(X"46464952", myfile, myrec); -- "RIFF"
write_int_le (file_size-8, myfile, myrec);
write_vector_le(X"45564157", myfile, myrec); -- "WAVE"
-- chunk header
write_vector_le(X"20746D66", myfile, myrec); -- "fmt "
write_int_le (16, myfile, myrec);
write_short_le (1, myfile, myrec); -- compression code = uncompressed
write_short_le (channels'length, myfile, myrec);
write_int_le (rate, myfile, myrec); -- sample rate
write_int_le (rate * channels'length * 2, myfile, myrec); -- Bps
write_short_le (channels'length * 2, myfile, myrec); -- alignment
write_short_le (16, myfile, myrec); -- bits per sample
write_vector_le(X"61746164", myfile, myrec); -- "data"
write_int_le (data_size, myfile, myrec);
-- now write out all data!
for i in 0 to max_length-1 loop
for j in channels'range loop
write_short_le(read_memory_int(channels(j).memory, i), myfile, myrec);
end loop;
end loop;
purge(myfile, myrec);
file_close(myfile);
end procedure;
end;
|
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