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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc932.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s04b00x00p03n03i00932pkg is
subtype register16 is bit_vector(15 downto 0);
function "+" (l,r : bit_vector) return bit_vector;
function "-" (l,r : bit_vector) return bit_vector;
end c10s04b00x00p03n03i00932pkg;
package body c10s04b00x00p03n03i00932pkg is
function "+" (l,r : bit_vector) return bit_vector is
begin
return (B"1111010100101010");
end;
function "-" (l,r : bit_vector) return bit_vector is
begin
return (B"1111010100101010");
end;
end c10s04b00x00p03n03i00932pkg;
use work.c10s04b00x00p03n03i00932pkg.all;
ENTITY c10s04b00x00p03n03i00932ent IS
END c10s04b00x00p03n03i00932ent;
ARCHITECTURE c10s04b00x00p03n03i00932arch OF c10s04b00x00p03n03i00932ent IS
signal i_sig : register16 := B"1010_1110_1010_0011";
BEGIN
TESTING: PROCESS
BEGIN
i_sig <= i_sig - i_sig + B"1111111100000000" after 10 ns;
wait for 20 ns;
assert NOT( i_sig = (B"1111010100101010") )
report "***PASSED TEST: c10s04b00x00p03n03i00932"
severity NOTE;
assert ( i_sig = (B"1111010100101010") )
report "***FAILED TEST: c10s04b00x00p03n03i00932 - All of the declarations of a package are visible within the declarative region if the suffix of a selected name in a use clause is the word 'all'."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s04b00x00p03n03i00932arch;
|
-- NEED RESULT: ARCH00104.P1: Multi transport transactions occurred on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00104: One transport transaction occurred on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00104: Old transactions were removed on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00104
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00104(ARCH00104)
-- ENT00104_Test_Bench(ARCH00104_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00104 is
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
end ENT00104 ;
--
architecture ARCH00104 of ENT00104 is
begin
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_arr1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00104.P1" ,
"Multi transport transactions occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00104" ,
"One transport transaction occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00104" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00104" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
--
end ARCH00104 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00104_Test_Bench is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
end ENT00104_Test_Bench ;
--
architecture ARCH00104_Test_Bench of ENT00104_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00104 ( ARCH00104 ) ;
begin
CIS1 : UUT
port map (
s_st_arr1_vector
) ;
end block L1 ;
end ARCH00104_Test_Bench ;
|
--CPU
-- library declaration
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; -- basic IEEE library
use IEEE.NUMERIC_STD.ALL; -- IEEE library for the unsigned type
entity CPU is
port ( clk : in std_logic; -- Systen clock
collision : in std_logic;
reset : in std_logic;
player_x : out integer;
player_y : out integer;
input : in std_logic;
new_column : in std_logic;
gap : out integer := 60;
height : out integer := 0;
terrain_change : in std_logic;
speed : out integer;
score : out std_logic_vector(15 downto 0));
end CPU;
architecture Behavioral of CPU is
-- Signals that connect to the bus (and the bus itself)
signal data_bus : std_logic_vector(15 downto 0);
signal pc : std_logic_vector(15 downto 0) := x"0012";
signal asr : std_logic_vector(15 downto 0);
signal alu_input : signed(15 downto 0);
signal alu_res : std_logic_vector(15 downto 0);
signal res : std_logic_vector(15 downto 0);
signal ir : std_logic_vector(31 downto 0);
signal pmem_asr : std_logic_vector(15 downto 0);
signal pmem_res : std_logic_vector(15 downto 0);
-- Registers
signal reg1 : std_logic_vector(15 downto 0) := "0000000000000011";
signal reg2 : std_logic_vector(15 downto 0) := "0000000000000001";
signal reg3 : std_logic_vector(15 downto 0);
signal reg4 : std_logic_vector(15 downto 0);
-- Micro
signal micro_instr : std_logic_vector(23 downto 0);
signal micro_pc : std_logic_vector(7 downto 0) := "00000000";
-- Interrupt alerts
signal terrain_prev : std_logic;
signal terrain_alert : std_logic;
signal input_prev : std_logic;
signal press_alert : std_logic;
signal release_alert : std_logic;
signal collision_prev : std_logic;
signal collision_alert : std_logic;
signal reset_prev : std_logic;
signal reset_alert : std_logic;
signal input_release : std_logic;
-- Move player signals
signal player_upd_alert : std_logic;
signal player_upd_counter : integer := 0;
-- Interrupt states saved
signal intr_pc : std_logic_vector(15 downto 0);
signal intr_res : std_logic_vector(15 downto 0);
signal intr_alu_res : std_logic_vector(15 downto 0);
signal intr_z : std_logic;
signal intr_c : std_logic;
signal intr_n : std_logic;
signal intr_o : std_logic;
signal intr_enable : std_logic := '0';
-- ALU signals
signal alu_add : std_logic_vector(16 downto 0);
signal alu_sub : std_logic_vector(16 downto 0);
signal alu_not : std_logic_vector(15 downto 0);
signal alu_and : std_logic_vector(15 downto 0);
signal alu_or : std_logic_vector(15 downto 0);
signal alu_xor : std_logic_vector(15 downto 0);
--ran_gen signals
signal ran_nr : std_logic_vector(31 downto 0) := (others => '0');
signal ran_bit : std_logic;
-- Initial value for new_ran is seed
signal new_ran : std_logic_vector(31 downto 0) := "10101010001010110010110001010010";
-- Flags
signal n_flag : std_logic;
signal z_flag : std_logic;
signal o_flag : std_logic;
signal c_flag : std_logic;
-- Constants (Variables)
signal x_pos : std_logic_vector(15 downto 0) := x"0004";
signal y_pos : std_logic_vector(15 downto 0) := x"0005";
signal height_pos : std_logic_vector(15 downto 0) := x"0007";
signal gap_pos : std_logic_vector(15 downto 0) := x"0008";
signal player_upd : std_logic_vector(15 downto 0) := x"000C";
signal press_pos : std_logic_vector(15 downto 0) := x"000D";
signal release_pos : std_logic_vector(15 downto 0) := x"000E";
signal speed_pos : std_logic_vector(15 downto 0) := x"0011";
signal speed_internal : integer := 1000;
signal player_speed : integer;
-- Progress signals
signal progress : unsigned(15 downto 0) := (others => '0');
signal progress_counter : integer := 0; -- updates progress every second
signal PROGRESS_LATENCY : integer := 10000000; -- 1/10th second (if clock at 100MHz)
-- Score signals
signal score_counter : integer := 0;
signal SCORE_LATENCY : integer := 10000000; -- 1/10th second (if clock at 100MHz)
-- Score counters
signal ones : unsigned(3 downto 0) := (others => '0');
signal tens : unsigned(3 downto 0) := (others => '0');
signal hundreds : unsigned(3 downto 0) := (others => '0');
signal thousands : unsigned(3 downto 0) := (others => '0');
-- Alias
alias TO_BUS : std_logic_vector(3 downto 0) is micro_instr(23 downto 20); -- to bus
alias FROM_BUS : std_logic_vector(3 downto 0) is micro_instr(19 downto 16); -- from bus
alias P_BIT : std_logic is micro_instr(15); -- p bit
alias ALU_OP : std_logic_vector(2 downto 0) is micro_instr(14 downto 12); -- alu_op
alias SEQ : std_logic_vector(3 downto 0) is micro_instr(11 downto 8); -- seq
alias MICRO_ADR : std_logic_vector(7 downto 0) is micro_instr(7 downto 0); -- micro address
alias FETCH_NEXT : std_logic is ir(21);
alias OP_CODE : std_logic_vector(7 downto 0) is ir(31 downto 24);
-- Interrupt vectors
constant COLLISION_INTERRUPT_VECTOR : std_logic_vector(15 downto 0) := x"0000";
constant TERRAIN_CHANGE_INTERRUPT_VECTOR : std_logic_vector(15 downto 0) := x"0001";
constant RESET_INTERRUPT_VECTOR : std_logic_vector(15 downto 0) := x"0002";
-- Player update frequency
constant PLAYER_UPDATE_LATENCY : integer := 1400000; -- same as offset for now
constant ZERO : std_logic_vector(15 downto 0) := x"0000";
constant ONE : std_logic_vector(15 downto 0) := x"0001";
-- PMEM (Max is 65535 for 16 bit addresses)
type ram_t is array (0 to 4096) of std_logic_vector(15 downto 0);
signal pmem : ram_t := (
-- The processed assembly code is pasted here
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"3420",
x"0000",
x"1620",
x"010d",
x"3420",
x"0001",
x"1620",
x"00f5",
x"3420",
x"0002",
x"1620",
x"010d",
x"3420",
x"0004",
x"1620",
x"0096",
x"3420",
x"0005",
x"1620",
x"00c8",
x"3420",
x"0007",
x"1620",
x"000f",
x"3420",
x"0008",
x"1620",
x"001e",
x"3420",
x"0006",
x"1620",
x"0001",
x"3420",
x"0010",
x"1620",
x"0000",
x"3420",
x"0011",
x"1620",
x"01f4",
x"4500",
x"4000",
x"3420",
x"000c",
x"3620",
x"0001",
x"1F20",
x"0070",
x"3D20",
x"000a",
x"1F20",
x"004a",
x"3320",
x"003e",
x"4420",
x"0000",
x"3420",
x"0013",
x"1720",
x"0001",
x"3420",
x"0011",
x"3620",
x"012c",
x"2320",
x"005a",
x"3420",
x"0011",
x"1B20",
x"000a",
x"3420",
x"0013",
x"3620",
x"000a",
x"2120",
x"003e",
x"3420",
x"0013",
x"1620",
x"0000",
x"3420",
x"0008",
x"3620",
x"0010",
x"2320",
x"003e",
x"3420",
x"0008",
x"1B20",
x"0001",
x"3320",
x"003e",
x"3420",
x"000c",
x"1620",
x"0000",
x"3420",
x"000d",
x"3620",
x"0000",
x"1F20",
x"008a",
x"3420",
x"000e",
x"3620",
x"0000",
x"1F20",
x"00a6",
x"3420",
x"000d",
x"1620",
x"0000",
x"3420",
x"000e",
x"1620",
x"0000",
x"3320",
x"003e",
x"3420",
x"0005",
x"3620",
x"01c2",
x"3920",
x"003e",
x"3420",
x"0010",
x"3620",
x"0005",
x"2120",
x"00c2",
x"3420",
x"0010",
x"1620",
x"0000",
x"3420",
x"0006",
x"3620",
x"0003",
x"1F20",
x"00c2",
x"3420",
x"0006",
x"1720",
x"0001",
x"3320",
x"00c2",
x"3420",
x"0005",
x"3620",
x"0003",
x"2320",
x"003e",
x"3420",
x"0010",
x"3620",
x"0005",
x"2120",
x"00c2",
x"3420",
x"0010",
x"1620",
x"0000",
x"3420",
x"0006",
x"3620",
x"fffd",
x"1F20",
x"00c2",
x"3420",
x"0006",
x"1B20",
x"0001",
x"3320",
x"00c2",
x"3420",
x"0010",
x"1720",
x"0001",
x"3420",
x"0005",
x"1760",
x"0006",
x"3420",
x"000c",
x"1620",
x"0000",
x"4500",
x"3320",
x"003e",
x"3420",
x"0007",
x"3620",
x"0001",
x"1F20",
x"0147",
x"3420",
x"0007",
x"1B20",
x"0001",
x"4500",
x"3B00",
x"3320",
x"003e",
x"3420",
x"0009",
x"1660",
x"0007",
x"3420",
x"0009",
x"1760",
x"0008",
x"3420",
x"0009",
x"3620",
x"003a",
x"3920",
x"014c",
x"3420",
x"0007",
x"1720",
x"0001",
x"4500",
x"3B00",
x"3320",
x"003e",
x"3520",
x"000a",
x"3420",
x"000a",
x"2720",
x"0003",
x"3420",
x"000a",
x"1760",
x"0012",
x"3420",
x"000a",
x"3620",
x"0002",
x"2320",
x"00d1",
x"3420",
x"000a",
x"3620",
x"0003",
x"3920",
x"00df",
x"3320",
x"0146",
x"3420",
x"0003",
x"1620",
x"0001",
x"3420",
x"0007",
x"1620",
x"0000",
x"3420",
x"0008",
x"1620",
x"0041",
x"4500",
x"3420",
x"000a",
x"1620",
x"ffff",
x"3420",
x"000a",
x"3620",
x"0000",
x"1F20",
x"012a",
x"3420",
x"000a",
x"1B20",
x"0001",
x"3320",
x"011e",
x"3420",
x"0008",
x"1620",
x"001e",
x"3420",
x"0007",
x"1620",
x"000f",
x"3420",
x"0005",
x"1620",
x"0014",
x"3420",
x"0011",
x"1620",
x"01f4",
x"4500",
x"3B00",
x"3320",
x"003e",
x"3420",
x"0003",
x"1620",
x"0001",
x"3420",
x"0005",
x"1620",
x"00c8",
x"3B00",
x"3420",
x"0012",
x"1620",
x"0001",
x"3B00",
x"3420",
x"0012",
x"1620",
x"0000",
x"3B00",
x"3320",
x"003e",
x"FF00",
others => "0000000000000000");
-- micro-MEM (Max is 255 for 8 bit addresses)
type micro_mem_t is array (0 to 255) of std_logic_vector(23 downto 0);
signal micro_mem : micro_mem_t := (
-- Here are all the micro programs
"000000000000111101000001", -- check for interrupts, ASR <= PC
"000100100000000000000000", -- asr <= pc
"001100000000000000000000", -- fetch instruction (only 16 bits)
"001101100000000000000000", -- and check for 32 bit instruction
"000000001000100000010100", -- if 32 bit fetch next 16, else goto OP
"000100101000000000000000", -- asr <= pc, pc++
"001100000000000000000000", -- fetch pmem(asr)
"001101110000000000000000", -- ir(15 downto 0) <= pmem(asr)
"000000000000001000000000", -- 08:check adress mod
"001100000000000000000000", -- 09:ABSOLUTE fetch pmem(asr)
"001100100000000100000000", -- asr <= pmem(asr)
"001100000000000000000000", -- 0B:DIRECT fetch pmem(asr)
"001100100000000000000000", -- asr <= pmem(asr)
"001100000000000000000000", -- fetch pmem(asr)
"001100100000000100000000", -- asr <= pmem(asr)
"001100000000000000000000", -- 0F:INDIRECT fetch pmem(asr)
"001100100000000000000000", -- asr <= pmem(asr)
"001100000000000000000000", -- fetch pmem(asr)
"001100100000000000000000", -- asr <= pmem(asr)
"001100000000000000000000", -- fetch pmem(asr)
"001100100000000100000000", -- asr <= pmem(asr)
"000000000000000100000000", -- 15:OP micro_pc <= OP
"001011000000001100000000", -- 16:mv pmem(res) <= asr
"110000000000000000000000", -- 17:add fetch pmem(res)
"110001000000000000000000", -- alu_res <= pmem(res)
"001000000001000000000000", -- alu_res += asr
"010011000000001100000000", -- pmem(res) <= alu_res
"110000000000000000000000", -- 1B:sub fetch pmem(res)
"110001000000000000000000", -- alu_res <= pmem(res)
"001000000010000000000000", -- alu_res -= asr
"010011000000001100000000", -- pmem(res) <= alu_res
"000000000000010100000000", -- 1F:beq if z = 0: u_pc <= 0
"001000010000001100000000", -- PC <= asr
"000000000000011100000000", -- 21:bne if z = 1: u_pc <= 0
"001000010000001100000000", -- PC <= asr
"000000000000100100000000", -- 23:bn if n = 0: u_pc <= 0
"001000010000001100000000", -- PC <= asr
"001000000011000000000000", -- 25:not alu_res <= not asr
"010011000000001100000000", -- pmem(res) <= alu_res
"110000000000000000000000", -- 27:and fetch pmem(res)
"110001000000000000000000", -- alu_res <= pmem(res)
"001000000100000000000000", -- alu_res <= alu_res and asr
"010011000000001100000000", -- pmem(res) <= alu_res
"110000000000000000000000", -- 2B:or fetch pmem(res)
"110001000000000000000000", -- alu_res <= pmem(res)
"001000000101000000000000", -- alu_res <= alu_res or asr
"010011000000001100000000", -- pmem(res) <= alu_res
"110000000000000000000000", -- 2F:xor fetch pmem(res)
"110001000000000000000000", -- alu_res <= pmem(res)
"001000000110000000000000", -- alu_res = alu_res xor asr
"010011000000001100000000", -- pmem(res) <= alu_res
"001000010000001100000000", -- 33:jmp PC <= asr
"001001010000001100000000", -- 34:res res <= asr (load res)
"110100110000001100000000", -- 35:ran pmem(asr) <= rand_nr
"110000000000000000000000", -- 36:cmp fetch pmem(res)
"110001000000000000000000", -- alu_res <= pmem(res)
"001000000010001100000000", -- alu_res <= alu_res - asr
"000000000000011000000000", -- 39:bp if n = 1: u_pc <= 0
"001000010000001100000000", -- PC <= asr
"000000000000101000000000", -- 3B:rfi (return from interrupt)
"000000000000001100000000", -- micro_pc <= 0
"111000000000000000000000", -- 3D:pcmp fetch progress
"111001000000000000000000", -- alu_res <= progress
"001000000010001100000000", -- alu_res <= alu_res - asr
"000000000000110000000000", -- 40:eint enable interrupts
"000100100000000000000000", -- 41:intr asr <= pc
"001100000000000000000000", -- fetch pmem(asr)
"001100010000010000000001", -- pc <= pmem(asr), micro_pc <= 1
"001011100000000000000000", -- 44:lprg progress <= asr
-- NOTE: place all new micro programs above upd, in case update needs to...update
"000000000000000000000001", -- 45:upd player_x <= pmem(x_pos)
"000000000000000000000010", -- player_y <= pmem(y_pos)
"000000000000000000000011", -- height <= pmem(height_pos)
"000000000000000000000100", -- gap <= pmem(gap_pos)
"000000000000000000000101", -- speed <= pmem(speed_pos)
"000000000000001100000000", -- micro_pc <= 0
others => "000000000000000000000000");
-- ROM (mod) (Includes all 4 mods, need to be updated with correct micro-addresses)
type mod_rom_t is array (0 to 3) of std_logic_vector(7 downto 0);
constant mod_rom : mod_rom_t := (x"09", x"0B", x"0F", x"00");
begin -- Behavioral
-- fetching micro_instr
micro_instr <= micro_mem(to_integer(unsigned(micro_pc)));
-- Speed
speed <= speed_internal;
-- Score
score(15 downto 12) <= std_logic_vector(thousands);
score(11 downto 8) <= std_logic_vector(hundreds);
score(7 downto 4) <= std_logic_vector(tens);
score(3 downto 0) <= std_logic_vector(ones);
-- Update
process(clk)
begin
if rising_edge(clk) then
-- Put the information from pmem on the correct signals
-- (this makes sure vga_motor and pic_mem has the correct information
-- for drawing on the screen)
if micro_instr = "000000000000000000000001" then
player_x <= to_integer(unsigned(pmem(to_integer(unsigned(x_pos)))));
elsif micro_instr = "000000000000000000000010" then
player_y <= to_integer(unsigned(pmem(to_integer(unsigned(y_pos)))));
elsif micro_instr = "000000000000000000000011" then
height <= to_integer(unsigned(pmem(to_integer(unsigned(height_pos)))));
elsif micro_instr = "000000000000000000000100" then
gap <= to_integer(unsigned(pmem(to_integer(unsigned(gap_pos)))));
elsif micro_instr = "000000000000000000000101" then
speed_internal <= to_integer(unsigned(pmem(to_integer(unsigned(speed_pos)))));
end if;
end if;
end process;
-- pc
process(clk)
begin
if rising_edge(clk) then
-- pc to bus
if FROM_BUS = "0001" then
pc <= data_bus;
-- pc++
elsif P_BIT = '1' then
pc <= std_logic_vector(unsigned(pc) + 1);
-- Handle interrupts
elsif SEQ = "1111" and intr_enable = '1' then
-- Store important information to be returned after the interrupt
intr_pc <= pc;
intr_res <= res;
intr_alu_res <= alu_res;
intr_z <= z_flag;
intr_n <= n_flag;
intr_o <= o_flag;
intr_c <= c_flag;
-- Set pc to the correct interrupt vector and disables interrupts
-- (interrupts are enabled after the specific interrupt code has been run)
if reset_alert = '1' then
intr_enable <= '0';
reset_alert <= '0';
pc <= RESET_INTERRUPT_VECTOR;
elsif collision_alert = '1' then
intr_enable <= '0';
collision_alert <= '0';
pc <= COLLISION_INTERRUPT_VECTOR;
elsif terrain_alert = '1' then
intr_enable <= '0';
terrain_alert <= '0';
pc <= TERRAIN_CHANGE_INTERRUPT_VECTOR;
end if;
-- Return from interrupt: enable interrupts and restore pc
elsif SEQ = "1010" then
intr_enable <= '1';
pc <= intr_pc;
-- Enable interrupts
elsif SEQ = "1100" then
intr_enable <= '1';
end if;
-- Check if the terrain needs to update
if terrain_change = '1' and terrain_prev = '0' then
terrain_alert <= '1';
end if;
-- Check if there has been a collision
if collision = '1' and collision_prev = '0' then
collision_alert <= '1';
end if;
-- Check if the reset button has been pressed
if reset = '1' and reset_prev = '0' then
reset_alert <= '1';
end if;
-- Keep track of previous
terrain_prev <= terrain_change;
collision_prev <= collision;
reset_prev <= reset;
end if;
end process;
-- asr
process(clk)
begin
if rising_edge(clk) then
-- from bus to asr
if FROM_BUS = "0010" then
asr <= data_bus;
end if;
end if;
end process;
-- pmem
process(clk)
begin
if rising_edge(clk) then
-- from bus to pmem(asr)
if FROM_BUS = "0011" then
pmem(to_integer(unsigned(asr))) <= data_bus;
-- from bus to pmem(res)
elsif FROM_BUS = "1100" then
pmem(to_integer(unsigned(res))) <= data_bus;
-- from pmem(asr) to pmem_asr (can be put on bus next clock cycle)
elsif TO_BUS = "0011" then
pmem_asr <= pmem(to_integer(unsigned(asr)));
-- from pmem(res) to pmem_res (can be put on bus next clock cycle)
elsif TO_BUS = "1100" then
pmem_res <= pmem(to_integer(unsigned(res)));
-- Write to memory if the player position needs to update
elsif player_upd_alert = '1' then
player_upd_alert <= '0';
pmem(to_integer(unsigned(player_upd))) <= ONE;
-- Write to memory if the spacebar has been released
elsif release_alert = '1' then
release_alert <= '0';
pmem(to_integer(unsigned(release_pos))) <= ONE;
-- Write to memory if the spacebar has been pressed
elsif press_alert = '1' then
press_alert <= '0';
pmem(to_integer(unsigned(press_pos))) <= ONE;
end if;
-- Creates a delay (based on speed) which decides when the player position
-- should update
if player_upd_counter >= player_speed then
player_upd_alert <= '1';
player_upd_counter <= 0;
else
player_upd_counter <= player_upd_counter + 1;
end if;
-- Check if the spacebar has been pressed
if input = '1' and input_prev = '0' then
press_alert <= '1';
end if;
-- Check if the spacebar has been released
if input = '0' and input_prev = '1' then
release_alert <= '1';
end if;
input_prev <= input;
end if;
end process;
-- Makes sure that the player speed gets faster as speed increases,
-- but not as fast as the terrain speed increases
player_speed <= (speed_internal*1000) + ((1000-speed_internal)*900);
-- progress
process(clk)
begin
if rising_edge(clk) then
-- bus to progress, reset progress_counter
if FROM_BUS = "1110" then
progress <= unsigned(data_bus);
progress_counter <= 0;
-- Increases progress every second (on a 100MHz clock)
elsif progress_counter = PROGRESS_LATENCY then
progress <= progress + 1;
progress_counter <= 0;
else
progress_counter <= progress_counter + 1;
end if;
end if;
end process;
-- score
process(clk)
begin
if rising_edge(clk) then
-- Reset score if there is a collision or if the game is reset
if reset = '1' or collision = '1' then
thousands <= (others => '0');
hundreds <= (others => '0');
tens <= (others => '0');
ones <= (others => '0');
score_counter <= 0;
-- Keep counting score up every 1/10th of a second
elsif score_counter = SCORE_LATENCY then
score_counter <= 0;
if ones = "1001" then
if tens = "1001" then
if hundreds = "1001" then
-- resets score if score is 9999
if thousands = "1001" then
thousands <= (others => '0');
hundreds <= (others => '0');
tens <= (others => '0');
ones <= (others => '0');
else
thousands <= thousands + 1;
hundreds <= (others => '0');
tens <= (others => '0');
ones <= (others => '0');
end if;
else
hundreds <= hundreds + 1;
tens <= (others => '0');
ones <= (others => '0');
end if;
else
tens <= tens + 1;
ones <= (others => '0');
end if;
else
ones <= ones + 1;
end if;
else
score_counter <= score_counter + 1;
end if;
end if;
end process;
-- res
process(clk)
begin
if rising_edge(clk) then
-- from bus to res
if FROM_BUS = "0101" then
res <= data_bus;
-- Return from interrupt: restore res
elsif SEQ = "1010" then
res <= intr_res;
end if;
end if;
end process;
-- from bus to ir
process(clk)
begin
if rising_edge(clk) then
-- from bus to ir(31->16)
if FROM_BUS = "0110" then
ir(31 downto 16) <= data_bus;
-- from bus to ir(15->0)
elsif FROM_BUS = "0111" then
ir(15 downto 0) <= data_bus;
end if;
end if;
end process;
-- from bus to reg1
process(clk)
begin
if rising_edge(clk) then
if FROM_BUS = "1000" then
reg1 <= data_bus;
end if;
end if;
end process;
-- from bus to reg2
process(clk)
begin
if rising_edge(clk) then
if FROM_BUS = "1001" then
reg2 <= data_bus;
end if;
end if;
end process;
-- from bus to reg3
process(clk)
begin
if rising_edge(clk) then
if FROM_BUS = "1010" then
reg3 <= data_bus;
end if;
end if;
end process;
-- from bus to reg4
process(clk)
begin
if rising_edge(clk) then
if FROM_BUS = "1011" then
reg4 <= data_bus;
end if;
end if;
end process;
-- Moving data TO the bus
with TO_BUS select
data_bus <= pc when "0001",
asr when "0010",
pmem_asr when "0011",
alu_res when "0100",
res when "0101",
ir(31 downto 16) when "0110",
ir(15 downto 0) when "0111",
reg1 when "1000",
reg2 when "1001",
reg3 when "1010",
reg4 when "1011",
pmem_res when "1100",
ran_nr(31 downto 16) when "1101",
std_logic_vector(progress) when "1110",
data_bus when others;
-- micro_pc
process(clk)
begin
if rising_edge(clk) then
if SEQ = "0000" then -- micro_pc += 1
micro_pc <= std_logic_vector(unsigned(micro_pc) + 1);
elsif SEQ = "0001" then -- micro_pc = op
micro_pc <= ir(31 downto 24);
elsif SEQ = "0010" then --micro_pc = mod
micro_pc <= mod_rom(to_integer(unsigned(ir(23 downto 22))));
elsif SEQ = "0011" then --micro_pc = 0
micro_pc <= "00000000";
elsif SEQ = "0100" then -- jmp
micro_pc <= MICRO_ADR;
elsif SEQ = "0101" then --jmp if Z = 1 --BEQ--
if z_flag = '0' then
micro_pc <= MICRO_ADR;
else
micro_pc <= std_logic_vector(unsigned(micro_pc) + 1);
end if;
elsif SEQ = "0110" then --jmp if N = 0 --BP--
if n_flag = '1' then
micro_pc <= MICRO_ADR;
else
micro_pc <= std_logic_vector(unsigned(micro_pc) + 1);
end if;
elsif SEQ = "0111" then --jmp if Z = 0 --BNE--
if z_flag = '1' then
micro_pc <= MICRO_ADR;
else
micro_pc <= std_logic_vector(unsigned(micro_pc) + 1);
end if;
elsif SEQ = "1000" then --check for 16 bit inst
if FETCH_NEXT = '0' then
micro_pc <= MICRO_ADR;
else
micro_pc <= std_logic_vector(unsigned(micro_pc) + 1);
end if;
elsif SEQ = "1001" then --jmp if N = 1 --BN--
if n_flag = '0' then
micro_pc <= MICRO_ADR;
else
micro_pc <= std_logic_vector(unsigned(micro_pc) + 1);
end if;
-- Jump to the interrupt micro program if there's an interrupt and
-- interrupts are enabled
elsif SEQ = "1111" then
if intr_enable = '1' then
if (reset_alert = '1') or (collision_alert = '1') or (terrain_alert = '1') then
micro_pc <= MICRO_ADR;
else
micro_pc <= std_logic_vector(unsigned(micro_pc) + 1);
end if;
else
micro_pc <= std_logic_vector(unsigned(micro_pc) + 1);
end if;
-- Fetch new instruction when returning from interrupt
elsif SEQ = "1100" then
micro_pc <= MICRO_ADR; -- MICRO_ADR will be 0
elsif SEQ = "1010" then
micro_pc <= std_logic_vector(unsigned(micro_pc) + 1);
else
micro_pc <= micro_pc;
end if;
end if;
end process;
-- alu combinatorics
alu_add <= std_logic_vector(signed(alu_res(15) & alu_res) + signed(data_bus(15) & data_bus));
alu_sub <= std_logic_vector(signed(alu_res(15) & alu_res) - signed(data_bus(15) & data_bus));
alu_not <= not data_bus;
alu_and <= alu_res and data_bus;
alu_or <= alu_res or data_bus;
alu_xor <= alu_res xor data_bus;
-- alu_res
process(clk)
begin
if rising_edge(clk) then
case ALU_OP is
when "001" => -- ADD
alu_res <= alu_add(15 downto 0);
if alu_add = "00000000000000000" then -- z_flag
z_flag <= '1';
else
z_flag <= '0';
end if;
n_flag <= alu_add(15); -- n_flag
c_flag <= alu_add(16); -- c_flag
if alu_res(15) = data_bus(15) then -- o_flag
if alu_res(15) = '0' and data_bus(15) = '0' and alu_add(15) = '1' then
o_flag <= '1';
elsif alu_res(15) = '1' and data_bus(15) = '1' and alu_add(15) = '0' then
o_flag <= '1';
else
o_flag <= '0';
end if;
else
o_flag <= '0';
end if;
when "010" => -- SUB
alu_res <= alu_sub(15 downto 0);
if alu_sub = "00000000000000000" then -- z_flag
z_flag <= '1';
else
z_flag <= '0';
end if;
n_flag <= alu_sub(15); -- n_flag
c_flag <= '0'; -- c_flag (no meaning when subtracting)
if alu_res(15) /= data_bus(15) then -- o_flag
if (alu_res(15) = '0' and data_bus(15) = '1' and alu_sub(15) = '1') then
o_flag <= '1';
elsif alu_res(15) = '1' and data_bus(15) = '0' and alu_sub(15) = '0' then
o_flag <= '1';
else
o_flag <= '0';
end if;
else
o_flag <= '0';
end if;
when "011" =>
alu_res <= alu_not; --NOT
if alu_not = "0000000000000000" then -- z_flag
z_flag <= '1';
else
z_flag <= '0';
end if;
when "100" =>
alu_res <= alu_and; --AND
if alu_and = "0000000000000000" then -- z_flag
z_flag <= '1';
else
z_flag <= '0';
end if;
n_flag <= alu_and(15);
o_flag <= '0';
c_flag <= '0';
when "101" =>
alu_res <= alu_or; --OR
if alu_or = "0000000000000000" then -- z_flag
z_flag <= '1';
else
z_flag <= '0';
end if;
n_flag <= alu_or(15);
o_flag <= '0';
c_flag <= '0';
when "110" =>
alu_res <= alu_xor; --XOR
if alu_xor = "0000000000000000" then -- z_flag
z_flag <= '1';
else
z_flag <= '0';
end if;
n_flag <= alu_xor(15);
o_flag <= '0';
c_flag <= '0';
when others =>
if FROM_BUS = "0100" then
alu_res <= data_bus;
-- Return from interrupt: restore all flags and alu_res
elsif SEQ = "1010" then
alu_res <= intr_alu_res;
z_flag <= intr_z;
n_flag <= intr_n;
o_flag <= intr_o;
c_flag <= intr_c;
else
alu_res <= alu_res;
end if;
n_flag <= n_flag;
o_flag <= o_flag;
c_flag <= c_flag;
z_flag <= z_flag;
end case;
end if;
end process;
--ran_gen
ran_bit <= new_ran(31) xor new_ran(29) xor new_ran(25) xor new_ran(24);
ran_nr <= new_ran;
process(clk)
begin
if rising_edge(clk) then
new_ran(31 downto 1) <= new_ran(30 downto 0);
new_ran(0) <= ran_bit;
end if;
end process;
end Behavioral;
|
-- CAN 2.0 interface
constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
constant CFG_CANLOOP : integer := CONFIG_CANLOOP;
constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
constant CFG_CANFT : integer := CONFIG_CAN_FT;
|
-- CAN 2.0 interface
constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
constant CFG_CANLOOP : integer := CONFIG_CANLOOP;
constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
constant CFG_CANFT : integer := CONFIG_CAN_FT;
|
-- CAN 2.0 interface
constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
constant CFG_CANLOOP : integer := CONFIG_CANLOOP;
constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
constant CFG_CANFT : integer := CONFIG_CAN_FT;
|
-- CAN 2.0 interface
constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
constant CFG_CANLOOP : integer := CONFIG_CANLOOP;
constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
constant CFG_CANFT : integer := CONFIG_CAN_FT;
|
-- CAN 2.0 interface
constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
constant CFG_CANLOOP : integer := CONFIG_CANLOOP;
constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
constant CFG_CANFT : integer := CONFIG_CAN_FT;
|
-- CAN 2.0 interface
constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
constant CFG_CANLOOP : integer := CONFIG_CANLOOP;
constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
constant CFG_CANFT : integer := CONFIG_CAN_FT;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: byte_data_ram.vhd
-- Version: v3.0
-- Description: This file is a DPRAM which got used in the design for the
-- endpoint configuration and status register space along with
-- default endpoint buffer space & end point 1-7 buffer space
-- using the generics (C_DPRAM_DEPTH and C_ADDR_LINES)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- Structure:
-- -- axi_usb2_device.vhd
-- -- axi_slave_burst.vhd
-- -- usbcore.v
-- -- ipic_if.vhd
-- -- byte_data_ram.vhd
-------------------------------------------------------------------------------
-- Author: PBB
-- History:
-- PBB 07/01/10 initial release
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library proc_common_v4_0;
use proc_common_v4_0.family.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- Data width
-- C_DPRAM_DEPTH -- Depth of the DPRAM
-- C_ADDR_LINES -- No of Address lines
-- C_IVR_RESET_VALUE -- Reset values of IVR registers in RAM
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Addra -- Port-A address
-- Addrb -- Port-B address
-- Clka -- Port-A clock
-- Clkb -- Port-B clock
-- Dina -- Port-A data input
-- Dinb -- Port-B data input
-- Ena -- Port-A chip enable
-- Enb -- Port-B chip enable
-- Wea -- Port-A write enable
-- Web -- Port-B write enable
-- Douta -- Port-A data output
-- Doutb -- Port-B data output
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity shared_ram_ivar IS
generic
(
C_WIDTH : integer := 32;
C_DPRAM_DEPTH : integer range 16 to 4096 := 16;
C_ADDR_LINES : integer range 0 to 15 := 4;
-- IVR Reset value parameter
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000"
);
port
(
Addra : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Addrb : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Clka : in std_logic;
Clkb : in std_logic;
Dina : in std_logic_VECTOR((C_WIDTH-1) downto 0);
Wea : in std_logic;
Douta : out std_logic_VECTOR((C_WIDTH-1) downto 0);
Doutb : out std_logic_VECTOR((C_WIDTH-1) downto 0)
);
end shared_ram_ivar;
architecture byte_data_ram_a of shared_ram_ivar is
type ramType is array (0 to C_DPRAM_DEPTH-1) of std_logic_vector
((C_WIDTH-1) downto 0);
--shared variable ram: ramType := (others => (others => '0'));
signal ram: ramType := (others => C_IVAR_RESET_VALUE);
attribute ram_style : string;
attribute ram_style of ram : signal is "distributed";
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- DPRAM Port A Interface
-------------------------------------------------------------------------------
PORT_A_PROCESS: process(Clka)
begin
if Clka'event and Clka = '1' then
if (Wea = '1') then
ram(conv_integer(Addra)) <= Dina;
end if;
Douta <= ram(conv_integer(Addra));
end if;
end process;
-------------------------------------------------------------------------------
-- DPRAM Port B Interface
-------------------------------------------------------------------------------
PORT_B_PROCESS: process(Clkb)
begin
if Clkb'event and Clkb = '1' then
Doutb <= ram(conv_integer(Addrb));
end if;
end process;
end byte_data_ram_a;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package codec_8b10b_pack is
subtype b8_t is std_ulogic_vector(7 downto 0);
subtype b10_t is std_ulogic_vector(9 downto 0);
type rd_t is (undef, plus1, minus1);
procedure data_8b10b(
b8_i : in b8_t;
rd_i : in rd_t;
b10_o : out b10_t;
rd_o : out rd_t);
end;
package body codec_8b10b_pack is
type rd_change_t is (undef, minus2, unchanged, plus2);
function to_rd_change(n : integer) return rd_change_t is
begin
case n is
when -2 => return minus2;
when 0 => return unchanged;
when 2 => return plus2;
when others => return undef;
end case;
end;
function "+"(rd : rd_t; rd_change : rd_change_t) return rd_t is
begin
case rd_change is
when unchanged => return rd;
when minus2 =>
if rd = plus1 then return minus1;
else return undef;
end if;
when plus2 =>
if rd = minus1 then return plus1;
else return undef;
end if;
when undef => return undef;
end case;
end;
function rd_change(d : std_ulogic_vector) return rd_change_t is
variable n : integer;
begin
n := 0;
for i in d'range loop
case to_x01(d(i)) is
when '0' => n := n - 1;
when '1' => n := n + 1;
when others =>
return undef;
end case;
end loop;
return to_rd_change(n);
end;
subtype b5_t is std_ulogic_vector(4 downto 0);
subtype b6_t is std_ulogic_vector(5 downto 0);
type code_5b6b_t is array(0 to 1) of b6_t;
type table_5b6b_t is array(0 to 31) of code_5b6b_t;
constant table_5b6b : table_5b6b_t := (
0 => (0 => "100111", 1 => "011000"),
1 => (0 => "011101", 1 => "100010"),
2 => (0 => "101101", 1 => "010010"),
3 => (0 => "110001", 1 => "110001"),
4 => (0 => "110101", 1 => "001010"),
5 => (0 => "101001", 1 => "101001"),
6 => (0 => "011001", 1 => "011001"),
7 => (0 => "111000", 1 => "000111"),
8 => (0 => "111001", 1 => "000110"),
9 => (0 => "100101", 1 => "100101"),
10 => (0 => "010101", 1 => "010101"),
11 => (0 => "110100", 1 => "110100"),
12 => (0 => "001101", 1 => "001101"),
13 => (0 => "101100", 1 => "101100"),
14 => (0 => "011100", 1 => "011100"),
15 => (0 => "010111", 1 => "101000"),
16 => (0 => "011011", 1 => "100100"),
17 => (0 => "100011", 1 => "100011"),
18 => (0 => "010011", 1 => "010011"),
19 => (0 => "110010", 1 => "110010"),
20 => (0 => "001011", 1 => "001011"),
21 => (0 => "101010", 1 => "101010"),
22 => (0 => "011010", 1 => "011010"),
23 => (0 => "111010", 1 => "000101"),
24 => (0 => "110011", 1 => "001100"),
25 => (0 => "100110", 1 => "100110"),
26 => (0 => "010110", 1 => "010110"),
27 => (0 => "110110", 1 => "001001"),
28 => (0 => "001110", 1 => "001110"),
29 => (0 => "101110", 1 => "010001"),
30 => (0 => "011110", 1 => "100001"),
31 => (0 => "101011", 1 => "010100"));
procedure data_5b6b(
b5_i : in b5_t;
rd_i : in rd_t;
b6_o : out b6_t;
rd_o : out rd_t) is
variable b6 : b6_t;
begin
case rd_i is
when minus1 => b6 := table_5b6b(to_integer(unsigned(b5_i)))(0);
when plus1 => b6 := table_5b6b(to_integer(unsigned(b5_i)))(1);
when others =>
b6_o := (others => 'X');
rd_o := undef;
return;
end case;
b6_o := b6;
rd_o := rd_i + rd_change(b6);
end;
function data_6b5b(b6_i : in b6_t) return b5_t is
begin
for i in table_5b6b'range loop
if b6_i = table_5b6b(i)(0) or b6_i = table_5b6b(i)(1) then
return b5_t(to_unsigned(i, 5));
end if;
end loop;
return (others => 'X');
end;
subtype b3_t is std_ulogic_vector(2 downto 0);
subtype b4_t is std_ulogic_vector(3 downto 0);
type code_3b4b_t is array(0 to 1) of b4_t;
type table_3b4b_t is array(0 to 7) of code_3b4b_t;
constant table_3b4b : table_3b4b_t := (
0 => (0 => "1011", 1 => "0100"),
1 => (0 => "1001", 1 => "1001"),
2 => (0 => "0101", 1 => "0101"),
3 => (0 => "1100", 1 => "0011"),
4 => (0 => "1101", 1 => "0010"),
5 => (0 => "1010", 1 => "1010"),
6 => (0 => "0110", 1 => "0110"),
-- 7 is a special case, handle in code
7 => (0 => "XXXX", 1 => "XXXX"));
procedure data_3b4b(
b3_i : in b3_t;
b6_i : in b6_t;
rd_i : in rd_t;
b4_o : out b4_t;
rd_o : out rd_t) is
variable b4 : b4_t;
begin
b4 := (others => 'X');
if not is_x(b3_i) then
case rd_i is
when minus1 =>
if b3_i = "111" then
case b6_i(0) is
when '0' => b4 := "1110";
when '1' => b4 := "0111";
when others => null;
end case;
else
b4 := table_3b4b(to_integer(unsigned(b3_i)))(0);
end if;
when plus1 =>
if b3_i = "111" then
case b6_i(0) is
when '0' => b4 := "1000";
when '1' => b4 := "0001";
when others => null;
end case;
else
b4 := table_3b4b(to_integer(unsigned(b3_i)))(1);
end if;
when others => null;
end case;
end if;
b4_o := b4;
rd_o := rd_i + rd_change(b4);
end procedure;
procedure data_8b10b(
b8_i : in b8_t;
rd_i : in rd_t;
b10_o : out b10_t;
rd_o : out rd_t) is
variable b6 : b6_t;
variable b4 : b4_t;
variable rd : rd_t;
begin
data_5b6b(b8_i(4 downto 0), rd_i, b6, rd);
data_3b4b(b8_i(7 downto 5), b6, rd, b4, rd_o);
b10_o := b6 & b4;
end;
end; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_11 is
end entity inline_11;
----------------------------------------------------------------
architecture test of inline_11 is
component comp is
end component comp;
signal clk_phase1, clk_phase2 : bit;
-- code from book:
group signal_pair is (signal, signal);
group clock_pair : signal_pair ( clk_phase1, clk_phase2 );
attribute max_skew : time;
attribute max_skew of clock_pair : group is 200 ps;
group component_instances is ( label <> );
group U1 : component_instances ( nand1, nand2, nand3 );
group U2 : component_instances ( inv1, inv2 );
attribute IC_allocation : string;
attribute IC_allocation of U1 : group is "74LS00";
attribute IC_allocation of U2 : group is "74LS04";
-- end of code from book
begin
nand1 : component comp;
nand2 : component comp;
nand3 : component comp;
inv1 : component comp;
inv2 : component comp;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_11 is
end entity inline_11;
----------------------------------------------------------------
architecture test of inline_11 is
component comp is
end component comp;
signal clk_phase1, clk_phase2 : bit;
-- code from book:
group signal_pair is (signal, signal);
group clock_pair : signal_pair ( clk_phase1, clk_phase2 );
attribute max_skew : time;
attribute max_skew of clock_pair : group is 200 ps;
group component_instances is ( label <> );
group U1 : component_instances ( nand1, nand2, nand3 );
group U2 : component_instances ( inv1, inv2 );
attribute IC_allocation : string;
attribute IC_allocation of U1 : group is "74LS00";
attribute IC_allocation of U2 : group is "74LS04";
-- end of code from book
begin
nand1 : component comp;
nand2 : component comp;
nand3 : component comp;
inv1 : component comp;
inv2 : component comp;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_11 is
end entity inline_11;
----------------------------------------------------------------
architecture test of inline_11 is
component comp is
end component comp;
signal clk_phase1, clk_phase2 : bit;
-- code from book:
group signal_pair is (signal, signal);
group clock_pair : signal_pair ( clk_phase1, clk_phase2 );
attribute max_skew : time;
attribute max_skew of clock_pair : group is 200 ps;
group component_instances is ( label <> );
group U1 : component_instances ( nand1, nand2, nand3 );
group U2 : component_instances ( inv1, inv2 );
attribute IC_allocation : string;
attribute IC_allocation of U1 : group is "74LS00";
attribute IC_allocation of U2 : group is "74LS04";
-- end of code from book
begin
nand1 : component comp;
nand2 : component comp;
nand3 : component comp;
inv1 : component comp;
inv2 : component comp;
end architecture test;
|
library verilog;
use verilog.vl_types.all;
entity rs is
port(
clock : in vl_logic;
rs_free : out vl_logic;
rs_lok : out vl_logic;
rs_sok : out vl_logic;
rg_ok : out vl_logic;
rg_num : in vl_logic_vector(4 downto 0);
rg_check : in vl_logic;
in_op : in vl_logic_vector(31 downto 0);
in_address : in vl_logic_vector(31 downto 0);
in_reg : in vl_logic_vector(4 downto 0);
in_reg2 : in vl_logic_vector(4 downto 0);
write : in vl_logic;
out_dst : out vl_logic_vector(4 downto 0);
out_dst_data : out vl_logic_vector(31 downto 0);
write_dst : out vl_logic;
in_databus : in vl_logic_vector(63 downto 0);
out_databus : out vl_logic_vector(63 downto 0);
write_databus : out vl_logic
);
end rs;
|
library verilog;
use verilog.vl_types.all;
entity rs is
port(
clock : in vl_logic;
rs_free : out vl_logic;
rs_lok : out vl_logic;
rs_sok : out vl_logic;
rg_ok : out vl_logic;
rg_num : in vl_logic_vector(4 downto 0);
rg_check : in vl_logic;
in_op : in vl_logic_vector(31 downto 0);
in_address : in vl_logic_vector(31 downto 0);
in_reg : in vl_logic_vector(4 downto 0);
in_reg2 : in vl_logic_vector(4 downto 0);
write : in vl_logic;
out_dst : out vl_logic_vector(4 downto 0);
out_dst_data : out vl_logic_vector(31 downto 0);
write_dst : out vl_logic;
in_databus : in vl_logic_vector(63 downto 0);
out_databus : out vl_logic_vector(63 downto 0);
write_databus : out vl_logic
);
end rs;
|
library IEEE;
use ieee.std_logic_1164.all;
entity cnt is
port(
rst: in std_logic;
T: in std_logic;
Q: out std_logic_vector(3 downto 0)
);
end entity;
architecture cnt of cnt is
component tc_trig is
port(T: in std_logic;
C: in std_logic;
R: in std_logic;
Q, notQ: out std_logic);
end component;
signal sQ: std_logic_vector(3 downto 0);
signal not_sQ: std_logic_vector(3 downto 0);
begin
tr0: tc_trig port map(C => T, T => '1', Q => sQ(0), notQ => not_sQ(0), R => rst);
tr1: tc_trig port map(C => not_sQ(0), T => '1', Q => sQ(1), notQ => not_sQ(1), R => rst);
tr2: tc_trig port map(C => not_sQ(1), T => '1', Q => sQ(2), notQ => not_sQ(2), R => rst);
tr3: tc_trig port map(C => not_sQ(2), T => '1', Q => sQ(3), notQ => not_sQ(3), R => rst);
Q <= sQ;
end architecture; |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of vgca_top
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:40:14 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vgca_top-struct-a.vhd,v 1.2 2004/08/18 10:46:56 wig Exp $
-- $Date: 2004/08/18 10:46:56 $
-- $Log: vgca_top-struct-a.vhd,v $
-- Revision 1.2 2004/08/18 10:46:56 wig
-- reworked some testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of vgca_top
--
architecture struct of vgca_top is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--__I_COMPONENT_NOCOMPDEC__ i_adc
--__I_COMPONENT_NOCOMPDEC__ i_cadc
--__I_COMPONENT_NOCOMPDEC__ i_dac
component padframe --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_dcs_shell --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_mcc_shell --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_tc --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for i_adc
i_adc: vgca_video_adcs
;
-- End of Generated Instance Port Map for i_adc
-- Generated Instance Port Map for i_cadc
i_cadc: vgca_cadc8_vin6
;
-- End of Generated Instance Port Map for i_cadc
-- Generated Instance Port Map for i_dac
i_dac: vgca_dac
;
-- End of Generated Instance Port Map for i_dac
-- Generated Instance Port Map for i_padframe
i_padframe: padframe
;
-- End of Generated Instance Port Map for i_padframe
-- Generated Instance Port Map for i_vgca
i_vgca: vgca
;
-- End of Generated Instance Port Map for i_vgca
-- Generated Instance Port Map for i_vgca_dcs_shell
i_vgca_dcs_shell: vgca_dcs_shell
;
-- End of Generated Instance Port Map for i_vgca_dcs_shell
-- Generated Instance Port Map for i_vgca_mcc_shell
i_vgca_mcc_shell: vgca_mcc_shell
;
-- End of Generated Instance Port Map for i_vgca_mcc_shell
-- Generated Instance Port Map for i_vgca_tc
i_vgca_tc: vgca_tc
;
-- End of Generated Instance Port Map for i_vgca_tc
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- entity that contains an FSM to decode midi type 1 files such that the FPGA can
-- play them
--
-- Determines if a file that has been sent to midi_ram is actually a midi file.
--
-- Reads the following data:
-- * number of tracks
-- * address and length of each track
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
use virtual_button_lib.button_pkg.all;
use virtual_button_lib.midi_pkg.all;
entity midi_decoder is
generic(
max_read_bytes : integer
);
port(
ctrl : in ctrl_t;
buttons : in button_arr;
-- ram read interface
read_start_addr : out unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0) := (others => '0');
read_num_bytes : out integer range 0 to max_read_bytes;
read_en : out std_logic;
read_busy : in std_logic;
midi_ram_out : in std_logic_vector((max_read_bytes * 8) - 1 downto 0);
contents_count : in natural range 0 to midi_file_rx_bram_depth;
chunk_data : out chunk_data_t_arr;
num_chunks : out integer range 0 to max_num_tracks - 1;
enable_decoder : out std_logic;
errors : out errors_t;
playing_en : out std_logic
);
end;
architecture rtl of midi_decoder is
signal read_start_addr_int : unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
signal enable_decoder_int : std_logic;
signal read_num_bytes_int : integer range 0 to max_read_bytes;
type midi_decoder_state_t is (
initial_wait,
read_chunk_header_1,
read_chunk_header_2,
read_mthd_1,
read_mthd_2,
update_track_details,
done
);
signal state : midi_decoder_state_t;
type header_data_t is record
num_tracks : unsigned(15 downto 0);
division_ticks : unsigned(15 downto 0);
end record;
signal first_chunk : std_logic;
signal errors_int : errors_t;
signal errors_noreg : errors_t;
signal header_data : header_data_t;
signal header_data_noreg : header_data_t;
signal chunk_data_int : chunk_data_t_arr;
signal chunk_no : integer range 0 to max_num_tracks;
signal chunk_is_mtrk : std_logic;
signal chunk_addr : unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
signal chunk_length : unsigned(31 downto 0);
-- ram related signals
signal read_busy_d1 : std_logic;
begin
read_start_addr <= read_start_addr_int;
enable_decoder <= enable_decoder_int;
errors <= errors_int;
chunk_data <= chunk_data_int;
-- Once the user is sure that the RAM is full of midi data, they will press q
-- to start the player.
wait_enable : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
enable_decoder_int <= '0';
else
if buttons(q).pressed = '1' then
enable_decoder_int <= '1';
end if;
end if;
end if;
end process;
delay_read_busy : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
read_busy_d1 <= read_busy;
end if;
end process;
midi_decoder_fsm : process(ctrl.clk) is
impure function ram_read_finished return boolean is
begin
return read_busy = '0' and read_busy_d1 = '1';
end;
-- Make setting literal addresses slightly easier
impure function format_addr(addr : std_logic_vector) return unsigned is
begin
return resize(unsigned(addr), read_start_addr_int'length);
end;
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
read_start_addr_int <= (others => '0');
state <= initial_wait;
errors_int <= (others => '0');
header_data <= (others => (others => '0'));
chunk_no <= 0;
chunk_data_int <= (others => (others => (others => '0')));
chunk_addr <= to_unsigned(0, chunk_addr'length);
chunk_length <= to_unsigned(0, chunk_length'length);
playing_en <= '0';
read_en <= '0';
first_chunk <= '1';
else
case state is
when initial_wait =>
if enable_decoder_int = '1' then
state <= read_chunk_header_1;
end if;
-- Reads the first 8 fixed bytes of a chunk.
when read_chunk_header_1 =>
-- Preset the errors. Hopefully we will clear them very soon.
-- Find the start of the chunk we are about to read by examining
-- summing the addr and length of the previous chunk
if first_chunk = '0' then
chunk_addr <= resize(8 + chunk_addr + chunk_length, chunk_addr'length);
read_start_addr_int <= resize(8 + chunk_addr + chunk_length, chunk_addr'length);
end if;
read_num_bytes_int <= 8;
-- Check if we are done by seeing if there is
-- room for another chunk before the end of the midi file.
if chunk_addr + chunk_length + 8 >= contents_count then
state <= done;
else
state <= read_chunk_header_2;
read_en <= '1';
end if;
when read_chunk_header_2 =>
read_en <= '0';
if ram_read_finished then
chunk_length <= unsigned(midi_ram_out(31 downto 0));
case midi_ram_out(63 downto 32) is
when mthd => state <= read_mthd_1;
when mtrk => state <= update_track_details;
when others => report "unknown chunk type found" severity note;
end case;
end if;
-- Check that the midi header exists in the received data. This is a
-- sanity check to make sure we actually have a midi file.
--
-- Also check that this midi file is format 1. This midi decoder
-- can only play format 1 tracks.
when read_mthd_1 =>
first_chunk <= '0';
errors_int.no_mthd <= '0';
read_start_addr_int <= chunk_addr + 8;
read_en <= '1';
read_num_bytes_int <= 6;
state <= read_mthd_2;
when read_mthd_2 =>
read_en <= '0';
if ram_read_finished then
if to_integer(unsigned(midi_ram_out(47 downto 32))) = 1 then
errors_int.not_format_1 <= '0';
else
errors_int.not_format_1 <= '1';
end if;
header_data.num_tracks <= unsigned(midi_ram_out(31 downto 16));
header_data.division_ticks <= unsigned(midi_ram_out(15 downto 0));
state <= read_chunk_header_1;
end if;
-- If we have correctly read a track chunk then store it.
when update_track_details =>
chunk_data_int(chunk_no).length <= chunk_length;
chunk_data_int(chunk_no).base_addr <= chunk_addr;
chunk_no <= chunk_no + 1;
state <= read_chunk_header_1;
when done =>
if errors_int.no_mthd = '0' and errors_int.not_format_1 = '0' and chunk_no > 1 then
playing_en <= '1';
num_chunks <= chunk_no - 1;
end if;
end case;
end if;
end if;
end process;
read_num_bytes <= read_num_bytes_int;
end;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- not both this and below -- USE ieee.std_logic_arith.all;
--use IEEE.numeric_bit.all; -- for integer to bit_vector conversion
use IEEE.numeric_std.all; -- for integer to bit_vector conversion
-- VGA std format 640 by 480 pixels in a frame
-- register them, count line by line
--
ENTITY SlowCounter IS
PORT
(
Clk : IN std_logic;
ClockOUT : OUT std_logic
);
END SlowCounter;
-- first register the pixel stream
ARCHITECTURE SlowCounter_v1 OF SlowCounter IS
CONSTANT maxval: natural := 100; -- **************NOTE: this is carefully chosen to ensure TrainFLAG (in Debouncer)is only one frame long
signal Counter: natural range 0 to maxval; -- reduce clock to approx 500ms from 64uS (Hsync input)
signal Ctemp: std_logic := '0';
begin
---------------------------------------------------------------------------
process (clk)
begin
if (clk'event) and (clk ='1') then
Counter <= Counter +1;
if Counter = 0 then
Ctemp <= '0';
end if;
if Counter = maxval then
Ctemp <= not(Ctemp);
end if;
end if;
end process;
Clockout <= Ctemp;
---------------------------------------------------------------------------
END SlowCounter_v1; |
module elevator |
entity e is
end entity;
architecture a of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type bad1 is protected
procedure foo (x : not_here); -- Error
end protected;
type bad1 is protected body
end protected body;
type bad2 is protected body -- Error
end protected body;
type integer is protected body -- Error
end protected body;
type now is protected body -- Error
end protected body;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
type SharedCounter is protected body -- Error
end protected body;
subtype s is SharedCounter; -- Error
shared variable x : integer; -- Error
shared variable y : SharedCounter; -- OK
shared variable y : SharedCounter := 1; -- Error
function make return SharedCounter is
variable result : SharedCounter;
begin
return result;
end function;
procedure proc(variable sh : in SharedCounter := make) is -- error
begin
end procedure;
begin
end architecture;
architecture a2 of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
procedure foo (x : in integer);
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
procedure bar (x : in integer ) is
begin
null;
end procedure;
procedure foo (x : in integer ) is
begin
bar(x + 1);
end procedure;
end protected body;
shared variable x : SharedCounter; -- OK
begin
process is
begin
x.increment(2); -- OK
x.increment; -- OK
x.counter := 5; -- Error
x.decrement(1, 2); -- Error
assert x.value = 5; -- OK
end process;
process is
function get_value (x : in sharedcounter ) return integer is -- Error
begin
return x.value;
end function;
begin
end process;
bad_assignment: process
variable y : SharedCounter;
variable z : SharedCounter;
begin
y := z; -- Error
wait;
end process;
end architecture;
package issue85 is
type protected_t is protected
procedure add(argument : inout protected_t); -- OK
end protected protected_t;
end package;
package pkg is
type protected_t is protected
end protected protected_t;
end package;
package body pkg is
-- Missing body for protected_t
end package body;
|
entity e is
end entity;
architecture a of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type bad1 is protected
procedure foo (x : not_here); -- Error
end protected;
type bad1 is protected body
end protected body;
type bad2 is protected body -- Error
end protected body;
type integer is protected body -- Error
end protected body;
type now is protected body -- Error
end protected body;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
type SharedCounter is protected body -- Error
end protected body;
subtype s is SharedCounter; -- Error
shared variable x : integer; -- Error
shared variable y : SharedCounter; -- OK
shared variable y : SharedCounter := 1; -- Error
function make return SharedCounter is
variable result : SharedCounter;
begin
return result;
end function;
procedure proc(variable sh : in SharedCounter := make) is -- error
begin
end procedure;
begin
end architecture;
architecture a2 of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
procedure foo (x : in integer);
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
procedure bar (x : in integer ) is
begin
null;
end procedure;
procedure foo (x : in integer ) is
begin
bar(x + 1);
end procedure;
end protected body;
shared variable x : SharedCounter; -- OK
begin
process is
begin
x.increment(2); -- OK
x.increment; -- OK
x.counter := 5; -- Error
x.decrement(1, 2); -- Error
assert x.value = 5; -- OK
end process;
process is
function get_value (x : in sharedcounter ) return integer is -- Error
begin
return x.value;
end function;
begin
end process;
bad_assignment: process
variable y : SharedCounter;
variable z : SharedCounter;
begin
y := z; -- Error
wait;
end process;
end architecture;
package issue85 is
type protected_t is protected
procedure add(argument : inout protected_t); -- OK
end protected protected_t;
end package;
package pkg is
type protected_t is protected
end protected protected_t;
end package;
package body pkg is
-- Missing body for protected_t
end package body;
|
entity e is
end entity;
architecture a of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type bad1 is protected
procedure foo (x : not_here); -- Error
end protected;
type bad1 is protected body
end protected body;
type bad2 is protected body -- Error
end protected body;
type integer is protected body -- Error
end protected body;
type now is protected body -- Error
end protected body;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
type SharedCounter is protected body -- Error
end protected body;
subtype s is SharedCounter; -- Error
shared variable x : integer; -- Error
shared variable y : SharedCounter; -- OK
shared variable y : SharedCounter := 1; -- Error
function make return SharedCounter is
variable result : SharedCounter;
begin
return result;
end function;
procedure proc(variable sh : in SharedCounter := make) is -- error
begin
end procedure;
begin
end architecture;
architecture a2 of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
procedure foo (x : in integer);
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
procedure bar (x : in integer ) is
begin
null;
end procedure;
procedure foo (x : in integer ) is
begin
bar(x + 1);
end procedure;
end protected body;
shared variable x : SharedCounter; -- OK
begin
process is
begin
x.increment(2); -- OK
x.increment; -- OK
x.counter := 5; -- Error
x.decrement(1, 2); -- Error
assert x.value = 5; -- OK
end process;
process is
function get_value (x : in sharedcounter ) return integer is -- Error
begin
return x.value;
end function;
begin
end process;
bad_assignment: process
variable y : SharedCounter;
variable z : SharedCounter;
begin
y := z; -- Error
wait;
end process;
end architecture;
package issue85 is
type protected_t is protected
procedure add(argument : inout protected_t); -- OK
end protected protected_t;
end package;
package pkg is
type protected_t is protected
end protected protected_t;
end package;
package body pkg is
-- Missing body for protected_t
end package body;
|
-- delay.vhd
--
-- Created on: 08 Jun 2017
-- Author: Fabian Meyer
--
-- Component that delays an input signal by
-- a given amount of cycles.
library ieee;
use ieee.std_logic_1164.all;
entity delay is
generic(RSTDEF: std_logic := '0';
DELAYLEN: natural := 8);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
din: in std_logic; -- data in
dout: out std_logic); -- data out
end entity;
architecture behavioral of delay is
-- vector through which signal is chained
signal dvec : std_logic_vector (DELAYLEN-1 downto 0) := (others => '0');
begin
dout <= dvec(DELAYLEN-1);
process (rst, clk)
begin
if rst = RSTDEF then
dvec <= (others => '0');
elsif rising_edge(clk) then
dvec <= dvec(DELAYLEN-2 downto 0) & din;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity condition_code_register is
port(
clk: in std_logic;
enable: in std_logic;
c_D: in std_logic;
z_D: in std_logic;
n_D: in std_logic;
lt_D: in std_logic;
c_Q: out std_logic;
z_Q: out std_logic;
n_Q: out std_logic;
lt_Q: out std_logic
);
end entity;
architecture a_condition_code_register of condition_code_register is
component flipflopD is
port(
clk: in std_logic;
enable: in std_logic;
D: in std_logic;
Q: out std_logic
);
end component;
--signal c_enable_sig,z_enable_sig,n_enable_sig,lt_enable_sig: std_logic;
--signal c_Q_sig,z_Q_sig,n_Q_sig,lt_Q_sig: std_logic;
begin
--c_enable_sig <= c_D xor c_Q_sig;
--z_enable_sig <= z_D xor z_Q_sig;
--n_enable_sig <= n_D xor n_Q_sig;
--lt_enable_sig <= lt_D xor lt_Q_sig;
--c_Q <= c_Q_sig;
--z_Q <= z_Q_sig;
--n_Q <= n_Q_sig;
--lt_Q <= lt_Q_sig;
ccr_c_ffD: flipflopD port map(clk=>clk,
enable=>enable,
D=>c_D,
Q=>c_Q
);
ccr_z_ffD: flipflopD port map(clk=>clk,
enable=>enable,
D=>z_D,
Q=>z_Q
);
ccr_n_ffD: flipflopD port map(clk=>clk,
enable=>enable,
D=>n_D,
Q=>n_Q
);
ccr_lt_ffD: flipflopD port map(clk=>clk,
enable=>enable,
D=>lt_D,
Q=>lt_Q
);
end architecture; |
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6000)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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1i0ki3aW7xPBgURIkBQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6000)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6000)
`protect data_block
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect data_block
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Vrefofkplusone is
port (
clock : in std_logic;
Vactcapofk : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
Yofk : in std_logic_vector(31 downto 0);
Vrefofkplusone : out std_logic_vector(31 downto 0)
);
end k_ukf_Vrefofkplusone;
architecture struct of k_ukf_Vrefofkplusone is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_mult port map
( clock => clock,
dataa => M,
datab => Yofk,
result => Z);
M2 : k_ukf_add port map
( clock => clock,
dataa => Vactcapofk,
datab => Z,
result => Vrefofkplusone);
end struct; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PS_to_PL_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
AXI_to_PL : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); --VL
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end PS_to_PL_v1_0;
architecture arch_imp of PS_to_PL_v1_0 is
-- component declaration
component PS_to_PL_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
AUDIO_OUT_FROM_AXI_TO_EFFECT : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --VL
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component PS_to_PL_v1_0_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
PS_to_PL_v1_0_S00_AXI_inst : PS_to_PL_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
AUDIO_OUT_FROM_AXI_TO_EFFECT => AXI_to_PL, --vl
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
|
----------------------------------------
-- Main Processor - Testbench : IITB-RISC
-- Author : Titto Thomas, Sainath, Anakha
-- Date : 9/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testbench is
end testbench;
architecture behave of testbench is
component pipeline_RISC is
port (
clock, reset : in std_logic; -- clock and reset signals
InstrData, InstrAddress, DataData, DataAddress : in std_logic_vector(15 downto 0); -- External data and address for programing
mode, InstrWrite, DataWrite : in std_logic -- Program / Execution mode
);
end component;
signal clock, reset, mode, InstrWrite, DataWrite : std_logic := '0';
signal InstrData, InstrAddress, DataData, DataAddress : std_logic_vector(15 downto 0);
begin --behave
DUT : pipeline_RISC port map (clock, reset, InstrData, InstrAddress, DataData, DataAddress, mode, InstrWrite, DataWrite);
clock <= not clock after 5 ns;
Main : process
begin
reset <= '1';
InstrData <= x"4201";
InstrAddress <= x"0000";
DataData <= x"0000";
DataAddress <= x"0000";
mode <= '1';
InstrWrite <= '0';
DataWrite <= '0';
InstrWrite <= '1';
wait for 10 ns;
InstrData <= x"4402";
InstrAddress <= x"0001";
wait for 10 ns;
InstrData <= x"06D4";
InstrAddress <= x"0002";
wait for 10 ns;
InstrData <= x"06D4";
InstrAddress <= x"0003";
wait for 10 ns;
InstrData <= x"06D4";
InstrAddress <= x"0004";
wait for 10 ns;
InstrData <= x"06D4";
InstrAddress <= x"0005";
wait for 10 ns;
InstrData <= x"0850";
InstrAddress <= x"0006";
wait for 10 ns;
InstrData <= x"06D4";
InstrAddress <= x"0005";
wait for 100 ns;
InstrData <= x"031A";
InstrAddress <= x"0007";
wait for 10 ns;
InstrData <= x"0319";
InstrAddress <= x"0008";
wait for 10 ns;
InstrData <= x"1A7F";
InstrAddress <= x"0009";
wait for 10 ns;
InstrData <= x"031A";
InstrAddress <= x"000A";
wait for 10 ns;
InstrWrite <= '0';
DataWrite <= '1';
DataData <= x"1234";
DataAddress <= x"0001";
wait for 10 ns;
DataData <= x"ABCD";
DataAddress <= x"0002";
wait for 10 ns;
DataWrite <= '0';
reset <= '0';
mode <= '0';
wait ;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_logic is
generic (
g_version : unsigned(7 downto 0) := X"FF";
g_simulation : boolean := true;
g_clock_freq : natural := 50_000_000;
g_baud_rate : natural := 115_200;
g_timer_rate : natural := 200_000;
g_fpga_type : natural := 0;
g_boot_rom : boolean := false;
g_video_overlay : boolean := false;
g_icap : boolean := false;
g_uart : boolean := false;
g_drive_1541 : boolean := false;
g_drive_1541_2 : boolean := false;
g_hardware_gcr : boolean := false;
g_cartridge : boolean := false;
g_command_intf : boolean := false;
g_stereo_sid : boolean := false;
g_ram_expansion : boolean := false;
g_extended_reu : boolean := false;
g_hardware_iec : boolean := false;
g_iec_prog_tim : boolean := false;
g_c2n_streamer : boolean := false;
g_c2n_recorder : boolean := false;
g_drive_sound : boolean := false;
g_rtc_chip : boolean := false;
g_rtc_timer : boolean := false;
g_usb_host : boolean := false;
g_spi_flash : boolean := false;
g_vic_copper : boolean := false;
g_sampler : boolean := false;
g_analyzer : boolean := false );
port (
-- globals
sys_clock : in std_logic;
sys_reset : in std_logic;
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic := '1';
BUFFER_ENn : out std_logic := '1';
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
mem_inhibit : out std_logic;
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
-- actual levels of the pins --
iec_reset_i : in std_logic;
iec_atn_i : in std_logic;
iec_data_i : in std_logic;
iec_clock_i : in std_logic;
iec_srq_i : in std_logic;
iec_reset_o : out std_logic := '1';
iec_atn_o : out std_logic;
iec_data_o : out std_logic;
iec_clock_o : out std_logic;
iec_srq_o : out std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1) := "ZZ";
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0) := "ZZZZZZZZ";
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Interface to other graphical output (Full HD of course and in 3D!) ;-)
vid_clock : in std_logic := '0';
vid_reset : in std_logic := '0';
vid_h_count : in unsigned(11 downto 0) := (others => '0');
vid_v_count : in unsigned(11 downto 0) := (others => '0');
vid_active : out std_logic;
vid_opaque : out std_logic;
vid_data : out unsigned(3 downto 0);
overlay_on : out std_logic;
keyb_row : in std_logic_vector(7 downto 0) := (others => '0');
keyb_col : inout std_logic_vector(7 downto 0) := (others => '0');
-- Buttons
button : in std_logic_vector(2 downto 0);
-- Simulation port
sim_io_req : in t_io_req := c_io_req_init;
sim_io_resp : out t_io_resp );
end ultimate_logic;
architecture logic of ultimate_logic is
function to_std(b : boolean) return std_logic is
begin
if b then
return '1';
end if;
return '0';
end function;
impure function create_capabilities return std_logic_vector is
variable cap : std_logic_vector(31 downto 0) := (others => '0');
begin
cap(00) := to_std(g_uart);
cap(01) := to_std(g_drive_1541);
cap(02) := to_std(g_drive_1541_2);
cap(03) := to_std(g_drive_sound);
cap(04) := to_std(g_hardware_gcr);
cap(05) := to_std(g_hardware_iec);
cap(06) := to_std(g_iec_prog_tim);
cap(07) := to_std(g_c2n_streamer);
cap(08) := to_std(g_c2n_recorder);
cap(09) := to_std(g_cartridge);
cap(10) := to_std(g_ram_expansion);
cap(11) := to_std(g_usb_host);
cap(12) := to_std(g_rtc_chip);
cap(13) := to_std(g_rtc_timer);
cap(14) := to_std(g_spi_flash);
cap(15) := to_std(g_icap);
cap(16) := to_std(g_extended_reu);
cap(17) := to_std(g_stereo_sid);
cap(18) := to_std(g_command_intf);
cap(19) := to_std(g_vic_copper);
cap(20) := to_std(g_video_overlay);
cap(21) := to_std(g_sampler);
cap(22) := to_std(g_analyzer);
cap(29 downto 28) := std_logic_vector(to_unsigned(g_fpga_type, 2));
cap(30) := to_std(g_boot_rom);
cap(31) := to_std(g_simulation);
return cap;
end function;
constant c_capabilities : std_logic_vector(31 downto 0) := create_capabilities;
constant c_tag_1541_cpu_1 : std_logic_vector(7 downto 0) := X"01";
constant c_tag_1541_floppy_1 : std_logic_vector(7 downto 0) := X"02";
constant c_tag_1541_audio_1 : std_logic_vector(7 downto 0) := X"03";
constant c_tag_1541_cpu_2 : std_logic_vector(7 downto 0) := X"04";
constant c_tag_1541_floppy_2 : std_logic_vector(7 downto 0) := X"05";
constant c_tag_1541_audio_2 : std_logic_vector(7 downto 0) := X"06";
constant c_tag_cpu : std_logic_vector(7 downto 0) := X"07";
constant c_tag_slot : std_logic_vector(7 downto 0) := X"08";
constant c_tag_reu : std_logic_vector(7 downto 0) := X"09";
-- Memory interface
signal mem_req_cpu : t_mem_req := c_mem_req_init;
signal mem_resp_cpu : t_mem_resp := c_mem_resp_init;
signal mem_req_1541 : t_mem_req := c_mem_req_init;
signal mem_resp_1541 : t_mem_resp := c_mem_resp_init;
signal mem_req_1541_2 : t_mem_req := c_mem_req_init;
signal mem_resp_1541_2 : t_mem_resp := c_mem_resp_init;
signal mem_req_cart : t_mem_req := c_mem_req_init;
signal mem_resp_cart : t_mem_resp := c_mem_resp_init;
signal mem_req_debug : t_mem_req := c_mem_req_init;
signal mem_resp_debug : t_mem_resp := c_mem_resp_init;
-- IO Bus
signal cpu_io_req : t_io_req;
signal cpu_io_resp : t_io_resp := c_io_resp_init;
signal io_req : t_io_req;
signal io_resp : t_io_resp := c_io_resp_init;
signal io_req_1541 : t_io_req;
signal io_resp_1541 : t_io_resp := c_io_resp_init;
signal io_req_1541_1 : t_io_req;
signal io_resp_1541_1 : t_io_resp := c_io_resp_init;
signal io_req_1541_2 : t_io_req;
signal io_resp_1541_2 : t_io_resp := c_io_resp_init;
signal io_req_itu : t_io_req;
signal io_resp_itu : t_io_resp := c_io_resp_init;
signal io_req_cart : t_io_req;
signal io_resp_cart : t_io_resp := c_io_resp_init;
signal io_req_io : t_io_req;
signal io_resp_io : t_io_resp := c_io_resp_init;
signal io_req_big_io : t_io_req;
signal io_resp_big_io : t_io_resp := c_io_resp_init;
signal io_req_sd : t_io_req;
signal io_resp_sd : t_io_resp := c_io_resp_init;
signal io_req_rtc : t_io_req;
signal io_resp_rtc : t_io_resp := c_io_resp_init;
signal io_req_rtc_tmr : t_io_req;
signal io_resp_rtc_tmr : t_io_resp := c_io_resp_init;
signal io_req_gcr_dec : t_io_req;
signal io_resp_gcr_dec : t_io_resp := c_io_resp_init;
signal io_req_flash : t_io_req;
signal io_resp_flash : t_io_resp := c_io_resp_init;
signal io_req_iec : t_io_req;
signal io_resp_iec : t_io_resp := c_io_resp_init;
signal io_req_usb : t_io_req;
signal io_resp_usb : t_io_resp := c_io_resp_init;
signal io_req_c2n : t_io_req;
signal io_resp_c2n : t_io_resp := c_io_resp_init;
signal io_req_c2n_rec : t_io_req;
signal io_resp_c2n_rec : t_io_resp := c_io_resp_init;
signal io_req_icap : t_io_req;
signal io_resp_icap : t_io_resp := c_io_resp_init;
signal io_req_aud_sel : t_io_req;
signal io_resp_aud_sel : t_io_resp := c_io_resp_init;
signal io_req_debug : t_io_req;
signal io_resp_debug : t_io_resp := c_io_resp_init;
-- Audio routing
signal pwm : std_logic;
signal pwm_2 : std_logic := '0';
signal drive_sample : signed(12 downto 0);
signal drive_sample_2 : signed(12 downto 0);
-- IEC signal routing
signal atn_o, atn_i : std_logic := '1';
signal clk_o, clk_i : std_logic := '1';
signal data_o, data_i : std_logic := '1';
signal srq_i : std_logic := '1';
signal atn_o_2 : std_logic := '1';
signal clk_o_2 : std_logic := '1';
signal data_o_2 : std_logic := '1';
signal hw_atn_o : std_logic := '1';
signal hw_clk_o : std_logic := '1';
signal hw_data_o : std_logic := '1';
signal hw_srq_o : std_logic := '1';
-- miscellaneous interconnect
signal irq_i : std_logic := '0';
signal c64_irq_n : std_logic;
signal c64_irq : std_logic;
signal phi2_tick : std_logic;
signal c64_stopped : std_logic;
signal c2n_sense : std_logic := '0';
signal c2n_sense_in : std_logic := '0';
signal c2n_out_r : std_logic := '1';
signal c2n_out_w : std_logic := '1';
signal sd_busy : std_logic;
signal usb_busy : std_logic;
signal sd_act_stretched : std_logic;
signal error : std_logic;
signal act_led_n : std_logic := '1';
signal motor_led_n : std_logic := '1';
signal cart_led_n : std_logic := '1';
signal c2n_pull_sense : std_logic := '0';
signal freezer_state : std_logic_vector(1 downto 0);
signal dirty_led_1_n : std_logic := '1';
signal dirty_led_2_n : std_logic := '1';
signal sid_pwm_left : std_logic;
signal sid_pwm_right : std_logic;
signal samp_pwm_left : std_logic;
signal samp_pwm_right : std_logic;
signal trigger_1 : std_logic;
signal trigger_2 : std_logic;
begin
i_cpu: entity work.cpu_wrapper_zpu
generic map (
g_mem_tag => c_tag_cpu,
g_internal_prg => true,
g_boot_rom => g_boot_rom,
g_simulation => g_simulation )
port map (
clock => sys_clock,
reset => sys_reset,
break_o => open,
error => error,
-- memory interface
mem_req => mem_req_cpu,
mem_resp => mem_resp_cpu,
io_req => cpu_io_req,
io_resp => cpu_io_resp );
i_io_arb: entity work.io_bus_arbiter_pri
generic map (
g_ports => 2 )
port map (
clock => sys_clock,
reset => sys_reset,
reqs(0) => sim_io_req,
reqs(1) => cpu_io_req,
resps(0) => sim_io_resp,
resps(1) => cpu_io_resp,
req => io_req,
resp => io_resp );
i_itu: entity work.itu
generic map (
g_version => g_version,
g_capabilities => c_capabilities,
g_uart => g_uart,
g_frequency => g_clock_freq,
g_edge_init => "00000001",
g_edge_write => false,
g_baudrate => g_baud_rate,
g_timer_rate => g_timer_rate)
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_itu,
io_resp => io_resp_itu,
irq_in(7) => button(2),
irq_in(6) => button(1),
irq_in(5) => button(0),
irq_in(4) => c64_irq,
irq_in(3) => '0',
irq_in(2) => '0',
uart_txd => UART_TXD,
uart_rxd => UART_RXD );
r_drive: if g_drive_1541 generate
begin
i_drive: entity work.c1541_drive
generic map (
g_cpu_tag => c_tag_1541_cpu_1,
g_floppy_tag => c_tag_1541_floppy_1,
g_audio_tag => c_tag_1541_audio_1,
g_audio => g_drive_sound,
g_audio_div => (g_clock_freq / 22500),
g_audio_base => X"0EC0000",
g_ram_base => X"0EE0000" )
port map (
clock => sys_clock,
reset => sys_reset,
drive_stop => c64_stopped,
-- slave port on io bus
io_req => io_req_1541_1,
io_resp => io_resp_1541_1,
-- master port on memory bus
mem_req => mem_req_1541,
mem_resp => mem_resp_1541,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
iec_reset_n => iec_reset_i,
c64_reset_n => RSTn,
-- LED
act_led_n => act_led_n,
motor_led_n => motor_led_n,
dirty_led_n => dirty_led_1_n,
-- audio out
audio_sample => drive_sample );
r_pwm: if g_drive_sound generate
i_pwm0: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 2,
g_width => drive_sample'length )
port map (
clock => sys_clock,
reset => sys_reset,
dac_in => drive_sample,
dac_out => pwm );
end generate;
end generate;
r_drive_2: if g_drive_1541_2 generate
begin
i_drive: entity work.c1541_drive
generic map (
g_cpu_tag => c_tag_1541_cpu_2,
g_floppy_tag => c_tag_1541_floppy_2,
g_audio_tag => c_tag_1541_audio_2,
g_audio => g_drive_sound,
g_audio_div => (g_clock_freq / 22500),
g_audio_base => X"0EC0000",
g_ram_base => X"0ED0000" )
port map (
clock => sys_clock,
reset => sys_reset,
drive_stop => c64_stopped,
-- slave port on io bus
io_req => io_req_1541_2,
io_resp => io_resp_1541_2,
-- master port on memory bus
mem_req => mem_req_1541_2,
mem_resp => mem_resp_1541_2,
-- serial bus pins
atn_o => atn_o_2, -- open drain
atn_i => atn_i,
clk_o => clk_o_2, -- open drain
clk_i => clk_i,
data_o => data_o_2, -- open drain
data_i => data_i,
iec_reset_n => iec_reset_i,
c64_reset_n => RSTn,
-- LED
act_led_n => open, --DISK_ACTn,
motor_led_n => open, --MOTOR_LEDn,
dirty_led_n => dirty_led_2_n,
-- audio out
audio_sample => drive_sample_2 );
r_pwm: if g_drive_sound generate
i_pwm0: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 2,
g_width => drive_sample_2'length )
port map (
clock => sys_clock,
reset => sys_reset,
dac_in => drive_sample_2,
dac_out => pwm_2 );
end generate;
end generate;
r_cart: if g_cartridge generate
i_slot_srv: entity work.slot_server_v4
generic map (
g_tag_slot => c_tag_slot,
g_tag_reu => c_tag_reu,
g_ram_base_reu => X"1000000", -- should be on 16M boundary, or should be limited in size
g_rom_base_cart => X"0F00000", -- should be on a 1M boundary
g_ram_base_cart => X"0EF0000", -- should be on a 64K boundary
g_control_read => true,
g_ram_expansion => g_ram_expansion,
g_extended_reu => g_extended_reu,
g_command_intf => g_command_intf,
g_sampler => g_sampler,
g_implement_sid => g_stereo_sid,
g_sid_voices => 16,
g_vic_copper => g_vic_copper )
port map (
clock => sys_clock,
reset => sys_reset,
-- Cartridge pins
RSTn => RSTn,
IRQn => IRQn,
NMIn => NMIn,
PHI2 => PHI2,
IO1n => IO1n,
IO2n => IO2n,
DMAn => DMAn,
BA => BA,
ROMLn => ROMLn,
ROMHn => ROMHn,
GAMEn => GAMEn,
EXROMn => EXROMn,
RWn => RWn,
ADDRESS => SLOT_ADDR,
DATA => SLOT_DATA,
-- other hardware pins
BUFFER_ENn => BUFFER_ENn,
buttons => BUTTON,
cart_led_n => cart_led_n,
-- audio
sid_pwm_left => sid_pwm_left,
sid_pwm_right => sid_pwm_right,
samp_pwm_left => samp_pwm_left,
samp_pwm_right => samp_pwm_right,
-- debug
freezer_state => freezer_state,
trigger_1 => trigger_1,
trigger_2 => trigger_2,
-- timing output
c64_stopped => c64_stopped,
phi2_tick => phi2_tick,
-- master on memory bus
memctrl_inhibit => mem_inhibit,
mem_req => mem_req_cart,
mem_resp => mem_resp_cart,
-- slave on io bus
io_req => io_req_cart,
io_resp => io_resp_cart );
end generate;
i_split1: entity work.io_bus_splitter
generic map (
g_range_lo => 17,
g_range_hi => 19,
g_ports => 8 )
port map (
clock => sys_clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_itu, -- 4000000 ( 16 ... 400000F)
reqs(1) => io_req_1541, -- 4020000 ( 8K... 4021FFF) & 4024000 for drive B
reqs(2) => io_req_cart, -- 4040000 (128K... 405FFFF)
reqs(3) => io_req_io, -- 4060000 ( 2K... 4060FFF)
reqs(4) => io_req_usb, -- 4080000 ( 8K... 4081FFF)
reqs(5) => io_req_c2n, -- 40A0000 ( 4K... 40A0FFF)
reqs(6) => io_req_c2n_rec, -- 40C0000 ( 4K... 40C0FFF)
reqs(7) => io_req_big_io, -- 40E0000 (128K... 40FFFFF)
resps(0) => io_resp_itu,
resps(1) => io_resp_1541,
resps(2) => io_resp_cart,
resps(3) => io_resp_io,
resps(4) => io_resp_usb,
resps(5) => io_resp_c2n,
resps(6) => io_resp_c2n_rec,
resps(7) => io_resp_big_io );
i_split2: entity work.io_bus_splitter
generic map (
g_range_lo => 14,
g_range_hi => 15,
g_ports => 3 )
port map (
clock => sys_clock,
req => io_req_1541,
resp => io_resp_1541,
reqs(0) => io_req_1541_1, -- 4020000
reqs(1) => io_req_1541_2, -- 4024000
reqs(2) => io_req_iec, -- 4028000
resps(0) => io_resp_1541_1,
resps(1) => io_resp_1541_2,
resps(2) => io_resp_iec );
i_split3: entity work.io_bus_splitter
generic map (
g_range_lo => 8,
g_range_hi => 11,
g_ports => 8 )
port map (
clock => sys_clock,
req => io_req_io,
resp => io_resp_io,
reqs(0) => io_req_sd, -- 4060000
reqs(1) => io_req_rtc, -- 4060100
reqs(2) => io_req_flash, -- 4060200
reqs(3) => io_req_debug, -- 4060300
reqs(4) => io_req_rtc_tmr, -- 4060400
reqs(5) => io_req_gcr_dec, -- 4060500
reqs(6) => io_req_icap, -- 4060600
reqs(7) => io_req_aud_sel, -- 4060700
resps(0) => io_resp_sd,
resps(1) => io_resp_rtc,
resps(2) => io_resp_flash,
resps(3) => io_resp_debug,
resps(4) => io_resp_rtc_tmr,
resps(5) => io_resp_gcr_dec,
resps(6) => io_resp_icap,
resps(7) => io_resp_aud_sel );
r_usb: if g_usb_host generate
i_usb: entity work.usb1_host_io
generic map (
g_simulation => g_simulation )
port map (
ulpi_clock => ULPI_CLOCK,
ulpi_reset => ulpi_reset,
-- ULPI Interface
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
usb_busy => usb_busy, -- LED interface
-- register interface bus
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_io_req => io_req_usb,
sys_io_resp => io_resp_usb );
end generate;
i_sd: entity work.spi_peripheral_io
generic map (
g_fixed_rate => false,
g_init_rate => 500,
g_crc => true )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_sd,
io_resp => io_resp_sd,
busy => sd_busy,
SD_DETECTn => SD_CARDDETn,
SD_WRPROTn => '1', --SD_WRPROTn,
SPI_SSn => SD_SSn,
SPI_CLK => SD_CLK,
SPI_MOSI => SD_MOSI,
SPI_MISO => SD_MISO );
i_stretch: entity work.pulse_stretch
generic map ( g_clock_freq / 200) -- 5 ms
port map (
clock => sys_clock,
reset => sys_reset,
pulse_in => sd_busy,
pulse_out => sd_act_stretched );
r_spi_flash: if g_spi_flash generate
i_spi_flash: entity work.spi_peripheral_io
generic map (
g_fixed_rate => true,
g_init_rate => 0,
g_crc => false )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_flash,
io_resp => io_resp_flash,
SD_DETECTn => '0',
SD_WRPROTn => '1',
SPI_SSn => FLASH_CSn,
SPI_CLK => FLASH_SCK,
SPI_MOSI => FLASH_MOSI,
SPI_MISO => FLASH_MISO );
end generate;
r_no_spi_flash: if not g_spi_flash generate
i_flash_dummy: entity work.io_dummy
port map (
clock => sys_clock,
io_req => io_req_flash,
io_resp => io_resp_flash );
end generate;
r_rtc: if g_rtc_chip generate
signal spi_ss_n : std_logic;
begin
i_spi_rtc: entity work.spi_peripheral_io
generic map (
g_fixed_rate => true,
g_init_rate => 31,
g_crc => false )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_rtc,
io_resp => io_resp_rtc,
SD_DETECTn => '0',
SD_WRPROTn => '1',
SPI_SSn => spi_ss_n,
SPI_CLK => RTC_SCK,
SPI_MOSI => RTC_MOSI,
SPI_MISO => RTC_MISO );
RTC_CS <= not spi_ss_n;
end generate;
r_no_rtc: if not g_rtc_chip generate
i_rtc_dummy: entity work.io_dummy
port map (
clock => sys_clock,
io_req => io_req_rtc,
io_resp => io_resp_rtc );
end generate;
r_rtc_timer: if g_rtc_timer generate
i_rtc_timer: entity work.real_time_clock
generic map (
g_freq => g_clock_freq )
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_rtc_tmr,
resp => io_resp_rtc_tmr );
end generate;
r_no_rtc_timer: if not g_rtc_chip generate
i_rtc_timer_dummy: entity work.io_dummy
port map (
clock => sys_clock,
io_req => io_req_rtc_tmr,
io_resp => io_resp_rtc_tmr );
end generate;
r_gcr_codec: if g_hardware_gcr generate
i_gcr_codec: entity work.gcr_codec
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_gcr_dec,
resp => io_resp_gcr_dec );
end generate;
r_iec: if g_hardware_iec generate
i_iec: entity work.iec_processor_io
port map (
clock => sys_clock,
reset => sys_reset,
atn_i => atn_i,
atn_o => hw_atn_o,
clk_i => clk_i,
clk_o => hw_clk_o,
data_i => data_i,
data_o => hw_data_o,
req => io_req_iec,
resp => io_resp_iec );
end generate;
r_c2n: if g_c2n_streamer generate
i_c2n: entity work.c2n_playback_io
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_c2n,
resp => io_resp_c2n,
c64_stopped => c64_stopped,
phi2_tick => phi2_tick,
c2n_sense => c2n_sense,
c2n_motor => CAS_MOTOR,
c2n_out_r => c2n_out_r,
c2n_out_w => c2n_out_w );
end generate;
r_c2n_rec: if g_c2n_recorder generate
i_c2n: entity work.c2n_record
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_c2n_rec,
resp => io_resp_c2n_rec,
c64_stopped => c64_stopped,
phi2_tick => phi2_tick,
pull_sense => c2n_pull_sense,
c2n_sense => c2n_sense_in,
c2n_motor => CAS_MOTOR,
c2n_write => CAS_WRITE,
c2n_read => CAS_READ );
end generate;
r_icap: if g_icap generate
i_icap: entity work.icap
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_icap,
io_resp => io_resp_icap );
end generate;
r_overlay: if g_video_overlay generate
i_overlay: entity work.char_generator_peripheral
generic map (
g_screen_size => 11,
g_color_ram => true )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_big_io, -- to be split later
io_resp => io_resp_big_io,
keyb_col => keyb_col,
keyb_row => keyb_row,
overlay_on => overlay_on,
pix_clock => vid_clock,
pix_reset => vid_reset,
h_count => vid_h_count,
v_count => vid_v_count,
pixel_active => vid_active,
pixel_opaque => vid_opaque,
pixel_data => vid_data );
end generate;
CAS_SENSE <= '0' when (c2n_sense='1') or (c2n_pull_sense='1') else 'Z';
CAS_READ <= '0' when c2n_out_r='0' else 'Z';
CAS_WRITE <= '0' when c2n_out_w='0' else 'Z';
-- CAS_READ <= trigger_1;
-- CAS_WRITE <= trigger_2;
c2n_sense_in <= '1' when CAS_SENSE='0' else '0';
i_mem_arb: entity work.mem_bus_arbiter_pri
generic map (
g_ports => 5,
g_registered => false )
port map (
clock => sys_clock,
reset => sys_reset,
reqs(0) => mem_req_cart,
reqs(1) => mem_req_1541,
reqs(2) => mem_req_1541_2,
reqs(3) => mem_req_debug,
reqs(4) => mem_req_cpu,
resps(0) => mem_resp_cart,
resps(1) => mem_resp_1541,
resps(2) => mem_resp_1541_2,
resps(3) => mem_resp_debug,
resps(4) => mem_resp_cpu,
req => mem_req,
resp => mem_resp );
i_aud_select: entity work.audio_select
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_aud_sel,
resp => io_resp_aud_sel,
drive0 => pwm,
drive1 => pwm_2,
cas_read => CAS_READ,
cas_write => CAS_WRITE,
sid_left => sid_pwm_left,
sid_right => sid_pwm_right,
samp_left => samp_pwm_left,
samp_right => samp_pwm_right,
pwm_out => PWM_OUT );
iec_atn_o <= '0' when atn_o='0' or atn_o_2='0' or hw_atn_o='0' else '1';
iec_clock_o <= '0' when clk_o='0' or clk_o_2='0' or hw_clk_o='0' else '1';
iec_data_o <= '0' when data_o='0' or data_o_2='0' or hw_data_o='0' else '1';
iec_srq_o <= hw_srq_o; -- only source
DISK_ACTn <= act_led_n xor error;
MOTOR_LEDn <= motor_led_n xor error;
CART_LEDn <= cart_led_n xor error;
SDACT_LEDn <= (dirty_led_1_n and dirty_led_2_n and not (sd_act_stretched or usb_busy)) xor error;
-- DISK_ACTn <= not freezer_state(1);
-- MOTOR_LEDn <= not freezer_state(0);
-- CART_LEDn <= IRQn;
-- SDACT_LEDn <= NMIn;
filt1: entity work.spike_filter generic map (10) port map(sys_clock, iec_atn_i, atn_i);
filt2: entity work.spike_filter generic map (10) port map(sys_clock, iec_clock_i, clk_i);
filt3: entity work.spike_filter generic map (10) port map(sys_clock, iec_data_i, data_i);
filt4: entity work.spike_filter generic map (10) port map(sys_clock, iec_srq_i, srq_i);
filt5: entity work.spike_filter port map(sys_clock, IRQn, c64_irq_n);
c64_irq <= not c64_irq_n;
-- dummy
SD_DATA <= "ZZ";
g_ela: if g_analyzer generate
signal ev_data : std_logic_vector(15 downto 0);
begin
i_ela: entity work.logic_analyzer
generic map (
g_timer_div => 50,
g_change_width => 16,
g_data_length => 2 )
port map (
clock => sys_clock,
reset => sys_reset,
ev_dav => '0',
ev_data => ev_data,
---
mem_req => mem_req_debug,
mem_resp => mem_resp_debug,
io_req => io_req_debug,
io_resp => io_resp_debug );
ev_data <= srq_i & atn_i & data_i & clk_i & '1' & atn_o_2 & data_o_2 & clk_o_2 &
'0' & atn_o & data_o & clk_o & hw_srq_o & hw_atn_o & hw_data_o & hw_clk_o;
end generate;
end logic;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clk200Hz_tb IS
END clk200Hz_tb;
ARCHITECTURE behavior OF clk200Hz_tb IS
COMPONENT clk200Hz
PORT(
entrada : IN std_logic;
reset : IN std_logic;
salida : OUT std_logic
);
END COMPONENT;
-- Entradas
signal entrada : std_logic := '0';
signal reset : std_logic := '0';
-- Salidas
signal salida : std_logic;
constant entrada_t : time := 20 ns;
BEGIN
-- Instancia de la unidad bajo prueba.
uut: clk200Hz PORT MAP (
entrada => entrada,
reset => reset,
salida => salida
);
-- Definición del reloj.
entrada_process :process
begin
entrada <= '0';
wait for entrada_t / 2;
entrada <= '1';
wait for entrada_t / 2;
end process;
-- Procesamiento de estímulos.
estimulos: process
begin
reset <= '1'; -- Condiciones iniciales.
wait for 100 ns;
reset <= '0'; -- ¡A trabajar!
wait;
end process;
END; |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clk200Hz_tb IS
END clk200Hz_tb;
ARCHITECTURE behavior OF clk200Hz_tb IS
COMPONENT clk200Hz
PORT(
entrada : IN std_logic;
reset : IN std_logic;
salida : OUT std_logic
);
END COMPONENT;
-- Entradas
signal entrada : std_logic := '0';
signal reset : std_logic := '0';
-- Salidas
signal salida : std_logic;
constant entrada_t : time := 20 ns;
BEGIN
-- Instancia de la unidad bajo prueba.
uut: clk200Hz PORT MAP (
entrada => entrada,
reset => reset,
salida => salida
);
-- Definición del reloj.
entrada_process :process
begin
entrada <= '0';
wait for entrada_t / 2;
entrada <= '1';
wait for entrada_t / 2;
end process;
-- Procesamiento de estímulos.
estimulos: process
begin
reset <= '1'; -- Condiciones iniciales.
wait for 100 ns;
reset <= '0'; -- ¡A trabajar!
wait;
end process;
END; |
library ieee;
use ieee.std_logic_1164.all;
entity SRAM is
port (
clk : in std_logic;
load : in boolean;
addr : in std_logic_vector(19 downto 0);
data : inout std_logic_vector(31 downto 0);
clkPin1 : out std_logic;
clkPin2 : out std_logic;
xStorePin : out std_logic;
xMaskPin : out std_logic_vector(3 downto 0);
addrPin : out std_logic_vector(19 downto 0);
dataPin : inout std_logic_vector(31 downto 0);
xEnablePin1 : out std_logic;
enablePin2 : out std_logic;
xEnablePin3 : out std_logic;
xOutEnablePin : out std_logic;
xClkEnablePin : out std_logic;
advancePin : out std_logic;
xLinearOrderPin : out std_logic;
sleepPin : out std_logic;
xFlowThruPin : out std_logic);
end SRAM;
architecture structural of SRAM is
begin
clkPin1 <= clk;
clkPin2 <= clk;
addrPin <= addr;
xStorePin <= '1' when load else '0';
xMaskPin <= "0000";
dataPin <= data;
xEnablePin1 <= '0';
enablePin2 <= '1';
xEnablePin3 <= '0';
xOutEnablePin <= '0';
xClkEnablePin <= '0';
advancePin <= '0';
xLinearOrderPin <= '1';
sleepPin <= '0';
xFlowThruPin <= '1';
end structural;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: Instr_Mem1_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY Instr_Mem1_tb IS
END ENTITY;
ARCHITECTURE Instr_Mem1_tb_ARCH OF Instr_Mem1_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
Instr_Mem1_synth_inst:ENTITY work.Instr_Mem1_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: Instr_Mem1_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY Instr_Mem1_tb IS
END ENTITY;
ARCHITECTURE Instr_Mem1_tb_ARCH OF Instr_Mem1_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
Instr_Mem1_synth_inst:ENTITY work.Instr_Mem1_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
entity ram2 is
generic (
WIDTH : integer := 32;
SIZE : integer := 64;
ADDRWIDTH : integer := 6
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end ram2;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
architecture behavioral of ram2 is
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
ram(conv_integer(addrA)) := diA;
end if;
doA <= ram(conv_integer(addrA));
end if;
end if;
end process;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
ram(conv_integer(addrB)) := diB;
end if;
doB <= ram(conv_integer(addrB));
end if;
end if;
end process;
end behavioral;
|
ARCHITECTURE behavior OF timingDemo IS
BEGIN
p1 : PROCESS() --add sesitivity list for the signal connecting to port E
--remeber to creat a variable here
BEGIN
END PROCESS;
p2: PROCESS() --add sesitivity list for the signals connecting to port O and port P
BEGIN
END PROCESS;
--transmit the signal to the port
N<=;
O<=;
P<=;
E<=;
END behavior;
|
library ieee;
use ieee.std_logic_1164.all;
entity ddr4_dimm_wrapper is
port (
sys_reset : in std_logic;
c0_ddr4_act_n : in std_logic;
c0_ddr4_adr : in std_logic_vector(16 downto 0);
c0_ddr4_ba : in std_logic_vector(1 downto 0);
c0_ddr4_bg : in std_logic_vector(0 downto 0);
c0_ddr4_cke : in std_logic_vector(0 downto 0);
c0_ddr4_odt : in std_logic_vector(0 downto 0);
c0_ddr4_cs_n : in std_logic_vector(0 downto 0);
c0_ddr4_ck_t : in std_logic_vector(0 downto 0);
c0_ddr4_ck_c : in std_logic_vector(0 downto 0);
c0_ddr4_reset_n : in std_logic;
c0_ddr4_dm_dbi_n : inout std_logic_vector(8 downto 0);
c0_ddr4_dq : inout std_logic_vector(71 downto 0);
c0_ddr4_dqs_t : inout std_logic_vector(8 downto 0);
c0_ddr4_dqs_c : inout std_logic_vector(8 downto 0)
);
end;
architecture arch of ddr4_dimm_wrapper is
component ddr4_dimm is
port (
sys_reset : in std_logic;
c0_ddr4_act_n : in std_logic;
c0_ddr4_adr : in std_logic_vector(16 downto 0);
c0_ddr4_ba : in std_logic_vector(1 downto 0);
c0_ddr4_bg : in std_logic_vector(0 downto 0);
c0_ddr4_cke : in std_logic_vector(0 downto 0);
c0_ddr4_odt : in std_logic_vector(0 downto 0);
c0_ddr4_cs_n : in std_logic_vector(0 downto 0);
c0_ddr4_ck_t : in std_logic_vector(0 downto 0);
c0_ddr4_ck_c : in std_logic_vector(0 downto 0);
c0_ddr4_reset_n : in std_logic;
c0_ddr4_dm_dbi_n : inout std_logic_vector(8 downto 0);
c0_ddr4_dq : inout std_logic_vector(71 downto 0);
c0_ddr4_dqs_t : inout std_logic_vector(8 downto 0);
c0_ddr4_dqs_c : inout std_logic_vector(8 downto 0)
);
end component;
begin
I1 : ddr4_dimm port map (
sys_reset ,
c0_ddr4_act_n ,
c0_ddr4_adr ,
c0_ddr4_ba ,
c0_ddr4_bg ,
c0_ddr4_cke ,
c0_ddr4_odt ,
c0_ddr4_cs_n ,
c0_ddr4_ck_t ,
c0_ddr4_ck_c ,
c0_ddr4_reset_n ,
c0_ddr4_dm_dbi_n ,
c0_ddr4_dq ,
c0_ddr4_dqs_t ,
c0_ddr4_dqs_c );
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- LV network: False
-- Data width: 32
-- Parity: False
-- Fault injectors: True
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
entity network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
--------------
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--fault injector signals
FI_Add_2_0, FI_Add_0_2: in std_logic_vector(4 downto 0);
sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0: in std_logic;
FI_Add_3_1, FI_Add_1_3: in std_logic_vector(4 downto 0);
sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1: in std_logic;
FI_Add_1_0, FI_Add_0_1: in std_logic_vector(4 downto 0);
sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0: in std_logic;
FI_Add_3_2, FI_Add_2_3: in std_logic_vector(4 downto 0);
sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2: in std_logic;
--------------
link_faults_0: out std_logic_vector(4 downto 0);
turn_faults_0: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_0: in std_logic_vector(7 downto 0);
Cx_reconf_PE_0: in std_logic_vector(3 downto 0);
Reconfig_command_0 : in std_logic;
--------------
link_faults_1: out std_logic_vector(4 downto 0);
turn_faults_1: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_1: in std_logic_vector(7 downto 0);
Cx_reconf_PE_1: in std_logic_vector(3 downto 0);
Reconfig_command_1 : in std_logic;
--------------
link_faults_2: out std_logic_vector(4 downto 0);
turn_faults_2: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_2: in std_logic_vector(7 downto 0);
Cx_reconf_PE_2: in std_logic_vector(3 downto 0);
Reconfig_command_2 : in std_logic;
--------------
link_faults_3: out std_logic_vector(4 downto 0);
turn_faults_3: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_3: in std_logic_vector(7 downto 0);
Cx_reconf_PE_3: in std_logic_vector(3 downto 0);
Reconfig_command_3 : in std_logic
);
end network_2x2;
architecture behavior of network_2x2 is
component router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end component;
component fault_injector is
generic(DATA_WIDTH : integer := 32);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector(4 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end component;
-- generating bulk signals. not all of them are used in the design...
signal credit_out_N_0, credit_out_E_0, credit_out_W_0, credit_out_S_0: std_logic;
signal credit_out_N_1, credit_out_E_1, credit_out_W_1, credit_out_S_1: std_logic;
signal credit_out_N_2, credit_out_E_2, credit_out_W_2, credit_out_S_2: std_logic;
signal credit_out_N_3, credit_out_E_3, credit_out_W_3, credit_out_S_3: std_logic;
signal credit_in_N_0, credit_in_E_0, credit_in_W_0, credit_in_S_0: std_logic;
signal credit_in_N_1, credit_in_E_1, credit_in_W_1, credit_in_S_1: std_logic;
signal credit_in_N_2, credit_in_E_2, credit_in_W_2, credit_in_S_2: std_logic;
signal credit_in_N_3, credit_in_E_3, credit_in_W_3, credit_in_S_3: std_logic;
signal RX_N_0, RX_E_0, RX_W_0, RX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_1, RX_E_1, RX_W_1, RX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_2, RX_E_2, RX_W_2, RX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_3, RX_E_3, RX_W_3, RX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal valid_out_N_0, valid_out_E_0, valid_out_W_0, valid_out_S_0: std_logic;
signal valid_out_N_1, valid_out_E_1, valid_out_W_1, valid_out_S_1: std_logic;
signal valid_out_N_2, valid_out_E_2, valid_out_W_2, valid_out_S_2: std_logic;
signal valid_out_N_3, valid_out_E_3, valid_out_W_3, valid_out_S_3: std_logic;
signal valid_in_N_0, valid_in_E_0, valid_in_W_0, valid_in_S_0: std_logic;
signal valid_in_N_1, valid_in_E_1, valid_in_W_1, valid_in_S_1: std_logic;
signal valid_in_N_2, valid_in_E_2, valid_in_W_2, valid_in_S_2: std_logic;
signal valid_in_N_3, valid_in_E_3, valid_in_W_3, valid_in_S_3: std_logic;
signal TX_N_0, TX_E_0, TX_W_0, TX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_1, TX_E_1, TX_W_1, TX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_2, TX_E_2, TX_W_2, TX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_3, TX_E_3, TX_W_3, TX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal Faulty_N_out0,Faulty_E_out0,Faulty_W_out0,Faulty_S_out0: std_logic;
signal Faulty_N_in0,Faulty_E_in0,Faulty_W_in0,Faulty_S_in0: std_logic;
signal Faulty_N_out1,Faulty_E_out1,Faulty_W_out1,Faulty_S_out1: std_logic;
signal Faulty_N_in1,Faulty_E_in1,Faulty_W_in1,Faulty_S_in1: std_logic;
signal Faulty_N_out2,Faulty_E_out2,Faulty_W_out2,Faulty_S_out2: std_logic;
signal Faulty_N_in2,Faulty_E_in2,Faulty_W_in2,Faulty_S_in2: std_logic;
signal Faulty_N_out3,Faulty_E_out3,Faulty_W_out3,Faulty_S_out3: std_logic;
signal Faulty_N_in3,Faulty_E_in3,Faulty_W_in3,Faulty_S_in3: std_logic;
-- organizaiton of the network:
-- x --------------->
-- y ---- ----
-- | | 0 | -*- | 1 |
-- | ---- ----
-- | * *
-- | ---- ----
-- | | 2 | -*- | 3 |
-- v ---- ----
--
begin
R_0: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 0, Rxy_rst => 60,
Cx_rst => 10, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_0, RX_E_0, RX_W_0, RX_S_0, RX_L_0,
credit_in_N_0, credit_in_E_0, credit_in_W_0, credit_in_S_0, credit_in_L_0,
valid_in_N_0, valid_in_E_0, valid_in_W_0, valid_in_S_0, valid_in_L_0,
valid_out_N_0, valid_out_E_0, valid_out_W_0, valid_out_S_0, valid_out_L_0,
credit_out_N_0, credit_out_E_0, credit_out_W_0, credit_out_S_0, credit_out_L_0,
TX_N_0, TX_E_0, TX_W_0, TX_S_0, TX_L_0,
Faulty_N_in0,Faulty_E_in0,Faulty_W_in0,Faulty_S_in0,
Faulty_N_out0,Faulty_E_out0,Faulty_W_out0,Faulty_S_out0,
-- should be connected to NI
link_faults_0, turn_faults_0,
Rxy_reconf_PE_0, Cx_reconf_PE_0, Reconfig_command_0
);
R_1: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 1, Rxy_rst => 60,
Cx_rst => 12, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_1, RX_E_1, RX_W_1, RX_S_1, RX_L_1,
credit_in_N_1, credit_in_E_1, credit_in_W_1, credit_in_S_1, credit_in_L_1,
valid_in_N_1, valid_in_E_1, valid_in_W_1, valid_in_S_1, valid_in_L_1,
valid_out_N_1, valid_out_E_1, valid_out_W_1, valid_out_S_1, valid_out_L_1,
credit_out_N_1, credit_out_E_1, credit_out_W_1, credit_out_S_1, credit_out_L_1,
TX_N_1, TX_E_1, TX_W_1, TX_S_1, TX_L_1,
Faulty_N_in1,Faulty_E_in1,Faulty_W_in1,Faulty_S_in1,
Faulty_N_out1,Faulty_E_out1,Faulty_W_out1,Faulty_S_out1,
-- should be connected to NI
link_faults_1, turn_faults_1,
Rxy_reconf_PE_1, Cx_reconf_PE_1, Reconfig_command_1
);
R_2: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 2, Rxy_rst => 60,
Cx_rst => 3, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_2, RX_E_2, RX_W_2, RX_S_2, RX_L_2,
credit_in_N_2, credit_in_E_2, credit_in_W_2, credit_in_S_2, credit_in_L_2,
valid_in_N_2, valid_in_E_2, valid_in_W_2, valid_in_S_2, valid_in_L_2,
valid_out_N_2, valid_out_E_2, valid_out_W_2, valid_out_S_2, valid_out_L_2,
credit_out_N_2, credit_out_E_2, credit_out_W_2, credit_out_S_2, credit_out_L_2,
TX_N_2, TX_E_2, TX_W_2, TX_S_2, TX_L_2,
Faulty_N_in2,Faulty_E_in2,Faulty_W_in2,Faulty_S_in2,
Faulty_N_out2,Faulty_E_out2,Faulty_W_out2,Faulty_S_out2,
-- should be connected to NI
link_faults_2, turn_faults_2,
Rxy_reconf_PE_2, Cx_reconf_PE_2, Reconfig_command_2
);
R_3: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 3, Rxy_rst => 60,
Cx_rst => 5, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_3, RX_E_3, RX_W_3, RX_S_3, RX_L_3,
credit_in_N_3, credit_in_E_3, credit_in_W_3, credit_in_S_3, credit_in_L_3,
valid_in_N_3, valid_in_E_3, valid_in_W_3, valid_in_S_3, valid_in_L_3,
valid_out_N_3, valid_out_E_3, valid_out_W_3, valid_out_S_3, valid_out_L_3,
credit_out_N_3, credit_out_E_3, credit_out_W_3, credit_out_S_3, credit_out_L_3,
TX_N_3, TX_E_3, TX_W_3, TX_S_3, TX_L_3,
Faulty_N_in3,Faulty_E_in3,Faulty_W_in3,Faulty_S_in3,
Faulty_N_out3,Faulty_E_out3,Faulty_W_out3,Faulty_S_out3,
-- should be connected to NI
link_faults_3, turn_faults_3,
Rxy_reconf_PE_3, Cx_reconf_PE_3, Reconfig_command_3
);
-- instantiating the Fault injectors
-- vertical FIs
FI_0_2: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_S_0,
address => FI_Add_0_2,
sta_0 => sta0_0_2,
sta_1 => sta1_0_2,
data_out => RX_N_2
);
FI_2_0: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_N_2,
address => FI_Add_2_0,
sta_0 => sta0_2_0,
sta_1 => sta1_2_0,
data_out => RX_S_0
);
FI_1_3: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_S_1,
address => FI_Add_1_3,
sta_0 => sta0_1_3,
sta_1 => sta1_1_3,
data_out => RX_N_3
);
FI_3_1: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_N_3,
address => FI_Add_3_1,
sta_0 => sta0_3_1,
sta_1 => sta1_3_1,
data_out => RX_S_1
);
-- horizontal FIs
FI_0_1: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_E_0,
address => FI_Add_0_1,
sta_0 => sta0_0_1,
sta_1 => sta1_0_1,
data_out => RX_W_1
);
FI_1_0: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_W_1,
address => FI_Add_1_0,
sta_0 => sta0_1_0,
sta_1 => sta1_1_0,
data_out => RX_E_0
);
FI_2_3: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_E_2,
address => FI_Add_2_3,
sta_0 => sta0_2_3,
sta_1 => sta1_2_3,
data_out => RX_W_3
);
FI_3_2: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_W_3,
address => FI_Add_3_2,
sta_0 => sta0_3_2,
sta_1 => sta1_3_2,
data_out => RX_E_2
);
---------------------------------------------------------------
-- binding the routers together
-- connecting router: 0 to router: 2 and vice versa
valid_in_N_2 <= valid_out_S_0;
valid_in_S_0 <= valid_out_N_2;
credit_in_S_0 <= credit_out_N_2;
credit_in_N_2 <= credit_out_S_0;
-------------------
-- connecting router: 1 to router: 3 and vice versa
valid_in_N_3 <= valid_out_S_1;
valid_in_S_1 <= valid_out_N_3;
credit_in_S_1 <= credit_out_N_3;
credit_in_N_3 <= credit_out_S_1;
-------------------
-- connecting router: 0 to router: 1 and vice versa
valid_in_E_0 <= valid_out_W_1;
valid_in_W_1 <= valid_out_E_0;
credit_in_W_1 <= credit_out_E_0;
credit_in_E_0 <= credit_out_W_1;
-------------------
-- connecting router: 2 to router: 3 and vice versa
valid_in_E_2 <= valid_out_W_3;
valid_in_W_3 <= valid_out_E_2;
credit_in_W_3 <= credit_out_E_2;
credit_in_E_2 <= credit_out_W_3;
-------------------
Faulty_S_in0 <= Faulty_N_out2;
Faulty_E_in0 <= Faulty_W_out1;
Faulty_S_in1 <= Faulty_N_out3;
Faulty_W_in1 <= Faulty_E_out0;
Faulty_N_in2 <= Faulty_S_out0;
Faulty_E_in2 <= Faulty_W_out3;
Faulty_N_in3 <= Faulty_S_out1;
Faulty_W_in3 <= Faulty_E_out2;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- LV network: False
-- Data width: 32
-- Parity: False
-- Fault injectors: True
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
entity network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
--------------
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--fault injector signals
FI_Add_2_0, FI_Add_0_2: in std_logic_vector(4 downto 0);
sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0: in std_logic;
FI_Add_3_1, FI_Add_1_3: in std_logic_vector(4 downto 0);
sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1: in std_logic;
FI_Add_1_0, FI_Add_0_1: in std_logic_vector(4 downto 0);
sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0: in std_logic;
FI_Add_3_2, FI_Add_2_3: in std_logic_vector(4 downto 0);
sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2: in std_logic;
--------------
link_faults_0: out std_logic_vector(4 downto 0);
turn_faults_0: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_0: in std_logic_vector(7 downto 0);
Cx_reconf_PE_0: in std_logic_vector(3 downto 0);
Reconfig_command_0 : in std_logic;
--------------
link_faults_1: out std_logic_vector(4 downto 0);
turn_faults_1: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_1: in std_logic_vector(7 downto 0);
Cx_reconf_PE_1: in std_logic_vector(3 downto 0);
Reconfig_command_1 : in std_logic;
--------------
link_faults_2: out std_logic_vector(4 downto 0);
turn_faults_2: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_2: in std_logic_vector(7 downto 0);
Cx_reconf_PE_2: in std_logic_vector(3 downto 0);
Reconfig_command_2 : in std_logic;
--------------
link_faults_3: out std_logic_vector(4 downto 0);
turn_faults_3: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_3: in std_logic_vector(7 downto 0);
Cx_reconf_PE_3: in std_logic_vector(3 downto 0);
Reconfig_command_3 : in std_logic
);
end network_2x2;
architecture behavior of network_2x2 is
component router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end component;
component fault_injector is
generic(DATA_WIDTH : integer := 32);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector(4 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end component;
-- generating bulk signals. not all of them are used in the design...
signal credit_out_N_0, credit_out_E_0, credit_out_W_0, credit_out_S_0: std_logic;
signal credit_out_N_1, credit_out_E_1, credit_out_W_1, credit_out_S_1: std_logic;
signal credit_out_N_2, credit_out_E_2, credit_out_W_2, credit_out_S_2: std_logic;
signal credit_out_N_3, credit_out_E_3, credit_out_W_3, credit_out_S_3: std_logic;
signal credit_in_N_0, credit_in_E_0, credit_in_W_0, credit_in_S_0: std_logic;
signal credit_in_N_1, credit_in_E_1, credit_in_W_1, credit_in_S_1: std_logic;
signal credit_in_N_2, credit_in_E_2, credit_in_W_2, credit_in_S_2: std_logic;
signal credit_in_N_3, credit_in_E_3, credit_in_W_3, credit_in_S_3: std_logic;
signal RX_N_0, RX_E_0, RX_W_0, RX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_1, RX_E_1, RX_W_1, RX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_2, RX_E_2, RX_W_2, RX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_3, RX_E_3, RX_W_3, RX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal valid_out_N_0, valid_out_E_0, valid_out_W_0, valid_out_S_0: std_logic;
signal valid_out_N_1, valid_out_E_1, valid_out_W_1, valid_out_S_1: std_logic;
signal valid_out_N_2, valid_out_E_2, valid_out_W_2, valid_out_S_2: std_logic;
signal valid_out_N_3, valid_out_E_3, valid_out_W_3, valid_out_S_3: std_logic;
signal valid_in_N_0, valid_in_E_0, valid_in_W_0, valid_in_S_0: std_logic;
signal valid_in_N_1, valid_in_E_1, valid_in_W_1, valid_in_S_1: std_logic;
signal valid_in_N_2, valid_in_E_2, valid_in_W_2, valid_in_S_2: std_logic;
signal valid_in_N_3, valid_in_E_3, valid_in_W_3, valid_in_S_3: std_logic;
signal TX_N_0, TX_E_0, TX_W_0, TX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_1, TX_E_1, TX_W_1, TX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_2, TX_E_2, TX_W_2, TX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_3, TX_E_3, TX_W_3, TX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal Faulty_N_out0,Faulty_E_out0,Faulty_W_out0,Faulty_S_out0: std_logic;
signal Faulty_N_in0,Faulty_E_in0,Faulty_W_in0,Faulty_S_in0: std_logic;
signal Faulty_N_out1,Faulty_E_out1,Faulty_W_out1,Faulty_S_out1: std_logic;
signal Faulty_N_in1,Faulty_E_in1,Faulty_W_in1,Faulty_S_in1: std_logic;
signal Faulty_N_out2,Faulty_E_out2,Faulty_W_out2,Faulty_S_out2: std_logic;
signal Faulty_N_in2,Faulty_E_in2,Faulty_W_in2,Faulty_S_in2: std_logic;
signal Faulty_N_out3,Faulty_E_out3,Faulty_W_out3,Faulty_S_out3: std_logic;
signal Faulty_N_in3,Faulty_E_in3,Faulty_W_in3,Faulty_S_in3: std_logic;
-- organizaiton of the network:
-- x --------------->
-- y ---- ----
-- | | 0 | -*- | 1 |
-- | ---- ----
-- | * *
-- | ---- ----
-- | | 2 | -*- | 3 |
-- v ---- ----
--
begin
R_0: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 0, Rxy_rst => 60,
Cx_rst => 10, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_0, RX_E_0, RX_W_0, RX_S_0, RX_L_0,
credit_in_N_0, credit_in_E_0, credit_in_W_0, credit_in_S_0, credit_in_L_0,
valid_in_N_0, valid_in_E_0, valid_in_W_0, valid_in_S_0, valid_in_L_0,
valid_out_N_0, valid_out_E_0, valid_out_W_0, valid_out_S_0, valid_out_L_0,
credit_out_N_0, credit_out_E_0, credit_out_W_0, credit_out_S_0, credit_out_L_0,
TX_N_0, TX_E_0, TX_W_0, TX_S_0, TX_L_0,
Faulty_N_in0,Faulty_E_in0,Faulty_W_in0,Faulty_S_in0,
Faulty_N_out0,Faulty_E_out0,Faulty_W_out0,Faulty_S_out0,
-- should be connected to NI
link_faults_0, turn_faults_0,
Rxy_reconf_PE_0, Cx_reconf_PE_0, Reconfig_command_0
);
R_1: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 1, Rxy_rst => 60,
Cx_rst => 12, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_1, RX_E_1, RX_W_1, RX_S_1, RX_L_1,
credit_in_N_1, credit_in_E_1, credit_in_W_1, credit_in_S_1, credit_in_L_1,
valid_in_N_1, valid_in_E_1, valid_in_W_1, valid_in_S_1, valid_in_L_1,
valid_out_N_1, valid_out_E_1, valid_out_W_1, valid_out_S_1, valid_out_L_1,
credit_out_N_1, credit_out_E_1, credit_out_W_1, credit_out_S_1, credit_out_L_1,
TX_N_1, TX_E_1, TX_W_1, TX_S_1, TX_L_1,
Faulty_N_in1,Faulty_E_in1,Faulty_W_in1,Faulty_S_in1,
Faulty_N_out1,Faulty_E_out1,Faulty_W_out1,Faulty_S_out1,
-- should be connected to NI
link_faults_1, turn_faults_1,
Rxy_reconf_PE_1, Cx_reconf_PE_1, Reconfig_command_1
);
R_2: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 2, Rxy_rst => 60,
Cx_rst => 3, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_2, RX_E_2, RX_W_2, RX_S_2, RX_L_2,
credit_in_N_2, credit_in_E_2, credit_in_W_2, credit_in_S_2, credit_in_L_2,
valid_in_N_2, valid_in_E_2, valid_in_W_2, valid_in_S_2, valid_in_L_2,
valid_out_N_2, valid_out_E_2, valid_out_W_2, valid_out_S_2, valid_out_L_2,
credit_out_N_2, credit_out_E_2, credit_out_W_2, credit_out_S_2, credit_out_L_2,
TX_N_2, TX_E_2, TX_W_2, TX_S_2, TX_L_2,
Faulty_N_in2,Faulty_E_in2,Faulty_W_in2,Faulty_S_in2,
Faulty_N_out2,Faulty_E_out2,Faulty_W_out2,Faulty_S_out2,
-- should be connected to NI
link_faults_2, turn_faults_2,
Rxy_reconf_PE_2, Cx_reconf_PE_2, Reconfig_command_2
);
R_3: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 3, Rxy_rst => 60,
Cx_rst => 5, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_3, RX_E_3, RX_W_3, RX_S_3, RX_L_3,
credit_in_N_3, credit_in_E_3, credit_in_W_3, credit_in_S_3, credit_in_L_3,
valid_in_N_3, valid_in_E_3, valid_in_W_3, valid_in_S_3, valid_in_L_3,
valid_out_N_3, valid_out_E_3, valid_out_W_3, valid_out_S_3, valid_out_L_3,
credit_out_N_3, credit_out_E_3, credit_out_W_3, credit_out_S_3, credit_out_L_3,
TX_N_3, TX_E_3, TX_W_3, TX_S_3, TX_L_3,
Faulty_N_in3,Faulty_E_in3,Faulty_W_in3,Faulty_S_in3,
Faulty_N_out3,Faulty_E_out3,Faulty_W_out3,Faulty_S_out3,
-- should be connected to NI
link_faults_3, turn_faults_3,
Rxy_reconf_PE_3, Cx_reconf_PE_3, Reconfig_command_3
);
-- instantiating the Fault injectors
-- vertical FIs
FI_0_2: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_S_0,
address => FI_Add_0_2,
sta_0 => sta0_0_2,
sta_1 => sta1_0_2,
data_out => RX_N_2
);
FI_2_0: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_N_2,
address => FI_Add_2_0,
sta_0 => sta0_2_0,
sta_1 => sta1_2_0,
data_out => RX_S_0
);
FI_1_3: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_S_1,
address => FI_Add_1_3,
sta_0 => sta0_1_3,
sta_1 => sta1_1_3,
data_out => RX_N_3
);
FI_3_1: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_N_3,
address => FI_Add_3_1,
sta_0 => sta0_3_1,
sta_1 => sta1_3_1,
data_out => RX_S_1
);
-- horizontal FIs
FI_0_1: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_E_0,
address => FI_Add_0_1,
sta_0 => sta0_0_1,
sta_1 => sta1_0_1,
data_out => RX_W_1
);
FI_1_0: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_W_1,
address => FI_Add_1_0,
sta_0 => sta0_1_0,
sta_1 => sta1_1_0,
data_out => RX_E_0
);
FI_2_3: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_E_2,
address => FI_Add_2_3,
sta_0 => sta0_2_3,
sta_1 => sta1_2_3,
data_out => RX_W_3
);
FI_3_2: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_W_3,
address => FI_Add_3_2,
sta_0 => sta0_3_2,
sta_1 => sta1_3_2,
data_out => RX_E_2
);
---------------------------------------------------------------
-- binding the routers together
-- connecting router: 0 to router: 2 and vice versa
valid_in_N_2 <= valid_out_S_0;
valid_in_S_0 <= valid_out_N_2;
credit_in_S_0 <= credit_out_N_2;
credit_in_N_2 <= credit_out_S_0;
-------------------
-- connecting router: 1 to router: 3 and vice versa
valid_in_N_3 <= valid_out_S_1;
valid_in_S_1 <= valid_out_N_3;
credit_in_S_1 <= credit_out_N_3;
credit_in_N_3 <= credit_out_S_1;
-------------------
-- connecting router: 0 to router: 1 and vice versa
valid_in_E_0 <= valid_out_W_1;
valid_in_W_1 <= valid_out_E_0;
credit_in_W_1 <= credit_out_E_0;
credit_in_E_0 <= credit_out_W_1;
-------------------
-- connecting router: 2 to router: 3 and vice versa
valid_in_E_2 <= valid_out_W_3;
valid_in_W_3 <= valid_out_E_2;
credit_in_W_3 <= credit_out_E_2;
credit_in_E_2 <= credit_out_W_3;
-------------------
Faulty_S_in0 <= Faulty_N_out2;
Faulty_E_in0 <= Faulty_W_out1;
Faulty_S_in1 <= Faulty_N_out3;
Faulty_W_in1 <= Faulty_E_out0;
Faulty_N_in2 <= Faulty_S_out0;
Faulty_E_in2 <= Faulty_W_out3;
Faulty_N_in3 <= Faulty_S_out1;
Faulty_W_in3 <= Faulty_E_out2;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- LV network: False
-- Data width: 32
-- Parity: False
-- Fault injectors: True
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
entity network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
--------------
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--fault injector signals
FI_Add_2_0, FI_Add_0_2: in std_logic_vector(4 downto 0);
sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0: in std_logic;
FI_Add_3_1, FI_Add_1_3: in std_logic_vector(4 downto 0);
sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1: in std_logic;
FI_Add_1_0, FI_Add_0_1: in std_logic_vector(4 downto 0);
sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0: in std_logic;
FI_Add_3_2, FI_Add_2_3: in std_logic_vector(4 downto 0);
sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2: in std_logic;
--------------
link_faults_0: out std_logic_vector(4 downto 0);
turn_faults_0: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_0: in std_logic_vector(7 downto 0);
Cx_reconf_PE_0: in std_logic_vector(3 downto 0);
Reconfig_command_0 : in std_logic;
--------------
link_faults_1: out std_logic_vector(4 downto 0);
turn_faults_1: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_1: in std_logic_vector(7 downto 0);
Cx_reconf_PE_1: in std_logic_vector(3 downto 0);
Reconfig_command_1 : in std_logic;
--------------
link_faults_2: out std_logic_vector(4 downto 0);
turn_faults_2: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_2: in std_logic_vector(7 downto 0);
Cx_reconf_PE_2: in std_logic_vector(3 downto 0);
Reconfig_command_2 : in std_logic;
--------------
link_faults_3: out std_logic_vector(4 downto 0);
turn_faults_3: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_3: in std_logic_vector(7 downto 0);
Cx_reconf_PE_3: in std_logic_vector(3 downto 0);
Reconfig_command_3 : in std_logic
);
end network_2x2;
architecture behavior of network_2x2 is
component router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end component;
component fault_injector is
generic(DATA_WIDTH : integer := 32);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector(4 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end component;
-- generating bulk signals. not all of them are used in the design...
signal credit_out_N_0, credit_out_E_0, credit_out_W_0, credit_out_S_0: std_logic;
signal credit_out_N_1, credit_out_E_1, credit_out_W_1, credit_out_S_1: std_logic;
signal credit_out_N_2, credit_out_E_2, credit_out_W_2, credit_out_S_2: std_logic;
signal credit_out_N_3, credit_out_E_3, credit_out_W_3, credit_out_S_3: std_logic;
signal credit_in_N_0, credit_in_E_0, credit_in_W_0, credit_in_S_0: std_logic;
signal credit_in_N_1, credit_in_E_1, credit_in_W_1, credit_in_S_1: std_logic;
signal credit_in_N_2, credit_in_E_2, credit_in_W_2, credit_in_S_2: std_logic;
signal credit_in_N_3, credit_in_E_3, credit_in_W_3, credit_in_S_3: std_logic;
signal RX_N_0, RX_E_0, RX_W_0, RX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_1, RX_E_1, RX_W_1, RX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_2, RX_E_2, RX_W_2, RX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_3, RX_E_3, RX_W_3, RX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal valid_out_N_0, valid_out_E_0, valid_out_W_0, valid_out_S_0: std_logic;
signal valid_out_N_1, valid_out_E_1, valid_out_W_1, valid_out_S_1: std_logic;
signal valid_out_N_2, valid_out_E_2, valid_out_W_2, valid_out_S_2: std_logic;
signal valid_out_N_3, valid_out_E_3, valid_out_W_3, valid_out_S_3: std_logic;
signal valid_in_N_0, valid_in_E_0, valid_in_W_0, valid_in_S_0: std_logic;
signal valid_in_N_1, valid_in_E_1, valid_in_W_1, valid_in_S_1: std_logic;
signal valid_in_N_2, valid_in_E_2, valid_in_W_2, valid_in_S_2: std_logic;
signal valid_in_N_3, valid_in_E_3, valid_in_W_3, valid_in_S_3: std_logic;
signal TX_N_0, TX_E_0, TX_W_0, TX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_1, TX_E_1, TX_W_1, TX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_2, TX_E_2, TX_W_2, TX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_3, TX_E_3, TX_W_3, TX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal Faulty_N_out0,Faulty_E_out0,Faulty_W_out0,Faulty_S_out0: std_logic;
signal Faulty_N_in0,Faulty_E_in0,Faulty_W_in0,Faulty_S_in0: std_logic;
signal Faulty_N_out1,Faulty_E_out1,Faulty_W_out1,Faulty_S_out1: std_logic;
signal Faulty_N_in1,Faulty_E_in1,Faulty_W_in1,Faulty_S_in1: std_logic;
signal Faulty_N_out2,Faulty_E_out2,Faulty_W_out2,Faulty_S_out2: std_logic;
signal Faulty_N_in2,Faulty_E_in2,Faulty_W_in2,Faulty_S_in2: std_logic;
signal Faulty_N_out3,Faulty_E_out3,Faulty_W_out3,Faulty_S_out3: std_logic;
signal Faulty_N_in3,Faulty_E_in3,Faulty_W_in3,Faulty_S_in3: std_logic;
-- organizaiton of the network:
-- x --------------->
-- y ---- ----
-- | | 0 | -*- | 1 |
-- | ---- ----
-- | * *
-- | ---- ----
-- | | 2 | -*- | 3 |
-- v ---- ----
--
begin
R_0: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 0, Rxy_rst => 60,
Cx_rst => 10, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_0, RX_E_0, RX_W_0, RX_S_0, RX_L_0,
credit_in_N_0, credit_in_E_0, credit_in_W_0, credit_in_S_0, credit_in_L_0,
valid_in_N_0, valid_in_E_0, valid_in_W_0, valid_in_S_0, valid_in_L_0,
valid_out_N_0, valid_out_E_0, valid_out_W_0, valid_out_S_0, valid_out_L_0,
credit_out_N_0, credit_out_E_0, credit_out_W_0, credit_out_S_0, credit_out_L_0,
TX_N_0, TX_E_0, TX_W_0, TX_S_0, TX_L_0,
Faulty_N_in0,Faulty_E_in0,Faulty_W_in0,Faulty_S_in0,
Faulty_N_out0,Faulty_E_out0,Faulty_W_out0,Faulty_S_out0,
-- should be connected to NI
link_faults_0, turn_faults_0,
Rxy_reconf_PE_0, Cx_reconf_PE_0, Reconfig_command_0
);
R_1: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 1, Rxy_rst => 60,
Cx_rst => 12, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_1, RX_E_1, RX_W_1, RX_S_1, RX_L_1,
credit_in_N_1, credit_in_E_1, credit_in_W_1, credit_in_S_1, credit_in_L_1,
valid_in_N_1, valid_in_E_1, valid_in_W_1, valid_in_S_1, valid_in_L_1,
valid_out_N_1, valid_out_E_1, valid_out_W_1, valid_out_S_1, valid_out_L_1,
credit_out_N_1, credit_out_E_1, credit_out_W_1, credit_out_S_1, credit_out_L_1,
TX_N_1, TX_E_1, TX_W_1, TX_S_1, TX_L_1,
Faulty_N_in1,Faulty_E_in1,Faulty_W_in1,Faulty_S_in1,
Faulty_N_out1,Faulty_E_out1,Faulty_W_out1,Faulty_S_out1,
-- should be connected to NI
link_faults_1, turn_faults_1,
Rxy_reconf_PE_1, Cx_reconf_PE_1, Reconfig_command_1
);
R_2: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 2, Rxy_rst => 60,
Cx_rst => 3, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_2, RX_E_2, RX_W_2, RX_S_2, RX_L_2,
credit_in_N_2, credit_in_E_2, credit_in_W_2, credit_in_S_2, credit_in_L_2,
valid_in_N_2, valid_in_E_2, valid_in_W_2, valid_in_S_2, valid_in_L_2,
valid_out_N_2, valid_out_E_2, valid_out_W_2, valid_out_S_2, valid_out_L_2,
credit_out_N_2, credit_out_E_2, credit_out_W_2, credit_out_S_2, credit_out_L_2,
TX_N_2, TX_E_2, TX_W_2, TX_S_2, TX_L_2,
Faulty_N_in2,Faulty_E_in2,Faulty_W_in2,Faulty_S_in2,
Faulty_N_out2,Faulty_E_out2,Faulty_W_out2,Faulty_S_out2,
-- should be connected to NI
link_faults_2, turn_faults_2,
Rxy_reconf_PE_2, Cx_reconf_PE_2, Reconfig_command_2
);
R_3: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 3, Rxy_rst => 60,
Cx_rst => 5, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_3, RX_E_3, RX_W_3, RX_S_3, RX_L_3,
credit_in_N_3, credit_in_E_3, credit_in_W_3, credit_in_S_3, credit_in_L_3,
valid_in_N_3, valid_in_E_3, valid_in_W_3, valid_in_S_3, valid_in_L_3,
valid_out_N_3, valid_out_E_3, valid_out_W_3, valid_out_S_3, valid_out_L_3,
credit_out_N_3, credit_out_E_3, credit_out_W_3, credit_out_S_3, credit_out_L_3,
TX_N_3, TX_E_3, TX_W_3, TX_S_3, TX_L_3,
Faulty_N_in3,Faulty_E_in3,Faulty_W_in3,Faulty_S_in3,
Faulty_N_out3,Faulty_E_out3,Faulty_W_out3,Faulty_S_out3,
-- should be connected to NI
link_faults_3, turn_faults_3,
Rxy_reconf_PE_3, Cx_reconf_PE_3, Reconfig_command_3
);
-- instantiating the Fault injectors
-- vertical FIs
FI_0_2: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_S_0,
address => FI_Add_0_2,
sta_0 => sta0_0_2,
sta_1 => sta1_0_2,
data_out => RX_N_2
);
FI_2_0: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_N_2,
address => FI_Add_2_0,
sta_0 => sta0_2_0,
sta_1 => sta1_2_0,
data_out => RX_S_0
);
FI_1_3: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_S_1,
address => FI_Add_1_3,
sta_0 => sta0_1_3,
sta_1 => sta1_1_3,
data_out => RX_N_3
);
FI_3_1: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_N_3,
address => FI_Add_3_1,
sta_0 => sta0_3_1,
sta_1 => sta1_3_1,
data_out => RX_S_1
);
-- horizontal FIs
FI_0_1: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_E_0,
address => FI_Add_0_1,
sta_0 => sta0_0_1,
sta_1 => sta1_0_1,
data_out => RX_W_1
);
FI_1_0: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_W_1,
address => FI_Add_1_0,
sta_0 => sta0_1_0,
sta_1 => sta1_1_0,
data_out => RX_E_0
);
FI_2_3: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_E_2,
address => FI_Add_2_3,
sta_0 => sta0_2_3,
sta_1 => sta1_2_3,
data_out => RX_W_3
);
FI_3_2: fault_injector generic map(DATA_WIDTH => DATA_WIDTH)
port map(
data_in => TX_W_3,
address => FI_Add_3_2,
sta_0 => sta0_3_2,
sta_1 => sta1_3_2,
data_out => RX_E_2
);
---------------------------------------------------------------
-- binding the routers together
-- connecting router: 0 to router: 2 and vice versa
valid_in_N_2 <= valid_out_S_0;
valid_in_S_0 <= valid_out_N_2;
credit_in_S_0 <= credit_out_N_2;
credit_in_N_2 <= credit_out_S_0;
-------------------
-- connecting router: 1 to router: 3 and vice versa
valid_in_N_3 <= valid_out_S_1;
valid_in_S_1 <= valid_out_N_3;
credit_in_S_1 <= credit_out_N_3;
credit_in_N_3 <= credit_out_S_1;
-------------------
-- connecting router: 0 to router: 1 and vice versa
valid_in_E_0 <= valid_out_W_1;
valid_in_W_1 <= valid_out_E_0;
credit_in_W_1 <= credit_out_E_0;
credit_in_E_0 <= credit_out_W_1;
-------------------
-- connecting router: 2 to router: 3 and vice versa
valid_in_E_2 <= valid_out_W_3;
valid_in_W_3 <= valid_out_E_2;
credit_in_W_3 <= credit_out_E_2;
credit_in_E_2 <= credit_out_W_3;
-------------------
Faulty_S_in0 <= Faulty_N_out2;
Faulty_E_in0 <= Faulty_W_out1;
Faulty_S_in1 <= Faulty_N_out3;
Faulty_W_in1 <= Faulty_E_out0;
Faulty_N_in2 <= Faulty_S_out0;
Faulty_E_in2 <= Faulty_W_out3;
Faulty_N_in3 <= Faulty_S_out1;
Faulty_W_in3 <= Faulty_E_out2;
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := artix7;
constant CFG_CLKMUL : integer := (9);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 1 + 64*0;
constant CFG_ATBSZ : integer := 1;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 128;
constant CFG_AHBRADDR : integer := 16#400#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0B#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (2);
constant CFG_SPIMCTRL_ASCALER : integer := (2);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
|
library verilog;
use verilog.vl_types.all;
entity pipeline_vlg_tst is
end pipeline_vlg_tst;
|
library verilog;
use verilog.vl_types.all;
entity pipeline_vlg_tst is
end pipeline_vlg_tst;
|
-- ================================================================================
-- Legal Notice: Copyright (C) 1991-2006 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
-- ================================================================================
--
-- Generated by: FIR Compiler 9.0
-- Generated on: 2014-8-27 12:08:48
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity tb_matchfilter is
--START MEGAWIZARD INSERT CONSTANTS
constant FIR_INPUT_FILE_c : string := "matchfilter_input.txt";
constant FIR_OUTPUT_FILE_c : string := "matchfilter_output.txt";
constant NUM_OF_CHANNELS_c : natural := 1;
constant DATA_WIDTH_c : natural := 15;
constant CHANNEL_OUT_WIDTH_c : natural := 0;
constant OUT_WIDTH_c : natural := 30;
constant COEF_SET_ADDRESS_WIDTH_c : natural := 0;
constant COEF_RELOAD_BIT_WIDTH_c : natural := 11;
--END MEGAWIZARD INSERT CONSTANTS
end entity tb_matchfilter;
--library work;
--library auk_dspip_lib;
-------------------------------------------------------------------------------
architecture rtl of tb_matchfilter is
signal ast_sink_data : std_logic_vector (DATA_WIDTH_c-1 downto 0) := (others => '0');
signal ast_source_data : std_logic_vector (OUT_WIDTH_c-1 downto 0);
signal ast_sink_error : std_logic_vector (1 downto 0) := (others => '0');
signal ast_source_error : std_logic_vector (1 downto 0);
signal ast_sink_valid : std_logic := '0';
signal ast_source_valid : std_logic;
signal ast_source_ready : std_logic := '0';
signal clk : std_logic := '0';
signal reset_testbench : std_logic := '0';
signal reset_design : std_logic;
signal eof : std_logic;
signal ast_sink_ready : std_logic;
signal start : std_logic;
signal cnt : natural range 0 to NUM_OF_CHANNELS_c;
constant tclk : time := 10 ns;
constant time_lapse_max : time := 60 us;
signal time_lapse : time;
begin
DUT : entity work.matchfilter
port map (
clk => clk,
reset_n => reset_design,
ast_sink_ready => ast_sink_ready,
ast_sink_data => ast_sink_data,
ast_source_data => ast_source_data,
ast_sink_valid => ast_sink_valid,
ast_source_valid => ast_source_valid,
ast_source_ready => ast_source_ready,
ast_sink_error => ast_sink_error,
ast_source_error => ast_source_error);
-- for example purposes, the ready signal is always asserted.
ast_source_ready <= '1';
-- no input error
ast_sink_error <= (others => '0');
-- start valid for first cycle to indicate that the file reading should start.
start_p : process (clk, reset_testbench)
begin
if reset_testbench = '0' then
start <= '1';
elsif rising_edge(clk) then
if ast_sink_valid = '1' and ast_sink_ready = '1' then
start <= '0';
end if;
end if;
end process start_p;
-----------------------------------------------------------------------------------------------
-- Read input data from file
-----------------------------------------------------------------------------------------------
source_model : process(clk) is
file in_file : text open read_mode is FIR_INPUT_FILE_c;
variable data_in : integer;
variable indata : line;
begin
if rising_edge(clk) then
if(reset_testbench = '0') then
ast_sink_data <= std_logic_vector(to_signed(0, DATA_WIDTH_c)) after tclk/4;
ast_sink_valid <= '0' after tclk/4;
eof <= '0';
else
if not endfile(in_file) and (eof = '0') then
eof <= '0';
if((ast_sink_valid = '1' and ast_sink_ready = '1') or
(start = '1'and not (ast_sink_valid = '1' and ast_sink_ready = '0'))) then
readline(in_file, indata);
read(indata, data_in);
ast_sink_valid <= '1' after tclk/4;
ast_sink_data <= std_logic_vector(to_signed(data_in, DATA_WIDTH_c)) after tclk/4;
else
ast_sink_valid <= '1' after tclk/4;
ast_sink_data <= ast_sink_data after tclk/4;
end if;
else
eof <= '1';
ast_sink_valid <= '0' after tclk/4;
ast_sink_data <= std_logic_vector(to_signed(0, DATA_WIDTH_c)) after tclk/4;
end if;
end if;
end if;
end process source_model;
---------------------------------------------------------------------------------------------
-- Write FIR output to file
---------------------------------------------------------------------------------------------
sink_model : process(clk) is
file ro_file : text open write_mode is FIR_OUTPUT_FILE_c;
variable rdata : line;
variable data_r : integer;
begin
if rising_edge(clk) then
if(ast_source_valid = '1' and ast_source_ready = '1') then
data_r := to_integer(signed(ast_source_data));
write(rdata, data_r);
writeline(ro_file, rdata);
end if;
end if;
end process sink_model;
-------------------------------------------------------------------------------
-- clock generator
-------------------------------------------------------------------------------
clkgen : process
begin -- process clkgen
if eof = '1' then
clk <= '0';
assert FALSE
report "NOTE: Stimuli ended" severity note;
wait;
elsif time_lapse >= time_lapse_max then
clk <= '0';
assert FALSE
report "ERROR: Reached time_lapse_max without activity, probably simulation is stuck!" severity Error;
wait;
else
clk <= '0';
wait for tclk/2;
clk <= '1';
wait for tclk/2;
end if;
end process clkgen;
monitor_toggling_activity : process(clk, reset_testbench,
ast_source_data, ast_source_valid)
begin
if reset_testbench = '0' then
time_lapse <= 0 ns;
elsif ast_source_data'event or ast_source_valid'event then
time_lapse <= 0 ns;
elsif rising_edge(clk) then
if time_lapse < time_lapse_max then
time_lapse <= time_lapse + tclk;
end if;
end if;
end process monitor_toggling_activity;
-------------------------------------------------------------------------------
-- reset generator
-------------------------------------------------------------------------------
reset_testbench_gen : process
begin -- process resetgen
reset_testbench <= '1';
wait for tclk/4;
reset_testbench <= '0';
wait for tclk*2;
reset_testbench <= '1';
wait;
end process reset_testbench_gen;
reset_design_gen : process
begin -- process resetgen
reset_design <= '1';
wait for tclk/4;
reset_design <= '0';
wait for tclk*2;
reset_design <= '1';
wait for tclk*80;
reset_design <= '1';
wait for tclk*81*2;
reset_design <= '1';
wait;
end process reset_design_gen;
-------------------------------------------------------------------------------
-- control signals
-------------------------------------------------------------------------------
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1569.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01569ent IS
END c08s10b00x00p03n01i01569ent;
ARCHITECTURE c08s10b00x00p03n01i01569arch OF c08s10b00x00p03n01i01569ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : integer := 0;
BEGIN
L1: for i in boolean loop
k := 5;
L2: for j in 1 to 3 loop
next;
k := 3;
end loop L2;
m := m + 1;
end loop L1;
assert NOT(( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***PASSED TEST: c08s10b00x00p03n01i01569"
severity NOTE;
assert (( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***FAILED TEST: c08s10b00x00p03n01i01569 - A next statement is used without a loop label, it occurs only within a loop and it refers to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01569arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1569.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01569ent IS
END c08s10b00x00p03n01i01569ent;
ARCHITECTURE c08s10b00x00p03n01i01569arch OF c08s10b00x00p03n01i01569ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : integer := 0;
BEGIN
L1: for i in boolean loop
k := 5;
L2: for j in 1 to 3 loop
next;
k := 3;
end loop L2;
m := m + 1;
end loop L1;
assert NOT(( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***PASSED TEST: c08s10b00x00p03n01i01569"
severity NOTE;
assert (( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***FAILED TEST: c08s10b00x00p03n01i01569 - A next statement is used without a loop label, it occurs only within a loop and it refers to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01569arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1569.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01569ent IS
END c08s10b00x00p03n01i01569ent;
ARCHITECTURE c08s10b00x00p03n01i01569arch OF c08s10b00x00p03n01i01569ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : integer := 0;
BEGIN
L1: for i in boolean loop
k := 5;
L2: for j in 1 to 3 loop
next;
k := 3;
end loop L2;
m := m + 1;
end loop L1;
assert NOT(( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***PASSED TEST: c08s10b00x00p03n01i01569"
severity NOTE;
assert (( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***FAILED TEST: c08s10b00x00p03n01i01569 - A next statement is used without a loop label, it occurs only within a loop and it refers to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01569arch;
|
-------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : fan.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-04-28
-- Last update: 2016-08-16
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Pulse width/density modulator
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-04-28 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.util_pkg.all;
entity fan is
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1ppms : in std_logic;
tsc_1ppus : in std_logic;
fan_pct : in std_logic_vector(7 downto 0);
fan_tach : in std_logic;
fan_pwm : out std_logic;
fan_uspr : out std_logic_vector(19 downto 0)
);
end fan;
architecture rtl of fan is
signal pwm_div : std_logic_vector(3 downto 0);
signal pwm_ce : std_logic;
signal pwm_cnt : std_logic_vector(7 downto 0);
signal pwm_term : std_logic;
signal pwm_out : std_logic;
signal tach_dly : std_logic_vector(2 downto 0);
signal tach_pulse : std_logic;
signal tach_meas : std_logic_vector(19 downto 0);
signal tach_msout : std_logic_vector(19 downto 0);
begin
-- First divider to generate clock enable for the PWM
-- Divide by 16
fan_pwmdiv:
process (rst_n, clk) is
begin
if (rst_n = '0') then
pwm_div <= (others => '0');
pwm_ce <= '0';
elsif (clk'event and clk = '1') then
if (pwm_ce = '1') then
pwm_div <= (others => '0');
else
pwm_div <= pwm_div + 1;
end if;
if (pwm_div = x"E") then
pwm_ce <= '1';
else
pwm_ce <= '0';
end if;
end if;
end process;
-- Pulse width modulator counter
fan_pwmcnt:
process (rst_n, clk) is
begin
if (rst_n = '0') then
pwm_cnt <= (others => '0');
pwm_term <= '0';
elsif (clk'event and clk = '1') then
if (pwm_ce = '1') then
pwm_cnt <= pwm_cnt + 1;
if (pwm_cnt = x"FE") then
pwm_term <= '1';
else
pwm_term <= '0';
end if;
end if;
end if;
end process;
-- Pulse width modulator output
fan_pwmout:
process (rst_n, clk) is
begin
if (rst_n = '0') then
pwm_out <= '0';
elsif (clk'event and clk = '1') then
if (pwm_ce = '1') then
if (pwm_term = '1') then
pwm_out <= '1';
elsif (pwm_cnt = fan_pct) then
pwm_out <= '0';
end if;
end if;
end if;
end process;
-- Final output register
fan_oreg: delay_sig generic map (1) port map (rst_n, clk, pwm_out, fan_pwm);
-- ----------------------------------------------------------------------
-- Tach measurement reference is 1 us
-- Tach input buffer and rising edge detector
fan_ireg:
process (rst_n, clk) is
begin
if (rst_n = '0') then
tach_dly <= (others => '0');
tach_pulse <= '0';
elsif (clk'event and clk = '1') then
tach_dly(0) <= fan_tach; -- input register
if (tsc_1ppus = '1') then
tach_dly(1) <= tach_dly(0);
tach_dly(2) <= tach_dly(1);
tach_pulse <= not tach_dly(2) and tach_dly(1);
end if;
end if;
end process;
-- Measure time between tach pulses
fan_meas:
process (rst_n, clk) is
variable tach_add : std_logic_vector(fan_uspr'left + 1 downto 0);
begin
if (rst_n = '0') then
tach_meas <= (others => '0');
tach_msout <= (others => '0');
elsif (clk'event and clk = '1') then
if (tsc_1ppus = '1') then
if (tach_pulse = '1') then
tach_meas <= (others => '0');
tach_meas(0) <= '1'; -- Start measurement at one
else
-- saturating up counter
tach_add := ('0' & tach_meas) + 1;
if (tach_add(tach_add'left) = '0') then
tach_meas <= tach_add(tach_meas'range);
end if;
end if;
-- Output at next pulse or overflow
if (tach_pulse = '1' or tach_add(tach_add'left) = '1') then
tach_msout <= tach_meas;
end if;
end if;
end if;
end process;
fan_uspr <= tach_msout;
end rtl;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ec_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ec_e-e.vhd,v 1.1 2004/04/06 10:50:49 wig Exp $
-- $Date: 2004/04/06 10:50:49 $
-- $Log: inst_ec_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:50:49 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ec_e
--
entity inst_ec_e is
-- Generics:
-- No Generated Generics for Entity inst_ec_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_ec_e
end inst_ec_e;
--
-- End of Generated Entity inst_ec_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GN6E6AAQPZ is
generic ( widthB : natural := 1;
widthA : natural := 1);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GN6E6AAQPZ is
Begin
output <= a & b;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GN6E6AAQPZ is
generic ( widthB : natural := 1;
widthA : natural := 1);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GN6E6AAQPZ is
Begin
output <= a & b;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GN6E6AAQPZ is
generic ( widthB : natural := 1;
widthA : natural := 1);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GN6E6AAQPZ is
Begin
output <= a & b;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GN6E6AAQPZ is
generic ( widthB : natural := 1;
widthA : natural := 1);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GN6E6AAQPZ is
Begin
output <= a & b;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GN6E6AAQPZ is
generic ( widthB : natural := 1;
widthA : natural := 1);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GN6E6AAQPZ is
Begin
output <= a & b;
end architecture; |
library ieee;
use ieee.std_logic_1164.all;
entity disptree is
port (
clk : in std_logic;
A : in std_logic_vector(5 downto 1);
B : out std_logic_vector(5 downto 1)
);
end disptree;
architecture rtl of disptree is
begin
gen_for : for i in 1 to 4 generate
test1: process (clk) is
begin
if (rising_edge(clk)) then
B(i) <= A(i);
end if;
end process test1;
end generate gen_for;
gen_if : if True generate
test2: process (clk) is
begin
if (rising_edge(clk)) then
B(5) <= A(5);
end if;
end process test2;
end generate gen_if;
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: clkgen_xilinx.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Author: Richard Pender, Pender Electronic Design
-- Description: Clock generators for Virtex and Virtex-2 fpgas
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.CLKDLL;
use unisim.BUFGDLL;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type
);
end;
architecture rtl of clkgen_virtex is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component CLKDLL
port (
CLK0 : out std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
LOCKED : out std_ulogic;
CLKFB : in std_ulogic;
CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
signal gnd, clk_i, clk_j, clk_k, dll0rst, dll0lock, dll1lock : std_logic;
signal dll1rst : std_logic_vector(0 to 3);
signal clk0B, clkint, CLK2XL, CLKDV, CLK180, pciclkint : std_logic;
begin
gnd <= '0'; clk <= clk_i; clkn <= not clk_i;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
dll0rst <= not cgi.pllrst;
dll0 : CLKDLL
port map (CLKIN => clkint, CLKFB => clk_k, CLK0 => clk_j, CLK180 => CLK180,
CLK2X => CLK2XL, CLKDV => CLKDV, LOCKED => dll0lock, RST => dll0rst);
clk0B <= CLK2XL when clk_mul/clk_div = 2
else CLKDV when clk_div/clk_mul = 2 else clk_j;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB = 0) generate
cgo.clklock <= dll1lock;
dll1 : CLKDLL
port map (CLKIN => clk_i, CLKFB => cgi.pllref, RST => dll1rst(0), CLK0 => sdclk,
CLK2X => clk2x, LOCKED => dll1lock);
rstdel : process (clk_i)
begin
if dll0lock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_i) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if not ((SDRAMEN /= 0) and (NOCLKFB = 0)) generate
sdclk <= clk_i; cgo.clklock <= dll0lock;
end generate;
cgo.pcilock <= '1';
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.IBUFG;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex2 clock generator ---------------------------------------
------------------------------------------------------------------
entity clkgen_virtex2 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_virtex2 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component IBUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
--constant CLKIN_PERIOD_ST : string := "20.0";
--attribute CLKIN_PERIOD : string;
--attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r, dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint, pciclkl, pciclkfb, pciclk0 : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= clk_m; clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
p2 : if (PCIDLL /= 0) and ( PCIDLL /= 1) generate
x1 : IBUFG port map (I => pciclkint, O => pciclkl);
dll0 : DCM
generic map (CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => PCIDLL)
port map ( CLKIN => pciclkint, CLKFB => pciclkfb,
DSSEN => gnd, PSCLK => gnd,
RST => gnd, PSEN => gnd, PSINCDEC => gnd, CLK0 => pciclk0);
x2 : BUFG port map (I => pciclk0, O => pciclkfb);
pciclk <= pciclkfb;
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_k;
clk2xu <= clk_x;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
bufg2 : BUFG port map (I => clk_l, O => clk_m);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
bufg3 : BUFG port map (I => clk_x, O => clk_i2);
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => sdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex2" & ": virtex-2 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex2" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkmul_virtex2 is
generic ( clk_mul : integer := 2 ; clk_div : integer := 2);
port (
resetin : in std_logic;
clkin : in std_logic;
clk : out std_logic;
resetout: out std_logic
);
end;
architecture struct of clkmul_virtex2 is
-- attribute CLKFX_MULTIPLY : string;
-- attribute CLKFX_DIVIDE : string;
-- attribute CLKIN_PERIOD : string;
--
-- attribute CLKFX_MULTIPLY of dll0: label is "5";
-- attribute CLKFX_DIVIDE of dll0: label is "4";
-- attribute CLKIN_PERIOD of dll0: label is "20";
--
-- attribute CLKFX_MULTIPLY of dll1: label is "4";
-- attribute CLKFX_DIVIDE of dll1: label is "4";
-- attribute CLKIN_PERIOD of dll1: label is "25";
--
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal gnd, clk_i, clk_j, clk_k, clk_l : std_logic;
signal clk0B, clk_FB, dll0rst, lock : std_logic;
begin
gnd <= '0'; clk <= clk_i;
dll0rst <= not resetin;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkin, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
LOCKED => resetout, CLKFX => clk0B );
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_spartan3 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 50000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_spartan3 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
--constant CLKIN_PERIOD_ST : string := "20.0";
--attribute CLKIN_PERIOD : string;
--attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r, dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= not clk_i when (CLK2XEN = 0) else not clk_p;
clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_j;
clk2xu <= clk_k;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_x, O => clk_k);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLK_FEEDBACK => "2X")
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
clk_i2 <= clk_k;
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => sdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_spartan3e" & ": spartan3/e sdram/pci clock generator, version " & tost(VERSION),
"clkgen_spartan3e" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2244.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02244ent IS
END c07s02b06x00p01n01i02244ent;
ARCHITECTURE c07s02b06x00p01n01i02244arch OF c07s02b06x00p01n01i02244ent IS
BEGIN
TESTING: PROCESS
variable BITSTRV : BIT_VECTOR( 0 to 31 );
variable k : integer;
BEGIN
k := BITSTRV rem X"7777";
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02244 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02244arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2244.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02244ent IS
END c07s02b06x00p01n01i02244ent;
ARCHITECTURE c07s02b06x00p01n01i02244arch OF c07s02b06x00p01n01i02244ent IS
BEGIN
TESTING: PROCESS
variable BITSTRV : BIT_VECTOR( 0 to 31 );
variable k : integer;
BEGIN
k := BITSTRV rem X"7777";
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02244 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02244arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2244.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02244ent IS
END c07s02b06x00p01n01i02244ent;
ARCHITECTURE c07s02b06x00p01n01i02244arch OF c07s02b06x00p01n01i02244ent IS
BEGIN
TESTING: PROCESS
variable BITSTRV : BIT_VECTOR( 0 to 31 );
variable k : integer;
BEGIN
k := BITSTRV rem X"7777";
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02244 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02244arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shooting_sound is
generic(
ADDR_WIDTH: integer := 5
);
port(
addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0);
data: out std_logic_vector(8 downto 0)
);
end shooting_sound;
architecture content of shooting_sound is
type tune is array(0 to 2 ** ADDR_WIDTH - 1)
of std_logic_vector(8 downto 0);
constant TEST: tune :=
(
"100001001",
"011001011",
"001001010",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000"
);
begin
data <= TEST(conv_integer(addr));
end content;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shooting_sound is
generic(
ADDR_WIDTH: integer := 5
);
port(
addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0);
data: out std_logic_vector(8 downto 0)
);
end shooting_sound;
architecture content of shooting_sound is
type tune is array(0 to 2 ** ADDR_WIDTH - 1)
of std_logic_vector(8 downto 0);
constant TEST: tune :=
(
"100001001",
"011001011",
"001001010",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000"
);
begin
data <= TEST(conv_integer(addr));
end content;
|
-----------------------------------------------------------------------------
-- Module for transmitting data from the 50MHz byte-format to the 25MHz
-- PHY nibble-format. Adds preamble, SFD and CRC.
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.crc.all;
entity txsync is
Port ( sysclk : in STD_LOGIC;
reset : in STD_LOGIC;
tx_clk : in STD_LOGIC;
txd : out STD_LOGIC_VECTOR (3 downto 0);
tx_dv : out STD_LOGIC;
data : in STD_LOGIC_VECTOR (7 downto 0);
data_send : in STD_LOGIC;
data_req : out STD_LOGIC;
debug:out std_logic_vector(7 downto 0)
);
end txsync;
architecture RTL of txsync is
signal byte_latch:std_logic_vector(7 downto 0):=(OTHERS => '0');
signal req:std_logic:='0';
signal req_ccd:std_logic_vector(2 downto 0):=(OTHERS => '0');
type state_t is (Idle, IdleWait, Preamble, SFD, Data0, Data1, stCRC);
signal state, nextstate:state_t:=Idle;
signal count:integer range 0 to 14:=0;
signal rst:std_logic;
signal tx_dv_d:std_logic;
signal crcnibble, txd_d:std_logic_vector(3 downto 0);
signal crc, nextcrc:std_logic_vector(31 downto 0);
begin
rst <= reset;
data_req <= '1' when req_ccd(2) /= req_ccd(1) else '0';
req_synchronizer:process(sysclk) is
begin
if rising_edge(sysclk) then
if rst = '1' then
req_ccd <= (OTHERS => '0');
else
req_ccd(0) <= req;
req_ccd(1) <= req_ccd(0);
req_ccd(2) <= req_ccd(1);
end if;
end if;
end process;
crcnibble(0) <= crc(31);
crcnibble(1) <= crc(30);
crcnibble(2) <= crc(29);
crcnibble(3) <= crc(28);
txd_d <= x"5" when state = Preamble
else x"d" when state = SFD
else byte_latch(3 downto 0) when state = Data0
else byte_latch(7 downto 4) when state = Data1
else not crcnibble when state = stCRC
else "0000";
tx_dv_d <= '1' when state /= Idle and state /= IdleWait else '0';
txreg:process(tx_clk) begin
if rising_edge(tx_clk) then
if rst = '1' then
txd <= "0000";
tx_dv <= '0';
else
txd <= txd_d;
tx_dv <= tx_dv_d;
end if;
end if;
end process;
nextcrc <= Crc32_4(txd_d, crc, '1') when state = Data0 or state = Data1
else Crc32_4("0000", crc, '0') when state = stCRC
else (OTHERS => '1');
nextstate <= IdleWait when (state = Idle and data_send = '0')
else Preamble when (state = Idle or (state=Preamble and count /= 0))
else SFD when state = Preamble
else Data0 when (state = SFD or (state = Data1 and data_send = '1'))
else Data1 when state = Data0
else stCRC when (state = Data1 or (state=stCRC and count /= 0))
else Idle;
process(tx_clk) begin
if rising_edge(tx_clk) then
if rst = '1' then
crc <= (OTHERS => '1');
state <= Idle;
byte_latch <= x"00";
req <= '0';
else
crc <= nextcrc;
state <= nextstate;
if state = Idle then
count <= 14;
elsif state = Data1 or state = Data0 then
count <= 7;
elsif count /= 0 then
count <= count - 1;
end if;
if state = IdleWait or state = Data1 then
byte_latch <= data;
req <= not req;
end if;
end if;
end if;
end process;
end RTL; |
-------------------------------------------------------------------------------
-- package for lfsr next state determination
-- the determination use the maximum feedback taps
-- the sequence will cycle through all values from 0 to 2^n-1
-- the lfsr should start with state (others => '0')
-- and the state (others => '1') is not allowed,
-- because the lfsr will stuck in this state
-- implementation:
-- must be implementet with n downto 1 because a lfsr has no zero tap
-- lfsr_state : std_ulogic_vector(n downto 1);
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package lfsr is
-- determinate next lfsr state
function lfsr_nx_state (
constant lfsr_state : std_ulogic_vector)
return std_ulogic_vector;
end package lfsr;
package body lfsr is
function lfsr_nx_state (
constant lfsr_state : std_ulogic_vector)
return std_ulogic_vector is
-- feedback taps
-- table from xilinx app note 052
constant lfsr_fb_table_len_c : natural := 168;
type lfsr_fb_table_t is array (
3 to lfsr_fb_table_len_c,
1 to lfsr_fb_table_len_c) of boolean;
constant lfsr_fb_table_c : lfsr_fb_table_t := (
(3 | 2 => true, others => false),
(4 | 3 => true, others => false),
(5 | 3 => true, others => false),
(6 | 5 => true, others => false),
(7 | 6 => true, others => false),
(8 | 6 | 5 | 4 => true, others => false),
(9 | 5 => true, others => false),
(10 | 7 => true, others => false),
(11 | 9 => true, others => false),
(12 | 6 | 4 | 1 => true, others => false),
(13 | 4 | 3 | 1 => true, others => false),
(14 | 5 | 3 | 1 => true, others => false),
(15 | 14 => true, others => false),
(16 | 15 | 13 | 4 => true, others => false),
(17 | 14 => true, others => false),
(18 | 11 => true, others => false),
(19 | 6 | 2 | 1 => true, others => false),
(20 | 17 => true, others => false),
(21 | 19 => true, others => false),
(22 | 21 => true, others => false),
(23 | 18 => true, others => false),
(24 | 23 | 22 | 17 => true, others => false),
(25 | 22 => true, others => false),
(26 | 6 | 2 | 1 => true, others => false),
(27 | 5 | 2 | 1 => true, others => false),
(28 | 25 => true, others => false),
(29 | 27 => true, others => false),
(30 | 6 | 4 | 1 => true, others => false),
(31 | 28 => true, others => false),
(32 | 22 | 2 | 1 => true, others => false),
(33 | 20 => true, others => false),
(34 | 27 | 2 | 1 => true, others => false),
(35 | 33 => true, others => false),
(36 | 25 => true, others => false),
(37 | 5 | 4 | 3 | 2 | 1 => true, others => false),
(38 | 6 | 5 | 1 => true, others => false),
(39 | 35 => true, others => false),
(40 | 38 | 21 | 19 => true, others => false),
(41 | 38 => true, others => false),
(42 | 41 | 20 | 19 => true, others => false),
(43 | 42 | 38 | 37 => true, others => false),
(44 | 43 | 18 | 17 => true, others => false),
(45 | 44 | 42 | 41 => true, others => false),
(46 | 45 | 26 | 25 => true, others => false),
(47 | 42 => true, others => false),
(48 | 47 | 21 | 20 => true, others => false),
(49 | 40 => true, others => false),
(50 | 49 | 24 | 23 => true, others => false),
(51 | 50 | 36 | 35 => true, others => false),
(52 | 49 => true, others => false),
(53 | 52 | 38 | 37 => true, others => false),
(54 | 53 | 18 | 17 => true, others => false),
(55 | 31 => true, others => false),
(56 | 55 | 35 | 34 => true, others => false),
(57 | 50 => true, others => false),
(58 | 39 => true, others => false),
(59 | 58 | 38 | 37 => true, others => false),
(60 | 59 => true, others => false),
(61 | 60 | 46 | 45 => true, others => false),
(62 | 61 | 6 | 5 => true, others => false),
(63 | 62 => true, others => false),
(64 | 63 | 61 | 60 => true, others => false),
(65 | 47 => true, others => false),
(66 | 65 | 57 | 56 => true, others => false),
(67 | 66 | 58 | 57 => true, others => false),
(68 | 59 => true, others => false),
(69 | 67 | 42 | 40 => true, others => false),
(70 | 69 | 55 | 54 => true, others => false),
(71 | 65 => true, others => false),
(72 | 66 | 25 | 19 => true, others => false),
(73 | 48 => true, others => false),
(74 | 73 | 59 | 58 => true, others => false),
(75 | 74 | 65 | 64 => true, others => false),
(76 | 75 | 41 | 40 => true, others => false),
(77 | 76 | 47 | 46 => true, others => false),
(78 | 77 | 59 | 58 => true, others => false),
(79 | 70 => true, others => false),
(80 | 79 | 43 | 42 => true, others => false),
(81 | 77 => true, others => false),
(82 | 79 | 47 | 44 => true, others => false),
(83 | 82 | 38 | 37 => true, others => false),
(84 | 71 => true, others => false),
(85 | 84 | 58 | 57 => true, others => false),
(86 | 85 | 74 | 73 => true, others => false),
(87 | 74 => true, others => false),
(88 | 87 | 17 | 16 => true, others => false),
(89 | 51 => true, others => false),
(90 | 89 | 72 | 71 => true, others => false),
(91 | 90 | 8 | 7 => true, others => false),
(92 | 91 | 80 | 79 => true, others => false),
(93 | 91 => true, others => false),
(94 | 73 => true, others => false),
(95 | 84 => true, others => false),
(96 | 94 | 49 | 47 => true, others => false),
(97 | 91 => true, others => false),
(98 | 87 => true, others => false),
(99 | 97 | 54 | 52 => true, others => false),
(100 | 63 => true, others => false),
(101 | 100 | 95 | 94 => true, others => false),
(102 | 101 | 36 | 35 => true, others => false),
(103 | 94 => true, others => false),
(104 | 103 | 94 | 93 => true, others => false),
(105 | 89 => true, others => false),
(106 | 91 => true, others => false),
(107 | 105 | 44 | 42 => true, others => false),
(108 | 77 => true, others => false),
(109 | 108 | 103 | 102 => true, others => false),
(110 | 109 | 98 | 97 => true, others => false),
(111 | 101 => true, others => false),
(112 | 110 | 69 | 67 => true, others => false),
(113 | 104 => true, others => false),
(114 | 113 | 33 | 32 => true, others => false),
(115 | 114 | 101 | 100 => true, others => false),
(116 | 115 | 46 | 45 => true, others => false),
(117 | 115 | 99 | 97 => true, others => false),
(118 | 85 => true, others => false),
(119 | 111 => true, others => false),
(120 | 113 | 9 | 2 => true, others => false),
(121 | 103 => true, others => false),
(122 | 131 | 63 | 62 => true, others => false),
(123 | 121 => true, others => false),
(124 | 87 => true, others => false),
(125 | 124 | 18 | 17 => true, others => false),
(126 | 125 | 90 | 89 => true, others => false),
(127 | 126 => true, others => false),
(128 | 126 | 101 | 99 => true, others => false),
(129 | 124 => true, others => false),
(130 | 127 => true, others => false),
(131 | 130 | 84 | 83 => true, others => false),
(132 | 103 => true, others => false),
(133 | 132 | 82 | 81 => true, others => false),
(134 | 77 => true, others => false),
(135 | 124 => true, others => false),
(136 | 125 | 11 | 10 => true, others => false),
(137 | 116 => true, others => false),
(138 | 137 | 131 | 130 => true, others => false),
(139 | 136 | 134 | 131 => true, others => false),
(140 | 111 => true, others => false),
(141 | 140 | 110 | 109 => true, others => false),
(142 | 121 => true, others => false),
(143 | 142 | 123 | 122 => true, others => false),
(144 | 143 | 75 | 74 => true, others => false),
(145 | 93 => true, others => false),
(146 | 145 | 87 | 86 => true, others => false),
(147 | 146 | 110 | 109 => true, others => false),
(148 | 121 => true, others => false),
(149 | 148 | 40 | 39 => true, others => false),
(150 | 97 => true, others => false),
(151 | 148 => true, others => false),
(152 | 151 | 87 | 86 => true, others => false),
(153 | 152 => true, others => false),
(154 | 152 | 27 | 25 => true, others => false),
(155 | 154 | 124 | 123 => true, others => false),
(156 | 155 | 41 | 40 => true, others => false),
(157 | 156 | 131 | 130 => true, others => false),
(158 | 157 | 132 | 131 => true, others => false),
(159 | 128 => true, others => false),
(160 | 159 | 142 | 141 => true, others => false),
(161 | 143 => true, others => false),
(162 | 161 | 75 | 74 => true, others => false),
(163 | 162 | 161 | 104 | 103 => true, others => false),
(164 | 163 | 151 | 150 => true, others => false),
(165 | 164 | 135 | 134 => true, others => false),
(166 | 165 | 128 | 127 => true, others => false),
(167 | 161 => true, others => false),
(168 | 166 | 153 | 151 => true, others => false));
constant xnor_neutral_elem_c : std_ulogic := '1';
variable fb_v : std_ulogic := xnor_neutral_elem_c;
begin
assert (lfsr_state'right = 1)
report "LFSR needs to be indexed like n downto 1"
severity failure;
assert (lfsr_state'left <= lfsr_fb_table_len_c)
report "Maximum LFSR length is 168!"
severity failure;
assert (lfsr_state'left >= 3)
report "Minimum LFSR length is 3!"
severity failure;
-- Since the xnor function is commutative and associative
for idx in lfsr_state'range loop
if lfsr_fb_table_c(lfsr_state'length, idx) then
fb_v := fb_v xnor lfsr_state(idx);
end if;
end loop;
-- Shift the computed bit into the LFSR. This is the next state of the LFSR
return lfsr_state(lfsr_state'length-1 downto 1) & fb_v;
end function lfsr_nx_state;
end package body lfsr;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity graphics_engine is
end entity graphics_engine;
-- end not in book
architecture behavioral of graphics_engine is
type point is array (1 to 3) of real;
type transformation_matrix is array (1 to 3, 1 to 3) of real;
signal p, transformed_p : point;
signal a : transformation_matrix;
signal clock : bit;
-- . . .
begin
transform_stage : for i in 1 to 3 generate
begin
cross_product_transform : process is
variable result1, result2, result3 : real := 0.0;
begin
wait until clock = '1';
transformed_p(i) <= result3;
result3 := result2;
result2 := result1;
result1 := a(i, 1) * p(1) + a(i, 2) * p(2) + a(i, 3) * p(3);
end process cross_product_transform;
end generate transform_stage;
-- . . . -- other stages in the pipeline, etc
-- not in book
clock_gen : clock <= '1' after 10 ns, '0' after 20 ns when clock = '0';
stimulus : process is
begin
a <= ( (1.0, 0.0, 0.0), (0.0, 1.0, 0.0), (0.0, 0.0, 1.0) );
p <= ( 10.0, 10.0, 10.0 );
wait until clock = '0';
p <= ( 20.0, 20.0, 20.0 );
wait until clock = '0';
p <= ( 30.0, 30.0, 30.0 );
wait until clock = '0';
p <= ( 40.0, 40.0, 40.0 );
wait until clock = '0';
p <= ( 50.0, 50.0, 50.0 );
wait until clock = '0';
p <= ( 60.0, 60.0, 60.0 );
wait;
end process stimulus;
-- end not in book
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity graphics_engine is
end entity graphics_engine;
-- end not in book
architecture behavioral of graphics_engine is
type point is array (1 to 3) of real;
type transformation_matrix is array (1 to 3, 1 to 3) of real;
signal p, transformed_p : point;
signal a : transformation_matrix;
signal clock : bit;
-- . . .
begin
transform_stage : for i in 1 to 3 generate
begin
cross_product_transform : process is
variable result1, result2, result3 : real := 0.0;
begin
wait until clock = '1';
transformed_p(i) <= result3;
result3 := result2;
result2 := result1;
result1 := a(i, 1) * p(1) + a(i, 2) * p(2) + a(i, 3) * p(3);
end process cross_product_transform;
end generate transform_stage;
-- . . . -- other stages in the pipeline, etc
-- not in book
clock_gen : clock <= '1' after 10 ns, '0' after 20 ns when clock = '0';
stimulus : process is
begin
a <= ( (1.0, 0.0, 0.0), (0.0, 1.0, 0.0), (0.0, 0.0, 1.0) );
p <= ( 10.0, 10.0, 10.0 );
wait until clock = '0';
p <= ( 20.0, 20.0, 20.0 );
wait until clock = '0';
p <= ( 30.0, 30.0, 30.0 );
wait until clock = '0';
p <= ( 40.0, 40.0, 40.0 );
wait until clock = '0';
p <= ( 50.0, 50.0, 50.0 );
wait until clock = '0';
p <= ( 60.0, 60.0, 60.0 );
wait;
end process stimulus;
-- end not in book
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity graphics_engine is
end entity graphics_engine;
-- end not in book
architecture behavioral of graphics_engine is
type point is array (1 to 3) of real;
type transformation_matrix is array (1 to 3, 1 to 3) of real;
signal p, transformed_p : point;
signal a : transformation_matrix;
signal clock : bit;
-- . . .
begin
transform_stage : for i in 1 to 3 generate
begin
cross_product_transform : process is
variable result1, result2, result3 : real := 0.0;
begin
wait until clock = '1';
transformed_p(i) <= result3;
result3 := result2;
result2 := result1;
result1 := a(i, 1) * p(1) + a(i, 2) * p(2) + a(i, 3) * p(3);
end process cross_product_transform;
end generate transform_stage;
-- . . . -- other stages in the pipeline, etc
-- not in book
clock_gen : clock <= '1' after 10 ns, '0' after 20 ns when clock = '0';
stimulus : process is
begin
a <= ( (1.0, 0.0, 0.0), (0.0, 1.0, 0.0), (0.0, 0.0, 1.0) );
p <= ( 10.0, 10.0, 10.0 );
wait until clock = '0';
p <= ( 20.0, 20.0, 20.0 );
wait until clock = '0';
p <= ( 30.0, 30.0, 30.0 );
wait until clock = '0';
p <= ( 40.0, 40.0, 40.0 );
wait until clock = '0';
p <= ( 50.0, 50.0, 50.0 );
wait until clock = '0';
p <= ( 60.0, 60.0, 60.0 );
wait;
end process stimulus;
-- end not in book
end architecture behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2321.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02321ent IS
END c07s02b07x00p01n01i02321ent;
ARCHITECTURE c07s02b07x00p01n01i02321arch OF c07s02b07x00p01n01i02321ent IS
BEGIN
TESTING: PROCESS
type MEMORY is array(INTEGER range <>) of BIT;
type ADDRESS is access MEMORY;
variable ADDRESSV : ADDRESS;
BEGIN
ADDRESSV := ABS ADDRESSV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p01n01i02321 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02321arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2321.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02321ent IS
END c07s02b07x00p01n01i02321ent;
ARCHITECTURE c07s02b07x00p01n01i02321arch OF c07s02b07x00p01n01i02321ent IS
BEGIN
TESTING: PROCESS
type MEMORY is array(INTEGER range <>) of BIT;
type ADDRESS is access MEMORY;
variable ADDRESSV : ADDRESS;
BEGIN
ADDRESSV := ABS ADDRESSV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p01n01i02321 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02321arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2321.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02321ent IS
END c07s02b07x00p01n01i02321ent;
ARCHITECTURE c07s02b07x00p01n01i02321arch OF c07s02b07x00p01n01i02321ent IS
BEGIN
TESTING: PROCESS
type MEMORY is array(INTEGER range <>) of BIT;
type ADDRESS is access MEMORY;
variable ADDRESSV : ADDRESS;
BEGIN
ADDRESSV := ABS ADDRESSV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p01n01i02321 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02321arch;
|
-- Codeslot
--
-- gemaakt door
--
-- __ ___ _
-- / |/ /___ ___ _______(_)_______
-- / /|_/ / __ `/ / / / ___/ / ___/ _ \
-- / / / / /_/ / /_/ / / / / /__/ __/
-- /_/ /_/\__,_/\__,_/_/ /_/\___/\___/
-- ____ __ ____
-- / __ \____ __ _____ ______ _____ / /___/ / /_
-- / / / / __ `/ | / / _ \/ ___/ | / / _ \/ / __ / __/
-- / /_/ / /_/ /| |/ / __/ / | |/ / __/ / /_/ / /_
-- /_____/\__,_/ |___/\___/_/ |___/\___/_/\__,_/\__/
--
-- Maurice Daverveldt
-- Ev3a
-- 1531491
--
-- gebruikte wachtwoord binair:
-- 0001010010010001
-- dit bestand bevat de testbench die het hele codeslot test
library ieee;
use ieee.std_logic_1164.all;
entity codeslot_tb is
end codeslot_tb;
architecture DUT of codeslot_tb is
component codeslot is
port( DIP : in std_logic_vector(3 downto 0);
druk : in std_logic;
clk : in std_logic;
disp_seg : out std_logic_vector(7 downto 0);
disp_sel : out std_logic_vector(3 downto 0);
LED : out std_logic);
end component;
signal DIP : std_logic_vector(3 downto 0);
signal druk : std_logic;
signal clk : std_logic;
signal disp_seg : std_logic_vector(7 downto 0);
signal disp_sel : std_logic_vector(3 downto 0);
signal LED : std_logic;
signal ok : std_logic;
constant tijd : TIME := 20 ns;
begin
DUT : entity work.codeslot port map(
DIP => DIP,
druk => druk,
clk => clk,
disp_seg => disp_seg,
disp_sel => disp_sel,
led => led
);
clock : process
begin
for i in 0 to 300 loop
clk <= '0'; wait for 1 ns;
clk <= '1'; wait for 1 ns;
end loop;
wait;
end process;
tb : process
begin
ok <= '1';
DIP <= "0000"; -- code slot staat op start stand
druk <= '0';
wait for 2 ns;
druk <= '1'; -- ga naar stand 1
wait for tijd;
druk <= '0';
wait for tijd;
DIP <= "0001"; -- zet eerste waarde op DIP
wait for tijd;
druk <= '1'; -- maak druk hoog
wait for tijd;
druk <= '0'; -- maak druk laag
wait for tijd;
DIP <= "0100"; -- zet tweede waarde op DIP
wait for tijd;
druk <= '1'; -- druk op knop
wait for tijd;
druk <= '0';
wait for tijd;
DIP <= "1001"; -- zet derde waarde op DIP
wait for tijd;
druk <= '1';
wait for tijd;
druk <= '0';
wait for tijd;
DIP <= "0001"; -- zet vierde waarde op DIP
wait for tijd;
druk <= '1'; -- ga naar laatste stand
wait for tijd;
druk <= '0';
if led /= '1' then
ok <= '0';
end if;
wait for tijd;
druk <= '1'; -- ga naar eerste stand
wait for tijd;
druk <= '0';
wait for tijd;
DIP <= "0001"; -- zet eerste waarde op DIP
wait for tijd;
druk <= '1'; -- maak druk hoog
wait for tijd;
druk <= '0';
wait for tijd;
DIP <= "0100"; -- zet tweede waarde op DIP
wait for tijd;
druk <= '1';
wait for tijd;
druk <= '0';
wait for tijd;
DIP <= "1001"; -- zet derde waarde op DIP
wait for tijd;
druk <= '1';
wait for tijd;
druk <= '0';
wait for tijd;
DIP <= "0101"; -- zet vierde (foute) waarde op DIP
wait for tijd;
druk <= '1';
wait for tijd;
druk <= '0';
wait for tijd;
druk <= '1';
wait for tijd;
druk <= '0';
wait for tijd;
if led /= '0' then -- check of led laag is
ok <= '0';
end if;
wait;
end process;
end DUT; |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Sat Sep 23 13:25:27 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_0/zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO is
port (
bvalid_cnt_inc : out STD_LOGIC;
bid_gets_fifo_load_d1_reg : out STD_LOGIC;
bid_gets_fifo_load : out STD_LOGIC;
axi_wdata_full_cmb114_out : out STD_LOGIC;
\axi_bid_int_reg[0]\ : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\bvalid_cnt_reg[2]\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
\bvalid_cnt_reg[2]_0\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
bram_addr_ld_en : in STD_LOGIC;
bid_gets_fifo_load_d1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
axi_bvalid_int_reg : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
\bvalid_cnt_reg[1]\ : in STD_LOGIC;
aw_active : in STD_LOGIC;
s_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
axi_awid_pipe : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
axi_wr_burst : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO : entity is "SRL_FIFO";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO is
signal \Addr_Counters[0].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[1].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[2].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].XORCY_I_i_1_n_0\ : STD_LOGIC;
signal CI : STD_LOGIC;
signal D : STD_LOGIC;
signal Data_Exists_DFF_i_2_n_0 : STD_LOGIC;
signal Data_Exists_DFF_i_3_n_0 : STD_LOGIC;
signal S : STD_LOGIC;
signal S0_out : STD_LOGIC;
signal S1_out : STD_LOGIC;
signal addr_cy_1 : STD_LOGIC;
signal addr_cy_2 : STD_LOGIC;
signal addr_cy_3 : STD_LOGIC;
signal \axi_bid_int[0]_i_2_n_0\ : STD_LOGIC;
signal axi_bvalid_int_i_4_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_5_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_6_n_0 : STD_LOGIC;
signal \^axi_wdata_full_cmb114_out\ : STD_LOGIC;
signal bid_fifo_ld : STD_LOGIC;
signal bid_fifo_not_empty : STD_LOGIC;
signal bid_fifo_rd : STD_LOGIC;
signal \^bid_gets_fifo_load\ : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_3_n_0 : STD_LOGIC;
signal \^bid_gets_fifo_load_d1_reg\ : STD_LOGIC;
signal \^bvalid_cnt_inc\ : STD_LOGIC;
signal sum_A_0 : STD_LOGIC;
signal sum_A_1 : STD_LOGIC;
signal sum_A_2 : STD_LOGIC;
signal sum_A_3 : STD_LOGIC;
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O";
attribute BOX_TYPE of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of Data_Exists_DFF : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
attribute BOX_TYPE of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name : string;
attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of axi_bvalid_int_i_3 : label is "soft_lutpair44";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_3 : label is "soft_lutpair44";
begin
axi_wdata_full_cmb114_out <= \^axi_wdata_full_cmb114_out\;
bid_gets_fifo_load <= \^bid_gets_fifo_load\;
bid_gets_fifo_load_d1_reg <= \^bid_gets_fifo_load_d1_reg\;
bvalid_cnt_inc <= \^bvalid_cnt_inc\;
\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_3,
Q => \Addr_Counters[0].FDRE_I_n_0\,
R => s_axi_aresetn
);
\Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3),
CO(2) => addr_cy_1,
CO(1) => addr_cy_2,
CO(0) => addr_cy_3,
CYINIT => CI,
DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3),
DI(2) => \Addr_Counters[2].FDRE_I_n_0\,
DI(1) => \Addr_Counters[1].FDRE_I_n_0\,
DI(0) => \Addr_Counters[0].FDRE_I_n_0\,
O(3) => sum_A_0,
O(2) => sum_A_1,
O(1) => sum_A_2,
O(0) => sum_A_3,
S(3) => \Addr_Counters[3].XORCY_I_i_1_n_0\,
S(2) => S0_out,
S(1) => S1_out,
S(0) => S
);
\Addr_Counters[0].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[1].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[0]_i_2_n_0\,
I5 => \Addr_Counters[0].FDRE_I_n_0\,
O => S
);
\Addr_Counters[0].MUXCY_L_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAAAAAAAAAAAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => \axi_bid_int[0]_i_2_n_0\,
I2 => \Addr_Counters[0].FDRE_I_n_0\,
I3 => \Addr_Counters[1].FDRE_I_n_0\,
I4 => \Addr_Counters[3].FDRE_I_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => CI
);
\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_2,
Q => \Addr_Counters[1].FDRE_I_n_0\,
R => s_axi_aresetn
);
\Addr_Counters[1].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[0]_i_2_n_0\,
I5 => \Addr_Counters[1].FDRE_I_n_0\,
O => S1_out
);
\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_1,
Q => \Addr_Counters[2].FDRE_I_n_0\,
R => s_axi_aresetn
);
\Addr_Counters[2].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[0]_i_2_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => S0_out
);
\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_0,
Q => \Addr_Counters[3].FDRE_I_n_0\,
R => s_axi_aresetn
);
\Addr_Counters[3].XORCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[0]_i_2_n_0\,
I5 => \Addr_Counters[3].FDRE_I_n_0\,
O => \Addr_Counters[3].XORCY_I_i_1_n_0\
);
Data_Exists_DFF: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D,
Q => bid_fifo_not_empty,
R => s_axi_aresetn
);
Data_Exists_DFF_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE0A"
)
port map (
I0 => bram_addr_ld_en,
I1 => Data_Exists_DFF_i_2_n_0,
I2 => Data_Exists_DFF_i_3_n_0,
I3 => bid_fifo_not_empty,
O => D
);
Data_Exists_DFF_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFFD"
)
port map (
I0 => \^bvalid_cnt_inc\,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
I3 => bvalid_cnt(1),
I4 => \^bid_gets_fifo_load_d1_reg\,
I5 => bid_gets_fifo_load_d1,
O => Data_Exists_DFF_i_2_n_0
);
Data_Exists_DFF_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => \Addr_Counters[2].FDRE_I_n_0\,
O => Data_Exists_DFF_i_3_n_0
);
\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld,
Q => bid_fifo_rd
);
\FIFO_RAM[0].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_awid_pipe,
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
O => bid_fifo_ld
);
\axi_bid_int[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ACAFACA0"
)
port map (
I0 => bid_fifo_ld,
I1 => bid_fifo_rd,
I2 => \^bid_gets_fifo_load\,
I3 => \axi_bid_int[0]_i_2_n_0\,
I4 => s_axi_bid(0),
O => \axi_bid_int_reg[0]\
);
\axi_bid_int[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888AAAAA8888888"
)
port map (
I0 => bid_fifo_not_empty,
I1 => bid_gets_fifo_load_d1,
I2 => s_axi_bready,
I3 => axi_bvalid_int_reg,
I4 => bid_gets_fifo_load_d1_i_3_n_0,
I5 => \^bvalid_cnt_inc\,
O => \axi_bid_int[0]_i_2_n_0\
);
axi_bvalid_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000055FD00000000"
)
port map (
I0 => \out\(2),
I1 => \^axi_wdata_full_cmb114_out\,
I2 => axi_bvalid_int_i_4_n_0,
I3 => axi_wr_burst,
I4 => \out\(1),
I5 => axi_bvalid_int_i_5_n_0,
O => \^bvalid_cnt_inc\
);
axi_bvalid_int_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FE000000"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => axi_bvalid_int_reg,
I4 => s_axi_bready,
O => \^bid_gets_fifo_load_d1_reg\
);
axi_bvalid_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"1F11000000000000"
)
port map (
I0 => axi_bvalid_int_i_6_n_0,
I1 => \bvalid_cnt_reg[2]\,
I2 => wr_addr_sm_cs,
I3 => \bvalid_cnt_reg[2]_0\,
I4 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I5 => axi_awaddr_full,
O => axi_bvalid_int_i_4_n_0
);
axi_bvalid_int_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"74446444"
)
port map (
I0 => \out\(0),
I1 => \out\(2),
I2 => s_axi_wvalid,
I3 => s_axi_wlast,
I4 => \^axi_wdata_full_cmb114_out\,
O => axi_bvalid_int_i_5_n_0
);
axi_bvalid_int_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFFFFF"
)
port map (
I0 => curr_awlen_reg_1_or_2,
I1 => axi_awlen_pipe_1_or_2,
I2 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I3 => axi_awaddr_full,
I4 => last_data_ack_mod,
O => axi_bvalid_int_i_6_n_0
);
axi_wready_int_mod_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F7F007F007F00"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => aw_active,
I4 => s_axi_awready,
I5 => s_axi_awvalid,
O => \^axi_wdata_full_cmb114_out\
);
bid_gets_fifo_load_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000800AA00AA00"
)
port map (
I0 => bram_addr_ld_en,
I1 => \^bid_gets_fifo_load_d1_reg\,
I2 => bid_fifo_not_empty,
I3 => \^bvalid_cnt_inc\,
I4 => \bvalid_cnt_reg[1]\,
I5 => bid_gets_fifo_load_d1_i_3_n_0,
O => \^bid_gets_fifo_load\
);
bid_gets_fifo_load_d1_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => bid_gets_fifo_load_d1_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_addr_ld_en_mod : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : out STD_LOGIC;
bram_addr_ld_en : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_1\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_2\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_0\ : out STD_LOGIC;
\wrap_burst_total_reg[2]_0\ : out STD_LOGIC;
curr_fixed_burst_reg_reg : out STD_LOGIC;
curr_wrap_burst_reg_reg : out STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
bram_addr_inc : in STD_LOGIC;
bram_addr_rst_cmb : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC;
bram_addr_a : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
aw_active : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_awsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
curr_fixed_burst : in STD_LOGIC;
curr_wrap_burst : in STD_LOGIC;
s_axi_aresetn_0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst : entity is "wrap_brst";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst is
signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[8]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal bram_addr_ld : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^bram_addr_ld_en_mod\ : STD_LOGIC;
signal save_init_bram_addr_ld : STD_LOGIC_VECTOR ( 15 downto 3 );
signal \save_init_bram_addr_ld[3]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_1\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_2\ : STD_LOGIC;
signal wrap_burst_total : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \wrap_burst_total[0]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_4__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_5_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[2]_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \curr_fixed_burst_reg_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_4__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_5\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3__0\ : label is "soft_lutpair47";
begin
D(13 downto 0) <= \^d\(13 downto 0);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[8]\;
SR(0) <= \^sr\(0);
bram_addr_ld_en <= \^bram_addr_ld_en\;
bram_addr_ld_en_mod <= \^bram_addr_ld_en_mod\;
\save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\;
\save_init_bram_addr_ld_reg[15]_1\ <= \^save_init_bram_addr_ld_reg[15]_1\;
\save_init_bram_addr_ld_reg[15]_2\ <= \^save_init_bram_addr_ld_reg[15]_2\;
\wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\;
\wrap_burst_total_reg[2]_0\ <= \^wrap_burst_total_reg[2]_0\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB8BBBBB88B88888"
)
port map (
I0 => bram_addr_ld(8),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(7),
I5 => bram_addr_a(8),
O => \^d\(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(9),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(9),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\,
I4 => bram_addr_a(8),
O => \^d\(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(12),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(10),
O => \^d\(10)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(13),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(11),
O => \^d\(11)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(14),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(12),
O => \^d\(12)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"4500FFFF"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => bram_addr_inc,
I3 => bram_addr_rst_cmb,
I4 => s_axi_aresetn,
O => \^sr\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => \^bram_addr_ld_en_mod\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(15),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(13),
O => \^d\(13)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFFDF"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => wrap_burst_total(1),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(0),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00C000"
)
port map (
I0 => bram_addr_a(2),
I1 => bram_addr_a(1),
I2 => wrap_burst_total(1),
I3 => bram_addr_a(0),
I4 => wrap_burst_total(0),
I5 => wrap_burst_total(2),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B800B800FFFF"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
I1 => axi_awaddr_full,
I2 => s_axi_awaddr(0),
I3 => \^bram_addr_ld_en\,
I4 => \^bram_addr_ld_en_mod\,
I5 => bram_addr_a(0),
O => \^d\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => bram_addr_ld(1),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(1),
I3 => bram_addr_a(0),
O => \^d\(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BB8B8B8"
)
port map (
I0 => bram_addr_ld(2),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(2),
I3 => bram_addr_a(0),
I4 => bram_addr_a(1),
O => \^d\(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8BB8B8B8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(3),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(3),
I3 => bram_addr_a(2),
I4 => bram_addr_a(0),
I5 => bram_addr_a(1),
O => \^d\(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B88B"
)
port map (
I0 => bram_addr_ld(4),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(4),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
O => \^d\(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(5),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(5),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I4 => bram_addr_a(4),
O => \^d\(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B88BB8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(6),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => bram_addr_a(4),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => bram_addr_a(5),
O => \^d\(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => bram_addr_a(1),
I1 => bram_addr_a(0),
I2 => bram_addr_a(2),
I3 => bram_addr_a(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(7),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(6),
O => \^d\(7)
);
\curr_fixed_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_fixed_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_fixed_burst,
I3 => \^sr\(0),
O => curr_fixed_burst_reg_reg
);
\curr_wrap_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_wrap_burst,
I3 => \^sr\(0),
O => curr_wrap_burst_reg_reg
);
\save_init_bram_addr_ld[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(10),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(8),
O => bram_addr_ld(8)
);
\save_init_bram_addr_ld[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(11),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(9),
O => bram_addr_ld(9)
);
\save_init_bram_addr_ld[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808080808AA0808"
)
port map (
I0 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I1 => \^save_init_bram_addr_ld_reg[15]_0\,
I2 => wr_addr_sm_cs,
I3 => \^save_init_bram_addr_ld_reg[15]_1\,
I4 => last_data_ack_mod,
I5 => \^save_init_bram_addr_ld_reg[15]_2\,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"007F007F007F0000"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
I3 => aw_active,
I4 => axi_awaddr_full,
I5 => s_axi_awvalid,
O => \^save_init_bram_addr_ld_reg[15]_0\
);
\save_init_bram_addr_ld[15]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => \^save_init_bram_addr_ld_reg[15]_1\
);
\save_init_bram_addr_ld[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I2 => axi_awlen_pipe_1_or_2,
I3 => curr_awlen_reg_1_or_2,
O => \^save_init_bram_addr_ld_reg[15]_2\
);
\save_init_bram_addr_ld[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(1),
O => bram_addr_ld(1)
);
\save_init_bram_addr_ld[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"C80C"
)
port map (
I0 => wrap_burst_total(0),
I1 => save_init_bram_addr_ld(3),
I2 => wrap_burst_total(1),
I3 => wrap_burst_total(2),
O => \save_init_bram_addr_ld[3]_i_2__0_n_0\
);
\save_init_bram_addr_ld[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(2),
O => bram_addr_ld(2)
);
\save_init_bram_addr_ld[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => save_init_bram_addr_ld(4),
I1 => wrap_burst_total(0),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[4]_i_2__0_n_0\
);
\save_init_bram_addr_ld[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F808F8F8F808080"
)
port map (
I0 => save_init_bram_addr_ld(5),
I1 => \save_init_bram_addr_ld[5]_i_2__0_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I3 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
I4 => axi_awaddr_full,
I5 => s_axi_awaddr(3),
O => bram_addr_ld(3)
);
\save_init_bram_addr_ld[5]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => wrap_burst_total(0),
I1 => wrap_burst_total(2),
I2 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[5]_i_2__0_n_0\
);
\save_init_bram_addr_ld[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(4),
O => bram_addr_ld(4)
);
\save_init_bram_addr_ld[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(5),
O => bram_addr_ld(5)
);
\save_init_bram_addr_ld[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(8),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(6),
O => bram_addr_ld(6)
);
\save_init_bram_addr_ld[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(7),
O => bram_addr_ld(7)
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(8),
Q => save_init_bram_addr_ld(10),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(9),
Q => save_init_bram_addr_ld(11),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(10),
Q => save_init_bram_addr_ld(12),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(11),
Q => save_init_bram_addr_ld(13),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(12),
Q => save_init_bram_addr_ld(14),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(13),
Q => save_init_bram_addr_ld(15),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(1),
Q => save_init_bram_addr_ld(3),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(2),
Q => save_init_bram_addr_ld(4),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(3),
Q => save_init_bram_addr_ld(5),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(4),
Q => save_init_bram_addr_ld(6),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(5),
Q => save_init_bram_addr_ld(7),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(6),
Q => save_init_bram_addr_ld(8),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(7),
Q => save_init_bram_addr_ld(9),
R => s_axi_aresetn_0
);
\wrap_burst_total[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F909090900000000"
)
port map (
I0 => \wrap_burst_total[0]_i_2__0_n_0\,
I1 => \^wrap_burst_total_reg[0]_0\,
I2 => \wrap_burst_total[0]_i_4__0_n_0\,
I3 => Q(1),
I4 => Q(2),
I5 => \wrap_burst_total[0]_i_5_n_0\,
O => \wrap_burst_total[0]_i_1__0_n_0\
);
\wrap_burst_total[0]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(2),
O => \wrap_burst_total[0]_i_2__0_n_0\
);
\wrap_burst_total[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(1),
O => \^wrap_burst_total_reg[0]_0\
);
\wrap_burst_total[0]_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_awaddr_full,
I1 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_4__0_n_0\
);
\wrap_burst_total[0]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_awlen(0),
I1 => Q(0),
I2 => s_axi_awlen(3),
I3 => axi_awaddr_full,
I4 => Q(3),
O => \wrap_burst_total[0]_i_5_n_0\
);
\wrap_burst_total[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"000008F3"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => axi_awsize_pipe(0),
I3 => \^wrap_burst_total_reg[2]_0\,
I4 => \wrap_burst_total[2]_i_2__0_n_0\,
O => \wrap_burst_total[1]_i_1__0_n_0\
);
\wrap_burst_total[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5000000044004400"
)
port map (
I0 => \wrap_burst_total[2]_i_2__0_n_0\,
I1 => s_axi_awlen(2),
I2 => Q(2),
I3 => \^wrap_burst_total_reg[2]_0\,
I4 => axi_awsize_pipe(0),
I5 => axi_awaddr_full,
O => \wrap_burst_total[2]_i_1__0_n_0\
);
\wrap_burst_total[2]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"335FFF5F"
)
port map (
I0 => s_axi_awlen(1),
I1 => Q(1),
I2 => s_axi_awlen(0),
I3 => axi_awaddr_full,
I4 => Q(0),
O => \wrap_burst_total[2]_i_2__0_n_0\
);
\wrap_burst_total[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(3),
O => \^wrap_burst_total_reg[2]_0\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1__0_n_0\,
Q => wrap_burst_total(0),
R => s_axi_aresetn_0
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1__0_n_0\,
Q => wrap_burst_total(1),
R => s_axi_aresetn_0
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1__0_n_0\,
Q => wrap_burst_total(2),
R => s_axi_aresetn_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 is
port (
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_burst_total_reg[0]_0\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_1\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_2\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_3\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 1 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
bram_addr_ld_en : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : out STD_LOGIC;
\rd_data_sm_cs_reg[1]\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_1\ : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_rvalid_int_reg : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
end_brst_rd : in STD_LOGIC;
brst_zero : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_arsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_araddr_full : in STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
axi_rd_burst_two_reg : in STD_LOGIC;
axi_rd_burst : in STD_LOGIC;
axi_aresetn_d2 : in STD_LOGIC;
last_bram_addr : in STD_LOGIC;
rd_addr_sm_cs : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
no_ar_ack : in STD_LOGIC;
pend_rd_op : in STD_LOGIC;
ar_active : in STD_LOGIC;
axi_b2b_brst : in STD_LOGIC;
axi_arsize_pipe_max : in STD_LOGIC;
disable_b2b_brst : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_arlen_pipe_1_or_2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 : entity is "wrap_brst";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 is
signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[6]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[1]\ : STD_LOGIC;
signal \save_init_bram_addr_ld[10]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[15]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[15]_i_3__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[6]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[7]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[8]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_1\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[10]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[11]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[12]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[13]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[14]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[15]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[4]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[5]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[6]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[7]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[8]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_5__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_1\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_2\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_3\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[2]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[15]_i_4__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[5]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_5__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3\ : label is "soft_lutpair4";
begin
D(13 downto 0) <= \^d\(13 downto 0);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[6]\;
SR(0) <= \^sr\(0);
bram_addr_ld_en <= \^bram_addr_ld_en\;
\rd_data_sm_cs_reg[1]\ <= \^rd_data_sm_cs_reg[1]\;
\save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\;
\save_init_bram_addr_ld_reg[15]_1\ <= \^save_init_bram_addr_ld_reg[15]_1\;
\wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\;
\wrap_burst_total_reg[0]_1\ <= \^wrap_burst_total_reg[0]_1\;
\wrap_burst_total_reg[0]_2\ <= \^wrap_burst_total_reg[0]_2\;
\wrap_burst_total_reg[0]_3\ <= \^wrap_burst_total_reg[0]_3\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"DF20FFFFDF200000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
O => \^d\(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"5D"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I2 => curr_fixed_burst_reg,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
O => \^d\(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0F0E0FFE0F0E0F0"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\,
I2 => \^rd_data_sm_cs_reg[1]\,
I3 => Q(1),
I4 => Q(3),
I5 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => Q(0),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0D00000000000000"
)
port map (
I0 => end_brst_rd,
I1 => axi_b2b_brst,
I2 => brst_zero,
I3 => axi_rvalid_int_reg,
I4 => s_axi_rready,
I5 => Q(0),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[12]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(10),
O => \^d\(10)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[13]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(11),
O => \^d\(11)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[14]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(12),
O => \^d\(12)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
O => E(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[15]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(13),
O => \^d\(13)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A80000"
)
port map (
I0 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\,
I2 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I4 => curr_wrap_burst_reg,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00A000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I2 => \wrap_burst_total_reg_n_0_[1]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I4 => \wrap_burst_total_reg_n_0_[0]\,
I5 => \wrap_burst_total_reg_n_0_[2]\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A808FD5D"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => s_axi_araddr(0),
I2 => axi_araddr_full,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
O => \^d\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6F60"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I3 => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
O => \^d\(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AFF6A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
O => \^d\(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAFFFF6AAA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
O => \^d\(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I3 => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
O => \^d\(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
O => \^d\(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A6AAFFFFA6AA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
O => \^d\(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
O => \^d\(7)
);
bram_en_int_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000004000"
)
port map (
I0 => Q(0),
I1 => Q(2),
I2 => axi_rvalid_int_reg,
I3 => s_axi_rready,
I4 => end_brst_rd,
I5 => brst_zero,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\
);
bram_rst_b_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\rd_data_sm_cs[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0302030203020300"
)
port map (
I0 => Q(0),
I1 => Q(3),
I2 => Q(2),
I3 => Q(1),
I4 => axi_rd_burst_two_reg,
I5 => axi_rd_burst,
O => \^rd_data_sm_cs_reg[1]\
);
\save_init_bram_addr_ld[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[10]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(8),
O => \save_init_bram_addr_ld[10]_i_1__0_n_0\
);
\save_init_bram_addr_ld[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[11]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(9),
O => \save_init_bram_addr_ld[11]_i_1__0_n_0\
);
\save_init_bram_addr_ld[15]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888A88888888"
)
port map (
I0 => axi_aresetn_d2,
I1 => \save_init_bram_addr_ld[15]_i_2__0_n_0\,
I2 => \save_init_bram_addr_ld[15]_i_3__0_n_0\,
I3 => \^save_init_bram_addr_ld_reg[15]_0\,
I4 => \^save_init_bram_addr_ld_reg[15]_1\,
I5 => last_bram_addr,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[15]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000054"
)
port map (
I0 => rd_addr_sm_cs,
I1 => axi_araddr_full,
I2 => s_axi_arvalid,
I3 => no_ar_ack,
I4 => pend_rd_op,
I5 => ar_active,
O => \save_init_bram_addr_ld[15]_i_2__0_n_0\
);
\save_init_bram_addr_ld[15]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => brst_zero,
I1 => s_axi_rready,
I2 => axi_rvalid_int_reg,
O => \save_init_bram_addr_ld[15]_i_3__0_n_0\
);
\save_init_bram_addr_ld[15]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
O => \^save_init_bram_addr_ld_reg[15]_0\
);
\save_init_bram_addr_ld[15]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFDFFFF"
)
port map (
I0 => axi_arsize_pipe_max,
I1 => disable_b2b_brst,
I2 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\,
I3 => axi_arlen_pipe_1_or_2,
I4 => axi_araddr_full,
O => \^save_init_bram_addr_ld_reg[15]_1\
);
\save_init_bram_addr_ld[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(1),
O => \save_init_bram_addr_ld[3]_i_1__0_n_0\
);
\save_init_bram_addr_ld[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A282"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[3]\,
I1 => \wrap_burst_total_reg_n_0_[1]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[0]\,
O => \save_init_bram_addr_ld[3]_i_2_n_0\
);
\save_init_bram_addr_ld[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(2),
O => \save_init_bram_addr_ld[4]_i_1__0_n_0\
);
\save_init_bram_addr_ld[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[4]\,
I1 => \wrap_burst_total_reg_n_0_[0]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[4]_i_2_n_0\
);
\save_init_bram_addr_ld[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[5]\,
I1 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
I4 => axi_araddr_full,
I5 => s_axi_araddr(3),
O => \save_init_bram_addr_ld[5]_i_1__0_n_0\
);
\save_init_bram_addr_ld[5]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \wrap_burst_total_reg_n_0_[0]\,
I1 => \wrap_burst_total_reg_n_0_[2]\,
I2 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[5]_i_2_n_0\
);
\save_init_bram_addr_ld[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[6]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(4),
O => \save_init_bram_addr_ld[6]_i_1__0_n_0\
);
\save_init_bram_addr_ld[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[7]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(5),
O => \save_init_bram_addr_ld[7]_i_1__0_n_0\
);
\save_init_bram_addr_ld[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[8]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(6),
O => \save_init_bram_addr_ld[8]_i_1__0_n_0\
);
\save_init_bram_addr_ld[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[9]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(7),
O => \save_init_bram_addr_ld[9]_i_1__0_n_0\
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[10]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[11]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(10),
Q => \save_init_bram_addr_ld_reg_n_0_[12]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(11),
Q => \save_init_bram_addr_ld_reg_n_0_[13]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(12),
Q => \save_init_bram_addr_ld_reg_n_0_[14]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(13),
Q => \save_init_bram_addr_ld_reg_n_0_[15]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[3]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[4]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[5]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[6]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[7]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[8]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[9]\,
R => \^sr\(0)
);
\wrap_burst_total[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A000C300"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I1 => \^wrap_burst_total_reg[0]_0\,
I2 => \^wrap_burst_total_reg[0]_1\,
I3 => \^wrap_burst_total_reg[0]_2\,
I4 => \wrap_burst_total[0]_i_5__0_n_0\,
I5 => \^wrap_burst_total_reg[0]_3\,
O => \wrap_burst_total[0]_i_1_n_0\
);
\wrap_burst_total[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I1 => axi_araddr_full,
I2 => s_axi_arlen(2),
O => \^wrap_burst_total_reg[0]_0\
);
\wrap_burst_total[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
O => \^wrap_burst_total_reg[0]_1\
);
\wrap_burst_total[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(0),
I1 => axi_araddr_full,
I2 => s_axi_arlen(0),
O => \^wrap_burst_total_reg[0]_2\
);
\wrap_burst_total[0]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_araddr_full,
I1 => axi_arsize_pipe(0),
O => \wrap_burst_total[0]_i_5__0_n_0\
);
\wrap_burst_total[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220A880A000A880A"
)
port map (
I0 => \wrap_burst_total[2]_i_2_n_0\,
I1 => axi_arsize_pipe(0),
I2 => s_axi_arlen(3),
I3 => axi_araddr_full,
I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3),
I5 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
O => \wrap_burst_total[1]_i_1_n_0\
);
\wrap_burst_total[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000888800000000"
)
port map (
I0 => \wrap_burst_total[2]_i_2_n_0\,
I1 => s_axi_arlen(2),
I2 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I3 => axi_arsize_pipe(0),
I4 => axi_araddr_full,
I5 => \^wrap_burst_total_reg[0]_3\,
O => \wrap_burst_total[2]_i_1_n_0\
);
\wrap_burst_total[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_arlen(1),
I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(1),
I2 => s_axi_arlen(0),
I3 => axi_araddr_full,
I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(0),
O => \wrap_burst_total[2]_i_2_n_0\
);
\wrap_burst_total[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3),
I1 => axi_araddr_full,
I2 => s_axi_arlen(3),
O => \^wrap_burst_total_reg[0]_3\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[0]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[1]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[2]\,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl is
port (
bram_rst_a : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_en_b : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arready : out STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
axi_aresetn_d2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
axi_aresetn_re_reg : in STD_LOGIC;
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl : entity is "rd_chnl";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl is
signal \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \/i__n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_arready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_4_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_int[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_int[0]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp2[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp2_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp2_reg_n_0_[0]\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[0]_i_3_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp_full_i_1_n_0\ : STD_LOGIC;
signal I_WRAP_BRST_n_0 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_18 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_22 : STD_LOGIC;
signal I_WRAP_BRST_n_24 : STD_LOGIC;
signal I_WRAP_BRST_n_25 : STD_LOGIC;
signal I_WRAP_BRST_n_26 : STD_LOGIC;
signal I_WRAP_BRST_n_27 : STD_LOGIC;
signal I_WRAP_BRST_n_3 : STD_LOGIC;
signal I_WRAP_BRST_n_4 : STD_LOGIC;
signal I_WRAP_BRST_n_5 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal act_rd_burst : STD_LOGIC;
signal act_rd_burst_i_1_n_0 : STD_LOGIC;
signal act_rd_burst_i_3_n_0 : STD_LOGIC;
signal act_rd_burst_i_4_n_0 : STD_LOGIC;
signal act_rd_burst_i_5_n_0 : STD_LOGIC;
signal act_rd_burst_set : STD_LOGIC;
signal act_rd_burst_two : STD_LOGIC;
signal act_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal ar_active : STD_LOGIC;
signal araddr_pipe_ld43_out : STD_LOGIC;
signal axi_araddr_full : STD_LOGIC;
signal axi_arburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_arid_pipe : STD_LOGIC;
signal axi_arlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_arlen_pipe_1_or_2 : STD_LOGIC;
signal axi_arready_int : STD_LOGIC;
signal axi_arsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_arsize_pipe_max : STD_LOGIC;
signal axi_arsize_pipe_max_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst : STD_LOGIC;
signal axi_b2b_brst_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst_i_2_n_0 : STD_LOGIC;
signal axi_early_arready_int : STD_LOGIC;
signal axi_rd_burst : STD_LOGIC;
signal axi_rd_burst_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_i_2_n_0 : STD_LOGIC;
signal axi_rd_burst_i_3_n_0 : STD_LOGIC;
signal axi_rd_burst_two : STD_LOGIC;
signal axi_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_two_reg_n_0 : STD_LOGIC;
signal axi_rid_temp : STD_LOGIC;
signal axi_rid_temp2 : STD_LOGIC;
signal axi_rid_temp2_full : STD_LOGIC;
signal axi_rid_temp_full : STD_LOGIC;
signal axi_rid_temp_full_d1 : STD_LOGIC;
signal axi_rlast_int_i_1_n_0 : STD_LOGIC;
signal axi_rlast_set : STD_LOGIC;
signal axi_rvalid_clr_ok : STD_LOGIC;
signal axi_rvalid_clr_ok_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_2_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_3_n_0 : STD_LOGIC;
signal axi_rvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_set : STD_LOGIC;
signal axi_rvalid_set_cmb : STD_LOGIC;
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal \^bram_en_b\ : STD_LOGIC;
signal bram_en_int_i_10_n_0 : STD_LOGIC;
signal bram_en_int_i_11_n_0 : STD_LOGIC;
signal bram_en_int_i_12_n_0 : STD_LOGIC;
signal bram_en_int_i_13_n_0 : STD_LOGIC;
signal bram_en_int_i_1_n_0 : STD_LOGIC;
signal bram_en_int_i_2_n_0 : STD_LOGIC;
signal bram_en_int_i_3_n_0 : STD_LOGIC;
signal bram_en_int_i_4_n_0 : STD_LOGIC;
signal bram_en_int_i_5_n_0 : STD_LOGIC;
signal bram_en_int_i_6_n_0 : STD_LOGIC;
signal bram_en_int_i_7_n_0 : STD_LOGIC;
signal bram_en_int_i_9_n_0 : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
signal brst_cnt : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \brst_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal brst_cnt_max : STD_LOGIC;
signal brst_cnt_max_d1 : STD_LOGIC;
signal brst_one : STD_LOGIC;
signal brst_one_i_1_n_0 : STD_LOGIC;
signal brst_one_i_2_n_0 : STD_LOGIC;
signal brst_zero : STD_LOGIC;
signal brst_zero_i_1_n_0 : STD_LOGIC;
signal brst_zero_i_2_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal disable_b2b_brst : STD_LOGIC;
signal disable_b2b_brst_cmb : STD_LOGIC;
signal disable_b2b_brst_i_2_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_3_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_4_n_0 : STD_LOGIC;
signal end_brst_rd : STD_LOGIC;
signal end_brst_rd_clr : STD_LOGIC;
signal end_brst_rd_clr_i_1_n_0 : STD_LOGIC;
signal end_brst_rd_i_1_n_0 : STD_LOGIC;
signal last_bram_addr : STD_LOGIC;
signal last_bram_addr0 : STD_LOGIC;
signal last_bram_addr_i_2_n_0 : STD_LOGIC;
signal last_bram_addr_i_3_n_0 : STD_LOGIC;
signal last_bram_addr_i_4_n_0 : STD_LOGIC;
signal last_bram_addr_i_5_n_0 : STD_LOGIC;
signal last_bram_addr_i_6_n_0 : STD_LOGIC;
signal last_bram_addr_i_7_n_0 : STD_LOGIC;
signal last_bram_addr_i_8_n_0 : STD_LOGIC;
signal last_bram_addr_i_9_n_0 : STD_LOGIC;
signal no_ar_ack : STD_LOGIC;
signal no_ar_ack_i_1_n_0 : STD_LOGIC;
signal p_0_in13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_48_out : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pend_rd_op : STD_LOGIC;
signal pend_rd_op_i_1_n_0 : STD_LOGIC;
signal pend_rd_op_i_2_n_0 : STD_LOGIC;
signal pend_rd_op_i_3_n_0 : STD_LOGIC;
signal pend_rd_op_i_4_n_0 : STD_LOGIC;
signal pend_rd_op_i_5_n_0 : STD_LOGIC;
signal pend_rd_op_i_6_n_0 : STD_LOGIC;
signal pend_rd_op_i_7_n_0 : STD_LOGIC;
signal pend_rd_op_i_8_n_0 : STD_LOGIC;
signal rd_addr_sm_cs : STD_LOGIC;
signal rd_adv_buf67_out : STD_LOGIC;
signal rd_data_sm_cs : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \rd_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_6_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_7_n_0\ : STD_LOGIC;
signal rd_data_sm_ns : STD_LOGIC;
signal rd_skid_buf : STD_LOGIC_VECTOR ( 31 downto 0 );
signal rd_skid_buf_ld : STD_LOGIC;
signal rd_skid_buf_ld_cmb : STD_LOGIC;
signal rd_skid_buf_ld_reg : STD_LOGIC;
signal rddata_mux_sel : STD_LOGIC;
signal rddata_mux_sel_cmb : STD_LOGIC;
signal rddata_mux_sel_i_1_n_0 : STD_LOGIC;
signal rddata_mux_sel_i_3_n_0 : STD_LOGIC;
signal rlast_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of rlast_sm_cs : signal is "yes";
signal \^s_axi_rid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_rlast\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_rlast_sm_cs[2]_i_2\ : label is "soft_lutpair14";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_arready_int_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_early_arready_int_i_3\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \GEN_AR_DUAL.ar_active_i_3\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_5\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_int[0]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp[0]_i_2\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of act_rd_burst_i_4 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of act_rd_burst_i_5 : label is "soft_lutpair43";
attribute SOFT_HLUTNM of axi_rd_burst_two_i_2 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_2 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of axi_rvalid_set_i_1 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of bram_en_int_i_10 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of bram_en_int_i_11 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of bram_en_int_i_13 : label is "soft_lutpair22";
attribute SOFT_HLUTNM of bram_en_int_i_6 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of bram_en_int_i_9 : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \brst_cnt[4]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_3\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_4\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of brst_one_i_2 : label is "soft_lutpair31";
attribute SOFT_HLUTNM of brst_zero_i_1 : label is "soft_lutpair18";
attribute SOFT_HLUTNM of brst_zero_i_2 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_1 : label is "soft_lutpair6";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_1 : label is "soft_lutpair6";
attribute SOFT_HLUTNM of disable_b2b_brst_i_2 : label is "soft_lutpair43";
attribute SOFT_HLUTNM of last_bram_addr_i_2 : label is "soft_lutpair31";
attribute SOFT_HLUTNM of last_bram_addr_i_7 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of last_bram_addr_i_9 : label is "soft_lutpair11";
attribute SOFT_HLUTNM of pend_rd_op_i_5 : label is "soft_lutpair27";
attribute SOFT_HLUTNM of pend_rd_op_i_6 : label is "soft_lutpair22";
attribute SOFT_HLUTNM of pend_rd_op_i_7 : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \rd_data_sm_cs[0]_i_3\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \rd_data_sm_cs[1]_i_2\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_3\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_4\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_5\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_6\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_7\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of rddata_mux_sel_i_1 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of s_axi_arready_INST_0 : label is "soft_lutpair21";
begin
Q(13 downto 0) <= \^q\(13 downto 0);
bram_en_b <= \^bram_en_b\;
bram_rst_a <= \^bram_rst_a\;
s_axi_rid(0) <= \^s_axi_rid\(0);
s_axi_rlast <= \^s_axi_rlast\;
s_axi_rvalid <= \^s_axi_rvalid\;
\/FSM_sequential_rlast_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0011001300130013"
)
port map (
I0 => axi_rd_burst,
I1 => rlast_sm_cs(1),
I2 => act_rd_burst_two,
I3 => axi_rd_burst_two_reg_n_0,
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\
);
\/FSM_sequential_rlast_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"003F007F003F0055"
)
port map (
I0 => axi_rd_burst,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rlast_sm_cs(1),
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_two,
O => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\
);
\/i_\: unisim.vcomponents.LUT6
generic map(
INIT => X"F000F111F000E000"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => rlast_sm_cs(0),
I5 => last_bram_addr,
O => \/i__n_0\
);
\/i___0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008080000F8080"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(1),
I4 => rlast_sm_cs(2),
I5 => \^s_axi_rlast\,
O => axi_rlast_set
);
\FSM_sequential_rlast_sm_cs[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(0),
O => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(1),
O => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A4FFFF00A40000"
)
port map (
I0 => rlast_sm_cs(1),
I1 => p_0_in13_in,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(2),
I4 => \/i__n_0\,
I5 => rlast_sm_cs(2),
O => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst,
O => p_0_in13_in
);
\FSM_sequential_rlast_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\,
Q => rlast_sm_cs(0),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\,
Q => rlast_sm_cs(1),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\,
Q => rlast_sm_cs(2),
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_arready_int_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEEE"
)
port map (
I0 => p_9_out,
I1 => axi_arready_int,
I2 => s_axi_arvalid,
I3 => axi_araddr_full,
I4 => araddr_pipe_ld43_out,
O => \GEN_ARREADY.axi_arready_int_i_1_n_0\
);
\GEN_ARREADY.axi_arready_int_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BAAA"
)
port map (
I0 => axi_aresetn_re_reg,
I1 => axi_early_arready_int,
I2 => axi_araddr_full,
I3 => bram_addr_ld_en,
O => p_9_out
);
\GEN_ARREADY.axi_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_ARREADY.axi_arready_int_i_1_n_0\,
Q => axi_arready_int,
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_early_arready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\,
I1 => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\,
I2 => rd_data_sm_cs(3),
I3 => brst_one,
I4 => axi_arready_int,
I5 => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\,
O => p_48_out
);
\GEN_ARREADY.axi_early_arready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"03C4000400C40004"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_adv_buf67_out,
I5 => bram_en_int_i_9_n_0,
O => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\
);
\GEN_ARREADY.axi_early_arready_int_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => axi_araddr_full,
I1 => s_axi_arvalid,
O => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\
);
\GEN_ARREADY.axi_early_arready_int_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAEAAAEAFFFFAAEA"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => \rd_data_sm_cs[3]_i_6_n_0\,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => brst_zero,
I5 => rd_adv_buf67_out,
O => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\
);
\GEN_ARREADY.axi_early_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_48_out,
Q => axi_early_arready_int,
R => \^bram_rst_a\
);
\GEN_AR_DUAL.ar_active_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0FBFBFBF0F0F0F0"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_2_n_0\,
I1 => \rd_data_sm_cs[2]_i_3_n_0\,
I2 => bram_addr_ld_en,
I3 => \rd_data_sm_cs[2]_i_5_n_0\,
I4 => rd_adv_buf67_out,
I5 => ar_active,
O => \GEN_AR_DUAL.ar_active_i_1_n_0\
);
\GEN_AR_DUAL.ar_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B0FFBFFFB0FFBF0F"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_3_n_0\,
I1 => I_WRAP_BRST_n_27,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => axi_rd_burst_two_reg_n_0,
I5 => axi_rd_burst,
O => \GEN_AR_DUAL.ar_active_i_2_n_0\
);
\GEN_AR_DUAL.ar_active_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0DFFFFFF"
)
port map (
I0 => end_brst_rd,
I1 => axi_b2b_brst,
I2 => brst_zero,
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => \GEN_AR_DUAL.ar_active_i_3_n_0\
);
\GEN_AR_DUAL.ar_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.ar_active_i_1_n_0\,
Q => ar_active,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_DUAL.rd_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10001000F0F01000"
)
port map (
I0 => rd_addr_sm_cs,
I1 => axi_araddr_full,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I4 => last_bram_addr,
I5 => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\,
O => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\
);
\GEN_AR_DUAL.rd_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\,
Q => rd_addr_sm_cs,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(8),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(9),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(10),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(11),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(12),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(13),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(0),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(1),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(2),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(3),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(4),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(5),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(6),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(7),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C08888CCCC8888"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => s_axi_aresetn,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I4 => axi_araddr_full,
I5 => bram_addr_ld_en,
O => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\,
Q => axi_araddr_full,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"03AA"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
I1 => s_axi_arburst(0),
I2 => s_axi_arburst(1),
I3 => araddr_pipe_ld43_out,
O => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(0),
Q => axi_arburst_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(1),
Q => axi_arburst_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(0),
Q => axi_arid_pipe,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220022002A002200"
)
port map (
I0 => axi_aresetn_d2,
I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I2 => rd_addr_sm_cs,
I3 => s_axi_arvalid,
I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I5 => axi_araddr_full,
O => araddr_pipe_ld43_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF70FFFFFFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => brst_zero,
I3 => I_WRAP_BRST_n_26,
I4 => I_WRAP_BRST_n_27,
I5 => last_bram_addr,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => no_ar_ack,
I1 => pend_rd_op,
I2 => ar_active,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_arlen(1),
I1 => s_axi_arlen(7),
I2 => s_axi_arlen(4),
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\,
O => p_13_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_axi_arlen(6),
I1 => s_axi_arlen(2),
I2 => s_axi_arlen(5),
I3 => s_axi_arlen(3),
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => p_13_out,
Q => axi_arlen_pipe_1_or_2,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(0),
Q => axi_arlen_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(1),
Q => axi_arlen_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(2),
Q => axi_arlen_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(3),
Q => axi_arlen_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(4),
Q => axi_arlen_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(5),
Q => axi_arlen_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(6),
Q => axi_arlen_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(7),
Q => axi_arlen_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => '1',
Q => axi_arsize_pipe(1),
R => '0'
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BAAA0000"
)
port map (
I0 => brst_cnt_max,
I1 => pend_rd_op,
I2 => ar_active,
I3 => brst_zero,
I4 => s_axi_aresetn,
I5 => bram_addr_ld_en,
O => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\,
Q => brst_cnt_max,
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(4),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
I5 => \^q\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => I_WRAP_BRST_n_24,
I3 => \^q\(5),
I4 => \^q\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_14,
Q => \^q\(8),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_13,
Q => \^q\(9),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_12,
Q => \^q\(10),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_11,
Q => \^q\(11),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_10,
Q => \^q\(12),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_9,
Q => \^q\(13),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_22,
Q => \^q\(0),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_21,
Q => \^q\(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_20,
Q => \^q\(2),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_19,
Q => \^q\(3),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_18,
Q => \^q\(4),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_17,
Q => \^q\(5),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_16,
Q => \^q\(6),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_15,
Q => \^q\(7),
R => '0'
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(0),
I1 => bram_rddata_b(0),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\,
Q => s_axi_rdata(0),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(10),
I1 => bram_rddata_b(10),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\,
Q => s_axi_rdata(10),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(11),
I1 => bram_rddata_b(11),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\,
Q => s_axi_rdata(11),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(12),
I1 => bram_rddata_b(12),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\,
Q => s_axi_rdata(12),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(13),
I1 => bram_rddata_b(13),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\,
Q => s_axi_rdata(13),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(14),
I1 => bram_rddata_b(14),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\,
Q => s_axi_rdata(14),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(15),
I1 => bram_rddata_b(15),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\,
Q => s_axi_rdata(15),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(16),
I1 => bram_rddata_b(16),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\,
Q => s_axi_rdata(16),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(17),
I1 => bram_rddata_b(17),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\,
Q => s_axi_rdata(17),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(18),
I1 => bram_rddata_b(18),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\,
Q => s_axi_rdata(18),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(19),
I1 => bram_rddata_b(19),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\,
Q => s_axi_rdata(19),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(1),
I1 => bram_rddata_b(1),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\,
Q => s_axi_rdata(1),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(20),
I1 => bram_rddata_b(20),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\,
Q => s_axi_rdata(20),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(21),
I1 => bram_rddata_b(21),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\,
Q => s_axi_rdata(21),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(22),
I1 => bram_rddata_b(22),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\,
Q => s_axi_rdata(22),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(23),
I1 => bram_rddata_b(23),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\,
Q => s_axi_rdata(23),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(24),
I1 => bram_rddata_b(24),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\,
Q => s_axi_rdata(24),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(25),
I1 => bram_rddata_b(25),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\,
Q => s_axi_rdata(25),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(26),
I1 => bram_rddata_b(26),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\,
Q => s_axi_rdata(26),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(27),
I1 => bram_rddata_b(27),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\,
Q => s_axi_rdata(27),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(28),
I1 => bram_rddata_b(28),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\,
Q => s_axi_rdata(28),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(29),
I1 => bram_rddata_b(29),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\,
Q => s_axi_rdata(29),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(2),
I1 => bram_rddata_b(2),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\,
Q => s_axi_rdata(2),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(30),
I1 => bram_rddata_b(30),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\,
Q => s_axi_rdata(30),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"08FF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rlast\,
I2 => axi_b2b_brst,
I3 => s_axi_aresetn,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414545410000404"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\,
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(31),
I1 => bram_rddata_b(31),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
O => rd_adv_buf67_out
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\,
Q => s_axi_rdata(31),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(3),
I1 => bram_rddata_b(3),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\,
Q => s_axi_rdata(3),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(4),
I1 => bram_rddata_b(4),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\,
Q => s_axi_rdata(4),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(5),
I1 => bram_rddata_b(5),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\,
Q => s_axi_rdata(5),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(6),
I1 => bram_rddata_b(6),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\,
Q => s_axi_rdata(6),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(7),
I1 => bram_rddata_b(7),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\,
Q => s_axi_rdata(7),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(8),
I1 => bram_rddata_b(8),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\,
Q => s_axi_rdata(8),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(9),
I1 => bram_rddata_b(9),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\,
Q => s_axi_rdata(9),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAABAAAAAA"
)
port map (
I0 => rd_skid_buf_ld_reg,
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(3),
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(2),
I5 => rd_data_sm_cs(0),
O => rd_skid_buf_ld
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(0),
Q => rd_skid_buf(0),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(10),
Q => rd_skid_buf(10),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(11),
Q => rd_skid_buf(11),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(12),
Q => rd_skid_buf(12),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(13),
Q => rd_skid_buf(13),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(14),
Q => rd_skid_buf(14),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(15),
Q => rd_skid_buf(15),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(16),
Q => rd_skid_buf(16),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(17),
Q => rd_skid_buf(17),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(18),
Q => rd_skid_buf(18),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(19),
Q => rd_skid_buf(19),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(1),
Q => rd_skid_buf(1),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(20),
Q => rd_skid_buf(20),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(21),
Q => rd_skid_buf(21),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(22),
Q => rd_skid_buf(22),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(23),
Q => rd_skid_buf(23),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(24),
Q => rd_skid_buf(24),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(25),
Q => rd_skid_buf(25),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(26),
Q => rd_skid_buf(26),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(27),
Q => rd_skid_buf(27),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(28),
Q => rd_skid_buf(28),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(29),
Q => rd_skid_buf(29),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(2),
Q => rd_skid_buf(2),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(30),
Q => rd_skid_buf(30),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(31),
Q => rd_skid_buf(31),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(3),
Q => rd_skid_buf(3),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(4),
Q => rd_skid_buf(4),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(5),
Q => rd_skid_buf(5),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(6),
Q => rd_skid_buf(6),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(7),
Q => rd_skid_buf(7),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(8),
Q => rd_skid_buf(8),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(9),
Q => rd_skid_buf(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_int[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E200E200F0000000"
)
port map (
I0 => \^s_axi_rid\(0),
I1 => axi_rvalid_set,
I2 => axi_rid_temp,
I3 => s_axi_aresetn,
I4 => axi_b2b_brst,
I5 => \GEN_RID.axi_rid_int[0]_i_2_n_0\,
O => \GEN_RID.axi_rid_int[0]_i_1_n_0\
);
\GEN_RID.axi_rid_int[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rlast\,
O => \GEN_RID.axi_rid_int[0]_i_2_n_0\
);
\GEN_RID.axi_rid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_int[0]_i_1_n_0\,
Q => \^s_axi_rid\(0),
R => '0'
);
\GEN_RID.axi_rid_temp2[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFFFFFB8000000"
)
port map (
I0 => axi_arid_pipe,
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
I3 => axi_rid_temp_full,
I4 => bram_addr_ld_en,
I5 => \GEN_RID.axi_rid_temp2_reg_n_0_[0]\,
O => \GEN_RID.axi_rid_temp2[0]_i_1_n_0\
);
\GEN_RID.axi_rid_temp2_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080000C8C800C0"
)
port map (
I0 => bram_addr_ld_en,
I1 => s_axi_aresetn,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full_d1,
I4 => axi_rid_temp_full,
I5 => p_4_out,
O => \GEN_RID.axi_rid_temp2_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp2_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp2_full_i_1_n_0\,
Q => axi_rid_temp2_full,
R => '0'
);
\GEN_RID.axi_rid_temp2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp2[0]_i_1_n_0\,
Q => \GEN_RID.axi_rid_temp2_reg_n_0_[0]\,
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFAACFCFC0AAC0C0"
)
port map (
I0 => axi_rid_temp2,
I1 => \GEN_RID.axi_rid_temp2_reg_n_0_[0]\,
I2 => \GEN_RID.axi_rid_temp[0]_i_3_n_0\,
I3 => axi_rid_temp_full,
I4 => bram_addr_ld_en,
I5 => axi_rid_temp,
O => \GEN_RID.axi_rid_temp[0]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe,
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
O => axi_rid_temp2
);
\GEN_RID.axi_rid_temp[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA08AAAAAA08AA08"
)
port map (
I0 => axi_rid_temp2_full,
I1 => axi_rid_temp_full_d1,
I2 => axi_rid_temp_full,
I3 => axi_rvalid_set,
I4 => \GEN_RID.axi_rid_int[0]_i_2_n_0\,
I5 => axi_b2b_brst,
O => \GEN_RID.axi_rid_temp[0]_i_3_n_0\
);
\GEN_RID.axi_rid_temp_full_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rid_temp_full,
Q => axi_rid_temp_full_d1,
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0E000F0A0A0"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_rid_temp_full_d1,
I2 => s_axi_aresetn,
I3 => p_4_out,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2_full,
O => \GEN_RID.axi_rid_temp_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_rvalid_set,
I1 => s_axi_rready,
I2 => \^s_axi_rlast\,
I3 => axi_b2b_brst,
O => p_4_out
);
\GEN_RID.axi_rid_temp_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp_full_i_1_n_0\,
Q => axi_rid_temp_full,
R => '0'
);
\GEN_RID.axi_rid_temp_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp[0]_i_1_n_0\,
Q => axi_rid_temp,
R => \^bram_rst_a\
);
I_WRAP_BRST: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0
port map (
D(13) => I_WRAP_BRST_n_9,
D(12) => I_WRAP_BRST_n_10,
D(11) => I_WRAP_BRST_n_11,
D(10) => I_WRAP_BRST_n_12,
D(9) => I_WRAP_BRST_n_13,
D(8) => I_WRAP_BRST_n_14,
D(7) => I_WRAP_BRST_n_15,
D(6) => I_WRAP_BRST_n_16,
D(5) => I_WRAP_BRST_n_17,
D(4) => I_WRAP_BRST_n_18,
D(3) => I_WRAP_BRST_n_19,
D(2) => I_WRAP_BRST_n_20,
D(1) => I_WRAP_BRST_n_21,
D(0) => I_WRAP_BRST_n_22,
E(1) => bram_addr_ld_en_mod,
E(0) => I_WRAP_BRST_n_7,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3 downto 0) => axi_arlen_pipe(3 downto 0),
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ => I_WRAP_BRST_n_0,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ => I_WRAP_BRST_n_8,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9 downto 0) => \^q\(9 downto 0),
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => I_WRAP_BRST_n_24,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\,
Q(3 downto 0) => rd_data_sm_cs(3 downto 0),
SR(0) => \^bram_rst_a\,
ar_active => ar_active,
axi_araddr_full => axi_araddr_full,
axi_aresetn_d2 => axi_aresetn_d2,
axi_arlen_pipe_1_or_2 => axi_arlen_pipe_1_or_2,
axi_arsize_pipe(0) => axi_arsize_pipe(1),
axi_arsize_pipe_max => axi_arsize_pipe_max,
axi_b2b_brst => axi_b2b_brst,
axi_rd_burst => axi_rd_burst,
axi_rd_burst_two_reg => axi_rd_burst_two_reg_n_0,
axi_rvalid_int_reg => \^s_axi_rvalid\,
bram_addr_ld_en => bram_addr_ld_en,
brst_zero => brst_zero,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_wrap_burst_reg => curr_wrap_burst_reg,
disable_b2b_brst => disable_b2b_brst,
end_brst_rd => end_brst_rd,
last_bram_addr => last_bram_addr,
no_ar_ack => no_ar_ack,
pend_rd_op => pend_rd_op,
rd_addr_sm_cs => rd_addr_sm_cs,
\rd_data_sm_cs_reg[1]\ => I_WRAP_BRST_n_25,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_rready => s_axi_rready,
\save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_26,
\save_init_bram_addr_ld_reg[15]_1\ => I_WRAP_BRST_n_27,
\wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_2,
\wrap_burst_total_reg[0]_1\ => I_WRAP_BRST_n_3,
\wrap_burst_total_reg[0]_2\ => I_WRAP_BRST_n_4,
\wrap_burst_total_reg[0]_3\ => I_WRAP_BRST_n_5
);
act_rd_burst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002EEE22E2"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_set,
I2 => bram_addr_ld_en,
I3 => axi_rd_burst_two,
I4 => axi_rd_burst,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_i_1_n_0
);
act_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A888A888888888"
)
port map (
I0 => \rd_data_sm_cs[2]_i_3_n_0\,
I1 => act_rd_burst_i_4_n_0,
I2 => act_rd_burst_i_5_n_0,
I3 => axi_rd_burst_i_2_n_0,
I4 => I_WRAP_BRST_n_4,
I5 => bram_addr_ld_en,
O => act_rd_burst_set
);
act_rd_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"20000040FFFFFFFF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => \rd_data_sm_cs[3]_i_7_n_0\,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => s_axi_aresetn,
O => act_rd_burst_i_3_n_0
);
act_rd_burst_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"5500FC00"
)
port map (
I0 => bram_en_int_i_12_n_0,
I1 => axi_rd_burst_two_reg_n_0,
I2 => axi_rd_burst,
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => act_rd_burst_i_4_n_0
);
act_rd_burst_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => act_rd_burst_i_5_n_0
);
act_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_i_1_n_0,
Q => act_rd_burst,
R => '0'
);
act_rd_burst_two_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2EEE222"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst_set,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_two_i_1_n_0
);
act_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_two_i_1_n_0,
Q => act_rd_burst_two,
R => '0'
);
axi_arsize_pipe_max_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => axi_arsize_pipe_max,
O => axi_arsize_pipe_max_i_1_n_0
);
axi_arsize_pipe_max_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_arsize_pipe_max_i_1_n_0,
Q => axi_arsize_pipe_max,
R => \^bram_rst_a\
);
axi_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"F000F074F0F0F074"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => axi_b2b_brst_i_2_n_0,
I2 => axi_b2b_brst,
I3 => rd_data_sm_cs(3),
I4 => rd_data_sm_cs(2),
I5 => disable_b2b_brst_i_2_n_0,
O => axi_b2b_brst_i_1_n_0
);
axi_b2b_brst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AA080000"
)
port map (
I0 => \rd_data_sm_cs[0]_i_3_n_0\,
I1 => end_brst_rd,
I2 => axi_b2b_brst,
I3 => brst_zero,
I4 => rd_adv_buf67_out,
I5 => I_WRAP_BRST_n_27,
O => axi_b2b_brst_i_2_n_0
);
axi_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_b2b_brst_i_1_n_0,
Q => axi_b2b_brst,
R => \^bram_rst_a\
);
axi_rd_burst_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"303000A0"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_i_2_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_i_1_n_0
);
axi_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000001000111"
)
port map (
I0 => I_WRAP_BRST_n_2,
I1 => I_WRAP_BRST_n_5,
I2 => axi_arlen_pipe(1),
I3 => axi_araddr_full,
I4 => s_axi_arlen(1),
I5 => axi_rd_burst_i_3_n_0,
O => axi_rd_burst_i_2_n_0
);
axi_rd_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFBBFCB8"
)
port map (
I0 => axi_arlen_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arlen(5),
I3 => axi_arlen_pipe(4),
I4 => s_axi_arlen(4),
I5 => last_bram_addr_i_9_n_0,
O => axi_rd_burst_i_3_n_0
);
axi_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_i_1_n_0,
Q => axi_rd_burst,
R => '0'
);
axi_rd_burst_two_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"C0C000A0"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst_two,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_two_i_1_n_0
);
axi_rd_burst_two_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"A808"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => axi_rd_burst_two
);
axi_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_two_i_1_n_0,
Q => axi_rd_burst_two_reg_n_0,
R => '0'
);
axi_rlast_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"88A8"
)
port map (
I0 => s_axi_aresetn,
I1 => axi_rlast_set,
I2 => \^s_axi_rlast\,
I3 => s_axi_rready,
O => axi_rlast_int_i_1_n_0
);
axi_rlast_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rlast_int_i_1_n_0,
Q => \^s_axi_rlast\,
R => '0'
);
axi_rvalid_clr_ok_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFEEEA"
)
port map (
I0 => axi_rvalid_clr_ok,
I1 => last_bram_addr,
I2 => disable_b2b_brst,
I3 => disable_b2b_brst_cmb,
I4 => axi_rvalid_clr_ok_i_2_n_0,
I5 => axi_rvalid_clr_ok_i_3_n_0,
O => axi_rvalid_clr_ok_i_1_n_0
);
axi_rvalid_clr_ok_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(3),
O => axi_rvalid_clr_ok_i_2_n_0
);
axi_rvalid_clr_ok_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\,
I1 => bram_addr_ld_en,
I2 => s_axi_aresetn,
O => axi_rvalid_clr_ok_i_3_n_0
);
axi_rvalid_clr_ok_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_clr_ok_i_1_n_0,
Q => axi_rvalid_clr_ok,
R => '0'
);
axi_rvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00E0E0E0E0E0E0E0"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => axi_rvalid_set,
I2 => s_axi_aresetn,
I3 => axi_rvalid_clr_ok,
I4 => \^s_axi_rlast\,
I5 => s_axi_rready,
O => axi_rvalid_int_i_1_n_0
);
axi_rvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_int_i_1_n_0,
Q => \^s_axi_rvalid\,
R => '0'
);
axi_rvalid_set_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
O => axi_rvalid_set_cmb
);
axi_rvalid_set_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_set_cmb,
Q => axi_rvalid_set,
R => \^bram_rst_a\
);
bram_en_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEEFFFA0022000A"
)
port map (
I0 => bram_en_int_i_2_n_0,
I1 => bram_en_int_i_3_n_0,
I2 => bram_en_int_i_4_n_0,
I3 => rd_data_sm_cs(3),
I4 => rd_data_sm_cs(2),
I5 => \^bram_en_b\,
O => bram_en_int_i_1_n_0
);
bram_en_int_i_10: unisim.vcomponents.LUT5
generic map(
INIT => X"E0000000"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => bram_addr_ld_en,
O => bram_en_int_i_10_n_0
);
bram_en_int_i_11: unisim.vcomponents.LUT4
generic map(
INIT => X"0111"
)
port map (
I0 => end_brst_rd,
I1 => brst_zero,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => bram_en_int_i_11_n_0
);
bram_en_int_i_12: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFBFBFBFFFBFFF"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => brst_zero,
I4 => axi_b2b_brst,
I5 => end_brst_rd,
O => bram_en_int_i_12_n_0
);
bram_en_int_i_13: unisim.vcomponents.LUT3
generic map(
INIT => X"45"
)
port map (
I0 => brst_zero,
I1 => axi_b2b_brst,
I2 => end_brst_rd,
O => bram_en_int_i_13_n_0
);
bram_en_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF4044"
)
port map (
I0 => bram_en_int_i_5_n_0,
I1 => rd_data_sm_cs(1),
I2 => bram_en_int_i_6_n_0,
I3 => rd_data_sm_cs(2),
I4 => bram_en_int_i_7_n_0,
I5 => I_WRAP_BRST_n_0,
O => bram_en_int_i_2_n_0
);
bram_en_int_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"707370707C7F7C7C"
)
port map (
I0 => bram_en_int_i_6_n_0,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => rd_adv_buf67_out,
I4 => bram_en_int_i_9_n_0,
I5 => bram_en_int_i_10_n_0,
O => bram_en_int_i_3_n_0
);
bram_en_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"A0001111AAAA1111"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => bram_addr_ld_en,
I2 => bram_en_int_i_11_n_0,
I3 => brst_one,
I4 => rd_data_sm_cs(1),
I5 => bram_en_int_i_12_n_0,
O => bram_en_int_i_4_n_0
);
bram_en_int_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0044054455440544"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => axi_rd_burst_two_reg_n_0,
I2 => bram_en_int_i_9_n_0,
I3 => rd_data_sm_cs(0),
I4 => rd_adv_buf67_out,
I5 => bram_en_int_i_13_n_0,
O => bram_en_int_i_5_n_0
);
bram_en_int_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"ECCC"
)
port map (
I0 => pend_rd_op,
I1 => bram_addr_ld_en,
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
O => bram_en_int_i_6_n_0
);
bram_en_int_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"5554005500540000"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => axi_rd_burst_two_reg_n_0,
I2 => axi_rd_burst,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(0),
I5 => bram_addr_ld_en,
O => bram_en_int_i_7_n_0
);
bram_en_int_i_9: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => brst_zero,
I1 => end_brst_rd,
O => bram_en_int_i_9_n_0
);
bram_en_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_int_i_1_n_0,
Q => \^bram_en_b\,
R => \^bram_rst_a\
);
\brst_cnt[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D1DDD111"
)
port map (
I0 => brst_cnt(0),
I1 => bram_addr_ld_en,
I2 => axi_arlen_pipe(0),
I3 => axi_araddr_full,
I4 => s_axi_arlen(0),
O => \brst_cnt[0]_i_1_n_0\
);
\brst_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB800B800B8FF"
)
port map (
I0 => axi_arlen_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
I3 => bram_addr_ld_en,
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[1]_i_1_n_0\
);
\brst_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_2,
I1 => bram_addr_ld_en,
I2 => brst_cnt(2),
I3 => brst_cnt(1),
I4 => brst_cnt(0),
O => \brst_cnt[2]_i_1_n_0\
);
\brst_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_5,
I1 => bram_addr_ld_en,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[3]_i_1_n_0\
);
\brst_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB800B800B8FF"
)
port map (
I0 => axi_arlen_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arlen(4),
I3 => bram_addr_ld_en,
I4 => brst_cnt(4),
I5 => \brst_cnt[4]_i_2_n_0\,
O => \brst_cnt[4]_i_1_n_0\
);
\brst_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => brst_cnt(3),
I1 => brst_cnt(2),
I2 => brst_cnt(0),
I3 => brst_cnt(1),
O => \brst_cnt[4]_i_2_n_0\
);
\brst_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arlen(5),
I3 => bram_addr_ld_en,
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[5]_i_1_n_0\
);
\brst_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(6),
I3 => brst_cnt(5),
I4 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[6]_i_1_n_0\
);
\brst_cnt[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arlen(6),
O => \brst_cnt[6]_i_2_n_0\
);
\brst_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_8,
O => \brst_cnt[7]_i_1_n_0\
);
\brst_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B88BB8B8B8B8"
)
port map (
I0 => \brst_cnt[7]_i_3_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(7),
I3 => brst_cnt(6),
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[7]_i_2_n_0\
);
\brst_cnt[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arlen(7),
O => \brst_cnt[7]_i_3_n_0\
);
\brst_cnt[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => brst_cnt(4),
I1 => brst_cnt(1),
I2 => brst_cnt(0),
I3 => brst_cnt(2),
I4 => brst_cnt(3),
O => \brst_cnt[7]_i_4_n_0\
);
brst_cnt_max_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_cnt_max,
Q => brst_cnt_max_d1,
R => \^bram_rst_a\
);
\brst_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[0]_i_1_n_0\,
Q => brst_cnt(0),
R => \^bram_rst_a\
);
\brst_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[1]_i_1_n_0\,
Q => brst_cnt(1),
R => \^bram_rst_a\
);
\brst_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[2]_i_1_n_0\,
Q => brst_cnt(2),
R => \^bram_rst_a\
);
\brst_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[3]_i_1_n_0\,
Q => brst_cnt(3),
R => \^bram_rst_a\
);
\brst_cnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[4]_i_1_n_0\,
Q => brst_cnt(4),
R => \^bram_rst_a\
);
\brst_cnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[5]_i_1_n_0\,
Q => brst_cnt(5),
R => \^bram_rst_a\
);
\brst_cnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[6]_i_1_n_0\,
Q => brst_cnt(6),
R => \^bram_rst_a\
);
\brst_cnt_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[7]_i_2_n_0\,
Q => brst_cnt(7),
R => \^bram_rst_a\
);
brst_one_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F0EE0000"
)
port map (
I0 => brst_one,
I1 => brst_one_i_2_n_0,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => s_axi_aresetn,
I5 => last_bram_addr_i_2_n_0,
O => brst_one_i_1_n_0
);
brst_one_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => last_bram_addr_i_5_n_0,
I1 => brst_cnt(1),
I2 => brst_cnt(0),
O => brst_one_i_2_n_0
);
brst_one_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_one_i_1_n_0,
Q => brst_one,
R => '0'
);
brst_zero_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => brst_zero,
I1 => last_bram_addr_i_2_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero_i_2_n_0,
O => brst_zero_i_1_n_0
);
brst_zero_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8A80AAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_arlen_pipe(0),
I2 => axi_araddr_full,
I3 => s_axi_arlen(0),
I4 => axi_rd_burst_i_2_n_0,
O => brst_zero_i_2_n_0
);
brst_zero_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_zero_i_1_n_0,
Q => brst_zero,
R => '0'
);
curr_fixed_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arburst(0),
I1 => axi_arburst_pipe(0),
I2 => s_axi_arburst(1),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(1),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_fixed_burst,
Q => curr_fixed_burst_reg,
R => \^bram_rst_a\
);
curr_wrap_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_arburst(1),
I1 => axi_arburst_pipe(1),
I2 => s_axi_arburst(0),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_wrap_burst,
Q => curr_wrap_burst_reg,
R => \^bram_rst_a\
);
disable_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000D0000"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(3),
I4 => disable_b2b_brst_i_2_n_0,
I5 => disable_b2b_brst_i_3_n_0,
O => disable_b2b_brst_cmb
);
disable_b2b_brst_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
O => disable_b2b_brst_i_2_n_0
);
disable_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEE00EE0EEEE"
)
port map (
I0 => disable_b2b_brst_i_4_n_0,
I1 => disable_b2b_brst,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => rd_data_sm_cs(3),
O => disable_b2b_brst_i_3_n_0
);
disable_b2b_brst_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FE0000000000"
)
port map (
I0 => brst_zero,
I1 => end_brst_rd,
I2 => brst_one,
I3 => rd_data_sm_cs(0),
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[2]_i_3_n_0\,
O => disable_b2b_brst_i_4_n_0
);
disable_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => disable_b2b_brst_cmb,
Q => disable_b2b_brst,
R => \^bram_rst_a\
);
end_brst_rd_clr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFCD00002200"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
I2 => bram_addr_ld_en,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(3),
I5 => end_brst_rd_clr,
O => end_brst_rd_clr_i_1_n_0
);
end_brst_rd_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_clr_i_1_n_0,
Q => end_brst_rd_clr,
R => \^bram_rst_a\
);
end_brst_rd_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0020F020"
)
port map (
I0 => brst_cnt_max,
I1 => brst_cnt_max_d1,
I2 => s_axi_aresetn,
I3 => end_brst_rd,
I4 => end_brst_rd_clr,
O => end_brst_rd_i_1_n_0
);
end_brst_rd_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_i_1_n_0,
Q => end_brst_rd,
R => '0'
);
last_bram_addr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FAAAAAAAAAAAAFAB"
)
port map (
I0 => last_bram_addr_i_2_n_0,
I1 => last_bram_addr_i_3_n_0,
I2 => rd_data_sm_cs(2),
I3 => last_bram_addr_i_4_n_0,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => last_bram_addr0
);
last_bram_addr_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => last_bram_addr_i_5_n_0,
I1 => brst_cnt(0),
I2 => brst_cnt(1),
O => last_bram_addr_i_2_n_0
);
last_bram_addr_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F707F7F7F7F7F"
)
port map (
I0 => p_0_in13_in,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(3),
I3 => bram_addr_ld_en,
I4 => I_WRAP_BRST_n_4,
I5 => axi_rd_burst_i_2_n_0,
O => last_bram_addr_i_3_n_0
);
last_bram_addr_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"A888200000000000"
)
port map (
I0 => rd_adv_buf67_out,
I1 => bram_addr_ld_en,
I2 => pend_rd_op,
I3 => p_0_in13_in,
I4 => last_bram_addr_i_6_n_0,
I5 => \rd_data_sm_cs[3]_i_6_n_0\,
O => last_bram_addr_i_4_n_0
);
last_bram_addr_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => I_WRAP_BRST_n_8,
I1 => brst_cnt(7),
I2 => brst_cnt(3),
I3 => brst_cnt(4),
I4 => brst_cnt(2),
I5 => last_bram_addr_i_7_n_0,
O => last_bram_addr_i_5_n_0
);
last_bram_addr_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => last_bram_addr_i_8_n_0,
I1 => last_bram_addr_i_9_n_0,
I2 => I_WRAP_BRST_n_3,
I3 => I_WRAP_BRST_n_5,
I4 => I_WRAP_BRST_n_2,
I5 => I_WRAP_BRST_n_4,
O => last_bram_addr_i_6_n_0
);
last_bram_addr_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => brst_cnt(6),
I1 => brst_cnt(5),
O => last_bram_addr_i_7_n_0
);
last_bram_addr_i_8: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => s_axi_arlen(4),
I1 => axi_arlen_pipe(4),
I2 => s_axi_arlen(5),
I3 => axi_araddr_full,
I4 => axi_arlen_pipe(5),
O => last_bram_addr_i_8_n_0
);
last_bram_addr_i_9: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => s_axi_arlen(6),
I1 => axi_arlen_pipe(6),
I2 => s_axi_arlen(7),
I3 => axi_araddr_full,
I4 => axi_arlen_pipe(7),
O => last_bram_addr_i_9_n_0
);
last_bram_addr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => last_bram_addr0,
Q => last_bram_addr,
R => \^bram_rst_a\
);
no_ar_ack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"88C8AAAAAAAAAAAA"
)
port map (
I0 => no_ar_ack,
I1 => rd_data_sm_cs(1),
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => \rd_data_sm_cs[3]_i_6_n_0\,
I5 => rd_data_sm_cs(0),
O => no_ar_ack_i_1_n_0
);
no_ar_ack_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => no_ar_ack_i_1_n_0,
Q => no_ar_ack,
R => \^bram_rst_a\
);
pend_rd_op_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFFFEAAAA0002"
)
port map (
I0 => pend_rd_op_i_2_n_0,
I1 => pend_rd_op_i_3_n_0,
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(2),
I4 => pend_rd_op_i_4_n_0,
I5 => pend_rd_op,
O => pend_rd_op_i_1_n_0
);
pend_rd_op_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFCC8C80CCCC8C8"
)
port map (
I0 => p_0_in13_in,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => pend_rd_op_i_5_n_0,
O => pend_rd_op_i_2_n_0
);
pend_rd_op_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0303070733F3FFFF"
)
port map (
I0 => p_0_in13_in,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => \^s_axi_rlast\,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => pend_rd_op_i_3_n_0
);
pend_rd_op_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080FFD5FF"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_adv_buf67_out,
I2 => pend_rd_op,
I3 => rd_data_sm_cs(1),
I4 => pend_rd_op_i_6_n_0,
I5 => pend_rd_op_i_7_n_0,
O => pend_rd_op_i_4_n_0
);
pend_rd_op_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => ar_active,
I1 => end_brst_rd,
O => pend_rd_op_i_5_n_0
);
pend_rd_op_i_6: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => bram_addr_ld_en,
I1 => end_brst_rd,
I2 => ar_active,
O => pend_rd_op_i_6_n_0
);
pend_rd_op_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"F1FF"
)
port map (
I0 => pend_rd_op_i_8_n_0,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(2),
O => pend_rd_op_i_7_n_0
);
pend_rd_op_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF0008888"
)
port map (
I0 => pend_rd_op,
I1 => \^s_axi_rlast\,
I2 => ar_active,
I3 => end_brst_rd,
I4 => rd_data_sm_cs(0),
I5 => rd_data_sm_cs(1),
O => pend_rd_op_i_8_n_0
);
pend_rd_op_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => pend_rd_op_i_1_n_0,
Q => pend_rd_op,
R => \^bram_rst_a\
);
\rd_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF54005555"
)
port map (
I0 => \rd_data_sm_cs[0]_i_2_n_0\,
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => \rd_data_sm_cs[0]_i_3_n_0\,
I5 => \rd_data_sm_cs[0]_i_4_n_0\,
O => \rd_data_sm_cs[0]_i_1_n_0\
);
\rd_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"E000E0E0FFFFFFFF"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst,
I2 => disable_b2b_brst_i_2_n_0,
I3 => bram_addr_ld_en,
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[3]_i_6_n_0\,
O => \rd_data_sm_cs[0]_i_2_n_0\
);
\rd_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[0]_i_3_n_0\
);
\rd_data_sm_cs[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"001100F7001100D5"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
I2 => rd_adv_buf67_out,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(3),
I5 => p_0_in13_in,
O => \rd_data_sm_cs[0]_i_4_n_0\
);
\rd_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAEAAAEFFFFAAAE"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => \rd_data_sm_cs[1]_i_2_n_0\,
I2 => end_brst_rd,
I3 => brst_zero,
I4 => I_WRAP_BRST_n_25,
I5 => \rd_data_sm_cs[2]_i_4_n_0\,
O => \rd_data_sm_cs[1]_i_1_n_0\
);
\rd_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[1]_i_2_n_0\
);
\rd_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEEEAEAEA"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => \rd_data_sm_cs[2]_i_3_n_0\,
I2 => \rd_data_sm_cs[2]_i_4_n_0\,
I3 => p_0_in13_in,
I4 => disable_b2b_brst_i_2_n_0,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => \rd_data_sm_cs[2]_i_1_n_0\
);
\rd_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000007000F000000"
)
port map (
I0 => \rd_data_sm_cs[3]_i_7_n_0\,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[2]_i_2_n_0\
);
\rd_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
O => \rd_data_sm_cs[2]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"C8C8C8C808C8C8C8"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
I5 => I_WRAP_BRST_n_27,
O => \rd_data_sm_cs[2]_i_4_n_0\
);
\rd_data_sm_cs[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000400040000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => brst_zero,
I5 => end_brst_rd,
O => \rd_data_sm_cs[2]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7444777730007444"
)
port map (
I0 => \rd_data_sm_cs[3]_i_3_n_0\,
I1 => \rd_data_sm_cs[3]_i_4_n_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
I4 => \rd_data_sm_cs[3]_i_5_n_0\,
I5 => bram_addr_ld_en,
O => rd_data_sm_ns
);
\rd_data_sm_cs[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800000AA800000"
)
port map (
I0 => \rd_data_sm_cs[3]_i_6_n_0\,
I1 => bram_addr_ld_en,
I2 => \rd_data_sm_cs[3]_i_7_n_0\,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[3]_i_2_n_0\
);
\rd_data_sm_cs[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000D0000000000"
)
port map (
I0 => end_brst_rd,
I1 => axi_b2b_brst,
I2 => brst_zero,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(3),
I5 => \rd_data_sm_cs[0]_i_3_n_0\,
O => \rd_data_sm_cs[3]_i_3_n_0\
);
\rd_data_sm_cs[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"BFAD"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_4_n_0\
);
\rd_data_sm_cs[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0053"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
O => \rd_data_sm_cs[3]_i_6_n_0\
);
\rd_data_sm_cs[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => act_rd_burst_two,
I3 => act_rd_burst,
O => \rd_data_sm_cs[3]_i_7_n_0\
);
\rd_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[0]_i_1_n_0\,
Q => rd_data_sm_cs(0),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[1]_i_1_n_0\,
Q => rd_data_sm_cs(1),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[2]_i_1_n_0\,
Q => rd_data_sm_cs(2),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[3]_i_2_n_0\,
Q => rd_data_sm_cs(3),
R => \^bram_rst_a\
);
rd_skid_buf_ld_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1000111111110000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => rd_skid_buf_ld_cmb
);
rd_skid_buf_ld_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rd_skid_buf_ld_cmb,
Q => rd_skid_buf_ld_reg,
R => \^bram_rst_a\
);
rddata_mux_sel_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => rddata_mux_sel_cmb,
I1 => rd_data_sm_cs(3),
I2 => rddata_mux_sel_i_3_n_0,
I3 => rddata_mux_sel,
O => rddata_mux_sel_i_1_n_0
);
rddata_mux_sel_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"D208D208D208F208"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
I2 => rd_adv_buf67_out,
I3 => rd_data_sm_cs(2),
I4 => act_rd_burst,
I5 => act_rd_burst_two,
O => rddata_mux_sel_cmb
);
rddata_mux_sel_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"A007AF07AF07AF07"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => rddata_mux_sel_i_3_n_0
);
rddata_mux_sel_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rddata_mux_sel_i_1_n_0,
Q => rddata_mux_sel,
R => \^bram_rst_a\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_arready_int,
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => axi_early_arready_int,
O => s_axi_arready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl is
port (
axi_aresetn_d2 : out STD_LOGIC;
axi_aresetn_re_reg : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\GEN_AW_DUAL.aw_active_reg_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aresetn_0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl : entity is "wr_chnl";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl is
signal BID_FIFO_n_1 : STD_LOGIC;
signal BID_FIFO_n_4 : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.aw_active_i_2_n_0\ : STD_LOGIC;
signal \^gen_aw_dual.aw_active_reg_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\ : STD_LOGIC;
signal \I_RD_CHNL/axi_aresetn_d1\ : STD_LOGIC;
signal I_WRAP_BRST_n_0 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_22 : STD_LOGIC;
signal I_WRAP_BRST_n_23 : STD_LOGIC;
signal I_WRAP_BRST_n_24 : STD_LOGIC;
signal I_WRAP_BRST_n_25 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal aw_active : STD_LOGIC;
signal \^axi_aresetn_d2\ : STD_LOGIC;
signal axi_aresetn_re : STD_LOGIC;
signal \^axi_aresetn_re_reg\ : STD_LOGIC;
signal axi_awaddr_full : STD_LOGIC;
signal axi_awburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_awid_pipe : STD_LOGIC;
signal axi_awlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_awlen_pipe_1_or_2 : STD_LOGIC;
signal axi_awsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_bvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_wdata_full_cmb : STD_LOGIC;
signal axi_wdata_full_cmb114_out : STD_LOGIC;
signal axi_wdata_full_reg : STD_LOGIC;
signal axi_wr_burst : STD_LOGIC;
signal axi_wr_burst_cmb : STD_LOGIC;
signal axi_wr_burst_cmb0 : STD_LOGIC;
signal axi_wr_burst_i_1_n_0 : STD_LOGIC;
signal axi_wr_burst_i_3_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_1_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_3_n_0 : STD_LOGIC;
signal bid_gets_fifo_load : STD_LOGIC;
signal bid_gets_fifo_load_d1 : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_2_n_0 : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal bram_addr_inc : STD_LOGIC;
signal bram_addr_ld : STD_LOGIC_VECTOR ( 13 downto 10 );
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal bram_addr_rst_cmb : STD_LOGIC;
signal bram_en_cmb : STD_LOGIC;
signal bvalid_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \bvalid_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal bvalid_cnt_inc : STD_LOGIC;
signal bvalid_cnt_inc11_out : STD_LOGIC;
signal clr_bram_we : STD_LOGIC;
signal clr_bram_we_cmb : STD_LOGIC;
signal curr_awlen_reg_1_or_2 : STD_LOGIC;
signal curr_awlen_reg_1_or_20 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_2_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal delay_aw_active_clr : STD_LOGIC;
signal last_data_ack_mod : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_bid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal wr_addr_sm_cs : STD_LOGIC;
signal wr_data_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of wr_data_sm_cs : signal is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\ : label is "soft_lutpair53";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \GEN_AW_DUAL.last_data_ack_mod_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_2 : label is "soft_lutpair51";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_2 : label is "soft_lutpair50";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_2 : label is "soft_lutpair50";
begin
\GEN_AW_DUAL.aw_active_reg_0\ <= \^gen_aw_dual.aw_active_reg_0\;
axi_aresetn_d2 <= \^axi_aresetn_d2\;
axi_aresetn_re_reg <= \^axi_aresetn_re_reg\;
bram_addr_a(13 downto 0) <= \^bram_addr_a\(13 downto 0);
s_axi_awready <= \^s_axi_awready\;
s_axi_bid(0) <= \^s_axi_bid\(0);
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_wready <= \^s_axi_wready\;
BID_FIFO: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO
port map (
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awid_pipe => axi_awid_pipe,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
\axi_bid_int_reg[0]\ => BID_FIFO_n_4,
axi_bvalid_int_reg => \^s_axi_bvalid\,
axi_wdata_full_cmb114_out => axi_wdata_full_cmb114_out,
axi_wr_burst => axi_wr_burst,
bid_gets_fifo_load => bid_gets_fifo_load,
bid_gets_fifo_load_d1 => bid_gets_fifo_load_d1,
bid_gets_fifo_load_d1_reg => BID_FIFO_n_1,
bram_addr_ld_en => bram_addr_ld_en,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
bvalid_cnt_inc => bvalid_cnt_inc,
\bvalid_cnt_reg[1]\ => bid_gets_fifo_load_d1_i_2_n_0,
\bvalid_cnt_reg[2]\ => I_WRAP_BRST_n_20,
\bvalid_cnt_reg[2]_0\ => I_WRAP_BRST_n_19,
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn_0,
s_axi_awid(0) => s_axi_awid(0),
s_axi_awready => \^s_axi_awready\,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => \^s_axi_bid\(0),
s_axi_bready => s_axi_bready,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
wr_addr_sm_cs => wr_addr_sm_cs
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(0),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"05051F1A"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => axi_wr_burst_cmb0,
I2 => wr_data_sm_cs(0),
I3 => axi_wdata_full_cmb114_out,
I4 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"5515"
)
port map (
I0 => I_WRAP_BRST_n_21,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
O => axi_wr_burst_cmb0
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(1),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000554000555540"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => s_axi_wlast,
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(2),
I5 => axi_wr_burst,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"44010001"
)
port map (
I0 => wr_data_sm_cs(2),
I1 => wr_data_sm_cs(1),
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7774777774744444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(0),
I5 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\,
Q => wr_data_sm_cs(0),
R => s_axi_aresetn_0
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\,
Q => wr_data_sm_cs(1),
R => s_axi_aresetn_0
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\,
Q => wr_data_sm_cs(2),
R => s_axi_aresetn_0
);
\GEN_AWREADY.axi_aresetn_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_aresetn,
Q => \I_RD_CHNL/axi_aresetn_d1\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \I_RD_CHNL/axi_aresetn_d1\,
Q => \^axi_aresetn_d2\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_re_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_aresetn,
I1 => \I_RD_CHNL/axi_aresetn_d1\,
O => axi_aresetn_re
);
\GEN_AWREADY.axi_aresetn_re_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_aresetn_re,
Q => \^axi_aresetn_re_reg\,
R => '0'
);
\GEN_AWREADY.axi_awready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFBFFFFFAA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => bram_addr_ld_en,
I4 => \^axi_aresetn_re_reg\,
I5 => \^s_axi_awready\,
O => \GEN_AWREADY.axi_awready_int_i_1_n_0\
);
\GEN_AWREADY.axi_awready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5444444400000000"
)
port map (
I0 => \GEN_AWREADY.axi_awready_int_i_3_n_0\,
I1 => aw_active,
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => s_axi_awvalid,
O => \GEN_AWREADY.axi_awready_int_i_2_n_0\
);
\GEN_AWREADY.axi_awready_int_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABABABABABABABA"
)
port map (
I0 => wr_addr_sm_cs,
I1 => I_WRAP_BRST_n_21,
I2 => last_data_ack_mod,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \GEN_AWREADY.axi_awready_int_i_3_n_0\
);
\GEN_AWREADY.axi_awready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AWREADY.axi_awready_int_i_1_n_0\,
Q => \^s_axi_awready\,
R => s_axi_aresetn_0
);
\GEN_AW_DUAL.aw_active_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axi_aresetn_d2\,
O => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.aw_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7FFFFFF0000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => wr_data_sm_cs(2),
I3 => delay_aw_active_clr,
I4 => bram_addr_ld_en,
I5 => aw_active,
O => \GEN_AW_DUAL.aw_active_i_2_n_0\
);
\GEN_AW_DUAL.aw_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.aw_active_i_2_n_0\,
Q => aw_active,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.last_data_ack_mod_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => p_18_out
);
\GEN_AW_DUAL.last_data_ack_mod_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_18_out,
Q => last_data_ack_mod,
R => s_axi_aresetn_0
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000100000"
)
port map (
I0 => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\,
I1 => wr_addr_sm_cs,
I2 => s_axi_awvalid,
I3 => axi_awaddr_full,
I4 => I_WRAP_BRST_n_20,
I5 => aw_active,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => I_WRAP_BRST_n_20,
I1 => last_data_ack_mod,
I2 => axi_awaddr_full,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => axi_awlen_pipe_1_or_2,
I5 => curr_awlen_reg_1_or_2,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\,
Q => wr_addr_sm_cs,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(8),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(9),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(10),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(11),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(12),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(13),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(0),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(1),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(2),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(3),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(4),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(5),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(6),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(7),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4000EA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => s_axi_aresetn,
I4 => bram_addr_ld_en,
O => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\,
Q => axi_awaddr_full,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BF00BF00BF00FF40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => s_axi_awburst(0),
I5 => s_axi_awburst(1),
O => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(0),
Q => axi_awburst_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(1),
Q => axi_awburst_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(0),
Q => axi_awid_pipe,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I1 => s_axi_awlen(3),
I2 => s_axi_awlen(2),
I3 => s_axi_awlen(1),
O => p_9_out
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_awlen(4),
I1 => s_axi_awlen(6),
I2 => s_axi_awlen(7),
I3 => s_axi_awlen(5),
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => p_9_out,
Q => axi_awlen_pipe_1_or_2,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(0),
Q => axi_awlen_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(1),
Q => axi_awlen_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(2),
Q => axi_awlen_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(3),
Q => axi_awlen_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(4),
Q => axi_awlen_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(5),
Q => axi_awlen_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(6),
Q => axi_awlen_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(7),
Q => axi_awlen_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => '1',
Q => axi_awsize_pipe(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^bram_addr_a\(4),
I1 => \^bram_addr_a\(1),
I2 => \^bram_addr_a\(0),
I3 => \^bram_addr_a\(2),
I4 => \^bram_addr_a\(3),
I5 => \^bram_addr_a\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^bram_addr_a\(6),
I1 => \^bram_addr_a\(4),
I2 => I_WRAP_BRST_n_17,
I3 => \^bram_addr_a\(5),
I4 => \^bram_addr_a\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => s_axi_wvalid,
O => bram_addr_inc
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => wr_data_sm_cs(1),
O => bram_addr_rst_cmb
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_8,
Q => \^bram_addr_a\(8),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_7,
Q => \^bram_addr_a\(9),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(10),
Q => \^bram_addr_a\(10),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(11),
Q => \^bram_addr_a\(11),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(12),
Q => \^bram_addr_a\(12),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(13),
Q => \^bram_addr_a\(13),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_16,
Q => \^bram_addr_a\(0),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_15,
Q => \^bram_addr_a\(1),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_14,
Q => \^bram_addr_a\(2),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_13,
Q => \^bram_addr_a\(3),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_12,
Q => \^bram_addr_a\(4),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_11,
Q => \^bram_addr_a\(5),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_10,
Q => \^bram_addr_a\(6),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_9,
Q => \^bram_addr_a\(7),
R => I_WRAP_BRST_n_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"15FF1500"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
O => axi_wdata_full_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wdata_full_cmb,
Q => axi_wdata_full_reg,
R => s_axi_aresetn_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4777477444444444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => s_axi_wvalid,
O => bram_en_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_cmb,
Q => bram_en_a,
R => s_axi_aresetn_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000101110"
)
port map (
I0 => wr_data_sm_cs(0),
I1 => wr_data_sm_cs(1),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I5 => axi_wr_burst,
O => clr_bram_we_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => clr_bram_we_cmb,
Q => clr_bram_we,
R => s_axi_aresetn_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAFEFF02AA0200"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\,
I1 => axi_wr_burst,
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\,
I5 => delay_aw_active_clr,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222E"
)
port map (
I0 => s_axi_wlast,
I1 => wr_data_sm_cs(2),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(1),
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8B338B0088008800"
)
port map (
I0 => delay_aw_active_clr,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => bvalid_cnt_inc11_out,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_wlast,
O => bvalid_cnt_inc11_out
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\,
Q => delay_aw_active_clr,
R => s_axi_aresetn_0
);
\GEN_WRDATA[0].bram_wrdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(0),
Q => bram_wrdata_a(0),
R => '0'
);
\GEN_WRDATA[10].bram_wrdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(10),
Q => bram_wrdata_a(10),
R => '0'
);
\GEN_WRDATA[11].bram_wrdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(11),
Q => bram_wrdata_a(11),
R => '0'
);
\GEN_WRDATA[12].bram_wrdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(12),
Q => bram_wrdata_a(12),
R => '0'
);
\GEN_WRDATA[13].bram_wrdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(13),
Q => bram_wrdata_a(13),
R => '0'
);
\GEN_WRDATA[14].bram_wrdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(14),
Q => bram_wrdata_a(14),
R => '0'
);
\GEN_WRDATA[15].bram_wrdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(15),
Q => bram_wrdata_a(15),
R => '0'
);
\GEN_WRDATA[16].bram_wrdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(16),
Q => bram_wrdata_a(16),
R => '0'
);
\GEN_WRDATA[17].bram_wrdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(17),
Q => bram_wrdata_a(17),
R => '0'
);
\GEN_WRDATA[18].bram_wrdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(18),
Q => bram_wrdata_a(18),
R => '0'
);
\GEN_WRDATA[19].bram_wrdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(19),
Q => bram_wrdata_a(19),
R => '0'
);
\GEN_WRDATA[1].bram_wrdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(1),
Q => bram_wrdata_a(1),
R => '0'
);
\GEN_WRDATA[20].bram_wrdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(20),
Q => bram_wrdata_a(20),
R => '0'
);
\GEN_WRDATA[21].bram_wrdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(21),
Q => bram_wrdata_a(21),
R => '0'
);
\GEN_WRDATA[22].bram_wrdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(22),
Q => bram_wrdata_a(22),
R => '0'
);
\GEN_WRDATA[23].bram_wrdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(23),
Q => bram_wrdata_a(23),
R => '0'
);
\GEN_WRDATA[24].bram_wrdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(24),
Q => bram_wrdata_a(24),
R => '0'
);
\GEN_WRDATA[25].bram_wrdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(25),
Q => bram_wrdata_a(25),
R => '0'
);
\GEN_WRDATA[26].bram_wrdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(26),
Q => bram_wrdata_a(26),
R => '0'
);
\GEN_WRDATA[27].bram_wrdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(27),
Q => bram_wrdata_a(27),
R => '0'
);
\GEN_WRDATA[28].bram_wrdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(28),
Q => bram_wrdata_a(28),
R => '0'
);
\GEN_WRDATA[29].bram_wrdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(29),
Q => bram_wrdata_a(29),
R => '0'
);
\GEN_WRDATA[2].bram_wrdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(2),
Q => bram_wrdata_a(2),
R => '0'
);
\GEN_WRDATA[30].bram_wrdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(30),
Q => bram_wrdata_a(30),
R => '0'
);
\GEN_WRDATA[31].bram_wrdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(31),
Q => bram_wrdata_a(31),
R => '0'
);
\GEN_WRDATA[3].bram_wrdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(3),
Q => bram_wrdata_a(3),
R => '0'
);
\GEN_WRDATA[4].bram_wrdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(4),
Q => bram_wrdata_a(4),
R => '0'
);
\GEN_WRDATA[5].bram_wrdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(5),
Q => bram_wrdata_a(5),
R => '0'
);
\GEN_WRDATA[6].bram_wrdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(6),
Q => bram_wrdata_a(6),
R => '0'
);
\GEN_WRDATA[7].bram_wrdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(7),
Q => bram_wrdata_a(7),
R => '0'
);
\GEN_WRDATA[8].bram_wrdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(8),
Q => bram_wrdata_a(8),
R => '0'
);
\GEN_WRDATA[9].bram_wrdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(9),
Q => bram_wrdata_a(9),
R => '0'
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"D0FF"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => clr_bram_we,
I3 => s_axi_aresetn,
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(0),
Q => bram_we_a(0),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(1),
Q => bram_we_a(1),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(2),
Q => bram_we_a(2),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(3),
Q => bram_we_a(3),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
I_WRAP_BRST: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst
port map (
D(13 downto 10) => bram_addr_ld(13 downto 10),
D(9) => I_WRAP_BRST_n_7,
D(8) => I_WRAP_BRST_n_8,
D(7) => I_WRAP_BRST_n_9,
D(6) => I_WRAP_BRST_n_10,
D(5) => I_WRAP_BRST_n_11,
D(4) => I_WRAP_BRST_n_12,
D(3) => I_WRAP_BRST_n_13,
D(2) => I_WRAP_BRST_n_14,
D(1) => I_WRAP_BRST_n_15,
D(0) => I_WRAP_BRST_n_16,
E(0) => I_WRAP_BRST_n_2,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => I_WRAP_BRST_n_17,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\,
Q(3 downto 0) => axi_awlen_pipe(3 downto 0),
SR(0) => I_WRAP_BRST_n_0,
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_awsize_pipe(0) => axi_awsize_pipe(1),
bram_addr_a(9 downto 0) => \^bram_addr_a\(9 downto 0),
bram_addr_inc => bram_addr_inc,
bram_addr_ld_en => bram_addr_ld_en,
bram_addr_ld_en_mod => bram_addr_ld_en_mod,
bram_addr_rst_cmb => bram_addr_rst_cmb,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
curr_fixed_burst => curr_fixed_burst,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_fixed_burst_reg_reg => I_WRAP_BRST_n_24,
curr_wrap_burst => curr_wrap_burst,
curr_wrap_burst_reg => curr_wrap_burst_reg,
curr_wrap_burst_reg_reg => I_WRAP_BRST_n_25,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => s_axi_aresetn_0,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_wvalid => s_axi_wvalid,
\save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_19,
\save_init_bram_addr_ld_reg[15]_1\ => I_WRAP_BRST_n_20,
\save_init_bram_addr_ld_reg[15]_2\ => I_WRAP_BRST_n_21,
wr_addr_sm_cs => wr_addr_sm_cs,
\wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_22,
\wrap_burst_total_reg[2]_0\ => I_WRAP_BRST_n_23
);
\axi_bid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => BID_FIFO_n_4,
Q => \^s_axi_bid\(0),
R => s_axi_aresetn_0
);
axi_bvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAA8A88"
)
port map (
I0 => s_axi_aresetn,
I1 => bvalid_cnt_inc,
I2 => BID_FIFO_n_1,
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => bvalid_cnt(1),
O => axi_bvalid_int_i_1_n_0
);
axi_bvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_bvalid_int_i_1_n_0,
Q => \^s_axi_bvalid\,
R => '0'
);
axi_wr_burst_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_wr_burst_cmb,
I1 => axi_wr_burst_i_3_n_0,
I2 => axi_wr_burst,
O => axi_wr_burst_i_1_n_0
);
axi_wr_burst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"3088FCBB"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wlast,
O => axi_wr_burst_cmb
);
axi_wr_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAA222"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(0),
I2 => axi_wr_burst_cmb0,
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(1),
I5 => wr_data_sm_cs(2),
O => axi_wr_burst_i_3_n_0
);
axi_wr_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wr_burst_i_1_n_0,
Q => axi_wr_burst,
R => s_axi_aresetn_0
);
axi_wready_int_mod_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EA00EAFF00000000"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
I5 => s_axi_aresetn,
O => axi_wready_int_mod_i_1_n_0
);
axi_wready_int_mod_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"F8F9F0F0"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => axi_wdata_full_reg,
I3 => axi_wdata_full_cmb114_out,
I4 => s_axi_wvalid,
O => axi_wready_int_mod_i_3_n_0
);
axi_wready_int_mod_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wready_int_mod_i_1_n_0,
Q => \^s_axi_wready\,
R => '0'
);
bid_gets_fifo_load_d1_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
O => bid_gets_fifo_load_d1_i_2_n_0
);
bid_gets_fifo_load_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bid_gets_fifo_load,
Q => bid_gets_fifo_load_d1,
R => s_axi_aresetn_0
);
\bvalid_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"95956A6A95956AAA"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[0]_i_1_n_0\
);
\bvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D5D5BFBF2A2A4000"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[1]_i_1_n_0\
);
\bvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D52AFF00FF00BF00"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[2]_i_1_n_0\
);
\bvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[0]_i_1_n_0\,
Q => bvalid_cnt(0),
R => s_axi_aresetn_0
);
\bvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[1]_i_1_n_0\,
Q => bvalid_cnt(1),
R => s_axi_aresetn_0
);
\bvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[2]_i_1_n_0\,
Q => bvalid_cnt(2),
R => s_axi_aresetn_0
);
curr_awlen_reg_1_or_2_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000151"
)
port map (
I0 => I_WRAP_BRST_n_23,
I1 => s_axi_awlen(2),
I2 => axi_awaddr_full,
I3 => axi_awlen_pipe(2),
I4 => I_WRAP_BRST_n_22,
I5 => curr_awlen_reg_1_or_2_i_2_n_0,
O => curr_awlen_reg_1_or_20
);
curr_awlen_reg_1_or_2_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F5F5F5F5F5F5F5C5"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I1 => axi_awlen_pipe(5),
I2 => axi_awaddr_full,
I3 => axi_awlen_pipe(6),
I4 => axi_awlen_pipe(7),
I5 => axi_awlen_pipe(4),
O => curr_awlen_reg_1_or_2_i_2_n_0
);
curr_awlen_reg_1_or_2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_awlen_reg_1_or_20,
Q => curr_awlen_reg_1_or_2,
R => s_axi_aresetn_0
);
curr_fixed_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_24,
Q => curr_fixed_burst_reg,
R => '0'
);
curr_wrap_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_25,
Q => curr_wrap_burst_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi : entity is "full_axi";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi is
signal I_WR_CHNL_n_36 : STD_LOGIC;
signal axi_aresetn_d2 : STD_LOGIC;
signal axi_aresetn_re_reg : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
begin
bram_rst_a <= \^bram_rst_a\;
I_RD_CHNL: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl
port map (
\GEN_AWREADY.axi_aresetn_d2_reg\ => I_WR_CHNL_n_36,
Q(13 downto 0) => bram_addr_b(13 downto 0),
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => s_axi_rid(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
I_WR_CHNL: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl
port map (
\GEN_AW_DUAL.aw_active_reg_0\ => I_WR_CHNL_n_36,
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0),
bram_en_a => bram_en_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => \^bram_rst_a\,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top : entity is "axi_bram_ctrl_top";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top is
begin
\GEN_AXI4.I_FULL_AXI\: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi
port map (
bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0),
bram_addr_b(13 downto 0) => bram_addr_b(13 downto 0),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => s_axi_rid(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ecc_interrupt : out STD_LOGIC;
ecc_ue : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_ctrl_awvalid : in STD_LOGIC;
s_axi_ctrl_awready : out STD_LOGIC;
s_axi_ctrl_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wvalid : in STD_LOGIC;
s_axi_ctrl_wready : out STD_LOGIC;
s_axi_ctrl_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_bvalid : out STD_LOGIC;
s_axi_ctrl_bready : in STD_LOGIC;
s_axi_ctrl_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_arvalid : in STD_LOGIC;
s_axi_ctrl_arready : out STD_LOGIC;
s_axi_ctrl_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_rvalid : out STD_LOGIC;
s_axi_ctrl_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 14;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 16384;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 16;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 1;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "axi_bram_ctrl";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "yes";
end zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl is
signal \<const0>\ : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \^bram_addr_b\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \^bram_rst_a\ : STD_LOGIC;
signal \^s_axi_aclk\ : STD_LOGIC;
begin
\^s_axi_aclk\ <= s_axi_aclk;
bram_addr_a(15 downto 2) <= \^bram_addr_a\(15 downto 2);
bram_addr_a(1) <= \<const0>\;
bram_addr_a(0) <= \<const0>\;
bram_addr_b(15 downto 2) <= \^bram_addr_b\(15 downto 2);
bram_addr_b(1) <= \<const0>\;
bram_addr_b(0) <= \<const0>\;
bram_clk_a <= \^s_axi_aclk\;
bram_clk_b <= \^s_axi_aclk\;
bram_rst_a <= \^bram_rst_a\;
bram_rst_b <= \^bram_rst_a\;
bram_we_b(3) <= \<const0>\;
bram_we_b(2) <= \<const0>\;
bram_we_b(1) <= \<const0>\;
bram_we_b(0) <= \<const0>\;
bram_wrdata_b(31) <= \<const0>\;
bram_wrdata_b(30) <= \<const0>\;
bram_wrdata_b(29) <= \<const0>\;
bram_wrdata_b(28) <= \<const0>\;
bram_wrdata_b(27) <= \<const0>\;
bram_wrdata_b(26) <= \<const0>\;
bram_wrdata_b(25) <= \<const0>\;
bram_wrdata_b(24) <= \<const0>\;
bram_wrdata_b(23) <= \<const0>\;
bram_wrdata_b(22) <= \<const0>\;
bram_wrdata_b(21) <= \<const0>\;
bram_wrdata_b(20) <= \<const0>\;
bram_wrdata_b(19) <= \<const0>\;
bram_wrdata_b(18) <= \<const0>\;
bram_wrdata_b(17) <= \<const0>\;
bram_wrdata_b(16) <= \<const0>\;
bram_wrdata_b(15) <= \<const0>\;
bram_wrdata_b(14) <= \<const0>\;
bram_wrdata_b(13) <= \<const0>\;
bram_wrdata_b(12) <= \<const0>\;
bram_wrdata_b(11) <= \<const0>\;
bram_wrdata_b(10) <= \<const0>\;
bram_wrdata_b(9) <= \<const0>\;
bram_wrdata_b(8) <= \<const0>\;
bram_wrdata_b(7) <= \<const0>\;
bram_wrdata_b(6) <= \<const0>\;
bram_wrdata_b(5) <= \<const0>\;
bram_wrdata_b(4) <= \<const0>\;
bram_wrdata_b(3) <= \<const0>\;
bram_wrdata_b(2) <= \<const0>\;
bram_wrdata_b(1) <= \<const0>\;
bram_wrdata_b(0) <= \<const0>\;
ecc_interrupt <= \<const0>\;
ecc_ue <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_ctrl_arready <= \<const0>\;
s_axi_ctrl_awready <= \<const0>\;
s_axi_ctrl_bresp(1) <= \<const0>\;
s_axi_ctrl_bresp(0) <= \<const0>\;
s_axi_ctrl_bvalid <= \<const0>\;
s_axi_ctrl_rdata(31) <= \<const0>\;
s_axi_ctrl_rdata(30) <= \<const0>\;
s_axi_ctrl_rdata(29) <= \<const0>\;
s_axi_ctrl_rdata(28) <= \<const0>\;
s_axi_ctrl_rdata(27) <= \<const0>\;
s_axi_ctrl_rdata(26) <= \<const0>\;
s_axi_ctrl_rdata(25) <= \<const0>\;
s_axi_ctrl_rdata(24) <= \<const0>\;
s_axi_ctrl_rdata(23) <= \<const0>\;
s_axi_ctrl_rdata(22) <= \<const0>\;
s_axi_ctrl_rdata(21) <= \<const0>\;
s_axi_ctrl_rdata(20) <= \<const0>\;
s_axi_ctrl_rdata(19) <= \<const0>\;
s_axi_ctrl_rdata(18) <= \<const0>\;
s_axi_ctrl_rdata(17) <= \<const0>\;
s_axi_ctrl_rdata(16) <= \<const0>\;
s_axi_ctrl_rdata(15) <= \<const0>\;
s_axi_ctrl_rdata(14) <= \<const0>\;
s_axi_ctrl_rdata(13) <= \<const0>\;
s_axi_ctrl_rdata(12) <= \<const0>\;
s_axi_ctrl_rdata(11) <= \<const0>\;
s_axi_ctrl_rdata(10) <= \<const0>\;
s_axi_ctrl_rdata(9) <= \<const0>\;
s_axi_ctrl_rdata(8) <= \<const0>\;
s_axi_ctrl_rdata(7) <= \<const0>\;
s_axi_ctrl_rdata(6) <= \<const0>\;
s_axi_ctrl_rdata(5) <= \<const0>\;
s_axi_ctrl_rdata(4) <= \<const0>\;
s_axi_ctrl_rdata(3) <= \<const0>\;
s_axi_ctrl_rdata(2) <= \<const0>\;
s_axi_ctrl_rdata(1) <= \<const0>\;
s_axi_ctrl_rdata(0) <= \<const0>\;
s_axi_ctrl_rresp(1) <= \<const0>\;
s_axi_ctrl_rresp(0) <= \<const0>\;
s_axi_ctrl_rvalid <= \<const0>\;
s_axi_ctrl_wready <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gext_inst.abcv4_0_ext_inst\: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top
port map (
bram_addr_a(13 downto 0) => \^bram_addr_a\(15 downto 2),
bram_addr_b(13 downto 0) => \^bram_addr_b\(15 downto 2),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => \^s_axi_aclk\,
s_axi_araddr(13 downto 0) => s_axi_araddr(15 downto 2),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(15 downto 2),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => s_axi_rid(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is "zqynq_lab_1_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is "axi_bram_ctrl,Vivado 2017.2";
end zqynq_lab_1_design_axi_bram_ctrl_0_0;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0 is
signal NLW_U0_ecc_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ecc_ue_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_ctrl_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ctrl_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_ctrl_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of U0 : label is 14;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of U0 : label is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of U0 : label is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of U0 : label is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of U0 : label is 16384;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 16;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of U0 : label is 1;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of U0 : label is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of U0 : label is 0;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl
port map (
bram_addr_a(15 downto 0) => bram_addr_a(15 downto 0),
bram_addr_b(15 downto 0) => bram_addr_b(15 downto 0),
bram_clk_a => bram_clk_a,
bram_clk_b => bram_clk_b,
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_a(31 downto 0) => bram_rddata_a(31 downto 0),
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_rst_b => bram_rst_b,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_we_b(3 downto 0) => bram_we_b(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
bram_wrdata_b(31 downto 0) => bram_wrdata_b(31 downto 0),
ecc_interrupt => NLW_U0_ecc_interrupt_UNCONNECTED,
ecc_ue => NLW_U0_ecc_ue_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(15 downto 0) => s_axi_araddr(15 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock => s_axi_arlock,
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(15 downto 0) => s_axi_awaddr(15 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock => s_axi_awlock,
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_ctrl_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_arready => NLW_U0_s_axi_ctrl_arready_UNCONNECTED,
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_awready => NLW_U0_s_axi_ctrl_awready_UNCONNECTED,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_bresp(1 downto 0) => NLW_U0_s_axi_ctrl_bresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_bvalid => NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED,
s_axi_ctrl_rdata(31 downto 0) => NLW_U0_s_axi_ctrl_rdata_UNCONNECTED(31 downto 0),
s_axi_ctrl_rready => '0',
s_axi_ctrl_rresp(1 downto 0) => NLW_U0_s_axi_ctrl_rresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_rvalid => NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED,
s_axi_ctrl_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_wready => NLW_U0_s_axi_ctrl_wready_UNCONNECTED,
s_axi_ctrl_wvalid => '0',
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 11;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 1;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant MAX_FPU_DELAY : integer := FSQRT_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 4;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
-------------------------------------------------------------------------------
-- Global package
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package Global is
constant cActivated : std_logic := '1';
constant cInactivated : std_logic := '0';
constant cnActivated : std_logic := '0';
constant cnInactivated : std_logic := '1';
constant cByteLength : natural := 8;
constant cWordLength : natural := 2 * cByteLength;
constant cFalse : natural := 0;
constant cTrue : natural := 1;
function LogDualis(cNumber : natural) return natural;
function maximum (a : natural; b : natural) return natural;
function minimum (a : natural; b : natural) return natural;
function integerToBoolean (a : integer) return boolean;
function booleanToInteger (a : boolean) return integer;
function byteSwap (iVector : std_logic_vector) return std_logic_vector;
function wordSwap (iVector : std_logic_vector) return std_logic_vector;
function reduceOr (iVector : std_logic_vector) return std_logic;
function reduceAnd (iVector : std_logic_vector) return std_logic;
end Global;
package body Global is
function LogDualis(cNumber : natural) return natural is
variable vClimbUp : natural := 1;
variable vResult : natural := 0;
begin
while vClimbUp < cNumber loop
vClimbUp := vClimbUp * 2;
vResult := vResult+1;
end loop;
return vResult;
end LogDualis;
function maximum (a : natural; b : natural) return natural is
variable vRes : natural;
begin
if a > b then
vRes := a;
else
vRes := b;
end if;
return vRes;
end function;
function minimum (a : natural; b : natural) return natural is
variable vRes : natural;
begin
if a < b then
vRes := a;
else
vRes := b;
end if;
return vRes;
end function;
function integerToBoolean (a : integer) return boolean is
variable vRes : boolean;
begin
if a = cFalse then
vRes := false;
else
vRes := true;
end if;
return vRes;
end function;
function booleanToInteger (a : boolean) return integer is
variable vRes : integer;
begin
if a = false then
vRes := cFalse;
else
vRes := cTrue;
end if;
return vRes;
end function;
function byteSwap (iVector : std_logic_vector) return std_logic_vector is
variable vResult : std_logic_vector(iVector'range);
variable vLeftIndex : natural;
variable vRightIndex : natural;
begin
assert ((iVector'length mod cByteLength) = 0)
report "Byte swapping can't be done with that vector!"
severity failure;
for i in iVector'length / cByteLength downto 1 loop
vLeftIndex := i;
vRightIndex := iVector'length / cByteLength - i + 1;
vResult(vLeftIndex * cByteLength - 1 downto (vLeftIndex-1) * cByteLength) :=
iVector(vRightIndex * cByteLength - 1 downto (vRightIndex-1) * cByteLength);
end loop;
return vResult;
end function;
function wordSwap (iVector : std_logic_vector) return std_logic_vector is
variable vResult : std_logic_vector(iVector'range);
variable vLeftIndex : natural;
variable vRightIndex : natural;
begin
assert ((iVector'length mod cWordLength) = 0)
report "Word swapping can't be done with that vector!"
severity failure;
for i in iVector'length / cWordLength downto 1 loop
vLeftIndex := i;
vRightIndex := iVector'length / cWordLength - i + 1;
vResult(vLeftIndex * cWordLength - 1 downto (vLeftIndex-1) * cWordLength) :=
iVector(vRightIndex * cWordLength - 1 downto (vRightIndex-1) * cWordLength);
end loop;
return vResult;
end function;
function reduceOr (iVector : std_logic_vector) return std_logic is
variable vRes_tmp : std_logic;
begin
-- initialize result variable
vRes_tmp := cInactivated;
for i in iVector'range loop
vRes_tmp := vRes_tmp or iVector(i);
end loop;
return vRes_tmp;
end function;
function reduceAnd (iVector : std_logic_vector) return std_logic is
variable vRes_tmp : std_logic;
begin
-- initialize result variable
vRes_tmp := cActivated;
for i in iVector'range loop
vRes_tmp := vRes_tmp and iVector(i);
end loop;
return vRes_tmp;
end function;
end Global; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc378.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n03i00378ent IS
END c03s02b01x01p03n03i00378ent;
ARCHITECTURE c03s02b01x01p03n03i00378arch OF c03s02b01x01p03n03i00378ent IS
type M1 is array (positive range <>) of integer;
subtype M2 is M1 (2 to 200); -- No_failure_here
BEGIN
TESTING: PROCESS
variable k : M2;
BEGIN
k(2) := 2;
k(200) := 200;
assert NOT ( k(2) = 2 and
k(200) = 200)
report "***PASSED TEST: c03s02b01x01p03n03i00378"
severity NOTE;
assert ( k(2) = 2 and
k(200) = 200)
report "***FAILED TEST: c03s02b01x01p03n03i00378 - The index constraint must provide a discrete range for each index of the array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n03i00378arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc378.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n03i00378ent IS
END c03s02b01x01p03n03i00378ent;
ARCHITECTURE c03s02b01x01p03n03i00378arch OF c03s02b01x01p03n03i00378ent IS
type M1 is array (positive range <>) of integer;
subtype M2 is M1 (2 to 200); -- No_failure_here
BEGIN
TESTING: PROCESS
variable k : M2;
BEGIN
k(2) := 2;
k(200) := 200;
assert NOT ( k(2) = 2 and
k(200) = 200)
report "***PASSED TEST: c03s02b01x01p03n03i00378"
severity NOTE;
assert ( k(2) = 2 and
k(200) = 200)
report "***FAILED TEST: c03s02b01x01p03n03i00378 - The index constraint must provide a discrete range for each index of the array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n03i00378arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc378.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n03i00378ent IS
END c03s02b01x01p03n03i00378ent;
ARCHITECTURE c03s02b01x01p03n03i00378arch OF c03s02b01x01p03n03i00378ent IS
type M1 is array (positive range <>) of integer;
subtype M2 is M1 (2 to 200); -- No_failure_here
BEGIN
TESTING: PROCESS
variable k : M2;
BEGIN
k(2) := 2;
k(200) := 200;
assert NOT ( k(2) = 2 and
k(200) = 200)
report "***PASSED TEST: c03s02b01x01p03n03i00378"
severity NOTE;
assert ( k(2) = 2 and
k(200) = 200)
report "***FAILED TEST: c03s02b01x01p03n03i00378 - The index constraint must provide a discrete range for each index of the array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n03i00378arch;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core_sv IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core_sv;
ARCHITECTURE gen OF dotp_core_sv IS
COMPONENT dotProduct64_dut is
port (
c_s : in std_logic_vector(7 downto 0);
cout_s : out std_logic_vector(7 downto 0);
datain_a_00 : in std_logic_vector(31 downto 0);
datain_a_01 : in std_logic_vector(31 downto 0);
datain_a_02 : in std_logic_vector(31 downto 0);
datain_a_03 : in std_logic_vector(31 downto 0);
datain_a_04 : in std_logic_vector(31 downto 0);
datain_a_05 : in std_logic_vector(31 downto 0);
datain_a_06 : in std_logic_vector(31 downto 0);
datain_a_07 : in std_logic_vector(31 downto 0);
datain_a_08 : in std_logic_vector(31 downto 0);
datain_a_09 : in std_logic_vector(31 downto 0);
datain_a_10 : in std_logic_vector(31 downto 0);
datain_a_11 : in std_logic_vector(31 downto 0);
datain_a_12 : in std_logic_vector(31 downto 0);
datain_a_13 : in std_logic_vector(31 downto 0);
datain_a_14 : in std_logic_vector(31 downto 0);
datain_a_15 : in std_logic_vector(31 downto 0);
datain_a_16 : in std_logic_vector(31 downto 0);
datain_a_17 : in std_logic_vector(31 downto 0);
datain_a_18 : in std_logic_vector(31 downto 0);
datain_a_19 : in std_logic_vector(31 downto 0);
datain_a_20 : in std_logic_vector(31 downto 0);
datain_a_21 : in std_logic_vector(31 downto 0);
datain_a_22 : in std_logic_vector(31 downto 0);
datain_a_23 : in std_logic_vector(31 downto 0);
datain_a_24 : in std_logic_vector(31 downto 0);
datain_a_25 : in std_logic_vector(31 downto 0);
datain_a_26 : in std_logic_vector(31 downto 0);
datain_a_27 : in std_logic_vector(31 downto 0);
datain_a_28 : in std_logic_vector(31 downto 0);
datain_a_29 : in std_logic_vector(31 downto 0);
datain_a_30 : in std_logic_vector(31 downto 0);
datain_a_31 : in std_logic_vector(31 downto 0);
datain_a_32 : in std_logic_vector(31 downto 0);
datain_a_33 : in std_logic_vector(31 downto 0);
datain_a_34 : in std_logic_vector(31 downto 0);
datain_a_35 : in std_logic_vector(31 downto 0);
datain_a_36 : in std_logic_vector(31 downto 0);
datain_a_37 : in std_logic_vector(31 downto 0);
datain_a_38 : in std_logic_vector(31 downto 0);
datain_a_39 : in std_logic_vector(31 downto 0);
datain_a_40 : in std_logic_vector(31 downto 0);
datain_a_41 : in std_logic_vector(31 downto 0);
datain_a_42 : in std_logic_vector(31 downto 0);
datain_a_43 : in std_logic_vector(31 downto 0);
datain_a_44 : in std_logic_vector(31 downto 0);
datain_a_45 : in std_logic_vector(31 downto 0);
datain_a_46 : in std_logic_vector(31 downto 0);
datain_a_47 : in std_logic_vector(31 downto 0);
datain_a_48 : in std_logic_vector(31 downto 0);
datain_a_49 : in std_logic_vector(31 downto 0);
datain_a_50 : in std_logic_vector(31 downto 0);
datain_a_51 : in std_logic_vector(31 downto 0);
datain_a_52 : in std_logic_vector(31 downto 0);
datain_a_53 : in std_logic_vector(31 downto 0);
datain_a_54 : in std_logic_vector(31 downto 0);
datain_a_55 : in std_logic_vector(31 downto 0);
datain_a_56 : in std_logic_vector(31 downto 0);
datain_a_57 : in std_logic_vector(31 downto 0);
datain_a_58 : in std_logic_vector(31 downto 0);
datain_a_59 : in std_logic_vector(31 downto 0);
datain_a_60 : in std_logic_vector(31 downto 0);
datain_a_61 : in std_logic_vector(31 downto 0);
datain_a_62 : in std_logic_vector(31 downto 0);
datain_a_63 : in std_logic_vector(31 downto 0);
datain_b_00 : in std_logic_vector(31 downto 0);
datain_b_01 : in std_logic_vector(31 downto 0);
datain_b_02 : in std_logic_vector(31 downto 0);
datain_b_03 : in std_logic_vector(31 downto 0);
datain_b_04 : in std_logic_vector(31 downto 0);
datain_b_05 : in std_logic_vector(31 downto 0);
datain_b_06 : in std_logic_vector(31 downto 0);
datain_b_07 : in std_logic_vector(31 downto 0);
datain_b_08 : in std_logic_vector(31 downto 0);
datain_b_09 : in std_logic_vector(31 downto 0);
datain_b_10 : in std_logic_vector(31 downto 0);
datain_b_11 : in std_logic_vector(31 downto 0);
datain_b_12 : in std_logic_vector(31 downto 0);
datain_b_13 : in std_logic_vector(31 downto 0);
datain_b_14 : in std_logic_vector(31 downto 0);
datain_b_15 : in std_logic_vector(31 downto 0);
datain_b_16 : in std_logic_vector(31 downto 0);
datain_b_17 : in std_logic_vector(31 downto 0);
datain_b_18 : in std_logic_vector(31 downto 0);
datain_b_19 : in std_logic_vector(31 downto 0);
datain_b_20 : in std_logic_vector(31 downto 0);
datain_b_21 : in std_logic_vector(31 downto 0);
datain_b_22 : in std_logic_vector(31 downto 0);
datain_b_23 : in std_logic_vector(31 downto 0);
datain_b_24 : in std_logic_vector(31 downto 0);
datain_b_25 : in std_logic_vector(31 downto 0);
datain_b_26 : in std_logic_vector(31 downto 0);
datain_b_27 : in std_logic_vector(31 downto 0);
datain_b_28 : in std_logic_vector(31 downto 0);
datain_b_29 : in std_logic_vector(31 downto 0);
datain_b_30 : in std_logic_vector(31 downto 0);
datain_b_31 : in std_logic_vector(31 downto 0);
datain_b_32 : in std_logic_vector(31 downto 0);
datain_b_33 : in std_logic_vector(31 downto 0);
datain_b_34 : in std_logic_vector(31 downto 0);
datain_b_35 : in std_logic_vector(31 downto 0);
datain_b_36 : in std_logic_vector(31 downto 0);
datain_b_37 : in std_logic_vector(31 downto 0);
datain_b_38 : in std_logic_vector(31 downto 0);
datain_b_39 : in std_logic_vector(31 downto 0);
datain_b_40 : in std_logic_vector(31 downto 0);
datain_b_41 : in std_logic_vector(31 downto 0);
datain_b_42 : in std_logic_vector(31 downto 0);
datain_b_43 : in std_logic_vector(31 downto 0);
datain_b_44 : in std_logic_vector(31 downto 0);
datain_b_45 : in std_logic_vector(31 downto 0);
datain_b_46 : in std_logic_vector(31 downto 0);
datain_b_47 : in std_logic_vector(31 downto 0);
datain_b_48 : in std_logic_vector(31 downto 0);
datain_b_49 : in std_logic_vector(31 downto 0);
datain_b_50 : in std_logic_vector(31 downto 0);
datain_b_51 : in std_logic_vector(31 downto 0);
datain_b_52 : in std_logic_vector(31 downto 0);
datain_b_53 : in std_logic_vector(31 downto 0);
datain_b_54 : in std_logic_vector(31 downto 0);
datain_b_55 : in std_logic_vector(31 downto 0);
datain_b_56 : in std_logic_vector(31 downto 0);
datain_b_57 : in std_logic_vector(31 downto 0);
datain_b_58 : in std_logic_vector(31 downto 0);
datain_b_59 : in std_logic_vector(31 downto 0);
datain_b_60 : in std_logic_vector(31 downto 0);
datain_b_61 : in std_logic_vector(31 downto 0);
datain_b_62 : in std_logic_vector(31 downto 0);
datain_b_63 : in std_logic_vector(31 downto 0);
dout_s : out std_logic_vector(31 downto 0);
v_s : in std_logic_vector(0 downto 0);
vout_s : out std_logic_vector(0 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
SIGNAL v_in : std_logic_vector(0 downto 0);
SIGNAL v_out : std_logic_vector(0 downto 0);
BEGIN
reset <= NOT resetn;
v_in <= "1" when (valid_in = '1') else "0";
cmp0: dotProduct64_dut
PORT MAP (clk=>clock, areset=>reset, h_areset => reset, v_s=>v_in,
vout_s=>v_out, dout_s=>res, c_s => "00000000",
datain_a_00 => a0(32 DOWNTO 1),
datain_b_00 => b0(32 DOWNTO 1),
datain_a_01 => a0(64 DOWNTO 33),
datain_b_01 => b0(64 DOWNTO 33),
datain_a_02 => a0(96 DOWNTO 65),
datain_b_02 => b0(96 DOWNTO 65),
datain_a_03 => a0(128 DOWNTO 97),
datain_b_03 => b0(128 DOWNTO 97),
datain_a_04 => a0(160 DOWNTO 129),
datain_b_04 => b0(160 DOWNTO 129),
datain_a_05 => a0(192 DOWNTO 161),
datain_b_05 => b0(192 DOWNTO 161),
datain_a_06 => a0(224 DOWNTO 193),
datain_b_06 => b0(224 DOWNTO 193),
datain_a_07 => a0(256 DOWNTO 225),
datain_b_07 => b0(256 DOWNTO 225),
datain_a_08 => a0(288 DOWNTO 257),
datain_b_08 => b0(288 DOWNTO 257),
datain_a_09 => a0(320 DOWNTO 289),
datain_b_09 => b0(320 DOWNTO 289),
datain_a_10 => a0(352 DOWNTO 321),
datain_b_10 => b0(352 DOWNTO 321),
datain_a_11 => a0(384 DOWNTO 353),
datain_b_11 => b0(384 DOWNTO 353),
datain_a_12 => a0(416 DOWNTO 385),
datain_b_12 => b0(416 DOWNTO 385),
datain_a_13 => a0(448 DOWNTO 417),
datain_b_13 => b0(448 DOWNTO 417),
datain_a_14 => a0(480 DOWNTO 449),
datain_b_14 => b0(480 DOWNTO 449),
datain_a_15 => a0(512 DOWNTO 481),
datain_b_15 => b0(512 DOWNTO 481),
datain_a_16 => a1(32 DOWNTO 1),
datain_b_16 => b1(32 DOWNTO 1),
datain_a_17 => a1(64 DOWNTO 33),
datain_b_17 => b1(64 DOWNTO 33),
datain_a_18 => a1(96 DOWNTO 65),
datain_b_18 => b1(96 DOWNTO 65),
datain_a_19 => a1(128 DOWNTO 97),
datain_b_19 => b1(128 DOWNTO 97),
datain_a_20 => a1(160 DOWNTO 129),
datain_b_20 => b1(160 DOWNTO 129),
datain_a_21 => a1(192 DOWNTO 161),
datain_b_21 => b1(192 DOWNTO 161),
datain_a_22 => a1(224 DOWNTO 193),
datain_b_22 => b1(224 DOWNTO 193),
datain_a_23 => a1(256 DOWNTO 225),
datain_b_23 => b1(256 DOWNTO 225),
datain_a_24 => a1(288 DOWNTO 257),
datain_b_24 => b1(288 DOWNTO 257),
datain_a_25 => a1(320 DOWNTO 289),
datain_b_25 => b1(320 DOWNTO 289),
datain_a_26 => a1(352 DOWNTO 321),
datain_b_26 => b1(352 DOWNTO 321),
datain_a_27 => a1(384 DOWNTO 353),
datain_b_27 => b1(384 DOWNTO 353),
datain_a_28 => a1(416 DOWNTO 385),
datain_b_28 => b1(416 DOWNTO 385),
datain_a_29 => a1(448 DOWNTO 417),
datain_b_29 => b1(448 DOWNTO 417),
datain_a_30 => a1(480 DOWNTO 449),
datain_b_30 => b1(480 DOWNTO 449),
datain_a_31 => a1(512 DOWNTO 481),
datain_b_31 => b1(512 DOWNTO 481),
datain_a_32 => a2(32 DOWNTO 1),
datain_b_32 => b2(32 DOWNTO 1),
datain_a_33 => a2(64 DOWNTO 33),
datain_b_33 => b2(64 DOWNTO 33),
datain_a_34 => a2(96 DOWNTO 65),
datain_b_34 => b2(96 DOWNTO 65),
datain_a_35 => a2(128 DOWNTO 97),
datain_b_35 => b2(128 DOWNTO 97),
datain_a_36 => a2(160 DOWNTO 129),
datain_b_36 => b2(160 DOWNTO 129),
datain_a_37 => a2(192 DOWNTO 161),
datain_b_37 => b2(192 DOWNTO 161),
datain_a_38 => a2(224 DOWNTO 193),
datain_b_38 => b2(224 DOWNTO 193),
datain_a_39 => a2(256 DOWNTO 225),
datain_b_39 => b2(256 DOWNTO 225),
datain_a_40 => a2(288 DOWNTO 257),
datain_b_40 => b2(288 DOWNTO 257),
datain_a_41 => a2(320 DOWNTO 289),
datain_b_41 => b2(320 DOWNTO 289),
datain_a_42 => a2(352 DOWNTO 321),
datain_b_42 => b2(352 DOWNTO 321),
datain_a_43 => a2(384 DOWNTO 353),
datain_b_43 => b2(384 DOWNTO 353),
datain_a_44 => a2(416 DOWNTO 385),
datain_b_44 => b2(416 DOWNTO 385),
datain_a_45 => a2(448 DOWNTO 417),
datain_b_45 => b2(448 DOWNTO 417),
datain_a_46 => a2(480 DOWNTO 449),
datain_b_46 => b2(480 DOWNTO 449),
datain_a_47 => a2(512 DOWNTO 481),
datain_b_47 => b2(512 DOWNTO 481),
datain_a_48 => a3(32 DOWNTO 1),
datain_b_48 => b3(32 DOWNTO 1),
datain_a_49 => a3(64 DOWNTO 33),
datain_b_49 => b3(64 DOWNTO 33),
datain_a_50 => a3(96 DOWNTO 65),
datain_b_50 => b3(96 DOWNTO 65),
datain_a_51 => a3(128 DOWNTO 97),
datain_b_51 => b3(128 DOWNTO 97),
datain_a_52 => a3(160 DOWNTO 129),
datain_b_52 => b3(160 DOWNTO 129),
datain_a_53 => a3(192 DOWNTO 161),
datain_b_53 => b3(192 DOWNTO 161),
datain_a_54 => a3(224 DOWNTO 193),
datain_b_54 => b3(224 DOWNTO 193),
datain_a_55 => a3(256 DOWNTO 225),
datain_b_55 => b3(256 DOWNTO 225),
datain_a_56 => a3(288 DOWNTO 257),
datain_b_56 => b3(288 DOWNTO 257),
datain_a_57 => a3(320 DOWNTO 289),
datain_b_57 => b3(320 DOWNTO 289),
datain_a_58 => a3(352 DOWNTO 321),
datain_b_58 => b3(352 DOWNTO 321),
datain_a_59 => a3(384 DOWNTO 353),
datain_b_59 => b3(384 DOWNTO 353),
datain_a_60 => a3(416 DOWNTO 385),
datain_b_60 => b3(416 DOWNTO 385),
datain_a_61 => a3(448 DOWNTO 417),
datain_b_61 => b3(448 DOWNTO 417),
datain_a_62 => a3(480 DOWNTO 449),
datain_b_62 => b3(480 DOWNTO 449),
datain_a_63 => a3(512 DOWNTO 481),
datain_b_63 => b3(512 DOWNTO 481));
done <= '1' when (v_out = "1") else '0';
result <= res;
valid_out <= done;
END gen;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core_sv IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core_sv;
ARCHITECTURE gen OF dotp_core_sv IS
COMPONENT dotProduct64_dut is
port (
c_s : in std_logic_vector(7 downto 0);
cout_s : out std_logic_vector(7 downto 0);
datain_a_00 : in std_logic_vector(31 downto 0);
datain_a_01 : in std_logic_vector(31 downto 0);
datain_a_02 : in std_logic_vector(31 downto 0);
datain_a_03 : in std_logic_vector(31 downto 0);
datain_a_04 : in std_logic_vector(31 downto 0);
datain_a_05 : in std_logic_vector(31 downto 0);
datain_a_06 : in std_logic_vector(31 downto 0);
datain_a_07 : in std_logic_vector(31 downto 0);
datain_a_08 : in std_logic_vector(31 downto 0);
datain_a_09 : in std_logic_vector(31 downto 0);
datain_a_10 : in std_logic_vector(31 downto 0);
datain_a_11 : in std_logic_vector(31 downto 0);
datain_a_12 : in std_logic_vector(31 downto 0);
datain_a_13 : in std_logic_vector(31 downto 0);
datain_a_14 : in std_logic_vector(31 downto 0);
datain_a_15 : in std_logic_vector(31 downto 0);
datain_a_16 : in std_logic_vector(31 downto 0);
datain_a_17 : in std_logic_vector(31 downto 0);
datain_a_18 : in std_logic_vector(31 downto 0);
datain_a_19 : in std_logic_vector(31 downto 0);
datain_a_20 : in std_logic_vector(31 downto 0);
datain_a_21 : in std_logic_vector(31 downto 0);
datain_a_22 : in std_logic_vector(31 downto 0);
datain_a_23 : in std_logic_vector(31 downto 0);
datain_a_24 : in std_logic_vector(31 downto 0);
datain_a_25 : in std_logic_vector(31 downto 0);
datain_a_26 : in std_logic_vector(31 downto 0);
datain_a_27 : in std_logic_vector(31 downto 0);
datain_a_28 : in std_logic_vector(31 downto 0);
datain_a_29 : in std_logic_vector(31 downto 0);
datain_a_30 : in std_logic_vector(31 downto 0);
datain_a_31 : in std_logic_vector(31 downto 0);
datain_a_32 : in std_logic_vector(31 downto 0);
datain_a_33 : in std_logic_vector(31 downto 0);
datain_a_34 : in std_logic_vector(31 downto 0);
datain_a_35 : in std_logic_vector(31 downto 0);
datain_a_36 : in std_logic_vector(31 downto 0);
datain_a_37 : in std_logic_vector(31 downto 0);
datain_a_38 : in std_logic_vector(31 downto 0);
datain_a_39 : in std_logic_vector(31 downto 0);
datain_a_40 : in std_logic_vector(31 downto 0);
datain_a_41 : in std_logic_vector(31 downto 0);
datain_a_42 : in std_logic_vector(31 downto 0);
datain_a_43 : in std_logic_vector(31 downto 0);
datain_a_44 : in std_logic_vector(31 downto 0);
datain_a_45 : in std_logic_vector(31 downto 0);
datain_a_46 : in std_logic_vector(31 downto 0);
datain_a_47 : in std_logic_vector(31 downto 0);
datain_a_48 : in std_logic_vector(31 downto 0);
datain_a_49 : in std_logic_vector(31 downto 0);
datain_a_50 : in std_logic_vector(31 downto 0);
datain_a_51 : in std_logic_vector(31 downto 0);
datain_a_52 : in std_logic_vector(31 downto 0);
datain_a_53 : in std_logic_vector(31 downto 0);
datain_a_54 : in std_logic_vector(31 downto 0);
datain_a_55 : in std_logic_vector(31 downto 0);
datain_a_56 : in std_logic_vector(31 downto 0);
datain_a_57 : in std_logic_vector(31 downto 0);
datain_a_58 : in std_logic_vector(31 downto 0);
datain_a_59 : in std_logic_vector(31 downto 0);
datain_a_60 : in std_logic_vector(31 downto 0);
datain_a_61 : in std_logic_vector(31 downto 0);
datain_a_62 : in std_logic_vector(31 downto 0);
datain_a_63 : in std_logic_vector(31 downto 0);
datain_b_00 : in std_logic_vector(31 downto 0);
datain_b_01 : in std_logic_vector(31 downto 0);
datain_b_02 : in std_logic_vector(31 downto 0);
datain_b_03 : in std_logic_vector(31 downto 0);
datain_b_04 : in std_logic_vector(31 downto 0);
datain_b_05 : in std_logic_vector(31 downto 0);
datain_b_06 : in std_logic_vector(31 downto 0);
datain_b_07 : in std_logic_vector(31 downto 0);
datain_b_08 : in std_logic_vector(31 downto 0);
datain_b_09 : in std_logic_vector(31 downto 0);
datain_b_10 : in std_logic_vector(31 downto 0);
datain_b_11 : in std_logic_vector(31 downto 0);
datain_b_12 : in std_logic_vector(31 downto 0);
datain_b_13 : in std_logic_vector(31 downto 0);
datain_b_14 : in std_logic_vector(31 downto 0);
datain_b_15 : in std_logic_vector(31 downto 0);
datain_b_16 : in std_logic_vector(31 downto 0);
datain_b_17 : in std_logic_vector(31 downto 0);
datain_b_18 : in std_logic_vector(31 downto 0);
datain_b_19 : in std_logic_vector(31 downto 0);
datain_b_20 : in std_logic_vector(31 downto 0);
datain_b_21 : in std_logic_vector(31 downto 0);
datain_b_22 : in std_logic_vector(31 downto 0);
datain_b_23 : in std_logic_vector(31 downto 0);
datain_b_24 : in std_logic_vector(31 downto 0);
datain_b_25 : in std_logic_vector(31 downto 0);
datain_b_26 : in std_logic_vector(31 downto 0);
datain_b_27 : in std_logic_vector(31 downto 0);
datain_b_28 : in std_logic_vector(31 downto 0);
datain_b_29 : in std_logic_vector(31 downto 0);
datain_b_30 : in std_logic_vector(31 downto 0);
datain_b_31 : in std_logic_vector(31 downto 0);
datain_b_32 : in std_logic_vector(31 downto 0);
datain_b_33 : in std_logic_vector(31 downto 0);
datain_b_34 : in std_logic_vector(31 downto 0);
datain_b_35 : in std_logic_vector(31 downto 0);
datain_b_36 : in std_logic_vector(31 downto 0);
datain_b_37 : in std_logic_vector(31 downto 0);
datain_b_38 : in std_logic_vector(31 downto 0);
datain_b_39 : in std_logic_vector(31 downto 0);
datain_b_40 : in std_logic_vector(31 downto 0);
datain_b_41 : in std_logic_vector(31 downto 0);
datain_b_42 : in std_logic_vector(31 downto 0);
datain_b_43 : in std_logic_vector(31 downto 0);
datain_b_44 : in std_logic_vector(31 downto 0);
datain_b_45 : in std_logic_vector(31 downto 0);
datain_b_46 : in std_logic_vector(31 downto 0);
datain_b_47 : in std_logic_vector(31 downto 0);
datain_b_48 : in std_logic_vector(31 downto 0);
datain_b_49 : in std_logic_vector(31 downto 0);
datain_b_50 : in std_logic_vector(31 downto 0);
datain_b_51 : in std_logic_vector(31 downto 0);
datain_b_52 : in std_logic_vector(31 downto 0);
datain_b_53 : in std_logic_vector(31 downto 0);
datain_b_54 : in std_logic_vector(31 downto 0);
datain_b_55 : in std_logic_vector(31 downto 0);
datain_b_56 : in std_logic_vector(31 downto 0);
datain_b_57 : in std_logic_vector(31 downto 0);
datain_b_58 : in std_logic_vector(31 downto 0);
datain_b_59 : in std_logic_vector(31 downto 0);
datain_b_60 : in std_logic_vector(31 downto 0);
datain_b_61 : in std_logic_vector(31 downto 0);
datain_b_62 : in std_logic_vector(31 downto 0);
datain_b_63 : in std_logic_vector(31 downto 0);
dout_s : out std_logic_vector(31 downto 0);
v_s : in std_logic_vector(0 downto 0);
vout_s : out std_logic_vector(0 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
SIGNAL v_in : std_logic_vector(0 downto 0);
SIGNAL v_out : std_logic_vector(0 downto 0);
BEGIN
reset <= NOT resetn;
v_in <= "1" when (valid_in = '1') else "0";
cmp0: dotProduct64_dut
PORT MAP (clk=>clock, areset=>reset, h_areset => reset, v_s=>v_in,
vout_s=>v_out, dout_s=>res, c_s => "00000000",
datain_a_00 => a0(32 DOWNTO 1),
datain_b_00 => b0(32 DOWNTO 1),
datain_a_01 => a0(64 DOWNTO 33),
datain_b_01 => b0(64 DOWNTO 33),
datain_a_02 => a0(96 DOWNTO 65),
datain_b_02 => b0(96 DOWNTO 65),
datain_a_03 => a0(128 DOWNTO 97),
datain_b_03 => b0(128 DOWNTO 97),
datain_a_04 => a0(160 DOWNTO 129),
datain_b_04 => b0(160 DOWNTO 129),
datain_a_05 => a0(192 DOWNTO 161),
datain_b_05 => b0(192 DOWNTO 161),
datain_a_06 => a0(224 DOWNTO 193),
datain_b_06 => b0(224 DOWNTO 193),
datain_a_07 => a0(256 DOWNTO 225),
datain_b_07 => b0(256 DOWNTO 225),
datain_a_08 => a0(288 DOWNTO 257),
datain_b_08 => b0(288 DOWNTO 257),
datain_a_09 => a0(320 DOWNTO 289),
datain_b_09 => b0(320 DOWNTO 289),
datain_a_10 => a0(352 DOWNTO 321),
datain_b_10 => b0(352 DOWNTO 321),
datain_a_11 => a0(384 DOWNTO 353),
datain_b_11 => b0(384 DOWNTO 353),
datain_a_12 => a0(416 DOWNTO 385),
datain_b_12 => b0(416 DOWNTO 385),
datain_a_13 => a0(448 DOWNTO 417),
datain_b_13 => b0(448 DOWNTO 417),
datain_a_14 => a0(480 DOWNTO 449),
datain_b_14 => b0(480 DOWNTO 449),
datain_a_15 => a0(512 DOWNTO 481),
datain_b_15 => b0(512 DOWNTO 481),
datain_a_16 => a1(32 DOWNTO 1),
datain_b_16 => b1(32 DOWNTO 1),
datain_a_17 => a1(64 DOWNTO 33),
datain_b_17 => b1(64 DOWNTO 33),
datain_a_18 => a1(96 DOWNTO 65),
datain_b_18 => b1(96 DOWNTO 65),
datain_a_19 => a1(128 DOWNTO 97),
datain_b_19 => b1(128 DOWNTO 97),
datain_a_20 => a1(160 DOWNTO 129),
datain_b_20 => b1(160 DOWNTO 129),
datain_a_21 => a1(192 DOWNTO 161),
datain_b_21 => b1(192 DOWNTO 161),
datain_a_22 => a1(224 DOWNTO 193),
datain_b_22 => b1(224 DOWNTO 193),
datain_a_23 => a1(256 DOWNTO 225),
datain_b_23 => b1(256 DOWNTO 225),
datain_a_24 => a1(288 DOWNTO 257),
datain_b_24 => b1(288 DOWNTO 257),
datain_a_25 => a1(320 DOWNTO 289),
datain_b_25 => b1(320 DOWNTO 289),
datain_a_26 => a1(352 DOWNTO 321),
datain_b_26 => b1(352 DOWNTO 321),
datain_a_27 => a1(384 DOWNTO 353),
datain_b_27 => b1(384 DOWNTO 353),
datain_a_28 => a1(416 DOWNTO 385),
datain_b_28 => b1(416 DOWNTO 385),
datain_a_29 => a1(448 DOWNTO 417),
datain_b_29 => b1(448 DOWNTO 417),
datain_a_30 => a1(480 DOWNTO 449),
datain_b_30 => b1(480 DOWNTO 449),
datain_a_31 => a1(512 DOWNTO 481),
datain_b_31 => b1(512 DOWNTO 481),
datain_a_32 => a2(32 DOWNTO 1),
datain_b_32 => b2(32 DOWNTO 1),
datain_a_33 => a2(64 DOWNTO 33),
datain_b_33 => b2(64 DOWNTO 33),
datain_a_34 => a2(96 DOWNTO 65),
datain_b_34 => b2(96 DOWNTO 65),
datain_a_35 => a2(128 DOWNTO 97),
datain_b_35 => b2(128 DOWNTO 97),
datain_a_36 => a2(160 DOWNTO 129),
datain_b_36 => b2(160 DOWNTO 129),
datain_a_37 => a2(192 DOWNTO 161),
datain_b_37 => b2(192 DOWNTO 161),
datain_a_38 => a2(224 DOWNTO 193),
datain_b_38 => b2(224 DOWNTO 193),
datain_a_39 => a2(256 DOWNTO 225),
datain_b_39 => b2(256 DOWNTO 225),
datain_a_40 => a2(288 DOWNTO 257),
datain_b_40 => b2(288 DOWNTO 257),
datain_a_41 => a2(320 DOWNTO 289),
datain_b_41 => b2(320 DOWNTO 289),
datain_a_42 => a2(352 DOWNTO 321),
datain_b_42 => b2(352 DOWNTO 321),
datain_a_43 => a2(384 DOWNTO 353),
datain_b_43 => b2(384 DOWNTO 353),
datain_a_44 => a2(416 DOWNTO 385),
datain_b_44 => b2(416 DOWNTO 385),
datain_a_45 => a2(448 DOWNTO 417),
datain_b_45 => b2(448 DOWNTO 417),
datain_a_46 => a2(480 DOWNTO 449),
datain_b_46 => b2(480 DOWNTO 449),
datain_a_47 => a2(512 DOWNTO 481),
datain_b_47 => b2(512 DOWNTO 481),
datain_a_48 => a3(32 DOWNTO 1),
datain_b_48 => b3(32 DOWNTO 1),
datain_a_49 => a3(64 DOWNTO 33),
datain_b_49 => b3(64 DOWNTO 33),
datain_a_50 => a3(96 DOWNTO 65),
datain_b_50 => b3(96 DOWNTO 65),
datain_a_51 => a3(128 DOWNTO 97),
datain_b_51 => b3(128 DOWNTO 97),
datain_a_52 => a3(160 DOWNTO 129),
datain_b_52 => b3(160 DOWNTO 129),
datain_a_53 => a3(192 DOWNTO 161),
datain_b_53 => b3(192 DOWNTO 161),
datain_a_54 => a3(224 DOWNTO 193),
datain_b_54 => b3(224 DOWNTO 193),
datain_a_55 => a3(256 DOWNTO 225),
datain_b_55 => b3(256 DOWNTO 225),
datain_a_56 => a3(288 DOWNTO 257),
datain_b_56 => b3(288 DOWNTO 257),
datain_a_57 => a3(320 DOWNTO 289),
datain_b_57 => b3(320 DOWNTO 289),
datain_a_58 => a3(352 DOWNTO 321),
datain_b_58 => b3(352 DOWNTO 321),
datain_a_59 => a3(384 DOWNTO 353),
datain_b_59 => b3(384 DOWNTO 353),
datain_a_60 => a3(416 DOWNTO 385),
datain_b_60 => b3(416 DOWNTO 385),
datain_a_61 => a3(448 DOWNTO 417),
datain_b_61 => b3(448 DOWNTO 417),
datain_a_62 => a3(480 DOWNTO 449),
datain_b_62 => b3(480 DOWNTO 449),
datain_a_63 => a3(512 DOWNTO 481),
datain_b_63 => b3(512 DOWNTO 481));
done <= '1' when (v_out = "1") else '0';
result <= res;
valid_out <= done;
END gen;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core_sv IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core_sv;
ARCHITECTURE gen OF dotp_core_sv IS
COMPONENT dotProduct64_dut is
port (
c_s : in std_logic_vector(7 downto 0);
cout_s : out std_logic_vector(7 downto 0);
datain_a_00 : in std_logic_vector(31 downto 0);
datain_a_01 : in std_logic_vector(31 downto 0);
datain_a_02 : in std_logic_vector(31 downto 0);
datain_a_03 : in std_logic_vector(31 downto 0);
datain_a_04 : in std_logic_vector(31 downto 0);
datain_a_05 : in std_logic_vector(31 downto 0);
datain_a_06 : in std_logic_vector(31 downto 0);
datain_a_07 : in std_logic_vector(31 downto 0);
datain_a_08 : in std_logic_vector(31 downto 0);
datain_a_09 : in std_logic_vector(31 downto 0);
datain_a_10 : in std_logic_vector(31 downto 0);
datain_a_11 : in std_logic_vector(31 downto 0);
datain_a_12 : in std_logic_vector(31 downto 0);
datain_a_13 : in std_logic_vector(31 downto 0);
datain_a_14 : in std_logic_vector(31 downto 0);
datain_a_15 : in std_logic_vector(31 downto 0);
datain_a_16 : in std_logic_vector(31 downto 0);
datain_a_17 : in std_logic_vector(31 downto 0);
datain_a_18 : in std_logic_vector(31 downto 0);
datain_a_19 : in std_logic_vector(31 downto 0);
datain_a_20 : in std_logic_vector(31 downto 0);
datain_a_21 : in std_logic_vector(31 downto 0);
datain_a_22 : in std_logic_vector(31 downto 0);
datain_a_23 : in std_logic_vector(31 downto 0);
datain_a_24 : in std_logic_vector(31 downto 0);
datain_a_25 : in std_logic_vector(31 downto 0);
datain_a_26 : in std_logic_vector(31 downto 0);
datain_a_27 : in std_logic_vector(31 downto 0);
datain_a_28 : in std_logic_vector(31 downto 0);
datain_a_29 : in std_logic_vector(31 downto 0);
datain_a_30 : in std_logic_vector(31 downto 0);
datain_a_31 : in std_logic_vector(31 downto 0);
datain_a_32 : in std_logic_vector(31 downto 0);
datain_a_33 : in std_logic_vector(31 downto 0);
datain_a_34 : in std_logic_vector(31 downto 0);
datain_a_35 : in std_logic_vector(31 downto 0);
datain_a_36 : in std_logic_vector(31 downto 0);
datain_a_37 : in std_logic_vector(31 downto 0);
datain_a_38 : in std_logic_vector(31 downto 0);
datain_a_39 : in std_logic_vector(31 downto 0);
datain_a_40 : in std_logic_vector(31 downto 0);
datain_a_41 : in std_logic_vector(31 downto 0);
datain_a_42 : in std_logic_vector(31 downto 0);
datain_a_43 : in std_logic_vector(31 downto 0);
datain_a_44 : in std_logic_vector(31 downto 0);
datain_a_45 : in std_logic_vector(31 downto 0);
datain_a_46 : in std_logic_vector(31 downto 0);
datain_a_47 : in std_logic_vector(31 downto 0);
datain_a_48 : in std_logic_vector(31 downto 0);
datain_a_49 : in std_logic_vector(31 downto 0);
datain_a_50 : in std_logic_vector(31 downto 0);
datain_a_51 : in std_logic_vector(31 downto 0);
datain_a_52 : in std_logic_vector(31 downto 0);
datain_a_53 : in std_logic_vector(31 downto 0);
datain_a_54 : in std_logic_vector(31 downto 0);
datain_a_55 : in std_logic_vector(31 downto 0);
datain_a_56 : in std_logic_vector(31 downto 0);
datain_a_57 : in std_logic_vector(31 downto 0);
datain_a_58 : in std_logic_vector(31 downto 0);
datain_a_59 : in std_logic_vector(31 downto 0);
datain_a_60 : in std_logic_vector(31 downto 0);
datain_a_61 : in std_logic_vector(31 downto 0);
datain_a_62 : in std_logic_vector(31 downto 0);
datain_a_63 : in std_logic_vector(31 downto 0);
datain_b_00 : in std_logic_vector(31 downto 0);
datain_b_01 : in std_logic_vector(31 downto 0);
datain_b_02 : in std_logic_vector(31 downto 0);
datain_b_03 : in std_logic_vector(31 downto 0);
datain_b_04 : in std_logic_vector(31 downto 0);
datain_b_05 : in std_logic_vector(31 downto 0);
datain_b_06 : in std_logic_vector(31 downto 0);
datain_b_07 : in std_logic_vector(31 downto 0);
datain_b_08 : in std_logic_vector(31 downto 0);
datain_b_09 : in std_logic_vector(31 downto 0);
datain_b_10 : in std_logic_vector(31 downto 0);
datain_b_11 : in std_logic_vector(31 downto 0);
datain_b_12 : in std_logic_vector(31 downto 0);
datain_b_13 : in std_logic_vector(31 downto 0);
datain_b_14 : in std_logic_vector(31 downto 0);
datain_b_15 : in std_logic_vector(31 downto 0);
datain_b_16 : in std_logic_vector(31 downto 0);
datain_b_17 : in std_logic_vector(31 downto 0);
datain_b_18 : in std_logic_vector(31 downto 0);
datain_b_19 : in std_logic_vector(31 downto 0);
datain_b_20 : in std_logic_vector(31 downto 0);
datain_b_21 : in std_logic_vector(31 downto 0);
datain_b_22 : in std_logic_vector(31 downto 0);
datain_b_23 : in std_logic_vector(31 downto 0);
datain_b_24 : in std_logic_vector(31 downto 0);
datain_b_25 : in std_logic_vector(31 downto 0);
datain_b_26 : in std_logic_vector(31 downto 0);
datain_b_27 : in std_logic_vector(31 downto 0);
datain_b_28 : in std_logic_vector(31 downto 0);
datain_b_29 : in std_logic_vector(31 downto 0);
datain_b_30 : in std_logic_vector(31 downto 0);
datain_b_31 : in std_logic_vector(31 downto 0);
datain_b_32 : in std_logic_vector(31 downto 0);
datain_b_33 : in std_logic_vector(31 downto 0);
datain_b_34 : in std_logic_vector(31 downto 0);
datain_b_35 : in std_logic_vector(31 downto 0);
datain_b_36 : in std_logic_vector(31 downto 0);
datain_b_37 : in std_logic_vector(31 downto 0);
datain_b_38 : in std_logic_vector(31 downto 0);
datain_b_39 : in std_logic_vector(31 downto 0);
datain_b_40 : in std_logic_vector(31 downto 0);
datain_b_41 : in std_logic_vector(31 downto 0);
datain_b_42 : in std_logic_vector(31 downto 0);
datain_b_43 : in std_logic_vector(31 downto 0);
datain_b_44 : in std_logic_vector(31 downto 0);
datain_b_45 : in std_logic_vector(31 downto 0);
datain_b_46 : in std_logic_vector(31 downto 0);
datain_b_47 : in std_logic_vector(31 downto 0);
datain_b_48 : in std_logic_vector(31 downto 0);
datain_b_49 : in std_logic_vector(31 downto 0);
datain_b_50 : in std_logic_vector(31 downto 0);
datain_b_51 : in std_logic_vector(31 downto 0);
datain_b_52 : in std_logic_vector(31 downto 0);
datain_b_53 : in std_logic_vector(31 downto 0);
datain_b_54 : in std_logic_vector(31 downto 0);
datain_b_55 : in std_logic_vector(31 downto 0);
datain_b_56 : in std_logic_vector(31 downto 0);
datain_b_57 : in std_logic_vector(31 downto 0);
datain_b_58 : in std_logic_vector(31 downto 0);
datain_b_59 : in std_logic_vector(31 downto 0);
datain_b_60 : in std_logic_vector(31 downto 0);
datain_b_61 : in std_logic_vector(31 downto 0);
datain_b_62 : in std_logic_vector(31 downto 0);
datain_b_63 : in std_logic_vector(31 downto 0);
dout_s : out std_logic_vector(31 downto 0);
v_s : in std_logic_vector(0 downto 0);
vout_s : out std_logic_vector(0 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
SIGNAL v_in : std_logic_vector(0 downto 0);
SIGNAL v_out : std_logic_vector(0 downto 0);
BEGIN
reset <= NOT resetn;
v_in <= "1" when (valid_in = '1') else "0";
cmp0: dotProduct64_dut
PORT MAP (clk=>clock, areset=>reset, h_areset => reset, v_s=>v_in,
vout_s=>v_out, dout_s=>res, c_s => "00000000",
datain_a_00 => a0(32 DOWNTO 1),
datain_b_00 => b0(32 DOWNTO 1),
datain_a_01 => a0(64 DOWNTO 33),
datain_b_01 => b0(64 DOWNTO 33),
datain_a_02 => a0(96 DOWNTO 65),
datain_b_02 => b0(96 DOWNTO 65),
datain_a_03 => a0(128 DOWNTO 97),
datain_b_03 => b0(128 DOWNTO 97),
datain_a_04 => a0(160 DOWNTO 129),
datain_b_04 => b0(160 DOWNTO 129),
datain_a_05 => a0(192 DOWNTO 161),
datain_b_05 => b0(192 DOWNTO 161),
datain_a_06 => a0(224 DOWNTO 193),
datain_b_06 => b0(224 DOWNTO 193),
datain_a_07 => a0(256 DOWNTO 225),
datain_b_07 => b0(256 DOWNTO 225),
datain_a_08 => a0(288 DOWNTO 257),
datain_b_08 => b0(288 DOWNTO 257),
datain_a_09 => a0(320 DOWNTO 289),
datain_b_09 => b0(320 DOWNTO 289),
datain_a_10 => a0(352 DOWNTO 321),
datain_b_10 => b0(352 DOWNTO 321),
datain_a_11 => a0(384 DOWNTO 353),
datain_b_11 => b0(384 DOWNTO 353),
datain_a_12 => a0(416 DOWNTO 385),
datain_b_12 => b0(416 DOWNTO 385),
datain_a_13 => a0(448 DOWNTO 417),
datain_b_13 => b0(448 DOWNTO 417),
datain_a_14 => a0(480 DOWNTO 449),
datain_b_14 => b0(480 DOWNTO 449),
datain_a_15 => a0(512 DOWNTO 481),
datain_b_15 => b0(512 DOWNTO 481),
datain_a_16 => a1(32 DOWNTO 1),
datain_b_16 => b1(32 DOWNTO 1),
datain_a_17 => a1(64 DOWNTO 33),
datain_b_17 => b1(64 DOWNTO 33),
datain_a_18 => a1(96 DOWNTO 65),
datain_b_18 => b1(96 DOWNTO 65),
datain_a_19 => a1(128 DOWNTO 97),
datain_b_19 => b1(128 DOWNTO 97),
datain_a_20 => a1(160 DOWNTO 129),
datain_b_20 => b1(160 DOWNTO 129),
datain_a_21 => a1(192 DOWNTO 161),
datain_b_21 => b1(192 DOWNTO 161),
datain_a_22 => a1(224 DOWNTO 193),
datain_b_22 => b1(224 DOWNTO 193),
datain_a_23 => a1(256 DOWNTO 225),
datain_b_23 => b1(256 DOWNTO 225),
datain_a_24 => a1(288 DOWNTO 257),
datain_b_24 => b1(288 DOWNTO 257),
datain_a_25 => a1(320 DOWNTO 289),
datain_b_25 => b1(320 DOWNTO 289),
datain_a_26 => a1(352 DOWNTO 321),
datain_b_26 => b1(352 DOWNTO 321),
datain_a_27 => a1(384 DOWNTO 353),
datain_b_27 => b1(384 DOWNTO 353),
datain_a_28 => a1(416 DOWNTO 385),
datain_b_28 => b1(416 DOWNTO 385),
datain_a_29 => a1(448 DOWNTO 417),
datain_b_29 => b1(448 DOWNTO 417),
datain_a_30 => a1(480 DOWNTO 449),
datain_b_30 => b1(480 DOWNTO 449),
datain_a_31 => a1(512 DOWNTO 481),
datain_b_31 => b1(512 DOWNTO 481),
datain_a_32 => a2(32 DOWNTO 1),
datain_b_32 => b2(32 DOWNTO 1),
datain_a_33 => a2(64 DOWNTO 33),
datain_b_33 => b2(64 DOWNTO 33),
datain_a_34 => a2(96 DOWNTO 65),
datain_b_34 => b2(96 DOWNTO 65),
datain_a_35 => a2(128 DOWNTO 97),
datain_b_35 => b2(128 DOWNTO 97),
datain_a_36 => a2(160 DOWNTO 129),
datain_b_36 => b2(160 DOWNTO 129),
datain_a_37 => a2(192 DOWNTO 161),
datain_b_37 => b2(192 DOWNTO 161),
datain_a_38 => a2(224 DOWNTO 193),
datain_b_38 => b2(224 DOWNTO 193),
datain_a_39 => a2(256 DOWNTO 225),
datain_b_39 => b2(256 DOWNTO 225),
datain_a_40 => a2(288 DOWNTO 257),
datain_b_40 => b2(288 DOWNTO 257),
datain_a_41 => a2(320 DOWNTO 289),
datain_b_41 => b2(320 DOWNTO 289),
datain_a_42 => a2(352 DOWNTO 321),
datain_b_42 => b2(352 DOWNTO 321),
datain_a_43 => a2(384 DOWNTO 353),
datain_b_43 => b2(384 DOWNTO 353),
datain_a_44 => a2(416 DOWNTO 385),
datain_b_44 => b2(416 DOWNTO 385),
datain_a_45 => a2(448 DOWNTO 417),
datain_b_45 => b2(448 DOWNTO 417),
datain_a_46 => a2(480 DOWNTO 449),
datain_b_46 => b2(480 DOWNTO 449),
datain_a_47 => a2(512 DOWNTO 481),
datain_b_47 => b2(512 DOWNTO 481),
datain_a_48 => a3(32 DOWNTO 1),
datain_b_48 => b3(32 DOWNTO 1),
datain_a_49 => a3(64 DOWNTO 33),
datain_b_49 => b3(64 DOWNTO 33),
datain_a_50 => a3(96 DOWNTO 65),
datain_b_50 => b3(96 DOWNTO 65),
datain_a_51 => a3(128 DOWNTO 97),
datain_b_51 => b3(128 DOWNTO 97),
datain_a_52 => a3(160 DOWNTO 129),
datain_b_52 => b3(160 DOWNTO 129),
datain_a_53 => a3(192 DOWNTO 161),
datain_b_53 => b3(192 DOWNTO 161),
datain_a_54 => a3(224 DOWNTO 193),
datain_b_54 => b3(224 DOWNTO 193),
datain_a_55 => a3(256 DOWNTO 225),
datain_b_55 => b3(256 DOWNTO 225),
datain_a_56 => a3(288 DOWNTO 257),
datain_b_56 => b3(288 DOWNTO 257),
datain_a_57 => a3(320 DOWNTO 289),
datain_b_57 => b3(320 DOWNTO 289),
datain_a_58 => a3(352 DOWNTO 321),
datain_b_58 => b3(352 DOWNTO 321),
datain_a_59 => a3(384 DOWNTO 353),
datain_b_59 => b3(384 DOWNTO 353),
datain_a_60 => a3(416 DOWNTO 385),
datain_b_60 => b3(416 DOWNTO 385),
datain_a_61 => a3(448 DOWNTO 417),
datain_b_61 => b3(448 DOWNTO 417),
datain_a_62 => a3(480 DOWNTO 449),
datain_b_62 => b3(480 DOWNTO 449),
datain_a_63 => a3(512 DOWNTO 481),
datain_b_63 => b3(512 DOWNTO 481));
done <= '1' when (v_out = "1") else '0';
result <= res;
valid_out <= done;
END gen;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core_sv IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core_sv;
ARCHITECTURE gen OF dotp_core_sv IS
COMPONENT dotProduct64_dut is
port (
c_s : in std_logic_vector(7 downto 0);
cout_s : out std_logic_vector(7 downto 0);
datain_a_00 : in std_logic_vector(31 downto 0);
datain_a_01 : in std_logic_vector(31 downto 0);
datain_a_02 : in std_logic_vector(31 downto 0);
datain_a_03 : in std_logic_vector(31 downto 0);
datain_a_04 : in std_logic_vector(31 downto 0);
datain_a_05 : in std_logic_vector(31 downto 0);
datain_a_06 : in std_logic_vector(31 downto 0);
datain_a_07 : in std_logic_vector(31 downto 0);
datain_a_08 : in std_logic_vector(31 downto 0);
datain_a_09 : in std_logic_vector(31 downto 0);
datain_a_10 : in std_logic_vector(31 downto 0);
datain_a_11 : in std_logic_vector(31 downto 0);
datain_a_12 : in std_logic_vector(31 downto 0);
datain_a_13 : in std_logic_vector(31 downto 0);
datain_a_14 : in std_logic_vector(31 downto 0);
datain_a_15 : in std_logic_vector(31 downto 0);
datain_a_16 : in std_logic_vector(31 downto 0);
datain_a_17 : in std_logic_vector(31 downto 0);
datain_a_18 : in std_logic_vector(31 downto 0);
datain_a_19 : in std_logic_vector(31 downto 0);
datain_a_20 : in std_logic_vector(31 downto 0);
datain_a_21 : in std_logic_vector(31 downto 0);
datain_a_22 : in std_logic_vector(31 downto 0);
datain_a_23 : in std_logic_vector(31 downto 0);
datain_a_24 : in std_logic_vector(31 downto 0);
datain_a_25 : in std_logic_vector(31 downto 0);
datain_a_26 : in std_logic_vector(31 downto 0);
datain_a_27 : in std_logic_vector(31 downto 0);
datain_a_28 : in std_logic_vector(31 downto 0);
datain_a_29 : in std_logic_vector(31 downto 0);
datain_a_30 : in std_logic_vector(31 downto 0);
datain_a_31 : in std_logic_vector(31 downto 0);
datain_a_32 : in std_logic_vector(31 downto 0);
datain_a_33 : in std_logic_vector(31 downto 0);
datain_a_34 : in std_logic_vector(31 downto 0);
datain_a_35 : in std_logic_vector(31 downto 0);
datain_a_36 : in std_logic_vector(31 downto 0);
datain_a_37 : in std_logic_vector(31 downto 0);
datain_a_38 : in std_logic_vector(31 downto 0);
datain_a_39 : in std_logic_vector(31 downto 0);
datain_a_40 : in std_logic_vector(31 downto 0);
datain_a_41 : in std_logic_vector(31 downto 0);
datain_a_42 : in std_logic_vector(31 downto 0);
datain_a_43 : in std_logic_vector(31 downto 0);
datain_a_44 : in std_logic_vector(31 downto 0);
datain_a_45 : in std_logic_vector(31 downto 0);
datain_a_46 : in std_logic_vector(31 downto 0);
datain_a_47 : in std_logic_vector(31 downto 0);
datain_a_48 : in std_logic_vector(31 downto 0);
datain_a_49 : in std_logic_vector(31 downto 0);
datain_a_50 : in std_logic_vector(31 downto 0);
datain_a_51 : in std_logic_vector(31 downto 0);
datain_a_52 : in std_logic_vector(31 downto 0);
datain_a_53 : in std_logic_vector(31 downto 0);
datain_a_54 : in std_logic_vector(31 downto 0);
datain_a_55 : in std_logic_vector(31 downto 0);
datain_a_56 : in std_logic_vector(31 downto 0);
datain_a_57 : in std_logic_vector(31 downto 0);
datain_a_58 : in std_logic_vector(31 downto 0);
datain_a_59 : in std_logic_vector(31 downto 0);
datain_a_60 : in std_logic_vector(31 downto 0);
datain_a_61 : in std_logic_vector(31 downto 0);
datain_a_62 : in std_logic_vector(31 downto 0);
datain_a_63 : in std_logic_vector(31 downto 0);
datain_b_00 : in std_logic_vector(31 downto 0);
datain_b_01 : in std_logic_vector(31 downto 0);
datain_b_02 : in std_logic_vector(31 downto 0);
datain_b_03 : in std_logic_vector(31 downto 0);
datain_b_04 : in std_logic_vector(31 downto 0);
datain_b_05 : in std_logic_vector(31 downto 0);
datain_b_06 : in std_logic_vector(31 downto 0);
datain_b_07 : in std_logic_vector(31 downto 0);
datain_b_08 : in std_logic_vector(31 downto 0);
datain_b_09 : in std_logic_vector(31 downto 0);
datain_b_10 : in std_logic_vector(31 downto 0);
datain_b_11 : in std_logic_vector(31 downto 0);
datain_b_12 : in std_logic_vector(31 downto 0);
datain_b_13 : in std_logic_vector(31 downto 0);
datain_b_14 : in std_logic_vector(31 downto 0);
datain_b_15 : in std_logic_vector(31 downto 0);
datain_b_16 : in std_logic_vector(31 downto 0);
datain_b_17 : in std_logic_vector(31 downto 0);
datain_b_18 : in std_logic_vector(31 downto 0);
datain_b_19 : in std_logic_vector(31 downto 0);
datain_b_20 : in std_logic_vector(31 downto 0);
datain_b_21 : in std_logic_vector(31 downto 0);
datain_b_22 : in std_logic_vector(31 downto 0);
datain_b_23 : in std_logic_vector(31 downto 0);
datain_b_24 : in std_logic_vector(31 downto 0);
datain_b_25 : in std_logic_vector(31 downto 0);
datain_b_26 : in std_logic_vector(31 downto 0);
datain_b_27 : in std_logic_vector(31 downto 0);
datain_b_28 : in std_logic_vector(31 downto 0);
datain_b_29 : in std_logic_vector(31 downto 0);
datain_b_30 : in std_logic_vector(31 downto 0);
datain_b_31 : in std_logic_vector(31 downto 0);
datain_b_32 : in std_logic_vector(31 downto 0);
datain_b_33 : in std_logic_vector(31 downto 0);
datain_b_34 : in std_logic_vector(31 downto 0);
datain_b_35 : in std_logic_vector(31 downto 0);
datain_b_36 : in std_logic_vector(31 downto 0);
datain_b_37 : in std_logic_vector(31 downto 0);
datain_b_38 : in std_logic_vector(31 downto 0);
datain_b_39 : in std_logic_vector(31 downto 0);
datain_b_40 : in std_logic_vector(31 downto 0);
datain_b_41 : in std_logic_vector(31 downto 0);
datain_b_42 : in std_logic_vector(31 downto 0);
datain_b_43 : in std_logic_vector(31 downto 0);
datain_b_44 : in std_logic_vector(31 downto 0);
datain_b_45 : in std_logic_vector(31 downto 0);
datain_b_46 : in std_logic_vector(31 downto 0);
datain_b_47 : in std_logic_vector(31 downto 0);
datain_b_48 : in std_logic_vector(31 downto 0);
datain_b_49 : in std_logic_vector(31 downto 0);
datain_b_50 : in std_logic_vector(31 downto 0);
datain_b_51 : in std_logic_vector(31 downto 0);
datain_b_52 : in std_logic_vector(31 downto 0);
datain_b_53 : in std_logic_vector(31 downto 0);
datain_b_54 : in std_logic_vector(31 downto 0);
datain_b_55 : in std_logic_vector(31 downto 0);
datain_b_56 : in std_logic_vector(31 downto 0);
datain_b_57 : in std_logic_vector(31 downto 0);
datain_b_58 : in std_logic_vector(31 downto 0);
datain_b_59 : in std_logic_vector(31 downto 0);
datain_b_60 : in std_logic_vector(31 downto 0);
datain_b_61 : in std_logic_vector(31 downto 0);
datain_b_62 : in std_logic_vector(31 downto 0);
datain_b_63 : in std_logic_vector(31 downto 0);
dout_s : out std_logic_vector(31 downto 0);
v_s : in std_logic_vector(0 downto 0);
vout_s : out std_logic_vector(0 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
SIGNAL v_in : std_logic_vector(0 downto 0);
SIGNAL v_out : std_logic_vector(0 downto 0);
BEGIN
reset <= NOT resetn;
v_in <= "1" when (valid_in = '1') else "0";
cmp0: dotProduct64_dut
PORT MAP (clk=>clock, areset=>reset, h_areset => reset, v_s=>v_in,
vout_s=>v_out, dout_s=>res, c_s => "00000000",
datain_a_00 => a0(32 DOWNTO 1),
datain_b_00 => b0(32 DOWNTO 1),
datain_a_01 => a0(64 DOWNTO 33),
datain_b_01 => b0(64 DOWNTO 33),
datain_a_02 => a0(96 DOWNTO 65),
datain_b_02 => b0(96 DOWNTO 65),
datain_a_03 => a0(128 DOWNTO 97),
datain_b_03 => b0(128 DOWNTO 97),
datain_a_04 => a0(160 DOWNTO 129),
datain_b_04 => b0(160 DOWNTO 129),
datain_a_05 => a0(192 DOWNTO 161),
datain_b_05 => b0(192 DOWNTO 161),
datain_a_06 => a0(224 DOWNTO 193),
datain_b_06 => b0(224 DOWNTO 193),
datain_a_07 => a0(256 DOWNTO 225),
datain_b_07 => b0(256 DOWNTO 225),
datain_a_08 => a0(288 DOWNTO 257),
datain_b_08 => b0(288 DOWNTO 257),
datain_a_09 => a0(320 DOWNTO 289),
datain_b_09 => b0(320 DOWNTO 289),
datain_a_10 => a0(352 DOWNTO 321),
datain_b_10 => b0(352 DOWNTO 321),
datain_a_11 => a0(384 DOWNTO 353),
datain_b_11 => b0(384 DOWNTO 353),
datain_a_12 => a0(416 DOWNTO 385),
datain_b_12 => b0(416 DOWNTO 385),
datain_a_13 => a0(448 DOWNTO 417),
datain_b_13 => b0(448 DOWNTO 417),
datain_a_14 => a0(480 DOWNTO 449),
datain_b_14 => b0(480 DOWNTO 449),
datain_a_15 => a0(512 DOWNTO 481),
datain_b_15 => b0(512 DOWNTO 481),
datain_a_16 => a1(32 DOWNTO 1),
datain_b_16 => b1(32 DOWNTO 1),
datain_a_17 => a1(64 DOWNTO 33),
datain_b_17 => b1(64 DOWNTO 33),
datain_a_18 => a1(96 DOWNTO 65),
datain_b_18 => b1(96 DOWNTO 65),
datain_a_19 => a1(128 DOWNTO 97),
datain_b_19 => b1(128 DOWNTO 97),
datain_a_20 => a1(160 DOWNTO 129),
datain_b_20 => b1(160 DOWNTO 129),
datain_a_21 => a1(192 DOWNTO 161),
datain_b_21 => b1(192 DOWNTO 161),
datain_a_22 => a1(224 DOWNTO 193),
datain_b_22 => b1(224 DOWNTO 193),
datain_a_23 => a1(256 DOWNTO 225),
datain_b_23 => b1(256 DOWNTO 225),
datain_a_24 => a1(288 DOWNTO 257),
datain_b_24 => b1(288 DOWNTO 257),
datain_a_25 => a1(320 DOWNTO 289),
datain_b_25 => b1(320 DOWNTO 289),
datain_a_26 => a1(352 DOWNTO 321),
datain_b_26 => b1(352 DOWNTO 321),
datain_a_27 => a1(384 DOWNTO 353),
datain_b_27 => b1(384 DOWNTO 353),
datain_a_28 => a1(416 DOWNTO 385),
datain_b_28 => b1(416 DOWNTO 385),
datain_a_29 => a1(448 DOWNTO 417),
datain_b_29 => b1(448 DOWNTO 417),
datain_a_30 => a1(480 DOWNTO 449),
datain_b_30 => b1(480 DOWNTO 449),
datain_a_31 => a1(512 DOWNTO 481),
datain_b_31 => b1(512 DOWNTO 481),
datain_a_32 => a2(32 DOWNTO 1),
datain_b_32 => b2(32 DOWNTO 1),
datain_a_33 => a2(64 DOWNTO 33),
datain_b_33 => b2(64 DOWNTO 33),
datain_a_34 => a2(96 DOWNTO 65),
datain_b_34 => b2(96 DOWNTO 65),
datain_a_35 => a2(128 DOWNTO 97),
datain_b_35 => b2(128 DOWNTO 97),
datain_a_36 => a2(160 DOWNTO 129),
datain_b_36 => b2(160 DOWNTO 129),
datain_a_37 => a2(192 DOWNTO 161),
datain_b_37 => b2(192 DOWNTO 161),
datain_a_38 => a2(224 DOWNTO 193),
datain_b_38 => b2(224 DOWNTO 193),
datain_a_39 => a2(256 DOWNTO 225),
datain_b_39 => b2(256 DOWNTO 225),
datain_a_40 => a2(288 DOWNTO 257),
datain_b_40 => b2(288 DOWNTO 257),
datain_a_41 => a2(320 DOWNTO 289),
datain_b_41 => b2(320 DOWNTO 289),
datain_a_42 => a2(352 DOWNTO 321),
datain_b_42 => b2(352 DOWNTO 321),
datain_a_43 => a2(384 DOWNTO 353),
datain_b_43 => b2(384 DOWNTO 353),
datain_a_44 => a2(416 DOWNTO 385),
datain_b_44 => b2(416 DOWNTO 385),
datain_a_45 => a2(448 DOWNTO 417),
datain_b_45 => b2(448 DOWNTO 417),
datain_a_46 => a2(480 DOWNTO 449),
datain_b_46 => b2(480 DOWNTO 449),
datain_a_47 => a2(512 DOWNTO 481),
datain_b_47 => b2(512 DOWNTO 481),
datain_a_48 => a3(32 DOWNTO 1),
datain_b_48 => b3(32 DOWNTO 1),
datain_a_49 => a3(64 DOWNTO 33),
datain_b_49 => b3(64 DOWNTO 33),
datain_a_50 => a3(96 DOWNTO 65),
datain_b_50 => b3(96 DOWNTO 65),
datain_a_51 => a3(128 DOWNTO 97),
datain_b_51 => b3(128 DOWNTO 97),
datain_a_52 => a3(160 DOWNTO 129),
datain_b_52 => b3(160 DOWNTO 129),
datain_a_53 => a3(192 DOWNTO 161),
datain_b_53 => b3(192 DOWNTO 161),
datain_a_54 => a3(224 DOWNTO 193),
datain_b_54 => b3(224 DOWNTO 193),
datain_a_55 => a3(256 DOWNTO 225),
datain_b_55 => b3(256 DOWNTO 225),
datain_a_56 => a3(288 DOWNTO 257),
datain_b_56 => b3(288 DOWNTO 257),
datain_a_57 => a3(320 DOWNTO 289),
datain_b_57 => b3(320 DOWNTO 289),
datain_a_58 => a3(352 DOWNTO 321),
datain_b_58 => b3(352 DOWNTO 321),
datain_a_59 => a3(384 DOWNTO 353),
datain_b_59 => b3(384 DOWNTO 353),
datain_a_60 => a3(416 DOWNTO 385),
datain_b_60 => b3(416 DOWNTO 385),
datain_a_61 => a3(448 DOWNTO 417),
datain_b_61 => b3(448 DOWNTO 417),
datain_a_62 => a3(480 DOWNTO 449),
datain_b_62 => b3(480 DOWNTO 449),
datain_a_63 => a3(512 DOWNTO 481),
datain_b_63 => b3(512 DOWNTO 481));
done <= '1' when (v_out = "1") else '0';
result <= res;
valid_out <= done;
END gen;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core_sv IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core_sv;
ARCHITECTURE gen OF dotp_core_sv IS
COMPONENT dotProduct64_dut is
port (
c_s : in std_logic_vector(7 downto 0);
cout_s : out std_logic_vector(7 downto 0);
datain_a_00 : in std_logic_vector(31 downto 0);
datain_a_01 : in std_logic_vector(31 downto 0);
datain_a_02 : in std_logic_vector(31 downto 0);
datain_a_03 : in std_logic_vector(31 downto 0);
datain_a_04 : in std_logic_vector(31 downto 0);
datain_a_05 : in std_logic_vector(31 downto 0);
datain_a_06 : in std_logic_vector(31 downto 0);
datain_a_07 : in std_logic_vector(31 downto 0);
datain_a_08 : in std_logic_vector(31 downto 0);
datain_a_09 : in std_logic_vector(31 downto 0);
datain_a_10 : in std_logic_vector(31 downto 0);
datain_a_11 : in std_logic_vector(31 downto 0);
datain_a_12 : in std_logic_vector(31 downto 0);
datain_a_13 : in std_logic_vector(31 downto 0);
datain_a_14 : in std_logic_vector(31 downto 0);
datain_a_15 : in std_logic_vector(31 downto 0);
datain_a_16 : in std_logic_vector(31 downto 0);
datain_a_17 : in std_logic_vector(31 downto 0);
datain_a_18 : in std_logic_vector(31 downto 0);
datain_a_19 : in std_logic_vector(31 downto 0);
datain_a_20 : in std_logic_vector(31 downto 0);
datain_a_21 : in std_logic_vector(31 downto 0);
datain_a_22 : in std_logic_vector(31 downto 0);
datain_a_23 : in std_logic_vector(31 downto 0);
datain_a_24 : in std_logic_vector(31 downto 0);
datain_a_25 : in std_logic_vector(31 downto 0);
datain_a_26 : in std_logic_vector(31 downto 0);
datain_a_27 : in std_logic_vector(31 downto 0);
datain_a_28 : in std_logic_vector(31 downto 0);
datain_a_29 : in std_logic_vector(31 downto 0);
datain_a_30 : in std_logic_vector(31 downto 0);
datain_a_31 : in std_logic_vector(31 downto 0);
datain_a_32 : in std_logic_vector(31 downto 0);
datain_a_33 : in std_logic_vector(31 downto 0);
datain_a_34 : in std_logic_vector(31 downto 0);
datain_a_35 : in std_logic_vector(31 downto 0);
datain_a_36 : in std_logic_vector(31 downto 0);
datain_a_37 : in std_logic_vector(31 downto 0);
datain_a_38 : in std_logic_vector(31 downto 0);
datain_a_39 : in std_logic_vector(31 downto 0);
datain_a_40 : in std_logic_vector(31 downto 0);
datain_a_41 : in std_logic_vector(31 downto 0);
datain_a_42 : in std_logic_vector(31 downto 0);
datain_a_43 : in std_logic_vector(31 downto 0);
datain_a_44 : in std_logic_vector(31 downto 0);
datain_a_45 : in std_logic_vector(31 downto 0);
datain_a_46 : in std_logic_vector(31 downto 0);
datain_a_47 : in std_logic_vector(31 downto 0);
datain_a_48 : in std_logic_vector(31 downto 0);
datain_a_49 : in std_logic_vector(31 downto 0);
datain_a_50 : in std_logic_vector(31 downto 0);
datain_a_51 : in std_logic_vector(31 downto 0);
datain_a_52 : in std_logic_vector(31 downto 0);
datain_a_53 : in std_logic_vector(31 downto 0);
datain_a_54 : in std_logic_vector(31 downto 0);
datain_a_55 : in std_logic_vector(31 downto 0);
datain_a_56 : in std_logic_vector(31 downto 0);
datain_a_57 : in std_logic_vector(31 downto 0);
datain_a_58 : in std_logic_vector(31 downto 0);
datain_a_59 : in std_logic_vector(31 downto 0);
datain_a_60 : in std_logic_vector(31 downto 0);
datain_a_61 : in std_logic_vector(31 downto 0);
datain_a_62 : in std_logic_vector(31 downto 0);
datain_a_63 : in std_logic_vector(31 downto 0);
datain_b_00 : in std_logic_vector(31 downto 0);
datain_b_01 : in std_logic_vector(31 downto 0);
datain_b_02 : in std_logic_vector(31 downto 0);
datain_b_03 : in std_logic_vector(31 downto 0);
datain_b_04 : in std_logic_vector(31 downto 0);
datain_b_05 : in std_logic_vector(31 downto 0);
datain_b_06 : in std_logic_vector(31 downto 0);
datain_b_07 : in std_logic_vector(31 downto 0);
datain_b_08 : in std_logic_vector(31 downto 0);
datain_b_09 : in std_logic_vector(31 downto 0);
datain_b_10 : in std_logic_vector(31 downto 0);
datain_b_11 : in std_logic_vector(31 downto 0);
datain_b_12 : in std_logic_vector(31 downto 0);
datain_b_13 : in std_logic_vector(31 downto 0);
datain_b_14 : in std_logic_vector(31 downto 0);
datain_b_15 : in std_logic_vector(31 downto 0);
datain_b_16 : in std_logic_vector(31 downto 0);
datain_b_17 : in std_logic_vector(31 downto 0);
datain_b_18 : in std_logic_vector(31 downto 0);
datain_b_19 : in std_logic_vector(31 downto 0);
datain_b_20 : in std_logic_vector(31 downto 0);
datain_b_21 : in std_logic_vector(31 downto 0);
datain_b_22 : in std_logic_vector(31 downto 0);
datain_b_23 : in std_logic_vector(31 downto 0);
datain_b_24 : in std_logic_vector(31 downto 0);
datain_b_25 : in std_logic_vector(31 downto 0);
datain_b_26 : in std_logic_vector(31 downto 0);
datain_b_27 : in std_logic_vector(31 downto 0);
datain_b_28 : in std_logic_vector(31 downto 0);
datain_b_29 : in std_logic_vector(31 downto 0);
datain_b_30 : in std_logic_vector(31 downto 0);
datain_b_31 : in std_logic_vector(31 downto 0);
datain_b_32 : in std_logic_vector(31 downto 0);
datain_b_33 : in std_logic_vector(31 downto 0);
datain_b_34 : in std_logic_vector(31 downto 0);
datain_b_35 : in std_logic_vector(31 downto 0);
datain_b_36 : in std_logic_vector(31 downto 0);
datain_b_37 : in std_logic_vector(31 downto 0);
datain_b_38 : in std_logic_vector(31 downto 0);
datain_b_39 : in std_logic_vector(31 downto 0);
datain_b_40 : in std_logic_vector(31 downto 0);
datain_b_41 : in std_logic_vector(31 downto 0);
datain_b_42 : in std_logic_vector(31 downto 0);
datain_b_43 : in std_logic_vector(31 downto 0);
datain_b_44 : in std_logic_vector(31 downto 0);
datain_b_45 : in std_logic_vector(31 downto 0);
datain_b_46 : in std_logic_vector(31 downto 0);
datain_b_47 : in std_logic_vector(31 downto 0);
datain_b_48 : in std_logic_vector(31 downto 0);
datain_b_49 : in std_logic_vector(31 downto 0);
datain_b_50 : in std_logic_vector(31 downto 0);
datain_b_51 : in std_logic_vector(31 downto 0);
datain_b_52 : in std_logic_vector(31 downto 0);
datain_b_53 : in std_logic_vector(31 downto 0);
datain_b_54 : in std_logic_vector(31 downto 0);
datain_b_55 : in std_logic_vector(31 downto 0);
datain_b_56 : in std_logic_vector(31 downto 0);
datain_b_57 : in std_logic_vector(31 downto 0);
datain_b_58 : in std_logic_vector(31 downto 0);
datain_b_59 : in std_logic_vector(31 downto 0);
datain_b_60 : in std_logic_vector(31 downto 0);
datain_b_61 : in std_logic_vector(31 downto 0);
datain_b_62 : in std_logic_vector(31 downto 0);
datain_b_63 : in std_logic_vector(31 downto 0);
dout_s : out std_logic_vector(31 downto 0);
v_s : in std_logic_vector(0 downto 0);
vout_s : out std_logic_vector(0 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
SIGNAL v_in : std_logic_vector(0 downto 0);
SIGNAL v_out : std_logic_vector(0 downto 0);
BEGIN
reset <= NOT resetn;
v_in <= "1" when (valid_in = '1') else "0";
cmp0: dotProduct64_dut
PORT MAP (clk=>clock, areset=>reset, h_areset => reset, v_s=>v_in,
vout_s=>v_out, dout_s=>res, c_s => "00000000",
datain_a_00 => a0(32 DOWNTO 1),
datain_b_00 => b0(32 DOWNTO 1),
datain_a_01 => a0(64 DOWNTO 33),
datain_b_01 => b0(64 DOWNTO 33),
datain_a_02 => a0(96 DOWNTO 65),
datain_b_02 => b0(96 DOWNTO 65),
datain_a_03 => a0(128 DOWNTO 97),
datain_b_03 => b0(128 DOWNTO 97),
datain_a_04 => a0(160 DOWNTO 129),
datain_b_04 => b0(160 DOWNTO 129),
datain_a_05 => a0(192 DOWNTO 161),
datain_b_05 => b0(192 DOWNTO 161),
datain_a_06 => a0(224 DOWNTO 193),
datain_b_06 => b0(224 DOWNTO 193),
datain_a_07 => a0(256 DOWNTO 225),
datain_b_07 => b0(256 DOWNTO 225),
datain_a_08 => a0(288 DOWNTO 257),
datain_b_08 => b0(288 DOWNTO 257),
datain_a_09 => a0(320 DOWNTO 289),
datain_b_09 => b0(320 DOWNTO 289),
datain_a_10 => a0(352 DOWNTO 321),
datain_b_10 => b0(352 DOWNTO 321),
datain_a_11 => a0(384 DOWNTO 353),
datain_b_11 => b0(384 DOWNTO 353),
datain_a_12 => a0(416 DOWNTO 385),
datain_b_12 => b0(416 DOWNTO 385),
datain_a_13 => a0(448 DOWNTO 417),
datain_b_13 => b0(448 DOWNTO 417),
datain_a_14 => a0(480 DOWNTO 449),
datain_b_14 => b0(480 DOWNTO 449),
datain_a_15 => a0(512 DOWNTO 481),
datain_b_15 => b0(512 DOWNTO 481),
datain_a_16 => a1(32 DOWNTO 1),
datain_b_16 => b1(32 DOWNTO 1),
datain_a_17 => a1(64 DOWNTO 33),
datain_b_17 => b1(64 DOWNTO 33),
datain_a_18 => a1(96 DOWNTO 65),
datain_b_18 => b1(96 DOWNTO 65),
datain_a_19 => a1(128 DOWNTO 97),
datain_b_19 => b1(128 DOWNTO 97),
datain_a_20 => a1(160 DOWNTO 129),
datain_b_20 => b1(160 DOWNTO 129),
datain_a_21 => a1(192 DOWNTO 161),
datain_b_21 => b1(192 DOWNTO 161),
datain_a_22 => a1(224 DOWNTO 193),
datain_b_22 => b1(224 DOWNTO 193),
datain_a_23 => a1(256 DOWNTO 225),
datain_b_23 => b1(256 DOWNTO 225),
datain_a_24 => a1(288 DOWNTO 257),
datain_b_24 => b1(288 DOWNTO 257),
datain_a_25 => a1(320 DOWNTO 289),
datain_b_25 => b1(320 DOWNTO 289),
datain_a_26 => a1(352 DOWNTO 321),
datain_b_26 => b1(352 DOWNTO 321),
datain_a_27 => a1(384 DOWNTO 353),
datain_b_27 => b1(384 DOWNTO 353),
datain_a_28 => a1(416 DOWNTO 385),
datain_b_28 => b1(416 DOWNTO 385),
datain_a_29 => a1(448 DOWNTO 417),
datain_b_29 => b1(448 DOWNTO 417),
datain_a_30 => a1(480 DOWNTO 449),
datain_b_30 => b1(480 DOWNTO 449),
datain_a_31 => a1(512 DOWNTO 481),
datain_b_31 => b1(512 DOWNTO 481),
datain_a_32 => a2(32 DOWNTO 1),
datain_b_32 => b2(32 DOWNTO 1),
datain_a_33 => a2(64 DOWNTO 33),
datain_b_33 => b2(64 DOWNTO 33),
datain_a_34 => a2(96 DOWNTO 65),
datain_b_34 => b2(96 DOWNTO 65),
datain_a_35 => a2(128 DOWNTO 97),
datain_b_35 => b2(128 DOWNTO 97),
datain_a_36 => a2(160 DOWNTO 129),
datain_b_36 => b2(160 DOWNTO 129),
datain_a_37 => a2(192 DOWNTO 161),
datain_b_37 => b2(192 DOWNTO 161),
datain_a_38 => a2(224 DOWNTO 193),
datain_b_38 => b2(224 DOWNTO 193),
datain_a_39 => a2(256 DOWNTO 225),
datain_b_39 => b2(256 DOWNTO 225),
datain_a_40 => a2(288 DOWNTO 257),
datain_b_40 => b2(288 DOWNTO 257),
datain_a_41 => a2(320 DOWNTO 289),
datain_b_41 => b2(320 DOWNTO 289),
datain_a_42 => a2(352 DOWNTO 321),
datain_b_42 => b2(352 DOWNTO 321),
datain_a_43 => a2(384 DOWNTO 353),
datain_b_43 => b2(384 DOWNTO 353),
datain_a_44 => a2(416 DOWNTO 385),
datain_b_44 => b2(416 DOWNTO 385),
datain_a_45 => a2(448 DOWNTO 417),
datain_b_45 => b2(448 DOWNTO 417),
datain_a_46 => a2(480 DOWNTO 449),
datain_b_46 => b2(480 DOWNTO 449),
datain_a_47 => a2(512 DOWNTO 481),
datain_b_47 => b2(512 DOWNTO 481),
datain_a_48 => a3(32 DOWNTO 1),
datain_b_48 => b3(32 DOWNTO 1),
datain_a_49 => a3(64 DOWNTO 33),
datain_b_49 => b3(64 DOWNTO 33),
datain_a_50 => a3(96 DOWNTO 65),
datain_b_50 => b3(96 DOWNTO 65),
datain_a_51 => a3(128 DOWNTO 97),
datain_b_51 => b3(128 DOWNTO 97),
datain_a_52 => a3(160 DOWNTO 129),
datain_b_52 => b3(160 DOWNTO 129),
datain_a_53 => a3(192 DOWNTO 161),
datain_b_53 => b3(192 DOWNTO 161),
datain_a_54 => a3(224 DOWNTO 193),
datain_b_54 => b3(224 DOWNTO 193),
datain_a_55 => a3(256 DOWNTO 225),
datain_b_55 => b3(256 DOWNTO 225),
datain_a_56 => a3(288 DOWNTO 257),
datain_b_56 => b3(288 DOWNTO 257),
datain_a_57 => a3(320 DOWNTO 289),
datain_b_57 => b3(320 DOWNTO 289),
datain_a_58 => a3(352 DOWNTO 321),
datain_b_58 => b3(352 DOWNTO 321),
datain_a_59 => a3(384 DOWNTO 353),
datain_b_59 => b3(384 DOWNTO 353),
datain_a_60 => a3(416 DOWNTO 385),
datain_b_60 => b3(416 DOWNTO 385),
datain_a_61 => a3(448 DOWNTO 417),
datain_b_61 => b3(448 DOWNTO 417),
datain_a_62 => a3(480 DOWNTO 449),
datain_b_62 => b3(480 DOWNTO 449),
datain_a_63 => a3(512 DOWNTO 481),
datain_b_63 => b3(512 DOWNTO 481));
done <= '1' when (v_out = "1") else '0';
result <= res;
valid_out <= done;
END gen;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core_sv IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core_sv;
ARCHITECTURE gen OF dotp_core_sv IS
COMPONENT dotProduct64_dut is
port (
c_s : in std_logic_vector(7 downto 0);
cout_s : out std_logic_vector(7 downto 0);
datain_a_00 : in std_logic_vector(31 downto 0);
datain_a_01 : in std_logic_vector(31 downto 0);
datain_a_02 : in std_logic_vector(31 downto 0);
datain_a_03 : in std_logic_vector(31 downto 0);
datain_a_04 : in std_logic_vector(31 downto 0);
datain_a_05 : in std_logic_vector(31 downto 0);
datain_a_06 : in std_logic_vector(31 downto 0);
datain_a_07 : in std_logic_vector(31 downto 0);
datain_a_08 : in std_logic_vector(31 downto 0);
datain_a_09 : in std_logic_vector(31 downto 0);
datain_a_10 : in std_logic_vector(31 downto 0);
datain_a_11 : in std_logic_vector(31 downto 0);
datain_a_12 : in std_logic_vector(31 downto 0);
datain_a_13 : in std_logic_vector(31 downto 0);
datain_a_14 : in std_logic_vector(31 downto 0);
datain_a_15 : in std_logic_vector(31 downto 0);
datain_a_16 : in std_logic_vector(31 downto 0);
datain_a_17 : in std_logic_vector(31 downto 0);
datain_a_18 : in std_logic_vector(31 downto 0);
datain_a_19 : in std_logic_vector(31 downto 0);
datain_a_20 : in std_logic_vector(31 downto 0);
datain_a_21 : in std_logic_vector(31 downto 0);
datain_a_22 : in std_logic_vector(31 downto 0);
datain_a_23 : in std_logic_vector(31 downto 0);
datain_a_24 : in std_logic_vector(31 downto 0);
datain_a_25 : in std_logic_vector(31 downto 0);
datain_a_26 : in std_logic_vector(31 downto 0);
datain_a_27 : in std_logic_vector(31 downto 0);
datain_a_28 : in std_logic_vector(31 downto 0);
datain_a_29 : in std_logic_vector(31 downto 0);
datain_a_30 : in std_logic_vector(31 downto 0);
datain_a_31 : in std_logic_vector(31 downto 0);
datain_a_32 : in std_logic_vector(31 downto 0);
datain_a_33 : in std_logic_vector(31 downto 0);
datain_a_34 : in std_logic_vector(31 downto 0);
datain_a_35 : in std_logic_vector(31 downto 0);
datain_a_36 : in std_logic_vector(31 downto 0);
datain_a_37 : in std_logic_vector(31 downto 0);
datain_a_38 : in std_logic_vector(31 downto 0);
datain_a_39 : in std_logic_vector(31 downto 0);
datain_a_40 : in std_logic_vector(31 downto 0);
datain_a_41 : in std_logic_vector(31 downto 0);
datain_a_42 : in std_logic_vector(31 downto 0);
datain_a_43 : in std_logic_vector(31 downto 0);
datain_a_44 : in std_logic_vector(31 downto 0);
datain_a_45 : in std_logic_vector(31 downto 0);
datain_a_46 : in std_logic_vector(31 downto 0);
datain_a_47 : in std_logic_vector(31 downto 0);
datain_a_48 : in std_logic_vector(31 downto 0);
datain_a_49 : in std_logic_vector(31 downto 0);
datain_a_50 : in std_logic_vector(31 downto 0);
datain_a_51 : in std_logic_vector(31 downto 0);
datain_a_52 : in std_logic_vector(31 downto 0);
datain_a_53 : in std_logic_vector(31 downto 0);
datain_a_54 : in std_logic_vector(31 downto 0);
datain_a_55 : in std_logic_vector(31 downto 0);
datain_a_56 : in std_logic_vector(31 downto 0);
datain_a_57 : in std_logic_vector(31 downto 0);
datain_a_58 : in std_logic_vector(31 downto 0);
datain_a_59 : in std_logic_vector(31 downto 0);
datain_a_60 : in std_logic_vector(31 downto 0);
datain_a_61 : in std_logic_vector(31 downto 0);
datain_a_62 : in std_logic_vector(31 downto 0);
datain_a_63 : in std_logic_vector(31 downto 0);
datain_b_00 : in std_logic_vector(31 downto 0);
datain_b_01 : in std_logic_vector(31 downto 0);
datain_b_02 : in std_logic_vector(31 downto 0);
datain_b_03 : in std_logic_vector(31 downto 0);
datain_b_04 : in std_logic_vector(31 downto 0);
datain_b_05 : in std_logic_vector(31 downto 0);
datain_b_06 : in std_logic_vector(31 downto 0);
datain_b_07 : in std_logic_vector(31 downto 0);
datain_b_08 : in std_logic_vector(31 downto 0);
datain_b_09 : in std_logic_vector(31 downto 0);
datain_b_10 : in std_logic_vector(31 downto 0);
datain_b_11 : in std_logic_vector(31 downto 0);
datain_b_12 : in std_logic_vector(31 downto 0);
datain_b_13 : in std_logic_vector(31 downto 0);
datain_b_14 : in std_logic_vector(31 downto 0);
datain_b_15 : in std_logic_vector(31 downto 0);
datain_b_16 : in std_logic_vector(31 downto 0);
datain_b_17 : in std_logic_vector(31 downto 0);
datain_b_18 : in std_logic_vector(31 downto 0);
datain_b_19 : in std_logic_vector(31 downto 0);
datain_b_20 : in std_logic_vector(31 downto 0);
datain_b_21 : in std_logic_vector(31 downto 0);
datain_b_22 : in std_logic_vector(31 downto 0);
datain_b_23 : in std_logic_vector(31 downto 0);
datain_b_24 : in std_logic_vector(31 downto 0);
datain_b_25 : in std_logic_vector(31 downto 0);
datain_b_26 : in std_logic_vector(31 downto 0);
datain_b_27 : in std_logic_vector(31 downto 0);
datain_b_28 : in std_logic_vector(31 downto 0);
datain_b_29 : in std_logic_vector(31 downto 0);
datain_b_30 : in std_logic_vector(31 downto 0);
datain_b_31 : in std_logic_vector(31 downto 0);
datain_b_32 : in std_logic_vector(31 downto 0);
datain_b_33 : in std_logic_vector(31 downto 0);
datain_b_34 : in std_logic_vector(31 downto 0);
datain_b_35 : in std_logic_vector(31 downto 0);
datain_b_36 : in std_logic_vector(31 downto 0);
datain_b_37 : in std_logic_vector(31 downto 0);
datain_b_38 : in std_logic_vector(31 downto 0);
datain_b_39 : in std_logic_vector(31 downto 0);
datain_b_40 : in std_logic_vector(31 downto 0);
datain_b_41 : in std_logic_vector(31 downto 0);
datain_b_42 : in std_logic_vector(31 downto 0);
datain_b_43 : in std_logic_vector(31 downto 0);
datain_b_44 : in std_logic_vector(31 downto 0);
datain_b_45 : in std_logic_vector(31 downto 0);
datain_b_46 : in std_logic_vector(31 downto 0);
datain_b_47 : in std_logic_vector(31 downto 0);
datain_b_48 : in std_logic_vector(31 downto 0);
datain_b_49 : in std_logic_vector(31 downto 0);
datain_b_50 : in std_logic_vector(31 downto 0);
datain_b_51 : in std_logic_vector(31 downto 0);
datain_b_52 : in std_logic_vector(31 downto 0);
datain_b_53 : in std_logic_vector(31 downto 0);
datain_b_54 : in std_logic_vector(31 downto 0);
datain_b_55 : in std_logic_vector(31 downto 0);
datain_b_56 : in std_logic_vector(31 downto 0);
datain_b_57 : in std_logic_vector(31 downto 0);
datain_b_58 : in std_logic_vector(31 downto 0);
datain_b_59 : in std_logic_vector(31 downto 0);
datain_b_60 : in std_logic_vector(31 downto 0);
datain_b_61 : in std_logic_vector(31 downto 0);
datain_b_62 : in std_logic_vector(31 downto 0);
datain_b_63 : in std_logic_vector(31 downto 0);
dout_s : out std_logic_vector(31 downto 0);
v_s : in std_logic_vector(0 downto 0);
vout_s : out std_logic_vector(0 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
SIGNAL v_in : std_logic_vector(0 downto 0);
SIGNAL v_out : std_logic_vector(0 downto 0);
BEGIN
reset <= NOT resetn;
v_in <= "1" when (valid_in = '1') else "0";
cmp0: dotProduct64_dut
PORT MAP (clk=>clock, areset=>reset, h_areset => reset, v_s=>v_in,
vout_s=>v_out, dout_s=>res, c_s => "00000000",
datain_a_00 => a0(32 DOWNTO 1),
datain_b_00 => b0(32 DOWNTO 1),
datain_a_01 => a0(64 DOWNTO 33),
datain_b_01 => b0(64 DOWNTO 33),
datain_a_02 => a0(96 DOWNTO 65),
datain_b_02 => b0(96 DOWNTO 65),
datain_a_03 => a0(128 DOWNTO 97),
datain_b_03 => b0(128 DOWNTO 97),
datain_a_04 => a0(160 DOWNTO 129),
datain_b_04 => b0(160 DOWNTO 129),
datain_a_05 => a0(192 DOWNTO 161),
datain_b_05 => b0(192 DOWNTO 161),
datain_a_06 => a0(224 DOWNTO 193),
datain_b_06 => b0(224 DOWNTO 193),
datain_a_07 => a0(256 DOWNTO 225),
datain_b_07 => b0(256 DOWNTO 225),
datain_a_08 => a0(288 DOWNTO 257),
datain_b_08 => b0(288 DOWNTO 257),
datain_a_09 => a0(320 DOWNTO 289),
datain_b_09 => b0(320 DOWNTO 289),
datain_a_10 => a0(352 DOWNTO 321),
datain_b_10 => b0(352 DOWNTO 321),
datain_a_11 => a0(384 DOWNTO 353),
datain_b_11 => b0(384 DOWNTO 353),
datain_a_12 => a0(416 DOWNTO 385),
datain_b_12 => b0(416 DOWNTO 385),
datain_a_13 => a0(448 DOWNTO 417),
datain_b_13 => b0(448 DOWNTO 417),
datain_a_14 => a0(480 DOWNTO 449),
datain_b_14 => b0(480 DOWNTO 449),
datain_a_15 => a0(512 DOWNTO 481),
datain_b_15 => b0(512 DOWNTO 481),
datain_a_16 => a1(32 DOWNTO 1),
datain_b_16 => b1(32 DOWNTO 1),
datain_a_17 => a1(64 DOWNTO 33),
datain_b_17 => b1(64 DOWNTO 33),
datain_a_18 => a1(96 DOWNTO 65),
datain_b_18 => b1(96 DOWNTO 65),
datain_a_19 => a1(128 DOWNTO 97),
datain_b_19 => b1(128 DOWNTO 97),
datain_a_20 => a1(160 DOWNTO 129),
datain_b_20 => b1(160 DOWNTO 129),
datain_a_21 => a1(192 DOWNTO 161),
datain_b_21 => b1(192 DOWNTO 161),
datain_a_22 => a1(224 DOWNTO 193),
datain_b_22 => b1(224 DOWNTO 193),
datain_a_23 => a1(256 DOWNTO 225),
datain_b_23 => b1(256 DOWNTO 225),
datain_a_24 => a1(288 DOWNTO 257),
datain_b_24 => b1(288 DOWNTO 257),
datain_a_25 => a1(320 DOWNTO 289),
datain_b_25 => b1(320 DOWNTO 289),
datain_a_26 => a1(352 DOWNTO 321),
datain_b_26 => b1(352 DOWNTO 321),
datain_a_27 => a1(384 DOWNTO 353),
datain_b_27 => b1(384 DOWNTO 353),
datain_a_28 => a1(416 DOWNTO 385),
datain_b_28 => b1(416 DOWNTO 385),
datain_a_29 => a1(448 DOWNTO 417),
datain_b_29 => b1(448 DOWNTO 417),
datain_a_30 => a1(480 DOWNTO 449),
datain_b_30 => b1(480 DOWNTO 449),
datain_a_31 => a1(512 DOWNTO 481),
datain_b_31 => b1(512 DOWNTO 481),
datain_a_32 => a2(32 DOWNTO 1),
datain_b_32 => b2(32 DOWNTO 1),
datain_a_33 => a2(64 DOWNTO 33),
datain_b_33 => b2(64 DOWNTO 33),
datain_a_34 => a2(96 DOWNTO 65),
datain_b_34 => b2(96 DOWNTO 65),
datain_a_35 => a2(128 DOWNTO 97),
datain_b_35 => b2(128 DOWNTO 97),
datain_a_36 => a2(160 DOWNTO 129),
datain_b_36 => b2(160 DOWNTO 129),
datain_a_37 => a2(192 DOWNTO 161),
datain_b_37 => b2(192 DOWNTO 161),
datain_a_38 => a2(224 DOWNTO 193),
datain_b_38 => b2(224 DOWNTO 193),
datain_a_39 => a2(256 DOWNTO 225),
datain_b_39 => b2(256 DOWNTO 225),
datain_a_40 => a2(288 DOWNTO 257),
datain_b_40 => b2(288 DOWNTO 257),
datain_a_41 => a2(320 DOWNTO 289),
datain_b_41 => b2(320 DOWNTO 289),
datain_a_42 => a2(352 DOWNTO 321),
datain_b_42 => b2(352 DOWNTO 321),
datain_a_43 => a2(384 DOWNTO 353),
datain_b_43 => b2(384 DOWNTO 353),
datain_a_44 => a2(416 DOWNTO 385),
datain_b_44 => b2(416 DOWNTO 385),
datain_a_45 => a2(448 DOWNTO 417),
datain_b_45 => b2(448 DOWNTO 417),
datain_a_46 => a2(480 DOWNTO 449),
datain_b_46 => b2(480 DOWNTO 449),
datain_a_47 => a2(512 DOWNTO 481),
datain_b_47 => b2(512 DOWNTO 481),
datain_a_48 => a3(32 DOWNTO 1),
datain_b_48 => b3(32 DOWNTO 1),
datain_a_49 => a3(64 DOWNTO 33),
datain_b_49 => b3(64 DOWNTO 33),
datain_a_50 => a3(96 DOWNTO 65),
datain_b_50 => b3(96 DOWNTO 65),
datain_a_51 => a3(128 DOWNTO 97),
datain_b_51 => b3(128 DOWNTO 97),
datain_a_52 => a3(160 DOWNTO 129),
datain_b_52 => b3(160 DOWNTO 129),
datain_a_53 => a3(192 DOWNTO 161),
datain_b_53 => b3(192 DOWNTO 161),
datain_a_54 => a3(224 DOWNTO 193),
datain_b_54 => b3(224 DOWNTO 193),
datain_a_55 => a3(256 DOWNTO 225),
datain_b_55 => b3(256 DOWNTO 225),
datain_a_56 => a3(288 DOWNTO 257),
datain_b_56 => b3(288 DOWNTO 257),
datain_a_57 => a3(320 DOWNTO 289),
datain_b_57 => b3(320 DOWNTO 289),
datain_a_58 => a3(352 DOWNTO 321),
datain_b_58 => b3(352 DOWNTO 321),
datain_a_59 => a3(384 DOWNTO 353),
datain_b_59 => b3(384 DOWNTO 353),
datain_a_60 => a3(416 DOWNTO 385),
datain_b_60 => b3(416 DOWNTO 385),
datain_a_61 => a3(448 DOWNTO 417),
datain_b_61 => b3(448 DOWNTO 417),
datain_a_62 => a3(480 DOWNTO 449),
datain_b_62 => b3(480 DOWNTO 449),
datain_a_63 => a3(512 DOWNTO 481),
datain_b_63 => b3(512 DOWNTO 481));
done <= '1' when (v_out = "1") else '0';
result <= res;
valid_out <= done;
END gen;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core_sv IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core_sv;
ARCHITECTURE gen OF dotp_core_sv IS
COMPONENT dotProduct64_dut is
port (
c_s : in std_logic_vector(7 downto 0);
cout_s : out std_logic_vector(7 downto 0);
datain_a_00 : in std_logic_vector(31 downto 0);
datain_a_01 : in std_logic_vector(31 downto 0);
datain_a_02 : in std_logic_vector(31 downto 0);
datain_a_03 : in std_logic_vector(31 downto 0);
datain_a_04 : in std_logic_vector(31 downto 0);
datain_a_05 : in std_logic_vector(31 downto 0);
datain_a_06 : in std_logic_vector(31 downto 0);
datain_a_07 : in std_logic_vector(31 downto 0);
datain_a_08 : in std_logic_vector(31 downto 0);
datain_a_09 : in std_logic_vector(31 downto 0);
datain_a_10 : in std_logic_vector(31 downto 0);
datain_a_11 : in std_logic_vector(31 downto 0);
datain_a_12 : in std_logic_vector(31 downto 0);
datain_a_13 : in std_logic_vector(31 downto 0);
datain_a_14 : in std_logic_vector(31 downto 0);
datain_a_15 : in std_logic_vector(31 downto 0);
datain_a_16 : in std_logic_vector(31 downto 0);
datain_a_17 : in std_logic_vector(31 downto 0);
datain_a_18 : in std_logic_vector(31 downto 0);
datain_a_19 : in std_logic_vector(31 downto 0);
datain_a_20 : in std_logic_vector(31 downto 0);
datain_a_21 : in std_logic_vector(31 downto 0);
datain_a_22 : in std_logic_vector(31 downto 0);
datain_a_23 : in std_logic_vector(31 downto 0);
datain_a_24 : in std_logic_vector(31 downto 0);
datain_a_25 : in std_logic_vector(31 downto 0);
datain_a_26 : in std_logic_vector(31 downto 0);
datain_a_27 : in std_logic_vector(31 downto 0);
datain_a_28 : in std_logic_vector(31 downto 0);
datain_a_29 : in std_logic_vector(31 downto 0);
datain_a_30 : in std_logic_vector(31 downto 0);
datain_a_31 : in std_logic_vector(31 downto 0);
datain_a_32 : in std_logic_vector(31 downto 0);
datain_a_33 : in std_logic_vector(31 downto 0);
datain_a_34 : in std_logic_vector(31 downto 0);
datain_a_35 : in std_logic_vector(31 downto 0);
datain_a_36 : in std_logic_vector(31 downto 0);
datain_a_37 : in std_logic_vector(31 downto 0);
datain_a_38 : in std_logic_vector(31 downto 0);
datain_a_39 : in std_logic_vector(31 downto 0);
datain_a_40 : in std_logic_vector(31 downto 0);
datain_a_41 : in std_logic_vector(31 downto 0);
datain_a_42 : in std_logic_vector(31 downto 0);
datain_a_43 : in std_logic_vector(31 downto 0);
datain_a_44 : in std_logic_vector(31 downto 0);
datain_a_45 : in std_logic_vector(31 downto 0);
datain_a_46 : in std_logic_vector(31 downto 0);
datain_a_47 : in std_logic_vector(31 downto 0);
datain_a_48 : in std_logic_vector(31 downto 0);
datain_a_49 : in std_logic_vector(31 downto 0);
datain_a_50 : in std_logic_vector(31 downto 0);
datain_a_51 : in std_logic_vector(31 downto 0);
datain_a_52 : in std_logic_vector(31 downto 0);
datain_a_53 : in std_logic_vector(31 downto 0);
datain_a_54 : in std_logic_vector(31 downto 0);
datain_a_55 : in std_logic_vector(31 downto 0);
datain_a_56 : in std_logic_vector(31 downto 0);
datain_a_57 : in std_logic_vector(31 downto 0);
datain_a_58 : in std_logic_vector(31 downto 0);
datain_a_59 : in std_logic_vector(31 downto 0);
datain_a_60 : in std_logic_vector(31 downto 0);
datain_a_61 : in std_logic_vector(31 downto 0);
datain_a_62 : in std_logic_vector(31 downto 0);
datain_a_63 : in std_logic_vector(31 downto 0);
datain_b_00 : in std_logic_vector(31 downto 0);
datain_b_01 : in std_logic_vector(31 downto 0);
datain_b_02 : in std_logic_vector(31 downto 0);
datain_b_03 : in std_logic_vector(31 downto 0);
datain_b_04 : in std_logic_vector(31 downto 0);
datain_b_05 : in std_logic_vector(31 downto 0);
datain_b_06 : in std_logic_vector(31 downto 0);
datain_b_07 : in std_logic_vector(31 downto 0);
datain_b_08 : in std_logic_vector(31 downto 0);
datain_b_09 : in std_logic_vector(31 downto 0);
datain_b_10 : in std_logic_vector(31 downto 0);
datain_b_11 : in std_logic_vector(31 downto 0);
datain_b_12 : in std_logic_vector(31 downto 0);
datain_b_13 : in std_logic_vector(31 downto 0);
datain_b_14 : in std_logic_vector(31 downto 0);
datain_b_15 : in std_logic_vector(31 downto 0);
datain_b_16 : in std_logic_vector(31 downto 0);
datain_b_17 : in std_logic_vector(31 downto 0);
datain_b_18 : in std_logic_vector(31 downto 0);
datain_b_19 : in std_logic_vector(31 downto 0);
datain_b_20 : in std_logic_vector(31 downto 0);
datain_b_21 : in std_logic_vector(31 downto 0);
datain_b_22 : in std_logic_vector(31 downto 0);
datain_b_23 : in std_logic_vector(31 downto 0);
datain_b_24 : in std_logic_vector(31 downto 0);
datain_b_25 : in std_logic_vector(31 downto 0);
datain_b_26 : in std_logic_vector(31 downto 0);
datain_b_27 : in std_logic_vector(31 downto 0);
datain_b_28 : in std_logic_vector(31 downto 0);
datain_b_29 : in std_logic_vector(31 downto 0);
datain_b_30 : in std_logic_vector(31 downto 0);
datain_b_31 : in std_logic_vector(31 downto 0);
datain_b_32 : in std_logic_vector(31 downto 0);
datain_b_33 : in std_logic_vector(31 downto 0);
datain_b_34 : in std_logic_vector(31 downto 0);
datain_b_35 : in std_logic_vector(31 downto 0);
datain_b_36 : in std_logic_vector(31 downto 0);
datain_b_37 : in std_logic_vector(31 downto 0);
datain_b_38 : in std_logic_vector(31 downto 0);
datain_b_39 : in std_logic_vector(31 downto 0);
datain_b_40 : in std_logic_vector(31 downto 0);
datain_b_41 : in std_logic_vector(31 downto 0);
datain_b_42 : in std_logic_vector(31 downto 0);
datain_b_43 : in std_logic_vector(31 downto 0);
datain_b_44 : in std_logic_vector(31 downto 0);
datain_b_45 : in std_logic_vector(31 downto 0);
datain_b_46 : in std_logic_vector(31 downto 0);
datain_b_47 : in std_logic_vector(31 downto 0);
datain_b_48 : in std_logic_vector(31 downto 0);
datain_b_49 : in std_logic_vector(31 downto 0);
datain_b_50 : in std_logic_vector(31 downto 0);
datain_b_51 : in std_logic_vector(31 downto 0);
datain_b_52 : in std_logic_vector(31 downto 0);
datain_b_53 : in std_logic_vector(31 downto 0);
datain_b_54 : in std_logic_vector(31 downto 0);
datain_b_55 : in std_logic_vector(31 downto 0);
datain_b_56 : in std_logic_vector(31 downto 0);
datain_b_57 : in std_logic_vector(31 downto 0);
datain_b_58 : in std_logic_vector(31 downto 0);
datain_b_59 : in std_logic_vector(31 downto 0);
datain_b_60 : in std_logic_vector(31 downto 0);
datain_b_61 : in std_logic_vector(31 downto 0);
datain_b_62 : in std_logic_vector(31 downto 0);
datain_b_63 : in std_logic_vector(31 downto 0);
dout_s : out std_logic_vector(31 downto 0);
v_s : in std_logic_vector(0 downto 0);
vout_s : out std_logic_vector(0 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
SIGNAL v_in : std_logic_vector(0 downto 0);
SIGNAL v_out : std_logic_vector(0 downto 0);
BEGIN
reset <= NOT resetn;
v_in <= "1" when (valid_in = '1') else "0";
cmp0: dotProduct64_dut
PORT MAP (clk=>clock, areset=>reset, h_areset => reset, v_s=>v_in,
vout_s=>v_out, dout_s=>res, c_s => "00000000",
datain_a_00 => a0(32 DOWNTO 1),
datain_b_00 => b0(32 DOWNTO 1),
datain_a_01 => a0(64 DOWNTO 33),
datain_b_01 => b0(64 DOWNTO 33),
datain_a_02 => a0(96 DOWNTO 65),
datain_b_02 => b0(96 DOWNTO 65),
datain_a_03 => a0(128 DOWNTO 97),
datain_b_03 => b0(128 DOWNTO 97),
datain_a_04 => a0(160 DOWNTO 129),
datain_b_04 => b0(160 DOWNTO 129),
datain_a_05 => a0(192 DOWNTO 161),
datain_b_05 => b0(192 DOWNTO 161),
datain_a_06 => a0(224 DOWNTO 193),
datain_b_06 => b0(224 DOWNTO 193),
datain_a_07 => a0(256 DOWNTO 225),
datain_b_07 => b0(256 DOWNTO 225),
datain_a_08 => a0(288 DOWNTO 257),
datain_b_08 => b0(288 DOWNTO 257),
datain_a_09 => a0(320 DOWNTO 289),
datain_b_09 => b0(320 DOWNTO 289),
datain_a_10 => a0(352 DOWNTO 321),
datain_b_10 => b0(352 DOWNTO 321),
datain_a_11 => a0(384 DOWNTO 353),
datain_b_11 => b0(384 DOWNTO 353),
datain_a_12 => a0(416 DOWNTO 385),
datain_b_12 => b0(416 DOWNTO 385),
datain_a_13 => a0(448 DOWNTO 417),
datain_b_13 => b0(448 DOWNTO 417),
datain_a_14 => a0(480 DOWNTO 449),
datain_b_14 => b0(480 DOWNTO 449),
datain_a_15 => a0(512 DOWNTO 481),
datain_b_15 => b0(512 DOWNTO 481),
datain_a_16 => a1(32 DOWNTO 1),
datain_b_16 => b1(32 DOWNTO 1),
datain_a_17 => a1(64 DOWNTO 33),
datain_b_17 => b1(64 DOWNTO 33),
datain_a_18 => a1(96 DOWNTO 65),
datain_b_18 => b1(96 DOWNTO 65),
datain_a_19 => a1(128 DOWNTO 97),
datain_b_19 => b1(128 DOWNTO 97),
datain_a_20 => a1(160 DOWNTO 129),
datain_b_20 => b1(160 DOWNTO 129),
datain_a_21 => a1(192 DOWNTO 161),
datain_b_21 => b1(192 DOWNTO 161),
datain_a_22 => a1(224 DOWNTO 193),
datain_b_22 => b1(224 DOWNTO 193),
datain_a_23 => a1(256 DOWNTO 225),
datain_b_23 => b1(256 DOWNTO 225),
datain_a_24 => a1(288 DOWNTO 257),
datain_b_24 => b1(288 DOWNTO 257),
datain_a_25 => a1(320 DOWNTO 289),
datain_b_25 => b1(320 DOWNTO 289),
datain_a_26 => a1(352 DOWNTO 321),
datain_b_26 => b1(352 DOWNTO 321),
datain_a_27 => a1(384 DOWNTO 353),
datain_b_27 => b1(384 DOWNTO 353),
datain_a_28 => a1(416 DOWNTO 385),
datain_b_28 => b1(416 DOWNTO 385),
datain_a_29 => a1(448 DOWNTO 417),
datain_b_29 => b1(448 DOWNTO 417),
datain_a_30 => a1(480 DOWNTO 449),
datain_b_30 => b1(480 DOWNTO 449),
datain_a_31 => a1(512 DOWNTO 481),
datain_b_31 => b1(512 DOWNTO 481),
datain_a_32 => a2(32 DOWNTO 1),
datain_b_32 => b2(32 DOWNTO 1),
datain_a_33 => a2(64 DOWNTO 33),
datain_b_33 => b2(64 DOWNTO 33),
datain_a_34 => a2(96 DOWNTO 65),
datain_b_34 => b2(96 DOWNTO 65),
datain_a_35 => a2(128 DOWNTO 97),
datain_b_35 => b2(128 DOWNTO 97),
datain_a_36 => a2(160 DOWNTO 129),
datain_b_36 => b2(160 DOWNTO 129),
datain_a_37 => a2(192 DOWNTO 161),
datain_b_37 => b2(192 DOWNTO 161),
datain_a_38 => a2(224 DOWNTO 193),
datain_b_38 => b2(224 DOWNTO 193),
datain_a_39 => a2(256 DOWNTO 225),
datain_b_39 => b2(256 DOWNTO 225),
datain_a_40 => a2(288 DOWNTO 257),
datain_b_40 => b2(288 DOWNTO 257),
datain_a_41 => a2(320 DOWNTO 289),
datain_b_41 => b2(320 DOWNTO 289),
datain_a_42 => a2(352 DOWNTO 321),
datain_b_42 => b2(352 DOWNTO 321),
datain_a_43 => a2(384 DOWNTO 353),
datain_b_43 => b2(384 DOWNTO 353),
datain_a_44 => a2(416 DOWNTO 385),
datain_b_44 => b2(416 DOWNTO 385),
datain_a_45 => a2(448 DOWNTO 417),
datain_b_45 => b2(448 DOWNTO 417),
datain_a_46 => a2(480 DOWNTO 449),
datain_b_46 => b2(480 DOWNTO 449),
datain_a_47 => a2(512 DOWNTO 481),
datain_b_47 => b2(512 DOWNTO 481),
datain_a_48 => a3(32 DOWNTO 1),
datain_b_48 => b3(32 DOWNTO 1),
datain_a_49 => a3(64 DOWNTO 33),
datain_b_49 => b3(64 DOWNTO 33),
datain_a_50 => a3(96 DOWNTO 65),
datain_b_50 => b3(96 DOWNTO 65),
datain_a_51 => a3(128 DOWNTO 97),
datain_b_51 => b3(128 DOWNTO 97),
datain_a_52 => a3(160 DOWNTO 129),
datain_b_52 => b3(160 DOWNTO 129),
datain_a_53 => a3(192 DOWNTO 161),
datain_b_53 => b3(192 DOWNTO 161),
datain_a_54 => a3(224 DOWNTO 193),
datain_b_54 => b3(224 DOWNTO 193),
datain_a_55 => a3(256 DOWNTO 225),
datain_b_55 => b3(256 DOWNTO 225),
datain_a_56 => a3(288 DOWNTO 257),
datain_b_56 => b3(288 DOWNTO 257),
datain_a_57 => a3(320 DOWNTO 289),
datain_b_57 => b3(320 DOWNTO 289),
datain_a_58 => a3(352 DOWNTO 321),
datain_b_58 => b3(352 DOWNTO 321),
datain_a_59 => a3(384 DOWNTO 353),
datain_b_59 => b3(384 DOWNTO 353),
datain_a_60 => a3(416 DOWNTO 385),
datain_b_60 => b3(416 DOWNTO 385),
datain_a_61 => a3(448 DOWNTO 417),
datain_b_61 => b3(448 DOWNTO 417),
datain_a_62 => a3(480 DOWNTO 449),
datain_b_62 => b3(480 DOWNTO 449),
datain_a_63 => a3(512 DOWNTO 481),
datain_b_63 => b3(512 DOWNTO 481));
done <= '1' when (v_out = "1") else '0';
result <= res;
valid_out <= done;
END gen;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core_sv IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core_sv;
ARCHITECTURE gen OF dotp_core_sv IS
COMPONENT dotProduct64_dut is
port (
c_s : in std_logic_vector(7 downto 0);
cout_s : out std_logic_vector(7 downto 0);
datain_a_00 : in std_logic_vector(31 downto 0);
datain_a_01 : in std_logic_vector(31 downto 0);
datain_a_02 : in std_logic_vector(31 downto 0);
datain_a_03 : in std_logic_vector(31 downto 0);
datain_a_04 : in std_logic_vector(31 downto 0);
datain_a_05 : in std_logic_vector(31 downto 0);
datain_a_06 : in std_logic_vector(31 downto 0);
datain_a_07 : in std_logic_vector(31 downto 0);
datain_a_08 : in std_logic_vector(31 downto 0);
datain_a_09 : in std_logic_vector(31 downto 0);
datain_a_10 : in std_logic_vector(31 downto 0);
datain_a_11 : in std_logic_vector(31 downto 0);
datain_a_12 : in std_logic_vector(31 downto 0);
datain_a_13 : in std_logic_vector(31 downto 0);
datain_a_14 : in std_logic_vector(31 downto 0);
datain_a_15 : in std_logic_vector(31 downto 0);
datain_a_16 : in std_logic_vector(31 downto 0);
datain_a_17 : in std_logic_vector(31 downto 0);
datain_a_18 : in std_logic_vector(31 downto 0);
datain_a_19 : in std_logic_vector(31 downto 0);
datain_a_20 : in std_logic_vector(31 downto 0);
datain_a_21 : in std_logic_vector(31 downto 0);
datain_a_22 : in std_logic_vector(31 downto 0);
datain_a_23 : in std_logic_vector(31 downto 0);
datain_a_24 : in std_logic_vector(31 downto 0);
datain_a_25 : in std_logic_vector(31 downto 0);
datain_a_26 : in std_logic_vector(31 downto 0);
datain_a_27 : in std_logic_vector(31 downto 0);
datain_a_28 : in std_logic_vector(31 downto 0);
datain_a_29 : in std_logic_vector(31 downto 0);
datain_a_30 : in std_logic_vector(31 downto 0);
datain_a_31 : in std_logic_vector(31 downto 0);
datain_a_32 : in std_logic_vector(31 downto 0);
datain_a_33 : in std_logic_vector(31 downto 0);
datain_a_34 : in std_logic_vector(31 downto 0);
datain_a_35 : in std_logic_vector(31 downto 0);
datain_a_36 : in std_logic_vector(31 downto 0);
datain_a_37 : in std_logic_vector(31 downto 0);
datain_a_38 : in std_logic_vector(31 downto 0);
datain_a_39 : in std_logic_vector(31 downto 0);
datain_a_40 : in std_logic_vector(31 downto 0);
datain_a_41 : in std_logic_vector(31 downto 0);
datain_a_42 : in std_logic_vector(31 downto 0);
datain_a_43 : in std_logic_vector(31 downto 0);
datain_a_44 : in std_logic_vector(31 downto 0);
datain_a_45 : in std_logic_vector(31 downto 0);
datain_a_46 : in std_logic_vector(31 downto 0);
datain_a_47 : in std_logic_vector(31 downto 0);
datain_a_48 : in std_logic_vector(31 downto 0);
datain_a_49 : in std_logic_vector(31 downto 0);
datain_a_50 : in std_logic_vector(31 downto 0);
datain_a_51 : in std_logic_vector(31 downto 0);
datain_a_52 : in std_logic_vector(31 downto 0);
datain_a_53 : in std_logic_vector(31 downto 0);
datain_a_54 : in std_logic_vector(31 downto 0);
datain_a_55 : in std_logic_vector(31 downto 0);
datain_a_56 : in std_logic_vector(31 downto 0);
datain_a_57 : in std_logic_vector(31 downto 0);
datain_a_58 : in std_logic_vector(31 downto 0);
datain_a_59 : in std_logic_vector(31 downto 0);
datain_a_60 : in std_logic_vector(31 downto 0);
datain_a_61 : in std_logic_vector(31 downto 0);
datain_a_62 : in std_logic_vector(31 downto 0);
datain_a_63 : in std_logic_vector(31 downto 0);
datain_b_00 : in std_logic_vector(31 downto 0);
datain_b_01 : in std_logic_vector(31 downto 0);
datain_b_02 : in std_logic_vector(31 downto 0);
datain_b_03 : in std_logic_vector(31 downto 0);
datain_b_04 : in std_logic_vector(31 downto 0);
datain_b_05 : in std_logic_vector(31 downto 0);
datain_b_06 : in std_logic_vector(31 downto 0);
datain_b_07 : in std_logic_vector(31 downto 0);
datain_b_08 : in std_logic_vector(31 downto 0);
datain_b_09 : in std_logic_vector(31 downto 0);
datain_b_10 : in std_logic_vector(31 downto 0);
datain_b_11 : in std_logic_vector(31 downto 0);
datain_b_12 : in std_logic_vector(31 downto 0);
datain_b_13 : in std_logic_vector(31 downto 0);
datain_b_14 : in std_logic_vector(31 downto 0);
datain_b_15 : in std_logic_vector(31 downto 0);
datain_b_16 : in std_logic_vector(31 downto 0);
datain_b_17 : in std_logic_vector(31 downto 0);
datain_b_18 : in std_logic_vector(31 downto 0);
datain_b_19 : in std_logic_vector(31 downto 0);
datain_b_20 : in std_logic_vector(31 downto 0);
datain_b_21 : in std_logic_vector(31 downto 0);
datain_b_22 : in std_logic_vector(31 downto 0);
datain_b_23 : in std_logic_vector(31 downto 0);
datain_b_24 : in std_logic_vector(31 downto 0);
datain_b_25 : in std_logic_vector(31 downto 0);
datain_b_26 : in std_logic_vector(31 downto 0);
datain_b_27 : in std_logic_vector(31 downto 0);
datain_b_28 : in std_logic_vector(31 downto 0);
datain_b_29 : in std_logic_vector(31 downto 0);
datain_b_30 : in std_logic_vector(31 downto 0);
datain_b_31 : in std_logic_vector(31 downto 0);
datain_b_32 : in std_logic_vector(31 downto 0);
datain_b_33 : in std_logic_vector(31 downto 0);
datain_b_34 : in std_logic_vector(31 downto 0);
datain_b_35 : in std_logic_vector(31 downto 0);
datain_b_36 : in std_logic_vector(31 downto 0);
datain_b_37 : in std_logic_vector(31 downto 0);
datain_b_38 : in std_logic_vector(31 downto 0);
datain_b_39 : in std_logic_vector(31 downto 0);
datain_b_40 : in std_logic_vector(31 downto 0);
datain_b_41 : in std_logic_vector(31 downto 0);
datain_b_42 : in std_logic_vector(31 downto 0);
datain_b_43 : in std_logic_vector(31 downto 0);
datain_b_44 : in std_logic_vector(31 downto 0);
datain_b_45 : in std_logic_vector(31 downto 0);
datain_b_46 : in std_logic_vector(31 downto 0);
datain_b_47 : in std_logic_vector(31 downto 0);
datain_b_48 : in std_logic_vector(31 downto 0);
datain_b_49 : in std_logic_vector(31 downto 0);
datain_b_50 : in std_logic_vector(31 downto 0);
datain_b_51 : in std_logic_vector(31 downto 0);
datain_b_52 : in std_logic_vector(31 downto 0);
datain_b_53 : in std_logic_vector(31 downto 0);
datain_b_54 : in std_logic_vector(31 downto 0);
datain_b_55 : in std_logic_vector(31 downto 0);
datain_b_56 : in std_logic_vector(31 downto 0);
datain_b_57 : in std_logic_vector(31 downto 0);
datain_b_58 : in std_logic_vector(31 downto 0);
datain_b_59 : in std_logic_vector(31 downto 0);
datain_b_60 : in std_logic_vector(31 downto 0);
datain_b_61 : in std_logic_vector(31 downto 0);
datain_b_62 : in std_logic_vector(31 downto 0);
datain_b_63 : in std_logic_vector(31 downto 0);
dout_s : out std_logic_vector(31 downto 0);
v_s : in std_logic_vector(0 downto 0);
vout_s : out std_logic_vector(0 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
SIGNAL v_in : std_logic_vector(0 downto 0);
SIGNAL v_out : std_logic_vector(0 downto 0);
BEGIN
reset <= NOT resetn;
v_in <= "1" when (valid_in = '1') else "0";
cmp0: dotProduct64_dut
PORT MAP (clk=>clock, areset=>reset, h_areset => reset, v_s=>v_in,
vout_s=>v_out, dout_s=>res, c_s => "00000000",
datain_a_00 => a0(32 DOWNTO 1),
datain_b_00 => b0(32 DOWNTO 1),
datain_a_01 => a0(64 DOWNTO 33),
datain_b_01 => b0(64 DOWNTO 33),
datain_a_02 => a0(96 DOWNTO 65),
datain_b_02 => b0(96 DOWNTO 65),
datain_a_03 => a0(128 DOWNTO 97),
datain_b_03 => b0(128 DOWNTO 97),
datain_a_04 => a0(160 DOWNTO 129),
datain_b_04 => b0(160 DOWNTO 129),
datain_a_05 => a0(192 DOWNTO 161),
datain_b_05 => b0(192 DOWNTO 161),
datain_a_06 => a0(224 DOWNTO 193),
datain_b_06 => b0(224 DOWNTO 193),
datain_a_07 => a0(256 DOWNTO 225),
datain_b_07 => b0(256 DOWNTO 225),
datain_a_08 => a0(288 DOWNTO 257),
datain_b_08 => b0(288 DOWNTO 257),
datain_a_09 => a0(320 DOWNTO 289),
datain_b_09 => b0(320 DOWNTO 289),
datain_a_10 => a0(352 DOWNTO 321),
datain_b_10 => b0(352 DOWNTO 321),
datain_a_11 => a0(384 DOWNTO 353),
datain_b_11 => b0(384 DOWNTO 353),
datain_a_12 => a0(416 DOWNTO 385),
datain_b_12 => b0(416 DOWNTO 385),
datain_a_13 => a0(448 DOWNTO 417),
datain_b_13 => b0(448 DOWNTO 417),
datain_a_14 => a0(480 DOWNTO 449),
datain_b_14 => b0(480 DOWNTO 449),
datain_a_15 => a0(512 DOWNTO 481),
datain_b_15 => b0(512 DOWNTO 481),
datain_a_16 => a1(32 DOWNTO 1),
datain_b_16 => b1(32 DOWNTO 1),
datain_a_17 => a1(64 DOWNTO 33),
datain_b_17 => b1(64 DOWNTO 33),
datain_a_18 => a1(96 DOWNTO 65),
datain_b_18 => b1(96 DOWNTO 65),
datain_a_19 => a1(128 DOWNTO 97),
datain_b_19 => b1(128 DOWNTO 97),
datain_a_20 => a1(160 DOWNTO 129),
datain_b_20 => b1(160 DOWNTO 129),
datain_a_21 => a1(192 DOWNTO 161),
datain_b_21 => b1(192 DOWNTO 161),
datain_a_22 => a1(224 DOWNTO 193),
datain_b_22 => b1(224 DOWNTO 193),
datain_a_23 => a1(256 DOWNTO 225),
datain_b_23 => b1(256 DOWNTO 225),
datain_a_24 => a1(288 DOWNTO 257),
datain_b_24 => b1(288 DOWNTO 257),
datain_a_25 => a1(320 DOWNTO 289),
datain_b_25 => b1(320 DOWNTO 289),
datain_a_26 => a1(352 DOWNTO 321),
datain_b_26 => b1(352 DOWNTO 321),
datain_a_27 => a1(384 DOWNTO 353),
datain_b_27 => b1(384 DOWNTO 353),
datain_a_28 => a1(416 DOWNTO 385),
datain_b_28 => b1(416 DOWNTO 385),
datain_a_29 => a1(448 DOWNTO 417),
datain_b_29 => b1(448 DOWNTO 417),
datain_a_30 => a1(480 DOWNTO 449),
datain_b_30 => b1(480 DOWNTO 449),
datain_a_31 => a1(512 DOWNTO 481),
datain_b_31 => b1(512 DOWNTO 481),
datain_a_32 => a2(32 DOWNTO 1),
datain_b_32 => b2(32 DOWNTO 1),
datain_a_33 => a2(64 DOWNTO 33),
datain_b_33 => b2(64 DOWNTO 33),
datain_a_34 => a2(96 DOWNTO 65),
datain_b_34 => b2(96 DOWNTO 65),
datain_a_35 => a2(128 DOWNTO 97),
datain_b_35 => b2(128 DOWNTO 97),
datain_a_36 => a2(160 DOWNTO 129),
datain_b_36 => b2(160 DOWNTO 129),
datain_a_37 => a2(192 DOWNTO 161),
datain_b_37 => b2(192 DOWNTO 161),
datain_a_38 => a2(224 DOWNTO 193),
datain_b_38 => b2(224 DOWNTO 193),
datain_a_39 => a2(256 DOWNTO 225),
datain_b_39 => b2(256 DOWNTO 225),
datain_a_40 => a2(288 DOWNTO 257),
datain_b_40 => b2(288 DOWNTO 257),
datain_a_41 => a2(320 DOWNTO 289),
datain_b_41 => b2(320 DOWNTO 289),
datain_a_42 => a2(352 DOWNTO 321),
datain_b_42 => b2(352 DOWNTO 321),
datain_a_43 => a2(384 DOWNTO 353),
datain_b_43 => b2(384 DOWNTO 353),
datain_a_44 => a2(416 DOWNTO 385),
datain_b_44 => b2(416 DOWNTO 385),
datain_a_45 => a2(448 DOWNTO 417),
datain_b_45 => b2(448 DOWNTO 417),
datain_a_46 => a2(480 DOWNTO 449),
datain_b_46 => b2(480 DOWNTO 449),
datain_a_47 => a2(512 DOWNTO 481),
datain_b_47 => b2(512 DOWNTO 481),
datain_a_48 => a3(32 DOWNTO 1),
datain_b_48 => b3(32 DOWNTO 1),
datain_a_49 => a3(64 DOWNTO 33),
datain_b_49 => b3(64 DOWNTO 33),
datain_a_50 => a3(96 DOWNTO 65),
datain_b_50 => b3(96 DOWNTO 65),
datain_a_51 => a3(128 DOWNTO 97),
datain_b_51 => b3(128 DOWNTO 97),
datain_a_52 => a3(160 DOWNTO 129),
datain_b_52 => b3(160 DOWNTO 129),
datain_a_53 => a3(192 DOWNTO 161),
datain_b_53 => b3(192 DOWNTO 161),
datain_a_54 => a3(224 DOWNTO 193),
datain_b_54 => b3(224 DOWNTO 193),
datain_a_55 => a3(256 DOWNTO 225),
datain_b_55 => b3(256 DOWNTO 225),
datain_a_56 => a3(288 DOWNTO 257),
datain_b_56 => b3(288 DOWNTO 257),
datain_a_57 => a3(320 DOWNTO 289),
datain_b_57 => b3(320 DOWNTO 289),
datain_a_58 => a3(352 DOWNTO 321),
datain_b_58 => b3(352 DOWNTO 321),
datain_a_59 => a3(384 DOWNTO 353),
datain_b_59 => b3(384 DOWNTO 353),
datain_a_60 => a3(416 DOWNTO 385),
datain_b_60 => b3(416 DOWNTO 385),
datain_a_61 => a3(448 DOWNTO 417),
datain_b_61 => b3(448 DOWNTO 417),
datain_a_62 => a3(480 DOWNTO 449),
datain_b_62 => b3(480 DOWNTO 449),
datain_a_63 => a3(512 DOWNTO 481),
datain_b_63 => b3(512 DOWNTO 481));
done <= '1' when (v_out = "1") else '0';
result <= res;
valid_out <= done;
END gen;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core_sv IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core_sv;
ARCHITECTURE gen OF dotp_core_sv IS
COMPONENT dotProduct64_dut is
port (
c_s : in std_logic_vector(7 downto 0);
cout_s : out std_logic_vector(7 downto 0);
datain_a_00 : in std_logic_vector(31 downto 0);
datain_a_01 : in std_logic_vector(31 downto 0);
datain_a_02 : in std_logic_vector(31 downto 0);
datain_a_03 : in std_logic_vector(31 downto 0);
datain_a_04 : in std_logic_vector(31 downto 0);
datain_a_05 : in std_logic_vector(31 downto 0);
datain_a_06 : in std_logic_vector(31 downto 0);
datain_a_07 : in std_logic_vector(31 downto 0);
datain_a_08 : in std_logic_vector(31 downto 0);
datain_a_09 : in std_logic_vector(31 downto 0);
datain_a_10 : in std_logic_vector(31 downto 0);
datain_a_11 : in std_logic_vector(31 downto 0);
datain_a_12 : in std_logic_vector(31 downto 0);
datain_a_13 : in std_logic_vector(31 downto 0);
datain_a_14 : in std_logic_vector(31 downto 0);
datain_a_15 : in std_logic_vector(31 downto 0);
datain_a_16 : in std_logic_vector(31 downto 0);
datain_a_17 : in std_logic_vector(31 downto 0);
datain_a_18 : in std_logic_vector(31 downto 0);
datain_a_19 : in std_logic_vector(31 downto 0);
datain_a_20 : in std_logic_vector(31 downto 0);
datain_a_21 : in std_logic_vector(31 downto 0);
datain_a_22 : in std_logic_vector(31 downto 0);
datain_a_23 : in std_logic_vector(31 downto 0);
datain_a_24 : in std_logic_vector(31 downto 0);
datain_a_25 : in std_logic_vector(31 downto 0);
datain_a_26 : in std_logic_vector(31 downto 0);
datain_a_27 : in std_logic_vector(31 downto 0);
datain_a_28 : in std_logic_vector(31 downto 0);
datain_a_29 : in std_logic_vector(31 downto 0);
datain_a_30 : in std_logic_vector(31 downto 0);
datain_a_31 : in std_logic_vector(31 downto 0);
datain_a_32 : in std_logic_vector(31 downto 0);
datain_a_33 : in std_logic_vector(31 downto 0);
datain_a_34 : in std_logic_vector(31 downto 0);
datain_a_35 : in std_logic_vector(31 downto 0);
datain_a_36 : in std_logic_vector(31 downto 0);
datain_a_37 : in std_logic_vector(31 downto 0);
datain_a_38 : in std_logic_vector(31 downto 0);
datain_a_39 : in std_logic_vector(31 downto 0);
datain_a_40 : in std_logic_vector(31 downto 0);
datain_a_41 : in std_logic_vector(31 downto 0);
datain_a_42 : in std_logic_vector(31 downto 0);
datain_a_43 : in std_logic_vector(31 downto 0);
datain_a_44 : in std_logic_vector(31 downto 0);
datain_a_45 : in std_logic_vector(31 downto 0);
datain_a_46 : in std_logic_vector(31 downto 0);
datain_a_47 : in std_logic_vector(31 downto 0);
datain_a_48 : in std_logic_vector(31 downto 0);
datain_a_49 : in std_logic_vector(31 downto 0);
datain_a_50 : in std_logic_vector(31 downto 0);
datain_a_51 : in std_logic_vector(31 downto 0);
datain_a_52 : in std_logic_vector(31 downto 0);
datain_a_53 : in std_logic_vector(31 downto 0);
datain_a_54 : in std_logic_vector(31 downto 0);
datain_a_55 : in std_logic_vector(31 downto 0);
datain_a_56 : in std_logic_vector(31 downto 0);
datain_a_57 : in std_logic_vector(31 downto 0);
datain_a_58 : in std_logic_vector(31 downto 0);
datain_a_59 : in std_logic_vector(31 downto 0);
datain_a_60 : in std_logic_vector(31 downto 0);
datain_a_61 : in std_logic_vector(31 downto 0);
datain_a_62 : in std_logic_vector(31 downto 0);
datain_a_63 : in std_logic_vector(31 downto 0);
datain_b_00 : in std_logic_vector(31 downto 0);
datain_b_01 : in std_logic_vector(31 downto 0);
datain_b_02 : in std_logic_vector(31 downto 0);
datain_b_03 : in std_logic_vector(31 downto 0);
datain_b_04 : in std_logic_vector(31 downto 0);
datain_b_05 : in std_logic_vector(31 downto 0);
datain_b_06 : in std_logic_vector(31 downto 0);
datain_b_07 : in std_logic_vector(31 downto 0);
datain_b_08 : in std_logic_vector(31 downto 0);
datain_b_09 : in std_logic_vector(31 downto 0);
datain_b_10 : in std_logic_vector(31 downto 0);
datain_b_11 : in std_logic_vector(31 downto 0);
datain_b_12 : in std_logic_vector(31 downto 0);
datain_b_13 : in std_logic_vector(31 downto 0);
datain_b_14 : in std_logic_vector(31 downto 0);
datain_b_15 : in std_logic_vector(31 downto 0);
datain_b_16 : in std_logic_vector(31 downto 0);
datain_b_17 : in std_logic_vector(31 downto 0);
datain_b_18 : in std_logic_vector(31 downto 0);
datain_b_19 : in std_logic_vector(31 downto 0);
datain_b_20 : in std_logic_vector(31 downto 0);
datain_b_21 : in std_logic_vector(31 downto 0);
datain_b_22 : in std_logic_vector(31 downto 0);
datain_b_23 : in std_logic_vector(31 downto 0);
datain_b_24 : in std_logic_vector(31 downto 0);
datain_b_25 : in std_logic_vector(31 downto 0);
datain_b_26 : in std_logic_vector(31 downto 0);
datain_b_27 : in std_logic_vector(31 downto 0);
datain_b_28 : in std_logic_vector(31 downto 0);
datain_b_29 : in std_logic_vector(31 downto 0);
datain_b_30 : in std_logic_vector(31 downto 0);
datain_b_31 : in std_logic_vector(31 downto 0);
datain_b_32 : in std_logic_vector(31 downto 0);
datain_b_33 : in std_logic_vector(31 downto 0);
datain_b_34 : in std_logic_vector(31 downto 0);
datain_b_35 : in std_logic_vector(31 downto 0);
datain_b_36 : in std_logic_vector(31 downto 0);
datain_b_37 : in std_logic_vector(31 downto 0);
datain_b_38 : in std_logic_vector(31 downto 0);
datain_b_39 : in std_logic_vector(31 downto 0);
datain_b_40 : in std_logic_vector(31 downto 0);
datain_b_41 : in std_logic_vector(31 downto 0);
datain_b_42 : in std_logic_vector(31 downto 0);
datain_b_43 : in std_logic_vector(31 downto 0);
datain_b_44 : in std_logic_vector(31 downto 0);
datain_b_45 : in std_logic_vector(31 downto 0);
datain_b_46 : in std_logic_vector(31 downto 0);
datain_b_47 : in std_logic_vector(31 downto 0);
datain_b_48 : in std_logic_vector(31 downto 0);
datain_b_49 : in std_logic_vector(31 downto 0);
datain_b_50 : in std_logic_vector(31 downto 0);
datain_b_51 : in std_logic_vector(31 downto 0);
datain_b_52 : in std_logic_vector(31 downto 0);
datain_b_53 : in std_logic_vector(31 downto 0);
datain_b_54 : in std_logic_vector(31 downto 0);
datain_b_55 : in std_logic_vector(31 downto 0);
datain_b_56 : in std_logic_vector(31 downto 0);
datain_b_57 : in std_logic_vector(31 downto 0);
datain_b_58 : in std_logic_vector(31 downto 0);
datain_b_59 : in std_logic_vector(31 downto 0);
datain_b_60 : in std_logic_vector(31 downto 0);
datain_b_61 : in std_logic_vector(31 downto 0);
datain_b_62 : in std_logic_vector(31 downto 0);
datain_b_63 : in std_logic_vector(31 downto 0);
dout_s : out std_logic_vector(31 downto 0);
v_s : in std_logic_vector(0 downto 0);
vout_s : out std_logic_vector(0 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
SIGNAL v_in : std_logic_vector(0 downto 0);
SIGNAL v_out : std_logic_vector(0 downto 0);
BEGIN
reset <= NOT resetn;
v_in <= "1" when (valid_in = '1') else "0";
cmp0: dotProduct64_dut
PORT MAP (clk=>clock, areset=>reset, h_areset => reset, v_s=>v_in,
vout_s=>v_out, dout_s=>res, c_s => "00000000",
datain_a_00 => a0(32 DOWNTO 1),
datain_b_00 => b0(32 DOWNTO 1),
datain_a_01 => a0(64 DOWNTO 33),
datain_b_01 => b0(64 DOWNTO 33),
datain_a_02 => a0(96 DOWNTO 65),
datain_b_02 => b0(96 DOWNTO 65),
datain_a_03 => a0(128 DOWNTO 97),
datain_b_03 => b0(128 DOWNTO 97),
datain_a_04 => a0(160 DOWNTO 129),
datain_b_04 => b0(160 DOWNTO 129),
datain_a_05 => a0(192 DOWNTO 161),
datain_b_05 => b0(192 DOWNTO 161),
datain_a_06 => a0(224 DOWNTO 193),
datain_b_06 => b0(224 DOWNTO 193),
datain_a_07 => a0(256 DOWNTO 225),
datain_b_07 => b0(256 DOWNTO 225),
datain_a_08 => a0(288 DOWNTO 257),
datain_b_08 => b0(288 DOWNTO 257),
datain_a_09 => a0(320 DOWNTO 289),
datain_b_09 => b0(320 DOWNTO 289),
datain_a_10 => a0(352 DOWNTO 321),
datain_b_10 => b0(352 DOWNTO 321),
datain_a_11 => a0(384 DOWNTO 353),
datain_b_11 => b0(384 DOWNTO 353),
datain_a_12 => a0(416 DOWNTO 385),
datain_b_12 => b0(416 DOWNTO 385),
datain_a_13 => a0(448 DOWNTO 417),
datain_b_13 => b0(448 DOWNTO 417),
datain_a_14 => a0(480 DOWNTO 449),
datain_b_14 => b0(480 DOWNTO 449),
datain_a_15 => a0(512 DOWNTO 481),
datain_b_15 => b0(512 DOWNTO 481),
datain_a_16 => a1(32 DOWNTO 1),
datain_b_16 => b1(32 DOWNTO 1),
datain_a_17 => a1(64 DOWNTO 33),
datain_b_17 => b1(64 DOWNTO 33),
datain_a_18 => a1(96 DOWNTO 65),
datain_b_18 => b1(96 DOWNTO 65),
datain_a_19 => a1(128 DOWNTO 97),
datain_b_19 => b1(128 DOWNTO 97),
datain_a_20 => a1(160 DOWNTO 129),
datain_b_20 => b1(160 DOWNTO 129),
datain_a_21 => a1(192 DOWNTO 161),
datain_b_21 => b1(192 DOWNTO 161),
datain_a_22 => a1(224 DOWNTO 193),
datain_b_22 => b1(224 DOWNTO 193),
datain_a_23 => a1(256 DOWNTO 225),
datain_b_23 => b1(256 DOWNTO 225),
datain_a_24 => a1(288 DOWNTO 257),
datain_b_24 => b1(288 DOWNTO 257),
datain_a_25 => a1(320 DOWNTO 289),
datain_b_25 => b1(320 DOWNTO 289),
datain_a_26 => a1(352 DOWNTO 321),
datain_b_26 => b1(352 DOWNTO 321),
datain_a_27 => a1(384 DOWNTO 353),
datain_b_27 => b1(384 DOWNTO 353),
datain_a_28 => a1(416 DOWNTO 385),
datain_b_28 => b1(416 DOWNTO 385),
datain_a_29 => a1(448 DOWNTO 417),
datain_b_29 => b1(448 DOWNTO 417),
datain_a_30 => a1(480 DOWNTO 449),
datain_b_30 => b1(480 DOWNTO 449),
datain_a_31 => a1(512 DOWNTO 481),
datain_b_31 => b1(512 DOWNTO 481),
datain_a_32 => a2(32 DOWNTO 1),
datain_b_32 => b2(32 DOWNTO 1),
datain_a_33 => a2(64 DOWNTO 33),
datain_b_33 => b2(64 DOWNTO 33),
datain_a_34 => a2(96 DOWNTO 65),
datain_b_34 => b2(96 DOWNTO 65),
datain_a_35 => a2(128 DOWNTO 97),
datain_b_35 => b2(128 DOWNTO 97),
datain_a_36 => a2(160 DOWNTO 129),
datain_b_36 => b2(160 DOWNTO 129),
datain_a_37 => a2(192 DOWNTO 161),
datain_b_37 => b2(192 DOWNTO 161),
datain_a_38 => a2(224 DOWNTO 193),
datain_b_38 => b2(224 DOWNTO 193),
datain_a_39 => a2(256 DOWNTO 225),
datain_b_39 => b2(256 DOWNTO 225),
datain_a_40 => a2(288 DOWNTO 257),
datain_b_40 => b2(288 DOWNTO 257),
datain_a_41 => a2(320 DOWNTO 289),
datain_b_41 => b2(320 DOWNTO 289),
datain_a_42 => a2(352 DOWNTO 321),
datain_b_42 => b2(352 DOWNTO 321),
datain_a_43 => a2(384 DOWNTO 353),
datain_b_43 => b2(384 DOWNTO 353),
datain_a_44 => a2(416 DOWNTO 385),
datain_b_44 => b2(416 DOWNTO 385),
datain_a_45 => a2(448 DOWNTO 417),
datain_b_45 => b2(448 DOWNTO 417),
datain_a_46 => a2(480 DOWNTO 449),
datain_b_46 => b2(480 DOWNTO 449),
datain_a_47 => a2(512 DOWNTO 481),
datain_b_47 => b2(512 DOWNTO 481),
datain_a_48 => a3(32 DOWNTO 1),
datain_b_48 => b3(32 DOWNTO 1),
datain_a_49 => a3(64 DOWNTO 33),
datain_b_49 => b3(64 DOWNTO 33),
datain_a_50 => a3(96 DOWNTO 65),
datain_b_50 => b3(96 DOWNTO 65),
datain_a_51 => a3(128 DOWNTO 97),
datain_b_51 => b3(128 DOWNTO 97),
datain_a_52 => a3(160 DOWNTO 129),
datain_b_52 => b3(160 DOWNTO 129),
datain_a_53 => a3(192 DOWNTO 161),
datain_b_53 => b3(192 DOWNTO 161),
datain_a_54 => a3(224 DOWNTO 193),
datain_b_54 => b3(224 DOWNTO 193),
datain_a_55 => a3(256 DOWNTO 225),
datain_b_55 => b3(256 DOWNTO 225),
datain_a_56 => a3(288 DOWNTO 257),
datain_b_56 => b3(288 DOWNTO 257),
datain_a_57 => a3(320 DOWNTO 289),
datain_b_57 => b3(320 DOWNTO 289),
datain_a_58 => a3(352 DOWNTO 321),
datain_b_58 => b3(352 DOWNTO 321),
datain_a_59 => a3(384 DOWNTO 353),
datain_b_59 => b3(384 DOWNTO 353),
datain_a_60 => a3(416 DOWNTO 385),
datain_b_60 => b3(416 DOWNTO 385),
datain_a_61 => a3(448 DOWNTO 417),
datain_b_61 => b3(448 DOWNTO 417),
datain_a_62 => a3(480 DOWNTO 449),
datain_b_62 => b3(480 DOWNTO 449),
datain_a_63 => a3(512 DOWNTO 481),
datain_b_63 => b3(512 DOWNTO 481));
done <= '1' when (v_out = "1") else '0';
result <= res;
valid_out <= done;
END gen;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core_sv IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core_sv;
ARCHITECTURE gen OF dotp_core_sv IS
COMPONENT dotProduct64_dut is
port (
c_s : in std_logic_vector(7 downto 0);
cout_s : out std_logic_vector(7 downto 0);
datain_a_00 : in std_logic_vector(31 downto 0);
datain_a_01 : in std_logic_vector(31 downto 0);
datain_a_02 : in std_logic_vector(31 downto 0);
datain_a_03 : in std_logic_vector(31 downto 0);
datain_a_04 : in std_logic_vector(31 downto 0);
datain_a_05 : in std_logic_vector(31 downto 0);
datain_a_06 : in std_logic_vector(31 downto 0);
datain_a_07 : in std_logic_vector(31 downto 0);
datain_a_08 : in std_logic_vector(31 downto 0);
datain_a_09 : in std_logic_vector(31 downto 0);
datain_a_10 : in std_logic_vector(31 downto 0);
datain_a_11 : in std_logic_vector(31 downto 0);
datain_a_12 : in std_logic_vector(31 downto 0);
datain_a_13 : in std_logic_vector(31 downto 0);
datain_a_14 : in std_logic_vector(31 downto 0);
datain_a_15 : in std_logic_vector(31 downto 0);
datain_a_16 : in std_logic_vector(31 downto 0);
datain_a_17 : in std_logic_vector(31 downto 0);
datain_a_18 : in std_logic_vector(31 downto 0);
datain_a_19 : in std_logic_vector(31 downto 0);
datain_a_20 : in std_logic_vector(31 downto 0);
datain_a_21 : in std_logic_vector(31 downto 0);
datain_a_22 : in std_logic_vector(31 downto 0);
datain_a_23 : in std_logic_vector(31 downto 0);
datain_a_24 : in std_logic_vector(31 downto 0);
datain_a_25 : in std_logic_vector(31 downto 0);
datain_a_26 : in std_logic_vector(31 downto 0);
datain_a_27 : in std_logic_vector(31 downto 0);
datain_a_28 : in std_logic_vector(31 downto 0);
datain_a_29 : in std_logic_vector(31 downto 0);
datain_a_30 : in std_logic_vector(31 downto 0);
datain_a_31 : in std_logic_vector(31 downto 0);
datain_a_32 : in std_logic_vector(31 downto 0);
datain_a_33 : in std_logic_vector(31 downto 0);
datain_a_34 : in std_logic_vector(31 downto 0);
datain_a_35 : in std_logic_vector(31 downto 0);
datain_a_36 : in std_logic_vector(31 downto 0);
datain_a_37 : in std_logic_vector(31 downto 0);
datain_a_38 : in std_logic_vector(31 downto 0);
datain_a_39 : in std_logic_vector(31 downto 0);
datain_a_40 : in std_logic_vector(31 downto 0);
datain_a_41 : in std_logic_vector(31 downto 0);
datain_a_42 : in std_logic_vector(31 downto 0);
datain_a_43 : in std_logic_vector(31 downto 0);
datain_a_44 : in std_logic_vector(31 downto 0);
datain_a_45 : in std_logic_vector(31 downto 0);
datain_a_46 : in std_logic_vector(31 downto 0);
datain_a_47 : in std_logic_vector(31 downto 0);
datain_a_48 : in std_logic_vector(31 downto 0);
datain_a_49 : in std_logic_vector(31 downto 0);
datain_a_50 : in std_logic_vector(31 downto 0);
datain_a_51 : in std_logic_vector(31 downto 0);
datain_a_52 : in std_logic_vector(31 downto 0);
datain_a_53 : in std_logic_vector(31 downto 0);
datain_a_54 : in std_logic_vector(31 downto 0);
datain_a_55 : in std_logic_vector(31 downto 0);
datain_a_56 : in std_logic_vector(31 downto 0);
datain_a_57 : in std_logic_vector(31 downto 0);
datain_a_58 : in std_logic_vector(31 downto 0);
datain_a_59 : in std_logic_vector(31 downto 0);
datain_a_60 : in std_logic_vector(31 downto 0);
datain_a_61 : in std_logic_vector(31 downto 0);
datain_a_62 : in std_logic_vector(31 downto 0);
datain_a_63 : in std_logic_vector(31 downto 0);
datain_b_00 : in std_logic_vector(31 downto 0);
datain_b_01 : in std_logic_vector(31 downto 0);
datain_b_02 : in std_logic_vector(31 downto 0);
datain_b_03 : in std_logic_vector(31 downto 0);
datain_b_04 : in std_logic_vector(31 downto 0);
datain_b_05 : in std_logic_vector(31 downto 0);
datain_b_06 : in std_logic_vector(31 downto 0);
datain_b_07 : in std_logic_vector(31 downto 0);
datain_b_08 : in std_logic_vector(31 downto 0);
datain_b_09 : in std_logic_vector(31 downto 0);
datain_b_10 : in std_logic_vector(31 downto 0);
datain_b_11 : in std_logic_vector(31 downto 0);
datain_b_12 : in std_logic_vector(31 downto 0);
datain_b_13 : in std_logic_vector(31 downto 0);
datain_b_14 : in std_logic_vector(31 downto 0);
datain_b_15 : in std_logic_vector(31 downto 0);
datain_b_16 : in std_logic_vector(31 downto 0);
datain_b_17 : in std_logic_vector(31 downto 0);
datain_b_18 : in std_logic_vector(31 downto 0);
datain_b_19 : in std_logic_vector(31 downto 0);
datain_b_20 : in std_logic_vector(31 downto 0);
datain_b_21 : in std_logic_vector(31 downto 0);
datain_b_22 : in std_logic_vector(31 downto 0);
datain_b_23 : in std_logic_vector(31 downto 0);
datain_b_24 : in std_logic_vector(31 downto 0);
datain_b_25 : in std_logic_vector(31 downto 0);
datain_b_26 : in std_logic_vector(31 downto 0);
datain_b_27 : in std_logic_vector(31 downto 0);
datain_b_28 : in std_logic_vector(31 downto 0);
datain_b_29 : in std_logic_vector(31 downto 0);
datain_b_30 : in std_logic_vector(31 downto 0);
datain_b_31 : in std_logic_vector(31 downto 0);
datain_b_32 : in std_logic_vector(31 downto 0);
datain_b_33 : in std_logic_vector(31 downto 0);
datain_b_34 : in std_logic_vector(31 downto 0);
datain_b_35 : in std_logic_vector(31 downto 0);
datain_b_36 : in std_logic_vector(31 downto 0);
datain_b_37 : in std_logic_vector(31 downto 0);
datain_b_38 : in std_logic_vector(31 downto 0);
datain_b_39 : in std_logic_vector(31 downto 0);
datain_b_40 : in std_logic_vector(31 downto 0);
datain_b_41 : in std_logic_vector(31 downto 0);
datain_b_42 : in std_logic_vector(31 downto 0);
datain_b_43 : in std_logic_vector(31 downto 0);
datain_b_44 : in std_logic_vector(31 downto 0);
datain_b_45 : in std_logic_vector(31 downto 0);
datain_b_46 : in std_logic_vector(31 downto 0);
datain_b_47 : in std_logic_vector(31 downto 0);
datain_b_48 : in std_logic_vector(31 downto 0);
datain_b_49 : in std_logic_vector(31 downto 0);
datain_b_50 : in std_logic_vector(31 downto 0);
datain_b_51 : in std_logic_vector(31 downto 0);
datain_b_52 : in std_logic_vector(31 downto 0);
datain_b_53 : in std_logic_vector(31 downto 0);
datain_b_54 : in std_logic_vector(31 downto 0);
datain_b_55 : in std_logic_vector(31 downto 0);
datain_b_56 : in std_logic_vector(31 downto 0);
datain_b_57 : in std_logic_vector(31 downto 0);
datain_b_58 : in std_logic_vector(31 downto 0);
datain_b_59 : in std_logic_vector(31 downto 0);
datain_b_60 : in std_logic_vector(31 downto 0);
datain_b_61 : in std_logic_vector(31 downto 0);
datain_b_62 : in std_logic_vector(31 downto 0);
datain_b_63 : in std_logic_vector(31 downto 0);
dout_s : out std_logic_vector(31 downto 0);
v_s : in std_logic_vector(0 downto 0);
vout_s : out std_logic_vector(0 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
SIGNAL v_in : std_logic_vector(0 downto 0);
SIGNAL v_out : std_logic_vector(0 downto 0);
BEGIN
reset <= NOT resetn;
v_in <= "1" when (valid_in = '1') else "0";
cmp0: dotProduct64_dut
PORT MAP (clk=>clock, areset=>reset, h_areset => reset, v_s=>v_in,
vout_s=>v_out, dout_s=>res, c_s => "00000000",
datain_a_00 => a0(32 DOWNTO 1),
datain_b_00 => b0(32 DOWNTO 1),
datain_a_01 => a0(64 DOWNTO 33),
datain_b_01 => b0(64 DOWNTO 33),
datain_a_02 => a0(96 DOWNTO 65),
datain_b_02 => b0(96 DOWNTO 65),
datain_a_03 => a0(128 DOWNTO 97),
datain_b_03 => b0(128 DOWNTO 97),
datain_a_04 => a0(160 DOWNTO 129),
datain_b_04 => b0(160 DOWNTO 129),
datain_a_05 => a0(192 DOWNTO 161),
datain_b_05 => b0(192 DOWNTO 161),
datain_a_06 => a0(224 DOWNTO 193),
datain_b_06 => b0(224 DOWNTO 193),
datain_a_07 => a0(256 DOWNTO 225),
datain_b_07 => b0(256 DOWNTO 225),
datain_a_08 => a0(288 DOWNTO 257),
datain_b_08 => b0(288 DOWNTO 257),
datain_a_09 => a0(320 DOWNTO 289),
datain_b_09 => b0(320 DOWNTO 289),
datain_a_10 => a0(352 DOWNTO 321),
datain_b_10 => b0(352 DOWNTO 321),
datain_a_11 => a0(384 DOWNTO 353),
datain_b_11 => b0(384 DOWNTO 353),
datain_a_12 => a0(416 DOWNTO 385),
datain_b_12 => b0(416 DOWNTO 385),
datain_a_13 => a0(448 DOWNTO 417),
datain_b_13 => b0(448 DOWNTO 417),
datain_a_14 => a0(480 DOWNTO 449),
datain_b_14 => b0(480 DOWNTO 449),
datain_a_15 => a0(512 DOWNTO 481),
datain_b_15 => b0(512 DOWNTO 481),
datain_a_16 => a1(32 DOWNTO 1),
datain_b_16 => b1(32 DOWNTO 1),
datain_a_17 => a1(64 DOWNTO 33),
datain_b_17 => b1(64 DOWNTO 33),
datain_a_18 => a1(96 DOWNTO 65),
datain_b_18 => b1(96 DOWNTO 65),
datain_a_19 => a1(128 DOWNTO 97),
datain_b_19 => b1(128 DOWNTO 97),
datain_a_20 => a1(160 DOWNTO 129),
datain_b_20 => b1(160 DOWNTO 129),
datain_a_21 => a1(192 DOWNTO 161),
datain_b_21 => b1(192 DOWNTO 161),
datain_a_22 => a1(224 DOWNTO 193),
datain_b_22 => b1(224 DOWNTO 193),
datain_a_23 => a1(256 DOWNTO 225),
datain_b_23 => b1(256 DOWNTO 225),
datain_a_24 => a1(288 DOWNTO 257),
datain_b_24 => b1(288 DOWNTO 257),
datain_a_25 => a1(320 DOWNTO 289),
datain_b_25 => b1(320 DOWNTO 289),
datain_a_26 => a1(352 DOWNTO 321),
datain_b_26 => b1(352 DOWNTO 321),
datain_a_27 => a1(384 DOWNTO 353),
datain_b_27 => b1(384 DOWNTO 353),
datain_a_28 => a1(416 DOWNTO 385),
datain_b_28 => b1(416 DOWNTO 385),
datain_a_29 => a1(448 DOWNTO 417),
datain_b_29 => b1(448 DOWNTO 417),
datain_a_30 => a1(480 DOWNTO 449),
datain_b_30 => b1(480 DOWNTO 449),
datain_a_31 => a1(512 DOWNTO 481),
datain_b_31 => b1(512 DOWNTO 481),
datain_a_32 => a2(32 DOWNTO 1),
datain_b_32 => b2(32 DOWNTO 1),
datain_a_33 => a2(64 DOWNTO 33),
datain_b_33 => b2(64 DOWNTO 33),
datain_a_34 => a2(96 DOWNTO 65),
datain_b_34 => b2(96 DOWNTO 65),
datain_a_35 => a2(128 DOWNTO 97),
datain_b_35 => b2(128 DOWNTO 97),
datain_a_36 => a2(160 DOWNTO 129),
datain_b_36 => b2(160 DOWNTO 129),
datain_a_37 => a2(192 DOWNTO 161),
datain_b_37 => b2(192 DOWNTO 161),
datain_a_38 => a2(224 DOWNTO 193),
datain_b_38 => b2(224 DOWNTO 193),
datain_a_39 => a2(256 DOWNTO 225),
datain_b_39 => b2(256 DOWNTO 225),
datain_a_40 => a2(288 DOWNTO 257),
datain_b_40 => b2(288 DOWNTO 257),
datain_a_41 => a2(320 DOWNTO 289),
datain_b_41 => b2(320 DOWNTO 289),
datain_a_42 => a2(352 DOWNTO 321),
datain_b_42 => b2(352 DOWNTO 321),
datain_a_43 => a2(384 DOWNTO 353),
datain_b_43 => b2(384 DOWNTO 353),
datain_a_44 => a2(416 DOWNTO 385),
datain_b_44 => b2(416 DOWNTO 385),
datain_a_45 => a2(448 DOWNTO 417),
datain_b_45 => b2(448 DOWNTO 417),
datain_a_46 => a2(480 DOWNTO 449),
datain_b_46 => b2(480 DOWNTO 449),
datain_a_47 => a2(512 DOWNTO 481),
datain_b_47 => b2(512 DOWNTO 481),
datain_a_48 => a3(32 DOWNTO 1),
datain_b_48 => b3(32 DOWNTO 1),
datain_a_49 => a3(64 DOWNTO 33),
datain_b_49 => b3(64 DOWNTO 33),
datain_a_50 => a3(96 DOWNTO 65),
datain_b_50 => b3(96 DOWNTO 65),
datain_a_51 => a3(128 DOWNTO 97),
datain_b_51 => b3(128 DOWNTO 97),
datain_a_52 => a3(160 DOWNTO 129),
datain_b_52 => b3(160 DOWNTO 129),
datain_a_53 => a3(192 DOWNTO 161),
datain_b_53 => b3(192 DOWNTO 161),
datain_a_54 => a3(224 DOWNTO 193),
datain_b_54 => b3(224 DOWNTO 193),
datain_a_55 => a3(256 DOWNTO 225),
datain_b_55 => b3(256 DOWNTO 225),
datain_a_56 => a3(288 DOWNTO 257),
datain_b_56 => b3(288 DOWNTO 257),
datain_a_57 => a3(320 DOWNTO 289),
datain_b_57 => b3(320 DOWNTO 289),
datain_a_58 => a3(352 DOWNTO 321),
datain_b_58 => b3(352 DOWNTO 321),
datain_a_59 => a3(384 DOWNTO 353),
datain_b_59 => b3(384 DOWNTO 353),
datain_a_60 => a3(416 DOWNTO 385),
datain_b_60 => b3(416 DOWNTO 385),
datain_a_61 => a3(448 DOWNTO 417),
datain_b_61 => b3(448 DOWNTO 417),
datain_a_62 => a3(480 DOWNTO 449),
datain_b_62 => b3(480 DOWNTO 449),
datain_a_63 => a3(512 DOWNTO 481),
datain_b_63 => b3(512 DOWNTO 481));
done <= '1' when (v_out = "1") else '0';
result <= res;
valid_out <= done;
END gen;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
l85BqJReQhKyfUH9N/fF/O0A4rQgMNzo408E3Zz/DGbFG3t6vS9EUpoh/U9ApmBJEFLB63ZhnmW0
/yBXizUrzg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Op0IdudFj2O93Fk4A3LE2t7u/usH5lWedR/0pqcVSEcZG2lOJXta+/S3F0Zk9clOqe5NbckPM4KW
HhX15evBpgtaew5g0A8QPa+2r2X3gMwwUy2aKtpN/OebaX9vwojwnVnQux+Su2m6vxYCIyo+4JTU
OD7TxGI0vysSBrirvnI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WRfoXSOnTmMBuYv3tza0fNZDe09qTACTvTuAo82B1IkRGVAhS9XHYZptMZ1l+C3+T2PJfwKL2jd1
5krNO6JYhkfI1QAXXmvsfNeXTacH8MVc3H3ZT1TeMJvIjVVrIGodwbACVsozPTkSz3R2Dy+eLOhD
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sEmPLJHe2EUR+Bkg05USGuLYr24jn174R4TCjA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Sj+1vUVfR3ha6SSfhBmSnVc2U1nb49DsrUION7aTpgNRQfQ9hVnvjG4Y+2Mu9qIHxSkmRxRDRYHu
IQ5GCg12ObT6RrYvQAvZ3eR2S77dZogPx1P4ITNNFqHE2crjGYuoIIF3VcLPwr3nYNbwApRBkrUs
Ls5IX6BwwhOzZJInFKQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
VBmVMVbAHHdEWF9/Qr5+XTSQjPqekPeZIlQrJmhq659RewMItTTCyjzWc5nXAg4VKe7oz0tJeh9/
c6V5YTdA3HTl6+g00zPXLKykykBO3M9rrjl32edAG3odAKXg8OVpHTl22iGKLxNqdbq7b6bJgYrW
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rd4g1fNqxp5Qw9Zy1lpavD6iAdlGmA3u1KZ/0ZVxetmIrGqvL0XLB2e2MbUd/GDRea0pGojBu+Xr
dhPCOxogiWBErOhwyTSw/JYsnfcCuFu54WC1Yg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576)
`protect data_block
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`protect end_protected
|
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