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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2159.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02159ent IS
END c07s02b04x00p21n01i02159ent;
ARCHITECTURE c07s02b04x00p21n01i02159arch OF c07s02b04x00p21n01i02159ent IS
TYPE severity_level_v is array (integer range <>) of severity_level;
SUBTYPE severity_level_5 is severity_level_v (1 to 5);
SUBTYPE severity_level_4 is severity_level_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : severity_level_5;
variable l_operand : severity_level := NOTE ;
variable r_operand : severity_level_4 := ( NOTE , FAILURE , NOTE , FAILURE );
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result=(NOTE,NOTE,FAILURE,NOTE,FAILURE)) and (result(1)=NOTE))
report "***PASSED TEST: c07s02b04x00p21n01i02159"
severity NOTE;
assert ((result=(NOTE,NOTE,FAILURE,NOTE,FAILURE)) and (result(1)=NOTE))
report "***FAILED TEST: c07s02b04x00p21n01i02159 - Concatenation of element and SEVERITY_LEVEL array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02159arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2159.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02159ent IS
END c07s02b04x00p21n01i02159ent;
ARCHITECTURE c07s02b04x00p21n01i02159arch OF c07s02b04x00p21n01i02159ent IS
TYPE severity_level_v is array (integer range <>) of severity_level;
SUBTYPE severity_level_5 is severity_level_v (1 to 5);
SUBTYPE severity_level_4 is severity_level_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : severity_level_5;
variable l_operand : severity_level := NOTE ;
variable r_operand : severity_level_4 := ( NOTE , FAILURE , NOTE , FAILURE );
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result=(NOTE,NOTE,FAILURE,NOTE,FAILURE)) and (result(1)=NOTE))
report "***PASSED TEST: c07s02b04x00p21n01i02159"
severity NOTE;
assert ((result=(NOTE,NOTE,FAILURE,NOTE,FAILURE)) and (result(1)=NOTE))
report "***FAILED TEST: c07s02b04x00p21n01i02159 - Concatenation of element and SEVERITY_LEVEL array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02159arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3119.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x01p05n01i03119ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b01x01p05n01i03119ent_a;
ARCHITECTURE c05s02b01x01p05n01i03119arch_a OF c05s02b01x01p05n01i03119ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b01x01p05n01i03119arch_a;
configuration c05s02b01x01p05n01i03119cfg_a of c05s02b01x01p05n01i03119ent_a is
for c05s02b01x01p05n01i03119arch_a
end for;
end c05s02b01x01p05n01i03119cfg_a;
--
ENTITY c05s02b01x01p05n01i03119ent IS
END c05s02b01x01p05n01i03119ent;
ARCHITECTURE c05s02b01x01p05n01i03119arch OF c05s02b01x01p05n01i03119ent IS
component virtual
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
signal s1,s2,s3,s4 : Bit;
BEGIN
u1 : virtual
generic map ( true )
port map (s1, s2);
u2 : virtual
generic map ( true )
port map (s2, s3);
u3 : virtual
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b01x01p05n01i03119"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b01x01p05n01i03119 - Use a configuration that is fully bound test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x01p05n01i03119arch;
configuration c05s02b01x01p05n01i03119cfg of c05s02b01x01p05n01i03119ent is
for c05s02b01x01p05n01i03119arch
for all : virtual use configuration work.c05s02b01x01p05n01i03119cfg_a;
end for;
end for;
end c05s02b01x01p05n01i03119cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3119.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x01p05n01i03119ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b01x01p05n01i03119ent_a;
ARCHITECTURE c05s02b01x01p05n01i03119arch_a OF c05s02b01x01p05n01i03119ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b01x01p05n01i03119arch_a;
configuration c05s02b01x01p05n01i03119cfg_a of c05s02b01x01p05n01i03119ent_a is
for c05s02b01x01p05n01i03119arch_a
end for;
end c05s02b01x01p05n01i03119cfg_a;
--
ENTITY c05s02b01x01p05n01i03119ent IS
END c05s02b01x01p05n01i03119ent;
ARCHITECTURE c05s02b01x01p05n01i03119arch OF c05s02b01x01p05n01i03119ent IS
component virtual
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
signal s1,s2,s3,s4 : Bit;
BEGIN
u1 : virtual
generic map ( true )
port map (s1, s2);
u2 : virtual
generic map ( true )
port map (s2, s3);
u3 : virtual
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b01x01p05n01i03119"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b01x01p05n01i03119 - Use a configuration that is fully bound test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x01p05n01i03119arch;
configuration c05s02b01x01p05n01i03119cfg of c05s02b01x01p05n01i03119ent is
for c05s02b01x01p05n01i03119arch
for all : virtual use configuration work.c05s02b01x01p05n01i03119cfg_a;
end for;
end for;
end c05s02b01x01p05n01i03119cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3119.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x01p05n01i03119ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b01x01p05n01i03119ent_a;
ARCHITECTURE c05s02b01x01p05n01i03119arch_a OF c05s02b01x01p05n01i03119ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b01x01p05n01i03119arch_a;
configuration c05s02b01x01p05n01i03119cfg_a of c05s02b01x01p05n01i03119ent_a is
for c05s02b01x01p05n01i03119arch_a
end for;
end c05s02b01x01p05n01i03119cfg_a;
--
ENTITY c05s02b01x01p05n01i03119ent IS
END c05s02b01x01p05n01i03119ent;
ARCHITECTURE c05s02b01x01p05n01i03119arch OF c05s02b01x01p05n01i03119ent IS
component virtual
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
signal s1,s2,s3,s4 : Bit;
BEGIN
u1 : virtual
generic map ( true )
port map (s1, s2);
u2 : virtual
generic map ( true )
port map (s2, s3);
u3 : virtual
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b01x01p05n01i03119"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b01x01p05n01i03119 - Use a configuration that is fully bound test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x01p05n01i03119arch;
configuration c05s02b01x01p05n01i03119cfg of c05s02b01x01p05n01i03119ent is
for c05s02b01x01p05n01i03119arch
for all : virtual use configuration work.c05s02b01x01p05n01i03119cfg_a;
end for;
end for;
end c05s02b01x01p05n01i03119cfg;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Jun 05 10:58:35 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/system_vga_hessian_0_0_stub.vhdl
-- Design : system_vga_hessian_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_hessian_0_0 is
Port (
clk_x16 : in STD_LOGIC;
active : in STD_LOGIC;
rst : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end system_vga_hessian_0_0;
architecture stub of system_vga_hessian_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_x16,active,rst,x_addr[9:0],y_addr[9:0],g_in[7:0],hessian_out[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_hessian,Vivado 2016.4";
begin
end;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:03:77 07/10/2015
-- Design Name:
-- Module Name: C:/Xilinx91i/dff4_test.VHD
-- Project Name: dff4
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dff4
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test IS
END test;
ARCHITECTURE behavior OF test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dff4
PORT(
A : IN std_logic;
clk : IN std_logic;
B : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal B : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dff4 PORT MAP (
A => A,
clk => clk,
B => B
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
A<='1';
--wait for 100 ns;
--wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for __COMMON__ of __COMMON__
--
-- Generated
-- by: lutscher
-- on: Tue Jun 23 10:43:20 2009
-- cmd: /home/lutscher/work/MIX/mix_1.pl a_clk.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author$
-- $Id$
-- $Date$
-- $Log$
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.109 2008/04/01 12:48:34 wig Exp
--
-- Generator: mix_1.pl Revision: 1.3 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of A_CLK
--
architecture rtl of A_CLK is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component PADS
-- No Generated Generics
port (
-- Generated Port for Entity PADS
p_mix_pad_conn_1_2_go : out std_ulogic;
p_mix_pad_conn_2_3_go : out std_ulogic;
p_mix_pad_conn_3_4_go : out std_ulogic;
p_mix_pad_conn_4_5_go : out std_ulogic;
p_mix_pad_conn_5_6_go : out std_ulogic;
p_mix_pad_conn_6_7_go : out std_ulogic;
p_mix_pad_conn_7_8_go : out std_ulogic;
p_mix_pad_conn_8_9_go : out std_ulogic;
p_mix_pad_conn_9_10_go : out std_ulogic
-- End of Generated Port for Entity PADS
);
end component;
-- ---------
component a_fsm
-- No Generated Generics
port (
-- Generated Port for Entity a_fsm
alarm_button : in std_ulogic;
alarm_in_u : in std_ulogic;
clk : in std_ulogic;
key : in std_ulogic_vector(3 downto 0);
load_new_a : out std_ulogic;
load_new_c : out std_ulogic;
one_second : in std_ulogic;
reset : in std_ulogic;
shift : out std_ulogic;
show_a : out std_ulogic;
show_new_time : out std_ulogic;
time_button : in std_ulogic;
wire_high_bit : in std_ulogic; -- Wire bit to high
wire_high_bus : in std_ulogic_vector(3 downto 0); -- Ground wire_low port
wire_low_bus : in std_ulogic_vector(3 downto 0) -- Ground wire_low port
-- End of Generated Port for Entity a_fsm
);
end component;
-- ---------
component alreg
-- No Generated Generics
port (
-- Generated Port for Entity alreg
alarm_time : out std_ulogic_vector(3 downto 0);
load_new_a : in std_ulogic;
new_alarm_time : in std_ulogic_vector(3 downto 0);
reset : in std_ulogic -- The Reset
-- End of Generated Port for Entity alreg
);
end component;
-- ---------
component count4
-- No Generated Generics
port (
-- Generated Port for Entity count4
clk : in std_ulogic;
current_time_ls_hr : out std_ulogic_vector(3 downto 0);
current_time_ls_min : out std_ulogic_vector(3 downto 0);
current_time_ms_hr : out std_ulogic_vector(3 downto 0);
current_time_ms_min : out std_ulogic_vector(3 downto 0);
load_new_c : in std_ulogic;
new_current_time_ls_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ls_min : in std_ulogic_vector(3 downto 0);
new_current_time_ms_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ms_min : in std_ulogic_vector(3 downto 0);
one_minute : in std_ulogic;
reset : in std_ulogic -- The Reset
-- End of Generated Port for Entity count4
);
end component;
-- ---------
component ddrv4
-- No Generated Generics
port (
-- Generated Port for Entity ddrv4
alarm_time_ls_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ls_min : in std_ulogic_vector(3 downto 0);
alarm_time_ms_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ms_min : in std_ulogic_vector(3 downto 0);
clk : in std_ulogic;
current_time_ls_hr : in std_ulogic_vector(3 downto 0);
current_time_ls_min : in std_ulogic_vector(3 downto 0);
current_time_ms_hr : in std_ulogic_vector(3 downto 0);
current_time_ms_min : in std_ulogic_vector(3 downto 0);
display_ls_hr : out std_ulogic_vector(6 downto 0);
display_ls_min : out std_ulogic_vector(6 downto 0);
display_ms_hr : out std_ulogic_vector(6 downto 0);
display_ms_min : out std_ulogic_vector(6 downto 0);
key_buffer_0 : in std_ulogic_vector(3 downto 0);
key_buffer_1 : in std_ulogic_vector(3 downto 0);
key_buffer_2 : in std_ulogic_vector(3 downto 0);
key_buffer_3 : in std_ulogic_vector(3 downto 0);
p_mix_sound_alarm_test1_go : out std_ulogic;
reset : in std_ulogic; -- The Reset
show_a : in std_ulogic;
show_new_time : in std_ulogic;
sound_alarm : out std_ulogic
-- End of Generated Port for Entity ddrv4
);
end component;
-- ---------
component keypad
-- No Generated Generics
port (
-- Generated Port for Entity keypad
clk : in std_ulogic;
columns : in std_ulogic_vector(2 downto 0);
reset : in std_ulogic; -- The Reset
rows : out std_ulogic_vector(3 downto 0) -- Keypad Output
-- End of Generated Port for Entity keypad
);
end component;
-- ---------
component keyscan
-- No Generated Generics
port (
-- Generated Port for Entity keyscan
alarm_button : out std_ulogic;
clk : in std_ulogic;
columns : out std_ulogic_vector(2 downto 0);
key : out std_ulogic_vector(3 downto 0);
key_buffer_0 : out std_ulogic_vector(3 downto 0);
key_buffer_1 : out std_ulogic_vector(3 downto 0);
key_buffer_2 : out std_ulogic_vector(3 downto 0);
key_buffer_3 : out std_ulogic_vector(3 downto 0);
reset : in std_ulogic; -- The Reset
rows : in std_ulogic_vector(3 downto 0); -- Keypad Output
shift : in std_ulogic;
time_button : out std_ulogic
-- End of Generated Port for Entity keyscan
);
end component;
-- ---------
component timegen
-- No Generated Generics
port (
-- Generated Port for Entity timegen
clk : in std_ulogic;
one_minute : out std_ulogic;
one_second : out std_ulogic;
reset : in std_ulogic; -- The Reset
stopwatch : in std_ulogic -- Driven by reset
-- End of Generated Port for Entity timegen
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic1_0 : std_ulogic;
signal mix_logic1_bus_1 : std_ulogic_vector(3 downto 0);
signal mix_logic0_bus_1 : std_ulogic_vector(3 downto 0);
signal alarm_button : std_ulogic;
signal s_int_alarm_time_ls_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ls_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ms_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ms_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal columns : std_ulogic_vector(2 downto 0);
signal s_int_current_time_ls_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ls_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ms_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ms_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal key : std_ulogic_vector(3 downto 0);
signal s_int_key_buffer_0 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_1 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_2 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_3 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal load_new_a : std_ulogic;
signal load_new_c : std_ulogic;
signal one_minute : std_ulogic;
signal one_sec_pulse : std_ulogic;
signal rows : std_ulogic_vector(3 downto 0);
signal shift : std_ulogic;
signal s_int_show_a : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_show_new_time : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sound_alarm_test1 : std_ulogic;
signal time_button : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic1_0 <= '1';
mix_logic1_bus_1 <= ( others => '1' );
mix_logic0_bus_1 <= ( others => '0' );
s_int_alarm_time_ls_hr <= alarm_time_ls_hr; -- __I_I_BUS_PORT
s_int_alarm_time_ls_min <= alarm_time_ls_min; -- __I_I_BUS_PORT
s_int_alarm_time_ms_hr <= alarm_time_ms_hr; -- __I_I_BUS_PORT
s_int_alarm_time_ms_min <= alarm_time_ms_min; -- __I_I_BUS_PORT
s_int_current_time_ls_hr <= current_time_ls_hr; -- __I_I_BUS_PORT
s_int_current_time_ls_min <= current_time_ls_min; -- __I_I_BUS_PORT
s_int_current_time_ms_hr <= current_time_ms_hr; -- __I_I_BUS_PORT
s_int_current_time_ms_min <= current_time_ms_min; -- __I_I_BUS_PORT
s_int_key_buffer_0 <= key_buffer_0; -- __I_I_BUS_PORT
s_int_key_buffer_1 <= key_buffer_1; -- __I_I_BUS_PORT
s_int_key_buffer_2 <= key_buffer_2; -- __I_I_BUS_PORT
s_int_key_buffer_3 <= key_buffer_3; -- __I_I_BUS_PORT
s_int_show_a <= show_a; -- __I_I_BIT_PORT
s_int_show_new_time <= show_new_time; -- __I_I_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for PADS
PADS: PADS
port map (
p_mix_pad_conn_1_2_go => pad_conn_1_2,
p_mix_pad_conn_2_3_go => pad_conn_2_3,
p_mix_pad_conn_3_4_go => pad_conn_3_4,
p_mix_pad_conn_4_5_go => pad_conn_4_5,
p_mix_pad_conn_5_6_go => pad_conn_5_6,
p_mix_pad_conn_6_7_go => pad_conn_6_7,
p_mix_pad_conn_7_8_go => pad_conn_7_8,
p_mix_pad_conn_8_9_go => pad_conn_8_9,
p_mix_pad_conn_9_10_go => pad_conn_9_10
);
-- End of Generated Instance Port Map for PADS
-- Generated Instance Port Map for control
control: a_fsm
port map (
alarm_button => alarm_button,
alarm_in_u => sound_alarm_test1, -- Use internally test1
clk => clk, -- The ClockThe d_Clk (X4)
key => key,
load_new_a => load_new_a,
load_new_c => load_new_c,
one_second => one_sec_pulse,
reset => reset, -- The Reset (X10)
shift => shift,
show_a => s_int_show_a,
show_new_time => s_int_show_new_time,
time_button => time_button,
wire_high_bit => mix_logic1_0, -- Wire bit to high
wire_high_bus => mix_logic1_bus_1, -- Ground wire_low port
wire_low_bus => mix_logic0_bus_1 -- Ground wire_low port
);
-- End of Generated Instance Port Map for control
-- Generated Instance Port Map for u0_alreg
u0_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ls_min, -- Display storage buffer 0 ls_min
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
reset => reset -- The Reset (X10)
);
-- End of Generated Instance Port Map for u0_alreg
-- Generated Instance Port Map for u1_alreg
u1_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ms_min, -- Display storage buffer 1 ms_min
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
reset => reset -- The Reset (X10)
);
-- End of Generated Instance Port Map for u1_alreg
-- Generated Instance Port Map for u2_alreg
u2_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
reset => reset -- The Reset (X10)
);
-- End of Generated Instance Port Map for u2_alreg
-- Generated Instance Port Map for u3_alreg
u3_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
reset => reset -- The Reset (X10)
);
-- End of Generated Instance Port Map for u3_alreg
-- Generated Instance Port Map for u_counter
u_counter: count4
port map (
clk => clk, -- The ClockThe d_Clk (X4)
current_time_ls_hr => s_int_current_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time_ls_min => s_int_current_time_ls_min, -- Display storage buffer 0 ls_min
current_time_ms_hr => s_int_current_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time_ms_min => s_int_current_time_ms_min, -- Display storage buffer 1 ms_min
load_new_c => load_new_c,
new_current_time_ls_hr => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
new_current_time_ls_min => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
new_current_time_ms_hr => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
new_current_time_ms_min => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
one_minute => one_minute,
reset => reset -- The Reset (X10)
);
-- End of Generated Instance Port Map for u_counter
-- Generated Instance Port Map for u_ddrv4
u_ddrv4: ddrv4
port map (
alarm_time_ls_hr => s_int_alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
alarm_time_ls_min => s_int_alarm_time_ls_min, -- Display storage buffer 0 ls_min
alarm_time_ms_hr => s_int_alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
alarm_time_ms_min => s_int_alarm_time_ms_min, -- Display storage buffer 1 ms_min
clk => clk, -- The ClockThe d_Clk (X4)
current_time_ls_hr => s_int_current_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time_ls_min => s_int_current_time_ls_min, -- Display storage buffer 0 ls_min
current_time_ms_hr => s_int_current_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time_ms_min => s_int_current_time_ms_min, -- Display storage buffer 1 ms_min
display_ls_hr => display_ls_hr, -- Display storage buffer 2 ls_hr
display_ls_min => display_ls_min, -- Display storage buffer 0 ls_min
display_ms_hr => display_ms_hr, -- Display storage buffer 3 ms_hr
display_ms_min => display_ms_min, -- Display storage buffer 1 ms_min
key_buffer_0 => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
key_buffer_1 => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
key_buffer_2 => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
key_buffer_3 => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
p_mix_sound_alarm_test1_go => sound_alarm_test1, -- Use internally test1
reset => reset, -- The Reset (X10)
show_a => s_int_show_a,
show_new_time => s_int_show_new_time,
sound_alarm => sound_alarm
);
-- End of Generated Instance Port Map for u_ddrv4
-- Generated Instance Port Map for u_keypad
u_keypad: keypad
port map (
clk => clk, -- The ClockThe d_Clk (X4)
columns => columns,
reset => reset, -- The Reset (X10)
rows => rows -- Keypad Output
);
-- End of Generated Instance Port Map for u_keypad
-- Generated Instance Port Map for u_keyscan
u_keyscan: keyscan
port map (
alarm_button => alarm_button,
clk => clk, -- The ClockThe d_Clk (X4)
columns => columns,
key => key,
key_buffer_0 => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
key_buffer_1 => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
key_buffer_2 => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
key_buffer_3 => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
reset => reset, -- The Reset (X10)
rows => rows, -- Keypad Output
shift => shift,
time_button => time_button
);
-- End of Generated Instance Port Map for u_keyscan
-- Generated Instance Port Map for u_timegen
u_timegen: timegen
port map (
clk => clk, -- The ClockThe d_Clk (X4)
one_minute => one_minute,
one_second => one_sec_pulse,
reset => reset, -- The Reset (X10)
stopwatch => stopwatch -- Driven by reset
);
-- End of Generated Instance Port Map for u_timegen
end rtl;
--
-- Start of Generated Architecture rtl of PADS
--
architecture rtl of PADS is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component padcell
-- No Generated Generics
port (
-- Generated Port for Entity padcell
EI : in std_ulogic;
EO : out std_ulogic
-- End of Generated Port for Entity padcell
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic0_0 : std_ulogic;
signal pad_conn_1_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_conn_2_3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_conn_3_4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_conn_4_5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_conn_5_6 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_conn_6_7 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_conn_7_8 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_conn_8_9 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_conn_9_10 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic0_0 <= '0';
p_mix_pad_conn_1_2_go <= pad_conn_1_2; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
p_mix_pad_conn_2_3_go <= pad_conn_2_3; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
p_mix_pad_conn_3_4_go <= pad_conn_3_4; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
p_mix_pad_conn_4_5_go <= pad_conn_4_5; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
p_mix_pad_conn_5_6_go <= pad_conn_5_6; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
p_mix_pad_conn_6_7_go <= pad_conn_6_7; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
p_mix_pad_conn_7_8_go <= pad_conn_7_8; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
p_mix_pad_conn_8_9_go <= pad_conn_8_9; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
p_mix_pad_conn_9_10_go <= pad_conn_9_10; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for Pad_1
Pad_1: padcell
port map (
EI => mix_logic0_0, -- Ground EI of Pad1
EO => pad_conn_1_2
);
-- End of Generated Instance Port Map for Pad_1
-- Generated Instance Port Map for Pad_10
Pad_10: padcell
port map (
EI => pad_conn_9_10
);
-- End of Generated Instance Port Map for Pad_10
-- Generated Instance Port Map for Pad_2
Pad_2: padcell
port map (
EI => pad_conn_1_2,
EO => pad_conn_2_3
);
-- End of Generated Instance Port Map for Pad_2
-- Generated Instance Port Map for Pad_3
Pad_3: padcell
port map (
EI => pad_conn_2_3,
EO => pad_conn_3_4
);
-- End of Generated Instance Port Map for Pad_3
-- Generated Instance Port Map for Pad_4
Pad_4: padcell
port map (
EI => pad_conn_3_4,
EO => pad_conn_4_5
);
-- End of Generated Instance Port Map for Pad_4
-- Generated Instance Port Map for Pad_5
Pad_5: padcell
port map (
EI => pad_conn_4_5,
EO => pad_conn_5_6
);
-- End of Generated Instance Port Map for Pad_5
-- Generated Instance Port Map for Pad_6
Pad_6: padcell
port map (
EI => pad_conn_5_6,
EO => pad_conn_6_7
);
-- End of Generated Instance Port Map for Pad_6
-- Generated Instance Port Map for Pad_7
Pad_7: padcell
port map (
EI => pad_conn_6_7,
EO => pad_conn_7_8
);
-- End of Generated Instance Port Map for Pad_7
-- Generated Instance Port Map for Pad_8
Pad_8: padcell
port map (
EI => pad_conn_7_8,
EO => pad_conn_8_9
);
-- End of Generated Instance Port Map for Pad_8
-- Generated Instance Port Map for Pad_9
Pad_9: padcell
port map (
EI => pad_conn_8_9,
EO => pad_conn_9_10
);
-- End of Generated Instance Port Map for Pad_9
end rtl;
--
-- Start of Generated Architecture rtl of ddrv4
--
architecture rtl of ddrv4 is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ddrv
-- No Generated Generics
port (
-- Generated Port for Entity ddrv
alarm_in : in std_ulogic; -- Use internally test1
alarm_time : in std_ulogic_vector(3 downto 0); -- Display storage buffer 1 ms_min
clk : in std_ulogic; -- The d_Clk
current_time : in std_ulogic_vector(3 downto 0); -- Display storage buffer 1 ms_min
display : out std_ulogic_vector(6 downto 0); -- Display storage buffer 1 ms_min
key_buffer : in std_ulogic_vector(3 downto 0); -- Display storage buffer 1 ms_min
show_a : in std_ulogic;
show_new_time : in std_ulogic;
sound_alarm : out std_ulogic -- Display storage buffer 1 ms_min __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ddrv
);
end component;
-- ---------
component and_f
-- No Generated Generics
port (
-- Generated Port for Entity and_f
clk : in std_ulogic;
mix_key_out : out std_ulogic;
out_2 : out std_ulogic; -- Use internally test1
reset : in std_ulogic; -- The Reset
y : in std_ulogic_vector(3 downto 0) -- Display storage buffer 3 ms_hr
-- End of Generated Port for Entity and_f
);
end component;
-- ---------
--
-- Generated Signal List
--
signal alarm : std_ulogic_vector(3 downto 0);
signal sound_alarm_test1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_sound_alarm_test1_go <= sound_alarm_test1; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for d_ls_hr
d_ls_hr: ddrv
port map (
alarm_time => alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
clk => clk, -- The ClockThe d_Clk (X4)
current_time => current_time_ls_hr, -- Display storage buffer 2 ls_hr
display => display_ls_hr, -- Display storage buffer 2 ls_hr
key_buffer => key_buffer_2, -- Display storage buffer 2 ls_hr
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(2) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
);
-- End of Generated Instance Port Map for d_ls_hr
-- Generated Instance Port Map for d_ls_min
d_ls_min: ddrv
port map (
alarm_time => alarm_time_ls_min, -- Display storage buffer 0 ls_min
clk => clk, -- The ClockThe d_Clk (X4)
current_time => current_time_ls_min, -- Display storage buffer 0 ls_min
display => display_ls_min, -- Display storage buffer 0 ls_min
key_buffer => key_buffer_0, -- Display storage buffer 0 ls_min
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(0) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
);
-- End of Generated Instance Port Map for d_ls_min
-- Generated Instance Port Map for d_ms_hr
d_ms_hr: ddrv
port map (
alarm_in => sound_alarm_test1, -- Use internally test1
alarm_time => alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
clk => clk, -- The ClockThe d_Clk (X4)
current_time => current_time_ms_hr, -- Display storage buffer 3 ms_hr
display => display_ms_hr, -- Display storage buffer 3 ms_hr
key_buffer => key_buffer_3, -- Display storage buffer 3 ms_hr
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(3) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
);
-- End of Generated Instance Port Map for d_ms_hr
-- Generated Instance Port Map for d_ms_min
d_ms_min: ddrv
port map (
alarm_time => alarm_time_ms_min, -- Display storage buffer 1 ms_min
clk => clk, -- The ClockThe d_Clk (X4)
current_time => current_time_ms_min, -- Display storage buffer 1 ms_min
display => display_ms_min, -- Display storage buffer 1 ms_min
key_buffer => key_buffer_1, -- Display storage buffer 1 ms_min
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(1) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
);
-- End of Generated Instance Port Map for d_ms_min
-- Generated Instance Port Map for u_and_f
u_and_f: and_f
port map (
clk => clk, -- The ClockThe d_Clk (X4)
mix_key_out => sound_alarm,
out_2 => sound_alarm_test1, -- Use internally test1
reset => reset, -- The Reset (X10)
y(0) => alarm(0), -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
y(1) => alarm(0), -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
y(2) => alarm(0), -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
y(3) => alarm(0) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
);
-- End of Generated Instance Port Map for u_and_f
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.std_logic_1164.all;
package types is
subtype reg_t is std_logic_vector( 7 downto 0);
subtype reg16_t is std_logic_vector(15 downto 0);
type op_t is ( op_adc, op_add, op_and,
op_bit, op_call, op_ccf,
op_cp, op_cpl, op_daa,
op_dec, op_di, op_ei,
op_halt, op_inc, op_jp,
op_jr, op_ld, op_lhd,
op_nop, op_or, op_pop,
op_prefix, op_push, op_res,
op_ret, op_reti, op_rla,
op_rl, op_rlca, op_rlc,
op_rra, op_rr, op_rrca,
op_rrc, op_rst, op_sbc,
op_scf, op_set, op_sla,
op_sra, op_srl, op_stop,
op_sub, op_swap, op_xor);
type alu_op_t is ( alu_op_adc, alu_op_add, alu_op_and,
alu_op_bit, alu_op_cp, alu_op_cpl,
alu_op_daa, alu_op_or, alu_op_rl,
alu_op_rr, alu_op_rrc, alu_op_sla,
alu_op_sra, alu_op_srl, alu_op_sub,
alu_op_swap, alu_op_xor);
constant CARRY_BIT : integer := 4;
constant HALF_CARRY_BIT : integer := 5;
constant SUBTRACT_BIT : integer := 6;
constant ZERO_BIT : integer := 7;
end;
|
package pack is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
end package;
package body pack is
type SharedCounter is protected body
constant INIT : integer := 5;
variable counter: Integer := INIT;
variable dummy: Integer;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
end package body;
-------------------------------------------------------------------------------
entity protected2 is
end entity;
use work.pack.all;
architecture test of protected2 is
shared variable x : SharedCounter;
begin
process is
begin
assert x.value = 5;
x.increment;
report "value is now " & integer'image(x.value);
x.increment(2);
assert x.value = 8;
wait;
end process;
process is
begin
wait for 1 ns;
assert x.value = 8;
x.decrement;
assert x.value = 7;
wait;
end process;
end architecture;
|
package pack is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
end package;
package body pack is
type SharedCounter is protected body
constant INIT : integer := 5;
variable counter: Integer := INIT;
variable dummy: Integer;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
end package body;
-------------------------------------------------------------------------------
entity protected2 is
end entity;
use work.pack.all;
architecture test of protected2 is
shared variable x : SharedCounter;
begin
process is
begin
assert x.value = 5;
x.increment;
report "value is now " & integer'image(x.value);
x.increment(2);
assert x.value = 8;
wait;
end process;
process is
begin
wait for 1 ns;
assert x.value = 8;
x.decrement;
assert x.value = 7;
wait;
end process;
end architecture;
|
package pack is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
end package;
package body pack is
type SharedCounter is protected body
constant INIT : integer := 5;
variable counter: Integer := INIT;
variable dummy: Integer;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
end package body;
-------------------------------------------------------------------------------
entity protected2 is
end entity;
use work.pack.all;
architecture test of protected2 is
shared variable x : SharedCounter;
begin
process is
begin
assert x.value = 5;
x.increment;
report "value is now " & integer'image(x.value);
x.increment(2);
assert x.value = 8;
wait;
end process;
process is
begin
wait for 1 ns;
assert x.value = 8;
x.decrement;
assert x.value = 7;
wait;
end process;
end architecture;
|
package pack is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
end package;
package body pack is
type SharedCounter is protected body
constant INIT : integer := 5;
variable counter: Integer := INIT;
variable dummy: Integer;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
end package body;
-------------------------------------------------------------------------------
entity protected2 is
end entity;
use work.pack.all;
architecture test of protected2 is
shared variable x : SharedCounter;
begin
process is
begin
assert x.value = 5;
x.increment;
report "value is now " & integer'image(x.value);
x.increment(2);
assert x.value = 8;
wait;
end process;
process is
begin
wait for 1 ns;
assert x.value = 8;
x.decrement;
assert x.value = 7;
wait;
end process;
end architecture;
|
package pack is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
end package;
package body pack is
type SharedCounter is protected body
constant INIT : integer := 5;
variable counter: Integer := INIT;
variable dummy: Integer;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
end package body;
-------------------------------------------------------------------------------
entity protected2 is
end entity;
use work.pack.all;
architecture test of protected2 is
shared variable x : SharedCounter;
begin
process is
begin
assert x.value = 5;
x.increment;
report "value is now " & integer'image(x.value);
x.increment(2);
assert x.value = 8;
wait;
end process;
process is
begin
wait for 1 ns;
assert x.value = 8;
x.decrement;
assert x.value = 7;
wait;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:52:28 01/20/2015
-- Design Name:
-- Module Name: C:/Users/sed/Downloads/Frecuencimetroo 9.0B/frecuencimentro/esc_tb.vhd
-- Project Name: Frecuencimentro
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: top1
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY esc_tb IS
END esc_tb;
ARCHITECTURE behavior OF esc_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top1
PORT(
entrada : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
led : OUT std_logic_vector(6 downto 0);
led_unidades : OUT std_logic_vector(1 downto 0);
selector : OUT std_logic_vector(3 downto 0);
prueba : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal entrada : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal led : std_logic_vector(6 downto 0);
signal led_unidades : std_logic_vector(1 downto 0);
signal selector : std_logic_vector(3 downto 0);
signal prueba : std_logic_vector(15 downto 0);
-- Clock period definitions
--constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top1 PORT MAP (
entrada => entrada,
clk => clk,
reset => reset,
led => led,
led_unidades => led_unidades,
selector => selector,
prueba => prueba
);
-- Clock process definitions
-- clk_process :process
-- begin
-- clk <= '0';
-- wait for clk_period/2;
-- clk <= '1';
-- wait for clk_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:52:28 01/20/2015
-- Design Name:
-- Module Name: C:/Users/sed/Downloads/Frecuencimetroo 9.0B/frecuencimentro/esc_tb.vhd
-- Project Name: Frecuencimentro
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: top1
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY esc_tb IS
END esc_tb;
ARCHITECTURE behavior OF esc_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top1
PORT(
entrada : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
led : OUT std_logic_vector(6 downto 0);
led_unidades : OUT std_logic_vector(1 downto 0);
selector : OUT std_logic_vector(3 downto 0);
prueba : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal entrada : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal led : std_logic_vector(6 downto 0);
signal led_unidades : std_logic_vector(1 downto 0);
signal selector : std_logic_vector(3 downto 0);
signal prueba : std_logic_vector(15 downto 0);
-- Clock period definitions
--constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top1 PORT MAP (
entrada => entrada,
clk => clk,
reset => reset,
led => led,
led_unidades => led_unidades,
selector => selector,
prueba => prueba
);
-- Clock process definitions
-- clk_process :process
-- begin
-- clk <= '0';
-- wait for clk_period/2;
-- clk <= '1';
-- wait for clk_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_447 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_447;
architecture augh of mul_447 is
signal tmp_res : signed(46 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_447 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_447;
architecture augh of mul_447 is
signal tmp_res : signed(46 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DataMemory is
Port ( enableMem : in STD_LOGIC;
reset : in STD_LOGIC;
cRD : in STD_LOGIC_VECTOR (31 downto 0);
address : in STD_LOGIC_VECTOR (31 downto 0);
wrEnMem : in STD_LOGIC;
datoToWr : out STD_LOGIC_VECTOR (31 downto 0)
);
end DataMemory;
architecture arqDataMemory of DataMemory is
type ram_type is array (0 to 63) of std_logic_vector (31 downto 0);
signal ramMemory : ram_type:=(others => x"00000000");
begin
process(enableMem,reset,cRD,address,wrEnMem)
begin
if(enableMem = '1') then
if(reset = '1')then
datoToWr <= (others => '0');
ramMemory <= (others => x"00000000");
else
if(wrEnMem = '0')then
datoToWr <= ramMemory(conv_integer(address(5 downto 0)));
else
ramMemory(conv_integer(address(5 downto 0))) <= cRD;
end if;
end if;
end if;
end process;
end arqDataMemory;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_STICKYFLAG9 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
SET : in vl_logic_vector(8 downto 0);
CLR : in vl_logic_vector(8 downto 0);
FLAG : out vl_logic_vector(8 downto 0)
);
end F2DSS_ACE_MISC_STICKYFLAG9;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_STICKYFLAG9 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
SET : in vl_logic_vector(8 downto 0);
CLR : in vl_logic_vector(8 downto 0);
FLAG : out vl_logic_vector(8 downto 0)
);
end F2DSS_ACE_MISC_STICKYFLAG9;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_STICKYFLAG9 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
SET : in vl_logic_vector(8 downto 0);
CLR : in vl_logic_vector(8 downto 0);
FLAG : out vl_logic_vector(8 downto 0)
);
end F2DSS_ACE_MISC_STICKYFLAG9;
|
architecture RTL of FIFO is
begin
process
begin
end process;
process (a, b)
begin
end process;
process (a, b) is
begin
end process;
-- Violations below
process
begin
end process;
process (a, b)
begin
end process;
process (a, b) is
begin
end process;
end architecture RTL;
|
-------------------------------------------------------------------------------
-- system_mdm_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library mdm_v2_10_a;
use mdm_v2_10_a.all;
entity system_mdm_0_wrapper is
port (
Interrupt : out std_logic;
Debug_SYS_Rst : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 2);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 5);
Sl_MWrErr : out std_logic_vector(0 to 5);
Sl_MRdErr : out std_logic_vector(0 to 5);
Sl_MIRQ : out std_logic_vector(0 to 5);
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
bscan_tdi : out std_logic;
bscan_reset : out std_logic;
bscan_shift : out std_logic;
bscan_update : out std_logic;
bscan_capture : out std_logic;
bscan_sel1 : out std_logic;
bscan_drck1 : out std_logic;
bscan_tdo1 : in std_logic;
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_mdm_0_wrapper : entity is "mdm_v2_10_a";
end system_mdm_0_wrapper;
architecture STRUCTURE of system_mdm_0_wrapper is
component mdm is
generic (
C_FAMILY : STRING;
C_JTAG_CHAIN : INTEGER;
C_INTERCONNECT : INTEGER;
C_BASEADDR : STD_LOGIC_VECTOR;
C_HIGHADDR : STD_LOGIC_VECTOR;
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_MB_DBG_PORTS : INTEGER;
C_USE_UART : INTEGER;
C_USE_BSCAN : integer;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER
);
port (
Interrupt : out std_logic;
Debug_SYS_Rst : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
bscan_tdi : out std_logic;
bscan_reset : out std_logic;
bscan_shift : out std_logic;
bscan_update : out std_logic;
bscan_capture : out std_logic;
bscan_sel1 : out std_logic;
bscan_drck1 : out std_logic;
bscan_tdo1 : in std_logic;
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end component;
begin
mdm_0 : mdm
generic map (
C_FAMILY => "virtex5",
C_JTAG_CHAIN => 2,
C_INTERCONNECT => 1,
C_BASEADDR => X"84400000",
C_HIGHADDR => X"8440ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 64,
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 3,
C_SPLB_NUM_MASTERS => 6,
C_SPLB_NATIVE_DWIDTH => 32,
C_SPLB_SUPPORT_BURSTS => 1,
C_MB_DBG_PORTS => 1,
C_USE_UART => 1,
C_USE_BSCAN => 0,
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_DATA_WIDTH => 32
)
port map (
Interrupt => Interrupt,
Debug_SYS_Rst => Debug_SYS_Rst,
Ext_BRK => Ext_BRK,
Ext_NM_BRK => Ext_NM_BRK,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Dbg_Clk_0 => Dbg_Clk_0,
Dbg_TDI_0 => Dbg_TDI_0,
Dbg_TDO_0 => Dbg_TDO_0,
Dbg_Reg_En_0 => Dbg_Reg_En_0,
Dbg_Capture_0 => Dbg_Capture_0,
Dbg_Shift_0 => Dbg_Shift_0,
Dbg_Update_0 => Dbg_Update_0,
Dbg_Rst_0 => Dbg_Rst_0,
Dbg_Clk_1 => Dbg_Clk_1,
Dbg_TDI_1 => Dbg_TDI_1,
Dbg_TDO_1 => Dbg_TDO_1,
Dbg_Reg_En_1 => Dbg_Reg_En_1,
Dbg_Capture_1 => Dbg_Capture_1,
Dbg_Shift_1 => Dbg_Shift_1,
Dbg_Update_1 => Dbg_Update_1,
Dbg_Rst_1 => Dbg_Rst_1,
Dbg_Clk_2 => Dbg_Clk_2,
Dbg_TDI_2 => Dbg_TDI_2,
Dbg_TDO_2 => Dbg_TDO_2,
Dbg_Reg_En_2 => Dbg_Reg_En_2,
Dbg_Capture_2 => Dbg_Capture_2,
Dbg_Shift_2 => Dbg_Shift_2,
Dbg_Update_2 => Dbg_Update_2,
Dbg_Rst_2 => Dbg_Rst_2,
Dbg_Clk_3 => Dbg_Clk_3,
Dbg_TDI_3 => Dbg_TDI_3,
Dbg_TDO_3 => Dbg_TDO_3,
Dbg_Reg_En_3 => Dbg_Reg_En_3,
Dbg_Capture_3 => Dbg_Capture_3,
Dbg_Shift_3 => Dbg_Shift_3,
Dbg_Update_3 => Dbg_Update_3,
Dbg_Rst_3 => Dbg_Rst_3,
Dbg_Clk_4 => Dbg_Clk_4,
Dbg_TDI_4 => Dbg_TDI_4,
Dbg_TDO_4 => Dbg_TDO_4,
Dbg_Reg_En_4 => Dbg_Reg_En_4,
Dbg_Capture_4 => Dbg_Capture_4,
Dbg_Shift_4 => Dbg_Shift_4,
Dbg_Update_4 => Dbg_Update_4,
Dbg_Rst_4 => Dbg_Rst_4,
Dbg_Clk_5 => Dbg_Clk_5,
Dbg_TDI_5 => Dbg_TDI_5,
Dbg_TDO_5 => Dbg_TDO_5,
Dbg_Reg_En_5 => Dbg_Reg_En_5,
Dbg_Capture_5 => Dbg_Capture_5,
Dbg_Shift_5 => Dbg_Shift_5,
Dbg_Update_5 => Dbg_Update_5,
Dbg_Rst_5 => Dbg_Rst_5,
Dbg_Clk_6 => Dbg_Clk_6,
Dbg_TDI_6 => Dbg_TDI_6,
Dbg_TDO_6 => Dbg_TDO_6,
Dbg_Reg_En_6 => Dbg_Reg_En_6,
Dbg_Capture_6 => Dbg_Capture_6,
Dbg_Shift_6 => Dbg_Shift_6,
Dbg_Update_6 => Dbg_Update_6,
Dbg_Rst_6 => Dbg_Rst_6,
Dbg_Clk_7 => Dbg_Clk_7,
Dbg_TDI_7 => Dbg_TDI_7,
Dbg_TDO_7 => Dbg_TDO_7,
Dbg_Reg_En_7 => Dbg_Reg_En_7,
Dbg_Capture_7 => Dbg_Capture_7,
Dbg_Shift_7 => Dbg_Shift_7,
Dbg_Update_7 => Dbg_Update_7,
Dbg_Rst_7 => Dbg_Rst_7,
Dbg_Clk_8 => Dbg_Clk_8,
Dbg_TDI_8 => Dbg_TDI_8,
Dbg_TDO_8 => Dbg_TDO_8,
Dbg_Reg_En_8 => Dbg_Reg_En_8,
Dbg_Capture_8 => Dbg_Capture_8,
Dbg_Shift_8 => Dbg_Shift_8,
Dbg_Update_8 => Dbg_Update_8,
Dbg_Rst_8 => Dbg_Rst_8,
Dbg_Clk_9 => Dbg_Clk_9,
Dbg_TDI_9 => Dbg_TDI_9,
Dbg_TDO_9 => Dbg_TDO_9,
Dbg_Reg_En_9 => Dbg_Reg_En_9,
Dbg_Capture_9 => Dbg_Capture_9,
Dbg_Shift_9 => Dbg_Shift_9,
Dbg_Update_9 => Dbg_Update_9,
Dbg_Rst_9 => Dbg_Rst_9,
Dbg_Clk_10 => Dbg_Clk_10,
Dbg_TDI_10 => Dbg_TDI_10,
Dbg_TDO_10 => Dbg_TDO_10,
Dbg_Reg_En_10 => Dbg_Reg_En_10,
Dbg_Capture_10 => Dbg_Capture_10,
Dbg_Shift_10 => Dbg_Shift_10,
Dbg_Update_10 => Dbg_Update_10,
Dbg_Rst_10 => Dbg_Rst_10,
Dbg_Clk_11 => Dbg_Clk_11,
Dbg_TDI_11 => Dbg_TDI_11,
Dbg_TDO_11 => Dbg_TDO_11,
Dbg_Reg_En_11 => Dbg_Reg_En_11,
Dbg_Capture_11 => Dbg_Capture_11,
Dbg_Shift_11 => Dbg_Shift_11,
Dbg_Update_11 => Dbg_Update_11,
Dbg_Rst_11 => Dbg_Rst_11,
Dbg_Clk_12 => Dbg_Clk_12,
Dbg_TDI_12 => Dbg_TDI_12,
Dbg_TDO_12 => Dbg_TDO_12,
Dbg_Reg_En_12 => Dbg_Reg_En_12,
Dbg_Capture_12 => Dbg_Capture_12,
Dbg_Shift_12 => Dbg_Shift_12,
Dbg_Update_12 => Dbg_Update_12,
Dbg_Rst_12 => Dbg_Rst_12,
Dbg_Clk_13 => Dbg_Clk_13,
Dbg_TDI_13 => Dbg_TDI_13,
Dbg_TDO_13 => Dbg_TDO_13,
Dbg_Reg_En_13 => Dbg_Reg_En_13,
Dbg_Capture_13 => Dbg_Capture_13,
Dbg_Shift_13 => Dbg_Shift_13,
Dbg_Update_13 => Dbg_Update_13,
Dbg_Rst_13 => Dbg_Rst_13,
Dbg_Clk_14 => Dbg_Clk_14,
Dbg_TDI_14 => Dbg_TDI_14,
Dbg_TDO_14 => Dbg_TDO_14,
Dbg_Reg_En_14 => Dbg_Reg_En_14,
Dbg_Capture_14 => Dbg_Capture_14,
Dbg_Shift_14 => Dbg_Shift_14,
Dbg_Update_14 => Dbg_Update_14,
Dbg_Rst_14 => Dbg_Rst_14,
Dbg_Clk_15 => Dbg_Clk_15,
Dbg_TDI_15 => Dbg_TDI_15,
Dbg_TDO_15 => Dbg_TDO_15,
Dbg_Reg_En_15 => Dbg_Reg_En_15,
Dbg_Capture_15 => Dbg_Capture_15,
Dbg_Shift_15 => Dbg_Shift_15,
Dbg_Update_15 => Dbg_Update_15,
Dbg_Rst_15 => Dbg_Rst_15,
Dbg_Clk_16 => Dbg_Clk_16,
Dbg_TDI_16 => Dbg_TDI_16,
Dbg_TDO_16 => Dbg_TDO_16,
Dbg_Reg_En_16 => Dbg_Reg_En_16,
Dbg_Capture_16 => Dbg_Capture_16,
Dbg_Shift_16 => Dbg_Shift_16,
Dbg_Update_16 => Dbg_Update_16,
Dbg_Rst_16 => Dbg_Rst_16,
Dbg_Clk_17 => Dbg_Clk_17,
Dbg_TDI_17 => Dbg_TDI_17,
Dbg_TDO_17 => Dbg_TDO_17,
Dbg_Reg_En_17 => Dbg_Reg_En_17,
Dbg_Capture_17 => Dbg_Capture_17,
Dbg_Shift_17 => Dbg_Shift_17,
Dbg_Update_17 => Dbg_Update_17,
Dbg_Rst_17 => Dbg_Rst_17,
Dbg_Clk_18 => Dbg_Clk_18,
Dbg_TDI_18 => Dbg_TDI_18,
Dbg_TDO_18 => Dbg_TDO_18,
Dbg_Reg_En_18 => Dbg_Reg_En_18,
Dbg_Capture_18 => Dbg_Capture_18,
Dbg_Shift_18 => Dbg_Shift_18,
Dbg_Update_18 => Dbg_Update_18,
Dbg_Rst_18 => Dbg_Rst_18,
Dbg_Clk_19 => Dbg_Clk_19,
Dbg_TDI_19 => Dbg_TDI_19,
Dbg_TDO_19 => Dbg_TDO_19,
Dbg_Reg_En_19 => Dbg_Reg_En_19,
Dbg_Capture_19 => Dbg_Capture_19,
Dbg_Shift_19 => Dbg_Shift_19,
Dbg_Update_19 => Dbg_Update_19,
Dbg_Rst_19 => Dbg_Rst_19,
Dbg_Clk_20 => Dbg_Clk_20,
Dbg_TDI_20 => Dbg_TDI_20,
Dbg_TDO_20 => Dbg_TDO_20,
Dbg_Reg_En_20 => Dbg_Reg_En_20,
Dbg_Capture_20 => Dbg_Capture_20,
Dbg_Shift_20 => Dbg_Shift_20,
Dbg_Update_20 => Dbg_Update_20,
Dbg_Rst_20 => Dbg_Rst_20,
Dbg_Clk_21 => Dbg_Clk_21,
Dbg_TDI_21 => Dbg_TDI_21,
Dbg_TDO_21 => Dbg_TDO_21,
Dbg_Reg_En_21 => Dbg_Reg_En_21,
Dbg_Capture_21 => Dbg_Capture_21,
Dbg_Shift_21 => Dbg_Shift_21,
Dbg_Update_21 => Dbg_Update_21,
Dbg_Rst_21 => Dbg_Rst_21,
Dbg_Clk_22 => Dbg_Clk_22,
Dbg_TDI_22 => Dbg_TDI_22,
Dbg_TDO_22 => Dbg_TDO_22,
Dbg_Reg_En_22 => Dbg_Reg_En_22,
Dbg_Capture_22 => Dbg_Capture_22,
Dbg_Shift_22 => Dbg_Shift_22,
Dbg_Update_22 => Dbg_Update_22,
Dbg_Rst_22 => Dbg_Rst_22,
Dbg_Clk_23 => Dbg_Clk_23,
Dbg_TDI_23 => Dbg_TDI_23,
Dbg_TDO_23 => Dbg_TDO_23,
Dbg_Reg_En_23 => Dbg_Reg_En_23,
Dbg_Capture_23 => Dbg_Capture_23,
Dbg_Shift_23 => Dbg_Shift_23,
Dbg_Update_23 => Dbg_Update_23,
Dbg_Rst_23 => Dbg_Rst_23,
Dbg_Clk_24 => Dbg_Clk_24,
Dbg_TDI_24 => Dbg_TDI_24,
Dbg_TDO_24 => Dbg_TDO_24,
Dbg_Reg_En_24 => Dbg_Reg_En_24,
Dbg_Capture_24 => Dbg_Capture_24,
Dbg_Shift_24 => Dbg_Shift_24,
Dbg_Update_24 => Dbg_Update_24,
Dbg_Rst_24 => Dbg_Rst_24,
Dbg_Clk_25 => Dbg_Clk_25,
Dbg_TDI_25 => Dbg_TDI_25,
Dbg_TDO_25 => Dbg_TDO_25,
Dbg_Reg_En_25 => Dbg_Reg_En_25,
Dbg_Capture_25 => Dbg_Capture_25,
Dbg_Shift_25 => Dbg_Shift_25,
Dbg_Update_25 => Dbg_Update_25,
Dbg_Rst_25 => Dbg_Rst_25,
Dbg_Clk_26 => Dbg_Clk_26,
Dbg_TDI_26 => Dbg_TDI_26,
Dbg_TDO_26 => Dbg_TDO_26,
Dbg_Reg_En_26 => Dbg_Reg_En_26,
Dbg_Capture_26 => Dbg_Capture_26,
Dbg_Shift_26 => Dbg_Shift_26,
Dbg_Update_26 => Dbg_Update_26,
Dbg_Rst_26 => Dbg_Rst_26,
Dbg_Clk_27 => Dbg_Clk_27,
Dbg_TDI_27 => Dbg_TDI_27,
Dbg_TDO_27 => Dbg_TDO_27,
Dbg_Reg_En_27 => Dbg_Reg_En_27,
Dbg_Capture_27 => Dbg_Capture_27,
Dbg_Shift_27 => Dbg_Shift_27,
Dbg_Update_27 => Dbg_Update_27,
Dbg_Rst_27 => Dbg_Rst_27,
Dbg_Clk_28 => Dbg_Clk_28,
Dbg_TDI_28 => Dbg_TDI_28,
Dbg_TDO_28 => Dbg_TDO_28,
Dbg_Reg_En_28 => Dbg_Reg_En_28,
Dbg_Capture_28 => Dbg_Capture_28,
Dbg_Shift_28 => Dbg_Shift_28,
Dbg_Update_28 => Dbg_Update_28,
Dbg_Rst_28 => Dbg_Rst_28,
Dbg_Clk_29 => Dbg_Clk_29,
Dbg_TDI_29 => Dbg_TDI_29,
Dbg_TDO_29 => Dbg_TDO_29,
Dbg_Reg_En_29 => Dbg_Reg_En_29,
Dbg_Capture_29 => Dbg_Capture_29,
Dbg_Shift_29 => Dbg_Shift_29,
Dbg_Update_29 => Dbg_Update_29,
Dbg_Rst_29 => Dbg_Rst_29,
Dbg_Clk_30 => Dbg_Clk_30,
Dbg_TDI_30 => Dbg_TDI_30,
Dbg_TDO_30 => Dbg_TDO_30,
Dbg_Reg_En_30 => Dbg_Reg_En_30,
Dbg_Capture_30 => Dbg_Capture_30,
Dbg_Shift_30 => Dbg_Shift_30,
Dbg_Update_30 => Dbg_Update_30,
Dbg_Rst_30 => Dbg_Rst_30,
Dbg_Clk_31 => Dbg_Clk_31,
Dbg_TDI_31 => Dbg_TDI_31,
Dbg_TDO_31 => Dbg_TDO_31,
Dbg_Reg_En_31 => Dbg_Reg_En_31,
Dbg_Capture_31 => Dbg_Capture_31,
Dbg_Shift_31 => Dbg_Shift_31,
Dbg_Update_31 => Dbg_Update_31,
Dbg_Rst_31 => Dbg_Rst_31,
bscan_tdi => bscan_tdi,
bscan_reset => bscan_reset,
bscan_shift => bscan_shift,
bscan_update => bscan_update,
bscan_capture => bscan_capture,
bscan_sel1 => bscan_sel1,
bscan_drck1 => bscan_drck1,
bscan_tdo1 => bscan_tdo1,
bscan_ext_tdi => bscan_ext_tdi,
bscan_ext_reset => bscan_ext_reset,
bscan_ext_shift => bscan_ext_shift,
bscan_ext_update => bscan_ext_update,
bscan_ext_capture => bscan_ext_capture,
bscan_ext_sel => bscan_ext_sel,
bscan_ext_drck => bscan_ext_drck,
bscan_ext_tdo => bscan_ext_tdo,
Ext_JTAG_DRCK => Ext_JTAG_DRCK,
Ext_JTAG_RESET => Ext_JTAG_RESET,
Ext_JTAG_SEL => Ext_JTAG_SEL,
Ext_JTAG_CAPTURE => Ext_JTAG_CAPTURE,
Ext_JTAG_SHIFT => Ext_JTAG_SHIFT,
Ext_JTAG_UPDATE => Ext_JTAG_UPDATE,
Ext_JTAG_TDI => Ext_JTAG_TDI,
Ext_JTAG_TDO => Ext_JTAG_TDO
);
end architecture STRUCTURE;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Sun Jun 18 18:41:14 2017
-- Host : DESKTOP-GKPSR1F running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/MartjnMirandaMe/clkdiv/clkdiv.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
-- Design : clk_wiz_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_wiz_0 is
Port (
clk_out1 : out STD_LOGIC;
reset : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end clk_wiz_0;
architecture stub of clk_wiz_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1";
begin
end;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
e5xVIDBGzQkhDoQ5sfeAF2q83P6A1Z/qsmlSYQJY5xTravGd4CV8IrniJyUa6zNomwm8ijfsSBDZ
3Cv5fk91Hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JTncam9YaU88Ye5zsiMSZerKzQZ8ndV/jFOlVBJ2+1NMrth4ym5MZgOOJUn+hqDs7WawEc66qp7n
dAXASYJYn+qFnCtyUAhIyvGYbamoaDWo5Ex6WN67wq/uxVFQHJyQE9mBWmFUuyQbfWAxdn0X8Ddd
XBKhuVWHjadjfvTndGU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WysH5jibOCiuNoaEF/J6UEux/f9qwkqszrQvmOG1LAQguVnzJ7+cmZtEvDLaeM5SMkI/c6AvWtXW
QAEuUSUqI7fc7s94OSdoy/EO2eWxzu/2PZr3+Vm/RDQkA2VgY92Mk7iTSAe4nvupzjwLJJp7MPFn
W0Qp6hutV366SMmocbalqT6lFUEm3BdJRb/waOPaQXsiK/eXFOfDC+OkXBIeDSI4U6bTS5BbTI6J
pFf7UmKKQ3+TO+1O/Q+2hW5WOgJzIUFjgYlL/k7HV9GLoiTkFeWQv9D4PmITDLLqEoJBQEH042D6
w9tSjJ90YaeXyJsQBc944KHiROaj7JIGL9ptSg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HfnNrIheX+bmcZCjcmnXLaiCn2W6T6H6Dp6dScskVGNGAylFhqrXsMMXHrPiUKf5LFkT6rGH4xNt
DnPlwzwiCAkQpMo27mNuJmSmEL1NZn19+z1IhIkgUjJMK+DU6V8j1HJvLoBzdBKXeOfEsIha7CfH
SYvgpUYxukUrvYeSdDM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FcdqosqcEEFjwfToDdg81IlS3kR13BUL9UoyGE7K0tYyJxwBRWvuEZwjlqyLvEdW74UEcoL322wG
MsjKrbrYQdHQMnu0VAIvQRAp+YUu8ZY/Amts9d4uoKQ4ceZKPNKKjhA2gLCTZlClOnHdKjhfnFhg
C4vFlIgGFFvgy7hYPvMYgUjBeujuUeMJVrfDQoBe2vY01NCaYs8PD38+MZrB1yBWXtoIH1Kudp5s
6rfzNC3iiU875HSyCH3s6Fgf+5qupOBLk1FOGYXDOgVB80WiCFsXlSgDSubN5g0HTJQJ5d2+rdH3
3+ADIpk9sqzMVdE2qp7yCA7kfUMNWwWOq2rtCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
4aK9nRWvVjlxIKF2x0qa9NV2t2mDrtthn+IbFT1fLWLDi9rczbae6bVONr1iJ6T4G8DETIVjBuY1
MnCmGcGz7CNbpq8u7J9aftYj2DQplUrwMmZQLI+iAsHWiuJzWU0b3FwfDqw32es7iPEO18SBbM11
AUYaZZkc5wmppvidg61k5iWmxF2/QEuB32yh+4rpuC8NxJdUc+fFl50TrjaknACqtyakfrSijiLr
V0N52T4m43DQRqYCpbvhs+mSRfQ2URyq3jAPeEuK3E+VtkaEMSRPcQJRZ6Q74LSybWpA+/PHMipH
IpvPOBIeGAeHqQ4qfRoR85Fvnj3xqr0rYAZs9/PEuPq3tAkWARp+CpULmmP/TsbRLDio6GgMjVl7
U0NgEoDGiYPf3wiQHNgNSmmD5UQVZwWB53EvOzwZ/RzPldIGz/wnsrQI5zJ7z+pteyjeG65/ckXJ
Ics9LDsjNdVCW15zIvW30VXS2LZghDynNaUMe5cdPpUmLPmlo0/fXC0LEzISnh+vX01/mFVIDN9R
LN1oXm2CMQfAHY/r3FOUqBfT3S5q3Pd9WiF6yfxA0pFeLxe/Nn+J61Pimb0i2tU4gNGNbIWqblVz
qkVyDTDoXDQYktHBMBpOl/TisHiMqXxxML+/jXqqAeP/jYyWxewwtoDZMxbBkrQqyv59n3aRWFzn
w+B44DiTyzPwvzmfUH8Vxxp5d/lENcT2D6LDIInJfZCTncF0uR1izDTomkfytyCG8UYmX3Jqo/yJ
FewjGVcSzt24nErLjAq8w6Pp3euilgx9LiBCGt9bcTBDdlZJJmHTtd3CSQOkjzYZ7XkQpjFyuYia
2XuG6TM/mTIWpaNoQVVoVwpXQM4IQEVHtlwRaC9fHriMinq6z2bi1IgXcMH6Jc22hOz2O9o3XxRk
ZZyhZF1Wn+fXHg6DYUj8UV8k4VzFO5cqbns+Gz03dHJpIkTMJGLL8fQqNbb+fJXwMqOv0EgV9dIR
rkkFtsiWD1UlNN0ie0wQIdTKrarBvYB8TuAmRjGVBOOzNjszRI+cC1p9ZhFpRDi6uDzqHXfo7hKI
7guyj6kn1yBgE52TfQDoQ9dqZEPTPgSQ94AzyD9HX9MdYgRM3fS50E+5iXiL82TRQsXARVDs/+yQ
5fo20BSJr4jOiO36moIM080YyeIu0UeZFeVblsdWBLt9p3HmHzdpnRgB+NXiFB5Hla7DIH9mImd5
EYcCe8JVfLlfSIpTC0vFymFvDOEiy5qqFp0fJK7Rlo9x0bwFADHdN0OfNv81Ax04VcmKC2SwKwCw
+UoDIEhCWUq5lVvA8ojO5GJkpJv3Q6DIvDlYBTK+TvOyJJ85ZRWck6ShdYBTKyGCyVCegiTY+bHq
Uq4ARs6gGYQ0m6Gi6tUhGmA9rvuaDzD3F8MSttOMjpfGIEPiFNeoATT/drJQgacG3Y82B/UaGyQD
oHwz03SrOPI7Tt27c93neen3xKkxnigJSc6q/OYLTzmxFgSUp8AVtyvqOX53PeGyc212H0K3sKeg
ClsKXM5PxFpyEPRsGBtxb6oQ15DWX/RfCcrZOspcOSw1EJRD39X+0+hm+nWdwTwpqhXtn14z4L5W
J4FbcclLMhXGlbpSsynMq/MnhEcb12sMxv6b8yTdTTk8CoPPc+MmkJXfMqjScYNmAkn5fYXn5Kbc
DcXAwQtRmZ0jO2gWo2fgno/uJxPGb+fdtDwWXAb6A2R8Y3nWI3kcmtF4NBAoROImC4FE/eeQegD0
IYl3qFZ35wHfIMWFZ287DaHfHeN8tfK+UuLfcmjH3Au37F21bUuzSgYspUpqPPeO5ZuJeudiKkgV
jqE3KlmbfkZZJZzOxPhFv2LqJZhrRGFYbkW+4O5ElcZd6babRC5y/+tTXut3vqsO3vN1S0nVPKh7
oq4ynJV+GYop64mBRIYFAz7RdM0i/Dn3tWB7aym6JEYrUkSmu6geUVAb9/PNisGIwwxR1HqhNE23
q8Y61H6SY3iMjFBOsitoteJLsh5M1Rgysaa/lWh4YnTFf2N2er2k4tJK/dynOqmJteWPmwBvp+9E
kuLxYbN1km2qvRZtuBesiW6tI89Q+mXCbJacwlv1VShV8/VBBN69BWfM/PjAsDD1lc4TGefASP7r
4NGYxNCUQO/7x+9k8kOaxbs2U0f5m9lsRn/b9n5ZYY/tkwUvy6p3Wn2pz8iguNQGEoXM/Tt+JJH5
cdsDW4UnCDcAN6hMAiUPN4FYS5kUhfeTviG2b6dVfXMCKCnD8PBBv0meZb67xvHxuxwI4qg81IhX
b7OvY2YjXQzuYrNtiinH92hRJXfFX4z1Dl5M6QPDsEkp59xTUxWHUFdr5r20Rn6JVWRqlGerZbN6
22mWO/z5gNPPZUJ+7SiX6B7IBe58BBW2Mvlw4PEHK/zlIOn2sjoIlitiA3tL4upIKpMvlB+r/7mZ
FWXeT1dbZLXCvtLNPTR9T/PnxMT/0ikRRHRCmqI0r0WDIV8N8k6NQYyEgqTcqVKG9P6pgVr/9b0B
4CY0LrXyVhFDzYYeIhIjWbqDYzbhu6wFEDmiZpdymniCsdZ8St2/DePgruxbYboH31Es90mQTKpC
0EhJ7V4b1M4+vAox6MOFFCfp9OWFNkUZcmUmYZb1l0NdGIBVz3CcDgnvD1lVeZcvwW9/ACQLJRxz
wSU62KvnojiWEVHPanl5Ar1dx4Jrk9HqYMEAyXHLLdLPSKHHq8yceyeDK9FqpjGj+pdbHCv1hfMx
max1sg+FTCRnyoVHWgd6NJaz7QA8T9jioTrGILX/EHMEySm4OQaw2GFt1vYLn/Alr+MGsw7D0bcz
qjOhkQ0QeBsgtz0z/Z2mAvl+1Gn7Hj9sulOo/ejH8EQf50K2Ng8qOYjmOv6H7rRw9AEeizg6IQgn
Z+5ccR5y8bgN3RA9UMShjPf85YYYwb2Ccr5E7tU0o3majPpyGwy2L6371mHcWNimqqOCy8YtJZGu
6jnMBdhlRBq2jNh3rxA2RY2U8MXYjaO8oeY2opVfbAFVehLIKVtlsBzLUt+CYwkmaxAtL5bOcEZY
nCSluBG7pEozMLKkN3vslg3caJIyoEuBi2SgCKWuRWvaEOc7BPB0H6pz+IxON0dUYnA3s8RdM9X3
VLbSl/AAxkbG9LF+cpYHUCBUo5euUKvIkV2CBeMKZOQl/0qzH4TmQHYW6yogDxfBSJfDTCqViq5c
nBFQ1GEJ2URhPaRojbDIY34r5pxIDHGQYw+2WkkYE6bDdR+O0Lc9AkjiqwlihNVlg23KtJuQgG3X
xpuImBIiNG2kJM7c2vG31/Z+31sXKrz6FE6FrwMDcodqbdY6oU9fbWsFQ+XHn1rs/tb0XlEAEK6z
+xW2icoEmZQlzNuYYL7d0ssnKCpuBXYMzIXbTl1zDxa1ankJSFTQAPvfOdOYzUJtuAcXtKBCTXjT
LsvcxEVB5dKcp3Nx4L6U/EUg4+ZghKZN6J4rGRf1k22oogZ7nPNG18z0bkUiiEiWpgLEtR61vMxI
T8Fgq5qu3NA8HTaTTqCOYLyaKntLXfABi7XvYOcIo2wYD/GlONQaz26/Sm5TqXBV1vxYvvHrU0/8
RQ0/gVfeIXMZXNgHVuMLukhMyUHFkJdRnijEnmishDmFSD0P9ArB9F4BosswXbdnzmpdAeuU+JtZ
WATDPT486Gs42vYYw81mZp+NYBoHob08pQ+dzkzbJk/DRD0BX72a0YnVkJfw3cq2i5TM0UZupnex
s157b8O5mtjrO8/LTW/5zta1PLPzBOBVJV9ESr42LX83BCIRZKWsYdd+Cm89m50XnTz0NRtDbwST
/RxJRs+BB9R7IYmhi0Y4C6O489uTTn5tMGkp1VMR6Ui0DneZqsFEq4WIjUG4QSu46E+RhvyJSxAS
YtR+8ma4XB/DpGVAQ+gb986Y+qd7XrwqS+mPoODY+Rh1qdDH+2lUjKuSZKpwMNjNqttGOp4YOakW
ljaORRukAoRtUisWF5j8YI3iimeLOUDWMXnMk9iocRdxSE590Q1Kt1rtbfAAmp9FnlulTW7BvLaW
tw17FMcSPHaLLx2+1on9+hEPk6IUtln6x6w4YKCKwpcaEiWkZ5d1aa1f3HCze9yWmwplVif4J/AX
bEdqWx58PIZHzBztJFFgrDazoeDolFskyXDFHALZbxd7mSAU2BuWPf++MBvYxBEigRFcvjefJQRU
SO3aHva1SoMv3nrsTaM4ksao1+NkQEnpPNVnkxNOm/OuUHmXCiGeLBvlJLRODV9VWvVF8BjxmCtS
WSbtW0YUV93FMmNIoOsANILkbU0bcgZfI5lS6UQEeFXz19i0ag2O5UP1zeE1bkKgAQPrbTsf0OcK
WYNtGySUizRLtqRcpiUowj9bW5sLe1LeD7fSmZHJh6WBOCUY5c1SBGidBlav1E4t+v7SdfOkMK0g
RrZSyGF8UGB0Ug58s9n6JidGuwqxHUvEuYgzkfJZXVbX/CT9gg3lGIuTJ5qPSOtb72p1Kr9sfZkN
gtPuQZGA2V6p/HOKNSgIzhbLwn+hUV4kQ6ZbY53FanDkiOVIq9hgagMzTwJpB7a6jrZDWmiv5a2E
hnx5p13b0s0UedCKAjwqG1CMJAYRhQtRcjzzXyXZZ0R8NJJJhWBpxHhbJ0ZHKKs7+4Uu3/oa6Gm4
0MQlDJADP5UHADUTKxF6MDly8Jh6ooD9I7I29mhuUYDpSeEsxP8Hw7sMAtaeXmXfo++BvLN7MWjf
iwPvX0HMtI/ZqV3ovcoYzBlss0IKmcgc/LK+VTuutvIYeLwoa1g9pNnJ6kierGxqdjkDwmzwSX1D
WjmXWqAHid+x6cMM0u320yJ+f6aBGrVKsjRXBFHyR0JYGBAb9FJsLx+ntkIgxGyzy+McqxuRIvFd
U14rXLF/cqixTaJXjJHGyiZGw4LI32NpEYNQ3LBHk2nac7lmBnv6P0A/haIDnonr+ggSeowiPA0v
zKEVy/Anv36fGp4BZBbygfc6F0m2UvHyxwx6q0y3l9BL7wto4GPl3qm5pePZNjbmPYPFug/Bic3G
chLmrdj5wS0Kf8o3e0Rgti3hdC4rFcRPRyGdfzQnvR2Hu29oOXefQh/6G1p/dH3F9eaOCRYm1T+b
HtDsOHLCkAlxpZCFbqYE49aefbddD7rVPNDZh4KBfJh9kGXZywEwKU8URlQYmJH2onBdV07Gtt74
+2DjwPrq1AXsWpXjQOdP3zkY4K0VYiZiK5aMC+GrzTTrC923SYj8gbZSCz432GzXI3MsV1oG7CWY
fSdSKof8+1s5pmVqYiMoYKnZfQnyBoSYWk5LmGCHeR1VBwI8Zv69+oD94zl3Cuc5u8FdnYp4Aq+j
zSnGWeKNJWm/XZiWgoAlutrPkRhHiNa3FJOnpXi9Vd6O5qoXyCkIgdmwAaqMf96KzyBKlo29JakM
/BPTE0WVrqCtHSSwtQCTRLjHp869XsvvKBBlF0BGcXSyhX5hSGYvNl0IWmZNQR8c3KiNVGvHTutS
1J1hBZrk9cyWRwI/San3ILnoyn2hsSE74hbJnr8+Rp7yzpno1F7vSSeo5FKj+XBOwYde8cL7nLxH
XTKH6CL9vFIIvmENyz2+hYPGCjapTwcmhD0vh8kXORle1c1cjRDCa3rDoRI4Y4bdvybl3KO5DB42
HqZoPKcUlh6+WU/YSnomHU3PX6UhXlt7AnRVaKa3BupudGRbGOtndayz+RYZKS8/xKkMxmcMaRXZ
09DDGfyzQ3X2Jl4ts8WMVPnIs/UVVv9qMtS44XHWe466ETYMFlIVkZ1ZpcCPDFdYi8DE4cbEruiK
t5F7nKi/In7prv9QfGho2D0srIxfWfKV06o+5uenw+wcZ0hi1G2KzWaulmUvRe7lVgn4I4E/U08C
dNnxH4TA8OPcL4PCu8jMkTuS9GYfMz3J8Kx6y9zSxHSgpIcviV9r1WtlOnHhvR3mispuAru3PRqM
YX1KCXTmNqONqeJPt7ZSrjz/oXwTH/YBY8ZNZy0V+qHRQM5ILccZBbd/0neFm3QRNmluVHm1CBr2
tuKpXs7HeYJCJi9bvEFcfXuwa39WHftKOxc2l/DONbEXVqviMt/pQvnb4ASDLb/oDd0PKEDFqix1
QcIkNR6SrZdBKwgYOfhispak/mscviRMBRVu1qDXuhorCZkEpUpdUGo3Js5Og53SJGcCb+nvHnuO
tSX+BbWKzGvUvIc56yAgELDeQpF8hkuqEtw4XXvsOCIGW0JmwgpJiC6GOMl2jngJd280tTQuTGd3
uL2vLQD14Q0ywqQ+IIJRmRmirtZAcgE5d44MmD3RCFaEYCLvqM0aBTzKb3KupiAklIB2xPsHdnSh
0U6fodMzCVKZ4PhP/1lmgbpV1Mx2eIGk7Y5tNHI1EJgCtXnem78ewL/8N1tcDw3Hg7oi63ud8uY7
Fv1aW9NByjBWbZKHa1lLOKI7xgNjkfJLFY/Gj9cCqOPUF4xnTHS7/92C2T41FqRHan7TEw10Qp0t
Uz8cbmZYy9rQSMZFLjkmKAb1D/DTB1+vC6qzAMB4RVOS5x93reznheRGxV/ZgJUtH/JtPTxmMjdM
uKIPVpbe4y5hbbAWChzuMVS+ujtarFSHsIhyFHbTUf65+GlUwJaE2Dr2/3wk2j/Dlocopva5PvHt
FJRWDxYsC7SY8mJXXZ55C8dFJE0jk1WVExUZEO84uSuB4+POFuvyCrzVQvc0wGu8Ir0VGq5MlXFp
4sBlYcn6ztA7zSFLk6UztfhI3UIQLIcbCvXOx4m5M98gVj1b0cy5tn6kZCNF9PaZ6bgUaD8llowC
OpDeBwsdp8ut18mv9fxOBFgkaln9NBA7n2sHmbLIdKpsmvx9ecKrrhPgbnhSbic+eQXrwecnRhAF
yUQbkkd/5d9mmRCzgdhXocyVy2NHizd5zsX2ShX4via0dVKQbmwakXxHkAwPYUPCqoPV8dUW8hKJ
9yiQ4yRxBSWGc7MlcqeXp+q2Nu6PXjuhi6IEE5PxkfsADNXnxdtYtmS1HtatmahwLX6ETSHlpyWN
0mdEEkMkObh15e2XkQpF5+Ge67cjMROeXRpW9x7QgqbesbO2KyZduaLPvpWs0g4uI811Xft1RVM7
haz1B8/vU16ZodJspc/8tn+oxyIip98/1M8pXNL3nfxszujQBcjn6aQyySCZ7c34mTuYuRztgU+N
981ppS/2iJ0g6Jt7KKxdRjlULrQNadR9bdbXO7QPkX/7g0L8IJ4Iku9ingOqwOkOI813pjUvGwUc
0aKdqNjnjwaVxoO8SFfRYPHz2dJi2IZZgkeKguxpL9HxYACdvFkwuvPR2lNLPAXB2ghJ2y5FAXP5
X7wHELeyIiZUiAYnlp+66Ea4sQJR2S4N0EZC39PriZEU8BZrjhlboH5/Pu0jGWcd7T/w4n761BWm
H9sDA72W9Tb68j1aDYCPP/ABG6qbVCbra9Ot+Z4OK1nlA78+5FvJ3tIJQAnZzgCEvdL5ZKHZbV9y
5ydYegQjw0r2Zq7RaAMDUas95D+n5m2Oez2iJ01CoM0BXxZeLeTvE/cZP6sNzKo4t6hQ3irPsjDg
yQblBhrTBg/CZhdKTRrnlWE/sdCr/mqNgUJ/TvyJzXE35cQw8KiR6twnBJZnaXElgC1MjSN2R7XW
GN20U+EBrv+xFfjqb9UkPVE+Iv6CQR8W6ScFzXMKxKd+ZrQwiKjNL0fSTNf9I/ME119CHOzmPo6p
KHo9wWf5PcYSwD7/vzJOebDTbqEof71cHlTV6QdoixOpybgJGI0mgrMfijnfCPGBkeNONNSqHEqb
GKlkETYKSYr5zY/aJRDHTufqtq0UPMLPr6UNG1SfLkD3XRVaMhmbpgOnInNFFrGBVDemvgAOOM5h
AQQqmXhZeYezksv0fYS4KUvt9ZiXRdNGYqTgZyfXOVi/gqdWwHybuq+6R0iVXxUJqntCNJ/W9NdR
uTHPXtZa/ErRtH8GpCOnVTZx8rNDT3XSFsvJNlX3DKh4ayUQI2KChkOhpwm3Z2CcVTHNhiGjnHrJ
ny6daaMZEX7XTP+Yiqj3m4h0m6Xo1l8eUv3TaY5A+LG7pZCsGVfCBfs4eF4pgThxoqNum6eMBX57
20gO5GIXHKbRnPQhufnb1aFJW4ukhxGl4CRZ2znum1mAQENqBpdfDq5wTJSC6b08Mmsl2dKugMtd
IDlLLPdoMk5D2KlHD0GQefeCzOza3oOW1HUsjXLrW8ugVQOnn+uGJbiqE0jeTeUbT3nfQZpiVTYQ
uNG8icfGXyabB13+Vi4kuA25gocLA2c99Cs3Et5G0n4gahbUo8nmuOmqvxXJK6uh6EBwlLn7u86D
9NtecIckktttuRSYppMZmUfzAfv4/ruxyVpu4AG1HVY3hp+Nh0Rbg0wbKIR0YbtGosZKAfL3RnL7
jT7cCRCTtW5AuknyPeBNN3w7ZvUKcySUb58gJTdmMD5c4ev27oQQm335yb0zVc4fs2IQVJK8YDdB
EUgmjzMKwo6Rgu6/yNJ44HEmODuAXp871awWsoLtYCO/FfmbppfBVX/45rFlDzBzc89Ql8j7HAVc
1KnvLS82qRdjFZfpC8JNSWEi9iYsWqWX23L5souT8Dccnv58yrkj3BO8DO5hPQcMvedIVQfdqgex
HNfI/OY+Z39vcvoCBNWyw8Gxj718s0WJEruxcdgNdrVTBza3MZllB2EyrP7HQ+F2OD72ffmznlQ1
mME8pEzedEfHlJu7zo69xPRGvaKG+9z9MQs4gE1deewywBEBABRixYzVRVkhm4rWmCiP4wpqMope
mca19hg/42MiiOkuYxe3yXmBiCNdgvL35TtVYqIKfJqDKJ+JN4selk9EEGcAaiODoeXjl96RXOBw
EP7E9LuNvQbTcVkTZTW0glaJbTN0Cq1rRevuZT4Op3qQ1k+c2T7tiYoTb85P0uav7l7uUKdoIarz
ellcV7FiL3Aa6t+dQMf/sZb1tGVlgrp7euu2vshmQE3XJYG3pb+ue9L8RE568LLt4J4CjR0SmDWk
IqXnp2AkA+xPpjSMDtLZxd18sApGI1Fyk8fasfUXOPCXXxZnS09ImK8w9bxqm1sYIfZdLDjPBWnh
zKBolZuc2PDzv3MU0x4dkucwYunAKS5OpxTESr36fGG1935x4/aQgTIoGS5usfXjEo9gMvzjE2Iw
jlZrqXFsBoU4MpaJlNHBe9Z9SCBnPMnxPdoVyMezUIfkmN+2WPtPl8yP7vtt5WAZOMQ1hIHFwUle
+eqE26AB4tcXU3oKYTQwErt2PxSMrw9MIzaR11G61KR38W2iXIjFXHWwsTs2DIkj9MVJ6nLclhvC
vkUM4cbXOe51eYgObwBOamtCb6mVgy7YJKn20WABL3KVYoUg+xPiuwU+dmc/dRCNEoNgY4oMJ4FE
y39LwQMS1iJ9X0K3Jot+PDECe0QtBkVWpkxD/0Nr+esN95Pqer5x1vkyYzwfy5MyDaiYPLXpkFzA
sa7gCKddRmAxmY+8Bqrzvx5BT/8y8FfyqrNjLw0E52kg1AZAWhMHyGJWpo8W1mxCgQMkIpmTjT4y
6HttKexCbX3f2/shojiPMRTlvx/OaA0FY/4EGaCJyaxkw0PxpKitnOgOjIGhIWiYngxiGJXrg77F
5gJ9AeNFRCUnSFK5SII/GNfDGG2kUi0ERy/HihtpOsIpMO7dD28d04nHNWjiZgGqcGSLeP/xp9qj
R8M/i2A5DjQ21vdU/udf6O8sCBDbwaEBEG4VOYNez2TaqM71zCsR2frRSFvEYah3CtaywxjE635H
pVrgFjoWpgbo/ECsazanpJLX3iy+DoRD+2GXnPZlOSBPSzb9RWawZ6yH8jcSG7zDKynjIgEyaxPB
RcAZUkVWKxve9kyLykSiBMA1yv30TZVG48QEuMpU3TQTrczHbSjDlFVbaziGbZsJtKFdwyA4wyH3
hYk3giJFqM58THA4FVK+V/WZmZ60cDhvi9Bod12vIOc662pKb0InZPYeU/i+XJMUnfNdG3E5xRPh
bTnStzc2fWu6F99XIq1USWMhRvj2AzYRwHaRQVcu2NLebnf8L5CU3zj7pcg2O8Hu45X6qRv7YW/Z
x7Sd/WXzKYCmnmXd0Hb6n8JCv4K+cgYbcdCAJIVoDWCDvXlizj9NlFwXEBTauXKHhBSx9mGmN5oM
HLhjue6aQdoZsfTirO42vvHLKrdxeE/Up1oM2T4dy+1OlVLaunvr2fl81EO/Fvu+ulWuXokk5uwr
EnZFcnAN5c0WssPYnbn2bSlUb2mGtc9M3Uvl3+8uo+7OcBZZJtyPnyZS9/Ai9C6syAHqor2ZMDXP
VwFZMRUlCif61os7ALddps51YDHcKc+ExUoyffrZ5fjJiRkZhM+oqiopH3ICuoz2bK+7n3dtzo1P
mqEMOzAvbmkDzBIDvg55S1f6c9/bjjFsRwi7HZreGYDw2dF7xtEOCorzR77Qx2B4h1Cu431cg8Sf
/X+y0dj+og8xVj9/8u4O/2VwV3unmAlCgGBwjy/IpR4Q0RgNvok1WK+vVDqxVybVLEwSvwQcOpMi
THU+UgAFgPNN2BLAy6MQzyeJt6ALYRXmsp/Z28kLqd8j8BoDwZ9d+hvXZBX/x/XDI9xBFPAQhDmn
/RlU8jWBlpYM/t9S/2vjWCoooc1y2Oa+WkzNTLIK5dhiAx8evwhDbB4pKAECx+OZuBza/uyYJbbw
9O2iSpFS3ZNIbNsqlttqgpFm9Q3gW2Mv2PK5Q3O6eIaEOeeabl3m1DMBZqhsBeS9XmIzNs3//uxl
kjSIdVscSLDqnHLoNBkIccMpNra1zPknY4FRxkZlruEsYWL6I7AlGEK6xn1IigpvzI+ctyPKdzEh
5B3hxWBbtDNOoJt+qKcuS0ANzKuBOuvPdtvJE/Y45Z2sbdKi9PTJspBHu3pPTJ1l0N0X1SVc16hk
rU7l9A4x8AMncqTYCKijZcbwCjXH0ro0D5gi8pOaHXfIrxtkbCoO5nBp3z4cTbjsqIT51AaNN42U
KwMWTlWiKjminvKEpmoqQ2KEj4PrTScaF/S52GL9a9E1prc0DBsxYcLRSF3UM4AoKB8v2ajkAx86
wX58YQpga/QPb/qEa6AHCeVxaYWPMUAUsBysHeOQ/H3fXNyGh2bvV6/w8DKcXZqnv7ojHFk+sl76
gMMrQ8iAn3DlkeInXMXt0/qc06Pp1sHSz2w2D67WLlBpGjsTCMixGFpP986ogkvXyyY9Z0CfH1UI
nZMBbv/8x+Q1UwFIIsxWviLszDYqbYXo+tCT/iNlPaA1kKn1cCCwhd3NmyR+nrljjKPe8y8O95+Y
hyhYskAPiE2c9y8uOyM0mGFnIIq0Atp15oOHunCnQKVzSjIr4UkgzGJgLT6ix8aWaLM0ENglYli6
1Go3RC08m8FNg7pVF41Oxr1PC90Qc677fcso5zSFb6cJ8YtOc6fJukVKdIp+jgy9QUdIxwvuB6eL
6ZQ3MenqeMjzJp7ldxj645/NRAxvNoEYljvTD2sZlhgBhDfKRqTqv3D5Ueta51/ujBxiz/DHtNAi
NqdVXXxDCNBwrXmuhOu05jx4h+3JLYLeemWI8mDsbOUIxIPE3b/+Mfox6+6574BqzdCgHonrL9Yw
QQWT9qtyjuQNa2vX+QoNC4RMudJIX2jtCQdQwAGQ3mGrjoukG/bP5ublze+UTeaS14KmsRiT5gRg
Jcwru+qllHkMq7xJU0737NcT/gERA2kIsTXjIFQD4aHYhUqu4DhpQa/TaWQVM83fCeo5rPsEPFp6
33aDxnvrIa2Q5/o0EH3ai5m4KiEyTd+MltNIB/a8lU+3UDPG+ISesHmsipcbtsQmi7CyisHnlioP
Qa96MQ1SPGqDYncMZ8gt1xGa5pv8rpZd8O5D0UiAiF1nwBLGFGVyINxJ/ekPw7hn0C5Ienue8q3H
b3mpMRCNQIdmY/y6ruHJjIL6XWYr9DJD/vdlVuWBuHA//87pggVA4MTYfmzXXHqJgc6CCf/CvVtF
S1lYqsgAkYy0M9Hyax46K5rDFlntypdir5L11k0t1oQGnRjVn+H7nmcbVf6gCIS8PRR8FekRwVTQ
g0EurL6ShBozppW3N8pLlO/AlKVglPnG3TPV5sUqBehXb+S1q5MTWQuC5/czdEq3LDrzjSAndxwd
PfeDCejZScO05FH/Ce/oveA2CSUyjkRyU0/DUQNIqucQn0bfKQwNlPZSZXuYYwAr7M3KNi4BnDhk
eS4X//kxYtFTup6jctfq61EnPZk71kDN+ORi5XhL2y+HdGZuKGOkQgpI+l8qLbpn8R+k+K+PCz99
GiOtB6D4S0qDSubF15IB+BZiVWABaKw4QnW1NtF0yZwm+5cGN5ldtBCNmBwjeCjnAgr1Rh4mlsTP
211zDqI9Y9jJfC1jsijJFu8kPOEO0aBj6avPWy80DrXK7421OiQSt0i+wVZb/uiPnk4grika1Flt
VX6G50S2y4PD5kOhO5hJChn+a2CZVCymU1BSV9rJ4PKJ1VZZagDe7gDjJRfyLUGt7+V1M7DcD5oD
R+OC2QImtkHSGV9Nr2WnIKocCo+lMW03HE2HIEVX8vYBe9bZsuVNeJcmtVnOb17NjfZUzcukV6yW
qN4iUJEcrZ1EN58wDvLHU4D260xXWHqYaG56/SnKlRV2/uQz8CRwiE5xCJSzdNB0aa52wdzimtCR
lW+cZk/I/8xwK5Td7H75PgQvD8lo7hxb86V4J8N/ePzK8PLR7rD32yA5djEIN2MBuUeuobmWabNA
IumojO0PdmA5NFjn7gdKzcEsQlKjjr/kjZ5kTMVCRJpcb/kSUEfrLeuIVnHvA9Lry34eEYce3U0B
ae0XNV+Ao3EcpYY+ZdMya79ZBSkq0l2bFYNGPeSFQCtSED4bQo9keDtgYzGMOXUUKDXIFqjoMFDU
rMZv+de4iygT6/0HACcUJiHbTX7JGs1xaGeviAntMwIdJ4FfoP6EWDMyh0RyEx4noc330sb+wER2
8UuJnkBP7K5LbEHKN8j6DJnpXx/v/v2CsaG3hDOJdxzR0svQI4Jo2BehF9p0qkoqz0zzAq+FwhyW
Qy00cX7K76JdugJoGjwfrCIo7Q8ONb7tjpFpYW7T4Q4jAC5vidzwKO2CmFqQkWDqzn89NUJ4DldF
XWC6TOsvCE2iasz2FHkdeaiyVUDSx54ZLb6fCiz7nKhkkFlZnYV+ZT/FlaOC8G/wjYWaY4jkgmlR
DVXmp0HE0JUfatxIKTPwi+mpORBSfyPXMZgxebpmR4o8IN1EmvZHvRSjO0sv8YqvP/3lURGhDNOn
XeXZFsT3k9tKC+4a1uZTDKHnrTTxieJkqXkeKLrER5aPAQaQtwudC3VBea1oq7a3DeqV46aT3IOx
hBvvQzO5EcJ6xofWZ/OTgpnI3IHnF1A9rcT+FbQwISSOfOiyKomQgGlC6Qq6EUZ0WIFaaK+mMrbU
Roz/kexZGdY9exSAF0JZreZwG0++1v3kPquIsZtjj3L6/vch3BUIpSDbphQQP3z3pYuQnulaVRO4
LeEpzHE3Gw6XpIbTwFmGPyQrY8rpOnvweIqAJLBwsqdWmWgxWINpIBQZEPK/uWzIHqEmCeCIZFfT
x2dkD94YNaWqDdkZ+S6OMjZHzs+AV7iJaNHlU+dlQ26phEaYyf3OuIMkV8YbsYtO4ekXPmYr0Xjb
JYVEP65jiJUgoTMPIY16RCAXugUGaTUgu/3fJbAlZs797ztl52naxrz9cJAiVXruU4Plx43aX3Xz
GnrZtc78vQgxkq8jmuoaPbZqZ49Bm20qp6/ZZFPXmnXjveXP7h8cSlntZG/sRJkWJG12T1rwCOFm
3XwR4S6OpvS5rUhtiyqwwgR3vYl5KHGgC1gFS7yeZOb9ho8iyIboaW0tOz+OZ+2YRhZbZ8zp82ry
go+jd3iz4gTMtVwS0VdHBo1w1+OJhE6R/naeUoBBCLPscAmvQQw90GayCVdYzoTZAKJCRnx5FkEn
jPza28ybMTjrp5POPEsyj+ceqTG+YKIAq8uwHzDRfLXlHQxjzVSs3HwTmSbNmuFXv2BepePoruQw
Zxk5osw2YjEO7ctAzU6z6lhpz5IOIfgIlveNQC6sWKgb8OQINcKsowq4R0nS8kqItZt2aLos7SIJ
EBqGbg8yfFESpRCMn0ljBuNQ5B7JotMXa52WhG1JXksfVuJv2pNid4cmNmhHALXSVf7mNmKbplXE
OpIOalpFsPC6UVLGTt20g+jFvKdPNZaEDm3gjR0L3VSONp0xBQyho1/Pr9tweZCmUGlDWGoE88YO
HbyFvGBmDem8lQuXbGJuzBLisUGtQPEMPT4t8tTgrDhQLYkj4Sj/aGbHfasakj137heCGfKSXbX6
dzlu7mzKuKOvu927L16umBogU7bWSY7Uhg3pTQoRpcHBn6LoHegKab9nup+/raZ80hSbJ+bu1SEY
drCvHaz1a4heCY/i2TR0YGtDOYGcStO+Y1Zbpyu2L+ETZO0Ho72jGrZnPepFFy30IJcrbRwZRtBh
U3hWGplKgoAZHT+X2rZwm1SyeijqpApaMTtUk3o2ndnwOuQ9G3RWLP624akw/j6UerUtJyKlhFf1
F79x9B7g8/wui7bfKhrCpLMZX0/zJHKlllb465vja+Addh8c7Qg4dCWSbetGmAGNvNrQotDEamyO
cXylWUyz3UABqJ3tI4kOy6NIvI5CDPLlr4OyS64VlKHeAT0V7NwICoYDc6GQskVSRRxzFzfmbxJ4
EqK+3Ek0c0GamslgY/EzarWxDbhfAa/Qjf9gRn73kmKCWRxx+XXRCnLjBML8V+0t+eq8FVOXJ2jH
hmIS9jiMqj1IL3lt8+xVrrCkUMW23kqWW59ndyt2BoZIh+PdckFOpFWJPq5worz5dIwrd8SqcHVm
8HZGLcPlS9baDQ1XTqkVo3fjpI1lIdJzz3yhRvOR/75tVKj0BfrU1RX8PTECZOG1nRCkNrTM102c
flaZlp3P8tY2BwU3snLV8IyTFXBB8q3lDa+rB6AkhSjQIKRZTSKooZs2aSQ6eCRwquxPQntfSMj6
8LeX9OpuQcbtbpOkfyHlBHEJvzrjTogsxoViEUkNO1DJurbcCI+T4gs5kN/jP6YirSMckW3Qm5T4
Kla6towUOaP+7kkQTaL/WGLFKajl1znUGF/InJAsmFeluvY2et3VlyPaFfDpbEkzK7s/Q3Au6QVf
EOj30zb51KsFclGzoryZDi1T3lVvG/UveeqQPCXPQU4jq9sK2kZVvTgjOH3isvx1vSutOzXGrW/Y
fv6av4uwMvsQjXGwG4SXdJW+62AqWUxAAgi0JWBBOuYZyJHz5KqOLQyBDAFRkTftVjtHIqoRLtWY
TGzYJTc+n5KBQP/NQ0AbolbyfxCyj8XTtVyly5UMjsqMOe1+MUdAmPi9IRQw2XZ5iIzDyaLZjqaV
Pln/c6Z5Cl64PS5kJwwXcyWz2oAnqq9g2yCtsWUMdmqhEeNKlybB38FdEOy1XBDqYT1FWQo8/u4x
s9cZ9txblxRA+lXG59Z0KI941eef++XnKPjN2ZOgdVS8gydYaQjJl+1jT+n1Tsx1CrDjUUPfLrte
xwEOXZ87qF8nTTaK2+ABEEmh23W1mqcZI7wqnb9Mbc/9CTQ3mhdedNlf8TQh7r8JP4sXQpGhqFV3
oPeHdaGzD+HSSpYT4+3F1HxRBGl6xw70c4mEtGGdflkMd3SDd9AlbQkNDK6njUlJD+QV7BOEpJyT
wbsZn/+KM9jSH5xQtIjotXvdHGCx8YfKHqYJDmmntG0F0F85cBVdc08bxlmjxpL8vjdyxTrnoHg2
W6bMgNuRMtxLPknEr/wDRH8QZDmK951bUiX2IIqaP2f7VLN6/oS2vGqe1DJNtPaiOy7dGI9TerxV
S3DCr5SQmUmvz/KHfMpqYdu2VScZqsh9aAxkvXvBwqg8XSczukWg5RnguRmEnAi7PdrbWO05qs/J
/5vnZMqdMlVN4HCFfSPHzA7/b5REquQmajz7XeYwnuufD5VM2u8qPdt4/kZuMfYVxiV1F7eD+gW+
BXIQxi3iVr/NBD9mAgv+clr8fG9Y0dAlOzqvj/Q/OqoggPs4wo09yxGjREMegxRi4nFS/iYlb8qG
rYdkQucL8foh8/CY+8QH84Df/YII8vlouQ8ij2rHeK58nCJ897/TYlEGTuV6hTZ1qERwgeIXJQ6C
8Di4j/wt8C3b2j64SF8yHeO8JPHtd3fG94lEoHKSQPF1Hu0eAnTedmT4etFUE2bfnsQpY9ZsEOCB
IJJtiPJGJGSIr4BMRbzmZtg5qeMpbBmri6QUUNHvnjaAtANWKuZkBOPL0SwqsKPq0783VOu0KAZJ
rJMt2A5wEEyk+td5LQ53F+rzJznjadYcBMhAnW+ikrqIoWcv/e7zjWKxLOZrPAdqJw5aLZ03iu+y
FEFXb8KZ/jjUd81fb8qbPPjtGgRWf3BjhyfapT5gb8CsAIllCwATwHEEw4F0YyUj9OdGpP6WHLaS
w/gRYiwE0Ay/pyJwL9/td72iVoOYsbH2PjbCa5+BVPHK9xjW4l6piDpDmBFORIgapfAi+Q9jNe+F
ZcWOx+e4AdJ84n6FlX38zkJCOndiY1McUQSzIY8YELMYfSZwGugBUuIVRoeT9Dwbt8HiUbypPVcD
37tIt4c7c2yGpi101MKG4OJ0n0HrAhrhbHBgSXQgWuv1HMi3VcmW4Zihk+qbWWyK3v+aqaLzzDJD
WLc4YHpCLVv6WwRrVtxVTw+h4swpA45ObaOtTAB3LCiPIlU6u/rdjNF+UOvPkmaUZAVHgcBdX7eq
iA7B33orJb8++w+AYdXxKAAUd/L56T9PxeTr3DqD9b2ffkL85xPsyOZRA1U1mlofY4J4dR6YPHmE
BP6qQrTOzEa8qfLs3wFvUMKzU3Q6tAoWd2Kcm5lfdEanPoFBiycznZCSNetD4sZYg/5CvgERlHRv
p5dbUL6FHwx1KSWYDQmA8Sh+6QLZJ8IohF6bayNcwEOu1WZj0ursCUF9QJbqv3A47h7lOn3Yi333
v0jaXanHo2UlSYUfnEY98KSzJ9FD4gZa6fATzR9OgdpWF9+YBWDd2kKUJw728qNwQT1ApV/Wddwj
T64AY0GG6HoinPJnxV7+73jw17w/RkCG9SFcxtZa/iMzWEjPiK3nixQNJiRsXfpaxQ3+9oigMjB8
xz2CcVeY8nGq1/XiEC6yQR/QvNvKtPbBXvl15/XhcPkMcmShAWCEknH7rK7fZ31bQbhZUVqu/9eM
ia8SB/4aSJaxelA6hOMewicbnLFrfpQJ3nTOzaP6fFY8FNRlxAdHcjvU6aefBV4TwUc66FzARSHm
AKHQ3xEHtdoSB4yOBppvZjzKoVOCm4QonfBCBS7SkOPHINRwTQMx8f9GKF3CRNMMSBekWi7MX85G
Hk3nSnfgRSgSqJZjYitlLonjfAb8yyIL55keYA/1W9lIINK22+AUs5mErs5KDs/YxsG3UELJqYUm
gsH2Ku6MHAfAbSjxXKuJ0XRR9RlheuqvbJgciDhn/TO4D5lFLos3lHQgj+oMkqJLGmDHv+8RDkQO
llBCRX8xL03EvJ/P+NxLIZVt4uwlIe4Lq2p4en0nBa3zVaore48R4dqG+7GP6WxQ2QORAFe/TsXi
+sTHfLIG1m+gxcgSwQRsvvGt/6GmhPxyDh0jmxOODWQs774MDVCf2D9cWN/fRdEEnWZGbkK1qn1+
FKkK+WhlSWEmJ4pzYnEaIkhJAJL/v3QTFAXplLuxP10OE1QmV7gxCg2sX6HFs8lR+fWgtuHosOYU
kOsozbnxc1g0PcAbhyUurHDBN907v7FqgAA/tm2raeLj5L+VcZLNzgyypLO8CEuJIcnVA5xlXSjs
fToO6XvV6cZL9Np6hNdHTAHq3tN+yaY2cogZHplfaSL6p/d2YkKX4LtzjXwDGw0wODGID/tDbzfQ
IoUUx4KJAx1INkelQJdGjdEOxyOpZfA4beQhCPGfKo6k3ddROeCjrhufkqRzOr67gWPfp/Oql++U
idg2Z9DY4/PfLmpWbEDWLJl6ionwJrIRyUj/RfbxGWtR5pmN7583Q0yYMiB7ueKFa5lZ8W/ERSR4
lsASSBeNg7iQun7TJWy13d2ZPQFBcj8YpswRZjwn4ACndI14V1PYfok/HvGUnHydwFkoGgTur8yt
YckxCyROZILbGEu5E4qyyld6OHn0KVN0OWAV5Xpg47KP5YL7f6oO8pXz0nAhpsdOx1zHZrA8gCso
zBeOy1aZgczNWJuIgVYdBd0LHQPlmC/JabOyyM29ToNoEhBF6KQpYKt7BN0zh4u5rQXh1bjYFRkC
p8f7O5gC0WYERfUFapF9sQRkeHVF0ihYReRFsW2yIWBkI38iy3PKKrOsoUQOrbET6OvNjdmBPyjo
oFLQ+SlMqLjJuiN/nkMRN5RldvuXqE/+SnqCHBh3MIlxJrFKLXJL2iANFeMifsR6Yfa1PccbfEL4
jRsWiz9k8CnjxMB0/yUT9qO4S5DggGGtx73EAa9QSEQPKlKVNyTUTPTTvDtj3P7CqwGhQLw9evMZ
LPmxa4NOj7GSTsERZGZnwu1lUdAh+56O+zejtGUAe9ypkxZfBm8c+NqG4xeXNLXnksNEYgSyKkOJ
9uwNWcLh4ixSGHUn2aF82WClfS5DoICSJqvsuRWqGHv1sO4C66v1zG7xI3REvxcpJPPskcEBLxL5
ucmVajPFyqqpqTjIEENYyvDB/10Dli5BE+DgXGJ2FkZt6BU6Hl0g7U0RUTnAHlIFJLj/HeVrLWNe
fK7MXbbEppZv0urqZNHwoSg1bitrjJjkwb7j8fIXDyk9syAqz9JCdqVJgZwL6aDkWbDOe7HksIva
Ru5vJzuEhUT2YMW5DscJ6PADTkyxO1Du251i9OewpAUoWU+GIpdvg96mJlaKHVYp9piQGZ8dDPyf
LzfZ31EacD03aCMzWK1GvZexekjDcR3mZ+4yM0Md62xt3ZRMASplgE7qwG2h1+20zHVW2g9JmLcL
f+uVJ/lqbQdeHfGD4iFCJhiPRPdmvqANs/juCejTZ3dzyhG9iMT/f8zhxDtMz17fpy9X0dw5Uf7I
MS0/vxQG3Selsw0etjGHm6HWg7zswjTU9BqSRLSegSWX56TvV3x9mnd2EAsytx0zJyKYWaiGlylO
yhsxUXrOTZMCSqPIA1/viEdVbEnGVoGVbtuliNwCgpmQVFXlfrCon+HSwj8QJlSQtbPgP3YQiD0A
Sq92oM7/Nei2NGQ+SUHDiZBPkdyUVtIpEMe75CHPCVRtYFmGiRkGHbYTDs1U+KVjfg/vuLXwnz+O
Jawy3w1flVk8bCMvWdrX3m3toE91+gGJPvWTsa+zRHbFkksTgSWP20yMt51sGIjTWNlpXBR/P3wY
d6GYpaM5EjKXJX3wm/fobRhmL2yuwnPPchWh15rw4YBX1lx+pn+MGGRKroqDTboSWpLoPNz5iJvR
A4PkCTZ/MAhpodeJJhLHg70QiBQY7ebReNCtgF2KmA+DQUIV2RZoLqOoqDJGoNHiwA3SXJmupzdu
EMmLUdLPR85TJaoBBEBC8zQNU597QzInw+YE7c4eA2975lf3tReQ71eY2JaQsG5vwxbFcHLCTgWE
h7eNMkUBKCdWuJPfWbkkCS7bulfS4NduV5WjPA4NPoZcE4Y3Q6WHimxlQLB/OJktqGRq+wJvLJtD
cLmxYARbF8LqpaIm4n94dTgjCqYenYWn0kBzj8vyigDhb4OgOnpKSubKvT4RWZmzvOHZos1pA1L4
zW1+QTdVypkdsQ8+KjQbjbOemLECgTMX6BFFrAkUtsYipvOJ0ZJgoS5BtDg2rD63HbC0/WQM3xpl
y+WmgyP5prCGQUfAiyRGdN2Vje6GiixKfS+dAPCbx4n1miMPJQxHcv36jcG+fKBAtRWK1RYcQaXx
l4cc8LNEtUxCHkvC4hhyhs8TmVishwGj3aWxZo9bhbZJeqKM6VW9zzB6TAXriBOGJC43pMC7RUBO
/xCh1TFaYhCxc9siwn5hs1bmiBUW9B9hy7PBoAXvBRfufcDLgrA1WKc4PGKtOowzmcxNip7gy3Nr
jkwhbH8ujsDAq8b60LRUDGvvqxpxEiD5AMO94V08JvqyAP5Ogr5GC3Rh29aIqDjUayPpMZXUuucW
PyhWXii5tNEtCGvJ2GLq6wynL0ofcKEbmmAuu4pAtzQpsdH8kpuRu03AJAdoPULZQtWzE+Tzstiq
4O444GNNM649CN2hNWR7D92AM8jVA/tKL8lk66UbILyq996BYjc3yIIamMIaw0XklO1XtmeH26Ad
HR8kXL4jwqm7lLSyHSqJ17NWWOo7k3Az/bdZHappuH7ODewi0rmtLxOk3+VGG+xwaVBZd+vQ/Ns8
S4zf5ew4heEzmKjqtA2YUKucYL8yHICqzqwGb7naxt46EE3tv6x9AjsGl833kulhyBzy0OyCod3+
7evYIexGofhKJwWiSD24rNvfkfmhAm2cXrl+dpIKZpGvzpqEKMlmMkQ5qSBrYozru5I6nWWMov+K
zwocnToZVa9SX8K556tabKoiv2doJ8b808+qGA82hf7JUKZuR8K+88tya2njBbsOYTjvOsUaHzFr
lL9yA9T2veRVPse0gY2Gj3wItR8vONMZxSblMXlheaEhZ+ng48ZkGoduuuo23IzqLDOIvkhzXq3+
XJoqqHMA/2Xt54gk3AFcVoUzeuDdw8xAAFi36gZfvDYu12Uz8aI3vLhoI/KIGoYXIktCRKpeTQ8t
7ffc9tC6DcUfian9Pb0A/ocE7BFN9bcBlZgdfAH+j4RJ8R9MmBCfjie9K6GZSjktVoxaG97VXJqi
hZzclxdE2cJuHmO0hMgR0fjryefVLkPCEhL3dWFcPoWucM3hUyqrQ/4e9yvxV/DrNAdnHMNN7mnB
DOLP9KMDxGgQgn/uQNwFbgpN2kSrezM4DVrVGnRQ3SjbDNZF9EOkcBdRHehwxokJbLEOuVswqJhP
OCHU+C7CogLBNGCCYbYgk2oY+djBulYEDnGB/bUNpDbM4iwteWTBgeNOlp0gxX/cHGl5QlRObnT5
tuszMh8FaogoqFgBAmTRL17zvNBQts7B4SE4qvsbonE6mnCYp6lLyi6gmFWsEYUkQlJkup4gA33T
fV5mUEyw6C8hjeCG1/lcFD+RHUas1GRcyechOhSJGBYjCLJORuDy7R8WBSobEWI9uiAuzMxLa3fE
CJBv3qgfnw41SuvbSHtMqyc7qgMC6Dlm6PA=
`protect end_protected
|
-- System_clock.vhd
--------------------------------
-- Generates all timing for the system
--------------------------------
-- Authors:
-- Åke Forslund
-- Terry Edberg
-- Göran Olsson
--------------------------------
-- Reused for WOLF experiment.
-- Time vector:
--M_TIME 0 32768 KHz
--M_TIME 1 16384 KHz
--M_TIME 2 8192 KHz
--M_TIME 3 4096 KHz
--M_TIME 4 2048 KHz
--M_TIME 5 1024 KHz
--M_TIME 6 512 KHz
--M_TIME 7 256 KHz
--M_TIME 8 128 KHz
--M_TIME 9 64 KHz
--M_TIME 10 32 KHz
--M_TIME 11 16 KHz
--M_TIME 12 8 KHz
--M_TIME 13 4 KHz
--M_TIME 14 2 KHz
--M_TIME 15 1 KHz
--M_TIME 16 500 Hz
--M_TIME 17 250 Hz
--M_TIME 18 128 Hz
--M_TIME 19 64 Hz
--M_TIME 20 32 Hz
--M_TIME 21 16 Hz
--M_TIME 22 8 Hz
--M_TIME 23 4 Hz
--M_TIME 24 2 Hz
--M_TIME 25 1 Hz
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY system_clock is
PORT(mclk, reset : in std_logic; -- mclk is 32.768 MHz
m_time : out std_logic_vector(25 downto 0) );
END system_clock;
ARCHITECTURE behaviour of system_clock is
signal s_time : std_logic_vector(7 downto 0) := (others => '0');
signal l_time : std_logic_vector(17 downto 1) := (others => '0');
signal flag : std_logic;
begin
m_time(25 downto 0) <= s_time & l_time & mclk;
-- Intermediate counter, 18 bit
process(mclk, reset)
begin
if reset /= '0' then
l_time <= (others => '0');
elsif falling_edge(mclk) then
l_time <= l_time + 1;
end if;
end process;
process(mclk, reset)
begin
if reset /= '0' then
flag <= '0';
elsif rising_edge(mclk) then
if l_time = '1' & x"FFFF" then
flag <= '1';
else
flag <= '0';
end if;
end if;
end process;
-- Slow counter, 8 bit, counts 0...249; MSB at 1 Hz
process(mclk, reset)
begin
if reset /= '0' then
s_time <= (others => '0');
elsif falling_edge(mclk) then
if flag = '1' then
if (s_time(7 downto 3) = x"1F") and(s_time(0) = '1') then -- 249; Don't check the zero bits
s_time <= (others => '0');
else
s_time <= s_time + 1;
end if;
end if;
end if;
end process;
end behaviour; |
----------------------------------------------------------------------------------
-- ------------------- --
-- | | --
-- S ---------| S Q |--------- Q --
-- R ---------| R | --
-- | | --
-- CLK ---------| CLK QN |--------- QN --
-- | | --
-- ------------------- --
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------------------------------------
entity LATCH_SR is
Port
(
S : in STD_LOGIC;
R : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : inout STD_LOGIC;
Qn : inout STD_LOGIC
);
end LATCH_SR;
----------------------------------------------------------------------------------
architecture Behavioral of LATCH_SR is
begin
-- One option
process(CLK, S, R)
begin
if (CLK'event and CLK = '1') then
if (S = '0' and R = '1') then
Q <= '0';
Qn <= '1';
elsif (S = '1' and R = '0') then
Q <= '1';
Qn <= '0';
elsif (S = '0' and R = '0') then
Q <= Q;
Qn <= Qn;
else
Q <= 'Z';
Qn <= 'Z';
end if;
end if;
end process;
end Behavioral;
|
entity repro3 is
end;
architecture behav of repro3 is
type bv_array is array (natural range <>) of bit_vector;
subtype byte_array is bv_array(open)(7 downto 0);
type mrec is record
b : boolean;
data : byte_array;
end record;
signal s : mrec (data(0 to 3));
procedure assign (signal sig : out mrec) is
variable a : mrec (data(1 to 4));
begin
sig <= a;
end assign;
begin
process
begin
assign (s);
wait;
end process;
end behav;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN16_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! direct data driver for EPROC_IN2 module
entity EPROC_IN16_direct is
port (
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (15 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN16_direct;
architecture Behavioral of EPROC_IN16_direct is
signal word10b : std_logic_vector (9 downto 0) := "1100000000"; -- comma
signal word8b_Byte0, word8b_Byte1, word8b_Byte0_s, word8b_Byte1_s : std_logic_vector (7 downto 0) := (others=>'0');
signal word8bRdy, word10bRdy, Byte_index : std_logic := '0';
begin
-------------------------------------------------------------------------------------------
-- input registers
-------------------------------------------------------------------------------------------
input_map: process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
word8b_Byte0_s <= edataIN(7 downto 0);
word8b_Byte1_s <= edataIN(15 downto 8);
word8b_Byte0 <= word8b_Byte0_s;
word8b_Byte1 <= word8b_Byte1_s;
end if;
end process;
-------------------------------------------------------------------------------------------
-- output (code = "00" = data)
-------------------------------------------------------------------------------------------
process(bitCLKx4, rst)
begin
if rst = '1' then
word8bRdy <= '0';
elsif bitCLKx4'event and bitCLKx4 = '1' then
word8bRdy <= not word8bRdy;
end if;
end process;
--
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if word8bRdy = '1' then
Byte_index <= not Byte_index;
end if;
end if;
end process;
--
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if word8bRdy = '1' then
if Byte_index = '0' then
word10b <= "00" & word8b_Byte0;
word10bRdy <= '1';
else
word10b <= "00" & word8b_Byte1;
word10bRdy <= '1';
end if;
else
word10bRdy <= '0';
end if;
end if;
end process;
dataOUT <= word10b;
dataOUTrdy <= word10bRdy;
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN16_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! direct data driver for EPROC_IN2 module
entity EPROC_IN16_direct is
port (
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (15 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN16_direct;
architecture Behavioral of EPROC_IN16_direct is
signal word10b : std_logic_vector (9 downto 0) := "1100000000"; -- comma
signal word8b_Byte0, word8b_Byte1, word8b_Byte0_s, word8b_Byte1_s : std_logic_vector (7 downto 0) := (others=>'0');
signal word8bRdy, word10bRdy, Byte_index : std_logic := '0';
begin
-------------------------------------------------------------------------------------------
-- input registers
-------------------------------------------------------------------------------------------
input_map: process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
word8b_Byte0_s <= edataIN(7 downto 0);
word8b_Byte1_s <= edataIN(15 downto 8);
word8b_Byte0 <= word8b_Byte0_s;
word8b_Byte1 <= word8b_Byte1_s;
end if;
end process;
-------------------------------------------------------------------------------------------
-- output (code = "00" = data)
-------------------------------------------------------------------------------------------
process(bitCLKx4, rst)
begin
if rst = '1' then
word8bRdy <= '0';
elsif bitCLKx4'event and bitCLKx4 = '1' then
word8bRdy <= not word8bRdy;
end if;
end process;
--
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if word8bRdy = '1' then
Byte_index <= not Byte_index;
end if;
end if;
end process;
--
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if word8bRdy = '1' then
if Byte_index = '0' then
word10b <= "00" & word8b_Byte0;
word10bRdy <= '1';
else
word10b <= "00" & word8b_Byte1;
word10bRdy <= '1';
end if;
else
word10bRdy <= '0';
end if;
end if;
end process;
dataOUT <= word10b;
dataOUTrdy <= word10bRdy;
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: weights_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY weights_tb IS
END ENTITY;
ARCHITECTURE weights_tb_ARCH OF weights_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
weights_synth_inst:ENTITY work.weights_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2347.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02347ent IS
END c07s02b07x00p02n02i02347ent;
ARCHITECTURE c07s02b07x00p02n02i02347arch OF c07s02b07x00p02n02i02347ent IS
BEGIN
TESTING: PROCESS
type SWITCH_LEVEL is ('0', '1', 'X');
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
variable LOGICV : LOGIC_SWITCH := '0';
variable INTV : integer;
BEGIN
INTV := 2 ** LOGICV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02347 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02347arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2347.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02347ent IS
END c07s02b07x00p02n02i02347ent;
ARCHITECTURE c07s02b07x00p02n02i02347arch OF c07s02b07x00p02n02i02347ent IS
BEGIN
TESTING: PROCESS
type SWITCH_LEVEL is ('0', '1', 'X');
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
variable LOGICV : LOGIC_SWITCH := '0';
variable INTV : integer;
BEGIN
INTV := 2 ** LOGICV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02347 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02347arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2347.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02347ent IS
END c07s02b07x00p02n02i02347ent;
ARCHITECTURE c07s02b07x00p02n02i02347arch OF c07s02b07x00p02n02i02347ent IS
BEGIN
TESTING: PROCESS
type SWITCH_LEVEL is ('0', '1', 'X');
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
variable LOGICV : LOGIC_SWITCH := '0';
variable INTV : integer;
BEGIN
INTV := 2 ** LOGICV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02347 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02347arch;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:29 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_rst_ps7_0_100M_0_sim_netlist.vhdl
-- Design : ip_design_rst_ps7_0_100M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute box_type : string;
attribute box_type of POR_SRL_I : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
port (
MB_out : out STD_LOGIC;
Bsr_out : out STD_LOGIC;
Pr_out : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
signal \^bsr_out\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^mb_out\ : STD_LOGIC;
signal \^pr_out\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Bsr_out <= \^bsr_out\;
MB_out <= \^mb_out\;
Pr_out <= \^pr_out\;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr_out\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr_out\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^mb_out\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^mb_out\,
S => lpf_int
);
SEQ_COUNTER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr_out\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr_out\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^mb_out\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr_out\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr_out\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
signal Bsr_out : STD_LOGIC;
signal MB_out : STD_LOGIC;
signal Pr_out : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal lpf_int : STD_LOGIC;
attribute box_type : string;
attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE";
attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE";
attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE";
attribute box_type of FDRE_inst : label is "PRIMITIVE";
attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Bsr_out,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
FDRE_inst: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => MB_out,
Q => mb_reset,
R => '0'
);
\PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Pr_out,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4,
Bsr_out => Bsr_out,
MB_out => MB_out,
Pr_out => Pr_out,
lpf_int => lpf_int,
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_rst_ps7_0_100M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "proc_sys_reset,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
attribute x_interface_info : string;
attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST";
attribute x_interface_parameter : string;
attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST";
attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST";
attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST";
attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK";
attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
|
--------------------------------------------------------------------------------
--! @file DualPortRam.vhd
--! @brief Dual port RAM
--! @author Takehiro Shiozaki
--! @date 2013-11-05
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity DualPortRam is
generic(
G_WIDTH : integer;
G_DEPTH : integer
);
port( -- write
WCLK : in std_logic;
DIN : in std_logic_vector(G_WIDTH - 1 downto 0);
WADDR : in std_logic_vector(G_DEPTH - 1 downto 0);
WE : in std_logic;
-- read
RCLK : in std_logic;
DOUT : out std_logic_vector(G_WIDTH - 1 downto 0);
RADDR : in std_logic_vector(G_DEPTH - 1 downto 0)
);
end DualPortRam;
architecture RTL of DualPortRam is
subtype RamWord is std_logic_vector(G_WIDTH - 1 downto 0);
type RamArray is array (0 to 2 ** G_DEPTH - 1) of RamWord;
signal RamData : RamArray;
signal WriteAddress : integer range 0 to 2 ** G_DEPTH - 1;
signal ReadAddress : integer range 0 to 2 ** G_DEPTH - 1;
begin
WriteAddress <= conv_integer(WADDR);
ReadAddress <= conv_integer(RADDR);
process(WCLK)
begin
if(WCLK'event and WCLK = '1') then
if(WE = '1') then
RamData(WriteAddress) <= DIN;
end if;
end if;
end process;
process(RCLK)
begin
if(RCLK'event and RCLK = '1') then
DOUT <= RamData(ReadAddress);
end if;
end process;
end RTL;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for time related expressions.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package time_pkg is
constant time_const : time := 200 ns;
subtype time_subtype is time range 0 fs to 1 ms;
end time_pkg;
package body time_pkg is
end time_pkg;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for time related expressions.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package time_pkg is
constant time_const : time := 200 ns;
subtype time_subtype is time range 0 fs to 1 ms;
end time_pkg;
package body time_pkg is
end time_pkg;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for time related expressions.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package time_pkg is
constant time_const : time := 200 ns;
subtype time_subtype is time range 0 fs to 1 ms;
end time_pkg;
package body time_pkg is
end time_pkg;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 23:19:33 11/16/2015
-- Design Name:
-- Module Name: ClockDiv - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ClockDiv is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_2t : out STD_LOGIC;
clk_4t : out STD_LOGIC;
clk_16t : out STD_LOGIC
);
end ClockDiv;
architecture Behavioral of ClockDiv is
signal clk_2t_q : STD_LOGIC := '0';
signal div_4t : STD_LOGIC := '0';
signal clk_4t_q : STD_LOGIC := '0';
signal div_16t : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal clk_16t_q : STD_LOGIC := '0';
begin
process (clk, reset)
begin
if (reset = '0') then
div_4t <= '0';
elsif (clk'event and clk = '1') then
div_4t <= not div_4t;
end if;
end process;
process (clk, reset)
begin
if (reset = '0') then
div_16t <= (others => '0');
elsif (clk'event and clk = '1') then
div_16t <= div_16t + '1';
end if;
end process;
process (clk, reset)
begin
if (reset = '0') then
clk_2t_q <= '0';
clk_4t_q <= '0';
clk_16t_q <= '0';
elsif (clk'event and clk = '1') then
clk_2t_q <= not clk_2t_q;
if (div_4t = '0') then
clk_4t_q <= not clk_4t_q;
else
clk_4t_q <= clk_4t_q;
end if;
if (div_16t = "0000") then
clk_16t_q <= not clk_16t_q;
else
clk_16t_q <= clk_16t_q;
end if;
end if;
end process;
clk_2t <= clk_2t_q;
clk_4t <= clk_4t_q;
clk_16t <= clk_16t_q;
end Behavioral;
|
-- File name: add_round_key_p.vhd
-- Created: 2009-04-26
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: parallel add round key stage
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add_round_key_p is
port (
data_in : in state_type;
key_in : in state_type;
data_out : out state_type
);
end entity add_round_key_p;
architecture dataflow of add_round_key_p is
begin
process(data_in, key_in)
begin
for i in index loop
for j in index loop
data_out(i, j) <= data_in(i, j) xor key_in(i, j);
end loop;
end loop;
end process;
end architecture dataflow;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use ieee.numeric_std.all;
entity tb is
generic(
address_width: integer := 15;
memory_file : string := "code.txt";
log_file: string := "out.txt";
uart_support : string := "no"
);
end tb;
architecture tb of tb is
signal clock_in, reset, data, stall, stall_sig: std_logic := '0';
signal uart_read, uart_write: std_logic;
signal boot_enable_n, ram_enable_n, ram_dly: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(15 downto 0);
signal gpiob_in, gpiob_out, gpiob_ddr: std_logic_vector(15 downto 0);
signal gpio_sig, gpio_sig2, gpio_sig3: std_logic := '0';
begin
process --25Mhz system clock
begin
clock_in <= not clock_in;
wait for 20 ns;
clock_in <= not clock_in;
wait for 20 ns;
end process;
process
begin
wait for 4 ms;
gpio_sig <= not gpio_sig;
gpio_sig2 <= not gpio_sig2;
wait for 3 ms;
gpio_sig <= not gpio_sig;
gpio_sig2 <= not gpio_sig2;
end process;
process
begin
wait for 5 ms;
gpio_sig3 <= not gpio_sig3;
wait for 5 ms;
gpio_sig3 <= not gpio_sig3;
end process;
gpioa_in <= x"00" & "0000" & gpio_sig & "000";
gpiob_in <= "10000" & gpio_sig3 & "00" & "00000" & gpio_sig2 & "00";
process
begin
stall <= not stall;
wait for 123 ns;
stall <= not stall;
wait for 123 ns;
end process;
reset <= '0', '1' after 5 ns, '0' after 500 ns;
stall_sig <= '0'; --stall;
ext_irq <= "0000000" & periph_irq;
boot_enable_n <= '0' when (address(31 downto 28) = "0000" and stall_sig = '0') or reset = '1' else '1';
ram_enable_n <= '0' when (address(31 downto 28) = "0100" and stall_sig = '0') or reset = '1' else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
process(clock_in, reset)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock_in'event and clock_in = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
-- HF-RISC core
processor: entity work.processor
port map( clk_i => clock_in,
rst_i => reset,
stall_i => stall_sig,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s;
data_write_periph <= data_write;
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock_in,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr,
gpiob_in => gpiob_in,
gpiob_out => gpiob_out,
gpiob_ddr => gpiob_ddr
);
-- boot ROM
boot0lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 0)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(7 downto 0)
);
boot0ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 1)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(15 downto 8)
);
boot1lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 2)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(23 downto 16)
);
boot1ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 3)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(31 downto 24)
);
-- RAM
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
-- debug process
debug:
if uart_support = "no" generate
process(clock_in, address)
file store_file : text open write_mode is "debug.txt";
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if clock_in'event and clock_in = '1' then
if address = x"f00000d0" and data = '0' then
data <= '1';
index := conv_integer(data_write(6 downto 0));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
writeline(store_file, hex_file_line);
line_length := 0;
end if;
else
data <= '0';
end if;
end if;
end process;
end generate;
process(clock_in, reset, address)
begin
if reset = '1' then
elsif clock_in'event and clock_in = '0' then
assert address /= x"e0000000" report "end of simulation" severity failure;
assert (address < x"50000000") or (address >= x"e0000000") report "out of memory region" severity failure;
assert address /= x"40000104" report "handling IRQ" severity warning;
end if;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DelayLine is
generic (
Depth : natural := 2;
Width : natural := 16
);
port(
din : in signed(Width-1 downto 0);
clk : in std_logic;
ce : in std_logic;
dout : out signed(Width-1 downto 0)
);
end DelayLine;
architecture behavioral of DelayLine is
type DelayType is array (0 to Depth-1) of signed(Width-1 downto 0);
signal DataBuffer : DelayType;
begin
dout <= DataBuffer(Depth-1);
process (clk)
begin
if rising_edge (clk) then
if (ce = '1') then
DataBuffer(0) <= din;
DataBuffer(1 to Depth-1) <= DataBuffer(0 to Depth-2); --XX
end if;
end if;
end process;
end behavioral;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 22 19:34:37 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_clk_wiz_0_0 -prefix
-- system_clk_wiz_0_0_ system_clk_wiz_0_0_stub.vhdl
-- Design : system_clk_wiz_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_clk_wiz_0_0 is
Port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end system_clk_wiz_0_0;
architecture stub of system_clk_wiz_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 22 19:34:37 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_clk_wiz_0_0 -prefix
-- system_clk_wiz_0_0_ system_clk_wiz_0_0_stub.vhdl
-- Design : system_clk_wiz_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_clk_wiz_0_0 is
Port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end system_clk_wiz_0_0;
architecture stub of system_clk_wiz_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1";
begin
end;
|
--
-- VGA interface for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity VIDEO_zpuino_wb_vga_hqvga is
generic(
vgaclk_divider: integer := 1
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- VGA interface
clk_50Mhz: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r2: out std_logic;
vga_r1: out std_logic;
vga_r0: out std_logic;
vga_g2: out std_logic;
vga_g1: out std_logic;
vga_g0: out std_logic;
vga_b1: out std_logic;
vga_b0: out std_logic
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
);
end entity VIDEO_zpuino_wb_vga_hqvga;
architecture behave of VIDEO_zpuino_wb_vga_hqvga is
-- Clock is 50 MHz Hor Vert
-- Disp FP Sync BP Disp FP Sync BP
-- 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
constant VGA_H_SYNC: integer := 120;
constant VGA_H_FRONTPORCH: integer := 56;
constant VGA_H_DISPLAY: integer := 800;
constant VGA_H_BACKPORCH: integer := 64;
constant VGA_V_FRONTPORCH: integer := 37;
constant VGA_V_SYNC: integer := 6;
constant VGA_V_DISPLAY: integer := 600;
constant VGA_V_BACKPORCH: integer := 23;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '0';
constant h_polarity: std_logic := '0';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
component zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0); -- 9 bits
mi_addr: in std_logic_vector(14 downto 0)
);
end component zpuino_vga_ram;
signal rstq1,rstq2: std_logic;
signal vga_ram_address: unsigned(14 downto 0);
signal vga_ram_data: std_logic_vector(7 downto 0);
signal v_display: std_logic;
signal ram_read: std_logic_vector(7 downto 0);
signal ram_we: std_logic;
signal vga_v_offset: unsigned(14 downto 0);
signal hoff: unsigned(2 downto 0); -- will count from 0 to 4
signal voff: unsigned(2 downto 0); -- will count from 0 to 4
signal hdisp: unsigned(13 downto 2);
signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
signal vga_r: std_logic_vector(2 downto 0);
signal vga_g: std_logic_vector(2 downto 0);
signal vga_b: std_logic_vector(1 downto 0);
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
vga_r2 <= vga_r(2);
vga_r1 <= vga_r(1);
vga_r0 <= vga_r(0);
vga_g2 <= vga_g(2);
vga_g1 <= vga_g(1);
vga_g0 <= vga_g(0);
vga_b1 <= vga_b(1);
vga_b0 <= vga_b(0);
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_ended<='0';
else
read_ended<=wb_stb_i and wb_cyc_i and not wb_we_i;
end if;
end if;
end process;
wb_ack_o <= wb_stb_i and wb_cyc_i and (read_ended or wb_we_i);
-- Read muxer
process(wb_adr_i,ram_read)
begin
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= ram_read;
end process;
process(wb_we_i,wb_cyc_i,wb_stb_i,wb_adr_i)
begin
ram_we <= wb_we_i and wb_cyc_i and wb_stb_i;
end process;
-- VGA reset generator.
process(clk_50Mhz, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(clk_50Mhz) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
-- Compute the VGA RAM offset we need to use to fetch the character.
vga_ram_address <= hdisp +
vga_v_offset;
ram:zpuino_vga_ram
port map (
v_clk => clk_50Mhz,
v_en => '1',
v_addr => std_logic_vector(vga_ram_address),
v_data => vga_ram_data,
-- Memory interface
mi_clk => wb_clk_i,
mi_dat_i => wb_dat_i(7 downto 0),
mi_we => ram_we,
mi_en => '1',
mi_dat_o => ram_read,
mi_addr => wb_adr_i(16 downto 2)
);
-- Horizontal counter
hcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
hoff <= (others =>'0');
hdisp <= (others => '0');
else
hcount_q <= hcount_q + 1;
if hoff="100" then
hoff <= (others => '0');
hdisp <= hdisp + 1;
else
hoff <= hoff + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end if;
end process;
hsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_BACKPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_FRONTPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
voff<=(others => '0');
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
voff <= (others => '0');
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
if voff="100" then
voff <= (others => '0');
vga_v_offset <= vga_v_offset + 160;
else
voff <= voff + 1;
end if;
end if;
end if;
end if;
end if;
end process;
vsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_BACKPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_FRONTPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if v_display='0' then
vga_b <= (others =>'0');
vga_r <= (others =>'0');
vga_g <= (others =>'0');
else
vga_r <= vga_ram_data(7 downto 5);
vga_g <= vga_ram_data(4 downto 2);
vga_b <= vga_ram_data(1 downto 0);
end if;
end if;
end process;
end behave;
|
--
-- VGA interface for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity VIDEO_zpuino_wb_vga_hqvga is
generic(
vgaclk_divider: integer := 1
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- VGA interface
clk_50Mhz: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r2: out std_logic;
vga_r1: out std_logic;
vga_r0: out std_logic;
vga_g2: out std_logic;
vga_g1: out std_logic;
vga_g0: out std_logic;
vga_b1: out std_logic;
vga_b0: out std_logic
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
);
end entity VIDEO_zpuino_wb_vga_hqvga;
architecture behave of VIDEO_zpuino_wb_vga_hqvga is
-- Clock is 50 MHz Hor Vert
-- Disp FP Sync BP Disp FP Sync BP
-- 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
constant VGA_H_SYNC: integer := 120;
constant VGA_H_FRONTPORCH: integer := 56;
constant VGA_H_DISPLAY: integer := 800;
constant VGA_H_BACKPORCH: integer := 64;
constant VGA_V_FRONTPORCH: integer := 37;
constant VGA_V_SYNC: integer := 6;
constant VGA_V_DISPLAY: integer := 600;
constant VGA_V_BACKPORCH: integer := 23;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '0';
constant h_polarity: std_logic := '0';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
component zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0); -- 9 bits
mi_addr: in std_logic_vector(14 downto 0)
);
end component zpuino_vga_ram;
signal rstq1,rstq2: std_logic;
signal vga_ram_address: unsigned(14 downto 0);
signal vga_ram_data: std_logic_vector(7 downto 0);
signal v_display: std_logic;
signal ram_read: std_logic_vector(7 downto 0);
signal ram_we: std_logic;
signal vga_v_offset: unsigned(14 downto 0);
signal hoff: unsigned(2 downto 0); -- will count from 0 to 4
signal voff: unsigned(2 downto 0); -- will count from 0 to 4
signal hdisp: unsigned(13 downto 2);
signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
signal vga_r: std_logic_vector(2 downto 0);
signal vga_g: std_logic_vector(2 downto 0);
signal vga_b: std_logic_vector(1 downto 0);
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
vga_r2 <= vga_r(2);
vga_r1 <= vga_r(1);
vga_r0 <= vga_r(0);
vga_g2 <= vga_g(2);
vga_g1 <= vga_g(1);
vga_g0 <= vga_g(0);
vga_b1 <= vga_b(1);
vga_b0 <= vga_b(0);
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_ended<='0';
else
read_ended<=wb_stb_i and wb_cyc_i and not wb_we_i;
end if;
end if;
end process;
wb_ack_o <= wb_stb_i and wb_cyc_i and (read_ended or wb_we_i);
-- Read muxer
process(wb_adr_i,ram_read)
begin
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= ram_read;
end process;
process(wb_we_i,wb_cyc_i,wb_stb_i,wb_adr_i)
begin
ram_we <= wb_we_i and wb_cyc_i and wb_stb_i;
end process;
-- VGA reset generator.
process(clk_50Mhz, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(clk_50Mhz) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
-- Compute the VGA RAM offset we need to use to fetch the character.
vga_ram_address <= hdisp +
vga_v_offset;
ram:zpuino_vga_ram
port map (
v_clk => clk_50Mhz,
v_en => '1',
v_addr => std_logic_vector(vga_ram_address),
v_data => vga_ram_data,
-- Memory interface
mi_clk => wb_clk_i,
mi_dat_i => wb_dat_i(7 downto 0),
mi_we => ram_we,
mi_en => '1',
mi_dat_o => ram_read,
mi_addr => wb_adr_i(16 downto 2)
);
-- Horizontal counter
hcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
hoff <= (others =>'0');
hdisp <= (others => '0');
else
hcount_q <= hcount_q + 1;
if hoff="100" then
hoff <= (others => '0');
hdisp <= hdisp + 1;
else
hoff <= hoff + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end if;
end process;
hsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_BACKPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_FRONTPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
voff<=(others => '0');
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
voff <= (others => '0');
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
if voff="100" then
voff <= (others => '0');
vga_v_offset <= vga_v_offset + 160;
else
voff <= voff + 1;
end if;
end if;
end if;
end if;
end if;
end process;
vsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_BACKPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_FRONTPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if v_display='0' then
vga_b <= (others =>'0');
vga_r <= (others =>'0');
vga_g <= (others =>'0');
else
vga_r <= vga_ram_data(7 downto 5);
vga_g <= vga_ram_data(4 downto 2);
vga_b <= vga_ram_data(1 downto 0);
end if;
end if;
end process;
end behave;
|
--
-- VGA interface for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity VIDEO_zpuino_wb_vga_hqvga is
generic(
vgaclk_divider: integer := 1
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- VGA interface
clk_50Mhz: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r2: out std_logic;
vga_r1: out std_logic;
vga_r0: out std_logic;
vga_g2: out std_logic;
vga_g1: out std_logic;
vga_g0: out std_logic;
vga_b1: out std_logic;
vga_b0: out std_logic
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
);
end entity VIDEO_zpuino_wb_vga_hqvga;
architecture behave of VIDEO_zpuino_wb_vga_hqvga is
-- Clock is 50 MHz Hor Vert
-- Disp FP Sync BP Disp FP Sync BP
-- 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
constant VGA_H_SYNC: integer := 120;
constant VGA_H_FRONTPORCH: integer := 56;
constant VGA_H_DISPLAY: integer := 800;
constant VGA_H_BACKPORCH: integer := 64;
constant VGA_V_FRONTPORCH: integer := 37;
constant VGA_V_SYNC: integer := 6;
constant VGA_V_DISPLAY: integer := 600;
constant VGA_V_BACKPORCH: integer := 23;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '0';
constant h_polarity: std_logic := '0';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
component zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0); -- 9 bits
mi_addr: in std_logic_vector(14 downto 0)
);
end component zpuino_vga_ram;
signal rstq1,rstq2: std_logic;
signal vga_ram_address: unsigned(14 downto 0);
signal vga_ram_data: std_logic_vector(7 downto 0);
signal v_display: std_logic;
signal ram_read: std_logic_vector(7 downto 0);
signal ram_we: std_logic;
signal vga_v_offset: unsigned(14 downto 0);
signal hoff: unsigned(2 downto 0); -- will count from 0 to 4
signal voff: unsigned(2 downto 0); -- will count from 0 to 4
signal hdisp: unsigned(13 downto 2);
signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
signal vga_r: std_logic_vector(2 downto 0);
signal vga_g: std_logic_vector(2 downto 0);
signal vga_b: std_logic_vector(1 downto 0);
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
vga_r2 <= vga_r(2);
vga_r1 <= vga_r(1);
vga_r0 <= vga_r(0);
vga_g2 <= vga_g(2);
vga_g1 <= vga_g(1);
vga_g0 <= vga_g(0);
vga_b1 <= vga_b(1);
vga_b0 <= vga_b(0);
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_ended<='0';
else
read_ended<=wb_stb_i and wb_cyc_i and not wb_we_i;
end if;
end if;
end process;
wb_ack_o <= wb_stb_i and wb_cyc_i and (read_ended or wb_we_i);
-- Read muxer
process(wb_adr_i,ram_read)
begin
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= ram_read;
end process;
process(wb_we_i,wb_cyc_i,wb_stb_i,wb_adr_i)
begin
ram_we <= wb_we_i and wb_cyc_i and wb_stb_i;
end process;
-- VGA reset generator.
process(clk_50Mhz, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(clk_50Mhz) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
-- Compute the VGA RAM offset we need to use to fetch the character.
vga_ram_address <= hdisp +
vga_v_offset;
ram:zpuino_vga_ram
port map (
v_clk => clk_50Mhz,
v_en => '1',
v_addr => std_logic_vector(vga_ram_address),
v_data => vga_ram_data,
-- Memory interface
mi_clk => wb_clk_i,
mi_dat_i => wb_dat_i(7 downto 0),
mi_we => ram_we,
mi_en => '1',
mi_dat_o => ram_read,
mi_addr => wb_adr_i(16 downto 2)
);
-- Horizontal counter
hcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
hoff <= (others =>'0');
hdisp <= (others => '0');
else
hcount_q <= hcount_q + 1;
if hoff="100" then
hoff <= (others => '0');
hdisp <= hdisp + 1;
else
hoff <= hoff + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end if;
end process;
hsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_BACKPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_FRONTPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
voff<=(others => '0');
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
voff <= (others => '0');
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
if voff="100" then
voff <= (others => '0');
vga_v_offset <= vga_v_offset + 160;
else
voff <= voff + 1;
end if;
end if;
end if;
end if;
end if;
end process;
vsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_BACKPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_FRONTPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if v_display='0' then
vga_b <= (others =>'0');
vga_r <= (others =>'0');
vga_g <= (others =>'0');
else
vga_r <= vga_ram_data(7 downto 5);
vga_g <= vga_ram_data(4 downto 2);
vga_b <= vga_ram_data(1 downto 0);
end if;
end if;
end process;
end behave;
|
--
-- VGA interface for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity VIDEO_zpuino_wb_vga_hqvga is
generic(
vgaclk_divider: integer := 1
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- VGA interface
clk_50Mhz: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r2: out std_logic;
vga_r1: out std_logic;
vga_r0: out std_logic;
vga_g2: out std_logic;
vga_g1: out std_logic;
vga_g0: out std_logic;
vga_b1: out std_logic;
vga_b0: out std_logic
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
);
end entity VIDEO_zpuino_wb_vga_hqvga;
architecture behave of VIDEO_zpuino_wb_vga_hqvga is
-- Clock is 50 MHz Hor Vert
-- Disp FP Sync BP Disp FP Sync BP
-- 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
constant VGA_H_SYNC: integer := 120;
constant VGA_H_FRONTPORCH: integer := 56;
constant VGA_H_DISPLAY: integer := 800;
constant VGA_H_BACKPORCH: integer := 64;
constant VGA_V_FRONTPORCH: integer := 37;
constant VGA_V_SYNC: integer := 6;
constant VGA_V_DISPLAY: integer := 600;
constant VGA_V_BACKPORCH: integer := 23;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '0';
constant h_polarity: std_logic := '0';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
component zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0); -- 9 bits
mi_addr: in std_logic_vector(14 downto 0)
);
end component zpuino_vga_ram;
signal rstq1,rstq2: std_logic;
signal vga_ram_address: unsigned(14 downto 0);
signal vga_ram_data: std_logic_vector(7 downto 0);
signal v_display: std_logic;
signal ram_read: std_logic_vector(7 downto 0);
signal ram_we: std_logic;
signal vga_v_offset: unsigned(14 downto 0);
signal hoff: unsigned(2 downto 0); -- will count from 0 to 4
signal voff: unsigned(2 downto 0); -- will count from 0 to 4
signal hdisp: unsigned(13 downto 2);
signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
signal vga_r: std_logic_vector(2 downto 0);
signal vga_g: std_logic_vector(2 downto 0);
signal vga_b: std_logic_vector(1 downto 0);
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
vga_r2 <= vga_r(2);
vga_r1 <= vga_r(1);
vga_r0 <= vga_r(0);
vga_g2 <= vga_g(2);
vga_g1 <= vga_g(1);
vga_g0 <= vga_g(0);
vga_b1 <= vga_b(1);
vga_b0 <= vga_b(0);
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_ended<='0';
else
read_ended<=wb_stb_i and wb_cyc_i and not wb_we_i;
end if;
end if;
end process;
wb_ack_o <= wb_stb_i and wb_cyc_i and (read_ended or wb_we_i);
-- Read muxer
process(wb_adr_i,ram_read)
begin
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= ram_read;
end process;
process(wb_we_i,wb_cyc_i,wb_stb_i,wb_adr_i)
begin
ram_we <= wb_we_i and wb_cyc_i and wb_stb_i;
end process;
-- VGA reset generator.
process(clk_50Mhz, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(clk_50Mhz) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
-- Compute the VGA RAM offset we need to use to fetch the character.
vga_ram_address <= hdisp +
vga_v_offset;
ram:zpuino_vga_ram
port map (
v_clk => clk_50Mhz,
v_en => '1',
v_addr => std_logic_vector(vga_ram_address),
v_data => vga_ram_data,
-- Memory interface
mi_clk => wb_clk_i,
mi_dat_i => wb_dat_i(7 downto 0),
mi_we => ram_we,
mi_en => '1',
mi_dat_o => ram_read,
mi_addr => wb_adr_i(16 downto 2)
);
-- Horizontal counter
hcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
hoff <= (others =>'0');
hdisp <= (others => '0');
else
hcount_q <= hcount_q + 1;
if hoff="100" then
hoff <= (others => '0');
hdisp <= hdisp + 1;
else
hoff <= hoff + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end if;
end process;
hsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_BACKPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_FRONTPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
voff<=(others => '0');
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
voff <= (others => '0');
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
if voff="100" then
voff <= (others => '0');
vga_v_offset <= vga_v_offset + 160;
else
voff <= voff + 1;
end if;
end if;
end if;
end if;
end if;
end process;
vsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_BACKPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_FRONTPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if v_display='0' then
vga_b <= (others =>'0');
vga_r <= (others =>'0');
vga_g <= (others =>'0');
else
vga_r <= vga_ram_data(7 downto 5);
vga_g <= vga_ram_data(4 downto 2);
vga_b <= vga_ram_data(1 downto 0);
end if;
end if;
end process;
end behave;
|
--
-- VGA interface for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity VIDEO_zpuino_wb_vga_hqvga is
generic(
vgaclk_divider: integer := 1
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- VGA interface
clk_50Mhz: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r2: out std_logic;
vga_r1: out std_logic;
vga_r0: out std_logic;
vga_g2: out std_logic;
vga_g1: out std_logic;
vga_g0: out std_logic;
vga_b1: out std_logic;
vga_b0: out std_logic
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
);
end entity VIDEO_zpuino_wb_vga_hqvga;
architecture behave of VIDEO_zpuino_wb_vga_hqvga is
-- Clock is 50 MHz Hor Vert
-- Disp FP Sync BP Disp FP Sync BP
-- 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
constant VGA_H_SYNC: integer := 120;
constant VGA_H_FRONTPORCH: integer := 56;
constant VGA_H_DISPLAY: integer := 800;
constant VGA_H_BACKPORCH: integer := 64;
constant VGA_V_FRONTPORCH: integer := 37;
constant VGA_V_SYNC: integer := 6;
constant VGA_V_DISPLAY: integer := 600;
constant VGA_V_BACKPORCH: integer := 23;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '0';
constant h_polarity: std_logic := '0';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
component zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0); -- 9 bits
mi_addr: in std_logic_vector(14 downto 0)
);
end component zpuino_vga_ram;
signal rstq1,rstq2: std_logic;
signal vga_ram_address: unsigned(14 downto 0);
signal vga_ram_data: std_logic_vector(7 downto 0);
signal v_display: std_logic;
signal ram_read: std_logic_vector(7 downto 0);
signal ram_we: std_logic;
signal vga_v_offset: unsigned(14 downto 0);
signal hoff: unsigned(2 downto 0); -- will count from 0 to 4
signal voff: unsigned(2 downto 0); -- will count from 0 to 4
signal hdisp: unsigned(13 downto 2);
signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
signal vga_r: std_logic_vector(2 downto 0);
signal vga_g: std_logic_vector(2 downto 0);
signal vga_b: std_logic_vector(1 downto 0);
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
vga_r2 <= vga_r(2);
vga_r1 <= vga_r(1);
vga_r0 <= vga_r(0);
vga_g2 <= vga_g(2);
vga_g1 <= vga_g(1);
vga_g0 <= vga_g(0);
vga_b1 <= vga_b(1);
vga_b0 <= vga_b(0);
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_ended<='0';
else
read_ended<=wb_stb_i and wb_cyc_i and not wb_we_i;
end if;
end if;
end process;
wb_ack_o <= wb_stb_i and wb_cyc_i and (read_ended or wb_we_i);
-- Read muxer
process(wb_adr_i,ram_read)
begin
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= ram_read;
end process;
process(wb_we_i,wb_cyc_i,wb_stb_i,wb_adr_i)
begin
ram_we <= wb_we_i and wb_cyc_i and wb_stb_i;
end process;
-- VGA reset generator.
process(clk_50Mhz, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(clk_50Mhz) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
-- Compute the VGA RAM offset we need to use to fetch the character.
vga_ram_address <= hdisp +
vga_v_offset;
ram:zpuino_vga_ram
port map (
v_clk => clk_50Mhz,
v_en => '1',
v_addr => std_logic_vector(vga_ram_address),
v_data => vga_ram_data,
-- Memory interface
mi_clk => wb_clk_i,
mi_dat_i => wb_dat_i(7 downto 0),
mi_we => ram_we,
mi_en => '1',
mi_dat_o => ram_read,
mi_addr => wb_adr_i(16 downto 2)
);
-- Horizontal counter
hcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
hoff <= (others =>'0');
hdisp <= (others => '0');
else
hcount_q <= hcount_q + 1;
if hoff="100" then
hoff <= (others => '0');
hdisp <= hdisp + 1;
else
hoff <= hoff + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end if;
end process;
hsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_BACKPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_FRONTPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
voff<=(others => '0');
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
voff <= (others => '0');
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
if voff="100" then
voff <= (others => '0');
vga_v_offset <= vga_v_offset + 160;
else
voff <= voff + 1;
end if;
end if;
end if;
end if;
end if;
end process;
vsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_BACKPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_FRONTPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if v_display='0' then
vga_b <= (others =>'0');
vga_r <= (others =>'0');
vga_g <= (others =>'0');
else
vga_r <= vga_ram_data(7 downto 5);
vga_g <= vga_ram_data(4 downto 2);
vga_b <= vga_ram_data(1 downto 0);
end if;
end if;
end process;
end behave;
|
--
-- VGA interface for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity VIDEO_zpuino_wb_vga_hqvga is
generic(
vgaclk_divider: integer := 1
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- VGA interface
clk_50Mhz: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r2: out std_logic;
vga_r1: out std_logic;
vga_r0: out std_logic;
vga_g2: out std_logic;
vga_g1: out std_logic;
vga_g0: out std_logic;
vga_b1: out std_logic;
vga_b0: out std_logic
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
);
end entity VIDEO_zpuino_wb_vga_hqvga;
architecture behave of VIDEO_zpuino_wb_vga_hqvga is
-- Clock is 50 MHz Hor Vert
-- Disp FP Sync BP Disp FP Sync BP
-- 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
constant VGA_H_SYNC: integer := 120;
constant VGA_H_FRONTPORCH: integer := 56;
constant VGA_H_DISPLAY: integer := 800;
constant VGA_H_BACKPORCH: integer := 64;
constant VGA_V_FRONTPORCH: integer := 37;
constant VGA_V_SYNC: integer := 6;
constant VGA_V_DISPLAY: integer := 600;
constant VGA_V_BACKPORCH: integer := 23;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '0';
constant h_polarity: std_logic := '0';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
component zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0); -- 9 bits
mi_addr: in std_logic_vector(14 downto 0)
);
end component zpuino_vga_ram;
signal rstq1,rstq2: std_logic;
signal vga_ram_address: unsigned(14 downto 0);
signal vga_ram_data: std_logic_vector(7 downto 0);
signal v_display: std_logic;
signal ram_read: std_logic_vector(7 downto 0);
signal ram_we: std_logic;
signal vga_v_offset: unsigned(14 downto 0);
signal hoff: unsigned(2 downto 0); -- will count from 0 to 4
signal voff: unsigned(2 downto 0); -- will count from 0 to 4
signal hdisp: unsigned(13 downto 2);
signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
signal vga_r: std_logic_vector(2 downto 0);
signal vga_g: std_logic_vector(2 downto 0);
signal vga_b: std_logic_vector(1 downto 0);
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
vga_r2 <= vga_r(2);
vga_r1 <= vga_r(1);
vga_r0 <= vga_r(0);
vga_g2 <= vga_g(2);
vga_g1 <= vga_g(1);
vga_g0 <= vga_g(0);
vga_b1 <= vga_b(1);
vga_b0 <= vga_b(0);
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_ended<='0';
else
read_ended<=wb_stb_i and wb_cyc_i and not wb_we_i;
end if;
end if;
end process;
wb_ack_o <= wb_stb_i and wb_cyc_i and (read_ended or wb_we_i);
-- Read muxer
process(wb_adr_i,ram_read)
begin
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= ram_read;
end process;
process(wb_we_i,wb_cyc_i,wb_stb_i,wb_adr_i)
begin
ram_we <= wb_we_i and wb_cyc_i and wb_stb_i;
end process;
-- VGA reset generator.
process(clk_50Mhz, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(clk_50Mhz) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
-- Compute the VGA RAM offset we need to use to fetch the character.
vga_ram_address <= hdisp +
vga_v_offset;
ram:zpuino_vga_ram
port map (
v_clk => clk_50Mhz,
v_en => '1',
v_addr => std_logic_vector(vga_ram_address),
v_data => vga_ram_data,
-- Memory interface
mi_clk => wb_clk_i,
mi_dat_i => wb_dat_i(7 downto 0),
mi_we => ram_we,
mi_en => '1',
mi_dat_o => ram_read,
mi_addr => wb_adr_i(16 downto 2)
);
-- Horizontal counter
hcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
hoff <= (others =>'0');
hdisp <= (others => '0');
else
hcount_q <= hcount_q + 1;
if hoff="100" then
hoff <= (others => '0');
hdisp <= hdisp + 1;
else
hoff <= hoff + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end if;
end process;
hsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_BACKPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_FRONTPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
voff<=(others => '0');
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
voff <= (others => '0');
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
if voff="100" then
voff <= (others => '0');
vga_v_offset <= vga_v_offset + 160;
else
voff <= voff + 1;
end if;
end if;
end if;
end if;
end if;
end process;
vsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_BACKPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_FRONTPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if v_display='0' then
vga_b <= (others =>'0');
vga_r <= (others =>'0');
vga_g <= (others =>'0');
else
vga_r <= vga_ram_data(7 downto 5);
vga_g <= vga_ram_data(4 downto 2);
vga_b <= vga_ram_data(1 downto 0);
end if;
end if;
end process;
end behave;
|
--
-- VGA interface for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity VIDEO_zpuino_wb_vga_hqvga is
generic(
vgaclk_divider: integer := 1
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- VGA interface
clk_50Mhz: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r2: out std_logic;
vga_r1: out std_logic;
vga_r0: out std_logic;
vga_g2: out std_logic;
vga_g1: out std_logic;
vga_g0: out std_logic;
vga_b1: out std_logic;
vga_b0: out std_logic
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
);
end entity VIDEO_zpuino_wb_vga_hqvga;
architecture behave of VIDEO_zpuino_wb_vga_hqvga is
-- Clock is 50 MHz Hor Vert
-- Disp FP Sync BP Disp FP Sync BP
-- 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
constant VGA_H_SYNC: integer := 120;
constant VGA_H_FRONTPORCH: integer := 56;
constant VGA_H_DISPLAY: integer := 800;
constant VGA_H_BACKPORCH: integer := 64;
constant VGA_V_FRONTPORCH: integer := 37;
constant VGA_V_SYNC: integer := 6;
constant VGA_V_DISPLAY: integer := 600;
constant VGA_V_BACKPORCH: integer := 23;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '0';
constant h_polarity: std_logic := '0';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
component zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0); -- 9 bits
mi_addr: in std_logic_vector(14 downto 0)
);
end component zpuino_vga_ram;
signal rstq1,rstq2: std_logic;
signal vga_ram_address: unsigned(14 downto 0);
signal vga_ram_data: std_logic_vector(7 downto 0);
signal v_display: std_logic;
signal ram_read: std_logic_vector(7 downto 0);
signal ram_we: std_logic;
signal vga_v_offset: unsigned(14 downto 0);
signal hoff: unsigned(2 downto 0); -- will count from 0 to 4
signal voff: unsigned(2 downto 0); -- will count from 0 to 4
signal hdisp: unsigned(13 downto 2);
signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
signal vga_r: std_logic_vector(2 downto 0);
signal vga_g: std_logic_vector(2 downto 0);
signal vga_b: std_logic_vector(1 downto 0);
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
vga_r2 <= vga_r(2);
vga_r1 <= vga_r(1);
vga_r0 <= vga_r(0);
vga_g2 <= vga_g(2);
vga_g1 <= vga_g(1);
vga_g0 <= vga_g(0);
vga_b1 <= vga_b(1);
vga_b0 <= vga_b(0);
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_ended<='0';
else
read_ended<=wb_stb_i and wb_cyc_i and not wb_we_i;
end if;
end if;
end process;
wb_ack_o <= wb_stb_i and wb_cyc_i and (read_ended or wb_we_i);
-- Read muxer
process(wb_adr_i,ram_read)
begin
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= ram_read;
end process;
process(wb_we_i,wb_cyc_i,wb_stb_i,wb_adr_i)
begin
ram_we <= wb_we_i and wb_cyc_i and wb_stb_i;
end process;
-- VGA reset generator.
process(clk_50Mhz, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(clk_50Mhz) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
-- Compute the VGA RAM offset we need to use to fetch the character.
vga_ram_address <= hdisp +
vga_v_offset;
ram:zpuino_vga_ram
port map (
v_clk => clk_50Mhz,
v_en => '1',
v_addr => std_logic_vector(vga_ram_address),
v_data => vga_ram_data,
-- Memory interface
mi_clk => wb_clk_i,
mi_dat_i => wb_dat_i(7 downto 0),
mi_we => ram_we,
mi_en => '1',
mi_dat_o => ram_read,
mi_addr => wb_adr_i(16 downto 2)
);
-- Horizontal counter
hcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
hoff <= (others =>'0');
hdisp <= (others => '0');
else
hcount_q <= hcount_q + 1;
if hoff="100" then
hoff <= (others => '0');
hdisp <= hdisp + 1;
else
hoff <= hoff + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end if;
end process;
hsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_BACKPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_FRONTPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
voff<=(others => '0');
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
voff <= (others => '0');
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
if voff="100" then
voff <= (others => '0');
vga_v_offset <= vga_v_offset + 160;
else
voff <= voff + 1;
end if;
end if;
end if;
end if;
end if;
end process;
vsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_BACKPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_FRONTPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if v_display='0' then
vga_b <= (others =>'0');
vga_r <= (others =>'0');
vga_g <= (others =>'0');
else
vga_r <= vga_ram_data(7 downto 5);
vga_g <= vga_ram_data(4 downto 2);
vga_b <= vga_ram_data(1 downto 0);
end if;
end if;
end process;
end behave;
|
--
-- VGA interface for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity VIDEO_zpuino_wb_vga_hqvga is
generic(
vgaclk_divider: integer := 1
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- VGA interface
clk_50Mhz: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r2: out std_logic;
vga_r1: out std_logic;
vga_r0: out std_logic;
vga_g2: out std_logic;
vga_g1: out std_logic;
vga_g0: out std_logic;
vga_b1: out std_logic;
vga_b0: out std_logic
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
);
end entity VIDEO_zpuino_wb_vga_hqvga;
architecture behave of VIDEO_zpuino_wb_vga_hqvga is
-- Clock is 50 MHz Hor Vert
-- Disp FP Sync BP Disp FP Sync BP
-- 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
constant VGA_H_SYNC: integer := 120;
constant VGA_H_FRONTPORCH: integer := 56;
constant VGA_H_DISPLAY: integer := 800;
constant VGA_H_BACKPORCH: integer := 64;
constant VGA_V_FRONTPORCH: integer := 37;
constant VGA_V_SYNC: integer := 6;
constant VGA_V_DISPLAY: integer := 600;
constant VGA_V_BACKPORCH: integer := 23;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '0';
constant h_polarity: std_logic := '0';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
component zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0); -- 9 bits
mi_addr: in std_logic_vector(14 downto 0)
);
end component zpuino_vga_ram;
signal rstq1,rstq2: std_logic;
signal vga_ram_address: unsigned(14 downto 0);
signal vga_ram_data: std_logic_vector(7 downto 0);
signal v_display: std_logic;
signal ram_read: std_logic_vector(7 downto 0);
signal ram_we: std_logic;
signal vga_v_offset: unsigned(14 downto 0);
signal hoff: unsigned(2 downto 0); -- will count from 0 to 4
signal voff: unsigned(2 downto 0); -- will count from 0 to 4
signal hdisp: unsigned(13 downto 2);
signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
signal vga_r: std_logic_vector(2 downto 0);
signal vga_g: std_logic_vector(2 downto 0);
signal vga_b: std_logic_vector(1 downto 0);
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
vga_r2 <= vga_r(2);
vga_r1 <= vga_r(1);
vga_r0 <= vga_r(0);
vga_g2 <= vga_g(2);
vga_g1 <= vga_g(1);
vga_g0 <= vga_g(0);
vga_b1 <= vga_b(1);
vga_b0 <= vga_b(0);
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_ended<='0';
else
read_ended<=wb_stb_i and wb_cyc_i and not wb_we_i;
end if;
end if;
end process;
wb_ack_o <= wb_stb_i and wb_cyc_i and (read_ended or wb_we_i);
-- Read muxer
process(wb_adr_i,ram_read)
begin
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= ram_read;
end process;
process(wb_we_i,wb_cyc_i,wb_stb_i,wb_adr_i)
begin
ram_we <= wb_we_i and wb_cyc_i and wb_stb_i;
end process;
-- VGA reset generator.
process(clk_50Mhz, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(clk_50Mhz) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
-- Compute the VGA RAM offset we need to use to fetch the character.
vga_ram_address <= hdisp +
vga_v_offset;
ram:zpuino_vga_ram
port map (
v_clk => clk_50Mhz,
v_en => '1',
v_addr => std_logic_vector(vga_ram_address),
v_data => vga_ram_data,
-- Memory interface
mi_clk => wb_clk_i,
mi_dat_i => wb_dat_i(7 downto 0),
mi_we => ram_we,
mi_en => '1',
mi_dat_o => ram_read,
mi_addr => wb_adr_i(16 downto 2)
);
-- Horizontal counter
hcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
hoff <= (others =>'0');
hdisp <= (others => '0');
else
hcount_q <= hcount_q + 1;
if hoff="100" then
hoff <= (others => '0');
hdisp <= hdisp + 1;
else
hoff <= hoff + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end if;
end process;
hsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_BACKPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_FRONTPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
voff<=(others => '0');
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
voff <= (others => '0');
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
if voff="100" then
voff <= (others => '0');
vga_v_offset <= vga_v_offset + 160;
else
voff <= voff + 1;
end if;
end if;
end if;
end if;
end if;
end process;
vsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_BACKPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_FRONTPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if v_display='0' then
vga_b <= (others =>'0');
vga_r <= (others =>'0');
vga_g <= (others =>'0');
else
vga_r <= vga_ram_data(7 downto 5);
vga_g <= vga_ram_data(4 downto 2);
vga_b <= vga_ram_data(1 downto 0);
end if;
end if;
end process;
end behave;
|
--
-- VGA interface for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity VIDEO_zpuino_wb_vga_hqvga is
generic(
vgaclk_divider: integer := 1
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- VGA interface
clk_50Mhz: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r2: out std_logic;
vga_r1: out std_logic;
vga_r0: out std_logic;
vga_g2: out std_logic;
vga_g1: out std_logic;
vga_g0: out std_logic;
vga_b1: out std_logic;
vga_b0: out std_logic
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
);
end entity VIDEO_zpuino_wb_vga_hqvga;
architecture behave of VIDEO_zpuino_wb_vga_hqvga is
-- Clock is 50 MHz Hor Vert
-- Disp FP Sync BP Disp FP Sync BP
-- 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
constant VGA_H_SYNC: integer := 120;
constant VGA_H_FRONTPORCH: integer := 56;
constant VGA_H_DISPLAY: integer := 800;
constant VGA_H_BACKPORCH: integer := 64;
constant VGA_V_FRONTPORCH: integer := 37;
constant VGA_V_SYNC: integer := 6;
constant VGA_V_DISPLAY: integer := 600;
constant VGA_V_BACKPORCH: integer := 23;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '0';
constant h_polarity: std_logic := '0';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
component zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0); -- 9 bits
mi_addr: in std_logic_vector(14 downto 0)
);
end component zpuino_vga_ram;
signal rstq1,rstq2: std_logic;
signal vga_ram_address: unsigned(14 downto 0);
signal vga_ram_data: std_logic_vector(7 downto 0);
signal v_display: std_logic;
signal ram_read: std_logic_vector(7 downto 0);
signal ram_we: std_logic;
signal vga_v_offset: unsigned(14 downto 0);
signal hoff: unsigned(2 downto 0); -- will count from 0 to 4
signal voff: unsigned(2 downto 0); -- will count from 0 to 4
signal hdisp: unsigned(13 downto 2);
signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
signal vga_r: std_logic_vector(2 downto 0);
signal vga_g: std_logic_vector(2 downto 0);
signal vga_b: std_logic_vector(1 downto 0);
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
vga_r2 <= vga_r(2);
vga_r1 <= vga_r(1);
vga_r0 <= vga_r(0);
vga_g2 <= vga_g(2);
vga_g1 <= vga_g(1);
vga_g0 <= vga_g(0);
vga_b1 <= vga_b(1);
vga_b0 <= vga_b(0);
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_ended<='0';
else
read_ended<=wb_stb_i and wb_cyc_i and not wb_we_i;
end if;
end if;
end process;
wb_ack_o <= wb_stb_i and wb_cyc_i and (read_ended or wb_we_i);
-- Read muxer
process(wb_adr_i,ram_read)
begin
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= ram_read;
end process;
process(wb_we_i,wb_cyc_i,wb_stb_i,wb_adr_i)
begin
ram_we <= wb_we_i and wb_cyc_i and wb_stb_i;
end process;
-- VGA reset generator.
process(clk_50Mhz, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(clk_50Mhz) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
-- Compute the VGA RAM offset we need to use to fetch the character.
vga_ram_address <= hdisp +
vga_v_offset;
ram:zpuino_vga_ram
port map (
v_clk => clk_50Mhz,
v_en => '1',
v_addr => std_logic_vector(vga_ram_address),
v_data => vga_ram_data,
-- Memory interface
mi_clk => wb_clk_i,
mi_dat_i => wb_dat_i(7 downto 0),
mi_we => ram_we,
mi_en => '1',
mi_dat_o => ram_read,
mi_addr => wb_adr_i(16 downto 2)
);
-- Horizontal counter
hcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
hoff <= (others =>'0');
hdisp <= (others => '0');
else
hcount_q <= hcount_q + 1;
if hoff="100" then
hoff <= (others => '0');
hdisp <= hdisp + 1;
else
hoff <= hoff + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end if;
end process;
hsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_BACKPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_FRONTPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
voff<=(others => '0');
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
voff <= (others => '0');
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
if voff="100" then
voff <= (others => '0');
vga_v_offset <= vga_v_offset + 160;
else
voff <= voff + 1;
end if;
end if;
end if;
end if;
end if;
end process;
vsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_BACKPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_FRONTPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if v_display='0' then
vga_b <= (others =>'0');
vga_r <= (others =>'0');
vga_g <= (others =>'0');
else
vga_r <= vga_ram_data(7 downto 5);
vga_g <= vga_ram_data(4 downto 2);
vga_b <= vga_ram_data(1 downto 0);
end if;
end if;
end process;
end behave;
|
--
-- VGA interface for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity VIDEO_zpuino_wb_vga_hqvga is
generic(
vgaclk_divider: integer := 1
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- VGA interface
clk_50Mhz: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r2: out std_logic;
vga_r1: out std_logic;
vga_r0: out std_logic;
vga_g2: out std_logic;
vga_g1: out std_logic;
vga_g0: out std_logic;
vga_b1: out std_logic;
vga_b0: out std_logic
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
);
end entity VIDEO_zpuino_wb_vga_hqvga;
architecture behave of VIDEO_zpuino_wb_vga_hqvga is
-- Clock is 50 MHz Hor Vert
-- Disp FP Sync BP Disp FP Sync BP
-- 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
constant VGA_H_SYNC: integer := 120;
constant VGA_H_FRONTPORCH: integer := 56;
constant VGA_H_DISPLAY: integer := 800;
constant VGA_H_BACKPORCH: integer := 64;
constant VGA_V_FRONTPORCH: integer := 37;
constant VGA_V_SYNC: integer := 6;
constant VGA_V_DISPLAY: integer := 600;
constant VGA_V_BACKPORCH: integer := 23;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '0';
constant h_polarity: std_logic := '0';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
component zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0); -- 9 bits
mi_addr: in std_logic_vector(14 downto 0)
);
end component zpuino_vga_ram;
signal rstq1,rstq2: std_logic;
signal vga_ram_address: unsigned(14 downto 0);
signal vga_ram_data: std_logic_vector(7 downto 0);
signal v_display: std_logic;
signal ram_read: std_logic_vector(7 downto 0);
signal ram_we: std_logic;
signal vga_v_offset: unsigned(14 downto 0);
signal hoff: unsigned(2 downto 0); -- will count from 0 to 4
signal voff: unsigned(2 downto 0); -- will count from 0 to 4
signal hdisp: unsigned(13 downto 2);
signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
signal vga_r: std_logic_vector(2 downto 0);
signal vga_g: std_logic_vector(2 downto 0);
signal vga_b: std_logic_vector(1 downto 0);
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
vga_r2 <= vga_r(2);
vga_r1 <= vga_r(1);
vga_r0 <= vga_r(0);
vga_g2 <= vga_g(2);
vga_g1 <= vga_g(1);
vga_g0 <= vga_g(0);
vga_b1 <= vga_b(1);
vga_b0 <= vga_b(0);
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_ended<='0';
else
read_ended<=wb_stb_i and wb_cyc_i and not wb_we_i;
end if;
end if;
end process;
wb_ack_o <= wb_stb_i and wb_cyc_i and (read_ended or wb_we_i);
-- Read muxer
process(wb_adr_i,ram_read)
begin
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= ram_read;
end process;
process(wb_we_i,wb_cyc_i,wb_stb_i,wb_adr_i)
begin
ram_we <= wb_we_i and wb_cyc_i and wb_stb_i;
end process;
-- VGA reset generator.
process(clk_50Mhz, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(clk_50Mhz) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
-- Compute the VGA RAM offset we need to use to fetch the character.
vga_ram_address <= hdisp +
vga_v_offset;
ram:zpuino_vga_ram
port map (
v_clk => clk_50Mhz,
v_en => '1',
v_addr => std_logic_vector(vga_ram_address),
v_data => vga_ram_data,
-- Memory interface
mi_clk => wb_clk_i,
mi_dat_i => wb_dat_i(7 downto 0),
mi_we => ram_we,
mi_en => '1',
mi_dat_o => ram_read,
mi_addr => wb_adr_i(16 downto 2)
);
-- Horizontal counter
hcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
hoff <= (others =>'0');
hdisp <= (others => '0');
else
hcount_q <= hcount_q + 1;
if hoff="100" then
hoff <= (others => '0');
hdisp <= hdisp + 1;
else
hoff <= hoff + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end if;
end process;
hsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_BACKPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_FRONTPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
voff<=(others => '0');
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
voff <= (others => '0');
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
if voff="100" then
voff <= (others => '0');
vga_v_offset <= vga_v_offset + 160;
else
voff <= voff + 1;
end if;
end if;
end if;
end if;
end if;
end process;
vsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_BACKPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_FRONTPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if v_display='0' then
vga_b <= (others =>'0');
vga_r <= (others =>'0');
vga_g <= (others =>'0');
else
vga_r <= vga_ram_data(7 downto 5);
vga_g <= vga_ram_data(4 downto 2);
vga_b <= vga_ram_data(1 downto 0);
end if;
end if;
end process;
end behave;
|
--
-- VGA interface for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity VIDEO_zpuino_wb_vga_hqvga is
generic(
vgaclk_divider: integer := 1
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- VGA interface
clk_50Mhz: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r2: out std_logic;
vga_r1: out std_logic;
vga_r0: out std_logic;
vga_g2: out std_logic;
vga_g1: out std_logic;
vga_g0: out std_logic;
vga_b1: out std_logic;
vga_b0: out std_logic
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
);
end entity VIDEO_zpuino_wb_vga_hqvga;
architecture behave of VIDEO_zpuino_wb_vga_hqvga is
-- Clock is 50 MHz Hor Vert
-- Disp FP Sync BP Disp FP Sync BP
-- 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
constant VGA_H_SYNC: integer := 120;
constant VGA_H_FRONTPORCH: integer := 56;
constant VGA_H_DISPLAY: integer := 800;
constant VGA_H_BACKPORCH: integer := 64;
constant VGA_V_FRONTPORCH: integer := 37;
constant VGA_V_SYNC: integer := 6;
constant VGA_V_DISPLAY: integer := 600;
constant VGA_V_BACKPORCH: integer := 23;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '0';
constant h_polarity: std_logic := '0';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
component zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0); -- 9 bits
mi_addr: in std_logic_vector(14 downto 0)
);
end component zpuino_vga_ram;
signal rstq1,rstq2: std_logic;
signal vga_ram_address: unsigned(14 downto 0);
signal vga_ram_data: std_logic_vector(7 downto 0);
signal v_display: std_logic;
signal ram_read: std_logic_vector(7 downto 0);
signal ram_we: std_logic;
signal vga_v_offset: unsigned(14 downto 0);
signal hoff: unsigned(2 downto 0); -- will count from 0 to 4
signal voff: unsigned(2 downto 0); -- will count from 0 to 4
signal hdisp: unsigned(13 downto 2);
signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
signal vga_r: std_logic_vector(2 downto 0);
signal vga_g: std_logic_vector(2 downto 0);
signal vga_b: std_logic_vector(1 downto 0);
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
vga_r2 <= vga_r(2);
vga_r1 <= vga_r(1);
vga_r0 <= vga_r(0);
vga_g2 <= vga_g(2);
vga_g1 <= vga_g(1);
vga_g0 <= vga_g(0);
vga_b1 <= vga_b(1);
vga_b0 <= vga_b(0);
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_ended<='0';
else
read_ended<=wb_stb_i and wb_cyc_i and not wb_we_i;
end if;
end if;
end process;
wb_ack_o <= wb_stb_i and wb_cyc_i and (read_ended or wb_we_i);
-- Read muxer
process(wb_adr_i,ram_read)
begin
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= ram_read;
end process;
process(wb_we_i,wb_cyc_i,wb_stb_i,wb_adr_i)
begin
ram_we <= wb_we_i and wb_cyc_i and wb_stb_i;
end process;
-- VGA reset generator.
process(clk_50Mhz, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(clk_50Mhz) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
-- Compute the VGA RAM offset we need to use to fetch the character.
vga_ram_address <= hdisp +
vga_v_offset;
ram:zpuino_vga_ram
port map (
v_clk => clk_50Mhz,
v_en => '1',
v_addr => std_logic_vector(vga_ram_address),
v_data => vga_ram_data,
-- Memory interface
mi_clk => wb_clk_i,
mi_dat_i => wb_dat_i(7 downto 0),
mi_we => ram_we,
mi_en => '1',
mi_dat_o => ram_read,
mi_addr => wb_adr_i(16 downto 2)
);
-- Horizontal counter
hcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
hoff <= (others =>'0');
hdisp <= (others => '0');
else
hcount_q <= hcount_q + 1;
if hoff="100" then
hoff <= (others => '0');
hdisp <= hdisp + 1;
else
hoff <= hoff + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end if;
end process;
hsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_BACKPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_FRONTPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
voff<=(others => '0');
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
voff <= (others => '0');
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
if voff="100" then
voff <= (others => '0');
vga_v_offset <= vga_v_offset + 160;
else
voff <= voff + 1;
end if;
end if;
end if;
end if;
end if;
end process;
vsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_BACKPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_FRONTPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if v_display='0' then
vga_b <= (others =>'0');
vga_r <= (others =>'0');
vga_g <= (others =>'0');
else
vga_r <= vga_ram_data(7 downto 5);
vga_g <= vga_ram_data(4 downto 2);
vga_b <= vga_ram_data(1 downto 0);
end if;
end if;
end process;
end behave;
|
--
-- VGA interface for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity VIDEO_zpuino_wb_vga_hqvga is
generic(
vgaclk_divider: integer := 1
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- VGA interface
clk_50Mhz: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r2: out std_logic;
vga_r1: out std_logic;
vga_r0: out std_logic;
vga_g2: out std_logic;
vga_g1: out std_logic;
vga_g0: out std_logic;
vga_b1: out std_logic;
vga_b0: out std_logic
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
);
end entity VIDEO_zpuino_wb_vga_hqvga;
architecture behave of VIDEO_zpuino_wb_vga_hqvga is
-- Clock is 50 MHz Hor Vert
-- Disp FP Sync BP Disp FP Sync BP
-- 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
constant VGA_H_SYNC: integer := 120;
constant VGA_H_FRONTPORCH: integer := 56;
constant VGA_H_DISPLAY: integer := 800;
constant VGA_H_BACKPORCH: integer := 64;
constant VGA_V_FRONTPORCH: integer := 37;
constant VGA_V_SYNC: integer := 6;
constant VGA_V_DISPLAY: integer := 600;
constant VGA_V_BACKPORCH: integer := 23;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '0';
constant h_polarity: std_logic := '0';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
component zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0); -- 9 bits
mi_addr: in std_logic_vector(14 downto 0)
);
end component zpuino_vga_ram;
signal rstq1,rstq2: std_logic;
signal vga_ram_address: unsigned(14 downto 0);
signal vga_ram_data: std_logic_vector(7 downto 0);
signal v_display: std_logic;
signal ram_read: std_logic_vector(7 downto 0);
signal ram_we: std_logic;
signal vga_v_offset: unsigned(14 downto 0);
signal hoff: unsigned(2 downto 0); -- will count from 0 to 4
signal voff: unsigned(2 downto 0); -- will count from 0 to 4
signal hdisp: unsigned(13 downto 2);
signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
signal vga_r: std_logic_vector(2 downto 0);
signal vga_g: std_logic_vector(2 downto 0);
signal vga_b: std_logic_vector(1 downto 0);
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
vga_r2 <= vga_r(2);
vga_r1 <= vga_r(1);
vga_r0 <= vga_r(0);
vga_g2 <= vga_g(2);
vga_g1 <= vga_g(1);
vga_g0 <= vga_g(0);
vga_b1 <= vga_b(1);
vga_b0 <= vga_b(0);
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_ended<='0';
else
read_ended<=wb_stb_i and wb_cyc_i and not wb_we_i;
end if;
end if;
end process;
wb_ack_o <= wb_stb_i and wb_cyc_i and (read_ended or wb_we_i);
-- Read muxer
process(wb_adr_i,ram_read)
begin
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= ram_read;
end process;
process(wb_we_i,wb_cyc_i,wb_stb_i,wb_adr_i)
begin
ram_we <= wb_we_i and wb_cyc_i and wb_stb_i;
end process;
-- VGA reset generator.
process(clk_50Mhz, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(clk_50Mhz) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
-- Compute the VGA RAM offset we need to use to fetch the character.
vga_ram_address <= hdisp +
vga_v_offset;
ram:zpuino_vga_ram
port map (
v_clk => clk_50Mhz,
v_en => '1',
v_addr => std_logic_vector(vga_ram_address),
v_data => vga_ram_data,
-- Memory interface
mi_clk => wb_clk_i,
mi_dat_i => wb_dat_i(7 downto 0),
mi_we => ram_we,
mi_en => '1',
mi_dat_o => ram_read,
mi_addr => wb_adr_i(16 downto 2)
);
-- Horizontal counter
hcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
hoff <= (others =>'0');
hdisp <= (others => '0');
else
hcount_q <= hcount_q + 1;
if hoff="100" then
hoff <= (others => '0');
hdisp <= hdisp + 1;
else
hoff <= hoff + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end if;
end process;
hsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_BACKPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_FRONTPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
voff<=(others => '0');
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
voff <= (others => '0');
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
if voff="100" then
voff <= (others => '0');
vga_v_offset <= vga_v_offset + 160;
else
voff <= voff + 1;
end if;
end if;
end if;
end if;
end if;
end process;
vsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_BACKPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_FRONTPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if v_display='0' then
vga_b <= (others =>'0');
vga_r <= (others =>'0');
vga_g <= (others =>'0');
else
vga_r <= vga_ram_data(7 downto 5);
vga_g <= vga_ram_data(4 downto 2);
vga_b <= vga_ram_data(1 downto 0);
end if;
end if;
end process;
end behave;
|
--
-- VGA interface for ZPUINO (and others)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity VIDEO_zpuino_wb_vga_hqvga is
generic(
vgaclk_divider: integer := 1
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
-- VGA interface
clk_50Mhz: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_r2: out std_logic;
vga_r1: out std_logic;
vga_r0: out std_logic;
vga_g2: out std_logic;
vga_g1: out std_logic;
vga_g0: out std_logic;
vga_b1: out std_logic;
vga_b0: out std_logic
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
);
end entity VIDEO_zpuino_wb_vga_hqvga;
architecture behave of VIDEO_zpuino_wb_vga_hqvga is
-- Clock is 50 MHz Hor Vert
-- Disp FP Sync BP Disp FP Sync BP
-- 800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
constant VGA_H_SYNC: integer := 120;
constant VGA_H_FRONTPORCH: integer := 56;
constant VGA_H_DISPLAY: integer := 800;
constant VGA_H_BACKPORCH: integer := 64;
constant VGA_V_FRONTPORCH: integer := 37;
constant VGA_V_SYNC: integer := 6;
constant VGA_V_DISPLAY: integer := 600;
constant VGA_V_BACKPORCH: integer := 23;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '0';
constant h_polarity: std_logic := '0';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
component zpuino_vga_ram is
port (
-- Scan
v_clk: in std_logic;
v_en: in std_logic;
v_addr: in std_logic_vector(14 downto 0);
v_data: out std_logic_vector(7 downto 0);
-- Memory interface
mi_clk: in std_logic;
mi_dat_i: in std_logic_vector(7 downto 0); -- Data write
mi_we: in std_logic;
mi_en: in std_logic;
mi_dat_o: out std_logic_vector(7 downto 0); -- 9 bits
mi_addr: in std_logic_vector(14 downto 0)
);
end component zpuino_vga_ram;
signal rstq1,rstq2: std_logic;
signal vga_ram_address: unsigned(14 downto 0);
signal vga_ram_data: std_logic_vector(7 downto 0);
signal v_display: std_logic;
signal ram_read: std_logic_vector(7 downto 0);
signal ram_we: std_logic;
signal vga_v_offset: unsigned(14 downto 0);
signal hoff: unsigned(2 downto 0); -- will count from 0 to 4
signal voff: unsigned(2 downto 0); -- will count from 0 to 4
signal hdisp: unsigned(13 downto 2);
signal read_ended: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
signal vga_r: std_logic_vector(2 downto 0);
signal vga_g: std_logic_vector(2 downto 0);
signal vga_b: std_logic_vector(1 downto 0);
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
-- vga_r: out std_logic_vector(2 downto 0);
-- vga_g: out std_logic_vector(2 downto 0);
-- vga_b: out std_logic_vector(1 downto 0)
vga_r2 <= vga_r(2);
vga_r1 <= vga_r(1);
vga_r0 <= vga_r(0);
vga_g2 <= vga_g(2);
vga_g1 <= vga_g(1);
vga_g0 <= vga_g(0);
vga_b1 <= vga_b(1);
vga_b0 <= vga_b(0);
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_ended<='0';
else
read_ended<=wb_stb_i and wb_cyc_i and not wb_we_i;
end if;
end if;
end process;
wb_ack_o <= wb_stb_i and wb_cyc_i and (read_ended or wb_we_i);
-- Read muxer
process(wb_adr_i,ram_read)
begin
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= ram_read;
end process;
process(wb_we_i,wb_cyc_i,wb_stb_i,wb_adr_i)
begin
ram_we <= wb_we_i and wb_cyc_i and wb_stb_i;
end process;
-- VGA reset generator.
process(clk_50Mhz, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(clk_50Mhz) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
-- Compute the VGA RAM offset we need to use to fetch the character.
vga_ram_address <= hdisp +
vga_v_offset;
ram:zpuino_vga_ram
port map (
v_clk => clk_50Mhz,
v_en => '1',
v_addr => std_logic_vector(vga_ram_address),
v_data => vga_ram_data,
-- Memory interface
mi_clk => wb_clk_i,
mi_dat_i => wb_dat_i(7 downto 0),
mi_we => ram_we,
mi_en => '1',
mi_dat_o => ram_read,
mi_addr => wb_adr_i(16 downto 2)
);
-- Horizontal counter
hcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
hoff <= (others =>'0');
hdisp <= (others => '0');
else
hcount_q <= hcount_q + 1;
if hoff="100" then
hoff <= (others => '0');
hdisp <= hdisp + 1;
else
hoff <= hoff + 1;
end if;
end if;
end if;
end if;
end process;
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end if;
end process;
hsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_BACKPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_FRONTPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
voff<=(others => '0');
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
voff <= (others => '0');
vga_v_offset <= (others => '0'); -- Reset VGA vertical offset
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
if voff="100" then
voff <= (others => '0');
vga_v_offset <= vga_v_offset + 160;
else
voff <= voff + 1;
end if;
end if;
end if;
end if;
end if;
end process;
vsyncgen: process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_BACKPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_FRONTPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(clk_50Mhz)
begin
if rising_edge(clk_50Mhz) then
if v_display='0' then
vga_b <= (others =>'0');
vga_r <= (others =>'0');
vga_g <= (others =>'0');
else
vga_r <= vga_ram_data(7 downto 5);
vga_g <= vga_ram_data(4 downto 2);
vga_b <= vga_ram_data(1 downto 0);
end if;
end if;
end process;
end behave;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cmd_status.vhd
--
-- Description:
-- This file implements the DataMover Command and Status interfaces.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_3;
Use axi_sg_v4_1_3.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_cmd_status is
generic (
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Indictes the width of the DataMover Address bus
C_INCLUDE_STSFIFO : Integer range 0 to 1 := 1;
-- Indicates if a Stus FIFO is to be included or omitted
-- 0 = Omit
-- 1 = Include
C_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Sets the depth of the Command and Status FIFOs
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Indicates if the Command and Status Stream Channels are clocked with
-- a different clock than the Main dataMover Clock
-- 0 = Same Clock
-- 1 = Different clocks
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command
C_STS_WIDTH : Integer := 8;
-- Sets the width of the output status
C_FAMILY : string := "virtex7"
-- Sets the target FPGA family
);
port (
-- Clock inputs ----------------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
secondary_awclk : in std_logic; --
-- Clock used for the Command and Status User Interface --
-- when the User Command and Status interface is Async --
-- to the MMap interface. Async mode is set by the assigned --
-- value to C_STSCMD_IS_ASYNC = 1. --
--------------------------------------------------------------------
-- Reset inputs ----------------------------------------------------
user_reset : in std_logic; --
-- Reset used for the User Stream interface logic --
--
internal_reset : in std_logic; --
-- Reset used for the internal master interface logic --
--------------------------------------------------------------------
-- User Command Stream Ports (AXI Stream) -------------------------------
cmd_wvalid : in std_logic; --
cmd_wready : out std_logic; --
cmd_wdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
cache_data : in std_logic_vector(7 downto 0); --
-------------------------------------------------------------------------
-- User Status Stream Ports (AXI Stream) ------------------------------------
sts_wvalid : out std_logic; --
sts_wready : in std_logic; --
sts_wdata : out std_logic_vector(C_STS_WIDTH-1 downto 0); --
sts_wstrb : out std_logic_vector((C_STS_WIDTH/8)-1 downto 0); --
sts_wlast : out std_logic; --
-----------------------------------------------------------------------------
-- Internal Command Out Interface -----------------------------------------------
cmd2mstr_command : Out std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : Out std_logic_vector(7 downto 0); --
-- The cache value available from the FIFO/Register --
--
mst2cmd_cmd_valid : Out std_logic; --
-- Handshake bit indicating the Command FIFO/Register has at least 1 valid --
-- command entry --
--
cmd2mstr_cmd_ready : in std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
---------------------------------------------------------------------------------
-- Internal Status In Interface -----------------------------------------------------
mstr2stat_status : in std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- The input for writing the status value to the Status FIFO/Register --
--
stat2mstr_status_ready : Out std_logic; --
-- Handshake bit indicating that the Status FIFO/Register is ready for transfer --
--
mst2stst_status_valid : In std_logic --
-- Handshake bit for writing the Status value into the Status FIFO/Register --
--------------------------------------------------------------------------------------
);
end entity axi_sg_cmd_status;
architecture implementation of axi_sg_cmd_status is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_fifo_prim_type
--
-- Function Description:
-- Returns the fifo primitiver type to use for the given input
-- conditions.
--
-- 0 = Not used or allowed here
-- 1 = BRAM Primitives (Block Memory)
-- 2 = Distributed memory
--
-------------------------------------------------------------------
function get_fifo_prim_type (is_async : integer;
depth : integer) return integer is
Variable var_temp_prim_type : Integer := 1;
begin
-- coverage off
if (is_async = 1) then -- Async FIFOs always use Blk Mem (BRAM)
var_temp_prim_type := 1;
elsif (depth <= 64) then -- (use srls or distrubuted)
var_temp_prim_type := 2;
else -- depth is too big for SRLs so use Blk Memory (BRAM)
var_temp_prim_type := 1;
end if;
-- coverage on
Return (var_temp_prim_type);
end function get_fifo_prim_type;
-- Constants
Constant REGISTER_TYPE : integer := 0;
Constant BRAM_TYPE : integer := 1;
--Constant SRL_TYPE : integer := 2;
--Constant FIFO_PRIM_TYPE : integer := SRL_TYPE;
Constant FIFO_PRIM_TYPE : integer := get_fifo_prim_type(C_STSCMD_IS_ASYNC,
C_STSCMD_FIFO_DEPTH);
-- Signals
signal sig_cmd_fifo_wr_clk : std_logic := '0';
signal sig_cmd_fifo_wr_rst : std_logic := '0';
signal sig_cmd_fifo_rd_clk : std_logic := '0';
signal sig_cmd_fifo_rd_rst : std_logic := '0';
signal sig_sts_fifo_wr_clk : std_logic := '0';
signal sig_sts_fifo_wr_rst : std_logic := '0';
signal sig_sts_fifo_rd_clk : std_logic := '0';
signal sig_sts_fifo_rd_rst : std_logic := '0';
signal sig_reset_mstr : std_logic := '0';
signal sig_reset_user : std_logic := '0';
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- synchronous User interface case
--
------------------------------------------------------------
GEN_SYNC_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= internal_reset ;
sig_cmd_fifo_wr_clk <= primary_aclk ;
sig_cmd_fifo_wr_rst <= sig_reset_user;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr;
sig_sts_fifo_rd_clk <= primary_aclk ;
sig_sts_fifo_rd_rst <= sig_reset_user;
end generate GEN_SYNC_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- Asynchronous User interface case
--
------------------------------------------------------------
GEN_ASYNC_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= user_reset ;
sig_cmd_fifo_wr_clk <= secondary_awclk;
sig_cmd_fifo_wr_rst <= sig_reset_user ;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr ;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr ;
sig_sts_fifo_rd_clk <= secondary_awclk;
sig_sts_fifo_rd_rst <= sig_reset_user ;
end generate GEN_ASYNC_RESET;
------------------------------------------------------------
-- Instance: I_CMD_FIFO
--
-- Description:
-- Instance for the Command FIFO
-- The User Interface is the Write Side
-- The Internal Interface is the Read side
--
------------------------------------------------------------
I_CMD_FIFO : entity axi_sg_v4_1_3.axi_sg_fifo
generic map (
C_DWIDTH => C_CMD_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => cmd_wready ,
fifo_wr_tdata => cmd_wdata ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cmd2mstr_command ,
fifo_rd_empty => open
);
I_CACHE_FIFO : entity axi_sg_v4_1_3.axi_sg_fifo
generic map (
C_DWIDTH => 8 ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => open ,--cmd_wready ,
fifo_wr_tdata => cache_data ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => open ,--mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cache2mstr_command ,
fifo_rd_empty => open
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_STATUS_FIFO
--
-- If Generate Description:
-- Instantiates a Status FIFO
--
--
------------------------------------------------------------
GEN_INCLUDE_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 1) generate
begin
-- Set constant outputs for Status Interface
sts_wstrb <= (others => '1');
sts_wlast <= '1';
------------------------------------------------------------
-- Instance: I_STS_FIFO
--
-- Description:
-- Instance for the Status FIFO
-- The Internal Interface is the Write Side
-- The User Interface is the Read side
--
------------------------------------------------------------
I_STS_FIFO : entity axi_sg_v4_1_3.axi_sg_fifo
generic map (
C_DWIDTH => C_STS_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_sts_fifo_wr_rst ,
fifo_wr_clk => sig_sts_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => mst2stst_status_valid ,
fifo_wr_tready => stat2mstr_status_ready,
fifo_wr_tdata => mstr2stat_status ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_sts_fifo_rd_rst ,
fifo_async_rd_clk => sig_sts_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => sts_wvalid ,
fifo_rd_tready => sts_wready ,
fifo_rd_tdata => sts_wdata ,
fifo_rd_empty => open
);
end generate GEN_INCLUDE_STATUS_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_STATUS_FIFO
--
-- If Generate Description:
-- Omits the Status FIFO
--
--
------------------------------------------------------------
GEN_OMIT_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 0) generate
begin
-- Status FIFO User interface housekeeping
sts_wvalid <= '0';
-- sts_wready -- ignored
sts_wdata <= (others => '0');
sts_wstrb <= (others => '0');
sts_wlast <= '0';
-- Status FIFO Internal interface housekeeping
stat2mstr_status_ready <= '1';
-- mstr2stat_status -- ignored
-- mst2stst_status_valid -- ignored
end generate GEN_OMIT_STATUS_FIFO;
end implementation;
|
library verilog;
use verilog.vl_types.all;
entity Test is
port(
address : in vl_logic_vector(0 downto 0);
clock : in vl_logic;
q : out vl_logic_vector(15 downto 0)
);
end Test;
|
library verilog;
use verilog.vl_types.all;
entity Test is
port(
address : in vl_logic_vector(0 downto 0);
clock : in vl_logic;
q : out vl_logic_vector(15 downto 0)
);
end Test;
|
-- implementation of the HDB1 decoder.
entity hdb1_dec is
port (
clr_bar,
clk, e0, e1 : in bit; -- inputs.
s : out bit -- output.
);
end hdb1_dec;
architecture behaviour of hdb1_dec is
signal q0, q1: bit; -- two flipflops.
begin
process (clk, clr_bar) begin
if clr_bar = '0' then
q0 <= '0';
q1 <= '0';
s <= '0';
elsif clk'event and clk = '1' then
s <= ( q0 and (not e0) ) or ( q1 and (not e1) );
q0 <= (not q0) and e0;
q1 <= (not q1) and e1;
end if;
end process;
end behaviour;
|
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/10/26 12:26:23
-- Nombre del módulo: contador_reloj - Behavioral
-- Descripción:
-- Contador para el reloj. Se encarga de recibir una señal de 1/60Hz (1 minuto)
-- y contar el tiempo para mostrar la hora y los minutos.
-- A la salida, entrega los cuatro dígitos correspondientes a HH:mm.
--
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
entity contador_reloj is
PORT (
clk : IN STD_LOGIC; --Reloj de 1Hz.
reset: IN STD_LOGIC; --Señal de reset.
H1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --Segundo digito de la hora.
H0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --Primer digito de la hora.
M1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --Segundo digito de los minutos.
M0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) --Primer digito de los minutos.
);
end contador_reloj;
architecture Behavioral of contador_reloj is
signal mm1: UNSIGNED(2 downto 0) := "000" ;
signal mm0: UNSIGNED(3 downto 0) := "0000";
signal hh1: UNSIGNED(2 downto 0) := "000" ;
signal hh0: UNSIGNED(3 downto 0) := "0000";
begin
reloj: process (clk, reset) begin
if reset = '1' then
hh1 <= "000" ;
hh0 <= "0000";
mm1 <= "000" ;
mm0 <= "0000";
elsif rising_edge(clk) then
mm0 <= mm0 + 1;
if mm0 = 9 then
mm1 <= mm1 + 1;
mm0 <= "0000";
end if;
-- Al pasar 59 minutos, contar una hora.
if mm1 = 5 AND mm0 = 9 then
hh0 <= hh0 + 1;
mm1 <= "000";
end if;
if hh0 = 9 then
hh1 <= hh1 + 1;
hh0 <= "0000";
end if;
-- Al pasar 23:59, regresar a 00:00.
if hh1 = 2 AND hh0 = 3 AND mm1 = 5 AND mm0 = 9 then
hh1 <= "000";
hh0 <= "0000";
end if;
end if;
end process;
--Asignación de señales.
H1 <= STD_LOGIC_VECTOR(hh1);
H0 <= STD_LOGIC_VECTOR(hh0);
M1 <= STD_LOGIC_VECTOR(mm1);
M0 <= STD_LOGIC_VECTOR(mm0);
end Behavioral; |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/10/26 12:26:23
-- Nombre del módulo: contador_reloj - Behavioral
-- Descripción:
-- Contador para el reloj. Se encarga de recibir una señal de 1/60Hz (1 minuto)
-- y contar el tiempo para mostrar la hora y los minutos.
-- A la salida, entrega los cuatro dígitos correspondientes a HH:mm.
--
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
entity contador_reloj is
PORT (
clk : IN STD_LOGIC; --Reloj de 1Hz.
reset: IN STD_LOGIC; --Señal de reset.
H1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --Segundo digito de la hora.
H0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --Primer digito de la hora.
M1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --Segundo digito de los minutos.
M0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) --Primer digito de los minutos.
);
end contador_reloj;
architecture Behavioral of contador_reloj is
signal mm1: UNSIGNED(2 downto 0) := "000" ;
signal mm0: UNSIGNED(3 downto 0) := "0000";
signal hh1: UNSIGNED(2 downto 0) := "000" ;
signal hh0: UNSIGNED(3 downto 0) := "0000";
begin
reloj: process (clk, reset) begin
if reset = '1' then
hh1 <= "000" ;
hh0 <= "0000";
mm1 <= "000" ;
mm0 <= "0000";
elsif rising_edge(clk) then
mm0 <= mm0 + 1;
if mm0 = 9 then
mm1 <= mm1 + 1;
mm0 <= "0000";
end if;
-- Al pasar 59 minutos, contar una hora.
if mm1 = 5 AND mm0 = 9 then
hh0 <= hh0 + 1;
mm1 <= "000";
end if;
if hh0 = 9 then
hh1 <= hh1 + 1;
hh0 <= "0000";
end if;
-- Al pasar 23:59, regresar a 00:00.
if hh1 = 2 AND hh0 = 3 AND mm1 = 5 AND mm0 = 9 then
hh1 <= "000";
hh0 <= "0000";
end if;
end if;
end process;
--Asignación de señales.
H1 <= STD_LOGIC_VECTOR(hh1);
H0 <= STD_LOGIC_VECTOR(hh0);
M1 <= STD_LOGIC_VECTOR(mm1);
M0 <= STD_LOGIC_VECTOR(mm0);
end Behavioral; |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/10/26 12:26:23
-- Nombre del módulo: contador_reloj - Behavioral
-- Descripción:
-- Contador para el reloj. Se encarga de recibir una señal de 1/60Hz (1 minuto)
-- y contar el tiempo para mostrar la hora y los minutos.
-- A la salida, entrega los cuatro dígitos correspondientes a HH:mm.
--
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
entity contador_reloj is
PORT (
clk : IN STD_LOGIC; --Reloj de 1Hz.
reset: IN STD_LOGIC; --Señal de reset.
H1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --Segundo digito de la hora.
H0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --Primer digito de la hora.
M1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --Segundo digito de los minutos.
M0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) --Primer digito de los minutos.
);
end contador_reloj;
architecture Behavioral of contador_reloj is
signal mm1: UNSIGNED(2 downto 0) := "000" ;
signal mm0: UNSIGNED(3 downto 0) := "0000";
signal hh1: UNSIGNED(2 downto 0) := "000" ;
signal hh0: UNSIGNED(3 downto 0) := "0000";
begin
reloj: process (clk, reset) begin
if reset = '1' then
hh1 <= "000" ;
hh0 <= "0000";
mm1 <= "000" ;
mm0 <= "0000";
elsif rising_edge(clk) then
mm0 <= mm0 + 1;
if mm0 = 9 then
mm1 <= mm1 + 1;
mm0 <= "0000";
end if;
-- Al pasar 59 minutos, contar una hora.
if mm1 = 5 AND mm0 = 9 then
hh0 <= hh0 + 1;
mm1 <= "000";
end if;
if hh0 = 9 then
hh1 <= hh1 + 1;
hh0 <= "0000";
end if;
-- Al pasar 23:59, regresar a 00:00.
if hh1 = 2 AND hh0 = 3 AND mm1 = 5 AND mm0 = 9 then
hh1 <= "000";
hh0 <= "0000";
end if;
end if;
end process;
--Asignación de señales.
H1 <= STD_LOGIC_VECTOR(hh1);
H0 <= STD_LOGIC_VECTOR(hh0);
M1 <= STD_LOGIC_VECTOR(mm1);
M0 <= STD_LOGIC_VECTOR(mm0);
end Behavioral; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad
-- File: iopad.vhd
-- Author: Nils Johan Wessman - Gaisler Research
-- Description: differential io pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iopad_ds is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iopad_ds is
signal oen : std_ulogic;
begin
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_pads(tech) = 0 generate
padp <= i after 2 ns when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z' after 2 ns;
padn <= not i after 2 ns when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z' after 2 ns;
o <= to_X01(padp) after 1 ns;
end generate;
xcv : if (tech = virtex5) generate
x0 : virtex5_iopad_ds generic map (level, slew, voltage, strength)
port map (padp, padn, i, oen, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_dsv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopad_dsv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en, o(j));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopad_dsvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en(j), o(j));
end generate;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad
-- File: iopad.vhd
-- Author: Nils Johan Wessman - Gaisler Research
-- Description: differential io pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iopad_ds is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iopad_ds is
signal oen : std_ulogic;
begin
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_pads(tech) = 0 generate
padp <= i after 2 ns when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z' after 2 ns;
padn <= not i after 2 ns when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z' after 2 ns;
o <= to_X01(padp) after 1 ns;
end generate;
xcv : if (tech = virtex5) generate
x0 : virtex5_iopad_ds generic map (level, slew, voltage, strength)
port map (padp, padn, i, oen, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_dsv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopad_dsv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en, o(j));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopad_dsvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en(j), o(j));
end generate;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity projeto2 is
port (
a : in std_logic_vector (3 downto 0) := "0001"; -- Entrada A.
b : in std_logic_vector (3 downto 0) := "0000"; -- Entrada B.
clk : in std_logic := '0'; -- Clock.
display1 : out std_logic_vector (6 downto 0);
display2 : out std_logic_vector (6 downto 0)
);
end projeto2;
architecture Behavioral of projeto2 is
signal saida_mux : std_logic_vector (3 downto 0);
signal bcd : std_logic_vector (6 downto 0); -- BCD.
begin
-- Mux 8->4.
process (a,b, clk)
begin
if (clk = '0') then
saida_mux <= a;
else
saida_mux <= b;
end if;
end process;
-- BCD.
process (a,b,clk, saida_mux, bcd)
begin
if (saida_mux = "0000") then -- 0
bcd <= "1111110";
elsif (saida_mux = "0001") then -- 1
bcd <= "0110000";
elsif (saida_mux = "0010") then -- 2
bcd <= "1101101";
elsif (saida_mux = "0011") then -- 3
bcd <= "1111001";
elsif (saida_mux = "0100") then -- 4
bcd <= "0110010";
elsif (saida_mux = "0101") then -- 5
bcd <= "1011010";
elsif (saida_mux = "0110") then -- 6
bcd <= "1011111";
elsif (saida_mux = "0111") then -- 7
bcd <= "1110000";
elsif (saida_mux = "1000") then -- 8
bcd <= "1111111";
elsif (saida_mux = "1001") then -- 9
bcd <= "1111011";
elsif (saida_mux = "1010") then -- A
bcd <= "1110111";
elsif (saida_mux = "1011") then -- B
bcd <= "0011111";
elsif (saida_mux = "1100") then -- C
bcd <= "1001110";
elsif (saida_mux = "1101") then -- D
bcd <= "0111101";
elsif (saida_mux = "1110") then -- E
bcd <= "1001111";
else
bcd <= "1000111"; -- Caso defaul -> 'F'
end if;
end process;
-- Mux 1->2.
process (bcd, clk)
begin
if (clk = '0') then
display1 <= bcd;
else
display2 <= bcd;
end if;
end process;
end Behavioral; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity projeto2 is
port (
a : in std_logic_vector (3 downto 0) := "0001"; -- Entrada A.
b : in std_logic_vector (3 downto 0) := "0000"; -- Entrada B.
clk : in std_logic := '0'; -- Clock.
display1 : out std_logic_vector (6 downto 0);
display2 : out std_logic_vector (6 downto 0)
);
end projeto2;
architecture Behavioral of projeto2 is
signal saida_mux : std_logic_vector (3 downto 0);
signal bcd : std_logic_vector (6 downto 0); -- BCD.
begin
-- Mux 8->4.
process (a,b, clk)
begin
if (clk = '0') then
saida_mux <= a;
else
saida_mux <= b;
end if;
end process;
-- BCD.
process (a,b,clk, saida_mux, bcd)
begin
if (saida_mux = "0000") then -- 0
bcd <= "1111110";
elsif (saida_mux = "0001") then -- 1
bcd <= "0110000";
elsif (saida_mux = "0010") then -- 2
bcd <= "1101101";
elsif (saida_mux = "0011") then -- 3
bcd <= "1111001";
elsif (saida_mux = "0100") then -- 4
bcd <= "0110010";
elsif (saida_mux = "0101") then -- 5
bcd <= "1011010";
elsif (saida_mux = "0110") then -- 6
bcd <= "1011111";
elsif (saida_mux = "0111") then -- 7
bcd <= "1110000";
elsif (saida_mux = "1000") then -- 8
bcd <= "1111111";
elsif (saida_mux = "1001") then -- 9
bcd <= "1111011";
elsif (saida_mux = "1010") then -- A
bcd <= "1110111";
elsif (saida_mux = "1011") then -- B
bcd <= "0011111";
elsif (saida_mux = "1100") then -- C
bcd <= "1001110";
elsif (saida_mux = "1101") then -- D
bcd <= "0111101";
elsif (saida_mux = "1110") then -- E
bcd <= "1001111";
else
bcd <= "1000111"; -- Caso defaul -> 'F'
end if;
end process;
-- Mux 1->2.
process (bcd, clk)
begin
if (clk = '0') then
display1 <= bcd;
else
display2 <= bcd;
end if;
end process;
end Behavioral; |
library gpr;
use gpr.OneHotGPR.all;
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity mrom_tb is
end mrom_tb;
architecture TB_ARCHITECTURE of mrom_tb is
-- Component declaration of the tested unit
component mrom
port(
RE : in STD_LOGIC;
ADDR : in mem_addr;
DOUT : out command );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal RE : STD_LOGIC;
signal ADDR : mem_addr;
-- Observed signals - signals mapped to the output ports of tested entity
signal DOUT : command;
constant WAIT_period: time := 10 ns;
begin
-- Unit Under Test port map
UUT : mrom
port map (
RE => RE,
ADDR => ADDR,
DOUT => DOUT
);
-- Add your stimulus here ...
main: process
begin
re <= '0';
addr <= "00010";
wait for 1 * WAIT_period;
re <= '1';
wait for 1 * WAIT_period;
addr <= "00000";
re <= '1';
wait for 1 * WAIT_period;
re <= '0';
wait for 100 * WAIT_period;
wait;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_mrom of mrom_tb is
for TB_ARCHITECTURE
for UUT : mrom
use entity work.mrom(beh_gpr);
end for;
end for;
end TESTBENCH_FOR_mrom;
|
----------------------------------------------------------------------------------------------------
-- MMU out
-- It arranges the output of the DRAM according to the control signals for the current mem operation
-- and on the control signal generated from MMU in
-- Note it arrenges byte according to the Big Endian format
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
-----------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------
entity mmu_out_dram is
port (
-- INPUTS
data_ram : in std_logic_vector(31 downto 0); -- data coming from the dram
mem_op : in std_logic_vector(5 downto 0); -- control signals grouped in the following order (sb, sw, lbu, lw, lhu, lb)
nibble : in std_logic_vector(1 downto 0); -- which byte should be selected
unaligned : in std_logic; -- in case of unaligned access set the output to zero
-- OUTPUTS
data_read : out std_logic_vector(31 downto 0) -- data in the correct format
);
end mmu_out_dram;
-----------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------
architecture behavioral of mmu_out_dram is
begin
-------------------------
-- Name: Comb Logic
-- Type: Combinational
-- Purpose: Implemnt the
-- comb logic of the
-- MMU out
------------------------
comb_logic:process(data_ram, mem_op, nibble, unaligned)
begin
if (unaligned = '1') then
data_read <= (others => '0');
else
case mem_op is
when "000100" => -- lw
data_read <= data_ram;
when "000010" => -- lhu
if (nibble = "00") then
data_read(31 downto 16) <= (others => '0');
data_read(15 downto 0) <= data_ram(31 downto 16);
else
-- nibble = "10"
data_read(31 downto 16) <= (others => '0');
data_read(15 downto 0) <= data_ram(15 downto 0);
end if;
when "000001" => -- lb
case nibble is
when "00" =>
if (data_ram(31) = '1') then
-- last bit at one, extend with one
data_read(7 downto 0) <= data_ram(31 downto 24);
data_read(31 downto 8) <= (others => '1');
else
-- last bit at zero, extend with zero
data_read(7 downto 0) <= data_ram(31 downto 24);
data_read(31 downto 8) <= (others => '0');
end if;
when "01" =>
if (data_ram(23) = '1') then
-- last bit at one, extend with one
data_read(7 downto 0) <= data_ram(23 downto 16);
data_read(31 downto 8) <= (others => '1');
else
-- last bit at zero, extend with zero
data_read(7 downto 0) <= data_ram(23 downto 16);
data_read(31 downto 8) <= (others => '0');
end if;
when "10" =>
if (data_ram(15) = '1') then
-- last bit at one, extend with one
data_read(7 downto 0) <= data_ram(15 downto 8);
data_read(31 downto 8) <= (others => '1');
else
-- last bit at zero, extend with zero
data_read(7 downto 0) <= data_ram(15 downto 8);
data_read(31 downto 8) <= (others => '0');
end if;
when "11" =>
if (data_ram(7) = '1') then
-- last bit at one, extend with one
data_read(7 downto 0) <= data_ram(7 downto 0);
data_read(31 downto 8) <= (others => '1');
else
-- last bit at zero, extend with zero
data_read(7 downto 0) <= data_ram(7 downto 0);
data_read(31 downto 8) <= (others => '0');
end if;
when others =>
data_read <= (others => '0');
end case;
when "001000" => -- lbu
case nibble is
when "00" =>
data_read(7 downto 0) <= data_ram(31 downto 24);
data_read(31 downto 8) <= (others => '0');
when "01" =>
data_read(7 downto 0) <= data_ram(23 downto 16);
data_read(31 downto 8) <= (others => '0');
when "10" =>
data_read(7 downto 0) <= data_ram(15 downto 8);
data_read(31 downto 8) <= (others => '0');
when "11" =>
data_read(7 downto 0) <= data_ram(7 downto 0);
data_read(31 downto 8) <= (others => '0');
when others =>
data_read <= (others => '0');
end case;
when others =>
data_read <= (others => '0');
end case;
end if;
end process;
end behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_205 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_205;
architecture augh of add_205 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_205 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_205;
architecture augh of add_205 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
package body pkg_fifo is
end package body pkg_fifo;
package body fifo is
end package body fifo;
|
-- Descp. Allow the user to input the score
--
-- entity name: g05_score_input
--
-- Version 1.0
-- Author: Felix Dube; [email protected] & Auguste Lalande; [email protected]
-- Date: November 30, 2015
library ieee;
use ieee.std_logic_1164.all;
entity g05_score_input is
port (
increment, sel : in std_logic;
score : out std_logic_vector(2 downto 0);
score_part : out std_logic
);
end g05_score_input;
architecture behavior of g05_score_input is
type score_part_type is (s1, s2);
type score_type is (c1, c2, c3, c4, c5);
signal s_present, s_next : score_part_type;
signal c_present, c_next : score_type;
begin
selector: process(sel)
begin
case s_present is
when s1 =>
if sel = '0' then
s_next <= s2;
else
s_next <= s1;
end if;
when s2 =>
if sel = '0' then
s_next <= s1;
else
s_next <= s2;
end if;
when others =>
s_next <= s1;
end case;
end process;
process(sel)
begin
if rising_edge(sel) then
s_present <= s_next;
end if;
end process;
incrementor: process(increment)
begin
case c_present is
when c1 =>
if increment = '0' then
c_next <= c2;
else
c_next <= c1;
end if;
when c2 =>
if increment = '0' then
c_next <= c3;
else
c_next <= c2;
end if;
when c3 =>
if increment = '0' then
c_next <= c4;
else
c_next <= c3;
end if;
when c4 =>
if increment = '0' then
c_next <= c5;
else
c_next <= c4;
end if;
when c5 =>
if increment = '0' then
c_next <= c1;
else
c_next <= c5;
end if;
when others =>
c_next <= c1;
end case;
end process;
process(increment)
begin
if rising_edge(increment) then
c_present <= c_next;
end if;
end process;
score <= "000" when c_present = c1 else
"001" when c_present = c2 else
"010" when c_present = c3 else
"011" when c_present = c4 else
"100" when c_present = c5 else
"000";
score_part <= '0' when s_present = s1 else '1';
end behavior; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben oztalay
--
-- Create Date: 00:56:02 04/10/2009
-- Design Name:
-- Module Name: Gate_Buf - Behavioral
-- Project Name: Buffer
-- Target Devices:
-- Tool versions:
-- Description: A buffer with 1 input
--
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Gate_Buf is
Port ( A : in STD_LOGIC;
Q : out STD_LOGIC);
end Gate_Buf;
architecture Behavioral of Gate_Buf is
begin
Q <= A;
end Behavioral;
|
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11 12:10:13 rherveille Exp $
--
-- $Date: 2006/10/11 12:10:13 $
-- $Revision: 1.14 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_bit_ctrl.vhd,v $
-- Revision 1.14 2006/10/11 12:10:13 rherveille
-- Added missing semicolons ';' on endif
--
-- Revision 1.13 2006/10/06 10:48:24 rherveille
-- fixed short scl high pulse after clock stretch
--
-- Revision 1.12 2004/05/07 11:53:31 rherveille
-- Fixed previous fix :) Made a variable vs signal mistake.
--
-- Revision 1.11 2004/05/07 11:04:00 rherveille
-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
-- Revision 1.10 2004/02/27 07:49:43 rherveille
-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
-- Revision 1.9 2003/08/12 14:48:37 rherveille
-- Forgot an 'end if' :-/
--
-- Revision 1.8 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.7 2003/02/05 00:06:02 rherveille
-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
-- Revision 1.6 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.5 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.4 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.3 2002/10/30 18:09:53 rherveille
-- Fixed some reported minor start/stop generation timing issuess.
--
-- Revision 1.2 2002/06/15 07:37:04 rherveille
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
-- Modified by Jan Andersson ([email protected]):
--
-- * Added two start states to fulfill Set-up time for
-- repeated START condition.
-- * Modified synchronization of SCL and SDA. START and STOP detection
-- is now performed after a two stage synchronizer and is also
-- filtered.
-- * Changed evaluation order of 'slave_wait', 'en' and 'cnt' in
-- generation of clk_en signal to prevent clk_en assertion when
-- slave_wait is asserted.
-- * Needed to differentiate between slave clock stretching and master
-- clock synchronization.
-- * Added register s_state which contains the next state in case
-- of clock synchronization
-- * Incorporated change in wr_b state from SVN rev. 72 of
-- original OC version (delay check of SDA).
-- * Added 'filter' generic that determines length of filter.
-- Original OC core has a median filter implemented. The solution
-- implemented in this version is a plain shift register with a
-- length determined by the new generic. All samples in this
-- register must be equal, otherwise the SCL or SDA value used by
-- the core will not be changed. Every SCL/SDA transition that is
-- not stable for 'filter' system clock cycles is disregarded.
-- This solution is potentially more vulnerable against short
-- periods of relatively quick fluctuations on the line, however
-- it should do a better job of ignoring 50 ns pulses and still
-- allow us to respond quickly to events on the line - assuming
-- that the core has been correctly configured.
-- Core revision has been increased to 2 (in GRLIB PnP)
-- * Added 'dynfilt' generic to allow dynamic adjustment of the
-- filter. This component takes in a filt vector that is used to
-- reload a filter counter. The filt vector is assigned via the
-- core's APB interface.
-- Reorganized parts of the code, moving signals into blocks.
-- Core revision increased to 3.
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start: SCL ~~~~~~~~~~~~~~\____
-- SDA XX/~~~~~~~\______
-- x | A | B | C | D | i
--
-- repstart SCL ______/~~~~~~~\___
-- SDA __/~~~~~~~\______
-- x | A | B | C | D | i
--
-- stop SCL _______/~~~~~~~~~~~
-- SDA ==\___________/~~~~~
-- x | A | B | C | D | i
--
--- write SCL ______/~~~~~~~\____
-- SDA XXX===============XX
-- x | A | B | C | D | i
--
--- read SCL ______/~~~~~~~\____
-- SDA XXXXXXX=XXXXXXXXXXX
-- x | A | B | C | D | i
--
-- Timing: Normal mode Fast mode
-----------------------------------------------------------------
-- Fscl 100KHz 400KHz
-- Th_scl 4.0us 0.6us High period of SCL
-- Tl_scl 4.7us 1.3us Low period of SCL
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity i2c_master_bit_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command completed
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_bit_ctrl;
architecture structural of i2c_master_bit_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
type states is (idle, start_a, start_b, start_c, start_d, start_e, start_f, start_g,
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state, s_state : states;
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
signal fSCL, fSDA : std_logic_vector(1 downto 0); -- Filtered SCL and SDA inputs
signal clk_en, slave_wait : std_logic; -- clock generation signals
signal ial : std_logic; -- internal arbitration lost signal
signal cnt : std_logic_vector(15 downto 0); -- clock divider counter
signal csync : std_logic; -- Need to synchronize clock with other master
begin
-- generate clk enable signal
gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cnt <= (others => '0');
clk_en <= '1';
elsif (ena = '0' or csync = '1') then
cnt <= clk_cnt;
clk_en <= '1';
elsif (slave_wait = '1') then
cnt <= cnt;
clk_en <= '0';
elsif (cnt = X"0000") then
cnt <= clk_cnt;
clk_en <= '1';
else
cnt <= cnt -1;
clk_en <= '0';
end if;
end if;
end process gen_clken;
-- generate bus status controller
bus_status_ctrl: block
signal sta_condition : std_logic; -- start detected
signal sto_condition : std_logic; -- stop detected
signal cmd_stop : std_logic; -- STOP command
signal ibusy : std_logic; -- internal busy signal
signal slvw_dis : std_logic; -- Slave wait disable;
begin
-- Static filter
staticfilt : if dynfilt = 0 generate
sfblock : block
constant FR : integer := filter; -- Filter range MSb
constant DR : integer := filter + 1; -- Delayed SCL/SDA range MSb
signal sSCL, sSDA : std_logic_vector(FR downto 0); -- synchronized SCL and SDA inputs
signal discl_oen : std_logic_vector(DR downto 0); -- delayed scl_oen signal
signal disda_oen : std_logic_vector(DR downto 0); -- delayed isda_oen
begin
-- synchronize SCL and SDA inputs
synch_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
sSCL <= (others => '1');
sSDA <= (others => '1');
fSCL <= (others => '1');
fSDA <= (others => '1');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sSCL <= (others => '1');
sSDA <= (others => '1');
fSCL <= (others => '1');
fSDA <= (others => '1');
else
sSCL <= sSCL(FR-1 downto 0) & scl_i;
sSDA <= sSDA(FR-1 downto 0) & sda_i;
-- Filtering
if andv(sSCL(FR downto 1)) = '1' then
fSCL <= fSCL(0) & '1';
elsif orv(sSCL(FR downto 1)) = '0' then
fSCL <= fSCL(0) & '0';
else
fSCL <= fSCL;
end if;
if andv(sSDA(FR downto 1)) = '1' then
fSDA <= fSDA(0) & '1';
elsif orv(sSDA(FR downto 1)) = '0' then
fSDA <= fSDA(0) & '0';
else
fSDA <= fSDA;
end if;
end if;
end if;
end process synch_SCL_SDA;
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk)
begin
if (clk'event and clk = '1') then
if rst = '1' then
discl_oen <= (others => '1');
slvw_dis <= '0';
else
-- Keep SCL output enable values
discl_oen <= discl_oen(DR-1 downto 0) & iscl_oen;
-- Disable slave stretch detection when other device drives SCL
-- H->L (only a master should to this).
slvw_dis <= (slvw_dis or csync) and discl_oen(0);
end if;
end if;
end process;
-- SCL forced low after master tried to assert, slave is stretching clock
slave_wait <= andv(discl_oen(DR downto 1)) and not fSCL(0) and not (slvw_dis or fSCL(1));
-- SCL HIGH time cut short, master clock synchronization
csync <= andv(discl_oen(DR downto 1)) and not fSCL(0) and fSCL(1);
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_al: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= (others => '1');
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= (others => '1');
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not fSDA(0) and disda_oen(DR));
else
ial <= (sda_chk and not fSDA(0) and disda_oen(DR)) or
(sto_condition and not cmd_stop);
end if;
end if;
disda_oen <= disda_oen(DR-1 downto 0) & isda_oen;
end if;
end process gen_al;
end block sfblock;
end generate staticfilt;
-- Dynamic filter
dynamicfilt : if dynfilt /= 0 generate
-- Fixed window
dfblock : block
signal filtcnt : std_logic_vector(filter-1 downto 0);
signal sSCL, sSDA : std_logic_vector(1 downto 0); -- synchronized SCL and SDA inputs
signal fiscl_oen : std_logic_vector(1 downto 0); -- "filtered" scl_oen signal
signal fisda_oen : std_ulogic; -- "filtered" sda_oen signal
signal fSCL_chg, fSDA_chg, fiscl_oen_chg, fisda_oen_chg : std_ulogic;
signal discl_oen : std_ulogic; -- delayed scl_oen signal
signal disda_oen : std_ulogic; -- delayed sda_oen signal
begin
-- Provides filtered signals for SCL and SDA, and corresponding
-- output enable signals.
sync_scl_sda: process(clk, nReset, fSCL_chg, fSDA_chg, fiscl_oen_chg, fisda_oen_chg)
variable scl_chg, sda_chg, iscl_oen_chg, isda_oen_chg : std_ulogic;
begin
--scl_chg := fSCL_chg; sda_chg := fSDA_chg;
--iscl_oen_chg := fiscl_oen_chg; isda_oen_chg := fisda_oen_chg;
if (nReset = '0') then
scl_chg := fSCL_chg; sda_chg := fSDA_chg;
iscl_oen_chg := fiscl_oen_chg; isda_oen_chg := fisda_oen_chg;
filtcnt <= (others => '0');
fSCL <= (others => '1'); fSDA <= (others => '1');
fSCL_chg <= '0'; fSDA_chg <= '0';
fiscl_oen <= (others => '1'); fiscl_oen_chg <= '0';
fisda_oen <= '1'; fisda_oen_chg <= '0';
elsif (clk'event and clk = '1') then
scl_chg := fSCL_chg; sda_chg := fSDA_chg;
iscl_oen_chg := fiscl_oen_chg; isda_oen_chg := fisda_oen_chg;
if (rst = '1') or (ena = '0') then
filtcnt <= (others => '0');
fSCL <= (others => '1'); fSDA <= (others => '1');
fSCL_chg <= '0'; fSDA_chg <= '0';
fiscl_oen <= (others => '1'); fiscl_oen_chg <= '0';
fisda_oen <= '1'; fisda_oen_chg <= '0';
else
if (sSCL(1) xor fSCL(0)) = '0' then scl_chg := '0'; end if;
if (sSDA(1) xor fSDA(0)) = '0' then sda_chg := '0'; end if;
if (discl_oen xor fiscl_oen(0)) = '0' then iscl_oen_chg := '0'; end if;
if (disda_oen xor fisda_oen) = '0' then isda_oen_chg := '0'; end if;
if filtcnt = zero32((filter-1)*dynfilt downto 0) then
filtcnt <= filt;
fSCL <= fSCL(0) & (fSCL(0) xor scl_chg);
fSDA <= fSDA(0) & (fSDA(0) xor sda_chg);
fSCL_chg <= '1'; fSDA_chg <= '1';
fiscl_oen <= fiscl_oen(0) & (fiscl_oen(0) xor iscl_oen_chg);
fiscl_oen_chg <= '1';
fisda_oen <= fisda_oen xor isda_oen_chg;
fisda_oen_chg <= '1';
else
filtcnt <= filtcnt - 1;
fSDA <= fSDA; fSCL <= fSCL;
fSCL_chg <= scl_chg; fSDA_chg <= sda_chg;
fiscl_oen <= fiscl_oen;
fiscl_oen_chg <= iscl_oen_chg;
fisda_oen <= fisda_oen;
fisda_oen_chg <= isda_oen_chg;
end if;
end if;
sSCL <= sSCL(0) & scl_i;
sSDA <= sSDA(0) & sda_i;
end if;
end process sync_SCL_SDA;
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk)
begin
if (clk'event and clk = '1') then
if rst = '1' then
discl_oen <= '1';
slvw_dis <= '0';
else
-- Keep SCL output enable values
discl_oen <= iscl_oen;
-- Disable slave stretch detection when other device drives SCL
-- H->L (only a master should to this).
slvw_dis <= (slvw_dis or csync) and discl_oen;
end if;
end if;
end process;
-- SCL forced low after master tried to assert, slave is stretching clock
slave_wait <= andv(fiscl_oen) and not fSCL(0) and not (slvw_dis or fSCL(1));
-- SCL HIGH time cut short, master clock synchronization
csync <= andv(fiscl_oen) and not fSCL(0) and fSCL(1);
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_ald: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= '1';
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not fSDA(0) and fisda_oen);
else
ial <= (sda_chk and not fSDA(0) and fisda_oen) or
(sto_condition and not cmd_stop);
end if;
disda_oen <= isda_oen;
end if;
end if;
end process gen_ald;
end block dfblock;
end generate dynamicfilt;
al <= ial;
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
detect_sta_sto: process(clk, nReset)
begin
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
if fSCL = "11" and fSDA = "10" then
sta_condition <= '1';
else
sta_condition <= '0';
end if;
if fSCL = "11" and fSDA = "01" then
sto_condition <= '1';
else
sto_condition <= '0';
end if;
end if;
end if;
end process detect_sta_sto;
-- generate i2c-bus busy signal
gen_busy: process(clk, nReset)
begin
if (nReset = '0') then
ibusy <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
ibusy <= '0';
else
ibusy <= (sta_condition or ibusy) and not sto_condition;
end if;
end if;
end process gen_busy;
busy <= ibusy;
-- generate dout signal, store dout on rising edge of SCL
gen_dout: process(clk)
begin
if (clk'event and clk = '1') then
if fSCL = "01" then
dout <= fSDA(1);
end if;
end if;
end process gen_dout;
end block bus_status_ctrl;
-- generate statemachine
nxt_state_decoder : process (clk, nReset, c_state, cmd)
begin
if (nReset = '0') then
c_state <= idle;
s_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or ial = '1') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif csync = '1' then
c_state <= s_state;
else
cmd_ack <= '0'; -- default no acknowledge
-- csync is always '0' here, but including it in the expression
-- appears to let some compilers optimize the design more...
if (clk_en or csync) = '1' then
case (c_state) is
-- idle
when idle =>
case cmd is
when I2C_CMD_START => c_state <= start_a;
s_state <= start_g;
when I2C_CMD_STOP => c_state <= stop_a;
s_state <= stop_d;
when I2C_CMD_WRITE => c_state <= wr_a;
s_state <= wr_d;
when I2C_CMD_READ => c_state <= rd_a;
s_state <= rd_d;
when others => c_state <= idle; -- NOP command
s_state <= idle;
end case;
iscl_oen <= iscl_oen; -- keep SCL in same state
isda_oen <= isda_oen; -- keep SDA in same state
sda_chk <= '0'; -- don't check SDA
-- start
when start_a =>
c_state <= start_b;
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
when start_b =>
c_state <= start_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_c =>
c_state <= start_d;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_d =>
c_state <= start_e;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_e =>
c_state <= start_f;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when start_f =>
c_state <= start_g;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when start_g =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
s_state <= idle;
-- stop
when stop_a =>
c_state <= stop_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when stop_b =>
c_state <= stop_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_c =>
c_state <= stop_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
s_state <= idle;
-- read
when rd_a =>
c_state <= rd_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_b =>
c_state <= rd_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_c =>
c_state <= rd_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
s_state <= idle;
-- write
when wr_a =>
c_state <= wr_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= din; -- set SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when wr_b =>
c_state <= wr_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (allow signals to settle)
when wr_c =>
c_state <= wr_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
s_state <= idle;
when others =>
end case;
end if;
end if;
end if;
end process nxt_state_decoder;
-- assign outputs
scl_o <= '0';
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
end architecture structural;
|
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11 12:10:13 rherveille Exp $
--
-- $Date: 2006/10/11 12:10:13 $
-- $Revision: 1.14 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_bit_ctrl.vhd,v $
-- Revision 1.14 2006/10/11 12:10:13 rherveille
-- Added missing semicolons ';' on endif
--
-- Revision 1.13 2006/10/06 10:48:24 rherveille
-- fixed short scl high pulse after clock stretch
--
-- Revision 1.12 2004/05/07 11:53:31 rherveille
-- Fixed previous fix :) Made a variable vs signal mistake.
--
-- Revision 1.11 2004/05/07 11:04:00 rherveille
-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
-- Revision 1.10 2004/02/27 07:49:43 rherveille
-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
-- Revision 1.9 2003/08/12 14:48:37 rherveille
-- Forgot an 'end if' :-/
--
-- Revision 1.8 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.7 2003/02/05 00:06:02 rherveille
-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
-- Revision 1.6 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.5 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.4 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.3 2002/10/30 18:09:53 rherveille
-- Fixed some reported minor start/stop generation timing issuess.
--
-- Revision 1.2 2002/06/15 07:37:04 rherveille
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
-- Modified by Jan Andersson ([email protected]):
--
-- * Added two start states to fulfill Set-up time for
-- repeated START condition.
-- * Modified synchronization of SCL and SDA. START and STOP detection
-- is now performed after a two stage synchronizer and is also
-- filtered.
-- * Changed evaluation order of 'slave_wait', 'en' and 'cnt' in
-- generation of clk_en signal to prevent clk_en assertion when
-- slave_wait is asserted.
-- * Needed to differentiate between slave clock stretching and master
-- clock synchronization.
-- * Added register s_state which contains the next state in case
-- of clock synchronization
-- * Incorporated change in wr_b state from SVN rev. 72 of
-- original OC version (delay check of SDA).
-- * Added 'filter' generic that determines length of filter.
-- Original OC core has a median filter implemented. The solution
-- implemented in this version is a plain shift register with a
-- length determined by the new generic. All samples in this
-- register must be equal, otherwise the SCL or SDA value used by
-- the core will not be changed. Every SCL/SDA transition that is
-- not stable for 'filter' system clock cycles is disregarded.
-- This solution is potentially more vulnerable against short
-- periods of relatively quick fluctuations on the line, however
-- it should do a better job of ignoring 50 ns pulses and still
-- allow us to respond quickly to events on the line - assuming
-- that the core has been correctly configured.
-- Core revision has been increased to 2 (in GRLIB PnP)
-- * Added 'dynfilt' generic to allow dynamic adjustment of the
-- filter. This component takes in a filt vector that is used to
-- reload a filter counter. The filt vector is assigned via the
-- core's APB interface.
-- Reorganized parts of the code, moving signals into blocks.
-- Core revision increased to 3.
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start: SCL ~~~~~~~~~~~~~~\____
-- SDA XX/~~~~~~~\______
-- x | A | B | C | D | i
--
-- repstart SCL ______/~~~~~~~\___
-- SDA __/~~~~~~~\______
-- x | A | B | C | D | i
--
-- stop SCL _______/~~~~~~~~~~~
-- SDA ==\___________/~~~~~
-- x | A | B | C | D | i
--
--- write SCL ______/~~~~~~~\____
-- SDA XXX===============XX
-- x | A | B | C | D | i
--
--- read SCL ______/~~~~~~~\____
-- SDA XXXXXXX=XXXXXXXXXXX
-- x | A | B | C | D | i
--
-- Timing: Normal mode Fast mode
-----------------------------------------------------------------
-- Fscl 100KHz 400KHz
-- Th_scl 4.0us 0.6us High period of SCL
-- Tl_scl 4.7us 1.3us Low period of SCL
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity i2c_master_bit_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command completed
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_bit_ctrl;
architecture structural of i2c_master_bit_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
type states is (idle, start_a, start_b, start_c, start_d, start_e, start_f, start_g,
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state, s_state : states;
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
signal fSCL, fSDA : std_logic_vector(1 downto 0); -- Filtered SCL and SDA inputs
signal clk_en, slave_wait : std_logic; -- clock generation signals
signal ial : std_logic; -- internal arbitration lost signal
signal cnt : std_logic_vector(15 downto 0); -- clock divider counter
signal csync : std_logic; -- Need to synchronize clock with other master
begin
-- generate clk enable signal
gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cnt <= (others => '0');
clk_en <= '1';
elsif (ena = '0' or csync = '1') then
cnt <= clk_cnt;
clk_en <= '1';
elsif (slave_wait = '1') then
cnt <= cnt;
clk_en <= '0';
elsif (cnt = X"0000") then
cnt <= clk_cnt;
clk_en <= '1';
else
cnt <= cnt -1;
clk_en <= '0';
end if;
end if;
end process gen_clken;
-- generate bus status controller
bus_status_ctrl: block
signal sta_condition : std_logic; -- start detected
signal sto_condition : std_logic; -- stop detected
signal cmd_stop : std_logic; -- STOP command
signal ibusy : std_logic; -- internal busy signal
signal slvw_dis : std_logic; -- Slave wait disable;
begin
-- Static filter
staticfilt : if dynfilt = 0 generate
sfblock : block
constant FR : integer := filter; -- Filter range MSb
constant DR : integer := filter + 1; -- Delayed SCL/SDA range MSb
signal sSCL, sSDA : std_logic_vector(FR downto 0); -- synchronized SCL and SDA inputs
signal discl_oen : std_logic_vector(DR downto 0); -- delayed scl_oen signal
signal disda_oen : std_logic_vector(DR downto 0); -- delayed isda_oen
begin
-- synchronize SCL and SDA inputs
synch_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
sSCL <= (others => '1');
sSDA <= (others => '1');
fSCL <= (others => '1');
fSDA <= (others => '1');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sSCL <= (others => '1');
sSDA <= (others => '1');
fSCL <= (others => '1');
fSDA <= (others => '1');
else
sSCL <= sSCL(FR-1 downto 0) & scl_i;
sSDA <= sSDA(FR-1 downto 0) & sda_i;
-- Filtering
if andv(sSCL(FR downto 1)) = '1' then
fSCL <= fSCL(0) & '1';
elsif orv(sSCL(FR downto 1)) = '0' then
fSCL <= fSCL(0) & '0';
else
fSCL <= fSCL;
end if;
if andv(sSDA(FR downto 1)) = '1' then
fSDA <= fSDA(0) & '1';
elsif orv(sSDA(FR downto 1)) = '0' then
fSDA <= fSDA(0) & '0';
else
fSDA <= fSDA;
end if;
end if;
end if;
end process synch_SCL_SDA;
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk)
begin
if (clk'event and clk = '1') then
if rst = '1' then
discl_oen <= (others => '1');
slvw_dis <= '0';
else
-- Keep SCL output enable values
discl_oen <= discl_oen(DR-1 downto 0) & iscl_oen;
-- Disable slave stretch detection when other device drives SCL
-- H->L (only a master should to this).
slvw_dis <= (slvw_dis or csync) and discl_oen(0);
end if;
end if;
end process;
-- SCL forced low after master tried to assert, slave is stretching clock
slave_wait <= andv(discl_oen(DR downto 1)) and not fSCL(0) and not (slvw_dis or fSCL(1));
-- SCL HIGH time cut short, master clock synchronization
csync <= andv(discl_oen(DR downto 1)) and not fSCL(0) and fSCL(1);
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_al: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= (others => '1');
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= (others => '1');
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not fSDA(0) and disda_oen(DR));
else
ial <= (sda_chk and not fSDA(0) and disda_oen(DR)) or
(sto_condition and not cmd_stop);
end if;
end if;
disda_oen <= disda_oen(DR-1 downto 0) & isda_oen;
end if;
end process gen_al;
end block sfblock;
end generate staticfilt;
-- Dynamic filter
dynamicfilt : if dynfilt /= 0 generate
-- Fixed window
dfblock : block
signal filtcnt : std_logic_vector(filter-1 downto 0);
signal sSCL, sSDA : std_logic_vector(1 downto 0); -- synchronized SCL and SDA inputs
signal fiscl_oen : std_logic_vector(1 downto 0); -- "filtered" scl_oen signal
signal fisda_oen : std_ulogic; -- "filtered" sda_oen signal
signal fSCL_chg, fSDA_chg, fiscl_oen_chg, fisda_oen_chg : std_ulogic;
signal discl_oen : std_ulogic; -- delayed scl_oen signal
signal disda_oen : std_ulogic; -- delayed sda_oen signal
begin
-- Provides filtered signals for SCL and SDA, and corresponding
-- output enable signals.
sync_scl_sda: process(clk, nReset, fSCL_chg, fSDA_chg, fiscl_oen_chg, fisda_oen_chg)
variable scl_chg, sda_chg, iscl_oen_chg, isda_oen_chg : std_ulogic;
begin
--scl_chg := fSCL_chg; sda_chg := fSDA_chg;
--iscl_oen_chg := fiscl_oen_chg; isda_oen_chg := fisda_oen_chg;
if (nReset = '0') then
scl_chg := fSCL_chg; sda_chg := fSDA_chg;
iscl_oen_chg := fiscl_oen_chg; isda_oen_chg := fisda_oen_chg;
filtcnt <= (others => '0');
fSCL <= (others => '1'); fSDA <= (others => '1');
fSCL_chg <= '0'; fSDA_chg <= '0';
fiscl_oen <= (others => '1'); fiscl_oen_chg <= '0';
fisda_oen <= '1'; fisda_oen_chg <= '0';
elsif (clk'event and clk = '1') then
scl_chg := fSCL_chg; sda_chg := fSDA_chg;
iscl_oen_chg := fiscl_oen_chg; isda_oen_chg := fisda_oen_chg;
if (rst = '1') or (ena = '0') then
filtcnt <= (others => '0');
fSCL <= (others => '1'); fSDA <= (others => '1');
fSCL_chg <= '0'; fSDA_chg <= '0';
fiscl_oen <= (others => '1'); fiscl_oen_chg <= '0';
fisda_oen <= '1'; fisda_oen_chg <= '0';
else
if (sSCL(1) xor fSCL(0)) = '0' then scl_chg := '0'; end if;
if (sSDA(1) xor fSDA(0)) = '0' then sda_chg := '0'; end if;
if (discl_oen xor fiscl_oen(0)) = '0' then iscl_oen_chg := '0'; end if;
if (disda_oen xor fisda_oen) = '0' then isda_oen_chg := '0'; end if;
if filtcnt = zero32((filter-1)*dynfilt downto 0) then
filtcnt <= filt;
fSCL <= fSCL(0) & (fSCL(0) xor scl_chg);
fSDA <= fSDA(0) & (fSDA(0) xor sda_chg);
fSCL_chg <= '1'; fSDA_chg <= '1';
fiscl_oen <= fiscl_oen(0) & (fiscl_oen(0) xor iscl_oen_chg);
fiscl_oen_chg <= '1';
fisda_oen <= fisda_oen xor isda_oen_chg;
fisda_oen_chg <= '1';
else
filtcnt <= filtcnt - 1;
fSDA <= fSDA; fSCL <= fSCL;
fSCL_chg <= scl_chg; fSDA_chg <= sda_chg;
fiscl_oen <= fiscl_oen;
fiscl_oen_chg <= iscl_oen_chg;
fisda_oen <= fisda_oen;
fisda_oen_chg <= isda_oen_chg;
end if;
end if;
sSCL <= sSCL(0) & scl_i;
sSDA <= sSDA(0) & sda_i;
end if;
end process sync_SCL_SDA;
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk)
begin
if (clk'event and clk = '1') then
if rst = '1' then
discl_oen <= '1';
slvw_dis <= '0';
else
-- Keep SCL output enable values
discl_oen <= iscl_oen;
-- Disable slave stretch detection when other device drives SCL
-- H->L (only a master should to this).
slvw_dis <= (slvw_dis or csync) and discl_oen;
end if;
end if;
end process;
-- SCL forced low after master tried to assert, slave is stretching clock
slave_wait <= andv(fiscl_oen) and not fSCL(0) and not (slvw_dis or fSCL(1));
-- SCL HIGH time cut short, master clock synchronization
csync <= andv(fiscl_oen) and not fSCL(0) and fSCL(1);
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_ald: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= '1';
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not fSDA(0) and fisda_oen);
else
ial <= (sda_chk and not fSDA(0) and fisda_oen) or
(sto_condition and not cmd_stop);
end if;
disda_oen <= isda_oen;
end if;
end if;
end process gen_ald;
end block dfblock;
end generate dynamicfilt;
al <= ial;
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
detect_sta_sto: process(clk, nReset)
begin
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
if fSCL = "11" and fSDA = "10" then
sta_condition <= '1';
else
sta_condition <= '0';
end if;
if fSCL = "11" and fSDA = "01" then
sto_condition <= '1';
else
sto_condition <= '0';
end if;
end if;
end if;
end process detect_sta_sto;
-- generate i2c-bus busy signal
gen_busy: process(clk, nReset)
begin
if (nReset = '0') then
ibusy <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
ibusy <= '0';
else
ibusy <= (sta_condition or ibusy) and not sto_condition;
end if;
end if;
end process gen_busy;
busy <= ibusy;
-- generate dout signal, store dout on rising edge of SCL
gen_dout: process(clk)
begin
if (clk'event and clk = '1') then
if fSCL = "01" then
dout <= fSDA(1);
end if;
end if;
end process gen_dout;
end block bus_status_ctrl;
-- generate statemachine
nxt_state_decoder : process (clk, nReset, c_state, cmd)
begin
if (nReset = '0') then
c_state <= idle;
s_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or ial = '1') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif csync = '1' then
c_state <= s_state;
else
cmd_ack <= '0'; -- default no acknowledge
-- csync is always '0' here, but including it in the expression
-- appears to let some compilers optimize the design more...
if (clk_en or csync) = '1' then
case (c_state) is
-- idle
when idle =>
case cmd is
when I2C_CMD_START => c_state <= start_a;
s_state <= start_g;
when I2C_CMD_STOP => c_state <= stop_a;
s_state <= stop_d;
when I2C_CMD_WRITE => c_state <= wr_a;
s_state <= wr_d;
when I2C_CMD_READ => c_state <= rd_a;
s_state <= rd_d;
when others => c_state <= idle; -- NOP command
s_state <= idle;
end case;
iscl_oen <= iscl_oen; -- keep SCL in same state
isda_oen <= isda_oen; -- keep SDA in same state
sda_chk <= '0'; -- don't check SDA
-- start
when start_a =>
c_state <= start_b;
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
when start_b =>
c_state <= start_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_c =>
c_state <= start_d;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_d =>
c_state <= start_e;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_e =>
c_state <= start_f;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when start_f =>
c_state <= start_g;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when start_g =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
s_state <= idle;
-- stop
when stop_a =>
c_state <= stop_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when stop_b =>
c_state <= stop_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_c =>
c_state <= stop_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
s_state <= idle;
-- read
when rd_a =>
c_state <= rd_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_b =>
c_state <= rd_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_c =>
c_state <= rd_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
s_state <= idle;
-- write
when wr_a =>
c_state <= wr_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= din; -- set SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when wr_b =>
c_state <= wr_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (allow signals to settle)
when wr_c =>
c_state <= wr_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
s_state <= idle;
when others =>
end case;
end if;
end if;
end if;
end process nxt_state_decoder;
-- assign outputs
scl_o <= '0';
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
end architecture structural;
|
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11 12:10:13 rherveille Exp $
--
-- $Date: 2006/10/11 12:10:13 $
-- $Revision: 1.14 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_bit_ctrl.vhd,v $
-- Revision 1.14 2006/10/11 12:10:13 rherveille
-- Added missing semicolons ';' on endif
--
-- Revision 1.13 2006/10/06 10:48:24 rherveille
-- fixed short scl high pulse after clock stretch
--
-- Revision 1.12 2004/05/07 11:53:31 rherveille
-- Fixed previous fix :) Made a variable vs signal mistake.
--
-- Revision 1.11 2004/05/07 11:04:00 rherveille
-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
-- Revision 1.10 2004/02/27 07:49:43 rherveille
-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
-- Revision 1.9 2003/08/12 14:48:37 rherveille
-- Forgot an 'end if' :-/
--
-- Revision 1.8 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.7 2003/02/05 00:06:02 rherveille
-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
-- Revision 1.6 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.5 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.4 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.3 2002/10/30 18:09:53 rherveille
-- Fixed some reported minor start/stop generation timing issuess.
--
-- Revision 1.2 2002/06/15 07:37:04 rherveille
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
-- Modified by Jan Andersson ([email protected]):
--
-- * Added two start states to fulfill Set-up time for
-- repeated START condition.
-- * Modified synchronization of SCL and SDA. START and STOP detection
-- is now performed after a two stage synchronizer and is also
-- filtered.
-- * Changed evaluation order of 'slave_wait', 'en' and 'cnt' in
-- generation of clk_en signal to prevent clk_en assertion when
-- slave_wait is asserted.
-- * Needed to differentiate between slave clock stretching and master
-- clock synchronization.
-- * Added register s_state which contains the next state in case
-- of clock synchronization
-- * Incorporated change in wr_b state from SVN rev. 72 of
-- original OC version (delay check of SDA).
-- * Added 'filter' generic that determines length of filter.
-- Original OC core has a median filter implemented. The solution
-- implemented in this version is a plain shift register with a
-- length determined by the new generic. All samples in this
-- register must be equal, otherwise the SCL or SDA value used by
-- the core will not be changed. Every SCL/SDA transition that is
-- not stable for 'filter' system clock cycles is disregarded.
-- This solution is potentially more vulnerable against short
-- periods of relatively quick fluctuations on the line, however
-- it should do a better job of ignoring 50 ns pulses and still
-- allow us to respond quickly to events on the line - assuming
-- that the core has been correctly configured.
-- Core revision has been increased to 2 (in GRLIB PnP)
-- * Added 'dynfilt' generic to allow dynamic adjustment of the
-- filter. This component takes in a filt vector that is used to
-- reload a filter counter. The filt vector is assigned via the
-- core's APB interface.
-- Reorganized parts of the code, moving signals into blocks.
-- Core revision increased to 3.
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start: SCL ~~~~~~~~~~~~~~\____
-- SDA XX/~~~~~~~\______
-- x | A | B | C | D | i
--
-- repstart SCL ______/~~~~~~~\___
-- SDA __/~~~~~~~\______
-- x | A | B | C | D | i
--
-- stop SCL _______/~~~~~~~~~~~
-- SDA ==\___________/~~~~~
-- x | A | B | C | D | i
--
--- write SCL ______/~~~~~~~\____
-- SDA XXX===============XX
-- x | A | B | C | D | i
--
--- read SCL ______/~~~~~~~\____
-- SDA XXXXXXX=XXXXXXXXXXX
-- x | A | B | C | D | i
--
-- Timing: Normal mode Fast mode
-----------------------------------------------------------------
-- Fscl 100KHz 400KHz
-- Th_scl 4.0us 0.6us High period of SCL
-- Tl_scl 4.7us 1.3us Low period of SCL
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity i2c_master_bit_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command completed
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_bit_ctrl;
architecture structural of i2c_master_bit_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
type states is (idle, start_a, start_b, start_c, start_d, start_e, start_f, start_g,
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state, s_state : states;
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
signal fSCL, fSDA : std_logic_vector(1 downto 0); -- Filtered SCL and SDA inputs
signal clk_en, slave_wait : std_logic; -- clock generation signals
signal ial : std_logic; -- internal arbitration lost signal
signal cnt : std_logic_vector(15 downto 0); -- clock divider counter
signal csync : std_logic; -- Need to synchronize clock with other master
begin
-- generate clk enable signal
gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cnt <= (others => '0');
clk_en <= '1';
elsif (ena = '0' or csync = '1') then
cnt <= clk_cnt;
clk_en <= '1';
elsif (slave_wait = '1') then
cnt <= cnt;
clk_en <= '0';
elsif (cnt = X"0000") then
cnt <= clk_cnt;
clk_en <= '1';
else
cnt <= cnt -1;
clk_en <= '0';
end if;
end if;
end process gen_clken;
-- generate bus status controller
bus_status_ctrl: block
signal sta_condition : std_logic; -- start detected
signal sto_condition : std_logic; -- stop detected
signal cmd_stop : std_logic; -- STOP command
signal ibusy : std_logic; -- internal busy signal
signal slvw_dis : std_logic; -- Slave wait disable;
begin
-- Static filter
staticfilt : if dynfilt = 0 generate
sfblock : block
constant FR : integer := filter; -- Filter range MSb
constant DR : integer := filter + 1; -- Delayed SCL/SDA range MSb
signal sSCL, sSDA : std_logic_vector(FR downto 0); -- synchronized SCL and SDA inputs
signal discl_oen : std_logic_vector(DR downto 0); -- delayed scl_oen signal
signal disda_oen : std_logic_vector(DR downto 0); -- delayed isda_oen
begin
-- synchronize SCL and SDA inputs
synch_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
sSCL <= (others => '1');
sSDA <= (others => '1');
fSCL <= (others => '1');
fSDA <= (others => '1');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sSCL <= (others => '1');
sSDA <= (others => '1');
fSCL <= (others => '1');
fSDA <= (others => '1');
else
sSCL <= sSCL(FR-1 downto 0) & scl_i;
sSDA <= sSDA(FR-1 downto 0) & sda_i;
-- Filtering
if andv(sSCL(FR downto 1)) = '1' then
fSCL <= fSCL(0) & '1';
elsif orv(sSCL(FR downto 1)) = '0' then
fSCL <= fSCL(0) & '0';
else
fSCL <= fSCL;
end if;
if andv(sSDA(FR downto 1)) = '1' then
fSDA <= fSDA(0) & '1';
elsif orv(sSDA(FR downto 1)) = '0' then
fSDA <= fSDA(0) & '0';
else
fSDA <= fSDA;
end if;
end if;
end if;
end process synch_SCL_SDA;
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk)
begin
if (clk'event and clk = '1') then
if rst = '1' then
discl_oen <= (others => '1');
slvw_dis <= '0';
else
-- Keep SCL output enable values
discl_oen <= discl_oen(DR-1 downto 0) & iscl_oen;
-- Disable slave stretch detection when other device drives SCL
-- H->L (only a master should to this).
slvw_dis <= (slvw_dis or csync) and discl_oen(0);
end if;
end if;
end process;
-- SCL forced low after master tried to assert, slave is stretching clock
slave_wait <= andv(discl_oen(DR downto 1)) and not fSCL(0) and not (slvw_dis or fSCL(1));
-- SCL HIGH time cut short, master clock synchronization
csync <= andv(discl_oen(DR downto 1)) and not fSCL(0) and fSCL(1);
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_al: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= (others => '1');
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= (others => '1');
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not fSDA(0) and disda_oen(DR));
else
ial <= (sda_chk and not fSDA(0) and disda_oen(DR)) or
(sto_condition and not cmd_stop);
end if;
end if;
disda_oen <= disda_oen(DR-1 downto 0) & isda_oen;
end if;
end process gen_al;
end block sfblock;
end generate staticfilt;
-- Dynamic filter
dynamicfilt : if dynfilt /= 0 generate
-- Fixed window
dfblock : block
signal filtcnt : std_logic_vector(filter-1 downto 0);
signal sSCL, sSDA : std_logic_vector(1 downto 0); -- synchronized SCL and SDA inputs
signal fiscl_oen : std_logic_vector(1 downto 0); -- "filtered" scl_oen signal
signal fisda_oen : std_ulogic; -- "filtered" sda_oen signal
signal fSCL_chg, fSDA_chg, fiscl_oen_chg, fisda_oen_chg : std_ulogic;
signal discl_oen : std_ulogic; -- delayed scl_oen signal
signal disda_oen : std_ulogic; -- delayed sda_oen signal
begin
-- Provides filtered signals for SCL and SDA, and corresponding
-- output enable signals.
sync_scl_sda: process(clk, nReset, fSCL_chg, fSDA_chg, fiscl_oen_chg, fisda_oen_chg)
variable scl_chg, sda_chg, iscl_oen_chg, isda_oen_chg : std_ulogic;
begin
--scl_chg := fSCL_chg; sda_chg := fSDA_chg;
--iscl_oen_chg := fiscl_oen_chg; isda_oen_chg := fisda_oen_chg;
if (nReset = '0') then
scl_chg := fSCL_chg; sda_chg := fSDA_chg;
iscl_oen_chg := fiscl_oen_chg; isda_oen_chg := fisda_oen_chg;
filtcnt <= (others => '0');
fSCL <= (others => '1'); fSDA <= (others => '1');
fSCL_chg <= '0'; fSDA_chg <= '0';
fiscl_oen <= (others => '1'); fiscl_oen_chg <= '0';
fisda_oen <= '1'; fisda_oen_chg <= '0';
elsif (clk'event and clk = '1') then
scl_chg := fSCL_chg; sda_chg := fSDA_chg;
iscl_oen_chg := fiscl_oen_chg; isda_oen_chg := fisda_oen_chg;
if (rst = '1') or (ena = '0') then
filtcnt <= (others => '0');
fSCL <= (others => '1'); fSDA <= (others => '1');
fSCL_chg <= '0'; fSDA_chg <= '0';
fiscl_oen <= (others => '1'); fiscl_oen_chg <= '0';
fisda_oen <= '1'; fisda_oen_chg <= '0';
else
if (sSCL(1) xor fSCL(0)) = '0' then scl_chg := '0'; end if;
if (sSDA(1) xor fSDA(0)) = '0' then sda_chg := '0'; end if;
if (discl_oen xor fiscl_oen(0)) = '0' then iscl_oen_chg := '0'; end if;
if (disda_oen xor fisda_oen) = '0' then isda_oen_chg := '0'; end if;
if filtcnt = zero32((filter-1)*dynfilt downto 0) then
filtcnt <= filt;
fSCL <= fSCL(0) & (fSCL(0) xor scl_chg);
fSDA <= fSDA(0) & (fSDA(0) xor sda_chg);
fSCL_chg <= '1'; fSDA_chg <= '1';
fiscl_oen <= fiscl_oen(0) & (fiscl_oen(0) xor iscl_oen_chg);
fiscl_oen_chg <= '1';
fisda_oen <= fisda_oen xor isda_oen_chg;
fisda_oen_chg <= '1';
else
filtcnt <= filtcnt - 1;
fSDA <= fSDA; fSCL <= fSCL;
fSCL_chg <= scl_chg; fSDA_chg <= sda_chg;
fiscl_oen <= fiscl_oen;
fiscl_oen_chg <= iscl_oen_chg;
fisda_oen <= fisda_oen;
fisda_oen_chg <= isda_oen_chg;
end if;
end if;
sSCL <= sSCL(0) & scl_i;
sSDA <= sSDA(0) & sda_i;
end if;
end process sync_SCL_SDA;
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk)
begin
if (clk'event and clk = '1') then
if rst = '1' then
discl_oen <= '1';
slvw_dis <= '0';
else
-- Keep SCL output enable values
discl_oen <= iscl_oen;
-- Disable slave stretch detection when other device drives SCL
-- H->L (only a master should to this).
slvw_dis <= (slvw_dis or csync) and discl_oen;
end if;
end if;
end process;
-- SCL forced low after master tried to assert, slave is stretching clock
slave_wait <= andv(fiscl_oen) and not fSCL(0) and not (slvw_dis or fSCL(1));
-- SCL HIGH time cut short, master clock synchronization
csync <= andv(fiscl_oen) and not fSCL(0) and fSCL(1);
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_ald: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= '1';
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not fSDA(0) and fisda_oen);
else
ial <= (sda_chk and not fSDA(0) and fisda_oen) or
(sto_condition and not cmd_stop);
end if;
disda_oen <= isda_oen;
end if;
end if;
end process gen_ald;
end block dfblock;
end generate dynamicfilt;
al <= ial;
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
detect_sta_sto: process(clk, nReset)
begin
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
if fSCL = "11" and fSDA = "10" then
sta_condition <= '1';
else
sta_condition <= '0';
end if;
if fSCL = "11" and fSDA = "01" then
sto_condition <= '1';
else
sto_condition <= '0';
end if;
end if;
end if;
end process detect_sta_sto;
-- generate i2c-bus busy signal
gen_busy: process(clk, nReset)
begin
if (nReset = '0') then
ibusy <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
ibusy <= '0';
else
ibusy <= (sta_condition or ibusy) and not sto_condition;
end if;
end if;
end process gen_busy;
busy <= ibusy;
-- generate dout signal, store dout on rising edge of SCL
gen_dout: process(clk)
begin
if (clk'event and clk = '1') then
if fSCL = "01" then
dout <= fSDA(1);
end if;
end if;
end process gen_dout;
end block bus_status_ctrl;
-- generate statemachine
nxt_state_decoder : process (clk, nReset, c_state, cmd)
begin
if (nReset = '0') then
c_state <= idle;
s_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or ial = '1') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif csync = '1' then
c_state <= s_state;
else
cmd_ack <= '0'; -- default no acknowledge
-- csync is always '0' here, but including it in the expression
-- appears to let some compilers optimize the design more...
if (clk_en or csync) = '1' then
case (c_state) is
-- idle
when idle =>
case cmd is
when I2C_CMD_START => c_state <= start_a;
s_state <= start_g;
when I2C_CMD_STOP => c_state <= stop_a;
s_state <= stop_d;
when I2C_CMD_WRITE => c_state <= wr_a;
s_state <= wr_d;
when I2C_CMD_READ => c_state <= rd_a;
s_state <= rd_d;
when others => c_state <= idle; -- NOP command
s_state <= idle;
end case;
iscl_oen <= iscl_oen; -- keep SCL in same state
isda_oen <= isda_oen; -- keep SDA in same state
sda_chk <= '0'; -- don't check SDA
-- start
when start_a =>
c_state <= start_b;
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
when start_b =>
c_state <= start_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_c =>
c_state <= start_d;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_d =>
c_state <= start_e;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_e =>
c_state <= start_f;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when start_f =>
c_state <= start_g;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when start_g =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
s_state <= idle;
-- stop
when stop_a =>
c_state <= stop_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when stop_b =>
c_state <= stop_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_c =>
c_state <= stop_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
s_state <= idle;
-- read
when rd_a =>
c_state <= rd_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_b =>
c_state <= rd_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_c =>
c_state <= rd_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
s_state <= idle;
-- write
when wr_a =>
c_state <= wr_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= din; -- set SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when wr_b =>
c_state <= wr_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (allow signals to settle)
when wr_c =>
c_state <= wr_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
s_state <= idle;
when others =>
end case;
end if;
end if;
end if;
end process nxt_state_decoder;
-- assign outputs
scl_o <= '0';
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
end architecture structural;
|
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11 12:10:13 rherveille Exp $
--
-- $Date: 2006/10/11 12:10:13 $
-- $Revision: 1.14 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_bit_ctrl.vhd,v $
-- Revision 1.14 2006/10/11 12:10:13 rherveille
-- Added missing semicolons ';' on endif
--
-- Revision 1.13 2006/10/06 10:48:24 rherveille
-- fixed short scl high pulse after clock stretch
--
-- Revision 1.12 2004/05/07 11:53:31 rherveille
-- Fixed previous fix :) Made a variable vs signal mistake.
--
-- Revision 1.11 2004/05/07 11:04:00 rherveille
-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
-- Revision 1.10 2004/02/27 07:49:43 rherveille
-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
-- Revision 1.9 2003/08/12 14:48:37 rherveille
-- Forgot an 'end if' :-/
--
-- Revision 1.8 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.7 2003/02/05 00:06:02 rherveille
-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
-- Revision 1.6 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.5 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.4 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.3 2002/10/30 18:09:53 rherveille
-- Fixed some reported minor start/stop generation timing issuess.
--
-- Revision 1.2 2002/06/15 07:37:04 rherveille
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
-- Modified by Jan Andersson ([email protected]):
--
-- * Added two start states to fulfill Set-up time for
-- repeated START condition.
-- * Modified synchronization of SCL and SDA. START and STOP detection
-- is now performed after a two stage synchronizer and is also
-- filtered.
-- * Changed evaluation order of 'slave_wait', 'en' and 'cnt' in
-- generation of clk_en signal to prevent clk_en assertion when
-- slave_wait is asserted.
-- * Needed to differentiate between slave clock stretching and master
-- clock synchronization.
-- * Added register s_state which contains the next state in case
-- of clock synchronization
-- * Incorporated change in wr_b state from SVN rev. 72 of
-- original OC version (delay check of SDA).
-- * Added 'filter' generic that determines length of filter.
-- Original OC core has a median filter implemented. The solution
-- implemented in this version is a plain shift register with a
-- length determined by the new generic. All samples in this
-- register must be equal, otherwise the SCL or SDA value used by
-- the core will not be changed. Every SCL/SDA transition that is
-- not stable for 'filter' system clock cycles is disregarded.
-- This solution is potentially more vulnerable against short
-- periods of relatively quick fluctuations on the line, however
-- it should do a better job of ignoring 50 ns pulses and still
-- allow us to respond quickly to events on the line - assuming
-- that the core has been correctly configured.
-- Core revision has been increased to 2 (in GRLIB PnP)
-- * Added 'dynfilt' generic to allow dynamic adjustment of the
-- filter. This component takes in a filt vector that is used to
-- reload a filter counter. The filt vector is assigned via the
-- core's APB interface.
-- Reorganized parts of the code, moving signals into blocks.
-- Core revision increased to 3.
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start: SCL ~~~~~~~~~~~~~~\____
-- SDA XX/~~~~~~~\______
-- x | A | B | C | D | i
--
-- repstart SCL ______/~~~~~~~\___
-- SDA __/~~~~~~~\______
-- x | A | B | C | D | i
--
-- stop SCL _______/~~~~~~~~~~~
-- SDA ==\___________/~~~~~
-- x | A | B | C | D | i
--
--- write SCL ______/~~~~~~~\____
-- SDA XXX===============XX
-- x | A | B | C | D | i
--
--- read SCL ______/~~~~~~~\____
-- SDA XXXXXXX=XXXXXXXXXXX
-- x | A | B | C | D | i
--
-- Timing: Normal mode Fast mode
-----------------------------------------------------------------
-- Fscl 100KHz 400KHz
-- Th_scl 4.0us 0.6us High period of SCL
-- Tl_scl 4.7us 1.3us Low period of SCL
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity i2c_master_bit_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command completed
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_bit_ctrl;
architecture structural of i2c_master_bit_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
type states is (idle, start_a, start_b, start_c, start_d, start_e, start_f, start_g,
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state, s_state : states;
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
signal fSCL, fSDA : std_logic_vector(1 downto 0); -- Filtered SCL and SDA inputs
signal clk_en, slave_wait : std_logic; -- clock generation signals
signal ial : std_logic; -- internal arbitration lost signal
signal cnt : std_logic_vector(15 downto 0); -- clock divider counter
signal csync : std_logic; -- Need to synchronize clock with other master
begin
-- generate clk enable signal
gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cnt <= (others => '0');
clk_en <= '1';
elsif (ena = '0' or csync = '1') then
cnt <= clk_cnt;
clk_en <= '1';
elsif (slave_wait = '1') then
cnt <= cnt;
clk_en <= '0';
elsif (cnt = X"0000") then
cnt <= clk_cnt;
clk_en <= '1';
else
cnt <= cnt -1;
clk_en <= '0';
end if;
end if;
end process gen_clken;
-- generate bus status controller
bus_status_ctrl: block
signal sta_condition : std_logic; -- start detected
signal sto_condition : std_logic; -- stop detected
signal cmd_stop : std_logic; -- STOP command
signal ibusy : std_logic; -- internal busy signal
signal slvw_dis : std_logic; -- Slave wait disable;
begin
-- Static filter
staticfilt : if dynfilt = 0 generate
sfblock : block
constant FR : integer := filter; -- Filter range MSb
constant DR : integer := filter + 1; -- Delayed SCL/SDA range MSb
signal sSCL, sSDA : std_logic_vector(FR downto 0); -- synchronized SCL and SDA inputs
signal discl_oen : std_logic_vector(DR downto 0); -- delayed scl_oen signal
signal disda_oen : std_logic_vector(DR downto 0); -- delayed isda_oen
begin
-- synchronize SCL and SDA inputs
synch_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
sSCL <= (others => '1');
sSDA <= (others => '1');
fSCL <= (others => '1');
fSDA <= (others => '1');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sSCL <= (others => '1');
sSDA <= (others => '1');
fSCL <= (others => '1');
fSDA <= (others => '1');
else
sSCL <= sSCL(FR-1 downto 0) & scl_i;
sSDA <= sSDA(FR-1 downto 0) & sda_i;
-- Filtering
if andv(sSCL(FR downto 1)) = '1' then
fSCL <= fSCL(0) & '1';
elsif orv(sSCL(FR downto 1)) = '0' then
fSCL <= fSCL(0) & '0';
else
fSCL <= fSCL;
end if;
if andv(sSDA(FR downto 1)) = '1' then
fSDA <= fSDA(0) & '1';
elsif orv(sSDA(FR downto 1)) = '0' then
fSDA <= fSDA(0) & '0';
else
fSDA <= fSDA;
end if;
end if;
end if;
end process synch_SCL_SDA;
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk)
begin
if (clk'event and clk = '1') then
if rst = '1' then
discl_oen <= (others => '1');
slvw_dis <= '0';
else
-- Keep SCL output enable values
discl_oen <= discl_oen(DR-1 downto 0) & iscl_oen;
-- Disable slave stretch detection when other device drives SCL
-- H->L (only a master should to this).
slvw_dis <= (slvw_dis or csync) and discl_oen(0);
end if;
end if;
end process;
-- SCL forced low after master tried to assert, slave is stretching clock
slave_wait <= andv(discl_oen(DR downto 1)) and not fSCL(0) and not (slvw_dis or fSCL(1));
-- SCL HIGH time cut short, master clock synchronization
csync <= andv(discl_oen(DR downto 1)) and not fSCL(0) and fSCL(1);
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_al: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= (others => '1');
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= (others => '1');
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not fSDA(0) and disda_oen(DR));
else
ial <= (sda_chk and not fSDA(0) and disda_oen(DR)) or
(sto_condition and not cmd_stop);
end if;
end if;
disda_oen <= disda_oen(DR-1 downto 0) & isda_oen;
end if;
end process gen_al;
end block sfblock;
end generate staticfilt;
-- Dynamic filter
dynamicfilt : if dynfilt /= 0 generate
-- Fixed window
dfblock : block
signal filtcnt : std_logic_vector(filter-1 downto 0);
signal sSCL, sSDA : std_logic_vector(1 downto 0); -- synchronized SCL and SDA inputs
signal fiscl_oen : std_logic_vector(1 downto 0); -- "filtered" scl_oen signal
signal fisda_oen : std_ulogic; -- "filtered" sda_oen signal
signal fSCL_chg, fSDA_chg, fiscl_oen_chg, fisda_oen_chg : std_ulogic;
signal discl_oen : std_ulogic; -- delayed scl_oen signal
signal disda_oen : std_ulogic; -- delayed sda_oen signal
begin
-- Provides filtered signals for SCL and SDA, and corresponding
-- output enable signals.
sync_scl_sda: process(clk, nReset, fSCL_chg, fSDA_chg, fiscl_oen_chg, fisda_oen_chg)
variable scl_chg, sda_chg, iscl_oen_chg, isda_oen_chg : std_ulogic;
begin
--scl_chg := fSCL_chg; sda_chg := fSDA_chg;
--iscl_oen_chg := fiscl_oen_chg; isda_oen_chg := fisda_oen_chg;
if (nReset = '0') then
scl_chg := fSCL_chg; sda_chg := fSDA_chg;
iscl_oen_chg := fiscl_oen_chg; isda_oen_chg := fisda_oen_chg;
filtcnt <= (others => '0');
fSCL <= (others => '1'); fSDA <= (others => '1');
fSCL_chg <= '0'; fSDA_chg <= '0';
fiscl_oen <= (others => '1'); fiscl_oen_chg <= '0';
fisda_oen <= '1'; fisda_oen_chg <= '0';
elsif (clk'event and clk = '1') then
scl_chg := fSCL_chg; sda_chg := fSDA_chg;
iscl_oen_chg := fiscl_oen_chg; isda_oen_chg := fisda_oen_chg;
if (rst = '1') or (ena = '0') then
filtcnt <= (others => '0');
fSCL <= (others => '1'); fSDA <= (others => '1');
fSCL_chg <= '0'; fSDA_chg <= '0';
fiscl_oen <= (others => '1'); fiscl_oen_chg <= '0';
fisda_oen <= '1'; fisda_oen_chg <= '0';
else
if (sSCL(1) xor fSCL(0)) = '0' then scl_chg := '0'; end if;
if (sSDA(1) xor fSDA(0)) = '0' then sda_chg := '0'; end if;
if (discl_oen xor fiscl_oen(0)) = '0' then iscl_oen_chg := '0'; end if;
if (disda_oen xor fisda_oen) = '0' then isda_oen_chg := '0'; end if;
if filtcnt = zero32((filter-1)*dynfilt downto 0) then
filtcnt <= filt;
fSCL <= fSCL(0) & (fSCL(0) xor scl_chg);
fSDA <= fSDA(0) & (fSDA(0) xor sda_chg);
fSCL_chg <= '1'; fSDA_chg <= '1';
fiscl_oen <= fiscl_oen(0) & (fiscl_oen(0) xor iscl_oen_chg);
fiscl_oen_chg <= '1';
fisda_oen <= fisda_oen xor isda_oen_chg;
fisda_oen_chg <= '1';
else
filtcnt <= filtcnt - 1;
fSDA <= fSDA; fSCL <= fSCL;
fSCL_chg <= scl_chg; fSDA_chg <= sda_chg;
fiscl_oen <= fiscl_oen;
fiscl_oen_chg <= iscl_oen_chg;
fisda_oen <= fisda_oen;
fisda_oen_chg <= isda_oen_chg;
end if;
end if;
sSCL <= sSCL(0) & scl_i;
sSDA <= sSDA(0) & sda_i;
end if;
end process sync_SCL_SDA;
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk)
begin
if (clk'event and clk = '1') then
if rst = '1' then
discl_oen <= '1';
slvw_dis <= '0';
else
-- Keep SCL output enable values
discl_oen <= iscl_oen;
-- Disable slave stretch detection when other device drives SCL
-- H->L (only a master should to this).
slvw_dis <= (slvw_dis or csync) and discl_oen;
end if;
end if;
end process;
-- SCL forced low after master tried to assert, slave is stretching clock
slave_wait <= andv(fiscl_oen) and not fSCL(0) and not (slvw_dis or fSCL(1));
-- SCL HIGH time cut short, master clock synchronization
csync <= andv(fiscl_oen) and not fSCL(0) and fSCL(1);
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_ald: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= '1';
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not fSDA(0) and fisda_oen);
else
ial <= (sda_chk and not fSDA(0) and fisda_oen) or
(sto_condition and not cmd_stop);
end if;
disda_oen <= isda_oen;
end if;
end if;
end process gen_ald;
end block dfblock;
end generate dynamicfilt;
al <= ial;
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
detect_sta_sto: process(clk, nReset)
begin
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
if fSCL = "11" and fSDA = "10" then
sta_condition <= '1';
else
sta_condition <= '0';
end if;
if fSCL = "11" and fSDA = "01" then
sto_condition <= '1';
else
sto_condition <= '0';
end if;
end if;
end if;
end process detect_sta_sto;
-- generate i2c-bus busy signal
gen_busy: process(clk, nReset)
begin
if (nReset = '0') then
ibusy <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
ibusy <= '0';
else
ibusy <= (sta_condition or ibusy) and not sto_condition;
end if;
end if;
end process gen_busy;
busy <= ibusy;
-- generate dout signal, store dout on rising edge of SCL
gen_dout: process(clk)
begin
if (clk'event and clk = '1') then
if fSCL = "01" then
dout <= fSDA(1);
end if;
end if;
end process gen_dout;
end block bus_status_ctrl;
-- generate statemachine
nxt_state_decoder : process (clk, nReset, c_state, cmd)
begin
if (nReset = '0') then
c_state <= idle;
s_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or ial = '1') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif csync = '1' then
c_state <= s_state;
else
cmd_ack <= '0'; -- default no acknowledge
-- csync is always '0' here, but including it in the expression
-- appears to let some compilers optimize the design more...
if (clk_en or csync) = '1' then
case (c_state) is
-- idle
when idle =>
case cmd is
when I2C_CMD_START => c_state <= start_a;
s_state <= start_g;
when I2C_CMD_STOP => c_state <= stop_a;
s_state <= stop_d;
when I2C_CMD_WRITE => c_state <= wr_a;
s_state <= wr_d;
when I2C_CMD_READ => c_state <= rd_a;
s_state <= rd_d;
when others => c_state <= idle; -- NOP command
s_state <= idle;
end case;
iscl_oen <= iscl_oen; -- keep SCL in same state
isda_oen <= isda_oen; -- keep SDA in same state
sda_chk <= '0'; -- don't check SDA
-- start
when start_a =>
c_state <= start_b;
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
when start_b =>
c_state <= start_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_c =>
c_state <= start_d;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_d =>
c_state <= start_e;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_e =>
c_state <= start_f;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when start_f =>
c_state <= start_g;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when start_g =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
s_state <= idle;
-- stop
when stop_a =>
c_state <= stop_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when stop_b =>
c_state <= stop_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_c =>
c_state <= stop_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
s_state <= idle;
-- read
when rd_a =>
c_state <= rd_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_b =>
c_state <= rd_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_c =>
c_state <= rd_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
s_state <= idle;
-- write
when wr_a =>
c_state <= wr_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= din; -- set SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when wr_b =>
c_state <= wr_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (allow signals to settle)
when wr_c =>
c_state <= wr_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
s_state <= idle;
when others =>
end case;
end if;
end if;
end if;
end process nxt_state_decoder;
-- assign outputs
scl_o <= '0';
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
end architecture structural;
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Binary wrap-around counter
entity counter is
generic (N_BITS : integer);
port (Clk : in std_logic;
Rst : in std_logic;
Cnt : out std_logic_vector (N_BITS - 1 downto 0));
end counter;
-- Operation:
-- Increase input from 0 to 2^N_BITS - 1 then start from zero again
architecture Behavioral of counter is
signal count : std_logic_vector (N_BITS - 1 downto 0);
begin
Cnt <= count;
inc : process (Clk)
begin
if RISING_EDGE(Clk) then
count <= count + 1;
if Rst = '1' then
count <= (others => '0');
end if;
end if;
end process;
end Behavioral;
|
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