content
stringlengths 1
1.04M
⌀ |
|---|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.2
-- \ \ Application :
-- / / Filename : xil_34000_21
-- /___/ /\ Timestamp : 01/16/2014 18:28:31
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity AlU4 is
port( Cl : in std_logic; -- Clock
A,B : in signed(3 downto 0); --input operands
Operation : in signed(3 downto 0); --select operation
Result : out signed(3 downto 0); --Reg3
Co : out std_logic --carry output
);
end ALU4;
architecture BEHAVIORAL of ALU4 is
signal Reg1,Reg2,Reg3 : signed(3 downto 0) := "0000";
begin
Reg1 <= A;
Reg2 <= B;
Result <= Reg3;
Co:= 0;
process(Cl)
begin
if(rising_edge(Cl)) then
case Operation is
when "0000" =>
Reg3 <= Reg1 + Reg2; --ADD
when "0001" =>
Reg3 <= Reg1 - Reg2; --SUB
when "0010" =>
Reg3 <= Reg1 * Reg2; --MUl
when "0011" =>
Reg3 <= Reg1 / Reg2; --DIV
when "0100" =>
Reg3 <= Reg1 nor Reg2; --NOR
when "0101" =>
Reg3 <= Reg1 nand Reg2; --NAND
when "0110" =>
Reg3 <= Reg1 or Reg2; --OR
when "0111" =>
Reg3 <= Reg1 and Reg2; --AND
when "1000" =>
Reg3 <= Reg1 xor Reg2; --xor
when "1001" =>
Reg3 <= Reg1 srl 1; --shift right logical
when "1010" =>
Reg3 <= Reg1 sll 1; --shift left logical
when "1011" =>
Reg3 <= Reg1 ror 1; -- right rotate
when "1100" =>
Reg3 <= Reg1 rol 1; -- left rotate
when others =>
NULL;
end case;
end if;
end process;
end BEHAVIORAL;
|
----------------------------------------------------------------------
-- brdRstClk (for EmCraft SoC FG484 Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
entity brdLexSwx is
port ( o_lex, o_pbx : out std_logic );
end brdLexSwx;
----------------------------------------------------------------------
architecture rtl of brdLexSwx is
begin
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
o_lex <= '0';
-- polarity of push button switch
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
o_pbx <= '1';
end rtl; |
entity fifo is
generic ( n : positive );
port (
wdata : bit_vector(1 to n) );
end entity;
architecture test of fifo is
begin
end architecture;
-------------------------------------------------------------------------------
entity neorv1 is
end entity;
architecture test of neorv1 is
signal x : bit;
signal y : bit_vector(1 to 2);
begin
g: for i in 0 to 1 generate
u: entity work.fifo
generic map ( 3 )
port map (
wdata(1) => x,
wdata(2 to 3) => y );
end generate;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity maxPool is
generic (
IMAGE_WIDTH : integer := 320;
IN_SIZE : integer := 8;
OUT_SIZE : integer := 8;
CLK_PROC_FREQ : integer := 50000000
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_data : out std_logic_vector(OUT_SIZE - 1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic;
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of maxPool is
component maxPool_process is
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE - 1 downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out_data : out std_logic_vector (PIXEL_SIZE - 1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end component;
begin
inst : maxPool_process
generic map (
PIXEL_SIZE => IN_SIZE,
KERNEL_SIZE => 2,
IMAGE_WIDTH => IMAGE_WIDTH
)
port map (
clk => clk_proc,
reset_n => reset_n,
enable => '1',
in_data => in_data,
in_dv => in_dv,
in_fv => in_fv,
out_data => out_data,
out_dv => out_dv,
out_fv => out_fv
);
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3053.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b04x00p03n01i03053ent IS
END c12s02b04x00p03n01i03053ent;
ARCHITECTURE c12s02b04x00p03n01i03053arch OF c12s02b04x00p03n01i03053ent IS
signal si:integer := 14;
signal sr:real := 1.4;
signal sb:bit := '0';
BEGIN
-- test for end ports associated
bl5: block
port (i:integer:=4;r:real:=6.4;b:bit:='1');
port map (i=>si, b=>sb);
begin
assert (r=6.4)
report "Default expression for unassociated real port R incorrect"
severity failure;
TESTING: PROCESS
BEGIN
assert NOT( i=14 and r=6.4 and b='0' )
report "***PASSED TEST: c12s02b04x00p03n01i03053"
severity NOTE;
assert ( i=14 and r=6.4 and b='0' )
report "***FAILED TEST: c12s02b04x00p03n01i03053 - Unassociated and associated ports are not correctly evaluated for the ports of a block."
severity ERROR;
wait;
END PROCESS TESTING;
end block;
END c12s02b04x00p03n01i03053arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3053.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b04x00p03n01i03053ent IS
END c12s02b04x00p03n01i03053ent;
ARCHITECTURE c12s02b04x00p03n01i03053arch OF c12s02b04x00p03n01i03053ent IS
signal si:integer := 14;
signal sr:real := 1.4;
signal sb:bit := '0';
BEGIN
-- test for end ports associated
bl5: block
port (i:integer:=4;r:real:=6.4;b:bit:='1');
port map (i=>si, b=>sb);
begin
assert (r=6.4)
report "Default expression for unassociated real port R incorrect"
severity failure;
TESTING: PROCESS
BEGIN
assert NOT( i=14 and r=6.4 and b='0' )
report "***PASSED TEST: c12s02b04x00p03n01i03053"
severity NOTE;
assert ( i=14 and r=6.4 and b='0' )
report "***FAILED TEST: c12s02b04x00p03n01i03053 - Unassociated and associated ports are not correctly evaluated for the ports of a block."
severity ERROR;
wait;
END PROCESS TESTING;
end block;
END c12s02b04x00p03n01i03053arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3053.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b04x00p03n01i03053ent IS
END c12s02b04x00p03n01i03053ent;
ARCHITECTURE c12s02b04x00p03n01i03053arch OF c12s02b04x00p03n01i03053ent IS
signal si:integer := 14;
signal sr:real := 1.4;
signal sb:bit := '0';
BEGIN
-- test for end ports associated
bl5: block
port (i:integer:=4;r:real:=6.4;b:bit:='1');
port map (i=>si, b=>sb);
begin
assert (r=6.4)
report "Default expression for unassociated real port R incorrect"
severity failure;
TESTING: PROCESS
BEGIN
assert NOT( i=14 and r=6.4 and b='0' )
report "***PASSED TEST: c12s02b04x00p03n01i03053"
severity NOTE;
assert ( i=14 and r=6.4 and b='0' )
report "***FAILED TEST: c12s02b04x00p03n01i03053 - Unassociated and associated ports are not correctly evaluated for the ports of a block."
severity ERROR;
wait;
END PROCESS TESTING;
end block;
END c12s02b04x00p03n01i03053arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/21/2013 02:38:36 AM
-- Design Name:
-- Module Name: ten_gig_eth_rx_parser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Parses incoming packets. Deals WITH ARP AND UDP and generates appropriate
-- action commands.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY ten_gig_eth_rx_parser IS
PORT (
RESET : IN std_logic;
RX_AXIS_FIFO_ARESETN : OUT std_logic;
-- Everything internal to this module is synchronous to this clock `ACLK'
RX_AXIS_FIFO_ACLK : IN std_logic;
RX_AXIS_FIFO_TDATA : IN std_logic_vector(63 DOWNTO 0);
RX_AXIS_FIFO_TKEEP : IN std_logic_vector(7 DOWNTO 0);
RX_AXIS_FIFO_TVALID : IN std_logic;
RX_AXIS_FIFO_TLAST : IN std_logic;
RX_AXIS_FIFO_TREADY : OUT std_logic;
-- Constants
SRC_MAC : IN std_logic_vector(47 DOWNTO 0);
SRC_IP : IN std_logic_vector(31 DOWNTO 0);
SRC_PORT : IN std_logic_vector(15 DOWNTO 0);
-- Command output fifo interface AFTER parsing the packet
-- dstMAC(48) dstIP(32) dstPort(16) opcode(32)
CMD_FIFO_Q : OUT std_logic_vector(127 DOWNTO 0);
CMD_FIFO_EMPTY : OUT std_logic;
CMD_FIFO_RDREQ : IN std_logic;
CMD_FIFO_RDCLK : IN std_logic
);
END ten_gig_eth_rx_parser;
ARCHITECTURE Behavioral OF ten_gig_eth_rx_parser IS
COMPONENT fifo128x
PORT (
RST : IN std_logic;
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
DIN : IN std_logic_vector(127 DOWNTO 0);
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DOUT : OUT std_logic_vector(127 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic
);
END COMPONENT;
--
CONSTANT pktType_ARP : std_logic_vector(15 DOWNTO 0) := x"0806";
CONSTANT pktType_IP : std_logic_vector(15 DOWNTO 0) := x"0800";
CONSTANT opcode_REQ : std_logic_vector(15 DOWNTO 0) := x"0001";
CONSTANT protocol_UDP : std_logic_vector(7 DOWNTO 0) := x"11";
--
SIGNAL clk_i : std_logic;
SIGNAL cmd_fifo_din : std_logic_vector(127 DOWNTO 0);
SIGNAL cmd_fifo_wren : std_logic;
SIGNAL cmd_fifo_full : std_logic;
--
SIGNAL tvalid_prev : std_logic;
SIGNAL tstart : std_logic;
SIGNAL tlast_i : std_logic;
--
SIGNAL dst_mac_reg : std_logic_vector(47 DOWNTO 0);
SIGNAL dst_ip_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL dst_port_reg : std_logic_vector(15 DOWNTO 0);
SIGNAL src_mac_reg : std_logic_vector(47 DOWNTO 0);
SIGNAL src_ip_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL src_port_reg : std_logic_vector(15 DOWNTO 0);
SIGNAL pktType_reg : std_logic_vector(15 DOWNTO 0);
SIGNAL opcode_reg : std_logic_vector(15 DOWNTO 0);
SIGNAL protocol_reg : std_logic_vector(7 DOWNTO 0);
SIGNAL udp_cmd_reg : std_logic_vector(31 DOWNTO 0);
--
TYPE parser_state_type IS (S0, S1, S2, S3, S4, S5, S6);
SIGNAL parser_state : parser_state_type;
SIGNAL cmd_state : parser_state_type;
BEGIN
clk_i <= RX_AXIS_FIFO_ACLK;
RX_AXIS_FIFO_ARESETN <= NOT RESET;
RX_AXIS_FIFO_TREADY <= NOT cmd_fifo_full;
cmd_fifo : fifo128x
PORT MAP (
RST => RESET,
WR_CLK => clk_i,
RD_CLK => CMD_FIFO_RDCLK,
DIN => cmd_fifo_din,
WR_EN => cmd_fifo_wren,
RD_EN => CMD_FIFO_RDREQ,
DOUT => CMD_FIFO_Q,
FULL => cmd_fifo_full,
EMPTY => CMD_FIFO_EMPTY
);
-- catch the rising edge of tvalid
PROCESS (clk_i, RESET) IS
BEGIN
IF falling_edge(clk_i) THEN
tvalid_prev <= RX_AXIS_FIFO_TVALID;
tstart <= RX_AXIS_FIFO_TVALID AND (NOT tvalid_prev);
END IF;
END PROCESS;
parser_sm : PROCESS (clk_i, RESET) IS
BEGIN
IF RESET = '1' THEN
dst_mac_reg <= (OTHERS => '0');
dst_ip_reg <= (OTHERS => '0');
dst_port_reg <= (OTHERS => '0');
src_mac_reg <= (OTHERS => '0');
src_ip_reg <= (OTHERS => '0');
src_port_reg <= (OTHERS => '0');
pktType_reg <= (OTHERS => '0');
opcode_reg <= (OTHERS => '0');
protocol_reg <= (OTHERS => '0');
udp_cmd_reg <= (OTHERS => '0');
parser_state <= S0;
ELSIF rising_edge(clk_i) THEN
tlast_i <= RX_AXIS_FIFO_TLAST;
parser_state <= S0;
CASE parser_state IS
WHEN S0 =>
IF tstart = '1' THEN
dst_mac_reg <= RX_AXIS_FIFO_TDATA(7 DOWNTO 0) &
RX_AXIS_FIFO_TDATA(15 DOWNTO 8) &
RX_AXIS_FIFO_TDATA(23 DOWNTO 16) &
RX_AXIS_FIFO_TDATA(31 DOWNTO 24) &
RX_AXIS_FIFO_TDATA(39 DOWNTO 32) &
RX_AXIS_FIFO_TDATA(47 DOWNTO 40);
src_mac_reg(47 DOWNTO 32) <= RX_AXIS_FIFO_TDATA(55 DOWNTO 48) &
RX_AXIS_FIFO_TDATA(63 DOWNTO 56);
parser_state <= S1;
END IF;
WHEN S1 =>
parser_state <= S1;
IF RX_AXIS_FIFO_TVALID = '1' THEN
src_mac_reg(31 DOWNTO 0) <= RX_AXIS_FIFO_TDATA(7 DOWNTO 0) &
RX_AXIS_FIFO_TDATA(15 DOWNTO 8) &
RX_AXIS_FIFO_TDATA(23 DOWNTO 16) &
RX_AXIS_FIFO_TDATA(31 DOWNTO 24);
pktType_reg <= RX_AXIS_FIFO_TDATA(39 DOWNTO 32) &
RX_AXIS_FIFO_TDATA(47 DOWNTO 40);
parser_state <= S2;
END IF;
WHEN S2 =>
parser_state <= S2;
IF RX_AXIS_FIFO_TVALID = '1' THEN
opcode_reg <= RX_AXIS_FIFO_TDATA(39 DOWNTO 32) &
RX_AXIS_FIFO_TDATA(47 DOWNTO 40);
protocol_reg <= RX_AXIS_FIFO_TDATA(63 DOWNTO 56);
parser_state <= S3;
END IF;
WHEN S3 =>
parser_state <= S3;
IF RX_AXIS_FIFO_TVALID = '1' THEN
IF pktType_reg = pktType_ARP THEN
src_ip_reg <= RX_AXIS_FIFO_TDATA(39 DOWNTO 32) &
RX_AXIS_FIFO_TDATA(47 DOWNTO 40) &
RX_AXIS_FIFO_TDATA(55 DOWNTO 48) &
RX_AXIS_FIFO_TDATA(63 DOWNTO 56);
ELSE
src_ip_reg <= RX_AXIS_FIFO_TDATA(23 DOWNTO 16) &
RX_AXIS_FIFO_TDATA(31 DOWNTO 24) &
RX_AXIS_FIFO_TDATA(39 DOWNTO 32) &
RX_AXIS_FIFO_TDATA(47 DOWNTO 40);
dst_ip_reg(31 DOWNTO 16) <= RX_AXIS_FIFO_TDATA(55 DOWNTO 48) &
RX_AXIS_FIFO_TDATA(63 DOWNTO 56);
END IF;
parser_state <= S4;
END IF;
WHEN S4 =>
parser_state <= S4;
IF RX_AXIS_FIFO_TVALID = '1' THEN
IF pktType_reg = pktType_ARP THEN
dst_ip_reg(31 DOWNTO 16) <= RX_AXIS_FIFO_TDATA(55 DOWNTO 48) &
RX_AXIS_FIFO_TDATA(63 DOWNTO 56);
ELSE
dst_ip_reg(15 DOWNTO 0) <= RX_AXIS_FIFO_TDATA(7 DOWNTO 0) &
RX_AXIS_FIFO_TDATA(15 DOWNTO 8);
src_port_reg <= RX_AXIS_FIFO_TDATA(23 DOWNTO 16) &
RX_AXIS_FIFO_TDATA(31 DOWNTO 24);
dst_port_reg <= RX_AXIS_FIFO_TDATA(39 DOWNTO 32) &
RX_AXIS_FIFO_TDATA(47 DOWNTO 40);
END IF;
parser_state <= S5;
END IF;
WHEN S5 =>
parser_state <= S5;
IF RX_AXIS_FIFO_TVALID = '1' THEN
IF pktType_reg = pktType_ARP THEN
dst_ip_reg(15 DOWNTO 0) <= RX_AXIS_FIFO_TDATA(7 DOWNTO 0) &
RX_AXIS_FIFO_TDATA(15 DOWNTO 8);
ELSE
udp_cmd_reg <= RX_AXIS_FIFO_TDATA(47 DOWNTO 16);
END IF;
IF RX_AXIS_FIFO_TLAST = '1' THEN
parser_state <= S0;
ELSE
parser_state <= S6;
END IF;
END IF;
WHEN S6 =>
parser_state <= S6;
IF RX_AXIS_FIFO_TLAST = '1' THEN
parser_state <= S0;
END IF;
WHEN OTHERS =>
parser_state <= S0;
END CASE;
END IF;
END PROCESS parser_sm;
PROCESS (clk_i, RESET) IS
BEGIN
IF RESET = '1' THEN
cmd_state <= S0;
ELSIF falling_edge(clk_i) THEN
cmd_fifo_wren <= '0';
cmd_state <= S0;
CASE cmd_state IS
WHEN S0 =>
IF tlast_i = '1' THEN
cmd_state <= S1;
END IF;
WHEN S1 =>
IF pktType_reg = pktType_ARP THEN
IF (dst_ip_reg = SRC_IP) AND (opcode_reg = opcode_REQ) THEN -- valid ARP request
cmd_fifo_din <= src_mac_reg & src_ip_reg & src_port_reg & x"00000000";
cmd_fifo_wren <= '1';
END IF;
ELSIF (pktType_reg = pktType_IP) AND (protocol_reg = protocol_UDP)
AND (dst_mac_reg = SRC_MAC) AND (dst_ip_reg = SRC_IP) AND (dst_port_reg = SRC_PORT)
THEN -- valid UDP packet
cmd_fifo_din <= src_mac_reg & src_ip_reg & src_port_reg & udp_cmd_reg;
cmd_fifo_wren <= '1';
END IF;
cmd_state <= S0;
WHEN OTHERS =>
cmd_state <= S0;
END CASE;
END IF;
END PROCESS;
END Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/21/2013 02:38:36 AM
-- Design Name:
-- Module Name: ten_gig_eth_rx_parser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Parses incoming packets. Deals WITH ARP AND UDP and generates appropriate
-- action commands.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY ten_gig_eth_rx_parser IS
PORT (
RESET : IN std_logic;
RX_AXIS_FIFO_ARESETN : OUT std_logic;
-- Everything internal to this module is synchronous to this clock `ACLK'
RX_AXIS_FIFO_ACLK : IN std_logic;
RX_AXIS_FIFO_TDATA : IN std_logic_vector(63 DOWNTO 0);
RX_AXIS_FIFO_TKEEP : IN std_logic_vector(7 DOWNTO 0);
RX_AXIS_FIFO_TVALID : IN std_logic;
RX_AXIS_FIFO_TLAST : IN std_logic;
RX_AXIS_FIFO_TREADY : OUT std_logic;
-- Constants
SRC_MAC : IN std_logic_vector(47 DOWNTO 0);
SRC_IP : IN std_logic_vector(31 DOWNTO 0);
SRC_PORT : IN std_logic_vector(15 DOWNTO 0);
-- Command output fifo interface AFTER parsing the packet
-- dstMAC(48) dstIP(32) dstPort(16) opcode(32)
CMD_FIFO_Q : OUT std_logic_vector(127 DOWNTO 0);
CMD_FIFO_EMPTY : OUT std_logic;
CMD_FIFO_RDREQ : IN std_logic;
CMD_FIFO_RDCLK : IN std_logic
);
END ten_gig_eth_rx_parser;
ARCHITECTURE Behavioral OF ten_gig_eth_rx_parser IS
COMPONENT fifo128x
PORT (
RST : IN std_logic;
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
DIN : IN std_logic_vector(127 DOWNTO 0);
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DOUT : OUT std_logic_vector(127 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic
);
END COMPONENT;
--
CONSTANT pktType_ARP : std_logic_vector(15 DOWNTO 0) := x"0806";
CONSTANT pktType_IP : std_logic_vector(15 DOWNTO 0) := x"0800";
CONSTANT opcode_REQ : std_logic_vector(15 DOWNTO 0) := x"0001";
CONSTANT protocol_UDP : std_logic_vector(7 DOWNTO 0) := x"11";
--
SIGNAL clk_i : std_logic;
SIGNAL cmd_fifo_din : std_logic_vector(127 DOWNTO 0);
SIGNAL cmd_fifo_wren : std_logic;
SIGNAL cmd_fifo_full : std_logic;
--
SIGNAL tvalid_prev : std_logic;
SIGNAL tstart : std_logic;
SIGNAL tlast_i : std_logic;
--
SIGNAL dst_mac_reg : std_logic_vector(47 DOWNTO 0);
SIGNAL dst_ip_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL dst_port_reg : std_logic_vector(15 DOWNTO 0);
SIGNAL src_mac_reg : std_logic_vector(47 DOWNTO 0);
SIGNAL src_ip_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL src_port_reg : std_logic_vector(15 DOWNTO 0);
SIGNAL pktType_reg : std_logic_vector(15 DOWNTO 0);
SIGNAL opcode_reg : std_logic_vector(15 DOWNTO 0);
SIGNAL protocol_reg : std_logic_vector(7 DOWNTO 0);
SIGNAL udp_cmd_reg : std_logic_vector(31 DOWNTO 0);
--
TYPE parser_state_type IS (S0, S1, S2, S3, S4, S5, S6);
SIGNAL parser_state : parser_state_type;
SIGNAL cmd_state : parser_state_type;
BEGIN
clk_i <= RX_AXIS_FIFO_ACLK;
RX_AXIS_FIFO_ARESETN <= NOT RESET;
RX_AXIS_FIFO_TREADY <= NOT cmd_fifo_full;
cmd_fifo : fifo128x
PORT MAP (
RST => RESET,
WR_CLK => clk_i,
RD_CLK => CMD_FIFO_RDCLK,
DIN => cmd_fifo_din,
WR_EN => cmd_fifo_wren,
RD_EN => CMD_FIFO_RDREQ,
DOUT => CMD_FIFO_Q,
FULL => cmd_fifo_full,
EMPTY => CMD_FIFO_EMPTY
);
-- catch the rising edge of tvalid
PROCESS (clk_i, RESET) IS
BEGIN
IF falling_edge(clk_i) THEN
tvalid_prev <= RX_AXIS_FIFO_TVALID;
tstart <= RX_AXIS_FIFO_TVALID AND (NOT tvalid_prev);
END IF;
END PROCESS;
parser_sm : PROCESS (clk_i, RESET) IS
BEGIN
IF RESET = '1' THEN
dst_mac_reg <= (OTHERS => '0');
dst_ip_reg <= (OTHERS => '0');
dst_port_reg <= (OTHERS => '0');
src_mac_reg <= (OTHERS => '0');
src_ip_reg <= (OTHERS => '0');
src_port_reg <= (OTHERS => '0');
pktType_reg <= (OTHERS => '0');
opcode_reg <= (OTHERS => '0');
protocol_reg <= (OTHERS => '0');
udp_cmd_reg <= (OTHERS => '0');
parser_state <= S0;
ELSIF rising_edge(clk_i) THEN
tlast_i <= RX_AXIS_FIFO_TLAST;
parser_state <= S0;
CASE parser_state IS
WHEN S0 =>
IF tstart = '1' THEN
dst_mac_reg <= RX_AXIS_FIFO_TDATA(7 DOWNTO 0) &
RX_AXIS_FIFO_TDATA(15 DOWNTO 8) &
RX_AXIS_FIFO_TDATA(23 DOWNTO 16) &
RX_AXIS_FIFO_TDATA(31 DOWNTO 24) &
RX_AXIS_FIFO_TDATA(39 DOWNTO 32) &
RX_AXIS_FIFO_TDATA(47 DOWNTO 40);
src_mac_reg(47 DOWNTO 32) <= RX_AXIS_FIFO_TDATA(55 DOWNTO 48) &
RX_AXIS_FIFO_TDATA(63 DOWNTO 56);
parser_state <= S1;
END IF;
WHEN S1 =>
parser_state <= S1;
IF RX_AXIS_FIFO_TVALID = '1' THEN
src_mac_reg(31 DOWNTO 0) <= RX_AXIS_FIFO_TDATA(7 DOWNTO 0) &
RX_AXIS_FIFO_TDATA(15 DOWNTO 8) &
RX_AXIS_FIFO_TDATA(23 DOWNTO 16) &
RX_AXIS_FIFO_TDATA(31 DOWNTO 24);
pktType_reg <= RX_AXIS_FIFO_TDATA(39 DOWNTO 32) &
RX_AXIS_FIFO_TDATA(47 DOWNTO 40);
parser_state <= S2;
END IF;
WHEN S2 =>
parser_state <= S2;
IF RX_AXIS_FIFO_TVALID = '1' THEN
opcode_reg <= RX_AXIS_FIFO_TDATA(39 DOWNTO 32) &
RX_AXIS_FIFO_TDATA(47 DOWNTO 40);
protocol_reg <= RX_AXIS_FIFO_TDATA(63 DOWNTO 56);
parser_state <= S3;
END IF;
WHEN S3 =>
parser_state <= S3;
IF RX_AXIS_FIFO_TVALID = '1' THEN
IF pktType_reg = pktType_ARP THEN
src_ip_reg <= RX_AXIS_FIFO_TDATA(39 DOWNTO 32) &
RX_AXIS_FIFO_TDATA(47 DOWNTO 40) &
RX_AXIS_FIFO_TDATA(55 DOWNTO 48) &
RX_AXIS_FIFO_TDATA(63 DOWNTO 56);
ELSE
src_ip_reg <= RX_AXIS_FIFO_TDATA(23 DOWNTO 16) &
RX_AXIS_FIFO_TDATA(31 DOWNTO 24) &
RX_AXIS_FIFO_TDATA(39 DOWNTO 32) &
RX_AXIS_FIFO_TDATA(47 DOWNTO 40);
dst_ip_reg(31 DOWNTO 16) <= RX_AXIS_FIFO_TDATA(55 DOWNTO 48) &
RX_AXIS_FIFO_TDATA(63 DOWNTO 56);
END IF;
parser_state <= S4;
END IF;
WHEN S4 =>
parser_state <= S4;
IF RX_AXIS_FIFO_TVALID = '1' THEN
IF pktType_reg = pktType_ARP THEN
dst_ip_reg(31 DOWNTO 16) <= RX_AXIS_FIFO_TDATA(55 DOWNTO 48) &
RX_AXIS_FIFO_TDATA(63 DOWNTO 56);
ELSE
dst_ip_reg(15 DOWNTO 0) <= RX_AXIS_FIFO_TDATA(7 DOWNTO 0) &
RX_AXIS_FIFO_TDATA(15 DOWNTO 8);
src_port_reg <= RX_AXIS_FIFO_TDATA(23 DOWNTO 16) &
RX_AXIS_FIFO_TDATA(31 DOWNTO 24);
dst_port_reg <= RX_AXIS_FIFO_TDATA(39 DOWNTO 32) &
RX_AXIS_FIFO_TDATA(47 DOWNTO 40);
END IF;
parser_state <= S5;
END IF;
WHEN S5 =>
parser_state <= S5;
IF RX_AXIS_FIFO_TVALID = '1' THEN
IF pktType_reg = pktType_ARP THEN
dst_ip_reg(15 DOWNTO 0) <= RX_AXIS_FIFO_TDATA(7 DOWNTO 0) &
RX_AXIS_FIFO_TDATA(15 DOWNTO 8);
ELSE
udp_cmd_reg <= RX_AXIS_FIFO_TDATA(47 DOWNTO 16);
END IF;
IF RX_AXIS_FIFO_TLAST = '1' THEN
parser_state <= S0;
ELSE
parser_state <= S6;
END IF;
END IF;
WHEN S6 =>
parser_state <= S6;
IF RX_AXIS_FIFO_TLAST = '1' THEN
parser_state <= S0;
END IF;
WHEN OTHERS =>
parser_state <= S0;
END CASE;
END IF;
END PROCESS parser_sm;
PROCESS (clk_i, RESET) IS
BEGIN
IF RESET = '1' THEN
cmd_state <= S0;
ELSIF falling_edge(clk_i) THEN
cmd_fifo_wren <= '0';
cmd_state <= S0;
CASE cmd_state IS
WHEN S0 =>
IF tlast_i = '1' THEN
cmd_state <= S1;
END IF;
WHEN S1 =>
IF pktType_reg = pktType_ARP THEN
IF (dst_ip_reg = SRC_IP) AND (opcode_reg = opcode_REQ) THEN -- valid ARP request
cmd_fifo_din <= src_mac_reg & src_ip_reg & src_port_reg & x"00000000";
cmd_fifo_wren <= '1';
END IF;
ELSIF (pktType_reg = pktType_IP) AND (protocol_reg = protocol_UDP)
AND (dst_mac_reg = SRC_MAC) AND (dst_ip_reg = SRC_IP) AND (dst_port_reg = SRC_PORT)
THEN -- valid UDP packet
cmd_fifo_din <= src_mac_reg & src_ip_reg & src_port_reg & udp_cmd_reg;
cmd_fifo_wren <= '1';
END IF;
cmd_state <= S0;
WHEN OTHERS =>
cmd_state <= S0;
END CASE;
END IF;
END PROCESS;
END Behavioral;
|
--!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library techmap;
use techmap.gencomp.all;
package config_target is
-- Technology and synthesis options
constant CFG_FABTECH : integer := zynq7000;
constant CFG_MEMTECH : integer := zynq7000;
constant CFG_PADTECH : integer := zynq7000;
constant CFG_JTAGTECH : integer := zynq7000;
constant CFG_ASYNC_RESET : boolean := false;
constant CFG_TOPDIR : string := "../../../";
--! @brief Number of processors in a system
--! @details This value may be in a range 1 to CFG_TOTAL_CPU_MAX-1
constant CFG_CPU_NUM : integer := 1;
--! @brief HEX-image for the initialization of the Boot ROM.
--! @details This file is used by \e inferred ROM implementation.
constant CFG_SIM_BOOTROM_HEX : string :=
CFG_TOPDIR & "examples/boot/linuxbuild/bin/bootimage.hex";
--! @brief HEX-image for the initialization of the FwImage ROM.
--! @details This file is used by \e inferred ROM implementation.
constant CFG_SIM_FWIMAGE_HEX : string :=
CFG_TOPDIR & "examples/zephyr/gcc711/zephyr.hex";
--! @brief Hardware SoC Identificator.
--!
--! @details Read Only unique platform identificator that could be
--! read by firmware from the Plug'n'Play support module.
constant CFG_HW_ID : std_logic_vector(31 downto 0) := X"20191206";
--! @brief Enabling Ethernet MAC interface.
--! @details By default MAC module enables support of the debug feature EDCL.
constant CFG_ETHERNET_ENABLE : boolean := false;
--! @brief Enable/Disable Debug Unit
constant CFG_DSU_ENABLE : boolean := true;
--! External Flash IC connected via SPI
constant CFG_EXT_FLASH_ENA : boolean := false;
--! GNSS sub-system
constant CFG_GNSS_SS_ENA : boolean := false;
--! OTP 8 KB memory bank
constant CFG_OTP8KB_ENA : boolean := false;
--! Coherent bridge with L2-cache
constant CFG_L2CACHE_ENA : boolean := false;
end;
|
-- ipif_reg_tb.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.utils_pkg.all;
entity ipif_reg_tb is
end entity;
architecture testbench of ipif_reg_tb is
constant BASE_MHZ : time := 1 us;
constant FREQ : real := 100.0;
constant PERIOD : time := BASE_MHZ / FREQ;
constant FREQ_SLOW : real := 25.0;
constant PERIOD_SLOW : time := BASE_MHZ / FREQ_SLOW;
signal clk : std_logic;
signal rst : std_logic;
signal clk_slow : std_logic;
signal rst_slow : std_logic;
signal ipif_busy : std_logic;
signal ipif_done : std_logic;
signal ipif_read : std_logic;
signal M_CLK : std_logic;
signal M_RST : std_logic;
signal M_IP2Bus_Data : std_logic_vector(31 downto 0);
signal M_IP2Bus_WrAck : std_logic;
signal M_IP2Bus_RdAck : std_logic;
signal M_IP2Bus_Error : std_logic;
signal M_Bus2IP_Addr : std_logic_vector(31 downto 0);
signal M_Bus2IP_Data : std_logic_vector(31 downto 0);
signal M_Bus2IP_RNW : std_logic;
signal M_Bus2IP_BE : std_logic_vector(3 downto 0);
signal M_Bus2IP_CS : std_logic_vector(0 downto 0);
signal S_CLK : std_logic;
signal S_RST : std_logic;
signal S_IP2Bus_Data : std_logic_vector(31 downto 0);
signal S_IP2Bus_WrAck : std_logic;
signal S_IP2Bus_RdAck : std_logic;
signal S_IP2Bus_Error : std_logic;
signal S_Bus2IP_Addr : std_logic_vector(31 downto 0);
signal S_Bus2IP_Data : std_logic_vector(31 downto 0);
signal S_Bus2IP_RNW : std_logic;
signal S_Bus2IP_BE : std_logic_vector(3 downto 0);
signal S_Bus2IP_CS : std_logic_vector(0 downto 0);
begin
M_CLK <= clk;
M_RST <= rst;
S_CLK <= clk_slow;
S_RST <= rst_slow;
ipif_gen_i : entity work.ipif_generator
generic map (
DWIDTH => 32,
AWIDTH => 32,
ADDR_MIN => 0,
ADDR_MAX => 1
)
port map (
CLK => M_CLK,
RST => M_RST,
Bus2IP_Addr => M_Bus2IP_Addr,
Bus2IP_Data => M_Bus2IP_Data,
Bus2IP_RNW => M_Bus2IP_RNW,
Bus2IP_BE => M_Bus2IP_BE,
Bus2IP_CS => M_Bus2IP_CS(0),
IPIF_BUSY => ipif_busy,
IPIF_READ => ipif_read,
IPIF_DONE => ipif_done
);
ipif_mon_i : entity work.ipif_monitor
generic map (
DWIDTH => 32
)
port map (
CLK => M_CLK,
RST => M_RST,
IP2Bus_Data => M_IP2Bus_Data,
IP2Bus_WrAck => M_IP2Bus_WrAck,
IP2Bus_RdAck => M_IP2Bus_RdAck,
IP2Bus_Error => M_IP2Bus_Error,
IPIF_BUSY => ipif_busy,
IPIF_READ => ipif_read,
IPIF_DONE => ipif_done
);
async_ipif_i : entity work.async_ipif
generic map (
AWIDTH => 32,
DWIDTH => 32,
NADDR => 1
)
port map (
M_CLK => M_CLK,
M_RST => M_RST,
M_IP2Bus_Data => M_IP2Bus_Data,
M_IP2Bus_WrAck => M_IP2Bus_WrAck,
M_IP2Bus_RdAck => M_IP2Bus_RdAck,
M_IP2Bus_Error => M_IP2Bus_Error,
M_Bus2IP_Addr => M_Bus2IP_Addr,
M_Bus2IP_Data => M_Bus2IP_Data,
M_Bus2IP_RNW => M_Bus2IP_RNW,
M_Bus2IP_BE => M_Bus2IP_BE,
M_Bus2IP_CS => M_Bus2IP_CS,
S_CLK => S_CLK,
S_RST => S_RST,
S_IP2Bus_Data => S_IP2Bus_Data,
S_IP2Bus_WrAck => S_IP2Bus_WrAck,
S_IP2Bus_RdAck => S_IP2Bus_RdAck,
S_IP2Bus_Error => S_IP2Bus_Error,
S_Bus2IP_Addr => S_Bus2IP_Addr,
S_Bus2IP_Data => S_Bus2IP_Data,
S_Bus2IP_RNW => S_Bus2IP_RNW,
S_Bus2IP_BE => S_Bus2IP_BE,
S_Bus2IP_CS => S_Bus2IP_CS
);
dut_i : entity work.ipif_reg
generic map (
REG_DWIDTH => 32,
REG_DEFAULT => X"00000000",
IPIF_DWIDTH => 32,
IPIF_MODE => IPIF_RW
)
port map (
CLK => S_CLK,
RST => S_RST,
IP2Bus_Data => S_IP2Bus_Data,
IP2Bus_WrAck => S_IP2Bus_WrAck,
IP2Bus_RdAck => S_IP2Bus_RdAck,
IP2Bus_Error => S_IP2Bus_Error,
Bus2IP_Data => S_Bus2IP_Data,
Bus2IP_BE => S_Bus2IP_BE,
Bus2IP_RNW => S_Bus2IP_RNW,
Bus2IP_CS => S_Bus2IP_CS(0),
REG_DO => open,
REG_WE => '0',
REG_DI => (others => 'X')
);
clkgenp : process
begin
clk <= '1';
wait for PERIOD / 2;
clk <= '0';
wait for PERIOD / 2;
end process;
rstgenp : process
begin
rst <= '1';
wait for 4 * PERIOD;
wait until rising_edge(clk);
rst <= '0';
wait;
end process;
clk_slow_genp : process
begin
clk_slow <= '1';
wait for PERIOD_SLOW / 2;
clk_slow <= '0';
wait for PERIOD_SLOW / 2;
end process;
rst_slow_genp : process
begin
rst_slow <= '1';
wait for 4 * PERIOD_SLOW;
wait until rising_edge(clk_slow);
rst_slow <= '0';
wait;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: regfile_3p_l3
-- File: regfile_3p_l3.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Gaisler Research
-- Description: 3-port regfile implemented with two 2-port rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
library techmap;
use techmap.gencomp.all;
use grlib.stdlib.all;
entity regfile_3p_l3 is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
wrfst : integer := 0; numregs : integer := 64;
testen : integer := 0);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end;
architecture rtl of regfile_3p_l3 is
constant rfinfer : boolean := (regfile_3p_infer(tech) = 1);
signal wd1, wd2 : std_logic_vector((dbits -1 + 8) downto 0);
signal e1, e2 : std_logic_vector((dbits-1) downto 0);
signal we1, we2 : std_ulogic;
signal vcc, gnd : std_ulogic;
signal vgnd : std_logic_vector(dbits-1 downto 0);
signal write2, renable2 : std_ulogic;
begin
vcc <= '1'; gnd <= '0'; vgnd <= (others => '0');
we1 <= we
;
we2 <= we
;
s0 : if rfinfer generate
inf : regfile_3p generic map (0, abits, dbits, wrfst, numregs, testen, memtest_vlen)
port map ( wclk, waddr, wdata, we, rclk, raddr1, re1, rdata1, raddr2, re2, rdata2,
testin
);
end generate;
s1 : if not rfinfer generate
rhu : regfile_3p generic map (tech, abits, dbits, wrfst, numregs, testen, memtest_vlen)
port map ( wclk, waddr, wdata, we, rclk, raddr1, re1, rdata1, raddr2, re2, rdata2,
testin
);
end generate;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity MODULUS_32b is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
ready : out std_logic;
nready : out std_logic;
icc : out std_logic_vector(3 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end MODULUS_32b;
-- ready = 0 indique que le circuit est pret a calculer
-- 1 signifie que le circuit est occupe
-- nready = 1 indique que le calcul est termine (1 cycle suffit)
architecture behav of MODULUS_32b is
signal buf : STD_LOGIC_VECTOR(63 downto 0);
signal dbuf : STD_LOGIC_VECTOR(31 downto 0);
signal sm : INTEGER range 0 to 32;
alias buf1 is buf(63 downto 32);
alias buf2 is buf(31 downto 0);
begin
-------------------------------------------------------------------------
reg : process(rst, clk)
variable sready, snready : std_logic;
begin
sready := '0';
snready := '0';
-- Si l'on recoit une demande de reset alors on reinitialise
if rst = '0' then
OUTPUT_1 <= (others => '0');
sm <= 0;
ready <= '0';
ready <= sready;
nready <= snready;
-- En cas de front montant de l'horloge alors on calcule
elsif rising_edge(clk) then
-- Si Flush alors on reset le composant
if (flush = '1') then
sm <= 0;
-- Si le signal de maintient est actif alors on gel l'execution
elsif (holdn = '0') then
sm <= sm;
-- Sinon on déroule l'execution de la division
else
case sm is
-- Etat d'attente du signal start
when 0 =>
OUTPUT_1 <= buf1;
if start = '1' then
buf1 <= (others => '0');
buf2 <= INPUT_1;
dbuf <= INPUT_2;
sm <= sm + 1; -- le calcul est en cours
else
sm <= sm;
end if;
-- Tous les autres états sont utiles au calcul
when others =>
sready := '1'; -- le calcul est en cours
sm <= 0;
if buf(62 downto 31) >= dbuf then
buf1 <= '0' & (buf(61 downto 31) - dbuf(30 downto 0));
buf2 <= buf2(30 downto 0) & '1';
else
buf <= buf(62 downto 0) & '0';
end if;
if sm /= 32 then
sm <= sm + 1;
snready := '0'; -- le resultat n'est pas disponible
else
snready := '1'; -- le resultat du calcul est disponible
sm <= 0;
end if;
end case;
-- On transmet les signaux au systeme
ready <= sready;
nready <= snready;
end if; -- Fin du process de calcul
end if;
end process;
end behav;
|
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- W I S H B O N E S L A V E (wbs_dual_out.vhd)
-- with two output registers
--
-- @author Simon Gansen
-------------------------------------------------------------------------------
--===========================================================================--
-- Type and component definition package
--===========================================================================--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.constants.all;
use work.interfaces.all;
package wbs_defs is
type wbs_reg_type is record
reg1 : std_logic_vector(WB_DW-1 downto 0);
reg2 : std_logic_vector(WB_DW-1 downto 0);
end record;
component wbs_dual_out
port (
-- wishbone interface
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type;
-- register outputs
reg1_out : out std_logic_vector(WB_DW-1 downto 0);
reg2_out : out std_logic_vector(WB_DW-1 downto 0)
);
end component;
end package;
--===========================================================================--
-- Entity
--===========================================================================--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.interfaces.all;
use work.constants.all;
use work.wbs_defs.all;
-------------------------------------------------------------------------------
entity wbs_dual_out is
-------------------------------------------------------------------------------
port (
-- wishbone interface
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type;
-- register outputs
reg1_out : out std_logic_vector(WB_DW-1 downto 0);
reg2_out : out std_logic_vector(WB_DW-1 downto 0)
);
end wbs_dual_out;
-------------------------------------------------------------------------------
architecture behavioral of wbs_dual_out is
-------------------------------------------------------------------------------
----------------------------------------------
-- register addresses
----------------------------------------------
constant REG1_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"00";
constant REG2_ADR : std_logic_vector(WB_REG_AW-1 downto 0) := x"01";
----------------------------------------------
-- signals
----------------------------------------------
signal reg_out_s, reg_in_s : wbs_reg_type;
signal reg1_adr_match_s, reg2_adr_match_s : std_logic;
signal reg1_ce_s, reg2_ce_s : std_logic;
begin
-------------------------------------------------------------------------------
-- Concurrent
-------------------------------------------------------------------------------
-- register address decoder/comparator
reg1_adr_match_s <= '1' when wbs_in.adr = REG1_ADR else '0';
reg2_adr_match_s <= '1' when wbs_in.adr = REG2_ADR else '0';
-- register CE
reg1_ce_s <= wbs_in.stb AND wbs_in.we AND reg1_adr_match_s;
reg2_ce_s <= wbs_in.stb AND wbs_in.we AND reg2_adr_match_s;
-- acknowledge output
wbs_out.ack <= wbs_in.stb;
-- register inputs always get data from wbs_in
reg_in_s.reg1 <= wbs_in.dat;
reg_in_s.reg2 <= wbs_in.dat;
-- register output -> wbs_out via demultiplexer
with wbs_in.adr select
wbs_out.dat <= reg_out_s.reg1 when REG1_ADR,
reg_out_s.reg2 when REG2_ADR,
(others => '-') when others;
-- register outputs -> non-wishbone outputs
reg1_out <= reg_out_s.reg1;
reg2_out <= reg_out_s.reg2;
-------------------------------------------------------------------------------
REGISTERS : process(wbs_in.clk)
-------------------------------------------------------------------------------
begin
-- everything sync to clk
if (rising_edge(wbs_in.clk)) then
-- store reg1
if (reg1_ce_s = '1') then
reg_out_s.reg1 <= reg_in_s.reg1;
-- store reg2
elsif (reg2_ce_s = '1') then
reg_out_s.reg2 <= reg_in_s.reg2;
-- hold
else
reg_out_s <= reg_out_s;
end if;
end if;
end process REGISTERS;
end behavioral;
|
-------------------------------------------------------------------------------
-- File Name : CtrlSM.vhd
--
-- Project : JPEG_ENC
--
-- Module : CtrlSM
--
-- Content : CtrlSM
--
-- Description : CtrlSM core
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity CtrlSM is
port
(
CLK : in std_logic;
RST : in std_logic;
-- output IF
outif_almost_full : in std_logic;
-- HOST IF
sof : in std_logic;
img_size_x : in std_logic_vector(15 downto 0);
img_size_y : in std_logic_vector(15 downto 0);
jpeg_ready : out std_logic;
jpeg_busy : out std_logic;
-- FDCT
fdct_start : out std_logic;
fdct_ready : in std_logic;
fdct_sm_settings : out T_SM_SETTINGS;
-- ZIGZAG
zig_start : out std_logic;
zig_ready : in std_logic;
zig_sm_settings : out T_SM_SETTINGS;
-- Quantizer
qua_start : out std_logic;
qua_ready : in std_logic;
qua_sm_settings : out T_SM_SETTINGS;
-- RLE
rle_start : out std_logic;
rle_ready : in std_logic;
rle_sm_settings : out T_SM_SETTINGS;
-- Huffman
huf_start : out std_logic;
huf_ready : in std_logic;
huf_sm_settings : out T_SM_SETTINGS;
-- ByteStuffdr
bs_start : out std_logic;
bs_ready : in std_logic;
bs_sm_settings : out T_SM_SETTINGS;
-- JFIF GEN
jfif_start : out std_logic;
jfif_ready : in std_logic;
jfif_eoi : out std_logic;
-- OUT MUX
out_mux_ctrl : out std_logic
);
end entity CtrlSM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of CtrlSM is
constant NUM_STAGES : integer := 6;
constant CMP_MAX : std_logic_vector(2 downto 0) := "100";
type T_STATE is (IDLES, JFIF, HORIZ, COMP, VERT, EOI);
type ARR_FSM is array(NUM_STAGES downto 1) of std_logic_vector(1 downto 0);
type T_ARR_SM_SETTINGS is array(NUM_STAGES+1 downto 1) of T_SM_SETTINGS;
signal Reg : T_ARR_SM_SETTINGS;
signal main_state : T_STATE;
signal start : std_logic_vector(NUM_STAGES+1 downto 1);
signal idle : std_logic_vector(NUM_STAGES+1 downto 1);
signal start_PB : std_logic_vector(NUM_STAGES downto 1);
signal ready_PB : std_logic_vector(NUM_STAGES downto 1);
signal fsm : ARR_FSM;
signal start1_d : std_logic;
signal RSM : T_SM_SETTINGS;
signal out_mux_ctrl_s : std_logic;
signal out_mux_ctrl_s2 : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
fdct_sm_settings <= Reg(1);
zig_sm_settings <= Reg(2);
qua_sm_settings <= Reg(3);
rle_sm_settings <= Reg(4);
huf_sm_settings <= Reg(5);
bs_sm_settings <= Reg(6);
fdct_start <= start_PB(1);
ready_PB(1) <= fdct_ready;
zig_start <= start_PB(2);
ready_PB(2) <= zig_ready;
qua_start <= start_PB(3);
ready_PB(3) <= qua_ready;
rle_start <= start_PB(4);
ready_PB(4) <= rle_ready;
huf_start <= start_PB(5);
ready_PB(5) <= huf_ready;
bs_start <= start_PB(6);
ready_PB(6) <= bs_ready;
-----------------------------------------------------------------------------
-- CTRLSM 1..NUM_STAGES
-----------------------------------------------------------------------------
G_S_CTRL_SM : for i in 1 to NUM_STAGES generate
-- CTRLSM 1..NUM_STAGES
U_S_CTRL_SM : entity work.SingleSM
port map
(
CLK => CLK,
RST => RST,
-- from/to SM(m)
start_i => start(i),
idle_o => idle(i),
-- from/to SM(m+1)
idle_i => idle(i+1),
start_o => start(i+1),
-- from/to processing block
pb_rdy_i => ready_PB(i),
pb_start_o => start_PB(i),
-- state out
fsm_o => fsm(i)
);
end generate G_S_CTRL_SM;
idle(NUM_STAGES+1) <= not outif_almost_full;
-------------------------------------------------------------------
-- Regs
-------------------------------------------------------------------
G_REG_SM : for i in 1 to NUM_STAGES generate
p_reg1 : process(CLK, RST)
begin
if RST = '1' then
Reg(i) <= C_SM_SETTINGS;
elsif CLK'event and CLK = '1' then
if start(i) = '1' then
if i = 1 then
Reg(i).x_cnt <= RSM.x_cnt;
Reg(i).y_cnt <= RSM.y_cnt;
Reg(i).cmp_idx <= RSM.cmp_idx;
else
Reg(i) <= Reg(i-1);
end if;
end if;
end if;
end process;
end generate G_REG_SM;
-------------------------------------------------------------------
-- Main_SM
-------------------------------------------------------------------
p_main_sm : process(CLK, RST)
begin
if RST = '1' then
main_state <= IDLES;
start(1) <= '0';
start1_d <= '0';
jpeg_ready <= '0';
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= (others => '0');
jpeg_busy <= '0';
RSM.cmp_idx <= (others => '0');
out_mux_ctrl_s <= '0';
out_mux_ctrl_s2 <= '0';
jfif_eoi <= '0';
out_mux_ctrl <= '0';
jfif_start <= '0';
elsif CLK'event and CLK = '1' then
start(1) <= '0';
start1_d <= start(1);
jpeg_ready <= '0';
jfif_start <= '0';
out_mux_ctrl_s2 <= out_mux_ctrl_s;
out_mux_ctrl <= out_mux_ctrl_s2;
case main_state is
-------------------------------
-- IDLE
-------------------------------
when IDLES =>
if sof = '1' then
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= (others => '0');
jfif_start <= '1';
out_mux_ctrl_s <= '0';
jfif_eoi <= '0';
main_state <= JFIF;
end if;
-------------------------------
-- JFIF
-------------------------------
when JFIF =>
if jfif_ready = '1' then
out_mux_ctrl_s <= '1';
main_state <= HORIZ;
end if;
-------------------------------
-- HORIZ
-------------------------------
when HORIZ =>
if RSM.x_cnt < unsigned(img_size_x) then
main_state <= COMP;
else
RSM.x_cnt <= (others => '0');
main_state <= VERT;
end if;
-------------------------------
-- COMP
-------------------------------
when COMP =>
if idle(1) = '1' and start(1) = '0' then
if RSM.cmp_idx < unsigned(CMP_MAX) then
start(1) <= '1';
else
RSM.cmp_idx <= (others => '0');
RSM.x_cnt <= RSM.x_cnt + 16;
main_state <= HORIZ;
end if;
end if;
-------------------------------
-- VERT
-------------------------------
when VERT =>
if RSM.y_cnt < unsigned(img_size_y)-8 then
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= RSM.y_cnt + 8;
main_state <= HORIZ;
else
if idle(NUM_STAGES+1 downto 1) = (NUM_STAGES+1 downto 1 => '1') then
main_state <= EOI;
jfif_eoi <= '1';
out_mux_ctrl_s <= '0';
jfif_start <= '1';
end if;
end if;
-------------------------------
-- VERT
-------------------------------
when EOI =>
if jfif_ready = '1' then
jpeg_ready <= '1';
main_state <= IDLES;
end if;
-------------------------------
-- others
-------------------------------
when others =>
main_state <= IDLES;
end case;
if start1_d = '1' then
RSM.cmp_idx <= RSM.cmp_idx + 1;
end if;
if main_state = IDLES then
jpeg_busy <= '0';
else
jpeg_busy <= '1';
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : CtrlSM.vhd
--
-- Project : JPEG_ENC
--
-- Module : CtrlSM
--
-- Content : CtrlSM
--
-- Description : CtrlSM core
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity CtrlSM is
port
(
CLK : in std_logic;
RST : in std_logic;
-- output IF
outif_almost_full : in std_logic;
-- HOST IF
sof : in std_logic;
img_size_x : in std_logic_vector(15 downto 0);
img_size_y : in std_logic_vector(15 downto 0);
jpeg_ready : out std_logic;
jpeg_busy : out std_logic;
-- FDCT
fdct_start : out std_logic;
fdct_ready : in std_logic;
fdct_sm_settings : out T_SM_SETTINGS;
-- ZIGZAG
zig_start : out std_logic;
zig_ready : in std_logic;
zig_sm_settings : out T_SM_SETTINGS;
-- Quantizer
qua_start : out std_logic;
qua_ready : in std_logic;
qua_sm_settings : out T_SM_SETTINGS;
-- RLE
rle_start : out std_logic;
rle_ready : in std_logic;
rle_sm_settings : out T_SM_SETTINGS;
-- Huffman
huf_start : out std_logic;
huf_ready : in std_logic;
huf_sm_settings : out T_SM_SETTINGS;
-- ByteStuffdr
bs_start : out std_logic;
bs_ready : in std_logic;
bs_sm_settings : out T_SM_SETTINGS;
-- JFIF GEN
jfif_start : out std_logic;
jfif_ready : in std_logic;
jfif_eoi : out std_logic;
-- OUT MUX
out_mux_ctrl : out std_logic
);
end entity CtrlSM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of CtrlSM is
constant NUM_STAGES : integer := 6;
constant CMP_MAX : std_logic_vector(2 downto 0) := "100";
type T_STATE is (IDLES, JFIF, HORIZ, COMP, VERT, EOI);
type ARR_FSM is array(NUM_STAGES downto 1) of std_logic_vector(1 downto 0);
type T_ARR_SM_SETTINGS is array(NUM_STAGES+1 downto 1) of T_SM_SETTINGS;
signal Reg : T_ARR_SM_SETTINGS;
signal main_state : T_STATE;
signal start : std_logic_vector(NUM_STAGES+1 downto 1);
signal idle : std_logic_vector(NUM_STAGES+1 downto 1);
signal start_PB : std_logic_vector(NUM_STAGES downto 1);
signal ready_PB : std_logic_vector(NUM_STAGES downto 1);
signal fsm : ARR_FSM;
signal start1_d : std_logic;
signal RSM : T_SM_SETTINGS;
signal out_mux_ctrl_s : std_logic;
signal out_mux_ctrl_s2 : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
fdct_sm_settings <= Reg(1);
zig_sm_settings <= Reg(2);
qua_sm_settings <= Reg(3);
rle_sm_settings <= Reg(4);
huf_sm_settings <= Reg(5);
bs_sm_settings <= Reg(6);
fdct_start <= start_PB(1);
ready_PB(1) <= fdct_ready;
zig_start <= start_PB(2);
ready_PB(2) <= zig_ready;
qua_start <= start_PB(3);
ready_PB(3) <= qua_ready;
rle_start <= start_PB(4);
ready_PB(4) <= rle_ready;
huf_start <= start_PB(5);
ready_PB(5) <= huf_ready;
bs_start <= start_PB(6);
ready_PB(6) <= bs_ready;
-----------------------------------------------------------------------------
-- CTRLSM 1..NUM_STAGES
-----------------------------------------------------------------------------
G_S_CTRL_SM : for i in 1 to NUM_STAGES generate
-- CTRLSM 1..NUM_STAGES
U_S_CTRL_SM : entity work.SingleSM
port map
(
CLK => CLK,
RST => RST,
-- from/to SM(m)
start_i => start(i),
idle_o => idle(i),
-- from/to SM(m+1)
idle_i => idle(i+1),
start_o => start(i+1),
-- from/to processing block
pb_rdy_i => ready_PB(i),
pb_start_o => start_PB(i),
-- state out
fsm_o => fsm(i)
);
end generate G_S_CTRL_SM;
idle(NUM_STAGES+1) <= not outif_almost_full;
-------------------------------------------------------------------
-- Regs
-------------------------------------------------------------------
G_REG_SM : for i in 1 to NUM_STAGES generate
p_reg1 : process(CLK, RST)
begin
if RST = '1' then
Reg(i) <= C_SM_SETTINGS;
elsif CLK'event and CLK = '1' then
if start(i) = '1' then
if i = 1 then
Reg(i).x_cnt <= RSM.x_cnt;
Reg(i).y_cnt <= RSM.y_cnt;
Reg(i).cmp_idx <= RSM.cmp_idx;
else
Reg(i) <= Reg(i-1);
end if;
end if;
end if;
end process;
end generate G_REG_SM;
-------------------------------------------------------------------
-- Main_SM
-------------------------------------------------------------------
p_main_sm : process(CLK, RST)
begin
if RST = '1' then
main_state <= IDLES;
start(1) <= '0';
start1_d <= '0';
jpeg_ready <= '0';
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= (others => '0');
jpeg_busy <= '0';
RSM.cmp_idx <= (others => '0');
out_mux_ctrl_s <= '0';
out_mux_ctrl_s2 <= '0';
jfif_eoi <= '0';
out_mux_ctrl <= '0';
jfif_start <= '0';
elsif CLK'event and CLK = '1' then
start(1) <= '0';
start1_d <= start(1);
jpeg_ready <= '0';
jfif_start <= '0';
out_mux_ctrl_s2 <= out_mux_ctrl_s;
out_mux_ctrl <= out_mux_ctrl_s2;
case main_state is
-------------------------------
-- IDLE
-------------------------------
when IDLES =>
if sof = '1' then
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= (others => '0');
jfif_start <= '1';
out_mux_ctrl_s <= '0';
jfif_eoi <= '0';
main_state <= JFIF;
end if;
-------------------------------
-- JFIF
-------------------------------
when JFIF =>
if jfif_ready = '1' then
out_mux_ctrl_s <= '1';
main_state <= HORIZ;
end if;
-------------------------------
-- HORIZ
-------------------------------
when HORIZ =>
if RSM.x_cnt < unsigned(img_size_x) then
main_state <= COMP;
else
RSM.x_cnt <= (others => '0');
main_state <= VERT;
end if;
-------------------------------
-- COMP
-------------------------------
when COMP =>
if idle(1) = '1' and start(1) = '0' then
if RSM.cmp_idx < unsigned(CMP_MAX) then
start(1) <= '1';
else
RSM.cmp_idx <= (others => '0');
RSM.x_cnt <= RSM.x_cnt + 16;
main_state <= HORIZ;
end if;
end if;
-------------------------------
-- VERT
-------------------------------
when VERT =>
if RSM.y_cnt < unsigned(img_size_y)-8 then
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= RSM.y_cnt + 8;
main_state <= HORIZ;
else
if idle(NUM_STAGES+1 downto 1) = (NUM_STAGES+1 downto 1 => '1') then
main_state <= EOI;
jfif_eoi <= '1';
out_mux_ctrl_s <= '0';
jfif_start <= '1';
end if;
end if;
-------------------------------
-- VERT
-------------------------------
when EOI =>
if jfif_ready = '1' then
jpeg_ready <= '1';
main_state <= IDLES;
end if;
-------------------------------
-- others
-------------------------------
when others =>
main_state <= IDLES;
end case;
if start1_d = '1' then
RSM.cmp_idx <= RSM.cmp_idx + 1;
end if;
if main_state = IDLES then
jpeg_busy <= '0';
else
jpeg_busy <= '1';
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : CtrlSM.vhd
--
-- Project : JPEG_ENC
--
-- Module : CtrlSM
--
-- Content : CtrlSM
--
-- Description : CtrlSM core
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity CtrlSM is
port
(
CLK : in std_logic;
RST : in std_logic;
-- output IF
outif_almost_full : in std_logic;
-- HOST IF
sof : in std_logic;
img_size_x : in std_logic_vector(15 downto 0);
img_size_y : in std_logic_vector(15 downto 0);
jpeg_ready : out std_logic;
jpeg_busy : out std_logic;
-- FDCT
fdct_start : out std_logic;
fdct_ready : in std_logic;
fdct_sm_settings : out T_SM_SETTINGS;
-- ZIGZAG
zig_start : out std_logic;
zig_ready : in std_logic;
zig_sm_settings : out T_SM_SETTINGS;
-- Quantizer
qua_start : out std_logic;
qua_ready : in std_logic;
qua_sm_settings : out T_SM_SETTINGS;
-- RLE
rle_start : out std_logic;
rle_ready : in std_logic;
rle_sm_settings : out T_SM_SETTINGS;
-- Huffman
huf_start : out std_logic;
huf_ready : in std_logic;
huf_sm_settings : out T_SM_SETTINGS;
-- ByteStuffdr
bs_start : out std_logic;
bs_ready : in std_logic;
bs_sm_settings : out T_SM_SETTINGS;
-- JFIF GEN
jfif_start : out std_logic;
jfif_ready : in std_logic;
jfif_eoi : out std_logic;
-- OUT MUX
out_mux_ctrl : out std_logic
);
end entity CtrlSM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of CtrlSM is
constant NUM_STAGES : integer := 6;
constant CMP_MAX : std_logic_vector(2 downto 0) := "100";
type T_STATE is (IDLES, JFIF, HORIZ, COMP, VERT, EOI);
type ARR_FSM is array(NUM_STAGES downto 1) of std_logic_vector(1 downto 0);
type T_ARR_SM_SETTINGS is array(NUM_STAGES+1 downto 1) of T_SM_SETTINGS;
signal Reg : T_ARR_SM_SETTINGS;
signal main_state : T_STATE;
signal start : std_logic_vector(NUM_STAGES+1 downto 1);
signal idle : std_logic_vector(NUM_STAGES+1 downto 1);
signal start_PB : std_logic_vector(NUM_STAGES downto 1);
signal ready_PB : std_logic_vector(NUM_STAGES downto 1);
signal fsm : ARR_FSM;
signal start1_d : std_logic;
signal RSM : T_SM_SETTINGS;
signal out_mux_ctrl_s : std_logic;
signal out_mux_ctrl_s2 : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
fdct_sm_settings <= Reg(1);
zig_sm_settings <= Reg(2);
qua_sm_settings <= Reg(3);
rle_sm_settings <= Reg(4);
huf_sm_settings <= Reg(5);
bs_sm_settings <= Reg(6);
fdct_start <= start_PB(1);
ready_PB(1) <= fdct_ready;
zig_start <= start_PB(2);
ready_PB(2) <= zig_ready;
qua_start <= start_PB(3);
ready_PB(3) <= qua_ready;
rle_start <= start_PB(4);
ready_PB(4) <= rle_ready;
huf_start <= start_PB(5);
ready_PB(5) <= huf_ready;
bs_start <= start_PB(6);
ready_PB(6) <= bs_ready;
-----------------------------------------------------------------------------
-- CTRLSM 1..NUM_STAGES
-----------------------------------------------------------------------------
G_S_CTRL_SM : for i in 1 to NUM_STAGES generate
-- CTRLSM 1..NUM_STAGES
U_S_CTRL_SM : entity work.SingleSM
port map
(
CLK => CLK,
RST => RST,
-- from/to SM(m)
start_i => start(i),
idle_o => idle(i),
-- from/to SM(m+1)
idle_i => idle(i+1),
start_o => start(i+1),
-- from/to processing block
pb_rdy_i => ready_PB(i),
pb_start_o => start_PB(i),
-- state out
fsm_o => fsm(i)
);
end generate G_S_CTRL_SM;
idle(NUM_STAGES+1) <= not outif_almost_full;
-------------------------------------------------------------------
-- Regs
-------------------------------------------------------------------
G_REG_SM : for i in 1 to NUM_STAGES generate
p_reg1 : process(CLK, RST)
begin
if RST = '1' then
Reg(i) <= C_SM_SETTINGS;
elsif CLK'event and CLK = '1' then
if start(i) = '1' then
if i = 1 then
Reg(i).x_cnt <= RSM.x_cnt;
Reg(i).y_cnt <= RSM.y_cnt;
Reg(i).cmp_idx <= RSM.cmp_idx;
else
Reg(i) <= Reg(i-1);
end if;
end if;
end if;
end process;
end generate G_REG_SM;
-------------------------------------------------------------------
-- Main_SM
-------------------------------------------------------------------
p_main_sm : process(CLK, RST)
begin
if RST = '1' then
main_state <= IDLES;
start(1) <= '0';
start1_d <= '0';
jpeg_ready <= '0';
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= (others => '0');
jpeg_busy <= '0';
RSM.cmp_idx <= (others => '0');
out_mux_ctrl_s <= '0';
out_mux_ctrl_s2 <= '0';
jfif_eoi <= '0';
out_mux_ctrl <= '0';
jfif_start <= '0';
elsif CLK'event and CLK = '1' then
start(1) <= '0';
start1_d <= start(1);
jpeg_ready <= '0';
jfif_start <= '0';
out_mux_ctrl_s2 <= out_mux_ctrl_s;
out_mux_ctrl <= out_mux_ctrl_s2;
case main_state is
-------------------------------
-- IDLE
-------------------------------
when IDLES =>
if sof = '1' then
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= (others => '0');
jfif_start <= '1';
out_mux_ctrl_s <= '0';
jfif_eoi <= '0';
main_state <= JFIF;
end if;
-------------------------------
-- JFIF
-------------------------------
when JFIF =>
if jfif_ready = '1' then
out_mux_ctrl_s <= '1';
main_state <= HORIZ;
end if;
-------------------------------
-- HORIZ
-------------------------------
when HORIZ =>
if RSM.x_cnt < unsigned(img_size_x) then
main_state <= COMP;
else
RSM.x_cnt <= (others => '0');
main_state <= VERT;
end if;
-------------------------------
-- COMP
-------------------------------
when COMP =>
if idle(1) = '1' and start(1) = '0' then
if RSM.cmp_idx < unsigned(CMP_MAX) then
start(1) <= '1';
else
RSM.cmp_idx <= (others => '0');
RSM.x_cnt <= RSM.x_cnt + 16;
main_state <= HORIZ;
end if;
end if;
-------------------------------
-- VERT
-------------------------------
when VERT =>
if RSM.y_cnt < unsigned(img_size_y)-8 then
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= RSM.y_cnt + 8;
main_state <= HORIZ;
else
if idle(NUM_STAGES+1 downto 1) = (NUM_STAGES+1 downto 1 => '1') then
main_state <= EOI;
jfif_eoi <= '1';
out_mux_ctrl_s <= '0';
jfif_start <= '1';
end if;
end if;
-------------------------------
-- VERT
-------------------------------
when EOI =>
if jfif_ready = '1' then
jpeg_ready <= '1';
main_state <= IDLES;
end if;
-------------------------------
-- others
-------------------------------
when others =>
main_state <= IDLES;
end case;
if start1_d = '1' then
RSM.cmp_idx <= RSM.cmp_idx + 1;
end if;
if main_state = IDLES then
jpeg_busy <= '0';
else
jpeg_busy <= '1';
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : CtrlSM.vhd
--
-- Project : JPEG_ENC
--
-- Module : CtrlSM
--
-- Content : CtrlSM
--
-- Description : CtrlSM core
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity CtrlSM is
port
(
CLK : in std_logic;
RST : in std_logic;
-- output IF
outif_almost_full : in std_logic;
-- HOST IF
sof : in std_logic;
img_size_x : in std_logic_vector(15 downto 0);
img_size_y : in std_logic_vector(15 downto 0);
jpeg_ready : out std_logic;
jpeg_busy : out std_logic;
-- FDCT
fdct_start : out std_logic;
fdct_ready : in std_logic;
fdct_sm_settings : out T_SM_SETTINGS;
-- ZIGZAG
zig_start : out std_logic;
zig_ready : in std_logic;
zig_sm_settings : out T_SM_SETTINGS;
-- Quantizer
qua_start : out std_logic;
qua_ready : in std_logic;
qua_sm_settings : out T_SM_SETTINGS;
-- RLE
rle_start : out std_logic;
rle_ready : in std_logic;
rle_sm_settings : out T_SM_SETTINGS;
-- Huffman
huf_start : out std_logic;
huf_ready : in std_logic;
huf_sm_settings : out T_SM_SETTINGS;
-- ByteStuffdr
bs_start : out std_logic;
bs_ready : in std_logic;
bs_sm_settings : out T_SM_SETTINGS;
-- JFIF GEN
jfif_start : out std_logic;
jfif_ready : in std_logic;
jfif_eoi : out std_logic;
-- OUT MUX
out_mux_ctrl : out std_logic
);
end entity CtrlSM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of CtrlSM is
constant NUM_STAGES : integer := 6;
constant CMP_MAX : std_logic_vector(2 downto 0) := "100";
type T_STATE is (IDLES, JFIF, HORIZ, COMP, VERT, EOI);
type ARR_FSM is array(NUM_STAGES downto 1) of std_logic_vector(1 downto 0);
type T_ARR_SM_SETTINGS is array(NUM_STAGES+1 downto 1) of T_SM_SETTINGS;
signal Reg : T_ARR_SM_SETTINGS;
signal main_state : T_STATE;
signal start : std_logic_vector(NUM_STAGES+1 downto 1);
signal idle : std_logic_vector(NUM_STAGES+1 downto 1);
signal start_PB : std_logic_vector(NUM_STAGES downto 1);
signal ready_PB : std_logic_vector(NUM_STAGES downto 1);
signal fsm : ARR_FSM;
signal start1_d : std_logic;
signal RSM : T_SM_SETTINGS;
signal out_mux_ctrl_s : std_logic;
signal out_mux_ctrl_s2 : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
fdct_sm_settings <= Reg(1);
zig_sm_settings <= Reg(2);
qua_sm_settings <= Reg(3);
rle_sm_settings <= Reg(4);
huf_sm_settings <= Reg(5);
bs_sm_settings <= Reg(6);
fdct_start <= start_PB(1);
ready_PB(1) <= fdct_ready;
zig_start <= start_PB(2);
ready_PB(2) <= zig_ready;
qua_start <= start_PB(3);
ready_PB(3) <= qua_ready;
rle_start <= start_PB(4);
ready_PB(4) <= rle_ready;
huf_start <= start_PB(5);
ready_PB(5) <= huf_ready;
bs_start <= start_PB(6);
ready_PB(6) <= bs_ready;
-----------------------------------------------------------------------------
-- CTRLSM 1..NUM_STAGES
-----------------------------------------------------------------------------
G_S_CTRL_SM : for i in 1 to NUM_STAGES generate
-- CTRLSM 1..NUM_STAGES
U_S_CTRL_SM : entity work.SingleSM
port map
(
CLK => CLK,
RST => RST,
-- from/to SM(m)
start_i => start(i),
idle_o => idle(i),
-- from/to SM(m+1)
idle_i => idle(i+1),
start_o => start(i+1),
-- from/to processing block
pb_rdy_i => ready_PB(i),
pb_start_o => start_PB(i),
-- state out
fsm_o => fsm(i)
);
end generate G_S_CTRL_SM;
idle(NUM_STAGES+1) <= not outif_almost_full;
-------------------------------------------------------------------
-- Regs
-------------------------------------------------------------------
G_REG_SM : for i in 1 to NUM_STAGES generate
p_reg1 : process(CLK, RST)
begin
if RST = '1' then
Reg(i) <= C_SM_SETTINGS;
elsif CLK'event and CLK = '1' then
if start(i) = '1' then
if i = 1 then
Reg(i).x_cnt <= RSM.x_cnt;
Reg(i).y_cnt <= RSM.y_cnt;
Reg(i).cmp_idx <= RSM.cmp_idx;
else
Reg(i) <= Reg(i-1);
end if;
end if;
end if;
end process;
end generate G_REG_SM;
-------------------------------------------------------------------
-- Main_SM
-------------------------------------------------------------------
p_main_sm : process(CLK, RST)
begin
if RST = '1' then
main_state <= IDLES;
start(1) <= '0';
start1_d <= '0';
jpeg_ready <= '0';
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= (others => '0');
jpeg_busy <= '0';
RSM.cmp_idx <= (others => '0');
out_mux_ctrl_s <= '0';
out_mux_ctrl_s2 <= '0';
jfif_eoi <= '0';
out_mux_ctrl <= '0';
jfif_start <= '0';
elsif CLK'event and CLK = '1' then
start(1) <= '0';
start1_d <= start(1);
jpeg_ready <= '0';
jfif_start <= '0';
out_mux_ctrl_s2 <= out_mux_ctrl_s;
out_mux_ctrl <= out_mux_ctrl_s2;
case main_state is
-------------------------------
-- IDLE
-------------------------------
when IDLES =>
if sof = '1' then
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= (others => '0');
jfif_start <= '1';
out_mux_ctrl_s <= '0';
jfif_eoi <= '0';
main_state <= JFIF;
end if;
-------------------------------
-- JFIF
-------------------------------
when JFIF =>
if jfif_ready = '1' then
out_mux_ctrl_s <= '1';
main_state <= HORIZ;
end if;
-------------------------------
-- HORIZ
-------------------------------
when HORIZ =>
if RSM.x_cnt < unsigned(img_size_x) then
main_state <= COMP;
else
RSM.x_cnt <= (others => '0');
main_state <= VERT;
end if;
-------------------------------
-- COMP
-------------------------------
when COMP =>
if idle(1) = '1' and start(1) = '0' then
if RSM.cmp_idx < unsigned(CMP_MAX) then
start(1) <= '1';
else
RSM.cmp_idx <= (others => '0');
RSM.x_cnt <= RSM.x_cnt + 16;
main_state <= HORIZ;
end if;
end if;
-------------------------------
-- VERT
-------------------------------
when VERT =>
if RSM.y_cnt < unsigned(img_size_y)-8 then
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= RSM.y_cnt + 8;
main_state <= HORIZ;
else
if idle(NUM_STAGES+1 downto 1) = (NUM_STAGES+1 downto 1 => '1') then
main_state <= EOI;
jfif_eoi <= '1';
out_mux_ctrl_s <= '0';
jfif_start <= '1';
end if;
end if;
-------------------------------
-- VERT
-------------------------------
when EOI =>
if jfif_ready = '1' then
jpeg_ready <= '1';
main_state <= IDLES;
end if;
-------------------------------
-- others
-------------------------------
when others =>
main_state <= IDLES;
end case;
if start1_d = '1' then
RSM.cmp_idx <= RSM.cmp_idx + 1;
end if;
if main_state = IDLES then
jpeg_busy <= '0';
else
jpeg_busy <= '1';
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : CtrlSM.vhd
--
-- Project : JPEG_ENC
--
-- Module : CtrlSM
--
-- Content : CtrlSM
--
-- Description : CtrlSM core
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity CtrlSM is
port
(
CLK : in std_logic;
RST : in std_logic;
-- output IF
outif_almost_full : in std_logic;
-- HOST IF
sof : in std_logic;
img_size_x : in std_logic_vector(15 downto 0);
img_size_y : in std_logic_vector(15 downto 0);
jpeg_ready : out std_logic;
jpeg_busy : out std_logic;
-- FDCT
fdct_start : out std_logic;
fdct_ready : in std_logic;
fdct_sm_settings : out T_SM_SETTINGS;
-- ZIGZAG
zig_start : out std_logic;
zig_ready : in std_logic;
zig_sm_settings : out T_SM_SETTINGS;
-- Quantizer
qua_start : out std_logic;
qua_ready : in std_logic;
qua_sm_settings : out T_SM_SETTINGS;
-- RLE
rle_start : out std_logic;
rle_ready : in std_logic;
rle_sm_settings : out T_SM_SETTINGS;
-- Huffman
huf_start : out std_logic;
huf_ready : in std_logic;
huf_sm_settings : out T_SM_SETTINGS;
-- ByteStuffdr
bs_start : out std_logic;
bs_ready : in std_logic;
bs_sm_settings : out T_SM_SETTINGS;
-- JFIF GEN
jfif_start : out std_logic;
jfif_ready : in std_logic;
jfif_eoi : out std_logic;
-- OUT MUX
out_mux_ctrl : out std_logic
);
end entity CtrlSM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of CtrlSM is
constant NUM_STAGES : integer := 6;
constant CMP_MAX : std_logic_vector(2 downto 0) := "100";
type T_STATE is (IDLES, JFIF, HORIZ, COMP, VERT, EOI);
type ARR_FSM is array(NUM_STAGES downto 1) of std_logic_vector(1 downto 0);
type T_ARR_SM_SETTINGS is array(NUM_STAGES+1 downto 1) of T_SM_SETTINGS;
signal Reg : T_ARR_SM_SETTINGS;
signal main_state : T_STATE;
signal start : std_logic_vector(NUM_STAGES+1 downto 1);
signal idle : std_logic_vector(NUM_STAGES+1 downto 1);
signal start_PB : std_logic_vector(NUM_STAGES downto 1);
signal ready_PB : std_logic_vector(NUM_STAGES downto 1);
signal fsm : ARR_FSM;
signal start1_d : std_logic;
signal RSM : T_SM_SETTINGS;
signal out_mux_ctrl_s : std_logic;
signal out_mux_ctrl_s2 : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
fdct_sm_settings <= Reg(1);
zig_sm_settings <= Reg(2);
qua_sm_settings <= Reg(3);
rle_sm_settings <= Reg(4);
huf_sm_settings <= Reg(5);
bs_sm_settings <= Reg(6);
fdct_start <= start_PB(1);
ready_PB(1) <= fdct_ready;
zig_start <= start_PB(2);
ready_PB(2) <= zig_ready;
qua_start <= start_PB(3);
ready_PB(3) <= qua_ready;
rle_start <= start_PB(4);
ready_PB(4) <= rle_ready;
huf_start <= start_PB(5);
ready_PB(5) <= huf_ready;
bs_start <= start_PB(6);
ready_PB(6) <= bs_ready;
-----------------------------------------------------------------------------
-- CTRLSM 1..NUM_STAGES
-----------------------------------------------------------------------------
G_S_CTRL_SM : for i in 1 to NUM_STAGES generate
-- CTRLSM 1..NUM_STAGES
U_S_CTRL_SM : entity work.SingleSM
port map
(
CLK => CLK,
RST => RST,
-- from/to SM(m)
start_i => start(i),
idle_o => idle(i),
-- from/to SM(m+1)
idle_i => idle(i+1),
start_o => start(i+1),
-- from/to processing block
pb_rdy_i => ready_PB(i),
pb_start_o => start_PB(i),
-- state out
fsm_o => fsm(i)
);
end generate G_S_CTRL_SM;
idle(NUM_STAGES+1) <= not outif_almost_full;
-------------------------------------------------------------------
-- Regs
-------------------------------------------------------------------
G_REG_SM : for i in 1 to NUM_STAGES generate
p_reg1 : process(CLK, RST)
begin
if RST = '1' then
Reg(i) <= C_SM_SETTINGS;
elsif CLK'event and CLK = '1' then
if start(i) = '1' then
if i = 1 then
Reg(i).x_cnt <= RSM.x_cnt;
Reg(i).y_cnt <= RSM.y_cnt;
Reg(i).cmp_idx <= RSM.cmp_idx;
else
Reg(i) <= Reg(i-1);
end if;
end if;
end if;
end process;
end generate G_REG_SM;
-------------------------------------------------------------------
-- Main_SM
-------------------------------------------------------------------
p_main_sm : process(CLK, RST)
begin
if RST = '1' then
main_state <= IDLES;
start(1) <= '0';
start1_d <= '0';
jpeg_ready <= '0';
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= (others => '0');
jpeg_busy <= '0';
RSM.cmp_idx <= (others => '0');
out_mux_ctrl_s <= '0';
out_mux_ctrl_s2 <= '0';
jfif_eoi <= '0';
out_mux_ctrl <= '0';
jfif_start <= '0';
elsif CLK'event and CLK = '1' then
start(1) <= '0';
start1_d <= start(1);
jpeg_ready <= '0';
jfif_start <= '0';
out_mux_ctrl_s2 <= out_mux_ctrl_s;
out_mux_ctrl <= out_mux_ctrl_s2;
case main_state is
-------------------------------
-- IDLE
-------------------------------
when IDLES =>
if sof = '1' then
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= (others => '0');
jfif_start <= '1';
out_mux_ctrl_s <= '0';
jfif_eoi <= '0';
main_state <= JFIF;
end if;
-------------------------------
-- JFIF
-------------------------------
when JFIF =>
if jfif_ready = '1' then
out_mux_ctrl_s <= '1';
main_state <= HORIZ;
end if;
-------------------------------
-- HORIZ
-------------------------------
when HORIZ =>
if RSM.x_cnt < unsigned(img_size_x) then
main_state <= COMP;
else
RSM.x_cnt <= (others => '0');
main_state <= VERT;
end if;
-------------------------------
-- COMP
-------------------------------
when COMP =>
if idle(1) = '1' and start(1) = '0' then
if RSM.cmp_idx < unsigned(CMP_MAX) then
start(1) <= '1';
else
RSM.cmp_idx <= (others => '0');
RSM.x_cnt <= RSM.x_cnt + 16;
main_state <= HORIZ;
end if;
end if;
-------------------------------
-- VERT
-------------------------------
when VERT =>
if RSM.y_cnt < unsigned(img_size_y)-8 then
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= RSM.y_cnt + 8;
main_state <= HORIZ;
else
if idle(NUM_STAGES+1 downto 1) = (NUM_STAGES+1 downto 1 => '1') then
main_state <= EOI;
jfif_eoi <= '1';
out_mux_ctrl_s <= '0';
jfif_start <= '1';
end if;
end if;
-------------------------------
-- VERT
-------------------------------
when EOI =>
if jfif_ready = '1' then
jpeg_ready <= '1';
main_state <= IDLES;
end if;
-------------------------------
-- others
-------------------------------
when others =>
main_state <= IDLES;
end case;
if start1_d = '1' then
RSM.cmp_idx <= RSM.cmp_idx + 1;
end if;
if main_state = IDLES then
jpeg_busy <= '0';
else
jpeg_busy <= '1';
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- Title : Predicts the next program counters values to be used
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : PC_Predictor.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-12-10
-- Last update: 2017-01-03
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-10 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cpu_defs.all;
use work.instruction_defs.all;
use work.instruction_record.all;
use work.instruction_prediction.all;
-------------------------------------------------------------------------------
entity PC_Predictor is
generic (
ADDR_WIDTH : integer;
STEP : integer
);
port (
clk : in std_logic;
rst : in std_logic;
stall_req : in std_logic;
-- Instruction tracker
--- Query to record new itag entries
o_itrack_req_pc1 : out std_logic;
o_itrack_req_pc2 : out std_logic;
o_itrack_pc1 : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
o_itrack_pc2 : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
o_itrack_pc1_instr_tag : out instr_tag_t;
o_itrack_pc2_instr_tag : out instr_tag_t;
--- Currently commited instruction
i_commited_instr_record : in instr_record;
i_commited_instr_tag : in instr_tag_t;
i_commited_jump_target : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
-- Misprediction inputs
i_mispredict : in std_logic;
i_mispredict_correct_pc : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
i_wrongly_taken_branch : in boolean;
i_wrongly_not_taken_branch : in boolean;
i_wrongly_taken_jump : in boolean;
i_wrongly_not_taken_jump : in boolean;
i_wrongly_predicted_is_branch : in boolean;
i_wrongly_predicted_is_jump : in boolean;
i_wrongly_predicted_is_stepped : in boolean;
-- Output predictions
o_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
o_pc_instr_tag : out instr_tag_t;
o_next_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
o_next_pc_instr_tag : out instr_tag_t;
o_next_next_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
-- Debug signals
o_dbg_prediction : out prediction_t
);
end entity PC_Predictor;
-------------------------------------------------------------------------------
architecture rtl of PC_Predictor is
subtype addr_t is std_logic_vector(ADDR_WIDTH - 1 downto 0);
-- Prediction cache
procedure update_prediction(i_address : in addr_t;
signal predictions : inout predictions_t;
prediction : in prediction_t) is
begin
for i in predictions'range loop
if predictions(i).valid and predictions(i).pc = i_address then
predictions(i) <= prediction;
end if;
end loop;
end procedure update_prediction;
function create_prediction(i_pc : addr_t;
i_next_pc : addr_t;
itag : instr_tag_t) return prediction_t is
variable o : prediction_t;
begin
o.valid := true;
o.pc := i_pc;
o.next_pc := i_next_pc;
o.is_ja_jr := itag.is_ja or itag.is_jr;
o.is_branch := itag.is_branch;
if itag.is_ja or itag.is_jr then
o.take_branch := 3;
elsif itag.is_branch then
if itag.is_branch_taken then
o.take_branch := 2;
else
o.take_branch := 1;
end if;
end if;
return o;
end function create_prediction;
function guess_next_pc(pc : addr_t;
predictions : predictions_t) return addr_t is
variable o : addr_t;
variable prediction : prediction_t;
begin
if is_prediction_hit(pc, predictions) then
prediction := get_prediction(pc, predictions);
o := prediction.next_pc;
else
o := std_logic_vector(unsigned(pc) + STEP);
end if;
return o;
end;
function guess_next_itag(pc : addr_t; itag : instr_tag_t;
predictions : predictions_t) return instr_tag_t is
variable o : instr_tag_t;
variable prediction : prediction_t;
begin
-- No real prediction yet, just a stepped PC
o.valid := itag.valid;
o.tag := itag.tag;
if is_prediction_hit(pc, predictions) then
prediction := get_prediction(pc, predictions);
o.is_branch := prediction.is_branch;
o.is_ja := prediction.is_ja_jr;
o.is_jr := prediction.is_ja_jr;
o.is_branch_taken := prediction.take_branch >= 2;
else
o.is_branch := false;
o.is_ja := false;
o.is_jr := false;
o.is_branch_taken := false;
end if;
return o;
end function guess_next_itag;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal alloc_itag : instr_tag_t;
-- Stall logic
signal stall : std_logic;
signal jump_while_stalling : boolean;
-- Forecasts
signal pc : addr_t;
signal pc_next : addr_t;
signal pc_itag : instr_tag_t;
signal pc_next_itag : instr_tag_t;
signal pc_next_next : addr_t;
-- Prediction data
signal predictions : predictions_t;
-- Aliaseses
alias irecord : instr_record is i_commited_instr_record;
alias itag : instr_tag_t is i_commited_instr_tag;
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
itag_allocator : process(clk, rst, stall) is
begin
if rst = '1' then
alloc_itag <= get_next_instr_tag(INSTR_TAG_FIRST_VALID, 2);
elsif rising_edge(clk) then
if i_mispredict = '1' then
alloc_itag <= get_next_instr_tag(alloc_itag, 2);
elsif stall = '0' then
alloc_itag <= get_next_instr_tag(alloc_itag, 1);
end if;
end if;
end process itag_allocator;
-- Instruction Tracker
--- Queries to create entries in itracker
--- Based on itags generated by itag_allocator
itrack_recorder : process(clk, rst, stall) is
begin
if rst = '1' then
o_itrack_req_pc1 <= '1';
o_itrack_req_pc2 <= '1';
elsif rising_edge(clk) then
if i_mispredict = '1' then
o_itrack_req_pc1 <= '1';
o_itrack_req_pc2 <= '1';
elsif stall = '1' then
o_itrack_req_pc1 <= '0';
o_itrack_req_pc2 <= '0';
else
o_itrack_req_pc1 <= '0';
o_itrack_req_pc2 <= '1';
end if;
end if;
end process itrack_recorder;
o_itrack_pc1 <= pc;
o_itrack_pc2 <= pc_next;
o_itrack_pc1_instr_tag <= pc_itag;
o_itrack_pc2_instr_tag <= pc_next_itag;
-- Program counter prediction
pc_predictor : process(clk, rst, stall) is
begin
if rst = '1' then
pc <= std_logic_vector(to_signed(0, ADDR_WIDTH));
pc_next <= std_logic_vector(to_signed(4, ADDR_WIDTH));
pc_itag <= INSTR_TAG_FIRST_VALID;
pc_next_itag <= get_next_instr_tag(INSTR_TAG_FIRST_VALID, 1);
jump_while_stalling <= false;
elsif rising_edge(clk) then
if i_mispredict = '1' then
-- Mispredict, break PC flow
--- So far, don't use any recorded branch history, use next 2 PCs
pc <= i_mispredict_correct_pc;
pc_next <= guess_next_pc(i_mispredict_correct_pc, predictions);
pc_itag <= alloc_itag;
pc_next_itag <= guess_next_itag(guess_next_pc(i_mispredict_correct_pc, predictions),
get_next_instr_tag(alloc_itag, 1), predictions);
if stall_req = '1' then
jump_while_stalling <= true;
else
jump_while_stalling <= false;
end if;
elsif stall = '1' then
else
-- No mispredict, normal stepped path
--- Shift pc_next* into pc*, and guess a new pc_next*
jump_while_stalling <= false;
pc <= pc_next;
pc_itag <= pc_next_itag;
pc_next <= guess_next_pc(pc_next, predictions);
pc_next_itag <= guess_next_itag(guess_next_pc(pc_next, predictions),
alloc_itag, predictions);
pc_next_next <= guess_next_pc(guess_next_pc(pc_next, predictions), predictions);
end if;
end if;
end process pc_predictor;
o_pc <= pc;
o_next_pc <= pc_next;
o_pc_instr_tag <= pc_itag;
o_next_pc_instr_tag <= pc_next_itag;
o_next_next_pc <= pc_next_next;
-- Stall logic
stall <=
'1' when stall_req = '1' or jump_while_stalling else '0';
predictor_updater : process(clk, rst, stall)
variable exists : prediction_t;
variable alloc_prediction_idx : natural range 0 to NB_PREDICTIONS - 1;
variable prediction : prediction_t;
variable hit : boolean;
begin
if rst = '1' then
alloc_prediction_idx := 0;
elsif itag.valid and rising_edge(clk) then
hit := is_prediction_hit(irecord.pc, predictions);
if hit then
-- Update a prediction
prediction := get_prediction(irecord.pc, predictions);
if i_wrongly_predicted_is_branch or i_wrongly_predicted_is_jump then
-- Remove a prediction entry
prediction.valid := false;
elsif itag.is_ja or itag.is_jr then
-- Replace a prediction entry
prediction := create_prediction(irecord.pc, i_commited_jump_target, itag);
elsif itag.is_branch and irecord.predict_next_pc = i_commited_jump_target then
-- Update a branch prediction
if itag.is_branch_taken then
if prediction.take_branch < 3 then
prediction.take_branch := prediction.take_branch + 1;
end if;
else
if prediction.take_branch > 0 then
prediction.take_branch := prediction.take_branch - 1;
end if;
end if;
elsif itag.is_branch_taken and irecord.predict_next_pc /= i_commited_jump_target then
-- Shouldn't be a pc disrupt: remove a prediction entry
prediction.valid := false;
elsif i_wrongly_not_taken_branch or i_wrongly_not_taken_jump then
-- Replace a prediction
prediction := create_prediction(irecord.pc, i_commited_jump_target, itag);
end if;
update_prediction(irecord.pc, predictions, prediction);
o_dbg_prediction <= prediction;
elsif i_wrongly_predicted_is_stepped then
-- Add a new prediction
predictions(alloc_prediction_idx) <= create_prediction(irecord.pc, i_commited_jump_target, itag);
o_dbg_prediction <= create_prediction(irecord.pc, i_commited_jump_target, itag);
alloc_prediction_idx := (alloc_prediction_idx + 1) mod NB_PREDICTIONS;
end if;
end if;
end process predictor_updater;
end architecture rtl;
-------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_prime_fifo_plain_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.k7_prime_fifo_plain_pkg.ALL;
ENTITY k7_prime_fifo_plain_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF k7_prime_fifo_plain_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:k7_prime_fifo_plain_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SEUdisp22 is
Port ( disp22 : in STD_LOGIC_VECTOR (21 downto 0);
SEUdisp22 : out STD_LOGIC_VECTOR (31 downto 0));
end SEUdisp22;
architecture Behavioral of SEUdisp22 is
begin
process(disp22)
begin
if disp22(21)='1' then
SEUdisp22<="1111111111"&disp22;
else
SEUdisp22<="0000000000"&disp22;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- adder.vhd
--
-- This file contains a simple N-bit full adder/subtractor using a carry chain.
-- The carry out of each bit is used to calculate that sum of the next bit.
-- This will slow the operation down slightly, but will reduce the amount of
-- logic required.
--
-- When 'Sub' is inactive, the operation 'OpA + OpB' is performed. If 'Sub' is
-- inactive, then 'OpA - OpB' is performed.
--
-- Note that the generic parameter N determines the number of bits of the input
-- and output, as well as the indices of the carry outputs. It should generally
-- be an even number for the half-carry to work properly.
--
-- The size of this cell is O(N). The speed of this cell is O(N).
--
-- Dependencies:
-- None.
--
-- Revision History:
-- 27 Jan 2015 Brian Kubisiak Initial revision.
-- 18 Jul 2015 Brian Kubisiak Small tweaks, updated documentation.
--
--------------------------------------------------------------------------------
-- bring in the necessary packages
library ieee;
use ieee.std_logic_1164.all;
-- Adder
--
-- parameters:
-- N (integer) Number of bits in the operands/result.
-- inputs:
-- Cin (std_logic) Carry/borrow for the adder.
-- OpA (std_logic_vector) First operand to the adder/subtractor.
-- OpB (std_logic_vector) Second operand to the adder/subtractor.
-- Sub (std_logic) Perform 'a - b' instead of 'a + b'. Active
-- high.
--
-- outputs:
-- Res (std_logic_vector) Result of the addition
-- Cout (std_logic) Carry out of bit N-1
-- Coutv (std_logic) Carry out of bit N-2, used for finding oflow
-- HCout (std_logic) Carry out of bit (N/2)-1 (half carry)
--
entity Adder is
-- N determines the size of the adder. Should be an even number.
generic (N : integer);
port (
-- Carry input.
Cin : in std_logic;
-- Indicates subtraction should be performed, active high.
Sub : in std_logic;
-- Operands on which to perform addition/subtraction.
OpA : in std_logic_vector(N-1 downto 0);
OpB : in std_logic_vector(N-1 downto 0);
-- Carry output of bit N-1.
Cout : out std_logic;
-- Carry out of bit N-2, used for finding overflow.
Coutv : out std_logic;
-- Carry out of bit (N/2)-1.
HCout : out std_logic;
-- Result of the addition/subtraction
Res : out std_logic_vector(N-1 downto 0)
);
end Adder;
--
-- This adder/subtractor uses a for-generate loop to create a carry chain of
-- full adders/subtractors. It saves the carry bits, so these can easily be
-- output.
--
architecture carry_chain of Adder is
-- This signal holds the carries into each bit
signal carry : std_logic_vector(N downto 0);
-- This is the second operand, inverted if subtracting
signal OpBmod: std_logic_vector(N-1 downto 0);
begin
-- Invert the carry input if subtracting
carry(0) <= Cin xor Sub;
-- Invert operand B if subtracting
InvB: for I in 0 to N-1 generate
OpBmod(I) <= OpB(I) xor Sub;
end generate InvB;
-- Chain together all the carry bits
FullAdder: for I in 0 to N-1 generate
-- Calculate each result bit based on the inputs and the carry in
Res(I) <= OpA(I) xor OpBmod(I) xor carry(I);
-- Base the next carry on the result
carry(I+1) <= ((OpA(I) xor OpBmod(I)) and carry(I))
or (OpA(I) and OpBmod(I));
end generate FullAdder;
-- Now we can just output the carry bits, inverted if we were subtracting
Cout <= carry(N) xor sub;
Coutv <= carry(N-1) xor sub;
HCout <= carry(N/2) xor sub;
end carry_chain;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_modulator/wave_generator.vhd
-- Created: 2018-02-20 12:01:50
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: wave_generator
-- Source Path: hdl_modulator/wave_generator
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_modulator_pac.ALL;
ENTITY wave_generator IS
PORT( u_u : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
x_x : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
y_y : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END wave_generator;
ARCHITECTURE rtl OF wave_generator IS
-- Constants
CONSTANT nc : vector_of_signed16(0 TO 511) :=
(to_signed(16#0000#, 16), to_signed(16#0032#, 16), to_signed(16#0065#, 16), to_signed(16#0097#, 16),
to_signed(16#00C9#, 16), to_signed(16#00FC#, 16), to_signed(16#012E#, 16), to_signed(16#0161#, 16),
to_signed(16#0193#, 16), to_signed(16#01C5#, 16), to_signed(16#01F8#, 16), to_signed(16#022A#, 16),
to_signed(16#025C#, 16), to_signed(16#028F#, 16), to_signed(16#02C1#, 16), to_signed(16#02F3#, 16),
to_signed(16#0325#, 16), to_signed(16#0358#, 16), to_signed(16#038A#, 16), to_signed(16#03BC#, 16),
to_signed(16#03EF#, 16), to_signed(16#0421#, 16), to_signed(16#0453#, 16), to_signed(16#0485#, 16),
to_signed(16#04B8#, 16), to_signed(16#04EA#, 16), to_signed(16#051C#, 16), to_signed(16#054E#, 16),
to_signed(16#0580#, 16), to_signed(16#05B3#, 16), to_signed(16#05E5#, 16), to_signed(16#0617#, 16),
to_signed(16#0649#, 16), to_signed(16#067B#, 16), to_signed(16#06AD#, 16), to_signed(16#06DF#, 16),
to_signed(16#0711#, 16), to_signed(16#0743#, 16), to_signed(16#0775#, 16), to_signed(16#07A7#, 16),
to_signed(16#07D9#, 16), to_signed(16#080B#, 16), to_signed(16#083D#, 16), to_signed(16#086F#, 16),
to_signed(16#08A1#, 16), to_signed(16#08D3#, 16), to_signed(16#0905#, 16), to_signed(16#0937#, 16),
to_signed(16#0969#, 16), to_signed(16#099B#, 16), to_signed(16#09CC#, 16), to_signed(16#09FE#, 16),
to_signed(16#0A30#, 16), to_signed(16#0A61#, 16), to_signed(16#0A93#, 16), to_signed(16#0AC5#, 16),
to_signed(16#0AF6#, 16), to_signed(16#0B28#, 16), to_signed(16#0B5A#, 16), to_signed(16#0B8B#, 16),
to_signed(16#0BBD#, 16), to_signed(16#0BEE#, 16), to_signed(16#0C20#, 16), to_signed(16#0C51#, 16),
to_signed(16#0C83#, 16), to_signed(16#0CB4#, 16), to_signed(16#0CE5#, 16), to_signed(16#0D17#, 16),
to_signed(16#0D48#, 16), to_signed(16#0D79#, 16), to_signed(16#0DAA#, 16), to_signed(16#0DDC#, 16),
to_signed(16#0E0D#, 16), to_signed(16#0E3E#, 16), to_signed(16#0E6F#, 16), to_signed(16#0EA0#, 16),
to_signed(16#0ED1#, 16), to_signed(16#0F02#, 16), to_signed(16#0F33#, 16), to_signed(16#0F64#, 16),
to_signed(16#0F95#, 16), to_signed(16#0FC5#, 16), to_signed(16#0FF6#, 16), to_signed(16#1027#, 16),
to_signed(16#1058#, 16), to_signed(16#1088#, 16), to_signed(16#10B9#, 16), to_signed(16#10EA#, 16),
to_signed(16#111A#, 16), to_signed(16#114B#, 16), to_signed(16#117B#, 16), to_signed(16#11AC#, 16),
to_signed(16#11DC#, 16), to_signed(16#120C#, 16), to_signed(16#123D#, 16), to_signed(16#126D#, 16),
to_signed(16#129D#, 16), to_signed(16#12CD#, 16), to_signed(16#12FD#, 16), to_signed(16#132D#, 16),
to_signed(16#135D#, 16), to_signed(16#138D#, 16), to_signed(16#13BD#, 16), to_signed(16#13ED#, 16),
to_signed(16#141D#, 16), to_signed(16#144D#, 16), to_signed(16#147D#, 16), to_signed(16#14AC#, 16),
to_signed(16#14DC#, 16), to_signed(16#150C#, 16), to_signed(16#153B#, 16), to_signed(16#156B#, 16),
to_signed(16#159A#, 16), to_signed(16#15C9#, 16), to_signed(16#15F9#, 16), to_signed(16#1628#, 16),
to_signed(16#1657#, 16), to_signed(16#1686#, 16), to_signed(16#16B5#, 16), to_signed(16#16E5#, 16),
to_signed(16#1714#, 16), to_signed(16#1742#, 16), to_signed(16#1771#, 16), to_signed(16#17A0#, 16),
to_signed(16#17CF#, 16), to_signed(16#17FE#, 16), to_signed(16#182C#, 16), to_signed(16#185B#, 16),
to_signed(16#188A#, 16), to_signed(16#18B8#, 16), to_signed(16#18E6#, 16), to_signed(16#1915#, 16),
to_signed(16#1943#, 16), to_signed(16#1971#, 16), to_signed(16#19A0#, 16), to_signed(16#19CE#, 16),
to_signed(16#19FC#, 16), to_signed(16#1A2A#, 16), to_signed(16#1A58#, 16), to_signed(16#1A85#, 16),
to_signed(16#1AB3#, 16), to_signed(16#1AE1#, 16), to_signed(16#1B0F#, 16), to_signed(16#1B3C#, 16),
to_signed(16#1B6A#, 16), to_signed(16#1B97#, 16), to_signed(16#1BC5#, 16), to_signed(16#1BF2#, 16),
to_signed(16#1C1F#, 16), to_signed(16#1C4D#, 16), to_signed(16#1C7A#, 16), to_signed(16#1CA7#, 16),
to_signed(16#1CD4#, 16), to_signed(16#1D01#, 16), to_signed(16#1D2E#, 16), to_signed(16#1D5A#, 16),
to_signed(16#1D87#, 16), to_signed(16#1DB4#, 16), to_signed(16#1DE0#, 16), to_signed(16#1E0D#, 16),
to_signed(16#1E39#, 16), to_signed(16#1E66#, 16), to_signed(16#1E92#, 16), to_signed(16#1EBE#, 16),
to_signed(16#1EEA#, 16), to_signed(16#1F16#, 16), to_signed(16#1F42#, 16), to_signed(16#1F6E#, 16),
to_signed(16#1F9A#, 16), to_signed(16#1FC6#, 16), to_signed(16#1FF1#, 16), to_signed(16#201D#, 16),
to_signed(16#2049#, 16), to_signed(16#2074#, 16), to_signed(16#209F#, 16), to_signed(16#20CB#, 16),
to_signed(16#20F6#, 16), to_signed(16#2121#, 16), to_signed(16#214C#, 16), to_signed(16#2177#, 16),
to_signed(16#21A2#, 16), to_signed(16#21CD#, 16), to_signed(16#21F7#, 16), to_signed(16#2222#, 16),
to_signed(16#224D#, 16), to_signed(16#2277#, 16), to_signed(16#22A2#, 16), to_signed(16#22CC#, 16),
to_signed(16#22F6#, 16), to_signed(16#2320#, 16), to_signed(16#234A#, 16), to_signed(16#2374#, 16),
to_signed(16#239E#, 16), to_signed(16#23C8#, 16), to_signed(16#23F2#, 16), to_signed(16#241B#, 16),
to_signed(16#2445#, 16), to_signed(16#246E#, 16), to_signed(16#2498#, 16), to_signed(16#24C1#, 16),
to_signed(16#24EA#, 16), to_signed(16#2513#, 16), to_signed(16#253C#, 16), to_signed(16#2565#, 16),
to_signed(16#258E#, 16), to_signed(16#25B7#, 16), to_signed(16#25DF#, 16), to_signed(16#2608#, 16),
to_signed(16#2630#, 16), to_signed(16#2659#, 16), to_signed(16#2681#, 16), to_signed(16#26A9#, 16),
to_signed(16#26D1#, 16), to_signed(16#26F9#, 16), to_signed(16#2721#, 16), to_signed(16#2749#, 16),
to_signed(16#2771#, 16), to_signed(16#2798#, 16), to_signed(16#27C0#, 16), to_signed(16#27E7#, 16),
to_signed(16#280F#, 16), to_signed(16#2836#, 16), to_signed(16#285D#, 16), to_signed(16#2884#, 16),
to_signed(16#28AB#, 16), to_signed(16#28D2#, 16), to_signed(16#28F9#, 16), to_signed(16#291F#, 16),
to_signed(16#2946#, 16), to_signed(16#296C#, 16), to_signed(16#2992#, 16), to_signed(16#29B9#, 16),
to_signed(16#29DF#, 16), to_signed(16#2A05#, 16), to_signed(16#2A2B#, 16), to_signed(16#2A51#, 16),
to_signed(16#2A76#, 16), to_signed(16#2A9C#, 16), to_signed(16#2AC2#, 16), to_signed(16#2AE7#, 16),
to_signed(16#2B0C#, 16), to_signed(16#2B32#, 16), to_signed(16#2B57#, 16), to_signed(16#2B7C#, 16),
to_signed(16#2BA1#, 16), to_signed(16#2BC5#, 16), to_signed(16#2BEA#, 16), to_signed(16#2C0F#, 16),
to_signed(16#2C33#, 16), to_signed(16#2C57#, 16), to_signed(16#2C7C#, 16), to_signed(16#2CA0#, 16),
to_signed(16#2CC4#, 16), to_signed(16#2CE8#, 16), to_signed(16#2D0C#, 16), to_signed(16#2D2F#, 16),
to_signed(16#2D53#, 16), to_signed(16#2D77#, 16), to_signed(16#2D9A#, 16), to_signed(16#2DBD#, 16),
to_signed(16#2DE0#, 16), to_signed(16#2E03#, 16), to_signed(16#2E26#, 16), to_signed(16#2E49#, 16),
to_signed(16#2E6C#, 16), to_signed(16#2E8F#, 16), to_signed(16#2EB1#, 16), to_signed(16#2ED3#, 16),
to_signed(16#2EF6#, 16), to_signed(16#2F18#, 16), to_signed(16#2F3A#, 16), to_signed(16#2F5C#, 16),
to_signed(16#2F7E#, 16), to_signed(16#2F9F#, 16), to_signed(16#2FC1#, 16), to_signed(16#2FE2#, 16),
to_signed(16#3004#, 16), to_signed(16#3025#, 16), to_signed(16#3046#, 16), to_signed(16#3067#, 16),
to_signed(16#3088#, 16), to_signed(16#30A9#, 16), to_signed(16#30CA#, 16), to_signed(16#30EA#, 16),
to_signed(16#310A#, 16), to_signed(16#312B#, 16), to_signed(16#314B#, 16), to_signed(16#316B#, 16),
to_signed(16#318B#, 16), to_signed(16#31AB#, 16), to_signed(16#31CA#, 16), to_signed(16#31EA#, 16),
to_signed(16#320A#, 16), to_signed(16#3229#, 16), to_signed(16#3248#, 16), to_signed(16#3267#, 16),
to_signed(16#3286#, 16), to_signed(16#32A5#, 16), to_signed(16#32C4#, 16), to_signed(16#32E2#, 16),
to_signed(16#3301#, 16), to_signed(16#331F#, 16), to_signed(16#333D#, 16), to_signed(16#335C#, 16),
to_signed(16#337A#, 16), to_signed(16#3397#, 16), to_signed(16#33B5#, 16), to_signed(16#33D3#, 16),
to_signed(16#33F0#, 16), to_signed(16#340E#, 16), to_signed(16#342B#, 16), to_signed(16#3448#, 16),
to_signed(16#3465#, 16), to_signed(16#3482#, 16), to_signed(16#349F#, 16), to_signed(16#34BB#, 16),
to_signed(16#34D8#, 16), to_signed(16#34F4#, 16), to_signed(16#3510#, 16), to_signed(16#352C#, 16),
to_signed(16#3548#, 16), to_signed(16#3564#, 16), to_signed(16#3580#, 16), to_signed(16#359B#, 16),
to_signed(16#35B7#, 16), to_signed(16#35D2#, 16), to_signed(16#35ED#, 16), to_signed(16#3608#, 16),
to_signed(16#3623#, 16), to_signed(16#363E#, 16), to_signed(16#3659#, 16), to_signed(16#3673#, 16),
to_signed(16#368E#, 16), to_signed(16#36A8#, 16), to_signed(16#36C2#, 16), to_signed(16#36DC#, 16),
to_signed(16#36F6#, 16), to_signed(16#3710#, 16), to_signed(16#3729#, 16), to_signed(16#3743#, 16),
to_signed(16#375C#, 16), to_signed(16#3775#, 16), to_signed(16#378E#, 16), to_signed(16#37A7#, 16),
to_signed(16#37C0#, 16), to_signed(16#37D9#, 16), to_signed(16#37F1#, 16), to_signed(16#380A#, 16),
to_signed(16#3822#, 16), to_signed(16#383A#, 16), to_signed(16#3852#, 16), to_signed(16#386A#, 16),
to_signed(16#3882#, 16), to_signed(16#3899#, 16), to_signed(16#38B1#, 16), to_signed(16#38C8#, 16),
to_signed(16#38DF#, 16), to_signed(16#38F6#, 16), to_signed(16#390D#, 16), to_signed(16#3924#, 16),
to_signed(16#393A#, 16), to_signed(16#3951#, 16), to_signed(16#3967#, 16), to_signed(16#397D#, 16),
to_signed(16#3994#, 16), to_signed(16#39A9#, 16), to_signed(16#39BF#, 16), to_signed(16#39D5#, 16),
to_signed(16#39EA#, 16), to_signed(16#3A00#, 16), to_signed(16#3A15#, 16), to_signed(16#3A2A#, 16),
to_signed(16#3A3F#, 16), to_signed(16#3A54#, 16), to_signed(16#3A68#, 16), to_signed(16#3A7D#, 16),
to_signed(16#3A91#, 16), to_signed(16#3AA6#, 16), to_signed(16#3ABA#, 16), to_signed(16#3ACE#, 16),
to_signed(16#3AE1#, 16), to_signed(16#3AF5#, 16), to_signed(16#3B09#, 16), to_signed(16#3B1C#, 16),
to_signed(16#3B2F#, 16), to_signed(16#3B42#, 16), to_signed(16#3B55#, 16), to_signed(16#3B68#, 16),
to_signed(16#3B7B#, 16), to_signed(16#3B8D#, 16), to_signed(16#3BA0#, 16), to_signed(16#3BB2#, 16),
to_signed(16#3BC4#, 16), to_signed(16#3BD6#, 16), to_signed(16#3BE8#, 16), to_signed(16#3BF9#, 16),
to_signed(16#3C0B#, 16), to_signed(16#3C1C#, 16), to_signed(16#3C2D#, 16), to_signed(16#3C3F#, 16),
to_signed(16#3C4F#, 16), to_signed(16#3C60#, 16), to_signed(16#3C71#, 16), to_signed(16#3C81#, 16),
to_signed(16#3C92#, 16), to_signed(16#3CA2#, 16), to_signed(16#3CB2#, 16), to_signed(16#3CC2#, 16),
to_signed(16#3CD2#, 16), to_signed(16#3CE1#, 16), to_signed(16#3CF1#, 16), to_signed(16#3D00#, 16),
to_signed(16#3D0F#, 16), to_signed(16#3D1E#, 16), to_signed(16#3D2D#, 16), to_signed(16#3D3C#, 16),
to_signed(16#3D4A#, 16), to_signed(16#3D59#, 16), to_signed(16#3D67#, 16), to_signed(16#3D75#, 16),
to_signed(16#3D83#, 16), to_signed(16#3D91#, 16), to_signed(16#3D9F#, 16), to_signed(16#3DAC#, 16),
to_signed(16#3DBA#, 16), to_signed(16#3DC7#, 16), to_signed(16#3DD4#, 16), to_signed(16#3DE1#, 16),
to_signed(16#3DEE#, 16), to_signed(16#3DFA#, 16), to_signed(16#3E07#, 16), to_signed(16#3E13#, 16),
to_signed(16#3E1F#, 16), to_signed(16#3E2B#, 16), to_signed(16#3E37#, 16), to_signed(16#3E43#, 16),
to_signed(16#3E4F#, 16), to_signed(16#3E5A#, 16), to_signed(16#3E65#, 16), to_signed(16#3E70#, 16),
to_signed(16#3E7B#, 16), to_signed(16#3E86#, 16), to_signed(16#3E91#, 16), to_signed(16#3E9B#, 16),
to_signed(16#3EA6#, 16), to_signed(16#3EB0#, 16), to_signed(16#3EBA#, 16), to_signed(16#3EC4#, 16),
to_signed(16#3ECE#, 16), to_signed(16#3ED7#, 16), to_signed(16#3EE1#, 16), to_signed(16#3EEA#, 16),
to_signed(16#3EF3#, 16), to_signed(16#3EFC#, 16), to_signed(16#3F05#, 16), to_signed(16#3F0E#, 16),
to_signed(16#3F16#, 16), to_signed(16#3F1F#, 16), to_signed(16#3F27#, 16), to_signed(16#3F2F#, 16),
to_signed(16#3F37#, 16), to_signed(16#3F3F#, 16), to_signed(16#3F46#, 16), to_signed(16#3F4E#, 16),
to_signed(16#3F55#, 16), to_signed(16#3F5C#, 16), to_signed(16#3F63#, 16), to_signed(16#3F6A#, 16),
to_signed(16#3F71#, 16), to_signed(16#3F78#, 16), to_signed(16#3F7E#, 16), to_signed(16#3F84#, 16),
to_signed(16#3F8A#, 16), to_signed(16#3F90#, 16), to_signed(16#3F96#, 16), to_signed(16#3F9C#, 16),
to_signed(16#3FA1#, 16), to_signed(16#3FA7#, 16), to_signed(16#3FAC#, 16), to_signed(16#3FB1#, 16),
to_signed(16#3FB6#, 16), to_signed(16#3FBA#, 16), to_signed(16#3FBF#, 16), to_signed(16#3FC3#, 16),
to_signed(16#3FC8#, 16), to_signed(16#3FCC#, 16), to_signed(16#3FD0#, 16), to_signed(16#3FD3#, 16),
to_signed(16#3FD7#, 16), to_signed(16#3FDB#, 16), to_signed(16#3FDE#, 16), to_signed(16#3FE1#, 16),
to_signed(16#3FE4#, 16), to_signed(16#3FE7#, 16), to_signed(16#3FEA#, 16), to_signed(16#3FEC#, 16),
to_signed(16#3FEF#, 16), to_signed(16#3FF1#, 16), to_signed(16#3FF3#, 16), to_signed(16#3FF5#, 16),
to_signed(16#3FF7#, 16), to_signed(16#3FF8#, 16), to_signed(16#3FFA#, 16), to_signed(16#3FFB#, 16),
to_signed(16#3FFC#, 16), to_signed(16#3FFD#, 16), to_signed(16#3FFE#, 16), to_signed(16#3FFF#, 16),
to_signed(16#3FFF#, 16), to_signed(16#4000#, 16), to_signed(16#4000#, 16), to_signed(16#4000#, 16));
-- sfix16 [512]
CONSTANT nc_2 : vector_of_signed16(0 TO 511) :=
(to_signed(16#0000#, 16), to_signed(16#0032#, 16), to_signed(16#0065#, 16), to_signed(16#0097#, 16),
to_signed(16#00C9#, 16), to_signed(16#00FC#, 16), to_signed(16#012E#, 16), to_signed(16#0161#, 16),
to_signed(16#0193#, 16), to_signed(16#01C5#, 16), to_signed(16#01F8#, 16), to_signed(16#022A#, 16),
to_signed(16#025C#, 16), to_signed(16#028F#, 16), to_signed(16#02C1#, 16), to_signed(16#02F3#, 16),
to_signed(16#0325#, 16), to_signed(16#0358#, 16), to_signed(16#038A#, 16), to_signed(16#03BC#, 16),
to_signed(16#03EF#, 16), to_signed(16#0421#, 16), to_signed(16#0453#, 16), to_signed(16#0485#, 16),
to_signed(16#04B8#, 16), to_signed(16#04EA#, 16), to_signed(16#051C#, 16), to_signed(16#054E#, 16),
to_signed(16#0580#, 16), to_signed(16#05B3#, 16), to_signed(16#05E5#, 16), to_signed(16#0617#, 16),
to_signed(16#0649#, 16), to_signed(16#067B#, 16), to_signed(16#06AD#, 16), to_signed(16#06DF#, 16),
to_signed(16#0711#, 16), to_signed(16#0743#, 16), to_signed(16#0775#, 16), to_signed(16#07A7#, 16),
to_signed(16#07D9#, 16), to_signed(16#080B#, 16), to_signed(16#083D#, 16), to_signed(16#086F#, 16),
to_signed(16#08A1#, 16), to_signed(16#08D3#, 16), to_signed(16#0905#, 16), to_signed(16#0937#, 16),
to_signed(16#0969#, 16), to_signed(16#099B#, 16), to_signed(16#09CC#, 16), to_signed(16#09FE#, 16),
to_signed(16#0A30#, 16), to_signed(16#0A61#, 16), to_signed(16#0A93#, 16), to_signed(16#0AC5#, 16),
to_signed(16#0AF6#, 16), to_signed(16#0B28#, 16), to_signed(16#0B5A#, 16), to_signed(16#0B8B#, 16),
to_signed(16#0BBD#, 16), to_signed(16#0BEE#, 16), to_signed(16#0C20#, 16), to_signed(16#0C51#, 16),
to_signed(16#0C83#, 16), to_signed(16#0CB4#, 16), to_signed(16#0CE5#, 16), to_signed(16#0D17#, 16),
to_signed(16#0D48#, 16), to_signed(16#0D79#, 16), to_signed(16#0DAA#, 16), to_signed(16#0DDC#, 16),
to_signed(16#0E0D#, 16), to_signed(16#0E3E#, 16), to_signed(16#0E6F#, 16), to_signed(16#0EA0#, 16),
to_signed(16#0ED1#, 16), to_signed(16#0F02#, 16), to_signed(16#0F33#, 16), to_signed(16#0F64#, 16),
to_signed(16#0F95#, 16), to_signed(16#0FC5#, 16), to_signed(16#0FF6#, 16), to_signed(16#1027#, 16),
to_signed(16#1058#, 16), to_signed(16#1088#, 16), to_signed(16#10B9#, 16), to_signed(16#10EA#, 16),
to_signed(16#111A#, 16), to_signed(16#114B#, 16), to_signed(16#117B#, 16), to_signed(16#11AC#, 16),
to_signed(16#11DC#, 16), to_signed(16#120C#, 16), to_signed(16#123D#, 16), to_signed(16#126D#, 16),
to_signed(16#129D#, 16), to_signed(16#12CD#, 16), to_signed(16#12FD#, 16), to_signed(16#132D#, 16),
to_signed(16#135D#, 16), to_signed(16#138D#, 16), to_signed(16#13BD#, 16), to_signed(16#13ED#, 16),
to_signed(16#141D#, 16), to_signed(16#144D#, 16), to_signed(16#147D#, 16), to_signed(16#14AC#, 16),
to_signed(16#14DC#, 16), to_signed(16#150C#, 16), to_signed(16#153B#, 16), to_signed(16#156B#, 16),
to_signed(16#159A#, 16), to_signed(16#15C9#, 16), to_signed(16#15F9#, 16), to_signed(16#1628#, 16),
to_signed(16#1657#, 16), to_signed(16#1686#, 16), to_signed(16#16B5#, 16), to_signed(16#16E5#, 16),
to_signed(16#1714#, 16), to_signed(16#1742#, 16), to_signed(16#1771#, 16), to_signed(16#17A0#, 16),
to_signed(16#17CF#, 16), to_signed(16#17FE#, 16), to_signed(16#182C#, 16), to_signed(16#185B#, 16),
to_signed(16#188A#, 16), to_signed(16#18B8#, 16), to_signed(16#18E6#, 16), to_signed(16#1915#, 16),
to_signed(16#1943#, 16), to_signed(16#1971#, 16), to_signed(16#19A0#, 16), to_signed(16#19CE#, 16),
to_signed(16#19FC#, 16), to_signed(16#1A2A#, 16), to_signed(16#1A58#, 16), to_signed(16#1A85#, 16),
to_signed(16#1AB3#, 16), to_signed(16#1AE1#, 16), to_signed(16#1B0F#, 16), to_signed(16#1B3C#, 16),
to_signed(16#1B6A#, 16), to_signed(16#1B97#, 16), to_signed(16#1BC5#, 16), to_signed(16#1BF2#, 16),
to_signed(16#1C1F#, 16), to_signed(16#1C4D#, 16), to_signed(16#1C7A#, 16), to_signed(16#1CA7#, 16),
to_signed(16#1CD4#, 16), to_signed(16#1D01#, 16), to_signed(16#1D2E#, 16), to_signed(16#1D5A#, 16),
to_signed(16#1D87#, 16), to_signed(16#1DB4#, 16), to_signed(16#1DE0#, 16), to_signed(16#1E0D#, 16),
to_signed(16#1E39#, 16), to_signed(16#1E66#, 16), to_signed(16#1E92#, 16), to_signed(16#1EBE#, 16),
to_signed(16#1EEA#, 16), to_signed(16#1F16#, 16), to_signed(16#1F42#, 16), to_signed(16#1F6E#, 16),
to_signed(16#1F9A#, 16), to_signed(16#1FC6#, 16), to_signed(16#1FF1#, 16), to_signed(16#201D#, 16),
to_signed(16#2049#, 16), to_signed(16#2074#, 16), to_signed(16#209F#, 16), to_signed(16#20CB#, 16),
to_signed(16#20F6#, 16), to_signed(16#2121#, 16), to_signed(16#214C#, 16), to_signed(16#2177#, 16),
to_signed(16#21A2#, 16), to_signed(16#21CD#, 16), to_signed(16#21F7#, 16), to_signed(16#2222#, 16),
to_signed(16#224D#, 16), to_signed(16#2277#, 16), to_signed(16#22A2#, 16), to_signed(16#22CC#, 16),
to_signed(16#22F6#, 16), to_signed(16#2320#, 16), to_signed(16#234A#, 16), to_signed(16#2374#, 16),
to_signed(16#239E#, 16), to_signed(16#23C8#, 16), to_signed(16#23F2#, 16), to_signed(16#241B#, 16),
to_signed(16#2445#, 16), to_signed(16#246E#, 16), to_signed(16#2498#, 16), to_signed(16#24C1#, 16),
to_signed(16#24EA#, 16), to_signed(16#2513#, 16), to_signed(16#253C#, 16), to_signed(16#2565#, 16),
to_signed(16#258E#, 16), to_signed(16#25B7#, 16), to_signed(16#25DF#, 16), to_signed(16#2608#, 16),
to_signed(16#2630#, 16), to_signed(16#2659#, 16), to_signed(16#2681#, 16), to_signed(16#26A9#, 16),
to_signed(16#26D1#, 16), to_signed(16#26F9#, 16), to_signed(16#2721#, 16), to_signed(16#2749#, 16),
to_signed(16#2771#, 16), to_signed(16#2798#, 16), to_signed(16#27C0#, 16), to_signed(16#27E7#, 16),
to_signed(16#280F#, 16), to_signed(16#2836#, 16), to_signed(16#285D#, 16), to_signed(16#2884#, 16),
to_signed(16#28AB#, 16), to_signed(16#28D2#, 16), to_signed(16#28F9#, 16), to_signed(16#291F#, 16),
to_signed(16#2946#, 16), to_signed(16#296C#, 16), to_signed(16#2992#, 16), to_signed(16#29B9#, 16),
to_signed(16#29DF#, 16), to_signed(16#2A05#, 16), to_signed(16#2A2B#, 16), to_signed(16#2A51#, 16),
to_signed(16#2A76#, 16), to_signed(16#2A9C#, 16), to_signed(16#2AC2#, 16), to_signed(16#2AE7#, 16),
to_signed(16#2B0C#, 16), to_signed(16#2B32#, 16), to_signed(16#2B57#, 16), to_signed(16#2B7C#, 16),
to_signed(16#2BA1#, 16), to_signed(16#2BC5#, 16), to_signed(16#2BEA#, 16), to_signed(16#2C0F#, 16),
to_signed(16#2C33#, 16), to_signed(16#2C57#, 16), to_signed(16#2C7C#, 16), to_signed(16#2CA0#, 16),
to_signed(16#2CC4#, 16), to_signed(16#2CE8#, 16), to_signed(16#2D0C#, 16), to_signed(16#2D2F#, 16),
to_signed(16#2D53#, 16), to_signed(16#2D77#, 16), to_signed(16#2D9A#, 16), to_signed(16#2DBD#, 16),
to_signed(16#2DE0#, 16), to_signed(16#2E03#, 16), to_signed(16#2E26#, 16), to_signed(16#2E49#, 16),
to_signed(16#2E6C#, 16), to_signed(16#2E8F#, 16), to_signed(16#2EB1#, 16), to_signed(16#2ED3#, 16),
to_signed(16#2EF6#, 16), to_signed(16#2F18#, 16), to_signed(16#2F3A#, 16), to_signed(16#2F5C#, 16),
to_signed(16#2F7E#, 16), to_signed(16#2F9F#, 16), to_signed(16#2FC1#, 16), to_signed(16#2FE2#, 16),
to_signed(16#3004#, 16), to_signed(16#3025#, 16), to_signed(16#3046#, 16), to_signed(16#3067#, 16),
to_signed(16#3088#, 16), to_signed(16#30A9#, 16), to_signed(16#30CA#, 16), to_signed(16#30EA#, 16),
to_signed(16#310A#, 16), to_signed(16#312B#, 16), to_signed(16#314B#, 16), to_signed(16#316B#, 16),
to_signed(16#318B#, 16), to_signed(16#31AB#, 16), to_signed(16#31CA#, 16), to_signed(16#31EA#, 16),
to_signed(16#320A#, 16), to_signed(16#3229#, 16), to_signed(16#3248#, 16), to_signed(16#3267#, 16),
to_signed(16#3286#, 16), to_signed(16#32A5#, 16), to_signed(16#32C4#, 16), to_signed(16#32E2#, 16),
to_signed(16#3301#, 16), to_signed(16#331F#, 16), to_signed(16#333D#, 16), to_signed(16#335C#, 16),
to_signed(16#337A#, 16), to_signed(16#3397#, 16), to_signed(16#33B5#, 16), to_signed(16#33D3#, 16),
to_signed(16#33F0#, 16), to_signed(16#340E#, 16), to_signed(16#342B#, 16), to_signed(16#3448#, 16),
to_signed(16#3465#, 16), to_signed(16#3482#, 16), to_signed(16#349F#, 16), to_signed(16#34BB#, 16),
to_signed(16#34D8#, 16), to_signed(16#34F4#, 16), to_signed(16#3510#, 16), to_signed(16#352C#, 16),
to_signed(16#3548#, 16), to_signed(16#3564#, 16), to_signed(16#3580#, 16), to_signed(16#359B#, 16),
to_signed(16#35B7#, 16), to_signed(16#35D2#, 16), to_signed(16#35ED#, 16), to_signed(16#3608#, 16),
to_signed(16#3623#, 16), to_signed(16#363E#, 16), to_signed(16#3659#, 16), to_signed(16#3673#, 16),
to_signed(16#368E#, 16), to_signed(16#36A8#, 16), to_signed(16#36C2#, 16), to_signed(16#36DC#, 16),
to_signed(16#36F6#, 16), to_signed(16#3710#, 16), to_signed(16#3729#, 16), to_signed(16#3743#, 16),
to_signed(16#375C#, 16), to_signed(16#3775#, 16), to_signed(16#378E#, 16), to_signed(16#37A7#, 16),
to_signed(16#37C0#, 16), to_signed(16#37D9#, 16), to_signed(16#37F1#, 16), to_signed(16#380A#, 16),
to_signed(16#3822#, 16), to_signed(16#383A#, 16), to_signed(16#3852#, 16), to_signed(16#386A#, 16),
to_signed(16#3882#, 16), to_signed(16#3899#, 16), to_signed(16#38B1#, 16), to_signed(16#38C8#, 16),
to_signed(16#38DF#, 16), to_signed(16#38F6#, 16), to_signed(16#390D#, 16), to_signed(16#3924#, 16),
to_signed(16#393A#, 16), to_signed(16#3951#, 16), to_signed(16#3967#, 16), to_signed(16#397D#, 16),
to_signed(16#3994#, 16), to_signed(16#39A9#, 16), to_signed(16#39BF#, 16), to_signed(16#39D5#, 16),
to_signed(16#39EA#, 16), to_signed(16#3A00#, 16), to_signed(16#3A15#, 16), to_signed(16#3A2A#, 16),
to_signed(16#3A3F#, 16), to_signed(16#3A54#, 16), to_signed(16#3A68#, 16), to_signed(16#3A7D#, 16),
to_signed(16#3A91#, 16), to_signed(16#3AA6#, 16), to_signed(16#3ABA#, 16), to_signed(16#3ACE#, 16),
to_signed(16#3AE1#, 16), to_signed(16#3AF5#, 16), to_signed(16#3B09#, 16), to_signed(16#3B1C#, 16),
to_signed(16#3B2F#, 16), to_signed(16#3B42#, 16), to_signed(16#3B55#, 16), to_signed(16#3B68#, 16),
to_signed(16#3B7B#, 16), to_signed(16#3B8D#, 16), to_signed(16#3BA0#, 16), to_signed(16#3BB2#, 16),
to_signed(16#3BC4#, 16), to_signed(16#3BD6#, 16), to_signed(16#3BE8#, 16), to_signed(16#3BF9#, 16),
to_signed(16#3C0B#, 16), to_signed(16#3C1C#, 16), to_signed(16#3C2D#, 16), to_signed(16#3C3F#, 16),
to_signed(16#3C4F#, 16), to_signed(16#3C60#, 16), to_signed(16#3C71#, 16), to_signed(16#3C81#, 16),
to_signed(16#3C92#, 16), to_signed(16#3CA2#, 16), to_signed(16#3CB2#, 16), to_signed(16#3CC2#, 16),
to_signed(16#3CD2#, 16), to_signed(16#3CE1#, 16), to_signed(16#3CF1#, 16), to_signed(16#3D00#, 16),
to_signed(16#3D0F#, 16), to_signed(16#3D1E#, 16), to_signed(16#3D2D#, 16), to_signed(16#3D3C#, 16),
to_signed(16#3D4A#, 16), to_signed(16#3D59#, 16), to_signed(16#3D67#, 16), to_signed(16#3D75#, 16),
to_signed(16#3D83#, 16), to_signed(16#3D91#, 16), to_signed(16#3D9F#, 16), to_signed(16#3DAC#, 16),
to_signed(16#3DBA#, 16), to_signed(16#3DC7#, 16), to_signed(16#3DD4#, 16), to_signed(16#3DE1#, 16),
to_signed(16#3DEE#, 16), to_signed(16#3DFA#, 16), to_signed(16#3E07#, 16), to_signed(16#3E13#, 16),
to_signed(16#3E1F#, 16), to_signed(16#3E2B#, 16), to_signed(16#3E37#, 16), to_signed(16#3E43#, 16),
to_signed(16#3E4F#, 16), to_signed(16#3E5A#, 16), to_signed(16#3E65#, 16), to_signed(16#3E70#, 16),
to_signed(16#3E7B#, 16), to_signed(16#3E86#, 16), to_signed(16#3E91#, 16), to_signed(16#3E9B#, 16),
to_signed(16#3EA6#, 16), to_signed(16#3EB0#, 16), to_signed(16#3EBA#, 16), to_signed(16#3EC4#, 16),
to_signed(16#3ECE#, 16), to_signed(16#3ED7#, 16), to_signed(16#3EE1#, 16), to_signed(16#3EEA#, 16),
to_signed(16#3EF3#, 16), to_signed(16#3EFC#, 16), to_signed(16#3F05#, 16), to_signed(16#3F0E#, 16),
to_signed(16#3F16#, 16), to_signed(16#3F1F#, 16), to_signed(16#3F27#, 16), to_signed(16#3F2F#, 16),
to_signed(16#3F37#, 16), to_signed(16#3F3F#, 16), to_signed(16#3F46#, 16), to_signed(16#3F4E#, 16),
to_signed(16#3F55#, 16), to_signed(16#3F5C#, 16), to_signed(16#3F63#, 16), to_signed(16#3F6A#, 16),
to_signed(16#3F71#, 16), to_signed(16#3F78#, 16), to_signed(16#3F7E#, 16), to_signed(16#3F84#, 16),
to_signed(16#3F8A#, 16), to_signed(16#3F90#, 16), to_signed(16#3F96#, 16), to_signed(16#3F9C#, 16),
to_signed(16#3FA1#, 16), to_signed(16#3FA7#, 16), to_signed(16#3FAC#, 16), to_signed(16#3FB1#, 16),
to_signed(16#3FB6#, 16), to_signed(16#3FBA#, 16), to_signed(16#3FBF#, 16), to_signed(16#3FC3#, 16),
to_signed(16#3FC8#, 16), to_signed(16#3FCC#, 16), to_signed(16#3FD0#, 16), to_signed(16#3FD3#, 16),
to_signed(16#3FD7#, 16), to_signed(16#3FDB#, 16), to_signed(16#3FDE#, 16), to_signed(16#3FE1#, 16),
to_signed(16#3FE4#, 16), to_signed(16#3FE7#, 16), to_signed(16#3FEA#, 16), to_signed(16#3FEC#, 16),
to_signed(16#3FEF#, 16), to_signed(16#3FF1#, 16), to_signed(16#3FF3#, 16), to_signed(16#3FF5#, 16),
to_signed(16#3FF7#, 16), to_signed(16#3FF8#, 16), to_signed(16#3FFA#, 16), to_signed(16#3FFB#, 16),
to_signed(16#3FFC#, 16), to_signed(16#3FFD#, 16), to_signed(16#3FFE#, 16), to_signed(16#3FFF#, 16),
to_signed(16#3FFF#, 16), to_signed(16#4000#, 16), to_signed(16#4000#, 16), to_signed(16#4000#, 16));
-- sfix16 [512]
-- Signals
SIGNAL u_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL insig_out1 : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL Point50_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL LTEp50_1_cast : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL LTEp50_relop1 : std_logic;
SIGNAL pow2switch_out1 : std_logic;
SIGNAL Amp50_sub_cast : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp50_sub_cast_1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp50_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL insig_out1_dtc : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL QuadHandle1_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Point25_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL LTEp25_1_cast : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL LTEp25_relop1 : std_logic;
SIGNAL p50mA_sub_cast : signed(17 DOWNTO 0); -- sfix18_En16
SIGNAL p50mA_sub_cast_1 : signed(17 DOWNTO 0); -- sfix18_En16
SIGNAL p50mA_out1 : signed(17 DOWNTO 0); -- sfix18_En16
SIGNAL p50mA_out1_dtc : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL QuadHandle1_out1_dtc : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL QuadHandle2_out1 : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL CastU16En2_out1 : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL CastU16En4_out1 : unsigned(9 DOWNTO 0); -- ufix10
SIGNAL x4_out1 : unsigned(9 DOWNTO 0); -- ufix10
SIGNAL CastU16En3_out1 : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL Switch_out1 : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL Look_Up_Table_k : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL Look_Up_Table_out1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Negate_cast : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Negate_cast_1 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Negate_out1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Sine : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Sine_1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Sine_2 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL insig_out1_1 : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL Point25_out1_1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL LTEp25_1_cast_1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL LTEp25_relop1_1 : std_logic;
SIGNAL Point75_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL GTEp75_1_cast : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL GTEp75_relop1 : std_logic;
SIGNAL alpha1st_or_4th_Quad_bool : std_logic;
SIGNAL alpha1st_or_4th_Quad_out1 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL pow2switch_out1_1 : std_logic;
SIGNAL Point50_out1_1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL p75mA_sub_cast : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL p75mA_sub_cast_1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL p75mA_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp75_sub_cast : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp75_sub_cast_1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp75_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp25_sub_cast : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp25_sub_cast_1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp25_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL p25mA_sub_cast : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL p25mA_sub_cast_1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL p25mA_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL LTEp50_1_cast_1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL LTEp50_relop1_1 : std_logic;
SIGNAL QuadHandle1b_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL QuadHandle1b_out1_dtc : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL QuadHandle1a_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL QuadHandle1a_out1_dtc : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL QuadHandle2_out1_1 : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL CastU16En1_out1 : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL CastU16En3_out1_1 : unsigned(9 DOWNTO 0); -- ufix10
SIGNAL x4_out1_1 : unsigned(9 DOWNTO 0); -- ufix10
SIGNAL CastU16En2_out1_1 : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL Switch_out1_1 : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL Look_Up_Table_k_1 : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL Look_Up_Table_out1_1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Negate_cast_2 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Negate_cast_3 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Negate_out1_1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Cosine : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Cosine_1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Cosine_2 : signed(15 DOWNTO 0); -- sfix16_En14
BEGIN
-- (C) 2016 Mathworks, Inc
--
-- (C) 2016 Mathworks, Inc
u_signed <= signed(u_u);
insig_out1 <= unsigned(u_signed(13 DOWNTO 5));
Point50_out1 <= to_unsigned(16#8000#, 16);
LTEp50_1_cast <= insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0';
LTEp50_relop1 <= '1' WHEN LTEp50_1_cast <= Point50_out1 ELSE
'0';
pow2switch_out1 <= '0';
Amp50_sub_cast <= signed(resize(insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0', 17));
Amp50_sub_cast_1 <= signed(resize(Point50_out1, 17));
Amp50_out1 <= Amp50_sub_cast - Amp50_sub_cast_1;
insig_out1_dtc <= signed(resize(insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0', 17));
QuadHandle1_out1 <= Amp50_out1 WHEN LTEp50_relop1 = '0' ELSE
insig_out1_dtc;
Point25_out1 <= to_unsigned(16#4000#, 16);
LTEp25_1_cast <= signed(resize(Point25_out1, 17));
LTEp25_relop1 <= '1' WHEN QuadHandle1_out1 <= LTEp25_1_cast ELSE
'0';
p50mA_sub_cast <= signed(resize(Point50_out1, 18));
p50mA_sub_cast_1 <= resize(QuadHandle1_out1, 18);
p50mA_out1 <= p50mA_sub_cast - p50mA_sub_cast_1;
p50mA_out1_dtc <= unsigned(p50mA_out1(15 DOWNTO 7));
QuadHandle1_out1_dtc <= unsigned(QuadHandle1_out1(15 DOWNTO 7));
QuadHandle2_out1 <= p50mA_out1_dtc WHEN LTEp25_relop1 = '0' ELSE
QuadHandle1_out1_dtc;
CastU16En2_out1 <= QuadHandle2_out1;
CastU16En4_out1 <= resize(CastU16En2_out1, 10);
-- equivalent to multiply
-- by 4 with saturation
x4_out1 <= CastU16En4_out1 sll 2;
-- saturation block maybe optimized away
-- if the NumDataPoints is a power of 2
CastU16En3_out1 <= "111111111" WHEN x4_out1(9) /= '0' ELSE
x4_out1(8 DOWNTO 0);
Switch_out1 <= CastU16En3_out1 WHEN pow2switch_out1 = '0' ELSE
CastU16En3_out1;
Look_Up_Table_k <= to_unsigned(16#000#, 9) WHEN Switch_out1 = to_unsigned(16#000#, 9) ELSE
to_unsigned(16#1FF#, 9) WHEN Switch_out1 = to_unsigned(16#1FF#, 9) ELSE
Switch_out1;
Look_Up_Table_out1 <= nc(to_integer(Look_Up_Table_k));
Negate_cast <= resize(Look_Up_Table_out1, 17);
Negate_cast_1 <= - (Negate_cast);
Negate_out1 <= Negate_cast_1(15 DOWNTO 0);
Sine <= Negate_out1 WHEN LTEp50_relop1 = '0' ELSE
Look_Up_Table_out1;
Sine_1 <= Sine;
Sine_2 <= Sine_1;
x_x <= std_logic_vector(Sine_2);
insig_out1_1 <= unsigned(u_signed(13 DOWNTO 5));
Point25_out1_1 <= to_unsigned(16#4000#, 16);
LTEp25_1_cast_1 <= insig_out1_1 & '0' & '0' & '0' & '0' & '0' & '0' & '0';
LTEp25_relop1_1 <= '1' WHEN LTEp25_1_cast_1 <= Point25_out1_1 ELSE
'0';
Point75_out1 <= to_unsigned(16#C000#, 16);
GTEp75_1_cast <= insig_out1_1 & '0' & '0' & '0' & '0' & '0' & '0' & '0';
GTEp75_relop1 <= '1' WHEN GTEp75_1_cast >= Point75_out1 ELSE
'0';
alpha1st_or_4th_Quad_bool <= LTEp25_relop1_1 OR GTEp75_relop1;
alpha1st_or_4th_Quad_out1 <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & alpha1st_or_4th_Quad_bool;
pow2switch_out1_1 <= '0';
Point50_out1_1 <= to_unsigned(16#8000#, 16);
p75mA_sub_cast <= signed(resize(Point75_out1, 17));
p75mA_sub_cast_1 <= signed(resize(insig_out1_1 & '0' & '0' & '0' & '0' & '0' & '0' & '0', 17));
p75mA_out1 <= p75mA_sub_cast - p75mA_sub_cast_1;
Amp75_sub_cast <= signed(resize(insig_out1_1 & '0' & '0' & '0' & '0' & '0' & '0' & '0', 17));
Amp75_sub_cast_1 <= signed(resize(Point75_out1, 17));
Amp75_out1 <= Amp75_sub_cast - Amp75_sub_cast_1;
Amp25_sub_cast <= signed(resize(insig_out1_1 & '0' & '0' & '0' & '0' & '0' & '0' & '0', 17));
Amp25_sub_cast_1 <= signed(resize(Point25_out1_1, 17));
Amp25_out1 <= Amp25_sub_cast - Amp25_sub_cast_1;
p25mA_sub_cast <= signed(resize(Point25_out1_1, 17));
p25mA_sub_cast_1 <= signed(resize(insig_out1_1 & '0' & '0' & '0' & '0' & '0' & '0' & '0', 17));
p25mA_out1 <= p25mA_sub_cast - p25mA_sub_cast_1;
LTEp50_1_cast_1 <= insig_out1_1 & '0' & '0' & '0' & '0' & '0' & '0' & '0';
LTEp50_relop1_1 <= '1' WHEN LTEp50_1_cast_1 <= Point50_out1_1 ELSE
'0';
QuadHandle1b_out1 <= p75mA_out1 WHEN GTEp75_relop1 = '0' ELSE
Amp75_out1;
QuadHandle1b_out1_dtc <= "111111111" WHEN (QuadHandle1b_out1(16) = '0') AND (QuadHandle1b_out1(15 DOWNTO 7)
= "111111111") ELSE
"000000000" WHEN QuadHandle1b_out1(16) = '1' ELSE
unsigned(QuadHandle1b_out1(15 DOWNTO 7));
QuadHandle1a_out1 <= Amp25_out1 WHEN LTEp25_relop1_1 = '0' ELSE
p25mA_out1;
QuadHandle1a_out1_dtc <= "111111111" WHEN (QuadHandle1a_out1(16) = '0') AND (QuadHandle1a_out1(15 DOWNTO 7)
= "111111111") ELSE
"000000000" WHEN QuadHandle1a_out1(16) = '1' ELSE
unsigned(QuadHandle1a_out1(15 DOWNTO 7));
QuadHandle2_out1_1 <= QuadHandle1b_out1_dtc WHEN LTEp50_relop1_1 = '0' ELSE
QuadHandle1a_out1_dtc;
CastU16En1_out1 <= QuadHandle2_out1_1;
CastU16En3_out1_1 <= resize(CastU16En1_out1, 10);
-- equivalent to multiply
-- by 4 with saturation
x4_out1_1 <= CastU16En3_out1_1 sll 2;
-- saturation block maybe optimized away
-- if the NumDataPoints is a power of 2
CastU16En2_out1_1 <= "111111111" WHEN x4_out1_1(9) /= '0' ELSE
x4_out1_1(8 DOWNTO 0);
Switch_out1_1 <= CastU16En2_out1_1 WHEN pow2switch_out1_1 = '0' ELSE
CastU16En2_out1_1;
Look_Up_Table_k_1 <= to_unsigned(16#000#, 9) WHEN Switch_out1_1 = to_unsigned(16#000#, 9) ELSE
to_unsigned(16#1FF#, 9) WHEN Switch_out1_1 = to_unsigned(16#1FF#, 9) ELSE
Switch_out1_1;
Look_Up_Table_out1_1 <= nc_2(to_integer(Look_Up_Table_k_1));
Negate_cast_2 <= resize(Look_Up_Table_out1_1, 17);
Negate_cast_3 <= - (Negate_cast_2);
Negate_out1_1 <= Negate_cast_3(15 DOWNTO 0);
Cosine <= Negate_out1_1 WHEN alpha1st_or_4th_Quad_out1 = to_unsigned(16#00#, 8) ELSE
Look_Up_Table_out1_1;
Cosine_1 <= Cosine;
Cosine_2 <= Cosine_1;
y_y <= std_logic_vector(Cosine_2);
END rtl;
|
package my_package is
type slv_1_t is array (natural range <>) of bit_vector;
function addslvreg_f(arg0 : slv_1_t; arg1 : bit_vector) return slv_1_t;
end package my_package;
package body my_package is
function addslvreg_f(arg0 : slv_1_t; arg1 : bit_vector) return slv_1_t is
variable cb_v : bit_vector(0 downto 0);
variable arg_v,retval : arg0'subtype;
constant W : integer := arg0(0)'length-1;
begin
return retval;
end function addslvreg_f;
end package body;
-------------------------------------------------------------------------------
entity issue539 is
end entity;
use work.my_package.all;
architecture test of issue539 is
function get_elt_left (x : slv_1_t) return integer is
begin
return x(x'left)'left;
end function;
function get_elt_left_2 (x : slv_1_t) return integer is
begin
return x'element'left;
end function;
begin
p1: process is
variable v1 : slv_1_t(0 to 3)(5 to 6);
variable v2 : slv_1_t(0 to 3)(6 to 5);
begin
assert v1(1)'left = 5;
assert v2(5)'left = 6;
assert get_elt_left(v1) = 5;
assert get_elt_left(v2) = 6;
assert get_elt_left_2(v1) = 5;
assert get_elt_left_2(v2) = 6;
assert addslvreg_f(v1, "101") = v1;
wait;
end process;
end architecture;
|
----- Libraries -----
library ieee;
use ieee.std_logic_1164.all;
entity Tester is
port( CLOCK_50 : in std_logic;
KEY : in std_logic_vector(3 downto 2);
SW : in std_logic_vector(3 downto 0);
LEDR : out std_logic_vector(2 downto 0)
);
end Tester;
architecture Code_Test of Tester is
begin
cl : entity work.Code_Lock port map ( clk => CLOCK_50, reset => KEY(2), enter => KEY(3),
code => SW, lock => LEDR(0), err => LEDR(2 downto 1));
end Code_Test; |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_851 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_851;
architecture augh of cmp_851 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_851 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_851;
architecture augh of cmp_851 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
--***************************************************************************************
--
-- File Name: CY7C1380_PL_SCD.vhd
-- Version: 1.0
-- Date: December 22nd, 2004
-- Model: BUS Functional
-- Simulator: Modelsim
--
--
-- Queries: MPD Applications
-- Website: www.cypress.com/support
-- Company: Cypress Semiconductor
-- Part #: CY7C1380D (512K x 36)
--
-- Description: Cypress 18Mb Synburst SRAM (Pipelined SCD)
--
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright(c) Cypress Semiconductor, 2004
-- All rights reserved
--
-- Rev Date Changes
-- --- ---------- ---------------------------------------
-- 1.0 12/22/2004 - New Model
-- - New Test Bench
-- - New Test Vectors
--
--***************************************************************************************
-- Timings for Different Speed Bins (sb): 250MHz, 225MHz, 200MHz, 167MHz, 133MHz
LIBRARY ieee, grlib, work;
USE ieee.std_logic_1164.all;
-- USE ieee.std_logic_unsigned.all;
-- Use IEEE.Std_Logic_Arith.all;
USE work.package_utility.all;
use grlib.stdlib.all;
use grlib.stdio.all;
use ieee.std_logic_1164.all;
use std.textio.all;
entity CY7C1380D is
GENERIC (
fname : string := "prom.srec"; -- File to read from
-- Constant Parameters
addr_bits : INTEGER := 19; -- This is external address
data_bits : INTEGER := 36;
--Clock timings for 250Mhz
Cyp_tCO : TIME := 2.6 ns; -- Data Output Valid After CLK Rise
Cyp_tCYC : TIME := 4.0 ns; -- Clock cycle time
Cyp_tCH : TIME := 1.7 ns; -- Clock HIGH time
Cyp_tCL : TIME := 1.7 ns; -- Clock LOW time
Cyp_tCHZ : TIME := 2.6 ns; -- Clock to High-Z
Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
Cyp_tOEHZ : TIME := 2.6 ns; -- OE# HIGH to Output High-Z
Cyp_tOELZ : TIME := 0.0 ns; -- OE# LOW to Output Low-Z
Cyp_tOEV : TIME := 2.6 ns; -- OE# LOW to Output Valid
Cyp_tAS : TIME := 1.2 ns; -- Address Set-up Before CLK Rise
Cyp_tADS : TIME := 1.2 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
Cyp_tADVS : TIME := 1.2 ns; -- ADV# Set-up Before CLK Rise
Cyp_tWES : TIME := 1.2 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
Cyp_tDS : TIME := 1.2 ns; -- Data Input Set-up Before CLK Rise
Cyp_tCES : TIME := 1.2 ns; -- Chip Enable Set-up
Cyp_tAH : TIME := 0.3 ns; -- Address Hold After CLK Rise
Cyp_tADH : TIME := 0.3 ns; -- ADSC#, ADSP# Hold After CLK Rise
Cyp_tADVH : TIME := 0.3 ns; -- ADV# Hold After CLK Rise
Cyp_tWEH : TIME := 0.3 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
Cyp_tDH : TIME := 0.3 ns; -- Data Input Hold After CLK Rise
Cyp_tCEH : TIME := 0.3 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 225Mhz
-- Cyp_tCO : TIME := 2.8 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 4.4 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 2.8 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 2.8 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 2.8 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 200Mhz
-- Cyp_tCO : TIME := 3.0 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 5.0 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.0 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 3.0 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 3.0 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 167Mhz
-- Cyp_tCO : TIME := 3.4 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 6.0 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.2 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.2 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.4 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 3.4 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 3.4 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 133Mhz
-- Cyp_tCO : TIME := 4.2 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 7.5 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.5 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.5 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.4 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 4.0 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 4.2 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
);
PORT (iZZ : IN STD_LOGIC;
iMode : IN STD_LOGIC;
iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0);
inGW : IN STD_LOGIC;
inBWE : IN STD_LOGIC;
inBWd : IN STD_LOGIC;
inBWc : IN STD_LOGIC;
inBWb : IN STD_LOGIC;
inBWa : IN STD_LOGIC;
inCE1 : IN STD_LOGIC;
iCE2 : IN STD_LOGIC;
inCE3 : IN STD_LOGIC;
inADSP : IN STD_LOGIC;
inADSC : IN STD_LOGIC;
inADV : IN STD_LOGIC;
inOE : IN STD_LOGIC;
ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0);
iCLK : IN STD_LOGIC);
end CY7C1380D;
ARCHITECTURE CY7C1380D_arch OF CY7C1380D IS
signal Read_reg_o1, Read_reg1 : STD_LOGIC;
signal WrN_reg1 : STD_LOGIC;
signal ADSP_N_o : STD_LOGIC;
signal pipe_reg1, ce_reg1,pcsr_write1, ctlr_write1 : STD_LOGIC;
signal Sys_clk : STD_LOGIC := '0';
signal test : STD_LOGIC;
signal dout, din1 : STD_LOGIC_VECTOR (data_bits-1 downto 0);
signal ce : STD_LOGIC;
signal Write_n : STD_LOGIC;
signal Read : STD_LOGIC;
signal bwa_n1 : STD_LOGIC;
signal bwb_n1 : STD_LOGIC;
signal bwc_n1 : STD_LOGIC;
signal bwd_n1 : STD_LOGIC;
signal latch_addr : STD_LOGIC;
signal addr_reg_read1,addr_reg_write1,addr_reg_in1 : STD_LOGIC_VECTOR (addr_bits-1 downto 0);
signal OeN_HZ : STD_LOGIC;
signal OeN_DataValid : STD_LOGIC;
signal OeN_efct : STD_LOGIC;
signal WR_HZ : STD_LOGIC;
signal WR_LZ : STD_LOGIC;
signal WR_efct : STD_LOGIC;
signal CE_HZ : STD_LOGIC;
signal CE_LZ : STD_LOGIC;
signal Pipe_efct : STD_LOGIC;
signal RD_HZ : STD_LOGIC;
signal RD_LZ : STD_LOGIC;
signal RD_efct : STD_LOGIC;
begin
ce <= ((not inCE1) and (iCE2) and (not inCE3));
Write_n <= not((((not inBWa) OR (not inBWb) OR (not inBWc) OR (not inBWd)) AND (not inBWE)) OR (not inGW));
Read <= (((inBWa AND inBWb AND inBWc AND inBWd) AND (not inBWE)) OR (inGW AND inBWE) OR (( not inADSP) AND ce));
bwa_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWa))));
bwb_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWb))));
bwc_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWc))));
bwd_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWd))));
latch_addr <= ((not inADSC) OR ((not inADSP) AND (not inCE1)));
OeN_efct <= OeN_DataValid when (inOE = '0') else OeN_HZ;
WR_efct <= WR_LZ when (WrN_reg1 = '0') else WR_HZ;
Pipe_efct <= CE_LZ when ((ce_reg1 = '1') and (pipe_reg1 = '1')) else CE_HZ;
RD_efct <= CE_LZ when (Read_reg_o1 = '1') else CE_HZ ;
Process (Read_reg_o1)
begin
if (Read_reg_o1 = '0') then
RD_HZ <= '0' after Cyp_tCHZ;
RD_LZ <= '0' after Cyp_tCLZ;
elsif (Read_reg_o1 = '1') then
RD_HZ <= '1' after Cyp_tCHZ;
RD_LZ <= '1' after Cyp_tCLZ;
else
RD_HZ <= 'X' after Cyp_tCHZ;
RD_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
Process (pipe_reg1)
begin
if (pipe_reg1 = '1') then
CE_LZ <= '1' after Cyp_tCLZ;
elsif (pipe_reg1 = '0') then
CE_LZ <= '0' after Cyp_tCLZ;
else
CE_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
-- System Clock Decode
Process (iclk)
variable Sys_clk1 : std_logic := '0';
begin
if (rising_edge (iclk)) then
Sys_clk1 := not iZZ;
end if;
if (falling_edge (iCLK)) then
Sys_clk1 := '0';
end if;
Sys_clk <= Sys_clk1;
end process;
Process (WrN_reg1)
begin
if (WrN_reg1 = '1') then
WR_HZ <= '1' after Cyp_tCHZ;
WR_LZ <= '1' after Cyp_tCLZ;
elsif (WrN_reg1 = '0') then
WR_HZ <= '0' after Cyp_tCHZ;
WR_LZ <= '0' after Cyp_tCLZ;
else
WR_HZ <= 'X' after Cyp_tCHZ;
WR_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
Process (inOE)
begin
if (inOE = '1') then
OeN_HZ <= '1' after Cyp_tOEHZ;
OeN_DataValid <= '1' after Cyp_tOEV;
elsif (inOE = '0') then
OeN_HZ <= '0' after Cyp_tOEHZ;
OeN_DataValid <= '0' after Cyp_tOEV;
else
OeN_HZ <= 'X' after Cyp_tOEHZ;
OeN_DataValid <= 'X' after Cyp_tOEV;
end if;
end process;
process (ce_reg1, pipe_reg1)
begin
if ((ce_reg1 = '0') or (pipe_reg1 = '0')) then
CE_HZ <= '0' after Cyp_tCHZ;
elsif ((ce_reg1 = '1') and (pipe_reg1 = '1')) then
CE_HZ <= '1' after Cyp_tCHZ;
else
CE_HZ <= 'X' after Cyp_tCHZ;
end if;
end process;
Process (Sys_clk)
TYPE memory_array IS ARRAY ((2**addr_bits -1) DOWNTO 0) OF STD_LOGIC_VECTOR ((data_bits/4) - 1 DOWNTO 0);
variable Read_reg_o : std_logic;
variable Read_reg : std_logic;
variable pcsr_write, ctlr_write : std_logic;
variable WrN_reg : std_logic;
variable latch_addr_old, latch_addr_current : std_logic;
variable addr_reg_in, addr_reg_read, addr_reg_write : std_logic_vector (addr_bits -1 downto 0) := (others => '0');
variable bcount, first_addr : std_logic_vector (1 downto 0) := "00";
variable bwa_reg,bwb_reg,bwc_reg,bwd_reg, pipe_reg, ce_reg : std_logic;
variable din : std_logic_vector (data_bits-1 downto 0);
variable first_addr_int : integer;
variable bank0 : memory_array;
variable bank1 : memory_array;
variable bank2 : memory_array;
variable bank3 : memory_array;
variable FIRST : boolean := true;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable CH : character;
variable ai : integer := 0;
variable L1 : line;
begin
if FIRST then
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
std.textio.read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
hread(L1, recdata);
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
bank3 (ai+i) := "0000" & recdata((i*32) to (i*32+4));
bank2 (ai+i) := recdata((i*32+5) to (i*32+13));
bank1 (ai+i) := recdata((i*32+14) to (i*32+22));
bank0 (ai+i) := recdata((i*32+23) to (i*32+31));
end loop;
end if;
end if;
end if;
end loop;
FIRST := false;
end if;
if rising_edge (Sys_clk) then
if (Write_n = '0') then
Read_reg_o := '0';
else
Read_reg_o := Read_reg;
end if;
if (Write_n = '0') then
Read_reg := '0';
else
Read_reg := Read;
end if;
Read_reg1 <= Read_reg;
Read_reg_o1 <= Read_reg_o;
if (Read_reg = '1') then
pcsr_write := '0';
ctlr_write := '0';
end if;
-- Write Register
if (Read_reg_o = '1') then
WrN_reg := '1';
else
WrN_reg := Write_n;
end if;
WrN_reg1 <= WrN_reg;
latch_addr_old := latch_addr_current;
latch_addr_current := latch_addr;
if (latch_addr_old = '1' and (Write_n = '0') and ADSP_N_o = '0') then
pcsr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
elsif (latch_addr_current = '1' and (Write_n = '0') and inADSP = '1' and inADSC = '0') then
ctlr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
end if;
-- ADDRess Register
if (latch_addr = '1') then
addr_reg_in := iADDR;
bcount := iADDR (1 downto 0);
first_addr := iADDR (1 downto 0);
end if;
addr_reg_in1 <= addr_reg_in;
-- ADSP_N Previous-Cycle Register
ADSP_N_o <= inADSP;
pcsr_write1 <= pcsr_write;
ctlr_write1 <= ctlr_write;
first_addr_int := CONV_INTEGER1 (first_addr);
-- Binary Counter and Logic
if ((iMode = '0') and (inADV = '0') and (latch_addr = '0')) then -- Linear Burst
bcount := (bcount + '1'); -- Advance Counter
elsif ((iMode = '1') and (inADV = '0') and (latch_addr = '0')) then -- Interleaved Burst
if ((first_addr_int REM 2) = 0) then
bcount := (bcount + '1'); -- Increment Counter
elsif ((first_addr_int REM 2) = 1) then
bcount := (bcount - '1'); -- Decrement Counter
end if;
end if;
-- Read ADDRess
addr_reg_read := addr_reg_write;
addr_reg_read1 <= addr_reg_read;
-- Write ADDRess
addr_reg_write := addr_reg_in ((addr_bits - 1) downto 2) & bcount(1) & bcount(0);
addr_reg_write1 <= addr_reg_write;
-- Byte Write Register
bwa_reg := not bwa_n1;
bwb_reg := not bwb_n1;
bwc_reg := not bwc_n1;
bwd_reg := not bwd_n1;
-- Enable Register
pipe_reg := ce_reg;
-- Enable Register
if (latch_addr = '1') then
ce_reg := ce;
end if;
pipe_reg1 <= pipe_reg;
ce_reg1 <= ce_reg;
-- Input Register
if ((ce_reg = '1') and ((bwa_n1 ='0') or (bwb_n1 = '0') or (bwc_n1 = '0') or (bwd_n1 = '0')) and
((pcsr_write = '1') or (ctlr_write = '1'))) then
din := ioDQ;
end if;
din1 <= din;
-- Byte Write Driver
if ((ce_reg = '1') and (bwa_reg = '1')) then
bank0 (CONV_INTEGER1 (addr_reg_write)) := din (8 downto 0);
end if;
if ((ce_reg = '1') and (bwb_reg = '1')) then
bank1 (CONV_INTEGER1 (addr_reg_write)) := din (17 downto 9);
end if;
if ((ce_reg = '1') and (bwc_reg = '1')) then
bank2 (CONV_INTEGER1 (addr_reg_write)) := din (26 downto 18);
end if;
if ((ce_reg = '1') and (bwd_reg = '1')) then
bank3 (CONV_INTEGER1 (addr_reg_write)) := din (35 downto 27);
end if;
-- Output Registers
if ((Write_n = '0') or (pipe_reg = '0')) then
dout (35 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" after Cyp_tCHZ;
elsif (Read_reg_o = '1') then
dout ( 8 downto 0) <= bank0 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (17 downto 9) <= bank1 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (26 downto 18) <= bank2 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (35 downto 27) <= bank3 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
end if;
end if;
end process;
-- Output Buffers
ioDQ <= dout when ((inOE ='0') and (iZZ='0') and (Pipe_efct='1') and (RD_efct='1') and (WR_efct='1'))
else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
clk_check : PROCESS
VARIABLE clk_high, clk_low : TIME := 0 ns;
BEGIN
WAIT ON iClk;
IF iClk = '1' AND NOW >= Cyp_tCYC THEN
ASSERT (NOW - clk_low >= Cyp_tCH)
REPORT "Clk width low - tCH violation"
SEVERITY ERROR;
ASSERT (NOW - clk_high >= Cyp_tCYC)
REPORT "Clk period high - tCYC violation"
SEVERITY ERROR;
clk_high := NOW;
ELSIF iClk = '0' AND NOW /= 0 ns THEN
ASSERT (NOW - clk_high >= Cyp_tCL)
REPORT "Clk width high - tCL violation"
SEVERITY ERROR;
ASSERT (NOW - clk_low >= Cyp_tCYC)
REPORT "Clk period low - tCYC violation"
SEVERITY ERROR;
clk_low := NOW;
END IF;
END PROCESS;
-- Check for Setup Timing Violation
setup_check : PROCESS
BEGIN
WAIT ON iClk;
IF iClk = '1' THEN
ASSERT (iAddr'LAST_EVENT >= Cyp_tAS)
REPORT "Addr - tAS violation"
SEVERITY ERROR;
ASSERT (inGW'LAST_EVENT >= Cyp_tWES)
REPORT "GW# - tWES violation"
SEVERITY ERROR;
ASSERT (inBWE'LAST_EVENT >= Cyp_tWES)
REPORT "BWE# - tWES violation"
SEVERITY ERROR;
ASSERT (inCe1'LAST_EVENT >= Cyp_tWES)
REPORT "CE1# - tWES violation"
SEVERITY ERROR;
ASSERT (iCe2'LAST_EVENT >= Cyp_tWES)
REPORT "CE2 - tWES violation"
SEVERITY ERROR;
ASSERT (inCe3'LAST_EVENT >= Cyp_tWES)
REPORT "CE3# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdv'LAST_EVENT >= Cyp_tADVS)
REPORT "ADV# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdsp'LAST_EVENT >= Cyp_tADVS)
REPORT "ADSP# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdsc'LAST_EVENT >= Cyp_tADVS)
REPORT "ADSC# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwa'LAST_EVENT >= Cyp_tWES)
REPORT "BWa# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwb'LAST_EVENT >= Cyp_tWES)
REPORT "BWb# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwc'LAST_EVENT >= Cyp_tWES)
REPORT "BWc# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwd'LAST_EVENT >= Cyp_tWES)
REPORT "BWd# - tWES violation"
SEVERITY ERROR;
ASSERT (ioDq'LAST_EVENT >= Cyp_tDS)
REPORT "Dq - tDS violation"
SEVERITY ERROR;
END IF;
END PROCESS;
-- Check for Hold Timing Violation
hold_check : PROCESS
BEGIN
WAIT ON iClk'DELAYED(Cyp_tAH), iClk'DELAYED(Cyp_tWEH), iClk'DELAYED(Cyp_tDH);
IF iClk'DELAYED(Cyp_tAH) = '1' THEN
ASSERT (iAddr'LAST_EVENT > Cyp_tAH)
REPORT "Addr - tAH violation"
SEVERITY ERROR;
END IF;
IF iClk'DELAYED(Cyp_tDH) = '1' THEN
ASSERT (ioDq'LAST_EVENT > Cyp_tDH)
REPORT "Dq - tDH violation"
SEVERITY ERROR;
END IF;
IF iClk'DELAYED(Cyp_tWEH) = '1' THEN
ASSERT (inCe1'LAST_EVENT > Cyp_tWEH)
REPORT "CE1# - tWEH violation"
SEVERITY ERROR;
ASSERT (iCe2'LAST_EVENT > Cyp_tWEH)
REPORT "CE2 - tWEH violation"
SEVERITY ERROR;
ASSERT (inCe3'LAST_EVENT > Cyp_tWEH)
REPORT "CE3 - tWEH violation"
SEVERITY ERROR;
ASSERT (inAdv'LAST_EVENT > Cyp_tWEH)
REPORT "ADV# - tWEH violation"
SEVERITY ERROR;
ASSERT (inADSP'LAST_EVENT > Cyp_tWEH)
REPORT "ADSP# - tWEH violation"
SEVERITY ERROR;
ASSERT (inADSC'LAST_EVENT > Cyp_tWEH)
REPORT "ADSC# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwa'LAST_EVENT > Cyp_tWEH)
REPORT "BWa# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwb'LAST_EVENT > Cyp_tWEH)
REPORT "BWb# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwc'LAST_EVENT > Cyp_tWEH)
REPORT "BWc# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwd'LAST_EVENT > Cyp_tWEH)
REPORT "BWd# - tWEH violation"
SEVERITY ERROR;
END IF;
END PROCESS;
end CY7C1380D_arch;
|
--***************************************************************************************
--
-- File Name: CY7C1380_PL_SCD.vhd
-- Version: 1.0
-- Date: December 22nd, 2004
-- Model: BUS Functional
-- Simulator: Modelsim
--
--
-- Queries: MPD Applications
-- Website: www.cypress.com/support
-- Company: Cypress Semiconductor
-- Part #: CY7C1380D (512K x 36)
--
-- Description: Cypress 18Mb Synburst SRAM (Pipelined SCD)
--
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright(c) Cypress Semiconductor, 2004
-- All rights reserved
--
-- Rev Date Changes
-- --- ---------- ---------------------------------------
-- 1.0 12/22/2004 - New Model
-- - New Test Bench
-- - New Test Vectors
--
--***************************************************************************************
-- Timings for Different Speed Bins (sb): 250MHz, 225MHz, 200MHz, 167MHz, 133MHz
LIBRARY ieee, grlib, work;
USE ieee.std_logic_1164.all;
-- USE ieee.std_logic_unsigned.all;
-- Use IEEE.Std_Logic_Arith.all;
USE work.package_utility.all;
use grlib.stdlib.all;
use grlib.stdio.all;
use ieee.std_logic_1164.all;
use std.textio.all;
entity CY7C1380D is
GENERIC (
fname : string := "prom.srec"; -- File to read from
-- Constant Parameters
addr_bits : INTEGER := 19; -- This is external address
data_bits : INTEGER := 36;
--Clock timings for 250Mhz
Cyp_tCO : TIME := 2.6 ns; -- Data Output Valid After CLK Rise
Cyp_tCYC : TIME := 4.0 ns; -- Clock cycle time
Cyp_tCH : TIME := 1.7 ns; -- Clock HIGH time
Cyp_tCL : TIME := 1.7 ns; -- Clock LOW time
Cyp_tCHZ : TIME := 2.6 ns; -- Clock to High-Z
Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
Cyp_tOEHZ : TIME := 2.6 ns; -- OE# HIGH to Output High-Z
Cyp_tOELZ : TIME := 0.0 ns; -- OE# LOW to Output Low-Z
Cyp_tOEV : TIME := 2.6 ns; -- OE# LOW to Output Valid
Cyp_tAS : TIME := 1.2 ns; -- Address Set-up Before CLK Rise
Cyp_tADS : TIME := 1.2 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
Cyp_tADVS : TIME := 1.2 ns; -- ADV# Set-up Before CLK Rise
Cyp_tWES : TIME := 1.2 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
Cyp_tDS : TIME := 1.2 ns; -- Data Input Set-up Before CLK Rise
Cyp_tCES : TIME := 1.2 ns; -- Chip Enable Set-up
Cyp_tAH : TIME := 0.3 ns; -- Address Hold After CLK Rise
Cyp_tADH : TIME := 0.3 ns; -- ADSC#, ADSP# Hold After CLK Rise
Cyp_tADVH : TIME := 0.3 ns; -- ADV# Hold After CLK Rise
Cyp_tWEH : TIME := 0.3 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
Cyp_tDH : TIME := 0.3 ns; -- Data Input Hold After CLK Rise
Cyp_tCEH : TIME := 0.3 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 225Mhz
-- Cyp_tCO : TIME := 2.8 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 4.4 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 2.8 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 2.8 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 2.8 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 200Mhz
-- Cyp_tCO : TIME := 3.0 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 5.0 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.0 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 3.0 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 3.0 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 167Mhz
-- Cyp_tCO : TIME := 3.4 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 6.0 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.2 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.2 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.4 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 3.4 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 3.4 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 133Mhz
-- Cyp_tCO : TIME := 4.2 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 7.5 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.5 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.5 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.4 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 4.0 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 4.2 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
);
PORT (iZZ : IN STD_LOGIC;
iMode : IN STD_LOGIC;
iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0);
inGW : IN STD_LOGIC;
inBWE : IN STD_LOGIC;
inBWd : IN STD_LOGIC;
inBWc : IN STD_LOGIC;
inBWb : IN STD_LOGIC;
inBWa : IN STD_LOGIC;
inCE1 : IN STD_LOGIC;
iCE2 : IN STD_LOGIC;
inCE3 : IN STD_LOGIC;
inADSP : IN STD_LOGIC;
inADSC : IN STD_LOGIC;
inADV : IN STD_LOGIC;
inOE : IN STD_LOGIC;
ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0);
iCLK : IN STD_LOGIC);
end CY7C1380D;
ARCHITECTURE CY7C1380D_arch OF CY7C1380D IS
signal Read_reg_o1, Read_reg1 : STD_LOGIC;
signal WrN_reg1 : STD_LOGIC;
signal ADSP_N_o : STD_LOGIC;
signal pipe_reg1, ce_reg1,pcsr_write1, ctlr_write1 : STD_LOGIC;
signal Sys_clk : STD_LOGIC := '0';
signal test : STD_LOGIC;
signal dout, din1 : STD_LOGIC_VECTOR (data_bits-1 downto 0);
signal ce : STD_LOGIC;
signal Write_n : STD_LOGIC;
signal Read : STD_LOGIC;
signal bwa_n1 : STD_LOGIC;
signal bwb_n1 : STD_LOGIC;
signal bwc_n1 : STD_LOGIC;
signal bwd_n1 : STD_LOGIC;
signal latch_addr : STD_LOGIC;
signal addr_reg_read1,addr_reg_write1,addr_reg_in1 : STD_LOGIC_VECTOR (addr_bits-1 downto 0);
signal OeN_HZ : STD_LOGIC;
signal OeN_DataValid : STD_LOGIC;
signal OeN_efct : STD_LOGIC;
signal WR_HZ : STD_LOGIC;
signal WR_LZ : STD_LOGIC;
signal WR_efct : STD_LOGIC;
signal CE_HZ : STD_LOGIC;
signal CE_LZ : STD_LOGIC;
signal Pipe_efct : STD_LOGIC;
signal RD_HZ : STD_LOGIC;
signal RD_LZ : STD_LOGIC;
signal RD_efct : STD_LOGIC;
begin
ce <= ((not inCE1) and (iCE2) and (not inCE3));
Write_n <= not((((not inBWa) OR (not inBWb) OR (not inBWc) OR (not inBWd)) AND (not inBWE)) OR (not inGW));
Read <= (((inBWa AND inBWb AND inBWc AND inBWd) AND (not inBWE)) OR (inGW AND inBWE) OR (( not inADSP) AND ce));
bwa_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWa))));
bwb_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWb))));
bwc_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWc))));
bwd_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWd))));
latch_addr <= ((not inADSC) OR ((not inADSP) AND (not inCE1)));
OeN_efct <= OeN_DataValid when (inOE = '0') else OeN_HZ;
WR_efct <= WR_LZ when (WrN_reg1 = '0') else WR_HZ;
Pipe_efct <= CE_LZ when ((ce_reg1 = '1') and (pipe_reg1 = '1')) else CE_HZ;
RD_efct <= CE_LZ when (Read_reg_o1 = '1') else CE_HZ ;
Process (Read_reg_o1)
begin
if (Read_reg_o1 = '0') then
RD_HZ <= '0' after Cyp_tCHZ;
RD_LZ <= '0' after Cyp_tCLZ;
elsif (Read_reg_o1 = '1') then
RD_HZ <= '1' after Cyp_tCHZ;
RD_LZ <= '1' after Cyp_tCLZ;
else
RD_HZ <= 'X' after Cyp_tCHZ;
RD_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
Process (pipe_reg1)
begin
if (pipe_reg1 = '1') then
CE_LZ <= '1' after Cyp_tCLZ;
elsif (pipe_reg1 = '0') then
CE_LZ <= '0' after Cyp_tCLZ;
else
CE_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
-- System Clock Decode
Process (iclk)
variable Sys_clk1 : std_logic := '0';
begin
if (rising_edge (iclk)) then
Sys_clk1 := not iZZ;
end if;
if (falling_edge (iCLK)) then
Sys_clk1 := '0';
end if;
Sys_clk <= Sys_clk1;
end process;
Process (WrN_reg1)
begin
if (WrN_reg1 = '1') then
WR_HZ <= '1' after Cyp_tCHZ;
WR_LZ <= '1' after Cyp_tCLZ;
elsif (WrN_reg1 = '0') then
WR_HZ <= '0' after Cyp_tCHZ;
WR_LZ <= '0' after Cyp_tCLZ;
else
WR_HZ <= 'X' after Cyp_tCHZ;
WR_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
Process (inOE)
begin
if (inOE = '1') then
OeN_HZ <= '1' after Cyp_tOEHZ;
OeN_DataValid <= '1' after Cyp_tOEV;
elsif (inOE = '0') then
OeN_HZ <= '0' after Cyp_tOEHZ;
OeN_DataValid <= '0' after Cyp_tOEV;
else
OeN_HZ <= 'X' after Cyp_tOEHZ;
OeN_DataValid <= 'X' after Cyp_tOEV;
end if;
end process;
process (ce_reg1, pipe_reg1)
begin
if ((ce_reg1 = '0') or (pipe_reg1 = '0')) then
CE_HZ <= '0' after Cyp_tCHZ;
elsif ((ce_reg1 = '1') and (pipe_reg1 = '1')) then
CE_HZ <= '1' after Cyp_tCHZ;
else
CE_HZ <= 'X' after Cyp_tCHZ;
end if;
end process;
Process (Sys_clk)
TYPE memory_array IS ARRAY ((2**addr_bits -1) DOWNTO 0) OF STD_LOGIC_VECTOR ((data_bits/4) - 1 DOWNTO 0);
variable Read_reg_o : std_logic;
variable Read_reg : std_logic;
variable pcsr_write, ctlr_write : std_logic;
variable WrN_reg : std_logic;
variable latch_addr_old, latch_addr_current : std_logic;
variable addr_reg_in, addr_reg_read, addr_reg_write : std_logic_vector (addr_bits -1 downto 0) := (others => '0');
variable bcount, first_addr : std_logic_vector (1 downto 0) := "00";
variable bwa_reg,bwb_reg,bwc_reg,bwd_reg, pipe_reg, ce_reg : std_logic;
variable din : std_logic_vector (data_bits-1 downto 0);
variable first_addr_int : integer;
variable bank0 : memory_array;
variable bank1 : memory_array;
variable bank2 : memory_array;
variable bank3 : memory_array;
variable FIRST : boolean := true;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable CH : character;
variable ai : integer := 0;
variable L1 : line;
begin
if FIRST then
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
std.textio.read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
hread(L1, recdata);
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
bank3 (ai+i) := "0000" & recdata((i*32) to (i*32+4));
bank2 (ai+i) := recdata((i*32+5) to (i*32+13));
bank1 (ai+i) := recdata((i*32+14) to (i*32+22));
bank0 (ai+i) := recdata((i*32+23) to (i*32+31));
end loop;
end if;
end if;
end if;
end loop;
FIRST := false;
end if;
if rising_edge (Sys_clk) then
if (Write_n = '0') then
Read_reg_o := '0';
else
Read_reg_o := Read_reg;
end if;
if (Write_n = '0') then
Read_reg := '0';
else
Read_reg := Read;
end if;
Read_reg1 <= Read_reg;
Read_reg_o1 <= Read_reg_o;
if (Read_reg = '1') then
pcsr_write := '0';
ctlr_write := '0';
end if;
-- Write Register
if (Read_reg_o = '1') then
WrN_reg := '1';
else
WrN_reg := Write_n;
end if;
WrN_reg1 <= WrN_reg;
latch_addr_old := latch_addr_current;
latch_addr_current := latch_addr;
if (latch_addr_old = '1' and (Write_n = '0') and ADSP_N_o = '0') then
pcsr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
elsif (latch_addr_current = '1' and (Write_n = '0') and inADSP = '1' and inADSC = '0') then
ctlr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
end if;
-- ADDRess Register
if (latch_addr = '1') then
addr_reg_in := iADDR;
bcount := iADDR (1 downto 0);
first_addr := iADDR (1 downto 0);
end if;
addr_reg_in1 <= addr_reg_in;
-- ADSP_N Previous-Cycle Register
ADSP_N_o <= inADSP;
pcsr_write1 <= pcsr_write;
ctlr_write1 <= ctlr_write;
first_addr_int := CONV_INTEGER1 (first_addr);
-- Binary Counter and Logic
if ((iMode = '0') and (inADV = '0') and (latch_addr = '0')) then -- Linear Burst
bcount := (bcount + '1'); -- Advance Counter
elsif ((iMode = '1') and (inADV = '0') and (latch_addr = '0')) then -- Interleaved Burst
if ((first_addr_int REM 2) = 0) then
bcount := (bcount + '1'); -- Increment Counter
elsif ((first_addr_int REM 2) = 1) then
bcount := (bcount - '1'); -- Decrement Counter
end if;
end if;
-- Read ADDRess
addr_reg_read := addr_reg_write;
addr_reg_read1 <= addr_reg_read;
-- Write ADDRess
addr_reg_write := addr_reg_in ((addr_bits - 1) downto 2) & bcount(1) & bcount(0);
addr_reg_write1 <= addr_reg_write;
-- Byte Write Register
bwa_reg := not bwa_n1;
bwb_reg := not bwb_n1;
bwc_reg := not bwc_n1;
bwd_reg := not bwd_n1;
-- Enable Register
pipe_reg := ce_reg;
-- Enable Register
if (latch_addr = '1') then
ce_reg := ce;
end if;
pipe_reg1 <= pipe_reg;
ce_reg1 <= ce_reg;
-- Input Register
if ((ce_reg = '1') and ((bwa_n1 ='0') or (bwb_n1 = '0') or (bwc_n1 = '0') or (bwd_n1 = '0')) and
((pcsr_write = '1') or (ctlr_write = '1'))) then
din := ioDQ;
end if;
din1 <= din;
-- Byte Write Driver
if ((ce_reg = '1') and (bwa_reg = '1')) then
bank0 (CONV_INTEGER1 (addr_reg_write)) := din (8 downto 0);
end if;
if ((ce_reg = '1') and (bwb_reg = '1')) then
bank1 (CONV_INTEGER1 (addr_reg_write)) := din (17 downto 9);
end if;
if ((ce_reg = '1') and (bwc_reg = '1')) then
bank2 (CONV_INTEGER1 (addr_reg_write)) := din (26 downto 18);
end if;
if ((ce_reg = '1') and (bwd_reg = '1')) then
bank3 (CONV_INTEGER1 (addr_reg_write)) := din (35 downto 27);
end if;
-- Output Registers
if ((Write_n = '0') or (pipe_reg = '0')) then
dout (35 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" after Cyp_tCHZ;
elsif (Read_reg_o = '1') then
dout ( 8 downto 0) <= bank0 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (17 downto 9) <= bank1 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (26 downto 18) <= bank2 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (35 downto 27) <= bank3 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
end if;
end if;
end process;
-- Output Buffers
ioDQ <= dout when ((inOE ='0') and (iZZ='0') and (Pipe_efct='1') and (RD_efct='1') and (WR_efct='1'))
else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
clk_check : PROCESS
VARIABLE clk_high, clk_low : TIME := 0 ns;
BEGIN
WAIT ON iClk;
IF iClk = '1' AND NOW >= Cyp_tCYC THEN
ASSERT (NOW - clk_low >= Cyp_tCH)
REPORT "Clk width low - tCH violation"
SEVERITY ERROR;
ASSERT (NOW - clk_high >= Cyp_tCYC)
REPORT "Clk period high - tCYC violation"
SEVERITY ERROR;
clk_high := NOW;
ELSIF iClk = '0' AND NOW /= 0 ns THEN
ASSERT (NOW - clk_high >= Cyp_tCL)
REPORT "Clk width high - tCL violation"
SEVERITY ERROR;
ASSERT (NOW - clk_low >= Cyp_tCYC)
REPORT "Clk period low - tCYC violation"
SEVERITY ERROR;
clk_low := NOW;
END IF;
END PROCESS;
-- Check for Setup Timing Violation
setup_check : PROCESS
BEGIN
WAIT ON iClk;
IF iClk = '1' THEN
ASSERT (iAddr'LAST_EVENT >= Cyp_tAS)
REPORT "Addr - tAS violation"
SEVERITY ERROR;
ASSERT (inGW'LAST_EVENT >= Cyp_tWES)
REPORT "GW# - tWES violation"
SEVERITY ERROR;
ASSERT (inBWE'LAST_EVENT >= Cyp_tWES)
REPORT "BWE# - tWES violation"
SEVERITY ERROR;
ASSERT (inCe1'LAST_EVENT >= Cyp_tWES)
REPORT "CE1# - tWES violation"
SEVERITY ERROR;
ASSERT (iCe2'LAST_EVENT >= Cyp_tWES)
REPORT "CE2 - tWES violation"
SEVERITY ERROR;
ASSERT (inCe3'LAST_EVENT >= Cyp_tWES)
REPORT "CE3# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdv'LAST_EVENT >= Cyp_tADVS)
REPORT "ADV# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdsp'LAST_EVENT >= Cyp_tADVS)
REPORT "ADSP# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdsc'LAST_EVENT >= Cyp_tADVS)
REPORT "ADSC# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwa'LAST_EVENT >= Cyp_tWES)
REPORT "BWa# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwb'LAST_EVENT >= Cyp_tWES)
REPORT "BWb# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwc'LAST_EVENT >= Cyp_tWES)
REPORT "BWc# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwd'LAST_EVENT >= Cyp_tWES)
REPORT "BWd# - tWES violation"
SEVERITY ERROR;
ASSERT (ioDq'LAST_EVENT >= Cyp_tDS)
REPORT "Dq - tDS violation"
SEVERITY ERROR;
END IF;
END PROCESS;
-- Check for Hold Timing Violation
hold_check : PROCESS
BEGIN
WAIT ON iClk'DELAYED(Cyp_tAH), iClk'DELAYED(Cyp_tWEH), iClk'DELAYED(Cyp_tDH);
IF iClk'DELAYED(Cyp_tAH) = '1' THEN
ASSERT (iAddr'LAST_EVENT > Cyp_tAH)
REPORT "Addr - tAH violation"
SEVERITY ERROR;
END IF;
IF iClk'DELAYED(Cyp_tDH) = '1' THEN
ASSERT (ioDq'LAST_EVENT > Cyp_tDH)
REPORT "Dq - tDH violation"
SEVERITY ERROR;
END IF;
IF iClk'DELAYED(Cyp_tWEH) = '1' THEN
ASSERT (inCe1'LAST_EVENT > Cyp_tWEH)
REPORT "CE1# - tWEH violation"
SEVERITY ERROR;
ASSERT (iCe2'LAST_EVENT > Cyp_tWEH)
REPORT "CE2 - tWEH violation"
SEVERITY ERROR;
ASSERT (inCe3'LAST_EVENT > Cyp_tWEH)
REPORT "CE3 - tWEH violation"
SEVERITY ERROR;
ASSERT (inAdv'LAST_EVENT > Cyp_tWEH)
REPORT "ADV# - tWEH violation"
SEVERITY ERROR;
ASSERT (inADSP'LAST_EVENT > Cyp_tWEH)
REPORT "ADSP# - tWEH violation"
SEVERITY ERROR;
ASSERT (inADSC'LAST_EVENT > Cyp_tWEH)
REPORT "ADSC# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwa'LAST_EVENT > Cyp_tWEH)
REPORT "BWa# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwb'LAST_EVENT > Cyp_tWEH)
REPORT "BWb# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwc'LAST_EVENT > Cyp_tWEH)
REPORT "BWc# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwd'LAST_EVENT > Cyp_tWEH)
REPORT "BWd# - tWEH violation"
SEVERITY ERROR;
END IF;
END PROCESS;
end CY7C1380D_arch;
|
--***************************************************************************************
--
-- File Name: CY7C1380_PL_SCD.vhd
-- Version: 1.0
-- Date: December 22nd, 2004
-- Model: BUS Functional
-- Simulator: Modelsim
--
--
-- Queries: MPD Applications
-- Website: www.cypress.com/support
-- Company: Cypress Semiconductor
-- Part #: CY7C1380D (512K x 36)
--
-- Description: Cypress 18Mb Synburst SRAM (Pipelined SCD)
--
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright(c) Cypress Semiconductor, 2004
-- All rights reserved
--
-- Rev Date Changes
-- --- ---------- ---------------------------------------
-- 1.0 12/22/2004 - New Model
-- - New Test Bench
-- - New Test Vectors
--
--***************************************************************************************
-- Timings for Different Speed Bins (sb): 250MHz, 225MHz, 200MHz, 167MHz, 133MHz
LIBRARY ieee, grlib, work;
USE ieee.std_logic_1164.all;
-- USE ieee.std_logic_unsigned.all;
-- Use IEEE.Std_Logic_Arith.all;
USE work.package_utility.all;
use grlib.stdlib.all;
use grlib.stdio.all;
use ieee.std_logic_1164.all;
use std.textio.all;
entity CY7C1380D is
GENERIC (
fname : string := "prom.srec"; -- File to read from
-- Constant Parameters
addr_bits : INTEGER := 19; -- This is external address
data_bits : INTEGER := 36;
--Clock timings for 250Mhz
Cyp_tCO : TIME := 2.6 ns; -- Data Output Valid After CLK Rise
Cyp_tCYC : TIME := 4.0 ns; -- Clock cycle time
Cyp_tCH : TIME := 1.7 ns; -- Clock HIGH time
Cyp_tCL : TIME := 1.7 ns; -- Clock LOW time
Cyp_tCHZ : TIME := 2.6 ns; -- Clock to High-Z
Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
Cyp_tOEHZ : TIME := 2.6 ns; -- OE# HIGH to Output High-Z
Cyp_tOELZ : TIME := 0.0 ns; -- OE# LOW to Output Low-Z
Cyp_tOEV : TIME := 2.6 ns; -- OE# LOW to Output Valid
Cyp_tAS : TIME := 1.2 ns; -- Address Set-up Before CLK Rise
Cyp_tADS : TIME := 1.2 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
Cyp_tADVS : TIME := 1.2 ns; -- ADV# Set-up Before CLK Rise
Cyp_tWES : TIME := 1.2 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
Cyp_tDS : TIME := 1.2 ns; -- Data Input Set-up Before CLK Rise
Cyp_tCES : TIME := 1.2 ns; -- Chip Enable Set-up
Cyp_tAH : TIME := 0.3 ns; -- Address Hold After CLK Rise
Cyp_tADH : TIME := 0.3 ns; -- ADSC#, ADSP# Hold After CLK Rise
Cyp_tADVH : TIME := 0.3 ns; -- ADV# Hold After CLK Rise
Cyp_tWEH : TIME := 0.3 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
Cyp_tDH : TIME := 0.3 ns; -- Data Input Hold After CLK Rise
Cyp_tCEH : TIME := 0.3 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 225Mhz
-- Cyp_tCO : TIME := 2.8 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 4.4 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 2.8 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 2.8 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 2.8 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 200Mhz
-- Cyp_tCO : TIME := 3.0 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 5.0 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.0 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 3.0 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 3.0 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 167Mhz
-- Cyp_tCO : TIME := 3.4 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 6.0 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.2 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.2 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.4 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 3.4 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 3.4 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 133Mhz
-- Cyp_tCO : TIME := 4.2 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 7.5 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.5 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.5 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.4 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 4.0 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 4.2 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
);
PORT (iZZ : IN STD_LOGIC;
iMode : IN STD_LOGIC;
iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0);
inGW : IN STD_LOGIC;
inBWE : IN STD_LOGIC;
inBWd : IN STD_LOGIC;
inBWc : IN STD_LOGIC;
inBWb : IN STD_LOGIC;
inBWa : IN STD_LOGIC;
inCE1 : IN STD_LOGIC;
iCE2 : IN STD_LOGIC;
inCE3 : IN STD_LOGIC;
inADSP : IN STD_LOGIC;
inADSC : IN STD_LOGIC;
inADV : IN STD_LOGIC;
inOE : IN STD_LOGIC;
ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0);
iCLK : IN STD_LOGIC);
end CY7C1380D;
ARCHITECTURE CY7C1380D_arch OF CY7C1380D IS
signal Read_reg_o1, Read_reg1 : STD_LOGIC;
signal WrN_reg1 : STD_LOGIC;
signal ADSP_N_o : STD_LOGIC;
signal pipe_reg1, ce_reg1,pcsr_write1, ctlr_write1 : STD_LOGIC;
signal Sys_clk : STD_LOGIC := '0';
signal test : STD_LOGIC;
signal dout, din1 : STD_LOGIC_VECTOR (data_bits-1 downto 0);
signal ce : STD_LOGIC;
signal Write_n : STD_LOGIC;
signal Read : STD_LOGIC;
signal bwa_n1 : STD_LOGIC;
signal bwb_n1 : STD_LOGIC;
signal bwc_n1 : STD_LOGIC;
signal bwd_n1 : STD_LOGIC;
signal latch_addr : STD_LOGIC;
signal addr_reg_read1,addr_reg_write1,addr_reg_in1 : STD_LOGIC_VECTOR (addr_bits-1 downto 0);
signal OeN_HZ : STD_LOGIC;
signal OeN_DataValid : STD_LOGIC;
signal OeN_efct : STD_LOGIC;
signal WR_HZ : STD_LOGIC;
signal WR_LZ : STD_LOGIC;
signal WR_efct : STD_LOGIC;
signal CE_HZ : STD_LOGIC;
signal CE_LZ : STD_LOGIC;
signal Pipe_efct : STD_LOGIC;
signal RD_HZ : STD_LOGIC;
signal RD_LZ : STD_LOGIC;
signal RD_efct : STD_LOGIC;
begin
ce <= ((not inCE1) and (iCE2) and (not inCE3));
Write_n <= not((((not inBWa) OR (not inBWb) OR (not inBWc) OR (not inBWd)) AND (not inBWE)) OR (not inGW));
Read <= (((inBWa AND inBWb AND inBWc AND inBWd) AND (not inBWE)) OR (inGW AND inBWE) OR (( not inADSP) AND ce));
bwa_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWa))));
bwb_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWb))));
bwc_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWc))));
bwd_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWd))));
latch_addr <= ((not inADSC) OR ((not inADSP) AND (not inCE1)));
OeN_efct <= OeN_DataValid when (inOE = '0') else OeN_HZ;
WR_efct <= WR_LZ when (WrN_reg1 = '0') else WR_HZ;
Pipe_efct <= CE_LZ when ((ce_reg1 = '1') and (pipe_reg1 = '1')) else CE_HZ;
RD_efct <= CE_LZ when (Read_reg_o1 = '1') else CE_HZ ;
Process (Read_reg_o1)
begin
if (Read_reg_o1 = '0') then
RD_HZ <= '0' after Cyp_tCHZ;
RD_LZ <= '0' after Cyp_tCLZ;
elsif (Read_reg_o1 = '1') then
RD_HZ <= '1' after Cyp_tCHZ;
RD_LZ <= '1' after Cyp_tCLZ;
else
RD_HZ <= 'X' after Cyp_tCHZ;
RD_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
Process (pipe_reg1)
begin
if (pipe_reg1 = '1') then
CE_LZ <= '1' after Cyp_tCLZ;
elsif (pipe_reg1 = '0') then
CE_LZ <= '0' after Cyp_tCLZ;
else
CE_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
-- System Clock Decode
Process (iclk)
variable Sys_clk1 : std_logic := '0';
begin
if (rising_edge (iclk)) then
Sys_clk1 := not iZZ;
end if;
if (falling_edge (iCLK)) then
Sys_clk1 := '0';
end if;
Sys_clk <= Sys_clk1;
end process;
Process (WrN_reg1)
begin
if (WrN_reg1 = '1') then
WR_HZ <= '1' after Cyp_tCHZ;
WR_LZ <= '1' after Cyp_tCLZ;
elsif (WrN_reg1 = '0') then
WR_HZ <= '0' after Cyp_tCHZ;
WR_LZ <= '0' after Cyp_tCLZ;
else
WR_HZ <= 'X' after Cyp_tCHZ;
WR_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
Process (inOE)
begin
if (inOE = '1') then
OeN_HZ <= '1' after Cyp_tOEHZ;
OeN_DataValid <= '1' after Cyp_tOEV;
elsif (inOE = '0') then
OeN_HZ <= '0' after Cyp_tOEHZ;
OeN_DataValid <= '0' after Cyp_tOEV;
else
OeN_HZ <= 'X' after Cyp_tOEHZ;
OeN_DataValid <= 'X' after Cyp_tOEV;
end if;
end process;
process (ce_reg1, pipe_reg1)
begin
if ((ce_reg1 = '0') or (pipe_reg1 = '0')) then
CE_HZ <= '0' after Cyp_tCHZ;
elsif ((ce_reg1 = '1') and (pipe_reg1 = '1')) then
CE_HZ <= '1' after Cyp_tCHZ;
else
CE_HZ <= 'X' after Cyp_tCHZ;
end if;
end process;
Process (Sys_clk)
TYPE memory_array IS ARRAY ((2**addr_bits -1) DOWNTO 0) OF STD_LOGIC_VECTOR ((data_bits/4) - 1 DOWNTO 0);
variable Read_reg_o : std_logic;
variable Read_reg : std_logic;
variable pcsr_write, ctlr_write : std_logic;
variable WrN_reg : std_logic;
variable latch_addr_old, latch_addr_current : std_logic;
variable addr_reg_in, addr_reg_read, addr_reg_write : std_logic_vector (addr_bits -1 downto 0) := (others => '0');
variable bcount, first_addr : std_logic_vector (1 downto 0) := "00";
variable bwa_reg,bwb_reg,bwc_reg,bwd_reg, pipe_reg, ce_reg : std_logic;
variable din : std_logic_vector (data_bits-1 downto 0);
variable first_addr_int : integer;
variable bank0 : memory_array;
variable bank1 : memory_array;
variable bank2 : memory_array;
variable bank3 : memory_array;
variable FIRST : boolean := true;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable CH : character;
variable ai : integer := 0;
variable L1 : line;
begin
if FIRST then
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
std.textio.read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
hread(L1, recdata);
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
bank3 (ai+i) := "0000" & recdata((i*32) to (i*32+4));
bank2 (ai+i) := recdata((i*32+5) to (i*32+13));
bank1 (ai+i) := recdata((i*32+14) to (i*32+22));
bank0 (ai+i) := recdata((i*32+23) to (i*32+31));
end loop;
end if;
end if;
end if;
end loop;
FIRST := false;
end if;
if rising_edge (Sys_clk) then
if (Write_n = '0') then
Read_reg_o := '0';
else
Read_reg_o := Read_reg;
end if;
if (Write_n = '0') then
Read_reg := '0';
else
Read_reg := Read;
end if;
Read_reg1 <= Read_reg;
Read_reg_o1 <= Read_reg_o;
if (Read_reg = '1') then
pcsr_write := '0';
ctlr_write := '0';
end if;
-- Write Register
if (Read_reg_o = '1') then
WrN_reg := '1';
else
WrN_reg := Write_n;
end if;
WrN_reg1 <= WrN_reg;
latch_addr_old := latch_addr_current;
latch_addr_current := latch_addr;
if (latch_addr_old = '1' and (Write_n = '0') and ADSP_N_o = '0') then
pcsr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
elsif (latch_addr_current = '1' and (Write_n = '0') and inADSP = '1' and inADSC = '0') then
ctlr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
end if;
-- ADDRess Register
if (latch_addr = '1') then
addr_reg_in := iADDR;
bcount := iADDR (1 downto 0);
first_addr := iADDR (1 downto 0);
end if;
addr_reg_in1 <= addr_reg_in;
-- ADSP_N Previous-Cycle Register
ADSP_N_o <= inADSP;
pcsr_write1 <= pcsr_write;
ctlr_write1 <= ctlr_write;
first_addr_int := CONV_INTEGER1 (first_addr);
-- Binary Counter and Logic
if ((iMode = '0') and (inADV = '0') and (latch_addr = '0')) then -- Linear Burst
bcount := (bcount + '1'); -- Advance Counter
elsif ((iMode = '1') and (inADV = '0') and (latch_addr = '0')) then -- Interleaved Burst
if ((first_addr_int REM 2) = 0) then
bcount := (bcount + '1'); -- Increment Counter
elsif ((first_addr_int REM 2) = 1) then
bcount := (bcount - '1'); -- Decrement Counter
end if;
end if;
-- Read ADDRess
addr_reg_read := addr_reg_write;
addr_reg_read1 <= addr_reg_read;
-- Write ADDRess
addr_reg_write := addr_reg_in ((addr_bits - 1) downto 2) & bcount(1) & bcount(0);
addr_reg_write1 <= addr_reg_write;
-- Byte Write Register
bwa_reg := not bwa_n1;
bwb_reg := not bwb_n1;
bwc_reg := not bwc_n1;
bwd_reg := not bwd_n1;
-- Enable Register
pipe_reg := ce_reg;
-- Enable Register
if (latch_addr = '1') then
ce_reg := ce;
end if;
pipe_reg1 <= pipe_reg;
ce_reg1 <= ce_reg;
-- Input Register
if ((ce_reg = '1') and ((bwa_n1 ='0') or (bwb_n1 = '0') or (bwc_n1 = '0') or (bwd_n1 = '0')) and
((pcsr_write = '1') or (ctlr_write = '1'))) then
din := ioDQ;
end if;
din1 <= din;
-- Byte Write Driver
if ((ce_reg = '1') and (bwa_reg = '1')) then
bank0 (CONV_INTEGER1 (addr_reg_write)) := din (8 downto 0);
end if;
if ((ce_reg = '1') and (bwb_reg = '1')) then
bank1 (CONV_INTEGER1 (addr_reg_write)) := din (17 downto 9);
end if;
if ((ce_reg = '1') and (bwc_reg = '1')) then
bank2 (CONV_INTEGER1 (addr_reg_write)) := din (26 downto 18);
end if;
if ((ce_reg = '1') and (bwd_reg = '1')) then
bank3 (CONV_INTEGER1 (addr_reg_write)) := din (35 downto 27);
end if;
-- Output Registers
if ((Write_n = '0') or (pipe_reg = '0')) then
dout (35 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" after Cyp_tCHZ;
elsif (Read_reg_o = '1') then
dout ( 8 downto 0) <= bank0 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (17 downto 9) <= bank1 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (26 downto 18) <= bank2 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (35 downto 27) <= bank3 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
end if;
end if;
end process;
-- Output Buffers
ioDQ <= dout when ((inOE ='0') and (iZZ='0') and (Pipe_efct='1') and (RD_efct='1') and (WR_efct='1'))
else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
clk_check : PROCESS
VARIABLE clk_high, clk_low : TIME := 0 ns;
BEGIN
WAIT ON iClk;
IF iClk = '1' AND NOW >= Cyp_tCYC THEN
ASSERT (NOW - clk_low >= Cyp_tCH)
REPORT "Clk width low - tCH violation"
SEVERITY ERROR;
ASSERT (NOW - clk_high >= Cyp_tCYC)
REPORT "Clk period high - tCYC violation"
SEVERITY ERROR;
clk_high := NOW;
ELSIF iClk = '0' AND NOW /= 0 ns THEN
ASSERT (NOW - clk_high >= Cyp_tCL)
REPORT "Clk width high - tCL violation"
SEVERITY ERROR;
ASSERT (NOW - clk_low >= Cyp_tCYC)
REPORT "Clk period low - tCYC violation"
SEVERITY ERROR;
clk_low := NOW;
END IF;
END PROCESS;
-- Check for Setup Timing Violation
setup_check : PROCESS
BEGIN
WAIT ON iClk;
IF iClk = '1' THEN
ASSERT (iAddr'LAST_EVENT >= Cyp_tAS)
REPORT "Addr - tAS violation"
SEVERITY ERROR;
ASSERT (inGW'LAST_EVENT >= Cyp_tWES)
REPORT "GW# - tWES violation"
SEVERITY ERROR;
ASSERT (inBWE'LAST_EVENT >= Cyp_tWES)
REPORT "BWE# - tWES violation"
SEVERITY ERROR;
ASSERT (inCe1'LAST_EVENT >= Cyp_tWES)
REPORT "CE1# - tWES violation"
SEVERITY ERROR;
ASSERT (iCe2'LAST_EVENT >= Cyp_tWES)
REPORT "CE2 - tWES violation"
SEVERITY ERROR;
ASSERT (inCe3'LAST_EVENT >= Cyp_tWES)
REPORT "CE3# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdv'LAST_EVENT >= Cyp_tADVS)
REPORT "ADV# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdsp'LAST_EVENT >= Cyp_tADVS)
REPORT "ADSP# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdsc'LAST_EVENT >= Cyp_tADVS)
REPORT "ADSC# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwa'LAST_EVENT >= Cyp_tWES)
REPORT "BWa# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwb'LAST_EVENT >= Cyp_tWES)
REPORT "BWb# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwc'LAST_EVENT >= Cyp_tWES)
REPORT "BWc# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwd'LAST_EVENT >= Cyp_tWES)
REPORT "BWd# - tWES violation"
SEVERITY ERROR;
ASSERT (ioDq'LAST_EVENT >= Cyp_tDS)
REPORT "Dq - tDS violation"
SEVERITY ERROR;
END IF;
END PROCESS;
-- Check for Hold Timing Violation
hold_check : PROCESS
BEGIN
WAIT ON iClk'DELAYED(Cyp_tAH), iClk'DELAYED(Cyp_tWEH), iClk'DELAYED(Cyp_tDH);
IF iClk'DELAYED(Cyp_tAH) = '1' THEN
ASSERT (iAddr'LAST_EVENT > Cyp_tAH)
REPORT "Addr - tAH violation"
SEVERITY ERROR;
END IF;
IF iClk'DELAYED(Cyp_tDH) = '1' THEN
ASSERT (ioDq'LAST_EVENT > Cyp_tDH)
REPORT "Dq - tDH violation"
SEVERITY ERROR;
END IF;
IF iClk'DELAYED(Cyp_tWEH) = '1' THEN
ASSERT (inCe1'LAST_EVENT > Cyp_tWEH)
REPORT "CE1# - tWEH violation"
SEVERITY ERROR;
ASSERT (iCe2'LAST_EVENT > Cyp_tWEH)
REPORT "CE2 - tWEH violation"
SEVERITY ERROR;
ASSERT (inCe3'LAST_EVENT > Cyp_tWEH)
REPORT "CE3 - tWEH violation"
SEVERITY ERROR;
ASSERT (inAdv'LAST_EVENT > Cyp_tWEH)
REPORT "ADV# - tWEH violation"
SEVERITY ERROR;
ASSERT (inADSP'LAST_EVENT > Cyp_tWEH)
REPORT "ADSP# - tWEH violation"
SEVERITY ERROR;
ASSERT (inADSC'LAST_EVENT > Cyp_tWEH)
REPORT "ADSC# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwa'LAST_EVENT > Cyp_tWEH)
REPORT "BWa# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwb'LAST_EVENT > Cyp_tWEH)
REPORT "BWb# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwc'LAST_EVENT > Cyp_tWEH)
REPORT "BWc# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwd'LAST_EVENT > Cyp_tWEH)
REPORT "BWd# - tWEH violation"
SEVERITY ERROR;
END IF;
END PROCESS;
end CY7C1380D_arch;
|
--***************************************************************************************
--
-- File Name: CY7C1380_PL_SCD.vhd
-- Version: 1.0
-- Date: December 22nd, 2004
-- Model: BUS Functional
-- Simulator: Modelsim
--
--
-- Queries: MPD Applications
-- Website: www.cypress.com/support
-- Company: Cypress Semiconductor
-- Part #: CY7C1380D (512K x 36)
--
-- Description: Cypress 18Mb Synburst SRAM (Pipelined SCD)
--
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright(c) Cypress Semiconductor, 2004
-- All rights reserved
--
-- Rev Date Changes
-- --- ---------- ---------------------------------------
-- 1.0 12/22/2004 - New Model
-- - New Test Bench
-- - New Test Vectors
--
--***************************************************************************************
-- Timings for Different Speed Bins (sb): 250MHz, 225MHz, 200MHz, 167MHz, 133MHz
LIBRARY ieee, grlib, work;
USE ieee.std_logic_1164.all;
-- USE ieee.std_logic_unsigned.all;
-- Use IEEE.Std_Logic_Arith.all;
USE work.package_utility.all;
use grlib.stdlib.all;
use grlib.stdio.all;
use ieee.std_logic_1164.all;
use std.textio.all;
entity CY7C1380D is
GENERIC (
fname : string := "prom.srec"; -- File to read from
-- Constant Parameters
addr_bits : INTEGER := 19; -- This is external address
data_bits : INTEGER := 36;
--Clock timings for 250Mhz
Cyp_tCO : TIME := 2.6 ns; -- Data Output Valid After CLK Rise
Cyp_tCYC : TIME := 4.0 ns; -- Clock cycle time
Cyp_tCH : TIME := 1.7 ns; -- Clock HIGH time
Cyp_tCL : TIME := 1.7 ns; -- Clock LOW time
Cyp_tCHZ : TIME := 2.6 ns; -- Clock to High-Z
Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
Cyp_tOEHZ : TIME := 2.6 ns; -- OE# HIGH to Output High-Z
Cyp_tOELZ : TIME := 0.0 ns; -- OE# LOW to Output Low-Z
Cyp_tOEV : TIME := 2.6 ns; -- OE# LOW to Output Valid
Cyp_tAS : TIME := 1.2 ns; -- Address Set-up Before CLK Rise
Cyp_tADS : TIME := 1.2 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
Cyp_tADVS : TIME := 1.2 ns; -- ADV# Set-up Before CLK Rise
Cyp_tWES : TIME := 1.2 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
Cyp_tDS : TIME := 1.2 ns; -- Data Input Set-up Before CLK Rise
Cyp_tCES : TIME := 1.2 ns; -- Chip Enable Set-up
Cyp_tAH : TIME := 0.3 ns; -- Address Hold After CLK Rise
Cyp_tADH : TIME := 0.3 ns; -- ADSC#, ADSP# Hold After CLK Rise
Cyp_tADVH : TIME := 0.3 ns; -- ADV# Hold After CLK Rise
Cyp_tWEH : TIME := 0.3 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
Cyp_tDH : TIME := 0.3 ns; -- Data Input Hold After CLK Rise
Cyp_tCEH : TIME := 0.3 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 225Mhz
-- Cyp_tCO : TIME := 2.8 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 4.4 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 2.8 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 2.8 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 2.8 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 200Mhz
-- Cyp_tCO : TIME := 3.0 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 5.0 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.0 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 3.0 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 3.0 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 167Mhz
-- Cyp_tCO : TIME := 3.4 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 6.0 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.2 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.2 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.4 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 3.4 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 3.4 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
--Clock timings for 133Mhz
-- Cyp_tCO : TIME := 4.2 ns; -- Data Output Valid After CLK Rise
-- Cyp_tCYC : TIME := 7.5 ns; -- Clock cycle time
-- Cyp_tCH : TIME := 2.5 ns; -- Clock HIGH time
-- Cyp_tCL : TIME := 2.5 ns; -- Clock LOW time
-- Cyp_tCHZ : TIME := 3.4 ns; -- Clock to High-Z
-- Cyp_tCLZ : TIME := 1.3 ns; -- Clock to Low-Z
-- Cyp_tOEHZ: TIME := 4.0 ns; -- OE# HIGH to Output High-Z
-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
-- Cyp_tOEV : TIME := 4.2 ns; -- OE# LOW to Output Valid
-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
);
PORT (iZZ : IN STD_LOGIC;
iMode : IN STD_LOGIC;
iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0);
inGW : IN STD_LOGIC;
inBWE : IN STD_LOGIC;
inBWd : IN STD_LOGIC;
inBWc : IN STD_LOGIC;
inBWb : IN STD_LOGIC;
inBWa : IN STD_LOGIC;
inCE1 : IN STD_LOGIC;
iCE2 : IN STD_LOGIC;
inCE3 : IN STD_LOGIC;
inADSP : IN STD_LOGIC;
inADSC : IN STD_LOGIC;
inADV : IN STD_LOGIC;
inOE : IN STD_LOGIC;
ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0);
iCLK : IN STD_LOGIC);
end CY7C1380D;
ARCHITECTURE CY7C1380D_arch OF CY7C1380D IS
signal Read_reg_o1, Read_reg1 : STD_LOGIC;
signal WrN_reg1 : STD_LOGIC;
signal ADSP_N_o : STD_LOGIC;
signal pipe_reg1, ce_reg1,pcsr_write1, ctlr_write1 : STD_LOGIC;
signal Sys_clk : STD_LOGIC := '0';
signal test : STD_LOGIC;
signal dout, din1 : STD_LOGIC_VECTOR (data_bits-1 downto 0);
signal ce : STD_LOGIC;
signal Write_n : STD_LOGIC;
signal Read : STD_LOGIC;
signal bwa_n1 : STD_LOGIC;
signal bwb_n1 : STD_LOGIC;
signal bwc_n1 : STD_LOGIC;
signal bwd_n1 : STD_LOGIC;
signal latch_addr : STD_LOGIC;
signal addr_reg_read1,addr_reg_write1,addr_reg_in1 : STD_LOGIC_VECTOR (addr_bits-1 downto 0);
signal OeN_HZ : STD_LOGIC;
signal OeN_DataValid : STD_LOGIC;
signal OeN_efct : STD_LOGIC;
signal WR_HZ : STD_LOGIC;
signal WR_LZ : STD_LOGIC;
signal WR_efct : STD_LOGIC;
signal CE_HZ : STD_LOGIC;
signal CE_LZ : STD_LOGIC;
signal Pipe_efct : STD_LOGIC;
signal RD_HZ : STD_LOGIC;
signal RD_LZ : STD_LOGIC;
signal RD_efct : STD_LOGIC;
begin
ce <= ((not inCE1) and (iCE2) and (not inCE3));
Write_n <= not((((not inBWa) OR (not inBWb) OR (not inBWc) OR (not inBWd)) AND (not inBWE)) OR (not inGW));
Read <= (((inBWa AND inBWb AND inBWc AND inBWd) AND (not inBWE)) OR (inGW AND inBWE) OR (( not inADSP) AND ce));
bwa_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWa))));
bwb_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWb))));
bwc_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWc))));
bwd_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWd))));
latch_addr <= ((not inADSC) OR ((not inADSP) AND (not inCE1)));
OeN_efct <= OeN_DataValid when (inOE = '0') else OeN_HZ;
WR_efct <= WR_LZ when (WrN_reg1 = '0') else WR_HZ;
Pipe_efct <= CE_LZ when ((ce_reg1 = '1') and (pipe_reg1 = '1')) else CE_HZ;
RD_efct <= CE_LZ when (Read_reg_o1 = '1') else CE_HZ ;
Process (Read_reg_o1)
begin
if (Read_reg_o1 = '0') then
RD_HZ <= '0' after Cyp_tCHZ;
RD_LZ <= '0' after Cyp_tCLZ;
elsif (Read_reg_o1 = '1') then
RD_HZ <= '1' after Cyp_tCHZ;
RD_LZ <= '1' after Cyp_tCLZ;
else
RD_HZ <= 'X' after Cyp_tCHZ;
RD_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
Process (pipe_reg1)
begin
if (pipe_reg1 = '1') then
CE_LZ <= '1' after Cyp_tCLZ;
elsif (pipe_reg1 = '0') then
CE_LZ <= '0' after Cyp_tCLZ;
else
CE_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
-- System Clock Decode
Process (iclk)
variable Sys_clk1 : std_logic := '0';
begin
if (rising_edge (iclk)) then
Sys_clk1 := not iZZ;
end if;
if (falling_edge (iCLK)) then
Sys_clk1 := '0';
end if;
Sys_clk <= Sys_clk1;
end process;
Process (WrN_reg1)
begin
if (WrN_reg1 = '1') then
WR_HZ <= '1' after Cyp_tCHZ;
WR_LZ <= '1' after Cyp_tCLZ;
elsif (WrN_reg1 = '0') then
WR_HZ <= '0' after Cyp_tCHZ;
WR_LZ <= '0' after Cyp_tCLZ;
else
WR_HZ <= 'X' after Cyp_tCHZ;
WR_LZ <= 'X' after Cyp_tCLZ;
end if;
end process;
Process (inOE)
begin
if (inOE = '1') then
OeN_HZ <= '1' after Cyp_tOEHZ;
OeN_DataValid <= '1' after Cyp_tOEV;
elsif (inOE = '0') then
OeN_HZ <= '0' after Cyp_tOEHZ;
OeN_DataValid <= '0' after Cyp_tOEV;
else
OeN_HZ <= 'X' after Cyp_tOEHZ;
OeN_DataValid <= 'X' after Cyp_tOEV;
end if;
end process;
process (ce_reg1, pipe_reg1)
begin
if ((ce_reg1 = '0') or (pipe_reg1 = '0')) then
CE_HZ <= '0' after Cyp_tCHZ;
elsif ((ce_reg1 = '1') and (pipe_reg1 = '1')) then
CE_HZ <= '1' after Cyp_tCHZ;
else
CE_HZ <= 'X' after Cyp_tCHZ;
end if;
end process;
Process (Sys_clk)
TYPE memory_array IS ARRAY ((2**addr_bits -1) DOWNTO 0) OF STD_LOGIC_VECTOR ((data_bits/4) - 1 DOWNTO 0);
variable Read_reg_o : std_logic;
variable Read_reg : std_logic;
variable pcsr_write, ctlr_write : std_logic;
variable WrN_reg : std_logic;
variable latch_addr_old, latch_addr_current : std_logic;
variable addr_reg_in, addr_reg_read, addr_reg_write : std_logic_vector (addr_bits -1 downto 0) := (others => '0');
variable bcount, first_addr : std_logic_vector (1 downto 0) := "00";
variable bwa_reg,bwb_reg,bwc_reg,bwd_reg, pipe_reg, ce_reg : std_logic;
variable din : std_logic_vector (data_bits-1 downto 0);
variable first_addr_int : integer;
variable bank0 : memory_array;
variable bank1 : memory_array;
variable bank2 : memory_array;
variable bank3 : memory_array;
variable FIRST : boolean := true;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable CH : character;
variable ai : integer := 0;
variable L1 : line;
begin
if FIRST then
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
std.textio.read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
hread(L1, recdata);
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
bank3 (ai+i) := "0000" & recdata((i*32) to (i*32+4));
bank2 (ai+i) := recdata((i*32+5) to (i*32+13));
bank1 (ai+i) := recdata((i*32+14) to (i*32+22));
bank0 (ai+i) := recdata((i*32+23) to (i*32+31));
end loop;
end if;
end if;
end if;
end loop;
FIRST := false;
end if;
if rising_edge (Sys_clk) then
if (Write_n = '0') then
Read_reg_o := '0';
else
Read_reg_o := Read_reg;
end if;
if (Write_n = '0') then
Read_reg := '0';
else
Read_reg := Read;
end if;
Read_reg1 <= Read_reg;
Read_reg_o1 <= Read_reg_o;
if (Read_reg = '1') then
pcsr_write := '0';
ctlr_write := '0';
end if;
-- Write Register
if (Read_reg_o = '1') then
WrN_reg := '1';
else
WrN_reg := Write_n;
end if;
WrN_reg1 <= WrN_reg;
latch_addr_old := latch_addr_current;
latch_addr_current := latch_addr;
if (latch_addr_old = '1' and (Write_n = '0') and ADSP_N_o = '0') then
pcsr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
elsif (latch_addr_current = '1' and (Write_n = '0') and inADSP = '1' and inADSC = '0') then
ctlr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
end if;
-- ADDRess Register
if (latch_addr = '1') then
addr_reg_in := iADDR;
bcount := iADDR (1 downto 0);
first_addr := iADDR (1 downto 0);
end if;
addr_reg_in1 <= addr_reg_in;
-- ADSP_N Previous-Cycle Register
ADSP_N_o <= inADSP;
pcsr_write1 <= pcsr_write;
ctlr_write1 <= ctlr_write;
first_addr_int := CONV_INTEGER1 (first_addr);
-- Binary Counter and Logic
if ((iMode = '0') and (inADV = '0') and (latch_addr = '0')) then -- Linear Burst
bcount := (bcount + '1'); -- Advance Counter
elsif ((iMode = '1') and (inADV = '0') and (latch_addr = '0')) then -- Interleaved Burst
if ((first_addr_int REM 2) = 0) then
bcount := (bcount + '1'); -- Increment Counter
elsif ((first_addr_int REM 2) = 1) then
bcount := (bcount - '1'); -- Decrement Counter
end if;
end if;
-- Read ADDRess
addr_reg_read := addr_reg_write;
addr_reg_read1 <= addr_reg_read;
-- Write ADDRess
addr_reg_write := addr_reg_in ((addr_bits - 1) downto 2) & bcount(1) & bcount(0);
addr_reg_write1 <= addr_reg_write;
-- Byte Write Register
bwa_reg := not bwa_n1;
bwb_reg := not bwb_n1;
bwc_reg := not bwc_n1;
bwd_reg := not bwd_n1;
-- Enable Register
pipe_reg := ce_reg;
-- Enable Register
if (latch_addr = '1') then
ce_reg := ce;
end if;
pipe_reg1 <= pipe_reg;
ce_reg1 <= ce_reg;
-- Input Register
if ((ce_reg = '1') and ((bwa_n1 ='0') or (bwb_n1 = '0') or (bwc_n1 = '0') or (bwd_n1 = '0')) and
((pcsr_write = '1') or (ctlr_write = '1'))) then
din := ioDQ;
end if;
din1 <= din;
-- Byte Write Driver
if ((ce_reg = '1') and (bwa_reg = '1')) then
bank0 (CONV_INTEGER1 (addr_reg_write)) := din (8 downto 0);
end if;
if ((ce_reg = '1') and (bwb_reg = '1')) then
bank1 (CONV_INTEGER1 (addr_reg_write)) := din (17 downto 9);
end if;
if ((ce_reg = '1') and (bwc_reg = '1')) then
bank2 (CONV_INTEGER1 (addr_reg_write)) := din (26 downto 18);
end if;
if ((ce_reg = '1') and (bwd_reg = '1')) then
bank3 (CONV_INTEGER1 (addr_reg_write)) := din (35 downto 27);
end if;
-- Output Registers
if ((Write_n = '0') or (pipe_reg = '0')) then
dout (35 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" after Cyp_tCHZ;
elsif (Read_reg_o = '1') then
dout ( 8 downto 0) <= bank0 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (17 downto 9) <= bank1 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (26 downto 18) <= bank2 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
dout (35 downto 27) <= bank3 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
end if;
end if;
end process;
-- Output Buffers
ioDQ <= dout when ((inOE ='0') and (iZZ='0') and (Pipe_efct='1') and (RD_efct='1') and (WR_efct='1'))
else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
clk_check : PROCESS
VARIABLE clk_high, clk_low : TIME := 0 ns;
BEGIN
WAIT ON iClk;
IF iClk = '1' AND NOW >= Cyp_tCYC THEN
ASSERT (NOW - clk_low >= Cyp_tCH)
REPORT "Clk width low - tCH violation"
SEVERITY ERROR;
ASSERT (NOW - clk_high >= Cyp_tCYC)
REPORT "Clk period high - tCYC violation"
SEVERITY ERROR;
clk_high := NOW;
ELSIF iClk = '0' AND NOW /= 0 ns THEN
ASSERT (NOW - clk_high >= Cyp_tCL)
REPORT "Clk width high - tCL violation"
SEVERITY ERROR;
ASSERT (NOW - clk_low >= Cyp_tCYC)
REPORT "Clk period low - tCYC violation"
SEVERITY ERROR;
clk_low := NOW;
END IF;
END PROCESS;
-- Check for Setup Timing Violation
setup_check : PROCESS
BEGIN
WAIT ON iClk;
IF iClk = '1' THEN
ASSERT (iAddr'LAST_EVENT >= Cyp_tAS)
REPORT "Addr - tAS violation"
SEVERITY ERROR;
ASSERT (inGW'LAST_EVENT >= Cyp_tWES)
REPORT "GW# - tWES violation"
SEVERITY ERROR;
ASSERT (inBWE'LAST_EVENT >= Cyp_tWES)
REPORT "BWE# - tWES violation"
SEVERITY ERROR;
ASSERT (inCe1'LAST_EVENT >= Cyp_tWES)
REPORT "CE1# - tWES violation"
SEVERITY ERROR;
ASSERT (iCe2'LAST_EVENT >= Cyp_tWES)
REPORT "CE2 - tWES violation"
SEVERITY ERROR;
ASSERT (inCe3'LAST_EVENT >= Cyp_tWES)
REPORT "CE3# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdv'LAST_EVENT >= Cyp_tADVS)
REPORT "ADV# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdsp'LAST_EVENT >= Cyp_tADVS)
REPORT "ADSP# - tWES violation"
SEVERITY ERROR;
ASSERT (inAdsc'LAST_EVENT >= Cyp_tADVS)
REPORT "ADSC# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwa'LAST_EVENT >= Cyp_tWES)
REPORT "BWa# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwb'LAST_EVENT >= Cyp_tWES)
REPORT "BWb# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwc'LAST_EVENT >= Cyp_tWES)
REPORT "BWc# - tWES violation"
SEVERITY ERROR;
ASSERT (inBwd'LAST_EVENT >= Cyp_tWES)
REPORT "BWd# - tWES violation"
SEVERITY ERROR;
ASSERT (ioDq'LAST_EVENT >= Cyp_tDS)
REPORT "Dq - tDS violation"
SEVERITY ERROR;
END IF;
END PROCESS;
-- Check for Hold Timing Violation
hold_check : PROCESS
BEGIN
WAIT ON iClk'DELAYED(Cyp_tAH), iClk'DELAYED(Cyp_tWEH), iClk'DELAYED(Cyp_tDH);
IF iClk'DELAYED(Cyp_tAH) = '1' THEN
ASSERT (iAddr'LAST_EVENT > Cyp_tAH)
REPORT "Addr - tAH violation"
SEVERITY ERROR;
END IF;
IF iClk'DELAYED(Cyp_tDH) = '1' THEN
ASSERT (ioDq'LAST_EVENT > Cyp_tDH)
REPORT "Dq - tDH violation"
SEVERITY ERROR;
END IF;
IF iClk'DELAYED(Cyp_tWEH) = '1' THEN
ASSERT (inCe1'LAST_EVENT > Cyp_tWEH)
REPORT "CE1# - tWEH violation"
SEVERITY ERROR;
ASSERT (iCe2'LAST_EVENT > Cyp_tWEH)
REPORT "CE2 - tWEH violation"
SEVERITY ERROR;
ASSERT (inCe3'LAST_EVENT > Cyp_tWEH)
REPORT "CE3 - tWEH violation"
SEVERITY ERROR;
ASSERT (inAdv'LAST_EVENT > Cyp_tWEH)
REPORT "ADV# - tWEH violation"
SEVERITY ERROR;
ASSERT (inADSP'LAST_EVENT > Cyp_tWEH)
REPORT "ADSP# - tWEH violation"
SEVERITY ERROR;
ASSERT (inADSC'LAST_EVENT > Cyp_tWEH)
REPORT "ADSC# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwa'LAST_EVENT > Cyp_tWEH)
REPORT "BWa# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwb'LAST_EVENT > Cyp_tWEH)
REPORT "BWb# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwc'LAST_EVENT > Cyp_tWEH)
REPORT "BWc# - tWEH violation"
SEVERITY ERROR;
ASSERT (inBwd'LAST_EVENT > Cyp_tWEH)
REPORT "BWd# - tWEH violation"
SEVERITY ERROR;
END IF;
END PROCESS;
end CY7C1380D_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity ADDER_PROCESS is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
O : out STD_LOGIC_VECTOR (7 downto 0));
end ADDER_PROCESS;
architecture Behavioral of ADDER_PROCESS is
begin
O <= A + B;
end Behavioral;
|
-- NEED RESULT: ARCH00085.P1: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P2: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P3: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P4: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P5: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P6: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P7: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P8: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P9: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P10: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P11: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P12: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P13: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P14: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P15: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P16: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P17: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: P17: Transport transactions entirely completed passed
-- NEED RESULT: P16: Transport transactions entirely completed passed
-- NEED RESULT: P15: Transport transactions entirely completed passed
-- NEED RESULT: P14: Transport transactions entirely completed passed
-- NEED RESULT: P13: Transport transactions entirely completed passed
-- NEED RESULT: P12: Transport transactions entirely completed passed
-- NEED RESULT: P11: Transport transactions entirely completed passed
-- NEED RESULT: P10: Transport transactions entirely completed passed
-- NEED RESULT: P9: Transport transactions entirely completed passed
-- NEED RESULT: P8: Transport transactions entirely completed passed
-- NEED RESULT: P7: Transport transactions entirely completed passed
-- NEED RESULT: P6: Transport transactions entirely completed passed
-- NEED RESULT: P5: Transport transactions entirely completed passed
-- NEED RESULT: P4: Transport transactions entirely completed passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00085
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00085(ARCH00085)
-- ENT00085_Test_Bench(ARCH00085_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00085 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_bit_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_phys1_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_real1_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_boolean_vector : inout st_boolean_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_boolean_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P1" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_boolean_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_bit_vector : inout st_bit_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_bit_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P2" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_bit_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_severity_level_vector : inout st_severity_level_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_severity_level_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P3" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_severity_level_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
procedure Proc4 (
signal s_st_string : inout st_string ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_string : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_2 (lowb+1 to lowb+3) after 10 ns,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P4" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_string <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc4 ;
--
procedure Proc5 (
signal s_st_enum1_vector : inout st_enum1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_enum1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P5" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc5 ;
--
procedure Proc6 (
signal s_st_integer_vector : inout st_integer_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_integer_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P6" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_integer_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc6 ;
--
procedure Proc7 (
signal s_st_int1_vector : inout st_int1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_int1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P7" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc7 ;
--
procedure Proc8 (
signal s_st_time_vector : inout st_time_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_time_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P8" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_time_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc8 ;
--
procedure Proc9 (
signal s_st_phys1_vector : inout st_phys1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_phys1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P9" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc9 ;
--
procedure Proc10 (
signal s_st_real_vector : inout st_real_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_real_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P10" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc10 ;
--
procedure Proc11 (
signal s_st_real1_vector : inout st_real1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_real1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P11" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc11 ;
--
procedure Proc12 (
signal s_st_rec1_vector : inout st_rec1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P12" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc12 ;
--
procedure Proc13 (
signal s_st_rec2_vector : inout st_rec2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P13" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc13 ;
--
procedure Proc14 (
signal s_st_rec3_vector : inout st_rec3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P14" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc14 ;
--
procedure Proc15 (
signal s_st_arr1_vector : inout st_arr1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P15" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc15 ;
--
procedure Proc16 (
signal s_st_arr2_vector : inout st_arr2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P16" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc16 ;
--
procedure Proc17 (
signal s_st_arr3_vector : inout st_arr3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P17" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc17 ;
--
--
end ENT00085 ;
--
architecture ARCH00085 of ENT00085 is
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_bit_vector : st_bit_vector
:= c_st_bit_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_phys1_vector : st_phys1_vector
:= c_st_phys1_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_real1_vector : st_real1_vector
:= c_st_real1_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_boolean_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_boolean_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_boolean_vector,
counter,
correct,
savtime,
chk_st_boolean_vector
) ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_bit_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_bit_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_bit_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_bit_vector,
counter,
correct,
savtime,
chk_st_bit_vector
) ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_severity_level_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_severity_level_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_severity_level_vector,
counter,
correct,
savtime,
chk_st_severity_level_vector
) ;
end process P3 ;
--
PGEN_CHKP_4 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions entirely completed",
chk_st_string = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P4 :
process ( s_st_string )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc4 (
s_st_string,
counter,
correct,
savtime,
chk_st_string
) ;
end process P4 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions entirely completed",
chk_st_enum1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P5 :
process ( s_st_enum1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc5 (
s_st_enum1_vector,
counter,
correct,
savtime,
chk_st_enum1_vector
) ;
end process P5 ;
--
PGEN_CHKP_6 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions entirely completed",
chk_st_integer_vector = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P6 :
process ( s_st_integer_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc6 (
s_st_integer_vector,
counter,
correct,
savtime,
chk_st_integer_vector
) ;
end process P6 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions entirely completed",
chk_st_int1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P7 :
process ( s_st_int1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc7 (
s_st_int1_vector,
counter,
correct,
savtime,
chk_st_int1_vector
) ;
end process P7 ;
--
PGEN_CHKP_8 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions entirely completed",
chk_st_time_vector = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P8 :
process ( s_st_time_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc8 (
s_st_time_vector,
counter,
correct,
savtime,
chk_st_time_vector
) ;
end process P8 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions entirely completed",
chk_st_phys1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P9 :
process ( s_st_phys1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc9 (
s_st_phys1_vector,
counter,
correct,
savtime,
chk_st_phys1_vector
) ;
end process P9 ;
--
PGEN_CHKP_10 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions entirely completed",
chk_st_real_vector = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P10 :
process ( s_st_real_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc10 (
s_st_real_vector,
counter,
correct,
savtime,
chk_st_real_vector
) ;
end process P10 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Transport transactions entirely completed",
chk_st_real1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P11 :
process ( s_st_real1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc11 (
s_st_real1_vector,
counter,
correct,
savtime,
chk_st_real1_vector
) ;
end process P11 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Transport transactions entirely completed",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P12 :
process ( s_st_rec1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc12 (
s_st_rec1_vector,
counter,
correct,
savtime,
chk_st_rec1_vector
) ;
end process P12 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Transport transactions entirely completed",
chk_st_rec2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P13 :
process ( s_st_rec2_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc13 (
s_st_rec2_vector,
counter,
correct,
savtime,
chk_st_rec2_vector
) ;
end process P13 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Transport transactions entirely completed",
chk_st_rec3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P14 :
process ( s_st_rec3_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc14 (
s_st_rec3_vector,
counter,
correct,
savtime,
chk_st_rec3_vector
) ;
end process P14 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Transport transactions entirely completed",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P15 :
process ( s_st_arr1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc15 (
s_st_arr1_vector,
counter,
correct,
savtime,
chk_st_arr1_vector
) ;
end process P15 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Transport transactions entirely completed",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P16 :
process ( s_st_arr2_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc16 (
s_st_arr2_vector,
counter,
correct,
savtime,
chk_st_arr2_vector
) ;
end process P16 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Transport transactions entirely completed",
chk_st_arr3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
P17 :
process ( s_st_arr3_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc17 (
s_st_arr3_vector,
counter,
correct,
savtime,
chk_st_arr3_vector
) ;
end process P17 ;
--
--
end ARCH00085 ;
--
entity ENT00085_Test_Bench is
end ENT00085_Test_Bench ;
--
architecture ARCH00085_Test_Bench of ENT00085_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00085 ( ARCH00085 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00085_Test_Bench ;
|
------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx/Lattice BRAM ----
---- ----
---- This file is part FPGA Libre project http://fpgalibre.sf.net/ ----
---- ----
---- Description: ----
---- This is a program memory for the AVR. It maps to a Xilinx/Lattice ----
---- BRAM. ----
---- This version can be modified by the CPU (i. e. SPM instruction) ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008-2017 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008-2017 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortPM(Xilinx) (Entity and architecture) ----
---- File name: pm_s_rw.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- iCE40 (iCE40HX4K) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- iCEcube2.2016.02 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity lattuino_1_blPM_8 is
generic(
WORD_SIZE : integer:=16; -- Word Size
FALL_EDGE : std_logic:='0'; -- Ram clock falling edge
ADDR_W : integer:=13); -- Address Width
port(
clk_i : in std_logic;
addr_i : in std_logic_vector(ADDR_W-1 downto 0);
data_o : out std_logic_vector(WORD_SIZE-1 downto 0);
we_i : in std_logic;
data_i : in std_logic_vector(WORD_SIZE-1 downto 0));
end entity lattuino_1_blPM_8;
architecture Xilinx of lattuino_1_blPM_8 is
constant ROM_SIZE : natural:=2**ADDR_W;
type rom_t is array(natural range 0 to ROM_SIZE-1) of std_logic_vector(WORD_SIZE-1 downto 0);
signal addr_r : std_logic_vector(ADDR_W-1 downto 0);
signal rom : rom_t :=
(
3768 => x"c00e",
3769 => x"c01d",
3770 => x"c01c",
3771 => x"c01b",
3772 => x"c01a",
3773 => x"c019",
3774 => x"c018",
3775 => x"c017",
3776 => x"c016",
3777 => x"c015",
3778 => x"c014",
3779 => x"c013",
3780 => x"c012",
3781 => x"c011",
3782 => x"c010",
3783 => x"2411",
3784 => x"be1f",
3785 => x"e5cf",
3786 => x"e0d2",
3787 => x"bfde",
3788 => x"bfcd",
3789 => x"e020",
3790 => x"e6a0",
3791 => x"e0b0",
3792 => x"c001",
3793 => x"921d",
3794 => x"36a5",
3795 => x"07b2",
3796 => x"f7e1",
3797 => x"d036",
3798 => x"c125",
3799 => x"cfe0",
3800 => x"e081",
3801 => x"bb8f",
3802 => x"e681",
3803 => x"ee93",
3804 => x"e1a6",
3805 => x"e0b0",
3806 => x"99f1",
3807 => x"c00a",
3808 => x"9701",
3809 => x"09a1",
3810 => x"09b1",
3811 => x"9700",
3812 => x"05a1",
3813 => x"05b1",
3814 => x"f7b9",
3815 => x"e0e0",
3816 => x"e0f0",
3817 => x"9509",
3818 => x"ba1f",
3819 => x"b38e",
3820 => x"9508",
3821 => x"e091",
3822 => x"bb9f",
3823 => x"9bf0",
3824 => x"cffe",
3825 => x"ba1f",
3826 => x"bb8e",
3827 => x"e080",
3828 => x"e090",
3829 => x"9508",
3830 => x"dfe1",
3831 => x"3280",
3832 => x"f421",
3833 => x"e184",
3834 => x"dff2",
3835 => x"e180",
3836 => x"cff0",
3837 => x"9508",
3838 => x"93cf",
3839 => x"2fc8",
3840 => x"dfd7",
3841 => x"3280",
3842 => x"f439",
3843 => x"e184",
3844 => x"dfe8",
3845 => x"2f8c",
3846 => x"dfe6",
3847 => x"e180",
3848 => x"91cf",
3849 => x"cfe3",
3850 => x"91cf",
3851 => x"9508",
3852 => x"9abe",
3853 => x"e044",
3854 => x"e450",
3855 => x"e020",
3856 => x"e030",
3857 => x"b388",
3858 => x"2785",
3859 => x"bb88",
3860 => x"01c9",
3861 => x"9701",
3862 => x"f7f1",
3863 => x"5041",
3864 => x"f7c1",
3865 => x"e011",
3866 => x"dfbd",
3867 => x"3380",
3868 => x"f0c9",
3869 => x"3381",
3870 => x"f499",
3871 => x"dfb8",
3872 => x"3280",
3873 => x"f7c1",
3874 => x"e184",
3875 => x"dfc9",
3876 => x"e481",
3877 => x"dfc7",
3878 => x"e586",
3879 => x"dfc5",
3880 => x"e582",
3881 => x"dfc3",
3882 => x"e280",
3883 => x"dfc1",
3884 => x"e489",
3885 => x"dfbf",
3886 => x"e583",
3887 => x"dfbd",
3888 => x"e580",
3889 => x"c0c2",
3890 => x"3480",
3891 => x"f421",
3892 => x"dfa3",
3893 => x"dfa2",
3894 => x"dfbf",
3895 => x"cfe2",
3896 => x"3481",
3897 => x"f469",
3898 => x"df9d",
3899 => x"3880",
3900 => x"f411",
3901 => x"e082",
3902 => x"c029",
3903 => x"3881",
3904 => x"f411",
3905 => x"e081",
3906 => x"c025",
3907 => x"3882",
3908 => x"f511",
3909 => x"e182",
3910 => x"c021",
3911 => x"3482",
3912 => x"f429",
3913 => x"e1c4",
3914 => x"df8d",
3915 => x"50c1",
3916 => x"f7e9",
3917 => x"cfe8",
3918 => x"3485",
3919 => x"f421",
3920 => x"df87",
3921 => x"df86",
3922 => x"df85",
3923 => x"cfe0",
3924 => x"eb90",
3925 => x"0f98",
3926 => x"3093",
3927 => x"f2f0",
3928 => x"3585",
3929 => x"f439",
3930 => x"df7d",
3931 => x"9380",
3932 => x"0063",
3933 => x"df7a",
3934 => x"9380",
3935 => x"0064",
3936 => x"cfd5",
3937 => x"3586",
3938 => x"f439",
3939 => x"df74",
3940 => x"df73",
3941 => x"df72",
3942 => x"df71",
3943 => x"e080",
3944 => x"df95",
3945 => x"cfb0",
3946 => x"3684",
3947 => x"f009",
3948 => x"c039",
3949 => x"df6a",
3950 => x"9380",
3951 => x"0062",
3952 => x"df67",
3953 => x"9380",
3954 => x"0061",
3955 => x"9210",
3956 => x"0060",
3957 => x"df62",
3958 => x"3485",
3959 => x"f419",
3960 => x"9310",
3961 => x"0060",
3962 => x"c00a",
3963 => x"9180",
3964 => x"0063",
3965 => x"9190",
3966 => x"0064",
3967 => x"0f88",
3968 => x"1f99",
3969 => x"9390",
3970 => x"0064",
3971 => x"9380",
3972 => x"0063",
3973 => x"e0c0",
3974 => x"e0d0",
3975 => x"9180",
3976 => x"0061",
3977 => x"9190",
3978 => x"0062",
3979 => x"17c8",
3980 => x"07d9",
3981 => x"f008",
3982 => x"cfa7",
3983 => x"df48",
3984 => x"2f08",
3985 => x"df46",
3986 => x"9190",
3987 => x"0060",
3988 => x"91e0",
3989 => x"0063",
3990 => x"91f0",
3991 => x"0064",
3992 => x"1191",
3993 => x"c005",
3994 => x"921f",
3995 => x"2e00",
3996 => x"2e18",
3997 => x"95e8",
3998 => x"901f",
3999 => x"9632",
4000 => x"93f0",
4001 => x"0064",
4002 => x"93e0",
4003 => x"0063",
4004 => x"9622",
4005 => x"cfe1",
4006 => x"3784",
4007 => x"f009",
4008 => x"c03e",
4009 => x"df2e",
4010 => x"9380",
4011 => x"0062",
4012 => x"df2b",
4013 => x"9380",
4014 => x"0061",
4015 => x"9210",
4016 => x"0060",
4017 => x"df26",
4018 => x"3485",
4019 => x"f419",
4020 => x"9310",
4021 => x"0060",
4022 => x"c00a",
4023 => x"9180",
4024 => x"0063",
4025 => x"9190",
4026 => x"0064",
4027 => x"0f88",
4028 => x"1f99",
4029 => x"9390",
4030 => x"0064",
4031 => x"9380",
4032 => x"0063",
4033 => x"df16",
4034 => x"3280",
4035 => x"f009",
4036 => x"cf55",
4037 => x"e184",
4038 => x"df26",
4039 => x"e0c0",
4040 => x"e0d0",
4041 => x"9180",
4042 => x"0061",
4043 => x"9190",
4044 => x"0062",
4045 => x"17c8",
4046 => x"07d9",
4047 => x"f528",
4048 => x"9180",
4049 => x"0060",
4050 => x"2388",
4051 => x"f011",
4052 => x"e080",
4053 => x"c005",
4054 => x"91e0",
4055 => x"0063",
4056 => x"91f0",
4057 => x"0064",
4058 => x"9184",
4059 => x"df11",
4060 => x"9180",
4061 => x"0063",
4062 => x"9190",
4063 => x"0064",
4064 => x"9601",
4065 => x"9390",
4066 => x"0064",
4067 => x"9380",
4068 => x"0063",
4069 => x"9621",
4070 => x"cfe2",
4071 => x"3785",
4072 => x"f479",
4073 => x"deee",
4074 => x"3280",
4075 => x"f009",
4076 => x"cf2d",
4077 => x"e184",
4078 => x"defe",
4079 => x"e18e",
4080 => x"defc",
4081 => x"e983",
4082 => x"defa",
4083 => x"e08b",
4084 => x"def8",
4085 => x"e180",
4086 => x"def6",
4087 => x"cf22",
4088 => x"3786",
4089 => x"f009",
4090 => x"cf1f",
4091 => x"cf6b",
4092 => x"94f8",
4093 => x"cfff",
others => x"0000"
);
begin
use_rising_edge:
if FALL_EDGE='0' generate
do_rom:
process (clk_i)
begin
if rising_edge(clk_i)then
addr_r <= addr_i;
if we_i='1' then
rom(to_integer(unsigned(addr_i))) <= data_i;
end if;
end if;
end process do_rom;
end generate use_rising_edge;
use_falling_edge:
if FALL_EDGE='1' generate
do_rom:
process (clk_i)
begin
if falling_edge(clk_i)then
addr_r <= addr_i;
if we_i='1' then
rom(to_integer(unsigned(addr_i))) <= data_i;
end if;
end if;
end process do_rom;
end generate use_falling_edge;
data_o <= rom(to_integer(unsigned(addr_r)));
end architecture Xilinx; -- Entity: lattuino_1_blPM_8
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity UART_VHDL is
port (
clock: in std_logic;
reset_N: in std_logic;
address: in std_logic;
writeData: in std_logic_vector(7 downto 0);
write: in std_logic;
readData: out std_logic_vector(7 downto 0);
read: in std_logic;
serialIn: in std_logic;
serialOut: out std_logic
);
end UART_VHDL;
ARCHITECTURE RTL OF UART_VHDL IS
type t_retime is record
once: std_logic;
twice: std_logic;
end record;
type t_TxState is (
IDLE,
START,
SEND,
STOP
);
type t_RxState is (
IDLE,
START,
RECEIVE,
STOP,
FULL,
ERROR
);
constant c_TX: std_logic := '0';
constant c_RX: std_logic := '0';
constant c_STATUS: std_logic := '1';
constant RxReady: integer := 0;
constant RxError: integer := 1;
constant TxReady: integer := 2;
signal s_serialOut: std_logic;
signal s_readData: std_logic_vector(7 downto 0);
begin
--+++++++++++++++++++++++++++
-- +
-- Main clocked logic. +
-- +
--+++++++++++++++++++++++++++
clockedLogic: process (clock, reset_N)
variable RxState: t_RxState;
variable TxState: t_TxState;
variable serialInRetimed: t_retime;
variable Tx,
Rx: std_logic_vector(7 downto 0);
variable RxSampleCount,
RxBitCount,
TxSampleCount,
TxBitCount: integer range 0 to 8;
variable v_serialOut: std_logic;
variable v_readData: std_logic_vector(7 downto 0);
begin
if reset_N = '0' then
s_serialOut <= '1';
RxState := IDLE;
TxState := IDLE;
Tx := (others=>'0');
Rx := (others=>'0');
serialInRetimed := ('1','1');
RxSampleCount := 0;
RxBitCount := 0;
TxSampleCount := 0;
TxBitCount := 0;
elsif clock'event and clock='1' then
--++++++++++++++++++++++++++++++++++++++++++++++++
-- +
-- Assign all temporary variables in order to +
-- avoid generating unwanted flip-flops. +
-- +
--++++++++++++++++++++++++++++++++++++++++++++++++
v_serialOut := s_serialOut;
v_readData := (others=>'0');
--+++++++++++++++++++++++++++++
-- +
-- Read/Write Registers. +
-- +
--+++++++++++++++++++++++++++++
if write = '1' then
case address is
when c_TX => Tx := writeData;
TxState := START;
when others =>
end case;
end if;
if read = '1' then
case address is
when c_RX => v_readData := Rx;
RxState := IDLE;
when c_STATUS => if RxState=FULL then
v_readData(RxReady) := '1';
end if;
if RxState=ERROR then
v_readData(RxError) := '1';
RxState := IDLE;
end if;
if TxState=IDLE then
v_readData(TxReady) := '1';
end if;
when others =>
end case;
end if;
--+++++++++++++++++++++++++++++++
-- +
-- Transmit State Machine. +
-- +
--+++++++++++++++++++++++++++++++
case TxState is
when IDLE =>
when START => v_SerialOut := '0'; -- Start Bit.
TxSampleCount := 0;
TxBitCount := 0;
TxState := SEND;
when SEND => TxSampleCount := TxSampleCount+1; -- Eight Data Bits.
if TxSampleCount = 8 then
TxSampleCount := 0;
v_SerialOut := Tx(TxBitCount);
TxBitCount := TxBitCount+1;
if TxBitCount=8 then
TxState := STOP;
end if;
end if;
when STOP => TxSampleCount := TxSampleCount+1;
if TxSampleCount = 8 then
v_SerialOut := '1'; -- Stop Bit.
TxState := IDLE;
end if;
end case;
--++++++++++++++++++++++++++++++
-- +
-- Receive State Machine. +
-- +
--++++++++++++++++++++++++++++++
case RxState is
when IDLE => if SerialInRetimed.TWICE = '0' then -- Falling Edge of Start Bit.
RxSampleCount := 0;
RxBitCount := 0;
RxState := RECEIVE;
end if;
when START => RxSampleCount := RxSampleCount+1;
if RxSampleCount = 4 then -- Centre of Start Bit
RxState := RECEIVE;
end if;
when RECEIVE => RxSampleCount := RxSampleCount+1; -- Eight Data Bits.
if RxSampleCount = 8 then
RxSampleCount := 0;
Rx(RxBitCount) := serialInRetimed.TWICE;
RxBitCount := RxBitCount+1;
if RxBitCount=8 then
RxState := STOP;
end if;
end if;
when STOP => RxSampleCount := RxSampleCount+1;
if RxSampleCount = 8 then
if serialInRetimed.TWICE = '1' then -- Check Stop Bit
RxState := FULL;
else
RxState := ERROR;
end if;
end if;
when FULL =>
when ERROR =>
end case;
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +
-- Re-time any asynchronous signals before use in order +
-- to avoid race hazards or problems of metastability +
-- +
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
serialInRetimed.TWICE := serialInRetimed.ONCE;
serialInRetimed.ONCE := serialIn;
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +
-- Assign the temporary variables to their `real' counterparts. +
-- +
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
s_serialOut <= v_serialOut;
s_readData <= v_readData;
end if;
end process clockedLogic;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +
-- Assign the outputs from their associated internal signals. +
-- +
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
serialOut <= s_serialOut;
readData <= s_readData;
end RTL;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_156 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(32 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end mul_156;
architecture augh of mul_156 is
signal tmp_res : signed(64 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
output <= std_logic_vector(tmp_res(63 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_156 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(32 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end mul_156;
architecture augh of mul_156 is
signal tmp_res : signed(64 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
output <= std_logic_vector(tmp_res(63 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_156 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(32 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end mul_156;
architecture augh of mul_156 is
signal tmp_res : signed(64 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
output <= std_logic_vector(tmp_res(63 downto 0));
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1835.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01835ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int) of small_int;
END c07s01b00x00p08n01i01835ent;
ARCHITECTURE c07s01b00x00p08n01i01835arch OF c07s01b00x00p08n01i01835ent IS
signal s_bus : cmd_bus;
BEGIN
TESTING : PROCESS
BEGIN
s_bus <= (0 => c07s01b00x00p08n01i01835ent, others => 0) after 5 ns;--entity name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01835 - Entity name are not permitted as primaries in an element association expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01835arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1835.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01835ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int) of small_int;
END c07s01b00x00p08n01i01835ent;
ARCHITECTURE c07s01b00x00p08n01i01835arch OF c07s01b00x00p08n01i01835ent IS
signal s_bus : cmd_bus;
BEGIN
TESTING : PROCESS
BEGIN
s_bus <= (0 => c07s01b00x00p08n01i01835ent, others => 0) after 5 ns;--entity name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01835 - Entity name are not permitted as primaries in an element association expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01835arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1835.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01835ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int) of small_int;
END c07s01b00x00p08n01i01835ent;
ARCHITECTURE c07s01b00x00p08n01i01835arch OF c07s01b00x00p08n01i01835ent IS
signal s_bus : cmd_bus;
BEGIN
TESTING : PROCESS
BEGIN
s_bus <= (0 => c07s01b00x00p08n01i01835ent, others => 0) after 5 ns;--entity name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01835 - Entity name are not permitted as primaries in an element association expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01835arch;
|
------------------------------------------------------------------------------
-- Special configuration which disconnects the ParamOutReg modules, so that
-- we can drive the values with VHDL'2008 external names in the Reconf.Module
-- wrapper <app>-wrapreconfmodule.vhd.
------------------------------------------------------------------------------
configuration WrapReconfModule_cfg of ExtADCSimple_tb is
for behavior
for DUT : ExtADCSimple
for WrapReconfModule
for MyReconfigLogic_0 : MyReconfigLogic
for struct
for all : ParamOutReg
use entity work.ParamOutReg(rtl)
port map (
Reset_n_i => '0',
Clk_i => '0',
Enable_i => '0',
ParamWrData_i => (others => '0'),
Param_o => open
);
end for;
end for;
end for;
end for;
end for;
end for;
end WrapReconfModule_cfg;
|
library verilog;
use verilog.vl_types.all;
entity Etapa1_vlg_vec_tst is
end Etapa1_vlg_vec_tst;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file acticv_mul.vhd when simulating
-- the core, acticv_mul. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY acticv_mul IS
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END acticv_mul;
ARCHITECTURE acticv_mul_a OF acticv_mul IS
-- synthesis translate_off
COMPONENT wrapped_acticv_mul
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_acticv_mul USE ENTITY XilinxCoreLib.xbip_dsp48_macro_v2_1(behavioral)
GENERIC MAP (
c_a_width => 16,
c_b_width => 16,
c_c_width => 48,
c_concat_width => 48,
c_constant_1 => 1,
c_d_width => 16,
c_has_a => 1,
c_has_acin => 0,
c_has_acout => 0,
c_has_b => 1,
c_has_bcin => 0,
c_has_bcout => 0,
c_has_c => 0,
c_has_carrycascin => 0,
c_has_carrycascout => 0,
c_has_carryin => 0,
c_has_carryout => 0,
c_has_ce => 1,
c_has_cea => 0,
c_has_ceb => 0,
c_has_cec => 0,
c_has_ceconcat => 0,
c_has_ced => 0,
c_has_cem => 0,
c_has_cep => 0,
c_has_cesel => 0,
c_has_concat => 0,
c_has_d => 1,
c_has_indep_ce => 0,
c_has_indep_sclr => 0,
c_has_pcin => 0,
c_has_pcout => 0,
c_has_sclr => 0,
c_has_sclra => 0,
c_has_sclrb => 0,
c_has_sclrc => 0,
c_has_sclrconcat => 0,
c_has_sclrd => 0,
c_has_sclrm => 0,
c_has_sclrp => 0,
c_has_sclrsel => 0,
c_latency => 128,
c_model_type => 0,
c_opmodes => "0000000001010001000",
c_p_lsb => 0,
c_p_msb => 31,
c_reg_config => "00000000000010010011000000000000",
c_sel_width => 0,
c_test_core => 0,
c_verbosity => 0,
c_xdevicefamily => "artix7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_acticv_mul
PORT MAP (
clk => clk,
ce => ce,
a => a,
b => b,
d => d,
p => p
);
-- synthesis translate_on
END acticv_mul_a;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Instr_decoder is
Port ( instruction : in STD_LOGIC_VECTOR (31 downto 0);
index : out STD_LOGIC_VECTOR (5 downto 0)
);
end Instr_decoder;
architecture Behavioral of Instr_decoder is
--OP_SPECIAL, "100000", ADD
--OP_NORMAL , "001000", ADDI
--OP_NORMAL , "001001", ADDIU
--OP_SPECIAL, "100001", ADDU
--OP_SPECIAL, "100100", AND
--OP_NORMAL , "001100", ANDI
--OP_NORMAL , "000100", BEQ
--OP_REGIMM , "000001", BGEZ
--OP_REGIMM , "010001", BGEZAL
--OP_NORMAL , "000111", BGTZ
--OP_NORMAL , "000110", BLEZ
--OP_REGIMM , "000000", BLTZ
--OP_REGIMM , "010000", BLTZAL
--OP_NORMAL , "000101", BNE
--OP_SPECIAL, "001101", BREAK
--OP_COP0 , "000001", COP0
--OP_NORMAL , "000010", J
--OP_NORMAL , "000011", JAL
--OP_SPECIAL, "001001", JALR
--OP_SPECIAL, "001000", JR
--OP_NORMAL , "001111", LUI
--OP_NORMAL , "100011", LW
--OP_NORMAL , "110000", LWC0
--OP_COP0 , "000000", MFC0
--OP_SPECIAL, "010000", MFHI
--OP_SPECIAL, "010010", MFLO
--OP_COP0 , "000100", MTC0
--OP_SPECIAL, "010001", MTHI
--OP_SPECIAL, "010011", MTLO
--OP_SPECIAL, "011000", MULT
--OP_SPECIAL, "011001", MULT
--OP_SPECIAL, "100111", NOR
--OP_SPECIAL, "100101", OR
--OP_NORMAL , "001101", ORI
--OP_SPECIAL, "000000", SLL
--OP_SPECIAL, "000100", SLLV
--OP_SPECIAL, "101010", SLT
--OP_NORMAL , "001010", SLTI
--OP_NORMAL , "001011", SLTIU
--OP_SPECIAL, "101011", SLTU
--OP_SPECIAL, "000011", SRA
--OP_SPECIAL, "000111", SRAV
--OP_SPECIAL, "000010", SRL
--OP_SPECIAL, "000110", SRLV
--OP_SPECIAL, "100010", SUB
--OP_SPECIAL, "100011", SUBU
--OP_NORMAL , "101011", SW
--OP_NORMAL , "111000", SWC0
--OP_SPECIAL, "001100", SYSC
--OP_SPECIAL, "100110", XOR
--OP_NORMAL , "001110", XORI
begin
process(instruction)
begin
case instruction(31 downto 26) is
when "000000" => --SPECIAL MODE
case instruction(5 downto 0) is
when "000000" => index <= "100010";
when "000010" => index <= "101010";
when "000011" => index <= "101000";
when "000100" => index <= "100011";
when "000110" => index <= "101011";
when "000111" => index <= "101001";
when "001000" => index <= "010011";
when "001001" => index <= "010010";
when "001100" => index <= "110000";
when "001101" => index <= "001110";
when "010000" => index <= "011000";
when "010001" => index <= "011011";
when "010010" => index <= "011001";
when "010011" => index <= "011100";
when "011000" => index <= "011101";
when "011001" => index <= "011110";
when "100000" => index <= "000000";
when "100001" => index <= "000011";
when "100010" => index <= "101100";
when "100011" => index <= "101101";
when "100100" => index <= "000100";
when "100101" => index <= "100000";
when "100110" => index <= "110001";
when "100111" => index <= "011111";
when "101010" => index <= "100100";
when "101011" => index <= "100111";
when others => index <= "111111";
end case;
-- op_code <= instruction(5 downto 0);
when "000001" => --REGIMM MODE
case '0' & instruction(20 downto 16) is
when "000000" => index <= "100010";
when "000001" => index <= "101010";
when "010000" => index <= "101000";
when "010001" => index <= "100011";
when others => index <= "111111";
end case;
-- op_code <= '0' & instruction(20 downto 16);
when "010000" => --COP0 MODE
case '0' & instruction(25 downto 21) is
when "000000" => index <= "010111";
when "000001" => index <= "001111";
when "000100" => index <= "011010";
when others => index <= "111111";
end case;
-- op_code <= '0' & instruction(25 downto 21);
when others => --NORMAL MODE
case instruction(31 downto 26)is
when "000010" => index <= "010000";
when "000011" => index <= "010001";
when "000100" => index <= "000110";
when "000101" => index <= "001101";
when "000110" => index <= "001010";
when "000111" => index <= "001001";
when "001000" => index <= "000001";
when "001001" => index <= "000010";
when "001010" => index <= "100101";
when "001011" => index <= "100110";
when "001100" => index <= "000101";
when "001101" => index <= "100001";
when "001110" => index <= "110010";
when "001111" => index <= "010100";
when "100011" => index <= "010101";
when "101011" => index <= "101110";
when "110000" => index <= "010110";
when "111000" => index <= "101111";
when others => index <= "111111";
end case;
-- op_code <= instruction(31 downto 26);
end case;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.ceil;
use ieee.math_real.log2;
use work.sampling.all;
entity sampling_network is
generic (
num_samplers : integer := 1;
tau : positive := 20
);
port (
clk, reset : in std_ulogic;
clock_tick : out std_ulogic;
systime : out systime_t;
state : out state_array_t(1 to num_samplers);
membranes : out membrane_array_t(1 to num_samplers);
fires : out std_ulogic_vector(1 to num_samplers);
seeds : in lfsr_state_array_t(1 to num_samplers);
biases : in weight_array_t(1 to num_samplers);
weights : in weight_array2_t(1 to num_samplers, 1 to num_samplers)
);
end sampling_network;
architecture rtl of sampling_network is
subtype sum_in_t is
signed(sum_in_size(num_samplers)-1 downto 0);
signal phase : phase_t;
signal do_prop_count : std_ulogic;
signal prop_ctr : integer range 0 to lfsr_width-1;
signal state_i : state_array_t(1 to num_samplers);
signal systime_i : systime_t;
begin
state <= state_i;
systime <= systime_i;
------------------------------------------------------------
gen_samplers: for sampler_i in 1 to num_samplers generate
signal sum_in : sum_in_t;
signal weight_row : weight_array_t(1 to num_samplers);
begin
process ( weights )
begin
for i in 1 to num_samplers loop
weight_row(i) <= weights(sampler_i, i);
end loop;
end process;
summation: entity work.input_sum
generic map (
num_samplers => num_samplers
)
port map (
clk => clk,
reset => reset,
phase => phase,
state => state_i,
weights => weight_row,
sum => sum_in
);
sampler: entity work.sampler(rtl)
generic map (
num_samplers => num_samplers,
lfsr_polynomial => lfsr_polynomial,
tau => tau
)
port map (
clk => clk,
reset => reset,
phase => phase,
bias => biases(sampler_i),
sum_in => sum_in,
state => state_i(sampler_i),
membrane => membranes(sampler_i),
fire => fires(sampler_i),
seed => seeds(sampler_i)
);
end generate gen_samplers;
------------------------------------------------------------
------------------------------------------------------------
count_propagation: process ( clk, reset )
begin
if reset = '1' then
prop_ctr <= 0;
elsif rising_edge(clk) then
if do_prop_count = '1' then
if prop_ctr < lfsr_width-1 then
prop_ctr <= prop_ctr + 1;
else
prop_ctr <= 0;
end if;
end if;
end if;
end process;
------------------------------------------------------------
------------------------------------------------------------
phase_fsm_transitions: process ( clk, reset )
begin
if reset = '1' then
phase <= idle;
elsif rising_edge(clk) then
case phase is
when idle =>
phase <= propagate;
when propagate =>
if prop_ctr = lfsr_width-2 then
phase <= tick;
end if;
when tick =>
phase <= evaluate;
when evaluate =>
phase <= propagate;
end case;
end if;
end process;
------------------------------------------------------------
------------------------------------------------------------
phase_fsm_output: process (phase)
begin
--default assignments
do_prop_count <= '0';
clock_tick <= '0';
case phase is
when propagate =>
do_prop_count <= '1';
when tick =>
clock_tick <= '1';
when others =>
end case;
end process;
------------------------------------------------------------
------------------------------------------------------------
systime_counter: process ( clk, reset )
begin
if reset = '1' then
systime_i <= to_unsigned(0, systime_i'length);
elsif rising_edge(clk) then
if phase = tick then
systime_i <= systime_i + to_unsigned(1, systime_i'length);
end if;
end if;
end process;
------------------------------------------------------------
end rtl;
|
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY register_generic IS
GENERIC(size: INTEGER);
PORT(d: IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0));
END register_generic;
ARCHITECTURE behave OF register_generic IS
SIGNAL q_int: STD_LOGIC_VECTOR(size-1 DOWNTO 0);
BEGIN
PROCESS(clk)
BEGIN
IF (rising_edge(clk)) THEN
q_int<=d;
END IF;
END PROCESS;
q<=q_int when rst='0' else (others=>'Z'); --asynchronous reset
END behave; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity reg is
port ( d : in bit_vector(7 downto 0);
q : out bit_vector(7 downto 0);
clk : in bit );
end entity reg;
--------------------------------------------------
-- not in book
entity microprocessor is
end entity microprocessor;
-- end not in book
architecture RTL of microprocessor is
signal interrupt_req : bit;
signal interrupt_level : bit_vector(2 downto 0);
signal carry_flag, negative_flag, overflow_flag, zero_flag : bit;
signal program_status : bit_vector(7 downto 0);
signal clk_PSR : bit;
-- . . .
begin
PSR : entity work.reg
port map ( d(7) => interrupt_req,
d(6 downto 4) => interrupt_level,
d(3) => carry_flag, d(2) => negative_flag,
d(1) => overflow_flag, d(0) => zero_flag,
q => program_status,
clk => clk_PSR );
-- . . .
end architecture RTL;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity reg is
port ( d : in bit_vector(7 downto 0);
q : out bit_vector(7 downto 0);
clk : in bit );
end entity reg;
--------------------------------------------------
-- not in book
entity microprocessor is
end entity microprocessor;
-- end not in book
architecture RTL of microprocessor is
signal interrupt_req : bit;
signal interrupt_level : bit_vector(2 downto 0);
signal carry_flag, negative_flag, overflow_flag, zero_flag : bit;
signal program_status : bit_vector(7 downto 0);
signal clk_PSR : bit;
-- . . .
begin
PSR : entity work.reg
port map ( d(7) => interrupt_req,
d(6 downto 4) => interrupt_level,
d(3) => carry_flag, d(2) => negative_flag,
d(1) => overflow_flag, d(0) => zero_flag,
q => program_status,
clk => clk_PSR );
-- . . .
end architecture RTL;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity reg is
port ( d : in bit_vector(7 downto 0);
q : out bit_vector(7 downto 0);
clk : in bit );
end entity reg;
--------------------------------------------------
-- not in book
entity microprocessor is
end entity microprocessor;
-- end not in book
architecture RTL of microprocessor is
signal interrupt_req : bit;
signal interrupt_level : bit_vector(2 downto 0);
signal carry_flag, negative_flag, overflow_flag, zero_flag : bit;
signal program_status : bit_vector(7 downto 0);
signal clk_PSR : bit;
-- . . .
begin
PSR : entity work.reg
port map ( d(7) => interrupt_req,
d(6 downto 4) => interrupt_level,
d(3) => carry_flag, d(2) => negative_flag,
d(1) => overflow_flag, d(0) => zero_flag,
q => program_status,
clk => clk_PSR );
-- . . .
end architecture RTL;
|
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
entity substractor is
generic (k : integer := 4);
port( carryin : in std_logic ;
A, B : in std_logic_vector (k-1 downto 0);
S : out std_logic_vector (k-1 downto 0);
carryout : out std_logic);
end entity substractor;
architecture Behave of substractor is
signal Sum : std_logic_vector (k downto 0);
begin
Sum <= ( '0' & A) - ( '0' & B) - carryin ;
S <= Sum (k-1 downto 0);
carryout <= Sum(k) ;
end Behave;
|
-- fichier : adder.vhd : vhdl structurelle pour un additionneur
library ieee;
use ieee.std_logic_1164.all;
-- déclaration de l'entité de l'additionneur:
entity adder is
port (
augend, addend, carry_in : in std_logic;
sum, carry_out : out std_logic
);
end adder;
-- architecture style structurelle de l'adder:
architecture adder_impl of adder is
-- déclaration des composants
component exclusive_or_gate
port(
x, y : in std_logic;
z : out std_logic
);
end component;
component and_gate
port(
x, y : in std_logic;
z : out std_logic
);
end component;
component or_gate
port(
x, y : in std_logic;
z : out std_logic
);
end component;
-- instantiation
-- signaux internes
signal s1, s2, s3: std_logic;
begin
xor_1: exclusive_or_gate port map( augend, addend, s1 );
xor_2: exclusive_or_gate port map( s1, carry_in, sum );
and_1: and_gate port map( augend, addend, s3 );
and_2: and_gate port map( s1, carry_in, s2 );
or_1 : or_gate port map( s2, s3, carry_out );
end adder_impl; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity address_decoder is
port ( addr : in work.cpu_types.address;
status : in work.cpu_types.status_value;
mem_sel, int_sel, io_sel : out bit );
end entity address_decoder;
--------------------------------------------------
architecture functional of address_decoder is
constant mem_low : work.cpu_types.address := X"000000";
constant mem_high : work.cpu_types.address := X"EFFFFF";
constant io_low : work.cpu_types.address := X"F00000";
constant io_high : work.cpu_types.address := X"FFFFFF";
begin
mem_decoder :
mem_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.fetch)
or work.cpu_types."="(status, work.cpu_types.mem_read)
or work.cpu_types."="(status, work.cpu_types.mem_write) )
and addr >= mem_low
and addr <= mem_high else
'0';
int_decoder :
int_sel <= '1' when work.cpu_types."="(status, work.cpu_types.int_ack) else
'0';
io_decoder :
io_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.io_read)
or work.cpu_types."="(status, work.cpu_types.io_write) )
and addr >= io_low
and addr <= io_high else
'0';
end architecture functional;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity address_decoder is
port ( addr : in work.cpu_types.address;
status : in work.cpu_types.status_value;
mem_sel, int_sel, io_sel : out bit );
end entity address_decoder;
--------------------------------------------------
architecture functional of address_decoder is
constant mem_low : work.cpu_types.address := X"000000";
constant mem_high : work.cpu_types.address := X"EFFFFF";
constant io_low : work.cpu_types.address := X"F00000";
constant io_high : work.cpu_types.address := X"FFFFFF";
begin
mem_decoder :
mem_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.fetch)
or work.cpu_types."="(status, work.cpu_types.mem_read)
or work.cpu_types."="(status, work.cpu_types.mem_write) )
and addr >= mem_low
and addr <= mem_high else
'0';
int_decoder :
int_sel <= '1' when work.cpu_types."="(status, work.cpu_types.int_ack) else
'0';
io_decoder :
io_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.io_read)
or work.cpu_types."="(status, work.cpu_types.io_write) )
and addr >= io_low
and addr <= io_high else
'0';
end architecture functional;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity address_decoder is
port ( addr : in work.cpu_types.address;
status : in work.cpu_types.status_value;
mem_sel, int_sel, io_sel : out bit );
end entity address_decoder;
--------------------------------------------------
architecture functional of address_decoder is
constant mem_low : work.cpu_types.address := X"000000";
constant mem_high : work.cpu_types.address := X"EFFFFF";
constant io_low : work.cpu_types.address := X"F00000";
constant io_high : work.cpu_types.address := X"FFFFFF";
begin
mem_decoder :
mem_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.fetch)
or work.cpu_types."="(status, work.cpu_types.mem_read)
or work.cpu_types."="(status, work.cpu_types.mem_write) )
and addr >= mem_low
and addr <= mem_high else
'0';
int_decoder :
int_sel <= '1' when work.cpu_types."="(status, work.cpu_types.int_ack) else
'0';
io_decoder :
io_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.io_read)
or work.cpu_types."="(status, work.cpu_types.io_write) )
and addr >= io_low
and addr <= io_high else
'0';
end architecture functional;
|
architecture RTL of ENT is
begin
-- Align left = no align paren = no
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_foo <=
resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_bar <= a or b and c
xor z and x or
w and z;
n_bar <=
a or b and c
xor z and x or
w and z;
-- Align left = no align paren = yes
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_foo <=
resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_bar <= a or b and c
xor z and x or
w and z;
n_bar <=
a or b and c
xor z and x or
w and z;
-- Align left = yes and align paren = no
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_foo <=
resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_bar <= a or b and c
xor z and x or
w and z;
n_bar <=
a or b and c
xor z and x or
w and z;
-- Align left = yes and align paren = yes
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_foo <=
resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_bar <= a or b and c
xor z and x or
w and z;
n_bar <=
a or b and c
xor z and x or
w and z;
end architecture RTL;
|
-- Copyright (C) 2016 Siavoosh Payandeh, Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_pseudo is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
N1_out, E1_out, W1_out, S1_out: out std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: out std_logic
);
end LBDR_pseudo;
architecture behavior of LBDR_pseudo is
signal Cx: std_logic_vector(3 downto 0);
signal Rxy: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1: std_logic;
begin
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
-- Taking X1 signals to the output interface for checking with checkers
N1_out <= N1;
E1_out <= E1;
W1_out <= W1;
S1_out <= S1;
-- The combionational part
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF) begin
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
Req_L_in <= not N1 and not E1 and not W1 and not S1;
elsif flit_type = "100" then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else -- Body flit
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
end process;
END; |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: BINARYZACJA_tb_agen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY BINARYZACJA_TB_AGEN IS
GENERIC (
C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END BINARYZACJA_TB_AGEN;
ARCHITECTURE BEHAVIORAL OF BINARYZACJA_TB_AGEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: BINARYZACJA_tb_agen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY BINARYZACJA_TB_AGEN IS
GENERIC (
C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END BINARYZACJA_TB_AGEN;
ARCHITECTURE BEHAVIORAL OF BINARYZACJA_TB_AGEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: BINARYZACJA_tb_agen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY BINARYZACJA_TB_AGEN IS
GENERIC (
C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END BINARYZACJA_TB_AGEN;
ARCHITECTURE BEHAVIORAL OF BINARYZACJA_TB_AGEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: BINARYZACJA_tb_agen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY BINARYZACJA_TB_AGEN IS
GENERIC (
C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END BINARYZACJA_TB_AGEN;
ARCHITECTURE BEHAVIORAL OF BINARYZACJA_TB_AGEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CHK_3BIT IS
PORT(DIN:IN STD_LOGIC;
CLK,RESET:IN STD_LOGIC;
BIT3:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
DOUT:OUT STD_LOGIC);
END ENTITY CHK_3BIT;
ARCHITECTURE ART1 OF CHK_3BIT IS
TYPE STATETYPE IS(S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15);
SIGNAL PRESENT_STATE,NEXT_STATE:STATETYPE;
SIGNAL CHOSEN_SEQ:STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
BEGIN
CHOOSE:PROCESS(BIT3)
BEGIN
--使用case语句时一定要列举完所有情况(善于应用others)，否则编译通过但仿真通不过
CASE BIT3 IS
WHEN "000"=>CHOSEN_SEQ<="00000001";
WHEN "001"=>CHOSEN_SEQ<="00000010";
WHEN "010"=>CHOSEN_SEQ<="00000100";
WHEN "011"=>CHOSEN_SEQ<="00001000";
WHEN "100"=>CHOSEN_SEQ<="00010000";
WHEN "101"=>CHOSEN_SEQ<="00100000";
WHEN "110"=>CHOSEN_SEQ<="01000000";
WHEN "111"=>CHOSEN_SEQ<="10000000";
WHEN OTHERS =>CHOSEN_SEQ<="00000000";
END CASE;
END PROCESS;
COMB:PROCESS(PRESENT_STATE,DIN,CHOSEN_SEQ)
BEGIN
CASE PRESENT_STATE IS
WHEN S1=>DOUT<='0';
IF DIN='0'THEN
NEXT_STATE<=S2;
ELSE
NEXT_STATE<=S3;
END IF;
WHEN S2=>DOUT<='0';
IF DIN='0'THEN
NEXT_STATE<=S4;
ELSE
NEXT_STATE<=S5;
END IF;
WHEN S3=>DOUT<='0';
IF DIN='0'THEN
NEXT_STATE<=S6;
ELSE
NEXT_STATE<=S7;
END IF;
WHEN S4=>DOUT<='0';
IF DIN='0'THEN
NEXT_STATE<=S8;
ELSE
NEXT_STATE<=S9;
END IF;
WHEN S5=>DOUT<='0';
IF DIN='0'THEN
NEXT_STATE<=S10;
ELSE
NEXT_STATE<=S11;
END IF;
WHEN S6=>DOUT<='0';
IF DIN='0'THEN
NEXT_STATE<=S12;
ELSE
NEXT_STATE<=S13;
END IF;
WHEN S7=>DOUT<='0';
IF DIN='0'THEN
NEXT_STATE<=S14;
ELSE
NEXT_STATE<=S15;
END IF;
WHEN S8=>DOUT<=CHOSEN_SEQ(0);
IF DIN='0'THEN
NEXT_STATE<=S8;
ELSE
NEXT_STATE<=S9;
END IF;
WHEN S9=>DOUT<=CHOSEN_SEQ(1);
IF DIN='0'THEN
NEXT_STATE<=S10;
ELSE
NEXT_STATE<=S11;
END IF;
WHEN S10=>DOUT<=CHOSEN_SEQ(2);
IF DIN='0'THEN
NEXT_STATE<=S12;
ELSE
NEXT_STATE<=S13;
END IF;
WHEN S11=>DOUT<=CHOSEN_SEQ(3);
IF DIN='0'THEN
NEXT_STATE<=S14;
ELSE
NEXT_STATE<=S15;
END IF;
WHEN S12=>DOUT<=CHOSEN_SEQ(4);
IF DIN='0'THEN
NEXT_STATE<=S8;
ELSE
NEXT_STATE<=S9;
END IF;
WHEN S13=>DOUT<=CHOSEN_SEQ(5);
IF DIN='0'THEN
NEXT_STATE<=S10;
ELSE
NEXT_STATE<=S11;
END IF;
WHEN S14=>DOUT<=CHOSEN_SEQ(6);
IF DIN='0'THEN
NEXT_STATE<=S12;
ELSE
NEXT_STATE<=S13;
END IF;
WHEN S15=>DOUT<=CHOSEN_SEQ(7);
IF DIN='0'THEN
NEXT_STATE<=S14;
ELSE
NEXT_STATE<=S15;
END IF;
END CASE;
END PROCESS;
CLOCK:PROCESS(CLK,RESET)
BEGIN
IF(RESET='1')THEN
PRESENT_STATE<=S1;
ELSIF(CLK'EVENT AND CLK='1')THEN
PRESENT_STATE<=NEXT_STATE;
END IF;
END PROCESS;
END ARCHITECTURE ART1;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 09:37:58 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_vga_sync_0_0 -prefix
-- system_vga_sync_0_0_ system_vga_sync_0_0_stub.vhdl
-- Design : system_vga_sync_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_sync_0_0 is
Port (
clk_25 : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end system_vga_sync_0_0;
architecture stub of system_vga_sync_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_25,rst,active,hsync,vsync,xaddr[9:0],yaddr[9:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_sync,Vivado 2016.4";
begin
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity TT is port(
T : in std_logic;
C : in std_logic;
Q : out std_logic
);
end TT;
architecture behavior of TT is
signal S : std_logic := '0';
begin
Main : process (T, C, S)
begin
if rising_edge(C) then
S <= T xor S;
end if;
end process;
Q <= S;
end behavior;
|
-------------------------------------------------------------------------------
--! @file dynamicBridgeRtl.vhd
--
--! @brief Dynamic Bridge for translating static to dynamic memory spaces
--
--! @details The Dynamic Bridge component translates a static memory mapping
--! into a dynamic memory map that can be changed during runtime.
--! This enhances the functionality of an ordinary memory mapped bridge logic.
--! Additionally several memory spaces can be configured (compilation).
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! need reduce or operation
use ieee.std_logic_misc.OR_REDUCE;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
-------------------------------------------------------------------------------
--! @brief Dynamic bridge translates a fixed address space into a flexible one.
-------------------------------------------------------------------------------
--! @details
--! The dynamic bridge has an input port with a fixed (before runtime) memory
--! mapping, which is translated to a flexible address space mapping.
--! The flexible address space can be changed during runtime in order to
--! redirect accesses from the input to other locations.
--! The base addresses for the static port are set by generic gBaseAddressArray.
--! The base addresses for the dynamic port are set through the BaseSet port
-------------------------------------------------------------------------------
entity dynamicBridge is
generic (
--! number of static address spaces
gAddressSpaceCount : natural := 2;
--! select wheather DPRAM or registers will be used as memory (false = 0, true /= 0)
gUseMemBlock : integer := 0;
--! base addresses in static address space (note: last-1 = high address)
gBaseAddressArray : tArrayStd32 := (x"0000_1000" , x"0000_2000" , x"0000_3000")
);
port (
-- Global
--! component-wide clock signal
iClk : in std_logic;
--! component-wide reset signal
iRst : in std_logic;
-- Bridge
--! address of static address space
iBridgeAddress : in std_logic_vector;
--! Request strobe
iBridgeRequest : in std_logic;
--! address of dynamic address space (translated input)
oBridgeAddress : out std_logic_vector;
--! Select signal of any address space selected
oBridgeSelectAny : out std_logic;
--! select signals of all address spaces
oBridgeSelect : out std_logic_vector(gAddressSpaceCount-1 downto 0);
--! Bridge output valid
oBridgeValid : out std_logic;
-- BaseSet Memory Mapped Write Bus
--! BaseSet write strobe
iBaseSetWrite : in std_logic;
--! BaseSet read strobe
iBaseSetRead : in std_logic;
--! BaseSet byteenable
iBaseSetByteenable : in std_logic_vector;
--! BaseSet address bus
iBaseSetAddress : in std_logic_vector(LogDualis(gAddressSpaceCount)-1 downto 0);
--! BaseSet write data bus
iBaseSetData : in std_logic_vector;
--! BaseSet read data bus
oBaseSetData : out std_logic_vector;
--! BaseSet acknowledge
oBaseSetAck : out std_logic
);
end dynamicBridge;
-------------------------------------------------------------------------------
--! @brief Register Transfer Level of Dynamic Bridge device
-------------------------------------------------------------------------------
--! @details
--! The dynamic bridge rtl applies generated address decoders
--! to generate select signals for the static address spaces.
--! The select signals are forwarded register file holding the base address
--! offsets in the dynamic memory space. The input address is manipulated with
--! arithmetic operators to gain the output address. The lut file holds the
--! base addresses in the static memory space.
-------------------------------------------------------------------------------
architecture rtl of dynamicBridge is
--! Bridge cycle delay
constant cBridgeCycleDelay : natural := 3;
--! Bridge read path enable all bytes
constant cByteenableAllOnes : std_logic_vector(iBaseSetByteenable'range) :=
(others => cActivated);
--! convert address array into stream
constant cBaseAddressArrayStd : std_logic_vector
((gAddressSpaceCount+1)*cArrayStd32ElementSize-1 downto 0) :=
CONV_STDLOGICVECTOR(gBaseAddressArray, gBaseAddressArray'length);
--! Input address register
signal inAddrReg : std_logic_vector(iBridgeAddress'range);
--! Request rising edge
signal bridgeRequest_rising : std_logic;
--! Input address store strobe
signal inAddrStore : std_logic;
--! Request acknowledge terminal count strobe
signal reqAckTcnt : std_logic;
--! address decoder select signals one hot coded
signal addrDecSelOneHot : std_logic_vector(gAddressSpaceCount-1 downto 0);
--! address decoder select signals binary coded
signal addrDecSelBinary : std_logic_vector(LogDualis(gAddressSpaceCount)-1 downto 0);
--! selected static lut file base offset
signal lutFileBase : std_logic_vector(inAddrReg'range);
--! Base address in bridge master environment
signal addrSpaceOffset : std_logic_vector(inAddrReg'range);
--! Base address in bridge master environment (unregistered)
signal addrSpaceOffset_unreg : std_logic_vector(inAddrReg'range);
--! Dynamic address offset within selected static space
signal dynamicOffset : std_logic_vector(iBaseSetData'range);
--! Translated address
signal translateAddress : std_logic_vector(maximum(iBaseSetData'high, oBridgeAddress'high) downto inAddrReg'low);
begin
-- assert
assert (cBridgeCycleDelay > 0)
report "Set cBridgeCycleDelay > 0"
severity failure;
-- export
oBridgeSelect <= addrDecSelOneHot;
oBridgeSelectAny <= OR_REDUCE(addrDecSelOneHot);
oBridgeValid <= reqAckTcnt;
oBridgeAddress <= translateAddress(oBridgeAddress'range);
--! Store the input address with the request strobe
storeAddr : process(iRst, iClk)
begin
if iRst = cActivated then
inAddrReg <= (others => cInactivated);
elsif rising_edge(iClk) then
if inAddrStore = cActivated then
inAddrReg <= iBridgeAddress;
end if;
end if;
end process;
--! Get rising edge of request signaling
reqEdge : entity libcommon.edgedetector
port map (
iArst => iRst,
iClk => iClk,
iEnable => cActivated,
iData => iBridgeRequest,
oRising => bridgeRequest_rising,
oFalling => open,
oAny => open
);
inAddrStore <= bridgeRequest_rising;
--! Generate the request acknowledge signal
reqAck : entity libcommon.cnt
generic map (
gCntWidth => logDualis(cBridgeCycleDelay+1),
gTcntVal => cBridgeCycleDelay
)
port map (
iArst => iRst,
iClk => iClk,
iEnable => iBridgeRequest,
iSrst => cInactivated,
oCnt => open,
oTcnt => reqAckTcnt
);
--! Generate Address Decoders
genAddressDecoder : for i in 0 to gAddressSpaceCount-1 generate
insAddressDecoder : entity libcommon.addrDecode
generic map (
gAddrWidth => inAddrReg'length,
gBaseAddr => to_integer(unsigned(gBaseAddressArray(i)(inAddrReg'range))),
gHighAddr => to_integer(unsigned(gBaseAddressArray(i+1)(inAddrReg'range))-1)
)
port map (
iEnable => iBridgeRequest,
iAddress => inAddrReg,
oSelect => addrDecSelOneHot(i)
);
end generate;
--! Convert one hot from address decoder to binary
insBinaryEncoder : entity libcommon.binaryEncoder
generic map (
gDataWidth => gAddressSpaceCount
)
port map (
iOneHot => addrDecSelOneHot,
oBinary => addrDecSelBinary
);
--! select static base address in lut file
insLutFile : entity libcommon.lutFile
generic map (
gLutCount => gAddressSpaceCount,
gLutWidth => cArrayStd32ElementSize,
gLutInitValue => cBaseAddressArrayStd(cBaseAddressArrayStd'left downto cArrayStd32ElementSize)
-- omit high address of last memory map
)
port map (
iAddrRead => addrDecSelBinary,
oData => lutFileBase
);
-- calculate address offset within static space
addrSpaceOffset_unreg <= std_logic_vector(
unsigned(inAddrReg) - unsigned(lutFileBase)
);
--! Registers to break combinational path of lut file output.
regAddrSpace : process(iRst, iClk)
begin
if iRst = cActivated then
addrSpaceOffset <= (others => cInactivated);
elsif rising_edge(iClk) then
addrSpaceOffset <= addrSpaceOffset_unreg;
end if;
end process;
REGFILE : if gUseMemBlock = 0 generate
signal dynamicOffset_unreg : std_logic_vector(dynamicOffset'range);
begin
--! select dynamic base address in register file
insRegFile : entity libcommon.registerFile
generic map (
gRegCount => gAddressSpaceCount
)
port map (
iClk => iClk,
iRst => iRst,
iWriteA => iBaseSetWrite,
iWriteB => cInactivated, -- write port B unused
iByteenableA => iBaseSetByteenable,
iByteenableB => cByteenableAllOnes,
iAddrA => iBaseSetAddress,
iAddrB => addrDecSelBinary,
iWritedataA => iBaseSetData,
oReaddataA => oBaseSetData,
iWritedataB => iBaseSetData, -- write port B unused
oReaddataB => dynamicOffset_unreg
);
regDynOff : process(iRst, iClk)
begin
if iRst = cActivated then
dynamicOffset <= (others => cInactivated);
elsif rising_edge(iClk) then
dynamicOffset <= dynamicOffset_unreg;
end if;
end process;
BASESETACK : oBaseSetAck <= iBaseSetWrite or iBaseSetRead;
end generate REGFILE;
genDPRAM : if gUseMemBlock /= 0 generate
-- Clip dpr word width to values of power 2 (e.g. 8, 16, 32)
constant cDprWordWidth : natural := 2**logDualis(iBaseSetData'length);
constant cDprAddrWidth : natural := logDualis(gAddressSpaceCount);
constant cDprReadDel : natural := 1;
type tDprPort is record
write : std_logic;
read : std_logic;
address : std_logic_vector(cDprAddrWidth-1 downto 0);
byteenable : std_logic_vector(cDprWordWidth/8-1 downto 0);
writedata : std_logic_vector(cDprWordWidth-1 downto 0);
readdata : std_logic_vector(cDprWordWidth-1 downto 0);
end record;
signal dprPortA : tDprPort;
signal dprPortA_readAck : std_logic;
signal dprPortB : tDprPort;
begin
--! This combinatoric process assigns base sets to the dpr.
--! The default assignments avoid warnings in synthesize tools.
dprAssign : process (
iBaseSetByteenable,
iBaseSetData
)
begin
--default assignments
dprPortA.byteenable <= (others => cInactivated);
dprPortA.writedata <= (others => cInactivated);
dprPortB.byteenable <= (others => cInactivated);
dprPortB.writedata <= (others => cInactivated);
dprPortA.byteenable(iBaseSetByteenable'range) <= iBaseSetByteenable;
dprPortA.writedata(iBaseSetData'range) <= iBaseSetData;
dprPortB.byteenable <= (others => cInactivated);
dprPortB.writedata(iBaseSetData'range) <= iBaseSetData;
end process;
dprPortA.write <= iBaseSetWrite;
dprPortA.read <= iBaseSetRead;
dprPortA.address <= iBaseSetAddress;
oBaseSetData <= dprPortA.readdata(oBaseSetData'range);
dprPortB.write <= cInactivated; --unused
dprPortB.read <= cActivated; --unused
dprPortB.address <= addrDecSelBinary;
dynamicOffset <= dprPortB.readdata(dynamicOffset'range);
insDPRAM: entity work.dpRam
generic map(
gWordWidth => cDprWordWidth,
gNumberOfWords => gAddressSpaceCount
)
port map(
iClk_A => iClk,
iEnable_A => cActivated,
iWriteEnable_A => dprPortA.write,
iAddress_A => dprPortA.address,
iByteEnable_A => dprPortA.byteenable,
iWritedata_A => dprPortA.writedata,
oReaddata_A => dprPortA.readdata,
iClk_B => iClk,
iEnable_B => cActivated,
iWriteEnable_B => dprPortB.write,
iAddress_B => dprPortB.address,
iByteEnable_B => dprPortB.byteenable,
iWritedata_B => dprPortB.writedata,
oReaddata_B => dprPortB.readdata
);
BASESETACK : oBaseSetAck <= dprPortA.write or dprPortA_readAck;
--! Generate the read acknowledge signal
rdAck : entity libcommon.cnt
generic map (
gCntWidth => logDualis(cDprReadDel+1),
gTcntVal => cDprReadDel
)
port map (
iArst => iRst,
iClk => iClk,
iEnable => dprPortA.read,
iSrst => cInactivated,
oCnt => open,
oTcnt => dprPortA_readAck
);
end generate genDPRAM;
-- calculate translated address offset in dynamic space
translateAddress <= std_logic_vector(
unsigned(dynamicOffset) + unsigned(addrSpaceOffset)
);
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: uart
-- File: uart.vhd
-- Authors: Jiri Gaisler - Gaisler Research
-- Marko Isomaki - Gaisler Research
-- Description: Asynchronous UART. Implements 8-bit data frame with one stop-bit.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity apbuart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
parity : integer := 1;
flow : integer := 1;
fifosize : integer range 1 to 32 := 1;
abits : integer := 8;
sbits : integer range 12 to 32 := 12);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in uart_in_type;
uarto : out uart_out_type);
end;
architecture rtl of apbuart is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBUART, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type rxfsmtype is (idle, startbit, data, cparity, stopbit);
type txfsmtype is (idle, data, cparity);
type fifo is array (0 to fifosize - 1) of std_logic_vector(7 downto 0);
type uartregs is record
rxen : std_ulogic; -- receiver enabled
txen : std_ulogic; -- transmitter enabled
rirqen : std_ulogic; -- receiver irq enable
tirqen : std_ulogic; -- transmitter irq enable
parsel : std_ulogic; -- parity select
paren : std_ulogic; -- parity select
flow : std_ulogic; -- flow control enable
loopb : std_ulogic; -- loop back mode enable
debug : std_ulogic; -- debug mode enable
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
tsemptyirqen : std_ulogic; -- generate irq when tx shift register is empty
break : std_ulogic; -- break detected
breakirqen : std_ulogic; -- generate irq when break has been received
ovf : std_ulogic; -- receiver overflow
parerr : std_ulogic; -- parity error
frame : std_ulogic; -- framing error
ctsn : std_logic_vector(1 downto 0); -- clear to send
rtsn : std_ulogic; -- request to send
extclken : std_ulogic; -- use external baud rate clock
extclk : std_ulogic; -- rising edge detect register
rhold : fifo;
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(9 downto 0);
thold : fifo;
irq : std_ulogic; -- tx/rx interrupt (internal)
irqpend : std_ulogic; -- pending irq for delayed rx irq
delayirqen : std_ulogic; -- enable delayed rx irq
tpar : std_ulogic; -- tx data parity (internal)
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_ulogic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_logic_vector(1 downto 0); -- rx delay
dpar : std_ulogic; -- rx data parity (internal)
rxtick : std_ulogic; -- rx clock (internal)
tick : std_ulogic; -- rx clock (internal)
scaler : std_logic_vector(sbits-1 downto 0);
brate : std_logic_vector(sbits-1 downto 0);
rxf : std_logic_vector(4 downto 0); -- rx data filtering buffer
txd : std_ulogic; -- transmitter data
rfifoirqen : std_ulogic; -- receiver fifo interrupt enable
tfifoirqen : std_ulogic; -- transmitter fifo interrupt enable
irqcnt : std_logic_vector(5 downto 0); -- delay counter for rx irq
--fifo counters
rwaddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
rraddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
traddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
twaddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
rcnt : std_logic_vector(log2x(fifosize) downto 0);
tcnt : std_logic_vector(log2x(fifosize) downto 0);
end record;
constant rcntzero : std_logic_vector(log2x(fifosize) downto 0) := (others => '0');
constant addrzero : std_logic_vector(log2x(fifosize)-1 downto 0) := (others => '0');
constant sbitszero : std_logic_vector(sbits-1 downto 0) := (others => '0');
constant fifozero : fifo := (others => (others => '0'));
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : uartregs :=
(rxen => '0', txen => '0', rirqen => '0', tirqen => '0', parsel => '0',
paren => '0', flow => '0', loopb => '0', debug => '0', rsempty => '1',
tsempty => '1', tsemptyirqen => '0', break => '0', breakirqen => '0',
ovf => '0', parerr => '0', frame => '0', ctsn => (others => '0'),
rtsn => '1', extclken => '0', extclk => '0', rhold => fifozero,
rshift => (others => '0'), tshift => (others => '1'), thold => fifozero,
irq => '0', irqpend => '0', delayirqen => '0', tpar => '0', txstate => idle,
txclk => (others => '0'), txtick => '0', rxstate => idle,
rxclk => (others => '0'), rxdb => (others => '0'), dpar => '0',rxtick => '0',
tick => '0', scaler => sbitszero, brate => sbitszero, rxf => (others => '0'),
txd => '1', rfifoirqen => '0', tfifoirqen => '0', irqcnt => (others => '0'),
rwaddr => addrzero, rraddr => addrzero, traddr => addrzero, twaddr => addrzero,
rcnt => rcntzero, tcnt => rcntzero);
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(sbits-1 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable rxd, ctsn : std_ulogic;
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable paddress : std_logic_vector(7 downto 2);
variable v : uartregs;
variable thalffull : std_ulogic;
variable rhalffull : std_ulogic;
variable rfull : std_ulogic;
variable tfull : std_ulogic;
variable dready : std_ulogic;
variable thempty : std_ulogic;
--pragma translate_off
variable L1 : line;
variable CH : character;
variable FIRST : boolean := true;
variable pt : time := 0 ns;
--pragma translate_on
begin
v := r; irq := (others => '0'); irq(pirq) := r.irq;
v.irq := '0'; v.txtick := '0'; v.rxtick := '0'; v.tick := '0';
rdata := (others => '0'); v.rxdb(1) := r.rxdb(0);
dready := '0'; thempty := '1'; thalffull := '1'; rhalffull := '0';
v.ctsn := r.ctsn(0) & uarti.ctsn;
paddress := (others => '0');
paddress(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
if fifosize = 1 then
dready := r.rcnt(0); rfull := dready; tfull := r.tcnt(0);
thempty := not tfull;
else
tfull := r.tcnt(log2x(fifosize)); rfull := r.rcnt(log2x(fifosize));
if (r.rcnt(log2x(fifosize)) or r.rcnt(log2x(fifosize) - 1)) = '1' then
rhalffull := '1';
end if;
if ((r.tcnt(log2x(fifosize)) or r.tcnt(log2x(fifosize) - 1))) = '1' then
thalffull := '0';
end if;
if r.rcnt /= rcntzero then dready := '1'; end if;
if r.tcnt /= rcntzero then thempty := '0'; end if;
end if;
-- scaler
scaler := r.scaler - 1;
if (r.rxen or r.txen) = '1' then
v.scaler := scaler;
v.tick := scaler(sbits-1) and not r.scaler(sbits-1);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- optional external uart clock
v.extclk := uarti.extclk;
if r.extclken = '1' then v.tick := r.extclk and not uarti.extclk; end if;
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddress(7 downto 2) is
when "000000" =>
rdata(7 downto 0) := r.rhold(conv_integer(r.rraddr));
if fifosize = 1 then v.rcnt(0) := '0';
else
if r.rcnt /= rcntzero then
v.rraddr := r.rraddr + 1; v.rcnt := r.rcnt - 1;
end if;
end if;
when "000001" =>
if fifosize /= 1 then
rdata (26 + log2x(fifosize) downto 26) := r.rcnt;
rdata (20 + log2x(fifosize) downto 20) := r.tcnt;
rdata (10 downto 7) := rfull & tfull & rhalffull & thalffull;
end if;
rdata(6 downto 0) := r.frame & r.parerr & r.ovf &
r.break & thempty & r.tsempty & dready;
--pragma translate_off
if CONSOLE = 1 then rdata(2 downto 1) := "11"; end if;
--pragma translate_on
when "000010" =>
if fifosize > 1 then
rdata(31) := '1';
end if;
rdata(14) := r.tsemptyirqen;
rdata(13) := r.delayirqen;
rdata(12) := r.breakirqen;
rdata(11) := r.debug;
if fifosize /= 1 then
rdata(10 downto 9) := r.rfifoirqen & r.tfifoirqen;
end if;
rdata(8 downto 0) := r.extclken & r.loopb &
r.flow & r.paren & r.parsel & r.tirqen & r.rirqen & r.txen & r.rxen;
when "000011" =>
rdata(sbits-1 downto 0) := r.brate;
when "000100" =>
-- Read TX FIFO.
if r.debug = '1' and r.tcnt /= rcntzero then
rdata(7 downto 0) := r.thold(conv_integer(r.traddr));
if fifosize = 1 then
v.tcnt(0) := '0';
else
v.traddr := r.traddr + 1;
v.tcnt := r.tcnt - 1;
end if;
end if;
when others =>
null;
end case;
end if;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddress(7 downto 2) is
when "000000" =>
when "000001" =>
v.frame := apbi.pwdata(6);
v.parerr := apbi.pwdata(5);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "000010" =>
v.tsemptyirqen := apbi.pwdata(14);
v.delayirqen := apbi.pwdata(13);
v.breakirqen := apbi.pwdata(12);
v.debug := apbi.pwdata(11);
if fifosize /= 1 then
v.rfifoirqen := apbi.pwdata(10);
v.tfifoirqen := apbi.pwdata(9);
end if;
v.extclken := apbi.pwdata(8);
v.loopb := apbi.pwdata(7);
v.flow := apbi.pwdata(6);
v.paren := apbi.pwdata(5);
v.parsel := apbi.pwdata(4);
v.tirqen := apbi.pwdata(3);
v.rirqen := apbi.pwdata(2);
v.txen := apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "000011" =>
v.brate := apbi.pwdata(sbits-1 downto 0);
v.scaler := apbi.pwdata(sbits-1 downto 0);
when "000100" =>
-- Write RX fifo and generate irq
if flow /= 0 then
v.rhold(conv_integer(r.rwaddr)) := apbi.pwdata(7 downto 0);
if fifosize = 1 then v.rcnt(0) := '1';
else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if;
if r.debug = '1' then
v.irq := v.irq or r.rirqen;
end if;
end if;
when others =>
null;
end case;
end if;
-- tx clock
txclk := r.txclk + 1;
if r.tick = '1' then
v.txclk := txclk;
v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
rxclk := r.rxclk + 1;
if r.tick = '1' then
v.rxclk := rxclk;
v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
if (r.rxtick and r.delayirqen) = '1' then
v.irqcnt := v.irqcnt + 1;
end if;
if r.irqcnt(5 downto 4) = "11" then
v.irq := v.irq or (r.delayirqen and r.irqpend); -- make sure no tx irqs are lost !
v.irqpend := '0';
end if;
-- filter rx data
-- v.rxf := r.rxf(6 downto 0) & uarti.rxd;
-- if ((r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) &
-- r.rxf(7)) = r.rxf(6 downto 0))
-- then v.rxdb(0) := r.rxf(7); end if;
v.rxf(1 downto 0) := r.rxf(0) & uarti.rxd; -- meta-stability filter
if r.tick = '1' then
v.rxf(4 downto 2) := r.rxf(3 downto 1);
end if;
v.rxdb(0) := (r.rxf(4) and r.rxf(3)) or (r.rxf(4) and r.rxf(2)) or
(r.rxf(3) and r.rxf(2));
-- loop-back mode
if r.loopb = '1' then
v.rxdb(0) := r.tshift(0); ctsn := dready and not r.rsempty;
elsif (flow = 1) then ctsn := r.ctsn(1); else ctsn := '0'; end if;
rxd := r.rxdb(0);
-- transmitter operation
case r.txstate is
when idle => -- idle and stopbit state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if ((not r.debug and r.txen and (not thempty) and r.txtick) and
((not ctsn) or not r.flow)) = '1' then
v.txstate := data;
v.tpar := r.parsel; v.tsempty := '0';
v.txclk := "00" & r.tick; v.txtick := '0';
v.tshift := '0' & r.thold(conv_integer(r.traddr)) & '0';
if fifosize = 1 then
v.irq := r.irq or r.tirqen; v.tcnt(0) := '0';
else
v.traddr := r.traddr + 1;
v.tcnt := r.tcnt - 1;
end if;
end if;
when data => -- transmit data frame
if r.txtick = '1' then
v.tpar := r.tpar xor r.tshift(1);
v.tshift := '1' & r.tshift(9 downto 1);
if r.tshift(9 downto 1) = "111111110" then
if r.paren = '1' then
v.tshift(0) := r.tpar; v.txstate := cparity;
else
v.tshift(0) := '1'; v.txstate := idle;
end if;
end if;
end if;
when cparity => -- transmit parity bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(9 downto 1); v.txstate := idle;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddress(4 downto 2) is
when "000" =>
if fifosize = 1 then
v.thold(0) := apbi.pwdata(7 downto 0); v.tcnt(0) := '1';
else
v.thold(conv_integer(r.twaddr)) := apbi.pwdata(7 downto 0);
if not (tfull = '1') then
v.twaddr := r.twaddr + 1; v.tcnt := v.tcnt + 1;
end if;
end if;
--pragma translate_off
if CONSOLE = 1 then
if first then L1:= new string'(""); first := false; end if; --'
if apbi.penable'event then --'
CH := character'val(conv_integer(apbi.pwdata(7 downto 0))); --'
if CH = CR then
std.textio.writeline(OUTPUT, L1);
elsif CH /= LF then
std.textio.write(L1,CH);
end if;
pt := now;
end if;
end if;
--pragma translate_on
when others => null;
end case;
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((r.rsempty = '0') and not (rfull = '1')) then
v.rsempty := '1';
v.rhold(conv_integer(r.rwaddr)) := r.rshift;
if fifosize = 1 then v.rcnt(0) := '1';
else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if;
end if;
if (r.rxen and r.rxdb(1) and (not rxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if rxd = '0' then
v.rshift := rxd & r.rshift(7 downto 1); v.rxstate := data;
v.dpar := r.parsel;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd;
v.rshift := rxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
if r.paren = '1' then v.rxstate := cparity;
else v.rxstate := stopbit; v.dpar := '0'; end if;
end if;
end if;
when cparity => -- receive parity bit
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd; v.rxstate := stopbit;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
if r.delayirqen = '0' then
v.irq := v.irq or r.rirqen; -- make sure no tx irqs are lost !
end if;
if rxd = '1' then
if r.delayirqen = '1' then
v.irqpend := r.rirqen; v.irqcnt := (others => '0');
end if;
v.parerr := r.parerr or r.dpar; v.rsempty := r.dpar;
if not (rfull = '1') and (r.dpar = '0') then
v.rsempty := '1';
v.rhold(conv_integer(r.rwaddr)) := r.rshift;
if fifosize = 1 then v.rcnt(0) := '1';
else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if;
end if;
else
if r.rshift = "00000000" then
v.break := '1';
v.irq := v.irq or r.breakirqen;
else v.frame := '1'; end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
end case;
if r.rxtick = '1' then
v.rtsn := (rfull and not r.rsempty) or r.loopb;
end if;
v.txd := r.tshift(0) or r.loopb or r.debug;
if fifosize /= 1 then
if thempty = '0' and v.tcnt = rcntzero then
v.irq := v.irq or r.tirqen;
end if;
v.irq := v.irq or (r.tfifoirqen and r.txen and thalffull);
v.irq := v.irq or (r.rfifoirqen and r.rxen and rhalffull);
if (r.rfifoirqen and r.rxen and rhalffull) = '1' then
v.irqpend := '0';
end if;
end if;
v.irq := v.irq or (r.tsemptyirqen and v.tsempty and not r.tsempty);
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.frame := RES.frame; v.rsempty := RES.rsempty;
v.parerr := RES.parerr; v.ovf := RES.ovf; v.break := RES.break;
v.tsempty := RES.tsempty; v.txen := RES.txen; v.rxen := RES.rxen;
v.txstate := RES.txstate; v.rxstate := RES.rxstate; v.tshift(0) := RES.tshift(0);
v.extclken := RES.extclken; v.rtsn := RES.rtsn; v.flow := RES.flow;
v.txclk := RES.txclk; v.rxclk := RES.rxclk;
v.rcnt := RES.rcnt; v.tcnt := RES.tcnt;
v.rwaddr := RES.rwaddr; v.twaddr := RES.twaddr;
v.rraddr := RES.rraddr; v.traddr := RES.traddr;
v.irqcnt := RES.irqcnt; v.irqpend := RES.irqpend;
end if;
-- update registers
rin <= v;
-- drive outputs
uarto.txd <= r.txd; uarto.rtsn <= r.rtsn;
uarto.scaler <= (others => '0');
uarto.scaler(sbits-1 downto 0) <= r.scaler;
apbo.prdata <= rdata; apbo.pirq <= irq;
apbo.pindex <= pindex;
uarto.txen <= r.txen; uarto.rxen <= r.rxen;
uarto.flow <= '0';
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
-- Sync. registers not reset
r.ctsn <= rin.ctsn;
r.rxf <= rin.rxf;
end if;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbuart" & tost(pindex) &
": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
", irq " & tost(pirq) & ", scaler bits " & tost(sbits));
-- pragma translate_on
end;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- UART Receiver with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- This module was made for use with Spartan-6 Generation Devices and is also ideally
-- suited for use with Virtex-6 and 7-Series devices.
--
-- Version 1 - 31st March 2011.
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the
-- implementation. The Unisim Library is used to define Xilinx primitives. It is also
-- used during simulation.
-- The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for
--
entity uart_rx6 is
Port ( serial_in : in std_logic;
en_16_x_baud : in std_logic;
data_out : out std_logic_vector(7 downto 0);
buffer_read : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end uart_rx6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for uart_rx6
--
architecture low_level_definition of uart_rx6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in uart_rx6
--
-------------------------------------------------------------------------------------------
--
signal pointer_value : std_logic_vector(3 downto 0);
signal pointer : std_logic_vector(3 downto 0);
signal en_pointer : std_logic;
signal zero : std_logic;
signal full_int : std_logic;
signal data_present_value : std_logic;
signal data_present_int : std_logic;
signal sample_value : std_logic;
signal sample : std_logic;
signal sample_dly_value : std_logic;
signal sample_dly : std_logic;
signal stop_bit_value : std_logic;
signal stop_bit : std_logic;
signal data_value : std_logic_vector(7 downto 0);
signal data : std_logic_vector(7 downto 0);
signal run_value : std_logic;
signal run : std_logic;
signal start_bit_value : std_logic;
signal start_bit : std_logic;
signal div_value : std_logic_vector(3 downto 0);
signal div : std_logic_vector(3 downto 0);
signal div_carry : std_logic;
signal sample_input_value : std_logic;
signal sample_input : std_logic;
signal buffer_write_value : std_logic;
signal buffer_write : std_logic;
--
-------------------------------------------------------------------------------------------
--
-- Attributes to guide mapping of logic into Slices.
-------------------------------------------------------------------------------------------
--
--
attribute hblknm : string;
attribute hblknm of pointer3_lut : label is "uart_rx6_1";
attribute hblknm of pointer3_flop : label is "uart_rx6_1";
attribute hblknm of pointer2_lut : label is "uart_rx6_1";
attribute hblknm of pointer2_flop : label is "uart_rx6_1";
attribute hblknm of pointer01_lut : label is "uart_rx6_1";
attribute hblknm of pointer1_flop : label is "uart_rx6_1";
attribute hblknm of pointer0_flop : label is "uart_rx6_1";
attribute hblknm of data_present_lut : label is "uart_rx6_1";
attribute hblknm of data_present_flop : label is "uart_rx6_1";
--
attribute hblknm of data01_lut : label is "uart_rx6_2";
attribute hblknm of data0_flop : label is "uart_rx6_2";
attribute hblknm of data1_flop : label is "uart_rx6_2";
attribute hblknm of data23_lut : label is "uart_rx6_2";
attribute hblknm of data2_flop : label is "uart_rx6_2";
attribute hblknm of data3_flop : label is "uart_rx6_2";
attribute hblknm of data45_lut : label is "uart_rx6_2";
attribute hblknm of data4_flop : label is "uart_rx6_2";
attribute hblknm of data5_flop : label is "uart_rx6_2";
attribute hblknm of data67_lut : label is "uart_rx6_2";
attribute hblknm of data6_flop : label is "uart_rx6_2";
attribute hblknm of data7_flop : label is "uart_rx6_2";
--
attribute hblknm of div01_lut : label is "uart_rx6_3";
attribute hblknm of div23_lut : label is "uart_rx6_3";
attribute hblknm of div0_flop : label is "uart_rx6_3";
attribute hblknm of div1_flop : label is "uart_rx6_3";
attribute hblknm of div2_flop : label is "uart_rx6_3";
attribute hblknm of div3_flop : label is "uart_rx6_3";
attribute hblknm of sample_input_lut : label is "uart_rx6_3";
attribute hblknm of sample_input_flop : label is "uart_rx6_3";
attribute hblknm of full_lut : label is "uart_rx6_3";
--
attribute hblknm of sample_lut : label is "uart_rx6_4";
attribute hblknm of sample_flop : label is "uart_rx6_4";
attribute hblknm of sample_dly_flop : label is "uart_rx6_4";
attribute hblknm of stop_bit_lut : label is "uart_rx6_4";
attribute hblknm of stop_bit_flop : label is "uart_rx6_4";
attribute hblknm of buffer_write_flop : label is "uart_rx6_4";
attribute hblknm of start_bit_lut : label is "uart_rx6_4";
attribute hblknm of start_bit_flop : label is "uart_rx6_4";
attribute hblknm of run_lut : label is "uart_rx6_4";
attribute hblknm of run_flop : label is "uart_rx6_4";
--
--
-------------------------------------------------------------------------------------------
--
-- Start of uart_rx6 circuit description
--
-------------------------------------------------------------------------------------------
--
begin
-- SRL16E data storage
data_width_loop: for i in 0 to 7 generate
attribute hblknm : string;
attribute hblknm of storage_srl : label is "uart_rx6_5";
begin
storage_srl: SRL16E
generic map (INIT => X"0000")
port map( D => data(i),
CE => buffer_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => data_out(i) );
end generate data_width_loop;
pointer3_lut: LUT6
generic map (INIT => X"FF00FE00FF80FF00")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(3));
pointer3_flop: FDR
port map ( D => pointer_value(3),
Q => pointer(3),
R => buffer_reset,
C => clk);
pointer2_lut: LUT6
generic map (INIT => X"F0F0E1E0F878F0F0")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(2));
pointer2_flop: FDR
port map ( D => pointer_value(2),
Q => pointer(2),
R => buffer_reset,
C => clk);
pointer01_lut: LUT6_2
generic map (INIT => X"CC9060CCAA5050AA")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => en_pointer,
I3 => buffer_write,
I4 => buffer_read,
I5 => '1',
O5 => pointer_value(0),
O6 => pointer_value(1));
pointer1_flop: FDR
port map ( D => pointer_value(1),
Q => pointer(1),
R => buffer_reset,
C => clk);
pointer0_flop: FDR
port map ( D => pointer_value(0),
Q => pointer(0),
R => buffer_reset,
C => clk);
data_present_lut: LUT6_2
generic map (INIT => X"F4FCF4FC040004C0")
port map( I0 => zero,
I1 => data_present_int,
I2 => buffer_write,
I3 => buffer_read,
I4 => full_int,
I5 => '1',
O5 => en_pointer,
O6 => data_present_value);
data_present_flop: FDR
port map ( D => data_present_value,
Q => data_present_int,
R => buffer_reset,
C => clk);
full_lut: LUT6_2
generic map (INIT => X"0001000080000000")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => '1',
I5 => '1',
O5 => full_int,
O6 => zero);
sample_lut: LUT6_2
generic map (INIT => X"CCF00000AACC0000")
port map( I0 => serial_in,
I1 => sample,
I2 => sample_dly,
I3 => en_16_x_baud,
I4 => '1',
I5 => '1',
O5 => sample_value,
O6 => sample_dly_value);
sample_flop: FD
port map ( D => sample_value,
Q => sample,
C => clk);
sample_dly_flop: FD
port map ( D => sample_dly_value,
Q => sample_dly,
C => clk);
stop_bit_lut: LUT6_2
generic map (INIT => X"CAFFCAFF0000C0C0")
port map( I0 => stop_bit,
I1 => sample,
I2 => sample_input,
I3 => run,
I4 => data(0),
I5 => '1',
O5 => buffer_write_value,
O6 => stop_bit_value);
buffer_write_flop: FD
port map ( D => buffer_write_value,
Q => buffer_write,
C => clk);
stop_bit_flop: FD
port map ( D => stop_bit_value,
Q => stop_bit,
C => clk);
data01_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(0),
I1 => data(1),
I2 => data(2),
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(0),
O6 => data_value(1));
data0_flop: FD
port map ( D => data_value(0),
Q => data(0),
C => clk);
data1_flop: FD
port map ( D => data_value(1),
Q => data(1),
C => clk);
data23_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(2),
I1 => data(3),
I2 => data(4),
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(2),
O6 => data_value(3));
data2_flop: FD
port map ( D => data_value(2),
Q => data(2),
C => clk);
data3_flop: FD
port map ( D => data_value(3),
Q => data(3),
C => clk);
data45_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(4),
I1 => data(5),
I2 => data(6),
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(4),
O6 => data_value(5));
data4_flop: FD
port map ( D => data_value(4),
Q => data(4),
C => clk);
data5_flop: FD
port map ( D => data_value(5),
Q => data(5),
C => clk);
data67_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(6),
I1 => data(7),
I2 => stop_bit,
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(6),
O6 => data_value(7));
data6_flop: FD
port map ( D => data_value(6),
Q => data(6),
C => clk);
data7_flop: FD
port map ( D => data_value(7),
Q => data(7),
C => clk);
run_lut: LUT6
generic map (INIT => X"2F2FAFAF0000FF00")
port map( I0 => data(0),
I1 => start_bit,
I2 => sample_input,
I3 => sample_dly,
I4 => sample,
I5 => run,
O => run_value);
run_flop: FD
port map ( D => run_value,
Q => run,
C => clk);
start_bit_lut: LUT6
generic map (INIT => X"222200F000000000")
port map( I0 => start_bit,
I1 => sample_input,
I2 => sample_dly,
I3 => sample,
I4 => run,
I5 => '1',
O => start_bit_value);
start_bit_flop: FD
port map ( D => start_bit_value,
Q => start_bit,
C => clk);
div01_lut: LUT6_2
generic map (INIT => X"6C0000005A000000")
port map( I0 => div(0),
I1 => div(1),
I2 => en_16_x_baud,
I3 => run,
I4 => '1',
I5 => '1',
O5 => div_value(0),
O6 => div_value(1));
div0_flop: FD
port map ( D => div_value(0),
Q => div(0),
C => clk);
div1_flop: FD
port map ( D => div_value(1),
Q => div(1),
C => clk);
div23_lut: LUT6_2
generic map (INIT => X"6CCC00005AAA0000")
port map( I0 => div(2),
I1 => div(3),
I2 => div_carry,
I3 => en_16_x_baud,
I4 => run,
I5 => '1',
O5 => div_value(2),
O6 => div_value(3));
div2_flop: FD
port map ( D => div_value(2),
Q => div(2),
C => clk);
div3_flop: FD
port map ( D => div_value(3),
Q => div(3),
C => clk);
sample_input_lut: LUT6_2
generic map (INIT => X"0080000088888888")
port map( I0 => div(0),
I1 => div(1),
I2 => div(2),
I3 => div(3),
I4 => en_16_x_baud,
I5 => '1',
O5 => div_carry,
O6 => sample_input_value);
sample_input_flop: FD
port map ( D => sample_input_value,
Q => sample_input,
C => clk);
-- assign internal signals to outputs
buffer_full <= full_int;
buffer_half_full <= pointer(3);
buffer_data_present <= data_present_int;
end low_level_definition;
-------------------------------------------------------------------------------------------
--
-- END OF FILE uart_rx6.vhd
--
-------------------------------------------------------------------------------------------
|
use work.graphics_types_pkg.all;
use work.sprites_pkg.all;
use work.resource_handles_pkg.all;
use work.npc_pkg.all;
package resource_handles_helper_pkg is
function get_sprite_id_from_handle(sprite_handle: sprite_handle_type) return natural;
function get_bitmap_id_from_handle(handle: bitmap_handle_type) return natural;
function get_collision_id_from_handle(handle: sprite_collision_handle_type) return natural;
function get_id(handle: sprite_handle_type) return natural;
function get_id(handle: bitmap_handle_type) return natural;
function get_id(handle: sprite_collision_handle_type) return natural;
function get_id(handle: npc_handle_type) return natural;
type sprite_handles_pair_type is array (0 to 1) of sprite_handle_type;
type sprite_collision_query_initialization_type is array (natural range <>) of sprite_handles_pair_type;
type sprite_position_pair is record
id: sprite_handle_type;
position: point_type;
end record;
type sprite_positions_init_array is array (natural range<>) of sprite_position_pair;
-- Data type relating a bitmap handle with the bitmap data. With this
-- structure, we can create an initializer function that takes in several
-- bitmap handles and data, and creates the array of bitmaps used in the
-- game. To customize a game, the user needs only to edit that array.
type bitmap_init_type is record
handle: bitmap_handle_type;
bitmap: paletted_bitmap_type(0 to BITMAP_WIDTH-1, 0 to BITMAP_HEIGHT-1);
end record;
type bitmap_init_array_type is array (natural range<>) of bitmap_init_type;
-- Data type relating a sprite handle with a sprite bitmap. With this
-- structure, we can create an initializer that takes in a sprite ID
-- and a bitmap, and creates the corresponding sprite.
type sprite_init_type is record
sprite_handle: sprite_handle_type;
bitmap_handle: bitmap_handle_type;
end record;
type sprite_init_array_type is array (natural range<>) of sprite_init_type;
type sprite_collision_init_type is record
collision_handle: sprite_collision_handle_type;
sprite_1: sprite_handle_type;
sprite_2: sprite_handle_type;
end record;
type sprite_collision_init_array_type is array (natural range<>) of sprite_collision_init_type;
type npc_init_type is record
npc_handle: npc_handle_type;
npc: npc_type;
end record;
type npc_init_array_type is array (natural range<>) of npc_init_type;
function game_strings_count return natural;
end;
package body resource_handles_helper_pkg is
function game_strings_count return natural is begin
return 1 + string_handle_type'pos(string_handle_type'right);
end;
-- Get a sprite ID (an integer non-negative number) associated with the
-- given sprite handle.
function get_sprite_id_from_handle(sprite_handle: sprite_handle_type) return natural is begin
return sprite_handle_type'pos(sprite_handle);
end;
function get_bitmap_id_from_handle(handle: bitmap_handle_type) return natural is begin
return bitmap_handle_type'pos(handle);
end;
function get_collision_id_from_handle(handle: sprite_collision_handle_type) return natural is begin
return sprite_collision_handle_type'pos(handle);
end;
function get_id(handle: sprite_handle_type) return natural is begin
return get_sprite_id_from_handle(handle);
end;
function get_id(handle: bitmap_handle_type) return natural is begin
return get_bitmap_id_from_handle(handle);
end;
function get_id(handle: sprite_collision_handle_type) return natural is begin
return get_collision_id_from_handle(handle);
end;
function get_id(handle: npc_handle_type) return natural is begin
return npc_handle_type'pos(handle);
end;
end;
|
--@ elab pkg_a
package pkg_a is
end package;
--!@ elab pkg_b
package pkg_b is
type BYTE is range 0 to 255;
constant K : BYTE;
end package;
--!@ elab pkg_c
package pkg_c is
use work.pkg_b.BYTE;
type SHORT is range 0 to 65535;
type INT is range 0 to 4294967295;
type PTR is access BYTE;
--type KILOBYTE is array (SHORT range <>) of BYTE;
constant K0 : BYTE;
constant K1 : SHORT;
constant K2 : INT;
end package;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--use work.all;
use work.textmode_controller_pkg.all;
entity textmode_controller_avalon is
generic
(
ROW_COUNT : integer := 30;
COLUM_COUNT : integer := 100;
CLK_FREQ : integer := 25000000;
DATA_WIDTH : integer := 32
);
port
(
clk : in std_logic;
reset_n : in std_logic;
-- avalon interface
address : in std_logic_vector(3 downto 0);
write_n : in std_logic;
writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
irq : out std_logic;
readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
-- ltm outputs
hd : out std_logic; -- horizontal sync signal
vd : out std_logic; -- vertical sync signal
den : out std_logic; -- data enable
r : out std_logic_vector(7 downto 0); -- pixel color value (red)
g : out std_logic_vector(7 downto 0); -- pixel color value (green)
b : out std_logic_vector(7 downto 0); -- pixel color value (blue)
grest : out std_logic -- display reset
);
end textmode_controller_avalon;
architecture behaviour of textmode_controller_avalon is
component textmode_controller_1c is
generic
(
ROW_COUNT : integer := 30;
COLUM_COUNT : integer := 100;
CLK_FREQ : integer := 25000000
);
port
(
clk : in std_logic;
res_n : in std_logic;
wr : in std_logic;
busy : out std_logic;
instr : in std_logic_vector(7 downto 0);
instr_data : in std_logic_vector(15 downto 0);
hd : out std_logic; -- horizontal sync signal
vd : out std_logic; -- vertical sync signal
den : out std_logic; -- data enable
r : out std_logic_vector(7 downto 0); -- pixel color value (red)
g : out std_logic_vector(7 downto 0); -- pixel color value (green)
b : out std_logic_vector(7 downto 0); -- pixel color value (blue)
grest : out std_logic -- display reset
);
end component textmode_controller_1c;
signal wr : std_logic;
signal busy : std_logic;
signal instr : std_logic_vector(7 downto 0);
signal instr_data : std_logic_vector(15 downto 0);
begin
tmc_inst: textmode_controller_1c
generic map
(
ROW_COUNT => ROW_COUNT,
COLUM_COUNT => COLUM_COUNT,
CLK_FREQ => CLK_FREQ
)
port map
(
clk => clk,
res_n => reset_n,
wr => wr,
busy => busy,
instr => instr,
instr_data => instr_data,
hd => hd,
vd => vd,
den => den,
r => r,
g => g,
b => b,
grest => grest
);
wr_proc: process(address,write_n,writedata)
begin
if (address = "0000") and (write_n = '0') then
instr <= writedata(7 downto 0);
instr_data <= writedata(23 downto 8);
wr <= '1';
else
instr <= INSTR_NOP;
instr_data <= (others => '0');
wr <= '0';
end if;
end process;
readdata <= (0 => busy, others => '0');
irq <= '0';
end behaviour;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--use work.all;
use work.textmode_controller_pkg.all;
entity textmode_controller_avalon is
generic
(
ROW_COUNT : integer := 30;
COLUM_COUNT : integer := 100;
CLK_FREQ : integer := 25000000;
DATA_WIDTH : integer := 32
);
port
(
clk : in std_logic;
reset_n : in std_logic;
-- avalon interface
address : in std_logic_vector(3 downto 0);
write_n : in std_logic;
writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
irq : out std_logic;
readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
-- ltm outputs
hd : out std_logic; -- horizontal sync signal
vd : out std_logic; -- vertical sync signal
den : out std_logic; -- data enable
r : out std_logic_vector(7 downto 0); -- pixel color value (red)
g : out std_logic_vector(7 downto 0); -- pixel color value (green)
b : out std_logic_vector(7 downto 0); -- pixel color value (blue)
grest : out std_logic -- display reset
);
end textmode_controller_avalon;
architecture behaviour of textmode_controller_avalon is
component textmode_controller_1c is
generic
(
ROW_COUNT : integer := 30;
COLUM_COUNT : integer := 100;
CLK_FREQ : integer := 25000000
);
port
(
clk : in std_logic;
res_n : in std_logic;
wr : in std_logic;
busy : out std_logic;
instr : in std_logic_vector(7 downto 0);
instr_data : in std_logic_vector(15 downto 0);
hd : out std_logic; -- horizontal sync signal
vd : out std_logic; -- vertical sync signal
den : out std_logic; -- data enable
r : out std_logic_vector(7 downto 0); -- pixel color value (red)
g : out std_logic_vector(7 downto 0); -- pixel color value (green)
b : out std_logic_vector(7 downto 0); -- pixel color value (blue)
grest : out std_logic -- display reset
);
end component textmode_controller_1c;
signal wr : std_logic;
signal busy : std_logic;
signal instr : std_logic_vector(7 downto 0);
signal instr_data : std_logic_vector(15 downto 0);
begin
tmc_inst: textmode_controller_1c
generic map
(
ROW_COUNT => ROW_COUNT,
COLUM_COUNT => COLUM_COUNT,
CLK_FREQ => CLK_FREQ
)
port map
(
clk => clk,
res_n => reset_n,
wr => wr,
busy => busy,
instr => instr,
instr_data => instr_data,
hd => hd,
vd => vd,
den => den,
r => r,
g => g,
b => b,
grest => grest
);
wr_proc: process(address,write_n,writedata)
begin
if (address = "0000") and (write_n = '0') then
instr <= writedata(7 downto 0);
instr_data <= writedata(23 downto 8);
wr <= '1';
else
instr <= INSTR_NOP;
instr_data <= (others => '0');
wr <= '0';
end if;
end process;
readdata <= (0 => busy, others => '0');
irq <= '0';
end behaviour;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP lookup in cache
-- request cache fill through ARP protocol if required
-- cache is simple 1 deep
-- Handle ARP protocol
-- Respond to ARP requests and replies
-- Ignore pkts that are not ARP
-- Ignore pkts that are not addressed to us
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Added req for mac tx and wait for grant
-- Revision 0.03 - Added data_out_first
-- Revision 0.04 - Added arp response timeout
-- Revision 0.05 - Added arp cache reset control
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.arp_types.all;
entity arp is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 1; -- (added for compatibility with arpv2. this value not used in this impl)
MAX_ARP_ENTRIES : integer := 1 -- (added for compatibility with arpv2. this value not used in this impl)
);
Port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
data_in_last : in STD_LOGIC; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0);
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
control : in arp_control_type;
req_count : out STD_LOGIC_VECTOR(7 downto 0) -- count of arp pkts received
);
end arp;
architecture Behavioral of arp is
type req_state_type is (IDLE,LOOKUP,REQUEST,WAIT_REPLY,PAUSE1,PAUSE2,PAUSE3);
type rx_state_type is (IDLE,PARSE,PROCESS_ARP,WAIT_END);
type rx_event_type is (NO_EVENT,DATA);
type count_mode_type is (RST,INCR,HOLD);
type arp_oper_type is (NOP,REQUEST,REPLY);
type set_clr_type is (SET, CLR, HOLD);
type tx_state_type is (IDLE,WAIT_MAC,SEND);
type arp_entry_type is record
ip : std_logic_vector (31 downto 0);
mac : std_logic_vector (47 downto 0);
is_valid : std_logic;
reply_required : std_logic;
end record;
-- state variables
signal req_state : req_state_type;
signal req_ip_addr : std_logic_vector (31 downto 0); -- IP address to lookup
signal mac_addr_found : STD_LOGIC_VECTOR (47 downto 0); -- mac address found
signal mac_addr_valid_reg: std_logic;
signal send_request_needed : std_logic;
signal tx_mac_chn_reqd : std_logic;
signal freq_scaler : unsigned (31 downto 0); -- scales data_in_clk downto 1Hz
signal timer : unsigned (7 downto 0); -- counts seconds timeout
signal timeout_reg : std_logic;
signal rx_state : rx_state_type;
signal rx_count : unsigned (7 downto 0);
signal arp_operation : arp_oper_type;
signal arp_req_count : unsigned (7 downto 0);
signal arp_entry : arp_entry_type; -- arp entry store
signal new_arp_entry : arp_entry_type;
signal tx_state : tx_state_type;
signal tx_count : unsigned (7 downto 0);
-- FIXME - remove these debug state signals
signal arp_err_data : std_logic_vector (7 downto 0);
signal set_err_data : std_logic;
attribute keep : string;
attribute keep of arp_err_data : signal is "true";
-- requester control signals
signal next_req_state : req_state_type;
signal set_req_state : std_logic;
signal set_req_ip : std_logic;
signal set_mac_addr : std_logic;
signal set_mac_addr_invalid : std_logic;
signal set_send_req : std_logic;
signal clear_send_req : std_logic;
signal set_timer : count_mode_type; -- timer reset, count, hold control
signal timer_enable : std_logic; -- enable the timer counting
signal set_timeout : set_clr_type; -- control the timeout register
-- rx control signals
signal next_rx_state : rx_state_type;
signal set_rx_state : std_logic;
signal rx_event : rx_event_type;
signal rx_count_mode : count_mode_type;
signal set_arp_oper : std_logic;
signal arp_oper_set_val : arp_oper_type;
signal dataval : std_logic_vector (7 downto 0);
signal set_arp_entry_request : std_logic;
signal set_mac5 : std_logic;
signal set_mac4 : std_logic;
signal set_mac3 : std_logic;
signal set_mac2 : std_logic;
signal set_mac1 : std_logic;
signal set_mac0 : std_logic;
signal set_ip3 : std_logic;
signal set_ip2 : std_logic;
signal set_ip1 : std_logic;
signal set_ip0 : std_logic;
-- tx control signals
signal next_tx_state : tx_state_type;
signal set_tx_state : std_logic;
signal tx_count_mode : count_mode_type;
signal clear_reply_req : std_logic;
signal set_chn_reqd : set_clr_type;
signal kill_data_out_valid : std_logic;
-- function to determine whether the rx pkt is an arp pkt and whether we want to process it
-- Returns 1 if we should discard
-- The following will make us ignore the frame (all values hexadecimal):
-- PDU type /= 0806
-- Protocol Type /= 0800
-- Hardware Type /= 1
-- Hardware Length /= 6
-- Protocol Length /= 4
-- Operation /= 1 or 2
-- Target IP /= our IP (i.er. message is not meant for us)
--
function not_our_arp(data : STD_LOGIC_VECTOR; count : unsigned; our_ip : std_logic_vector) return std_logic is
begin
if
(count = 12 and data /= x"08") or -- PDU type 0806 : ARP
(count = 13 and data /= x"06") or
(count = 14 and data /= x"00") or -- HW type 1 : eth
(count = 15 and data /= x"01") or
(count = 16 and data /= x"08") or -- Protocol 0800 : IP
(count = 17 and data /= x"00") or
(count = 18 and data /= x"06") or -- HW Length 6
(count = 19 and data /= x"04") or -- protocol length 4
(count = 20 and data /= x"00") or -- operation 1 or 2 (req or reply)
(count = 21 and data /= x"01" and data /= x"02") or
(count = 38 and data /= our_ip(31 downto 24)) or -- target IP is ours
(count = 39 and data /= our_ip(23 downto 16)) or
(count = 40 and data /= our_ip(15 downto 8)) or
(count = 41 and data /= our_ip(7 downto 0))
then
return '1';
else
return '0';
end if;
end function not_our_arp;
begin
req_combinatorial : process (
-- input signals
arp_req_req,
-- state variables
req_state, req_ip_addr, mac_addr_found, mac_addr_valid_reg, send_request_needed, arp_entry,
freq_scaler, timer, timeout_reg,
-- control signals
next_req_state, set_req_state, set_req_ip, set_mac_addr, control,
set_mac_addr_invalid,set_send_req, clear_send_req, set_timer, timer_enable, set_timeout
)
begin
-- set output followers
if arp_req_req.lookup_req = '1' then
arp_req_rslt.got_err <= '0';
else
arp_req_rslt.got_err <= timeout_reg;
end if;
-- zero time response to lookup request if already in cache
if arp_req_req.lookup_req = '1' and arp_req_req.ip = arp_entry.ip and arp_entry.is_valid = '1' then
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_entry.mac;
elsif arp_req_req.lookup_req = '1' then
arp_req_rslt.got_mac <= '0'; -- hold off got_mac while req is there as arp_entry will not be correct yet
arp_req_rslt.mac <= arp_entry.mac;
else
arp_req_rslt.got_mac <= mac_addr_valid_reg;
arp_req_rslt.mac <= mac_addr_found;
end if;
-- set signal defaults
next_req_state <= IDLE;
set_req_state <= '0';
set_req_ip <= '0';
set_mac_addr <= '0';
set_mac_addr_invalid <= '0';
set_send_req <= '0';
clear_send_req <= '0';
set_timer <= INCR; -- default is timer running, unless we hold or reset it
set_timeout <= HOLD;
timer_enable <= '0';
-- combinatorial logic
if freq_scaler = x"00000000" then
timer_enable <= '1';
end if;
-- REQ FSM
case req_state is
when IDLE =>
set_timer <= RST;
if arp_req_req.lookup_req = '1' then
-- check if we already have the info in cache
if arp_req_req.ip = arp_entry.ip and arp_entry.is_valid = '1' then
-- already have this IP
set_mac_addr <= '1';
else
set_timeout <= CLR;
next_req_state <= LOOKUP;
set_req_state <= '1';
set_req_ip <= '1';
set_mac_addr_invalid <= '1';
end if;
end if;
when LOOKUP =>
if arp_entry.ip = req_ip_addr and arp_entry.is_valid = '1' then
-- already have this IP
next_req_state <= IDLE;
set_req_state <= '1';
set_mac_addr <= '1';
else
-- need to request mac for this IP
set_send_req <= '1';
set_timer <= RST;
next_req_state <= REQUEST;
set_req_state <= '1';
end if;
when REQUEST =>
clear_send_req <= '1';
next_req_state <= WAIT_REPLY;
set_req_state <= '1';
when WAIT_REPLY =>
if arp_entry.is_valid = '1' then
-- have reply, go back to LOOKUP state to see if it is the right one
next_req_state <= LOOKUP;
set_req_state <= '1';
end if;
if timer >= ARP_TIMEOUT then
set_timeout <= SET;
next_req_state <= PAUSE1;
set_req_state <= '1';
end if;
when PAUSE1 =>
next_req_state <= PAUSE2;
set_req_state <= '1';
when PAUSE2 =>
next_req_state <= PAUSE3;
set_req_state <= '1';
when PAUSE3 =>
next_req_state <= IDLE;
set_req_state <= '1';
end case;
end process;
req_sequential : process (data_in_clk,reset)
begin
if rising_edge(data_in_clk) then
if reset = '1' then
-- reset state variables
req_state <= IDLE;
req_ip_addr <= (others => '0');
mac_addr_found <= (others => '0');
mac_addr_valid_reg <= '0';
send_request_needed <= '0';
freq_scaler <= to_unsigned(CLOCK_FREQ,32);
timer <= (others => '0');
timeout_reg <= '0';
else
-- Next req_state processing
if set_req_state = '1' then
req_state <= next_req_state;
else
req_state <= req_state;
end if;
-- Latch the requested IP address
if set_req_ip = '1' then
req_ip_addr <= arp_req_req.ip;
else
req_ip_addr <= req_ip_addr;
end if;
-- send request to TX&RX FSMs to send an ARP request
if set_send_req = '1' then
send_request_needed <= '1';
elsif clear_send_req = '1' then
send_request_needed <= '0';
else
send_request_needed <= send_request_needed;
end if;
-- Set the found mac address
if set_mac_addr = '1' then
mac_addr_found <= arp_entry.mac;
mac_addr_valid_reg <= '1';
elsif set_mac_addr_invalid = '1' then
mac_addr_found <= (others => '0');
mac_addr_valid_reg <= '0';
else
mac_addr_found <= mac_addr_found;
mac_addr_valid_reg <= mac_addr_valid_reg;
end if;
-- freq scaling and 1-sec timer
if freq_scaler = x"00000000" then
freq_scaler <= to_unsigned(CLOCK_FREQ,32);
else
freq_scaler <= freq_scaler - 1;
end if;
-- timer processing
case set_timer is
when RST =>
timer <= x"00";
when INCR =>
if timer_enable = '1' then
timer <= timer + 1;
else
timer <= timer;
end if;
when HOLD =>
timer <= timer;
end case;
-- timeout latching
case set_timeout is
when CLR => timeout_reg <= '0';
when SET => timeout_reg <= '1';
when HOLD => timeout_reg <= timeout_reg;
end case;
end if;
end if;
end process;
rx_combinatorial : process (
-- input signals
data_in, data_in_valid, data_in_last, our_ip_address,
-- state variables
rx_state, rx_count, arp_operation, arp_req_count, arp_err_data,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode, set_arp_oper, arp_oper_set_val,
dataval,set_mac5,set_mac4,set_mac3,set_mac2,set_mac1,set_mac0,set_ip3,set_ip2,set_ip1,set_ip0, set_err_data,
set_arp_entry_request)
begin
-- set output followers
req_count <= STD_LOGIC_VECTOR(arp_req_count);
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_arp_oper <= '0';
arp_oper_set_val <= NOP;
dataval <= (others => '0');
set_mac5 <= '0';
set_mac4 <= '0';
set_mac3 <= '0';
set_mac2 <= '0';
set_mac1 <= '0';
set_mac0 <= '0';
set_ip3 <= '0';
set_ip2 <= '0';
set_ip1 <= '0';
set_ip0 <= '0';
set_arp_entry_request <= '0';
set_err_data <= '0';
-- determine event (if any)
if data_in_valid = '1' then
rx_event <= DATA;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
next_rx_state <= PARSE;
set_rx_state <= '1';
rx_count_mode <= INCR;
end case;
when PARSE =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
rx_count_mode <= INCR;
-- handle early frame termination
if data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
else
-- check for end of frame. Also, detect and discard if not our frame
if rx_count = 42 then
next_rx_state <= PROCESS_ARP;
set_rx_state <= '1';
elsif not_our_arp(data_in,rx_count,our_ip_address) = '1' then
dataval <= data_in;
set_err_data <= '1';
next_rx_state <= WAIT_END;
set_rx_state <= '1';
elsif rx_count = 21 then
-- capture ARP operation
case data_in is
when x"01" =>
arp_oper_set_val <= REQUEST;
set_arp_oper <= '1';
when x"02" =>
arp_oper_set_val <= REPLY;
set_arp_oper <= '1';
when others => -- ignore other values
end case;
-- capture source mac addr
elsif rx_count = 22 then
set_mac5 <= '1';
dataval <= data_in;
elsif rx_count = 23 then
set_mac4 <= '1';
dataval <= data_in;
elsif rx_count = 24 then
set_mac3 <= '1';
dataval <= data_in;
elsif rx_count = 25 then
set_mac2 <= '1';
dataval <= data_in;
elsif rx_count = 26 then
set_mac1 <= '1';
dataval <= data_in;
elsif rx_count = 27 then
set_mac0 <= '1';
dataval <= data_in;
-- capture source ip addr
elsif rx_count = 28 then
set_ip3 <= '1';
dataval <= data_in;
elsif rx_count = 29 then
set_ip2 <= '1';
dataval <= data_in;
elsif rx_count = 30 then
set_ip1 <= '1';
dataval <= data_in;
elsif rx_count = 31 then
set_ip0 <= '1';
dataval <= data_in;
end if;
end if;
end case;
when PROCESS_ARP =>
next_rx_state <= WAIT_END;
set_rx_state <= '1';
case arp_operation is
when NOP => -- (nothing to do)
when REQUEST =>
set_arp_entry_request <= '1';
arp_oper_set_val <= NOP;
set_arp_oper <= '1';
when REPLY =>
set_arp_entry_request <= '1';
arp_oper_set_val <= NOP;
set_arp_oper <= '1';
end case;
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
end case;
end case;
end process;
rx_sequential : process (data_in_clk)
begin
if rising_edge(data_in_clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"00";
arp_operation <= NOP;
arp_req_count <= x"00";
-- reset arp entry store
arp_entry.ip <= x"00000000";
arp_entry.mac <= x"000000000000";
arp_entry.is_valid <= '0';
arp_entry.reply_required <= '0';
arp_err_data <= (others => '0');
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST =>
rx_count <= x"00";
when INCR =>
rx_count <= rx_count + 1;
when HOLD =>
rx_count <= rx_count;
end case;
-- err data
if set_err_data = '1' then
arp_err_data <= data_in;
else
arp_err_data <= arp_err_data;
end if;
-- arp operation processing
if set_arp_oper = '1' then
arp_operation <= arp_oper_set_val;
else
arp_operation <= arp_operation;
end if;
-- source mac capture
if (set_mac5 = '1') then new_arp_entry.mac(47 downto 40) <= dataval; end if;
if (set_mac4 = '1') then new_arp_entry.mac(39 downto 32) <= dataval; end if;
if (set_mac3 = '1') then new_arp_entry.mac(31 downto 24) <= dataval; end if;
if (set_mac2 = '1') then new_arp_entry.mac(23 downto 16) <= dataval; end if;
if (set_mac1 = '1') then new_arp_entry.mac(15 downto 8) <= dataval; end if;
if (set_mac0 = '1') then new_arp_entry.mac(7 downto 0) <= dataval; end if;
-- source ip capture
if (set_ip3 = '1') then new_arp_entry.ip(31 downto 24) <= dataval; end if;
if (set_ip2 = '1') then new_arp_entry.ip(23 downto 16) <= dataval; end if;
if (set_ip1 = '1') then new_arp_entry.ip(15 downto 8) <= dataval; end if;
if (set_ip0 = '1') then new_arp_entry.ip(7 downto 0) <= dataval; end if;
-- set arp entry request
if control.clear_cache = '1' then
arp_entry.ip <= x"00000000";
arp_entry.mac <= x"000000000000";
arp_entry.is_valid <= '0';
arp_entry.reply_required <= '0';
elsif set_arp_entry_request = '1' then
-- copy info from new entry to arp_entry and set reply required
arp_entry.mac <= new_arp_entry.mac;
arp_entry.ip <= new_arp_entry.ip;
arp_entry.is_valid <= '1';
if arp_operation = REQUEST then
arp_entry.reply_required <= '1';
else
arp_entry.reply_required <= '0';
end if;
-- count another ARP pkt received
arp_req_count <= arp_req_count + 1;
elsif clear_reply_req = '1' then
-- note: clear_reply_req is set by tx logic, but handled in the clk domain of the rx
-- maintain arp entry state, but reset the reply required flag
arp_entry.mac <= arp_entry.mac;
arp_entry.ip <= arp_entry.ip;
arp_entry.is_valid <= arp_entry.is_valid;
arp_entry.reply_required <= '0';
arp_req_count <= arp_req_count;
elsif send_request_needed = '1' then
-- set up the arp entry to take the request to be transmitted out by the TX FSM
arp_entry.ip <= req_ip_addr;
arp_entry.mac <= (others => '0');
arp_entry.is_valid <= '0';
arp_entry.reply_required <= '0';
else
arp_entry <= arp_entry;
arp_req_count <= arp_req_count;
end if;
end if;
end if;
end process;
tx_combinatorial : process (
-- input signals
data_out_ready, send_request_needed, mac_tx_granted, our_mac_address, our_ip_address,
-- state variables
tx_state, tx_count, tx_mac_chn_reqd, arp_entry,
-- control signals
next_rx_state, set_rx_state, tx_count_mode, kill_data_out_valid,
set_chn_reqd, clear_reply_req)
begin
-- set output followers
mac_tx_req <= tx_mac_chn_reqd;
-- set initial values for combinatorial outputs
data_out_first <= '0';
case tx_state is
when SEND =>
if data_out_ready = '1' and kill_data_out_valid = '0' then
data_out_valid <= '1';
else
data_out_valid <= '0';
end if;
when OTHERS => data_out_valid <= '0';
end case;
-- set signal defaults
next_tx_state <= IDLE;
set_tx_state <= '0';
tx_count_mode <= HOLD;
data_out <= x"00";
data_out_last <= '0';
clear_reply_req <= '0';
set_chn_reqd <= HOLD;
kill_data_out_valid <= '0';
-- TX FSM
case tx_state is
when IDLE =>
tx_count_mode <= RST;
if arp_entry.reply_required = '1' then
set_chn_reqd <= SET;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
elsif send_request_needed = '1' then
set_chn_reqd <= SET;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
else
set_chn_reqd <= CLR;
end if;
when WAIT_MAC =>
tx_count_mode <= RST;
if mac_tx_granted = '1' then
next_tx_state <= SEND;
set_tx_state <= '1';
end if;
-- TODO - should handle timeout here
when SEND =>
if data_out_ready = '1' then
tx_count_mode <= INCR;
end if;
case tx_count is
when x"00" =>
data_out_first <= data_out_ready;
data_out <= x"ff"; -- dst = broadcast
when x"01" => data_out <= x"ff";
when x"02" => data_out <= x"ff";
when x"03" => data_out <= x"ff";
when x"04" => data_out <= x"ff";
when x"05" => data_out <= x"ff";
when x"06" => data_out <= our_mac_address (47 downto 40); -- src = our mac
when x"07" => data_out <= our_mac_address (39 downto 32);
when x"08" => data_out <= our_mac_address (31 downto 24);
when x"09" => data_out <= our_mac_address (23 downto 16);
when x"0a" => data_out <= our_mac_address (15 downto 8);
when x"0b" => data_out <= our_mac_address (7 downto 0);
when x"0c" => data_out <= x"08"; -- pkt type = 0806 : ARP
when x"0d" => data_out <= x"06";
when x"0e" => data_out <= x"00"; -- HW type = 0001 : eth
when x"0f" => data_out <= x"01";
when x"10" => data_out <= x"08"; -- protocol = 0800 : ip
when x"11" => data_out <= x"00";
when x"12" => data_out <= x"06"; -- HW size = 06
when x"13" => data_out <= x"04"; -- prot size = 04
when x"14" => data_out <= x"00"; -- opcode =
when x"15" =>
if arp_entry.is_valid = '1' then
data_out <= x"02"; -- 02 : REPLY if arp_entry valid
else
data_out <= x"01"; -- 01 : REQ if arp_entry invalid
end if;
when x"16" => data_out <= our_mac_address (47 downto 40); -- sender mac
when x"17" => data_out <= our_mac_address (39 downto 32);
when x"18" => data_out <= our_mac_address (31 downto 24);
when x"19" => data_out <= our_mac_address (23 downto 16);
when x"1a" => data_out <= our_mac_address (15 downto 8);
when x"1b" => data_out <= our_mac_address (7 downto 0);
when x"1c" => data_out <= our_ip_address (31 downto 24); -- sender ip
when x"1d" => data_out <= our_ip_address (23 downto 16);
when x"1e" => data_out <= our_ip_address (15 downto 8);
when x"1f" => data_out <= our_ip_address (7 downto 0);
when x"20" => data_out <= arp_entry.mac (47 downto 40); -- target mac
when x"21" => data_out <= arp_entry.mac (39 downto 32);
when x"22" => data_out <= arp_entry.mac (31 downto 24);
when x"23" => data_out <= arp_entry.mac (23 downto 16);
when x"24" => data_out <= arp_entry.mac (15 downto 8);
when x"25" => data_out <= arp_entry.mac (7 downto 0);
when x"26" => data_out <= arp_entry.ip (31 downto 24); -- target ip
when x"27" => data_out <= arp_entry.ip (23 downto 16);
when x"28" => data_out <= arp_entry.ip (15 downto 8);
when x"29" =>
data_out <= arp_entry.ip(7 downto 0);
data_out_last <= '1';
when x"2a" =>
clear_reply_req <= '1'; -- reset the reply request (done in the rx clk process domain)
kill_data_out_valid <= '1'; -- data is no longer valid
next_tx_state <= IDLE;
set_tx_state <= '1';
when others =>
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end case;
end process;
tx_sequential : process (data_out_clk,reset)
begin
if rising_edge(data_out_clk) then
if reset = '1' then
-- reset state variables
tx_state <= IDLE;
tx_mac_chn_reqd <= '0';
else
-- Next rx_state processing
if set_tx_state = '1' then
tx_state <= next_tx_state;
else
tx_state <= tx_state;
end if;
-- tx_count processing
case tx_count_mode is
when RST =>
tx_count <= x"00";
when INCR =>
tx_count <= tx_count + 1;
when HOLD =>
tx_count <= tx_count;
end case;
-- control access request to mac tx chn
case set_chn_reqd is
when SET => tx_mac_chn_reqd <= '1';
when CLR => tx_mac_chn_reqd <= '0';
when HOLD => tx_mac_chn_reqd <= tx_mac_chn_reqd;
end case;
end if;
end if;
end process;
end Behavioral;
|
---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : SN74LVTH245.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 09/02/12
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: SN74LVTH245.vhd,v $
-- Revision 1.1 2012/03/29 10:28:42 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SN74LVTH245 IS
GENERIC (
OP_COND : integer:=1; -- 0=min, 1=typ, 2=max
WIDTH : integer:=8
);
PORT (
dir : IN std_logic; -- direction: 0= B data to A, 1= A data to B
oe_n : IN std_logic; -- output enable: 0= driver is active, 1= tri-state
a : INOUT std_logic_vector(WIDTH-1 DOWNTO 0); -- port A
b : INOUT std_logic_vector(WIDTH-1 DOWNTO 0) -- port B
);
END SN74LVTH245;
ARCHITECTURE SN74LVTH245_arch OF SN74LVTH245 IS
CONSTANT tPLH_max : time:= 3.5 ns;
CONSTANT tPHL_max : time:= 3.5 ns;
CONSTANT tPZH_max : time:= 5.5 ns;
CONSTANT tPZL_max : time:= 5.5 ns;
CONSTANT tPHZ_max : time:= 5.9 ns;
CONSTANT tPLZ_max : time:= 5.0 ns;
CONSTANT tPLH_min : time:= 1.2 ns;
CONSTANT tPHL_min : time:= 1.2 ns;
CONSTANT tPZH_min : time:= 1.3 ns;
CONSTANT tPZL_min : time:= 1.7 ns;
CONSTANT tPHZ_min : time:= 2.2 ns;
CONSTANT tPLZ_min : time:= 2.2 ns;
CONSTANT tPLH_typ : time:= 2.3 ns;
CONSTANT tPHL_typ : time:= 2.1 ns;
CONSTANT tPZH_typ : time:= 3.2 ns;
CONSTANT tPZL_typ : time:= 3.4 ns;
CONSTANT tPHZ_typ : time:= 3.5 ns;
CONSTANT tPLZ_typ : time:= 3.4 ns;
SIGNAL oe_n_in : std_logic;
SIGNAL dir_in : std_logic;
SIGNAL a_out : std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL b_out : std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL a_int : std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL b_int : std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL tPLH : time;
SIGNAL tPHL : time;
SIGNAL tPZH : time;
SIGNAL tPZL : time;
SIGNAL tPHZ : time;
SIGNAL tPLZ : time;
SIGNAL pwr_rst : std_logic;
BEGIN
tPLH <= tPLH_min WHEN OP_COND = 0 ELSE
tPLH_typ WHEN OP_COND = 1 ELSE
tPLH_max;
tPHL <= tPHL_min WHEN OP_COND = 0 ELSE
tPHL_typ WHEN OP_COND = 1 ELSE
tPHL_max;
tPZH <= tPZH_min WHEN OP_COND = 0 ELSE
tPZH_typ WHEN OP_COND = 1 ELSE
tPZH_max;
tPZL <= tPZL_min WHEN OP_COND = 0 ELSE
tPZL_typ WHEN OP_COND = 1 ELSE
tPZL_max;
tPHZ <= tPHZ_min WHEN OP_COND = 0 ELSE
tPHZ_typ WHEN OP_COND = 1 ELSE
tPHZ_max;
tPLZ <= tPLZ_min WHEN OP_COND = 0 ELSE
tPLZ_typ WHEN OP_COND = 1 ELSE
tPLZ_max;
a <= a_out;
b <= b_out;
a_int <= transport to_x01(a) after 1 ps;
b_int <= transport to_x01(b) after 1 ps;
oe_n_in <= to_x01(oe_n);
dir_in <= to_x01(dir);
pwr_rst <= '1', '0' AFTER 2 ps;
gen: FOR i IN 0 TO (WIDTH-1) GENERATE
PROCESS(pwr_rst, dir_in, oe_n_in, a_int, b_int, a_out(i), b_out(i))
BEGIN
IF pwr_rst'event AND dir_in = '0' AND oe_n_in = '1' THEN
a_out(i) <= 'H';
ELSIF pwr_rst'event AND dir_in = '0' AND oe_n_in = '0' THEN
a_out(i) <= b_int(i);
ELSIF (pwr_rst'event OR dir_in'event) AND dir_in = '1' THEN
a_out(i) <= 'H';
ELSIF (b_int(i)'event AND b_int(i) = '1' AND oe_n_in = '0' AND dir_in = '0') OR -- b 0->1
(dir_in'event AND dir_in = '0' AND oe_n_in = '0' AND b_int(i) = '1') THEN -- dir_in 1->0
a_out(i) <= transport b_int(i) AFTER tPLH;
ELSIF (b_int(i)'event AND b_int(i) = '0' AND oe_n_in = '0' AND dir_in = '0') OR -- b 1->0
(dir_in'event AND dir_in = '0' AND oe_n_in = '0' AND b_int(i) = '0') THEN -- dir_in 0->1
a_out(i) <= transport b_int(i) AFTER tPHL;
ELSIF (oe_n_in'event AND oe_n_in = '0' AND b_int(i) = '1' AND dir_in = '0') THEN -- oe_n_in 1->0 b=1
a_out(i) <= transport b_int(i) AFTER tPZH;
ELSIF (oe_n_in'event AND oe_n_in = '0' AND b_int(i) = '0' AND dir_in = '0') THEN -- oe_n_in 1->0 b=0
a_out(i) <= transport b_int(i) AFTER tPZL;
ELSIF (oe_n_in'event AND oe_n_in = '1' AND a_int(i) = '1' AND dir_in = '0') THEN -- oe_n_in 0->1 a=1
a_out(i) <= transport 'H' AFTER tPHZ;
ELSIF (oe_n_in'event AND oe_n_in = '1' AND a_int(i) = '0' AND dir_in = '0') THEN -- oe_n_in 0->1 a=0
a_out(i) <= transport 'H' AFTER tPLZ;
END IF;
IF pwr_rst'event AND dir_in = '1' AND oe_n_in = '1' THEN
b_out(i) <= 'H';
ELSIF pwr_rst'event AND dir_in = '1' AND oe_n_in = '0' THEN
b_out(i) <= a_int(i);
ELSIF (pwr_rst'event OR dir_in'event) AND dir_in = '0' THEN
b_out(i) <= 'H';
ELSIF (a_int(i)'event AND a_int(i) = '1' AND oe_n_in = '0' AND dir_in = '1') OR -- a 0->1
(dir_in'event AND dir_in = '1' AND oe_n_in = '0' AND a_int(i) = '1') THEN -- dir_in 0->1
b_out(i) <= transport a_int(i) AFTER tPLH;
ELSIF (a_int(i)'event AND a_int(i) = '0' AND oe_n_in = '0' AND dir_in = '1') OR -- a 1->0
(dir_in'event AND dir_in = '1' AND oe_n_in = '0' AND a_int(i) = '0') THEN -- dir_in 1->0
b_out(i) <= transport a_int(i) AFTER tPHL;
ELSIF (oe_n_in'event AND oe_n_in = '0' AND a_int(i) = '1' AND dir_in = '1') THEN -- oe_n_in 1->0 a=1
b_out(i) <= transport a_int(i) AFTER tPZH;
ELSIF (oe_n_in'event AND oe_n_in = '0' AND a_int(i) = '0' AND dir_in = '1') THEN -- oe_n_in 1->0 a=0
b_out(i) <= transport a_int(i) AFTER tPZL;
ELSIF (oe_n_in'event AND oe_n_in = '1' AND b_int(i) = '1' AND dir_in = '1') THEN -- oe_n_in 0->1 b=1
b_out(i) <= transport 'H' AFTER tPHZ;
ELSIF (oe_n_in'event AND oe_n_in = '1' AND b_int(i) = '0' AND dir_in = '1') THEN -- oe_n_in 0->1 b=0
b_out(i) <= transport 'H' AFTER tPLZ;
END IF;
END PROCESS;
END GENERATE gen;
END SN74LVTH245_arch;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IVxyk7XRM4VsQcD0QPYws4xsTeDPKdwWYfreQJ7l1z8C+G+JAKZ2psrNI+b5ecZ2ziPH9MBGr/oY
8XtzCKmjJw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VO3Jpo4aYF9TyVwyAUb3a/oDy8Yhm9ea/9mAjNtuOBRL0qoy0/CWzL7D+bc1SnZvEP4BG903Ildl
dM2y4TNyVTBUaU7Cz+LzZfu9kCPWnmttlx92LcMKLNuvGUMPXmV5jr3PzSFEvoDuCinMqNc8uKFO
Ux/aX6fmBD8AbQfpK30=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qOkimDe0rSU5f1zKvoE8a4lZw1WOOUxh8wtTIN0ys09AXuQuNNCdfu6VL2Xuj0Xus09sBU1FazgW
XpQHuw7XcozHRlnUFKPJg2P12yPJsLRkOqUWtHTUXmH/8s2RglOoEcmFeX9FVh1IRMdnp+D/F4GX
/80OwH0Jtm4eUDa5EFkNoIfhlOG4JOG/JCsYRnsAoZAbyHMEk6qPxdOGDrYzkbA3CMCikTuE6wOm
0j69ZgENzpWR5aludQDu44oKZqgkdMKNm6Mvk//s2aUOTBYWabbSKe/I/+cEp1tWS7+9AAmaVwO+
KwmsZsNR4Ztb6OH4hCq0936o+bycwR0b+Wr1VA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4df1QYXbx3PmA5i1scwSy/ZAJgZ0wNtl21eeCeUI5h4IQD2UalJOUkc5a5UR/j7lX9ToyF2yFHzK
L4EoH+xXm54bGihfoaTvocQQsWhCDObbmBOtqB6WS1/bog7FNgoEObi/E19vJsjPSd6nCCdhglZ1
j33mJRkZed+lVziTR/s=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Rtu5N6w0tnewss9ZQUyM3gMzu1D5Ba/+qJO2rdGgk0QN5Nm+4TaVyiEXzVM5DP8z3mycaRD+z4HG
QXarW6RH4GHKahoLlSY8cryjSJRWS6D7/Z1joY2fgJb8apydMguGWjRZ/uW6R7BEimGxB3Xuon63
ZdpcvKZmoyvfg0kjAjor/DxtP3SP6DKxH3BeegGQKpP/+5EmCrAhhPu+NA21340wcbghotvyYusJ
ErSZhtj+1FLwV2sO7TUt1etBG8nf/yETDQPE7Q+zX+BzOktmY3tIKds/9qdyDt6Qb5WIxLMyaMa3
eyi0SGAuZdeDtK8Os3w2ajEZI+VjufruVqtCCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17760)
`protect data_block
yvvRtu+tA91Rtyv3I35O4K6BiUlBjs7LTFLRc9twWgYZkATXrSpXZut2NlvE8mcC7mB31ueT2vlU
P9hzhGYaJ5GcmScpsC1FKNndMfl3Ug9Pqiw49YT0Xp/AQWIr+q38Pu2DmkLm87YVBi0HN6JMSu6G
rwJt5qvXJYVA5oSnqcy27I93z0KCdBaCW4BhEaXbMLEY+qzcYsWxGhgjRzVfC2OhOSpdpDr2MKHw
1YDri1cTZAVy/b3L8VUTlyQx4YRG+qS3u0Cz3dOLm9nglzh9Pa9XJC4+Lnpli7w7vpvakaXaH9W9
I9Xs/9ShuVul4UrHUMsoz9V5jcPh1iHPT9m0ZTeLUdfod7NEEFDW47vWU8XjL6iEqBvA/DrJKrri
hjJ//n7fbl9gjxGZT+IKqHleRVz+dRiS/uTuRo22UsAcWrLoCdroE0x4MAJ9vC0vScZa86PQBj0m
ixJFhU15XHesAUmaWmkIVFZdUdZL6n63C2nZpQmpBX8G1td46ib/xrjcP1HPzbr1hPb30S/GA95D
4e3ICss1yPb8NZCwvzZHNKYRJlVJ6EOWwDxLeBOjWmUySMUcywo+toi8FWztPmB/Fzs/gyRSBxsb
FBe82kj2NTjDK0dD4XCcU8bGjVOKNJ3KoJmC+0UD0jihX5N1CdPg7+/bvmP+MCdk3ondXZKJzYI3
9YFYkr0RM2BhF57jZwHcHHmFJrakmG38Lap7lsdonuIO5mfOOuicr4JGW8Qijs1+c7VMc6LUwGDt
YKznnHTq75vwwVLxmtGYpW4RTIuqlZmOJwC34kp9oVx0+wFtUxMvQgXry9FwUwb2gSWRseSfbmMB
auDz+22lW+enEoOu3PzG3plNq4oQP2K2H++ZU7HNTNGSA6VpJWDQ1c8o+i7+XEkyIqt9DZHUxb+3
HlbwgxRkMYX88B7lb3GnNDLF2YzkJMgQjpyPi+t3N2MtquCFuqNuaKv0LoD6+mwRceg/hAylp3x1
m9DKQ0DcKuhctFlcx3aOGMXc0mzgjh9Umxn2Ng7JEliL6/L086w36Jar0AAtsKsXZ1NsDDBpiIeT
c9pWEQj9ud2144CtZKOT9/hr1wy8/jpi1lQaHanlWWtc/eb1aDpSY58hPbltVjUTyizUFFWsqQAC
PGoqDXF3N036pR2Ipsz0lKGQE6qHOZ9IQByoJkJfVJQFD7arWnGsW4G4I9tdTj8LBH1I0/XQKvur
lSNx9C6iPx8J8GemXPHqEIipG+GgoeMURYc7ft3GzrBdwbTFPm/qrxT/0vdju3tRDBl4JSzWO+do
z/s/CD6wNYNcDBCSDKcprRdML0+tkUYr6Jexl5rxIe2GBG2XGRgBDqc+wBSNJY7VVfutmSr3NjPK
RJK5NldZFn8fT/rjewbLV4flhMn1tgsE6HhNm8GuRS52PpzP+BK3fCtYvb1mnkFy+e3mwc3RgZ45
5iaZGmsBwnJwI9GcgMGoWSDkSaL/1PrI03WtUczFAidTPvIY08FA8CTdX8Bo/j1vK5yj8spVzrNq
2YNw08dzyQOA6p4yaEO8Raki3qlKk9oCGUe72zvHFj8EIo6DPYz7MTOBMZh7qLr1JDqBA+iyQCSU
UO9dElHR49OYArhLqejxnXEbJqi2McLLRKhJoiH7B/feWKz5mjNEjtWpHgiwx6VhyEKkL6UZ1Rib
ZtiEI9gtUbhZ6XzaYm3TiIRoYgTzxH0j8bAv7Zy61YnOi5ds35hrlF48AdxPXK/eT9RxLQ9JC4D+
xhLyqoQdstrt5DgaM3NxG2mKEJVH9uc9wj8j/rmn9YrBedhVek2F8Uvojvb9UP2S80Gz13xgD5DT
uHlDBG0pjratONtNE06BnMLwZRtD8fOAmitaJqr+uurpGUSmFSP1C9+FHTWgzBTdRwxLO8vYdEOz
WFiLspZhFCxJpRdUt6N09XI21qtC+0+ZgVoJcuL102pig2HCGw+mVSkibp2ZzBHApj3TyyQWeR0T
soE6qVGrU0cCA6w+mgSp/LpLjFALA+nFAG3lXPvfyzy3nWkgcWbCXiItZJY+SdblaE3tEF0j7zRy
QEv4a8Rg+L6tHbS4IhpoHW2u/3VbDszbEYb4sRKfYUA0hAwJaM8jOAxyu4YRtJsjn94Jek1Taiie
hp0Ndlnhy5vlx4q5I6i8Nc99UyR9uhRu8iqRtT7nCYuJSAzDby3Uxqh6srwmKPrb31KF5pRhTgEE
hoDR5pRAhvr+p6GEHRm1IAJTB/vA3Cmck+beIM8DaYRIdaZnzC9N04oH+sWVHExAUc9WW2ZHotPC
yowKFvokfu+7look6EHxqKtkI6qUIsFrQgy755fSnh7+GR8EVZFKqkRCDv0zQz3m3MIaUQ9GzxNA
nVZg02l+SgGZHXvy8wOZE4ONpWcUccgX9k8Mqf2VrJEhn7FTdwr/L68VLWlWyJ51gTID4qsEbmQR
eUcVhXwZ8J6/Jr+tfQkihSE/r9/FrMS9DtCeXZFSTXFkRXX3jwy08FYzVkX1AU3nfi5uob/pWe44
jJ4c+H4TgTK/YFd0U9+b9+hcQ/PKCmyuUWlZMD2jh2m6YaM0tRHT7pTE3k+5NorK0KIzBPhuhR0P
kwadh+BfDa9Ed/g8FI4r9aO+bzUYkbubz1m2BkiyrHNUN4b/jhDQyeuJYsvVZmik7vXZ6GcS1rnC
ZJpUE1bWR8FcYhqQoncmXGI126qn791BoIP3g9UyBSGDJ/hK/eFW6lylhaaJjjVsKepmxGzcVN1B
mCwVpKVdTSGBmK72htH5om7KKA2S1rC5U1UUj3MbiW7ZNwfDd0USkl8imBDLwgYFtoEE1ko8C7Jc
eUprl5A05bpIwcNw4M1zuvcSJzD1rtWdZQl2vo3uekE+ox++ptfYE1O4Xj/2TqSRnKWmvElAWcGk
d1P93oZ45PNjviXZ8GjPM3O0qWdvlgjvAq0xdzA6x0TysB9PpseLW+g8nB6svNvi0GhK/LLkeLYg
V+VOQradYifDOr8PNb0cqid1ncvsR8+c0tlZfcJr23pLfcE3Vqz5wPmHYoK484/vAUmQUEHiXjLv
MiKyjk8ywnYHQ/TOYWuO5OiF3b4XtDucLmEyRzxNB7rY1i7qaj6wGs15PP5RLOMaDOI9Kg6163IT
YHmjt12E1isvBtgqS4df/zN19hcUsAr+Hd+fpoCiaRD8qfZT7eD2F7aDUpS5tVOH7gVSyJWqzQ5q
Obv9Yhw7rja/O45RtfCLUeQNveIdOxbYJdxtkbtNUL4THMOaUooUKNDHf2XRJ/IU29P3yYsch8DL
w6GDueFKcmhtTaLLsoIw5tztfz1OnR/Ji8//265ufazAczEkWZEuwDJ820UjB8sYf6rqgnsGaFMq
k4/RqF2vivZ5ejxFZq4j5HxYIkrT0dvfR14iHiz1gFBjRkaPy0KB92AudlRi5GguJSj9i9apnV0C
9Q8mNjw2IhqKOYuyV9e6QbBpKJ96If+glayPM19wkoNu3wYrQpc35Fto6fYKFdY6dhE8nKPhcitV
/uItKlA/SbBd82Zd2+R5YPNcmQq0sWFXHgntGjncAGogKw7gdfoVMOM8623k3ZSxgx+hl1hERb55
2VAlad1Z2TVWotbB4SU6fYbYbkgvMzH5sJuCqbAAKfcoPFz1nWbbyWa08tpLEd7dFgSfxRMD6emG
vbRwvFQQjTUHayp8X4YhTp75/cn7s7BNav/nMANVwbzv+7PlcCBDE/FAkBmre/mWCARVoeNQi9yk
Lmy+/QFbBCSDmgH9dT+J0qyptUReayys26DpOx3zpnRbUVqoevpDLpdsoEIttEWQIhHlgFCwxqwE
aRk/jq630RhYJrspYYhMKJx7vBModJIEGer5px3GFiyOMr4+4I2Loz4N0yOCB4NxzVtMSM+DMFzb
Yqmp3TY7W03MSy4BUlptWvy4cfrCDCrea8duJ43frMTKFTfbW+IerIgRfu6o1EW2xXm1cTpBK1C5
GDw5N3ENOo9k6+Og7Rv6BqrZrvmt4KofAZpoRQwtrvIUEswUfZzexMH0dWDua0IDEUztjkju9U3k
MYVajimuyW6IXCYU0qQCvsz9sBM2LLZ1x1Vup7fB1Ec5aPwU/UHatOkTm3aX0ZLYdmaCrVM88w9G
XHeo1x2sSQwb3bclHeYGqJ5KFtGY8NkrjA2kOqD+X2jo651hd0o8X/ii6dRA1MaQa3XRL48KOtEM
HH0PUmnhNz19o5YiXS60R4NMyF8DBJ2arUQqgtrBdHpYd+zsNwOO4FJe/HVkB0g9fp75mEMH5PiJ
iCp8PJo1jsqW1yWtRGUFGwq3z88uUmySC3W8F4jZcCA/IVM3H1z/nL/Xi6GkPU3ho614p2M5bRq2
14TEYUDIUMMz5OS3VFeKp3NLgKmCpVj7tbmiZi9T8Yde5BbWfETD2YjKPY4NPYiw4TNz+908oHc2
yTbewFueWvL/NaEUrh1xMwQw0DRkd8xsxovrukJPMeMMIOpJVuHAqxeQFIhjwyO05shLRO+8ICOY
lVC8RDu4KIeHaBIdj78ETsgHAau5157cMpNdCv1z6u/eAEhsPNaTpoYf5z4Ulz5+vbrw+Ig6ywPW
AC3chkAwdqF9uooKaqUaS0uaMYKHDaK2y5UfVCBUcfko4mCk+jjZbqPR4oE/RY4mRKF+S5KVRb51
goeafsPpARmOwOZcbpLNMXGonqOUJEFV7nFBn0sn+mMycGAzE+JXd2B03sI8g6vqICD4805s8/Q7
Q9RvYQCBXt2A6pU5gu9eZBujlJ5yteDEmqSPNTNLHzUtnYMoAcOjjRN+mnEfti3CP2YaqZYc7AEK
EmGhccCK28g3Iq3fyEIwqSG5ZMQqTqoqd2RXD5hdEa8/QoSw8h+tBDysQ5iCskiecYnVoVm2sJ9g
EiFptSQHJIy0hyW5bqu4IBzo173gYuxltoA/x0vJsCyFYs77QhbyJAFsJLmGHqO3cT9lndY5RmIe
G2IsYZVzwYIn/hCH0vy7GSobNYDvEMIvGBaU5p1UTsf1zLoaBwNW5il64Rmt8mWVqr6Q4Cv07zk7
YKXZHTXhEeAgsPcWekKsDPhosTQ1OG/Lbmqe6Xtt932gr1mKpZC9HDG0zXIrXY+2oSE8WilO1BRy
J88nrrr7Yu0oYnF4wZWHuAWIyjgLKyWWX4IP/WRaze8T+DWjRzYC+x719Lw3Own8W4ws2iTfKhys
/AoSQctmniBEUleebvUzkP/54oUfgrmlSFnT+LQI1wpo2T+VfQtutqXZD+Q9onWKVVV4HeEbkZlD
NiZEFqgI7BCHMNKvyQsr+gN3d1+ljxpDWwjLTifh1kNDK1FTX628L7Esv/ze15vf2ojo/9c1/gl/
t1SV+B85OJEVM2ghrmoVc/L4ECZPJK0ZQo5F/4K6TFqIGKCvu6JvWCTXCXXQuvIJWVCf3yQ+xB28
CnIRjnpjYhPYNojhQfb5Zv+GZ7LFqZZ1/o78veE9yuWl0lUlNLkf7AciAMp2qc67QqLSzbmp+IIZ
GRPGcMLDzgqZMu5UoNLRtDcIK4IdO68RfVU+DfGj7azU8UasdLC7EXFxENSmQ/djh/0I4Ci41R+q
wsa+kmx3eYs+rFXPF/gpMof9+m7gcNIlaKRiKrmGwaefZwbiLS2b5ZrIZ6dIXfBst6s3VP1CYaaa
+z49NTCU0GqV80EBrXnRQ63CMSRECEHoQlN/WGzyaldjxjHPYO9Hmx4A4l37hy0X4CBEgwcgcLmn
2IaYATXcAYJj2x+86KLB5ybH7SyK4Ew14BYjahhIhbE/HpiaKw6srEVCnQJsybU/L8kpmLrJFJJB
A7L0H6rsyqypQ0Gw1vYRNT/Iq1SfeeCbJucKyPaC8FIIMxhLscoBs871BAGV6PnoCQwWlPdh7wt/
cV+rFe76p7fOp7y/iWBGEIZ3hi+nWA/1wg/Gwy2n5z+TL5zSsOLvSN/UaFnaFFlJfzsshhbbzRjm
u8HmR4iISYlZfg+PuCGg4qWDzTm+W3rHe0IKKFdTl4GXGM1/EpTtOAqbIDIWKEIZkJ5l8b15nkSy
kXA7m+xG+B2kCr6obeLcnH/Kll+3TvkRO20Bb17nVNUb9o9OAtuAZf0dsN0dkMWVbDBmARX5RrB8
Xaso0jhmy2GD0839FOGPRmjq0itlZIHy9gyGxFuelbdXGBP7YJlreCebt5nS69xLW/ntBMeaobHB
+fuRF9ZeLz6NIAjircenBW7v07uWGziq8CV4rmH/bVbBQVpgNLXkN8+irSvzIih6+uQU+4qnhkGf
6DPM1CIN42m9ynyzhboG0MwLmsmxfHNu6W7pdDbuQK0nD+bziOLzzqrXLBnyPXGnwpO2QuvUEpHz
JbvGAC0fH3+ZHVgO2K75xWmD0ckLOS8k2Z5yXiDsc+mex5g46t0h1hrH4Yyvs+xHhn22sZ5vmAd9
z+TAxX31wRoiRQvb/b9h8k+DfNRbYFTRb2ARM5f0wglZ2CBCHU3UDca46UnCcX0s2i8dCJiik+U8
1YIMvzM1YeyL3p4mMj0N+JIFkUtiWw2Iimbj4Zp6ofh5N27FA2Lw2SNpuIQppGII0um+Cd8fl8LJ
wmvWzSxiUir0Ax11Yq2EPE4jm3nKtv2sY0E6lx8WJYJydjXzqOwe7I/q8cblI4Vw7LJj+vuX/Vac
5mEUxAfQSPmHwmPnz7dWxElLo7zN511DK5ZEC8GBtiK9/m3RoIfI1+3Csl/GLaL5uWLV5jg3nmav
Y0x1hldBRI4gGM/8vCOKB1q8BY8TbeB6wETtrgJDpKK2w6lzrgVWA5wHTPjCuFeJZQKurXZeL80g
JJpIX8UxxYd+U6Gg7ji8gqW9cjciYoznCFRSJAcwiV6/RLQ7TMkMWTU2UPbgRRUhP5AJaTlsHLBG
kDpRv5sUys85ONbc5+pksLhtG+6Vd/mWvnomEBms1/e+jX8+Af6n98WPo67PSdCntlBBB0GpSw77
A58uptTtJh3ZnWGQRMSuQLMvad/WJZKosSXA1e4gAi8brVgIYmbIc2kzpFVAw8CT8ZJVQt0dh7lh
8tVc9ifnMjHMk7eBB/kSfTmYqiH66g/FPPIMThz2zJc8uB+JcA65L3cTruK5TAIZfFjQsRhDD+jo
+IQSPEMe5sSQGn6lLvuEYseLQbSEswNwE1xM0mWOmQTgipmdzDR1ApQU7CJ3glXHI7CVSZ+Ptc0x
tMhQKU+3nMUBMdbrbWczDZr8+LtuVq79gy6RjWSEvDiU8k/C2jfU7gvAAhYeQmEWA2ZDfrBZGMUe
ctwS4RKrBsgrdotouRos6i7rnUYet3BfSROrkb0kSdMZRGxAyAEEU/HXaAAC8PBph61GdBPOjY2o
ucgy4/5j59ePvr2AHV13YPvzcUThetgzbOE/iQtfdAyChyoVx/t7MUXlzDXK9YyFeO5akcWlv5cV
/tZmdn+0Ip2LqVVRXFEBSoKdQdXJdPtlxjfAelCI04ov4YoJ58o+t0nhwgO7bkbIx87oHNgrzQ2M
F9Nx7WUW7kGIwr83dm82aDD3MxmSYxoppKine4XFBSQuB5OgrdtAHhsoSTFIgdLrqVtjPempXbGk
sAGCyeTTFU5G+XjRzr/5F6bDtFizNprxJBKDaht1ZHz7ETvgFDqUE1wXMVV/4EQdWo3mWO3IzFHy
MHtIRlXUch3GQNXGHB3VG9FfABO63ISUv+i8letcphRuJGaIqd6D140yb1j9b65V/pllsmcXjxZI
Ah43oD+OViZ853FMzqnn1m6QUPSsMZIRyqrAz1NPtluN+CJrw1FCZVpiTakwpdxU24wYPLdzkJVt
MpfNjTp4CfPgAm7JSZ8uNwQriV6W+lMhO/nOlWDmWdpkvsTuaEmfMCDUgnSLOZS+lGvmuwQqc4c7
zpaP6+TmfafMbg199BGBGKHnAzZYORNMzqGduqQH2rfIjXYsYhgEvrviZ02MrjLaQZP6+Ut5Alf8
E/kL+HVFFRph1szoSkmJ7EBXybrGUR5qMCQirKzjN+9O+mZGlpjLRjEm9OvwEI2YBAdnbEy2PUIS
EppQU9iHilUApIhfes6nYf+wBw90smvQ+ggytyPZpyUuHI4qtFg7oOfeQJsHmMUTERb3j27kJedP
2tYr9qiiRWvUkdwJ4KJwqWf4pQgGognpwYEamf+1nPv2wTMMQK8Xx/yjdn10Y0/KWTAYXLQMmYjz
1frZ7sNr9m2G1bncTeAGzAAYatbj5nvolqrKxgG3z0xhGVUVc40Ki2Nepm+7jD8G0IY0ml5LLddn
YbZpN/8M3Qhx3Xq5oGiH/2TnC8sMX0iYn2UCyLxrWczitSRdquyZOivyQrbiaox+Q14RjH2RZNd5
aQF0j+++AlFnkxA005oCTlPjkpfMTIc4RxeeLQJ/tOK503oFkgsrCogo+yF12lnKy6igucSzbMPn
3Wor45sypUNSbvvkuBCYT1dqOqZXmmu2OwrJxxib2arzDMD+Od3/2YCFIL50cnXvoIjhEB0DXR9K
/K7a88aV7qbJ4DHBzJ3f0XIdiFQ8SQgz7J1rbVBgheu6FymoZephdjJLqZb90iDDQWVJmojtbzXg
gFOUIz5M7rwsn1szvg6OQvvyk2BO7F4pzU/gosxylIy+ZgksSmVFg/qaV20rZ1k+aSKwrFaoQyeZ
RFL+1rHpj+IbGKJ0T6azxeZPrSBdULXO4GIJdvr3Qb7m1uZp95FUpJBDu9qVsBeW+e88fCT6V8gX
VS6NTuR49358rzHdu4P84iHiJvQ86U9hTj3lb3jjwQAZN8p0kHLIhJ/OK3HNXw+RTjLj3vFhUR/i
IRh025GWPgCvLKW/Fcjs6l17Yf4iBubssKiYf8wlCs3fcp9iubVKMP7pRHwefSdGrCymu6kYmLgw
mqeCa1xHRtdyJWo9Qe40/RZF/z5wrG4kAL6/QY4JsNK5IuaqdL11AZL2SCSWi+If9d6xMChOcgdO
Kz8rL/ul1zVN4v9usZdnQoWuT37LkO/XTV67Fotcg6wt/2SklpnESLjZ8scuc4uMPNBaKqJxjusu
l1vSBAc0RfX+94qdKAB1kZkl5L/0wR4MeVpy7u7MCHssLTOzpzCO9upNisBXiFFPDC00CfVouYZN
XXF0RkU9ILKEeChv27SW6Gi7Qy+jku7OC4OkwVTtOeSe3uN21fa0MxUAVDqDcSYih33eUdQ2UgQt
L6AkF4QraqjCQmkNLaNY6/FADaaIph2sC0y2v4R6EliBhBDUC/ueMaaLEicWDYdky6CenbfyuZOC
Uvu3Y/IwIV5G1ioj22TVv+/LM2NMXlM3efeBXVFLlpk0glMoySXNMXgPIwpcUbWKr9MvEuUqvHfU
Ua+EPFCKPWY+MPtNhxODgEaf5SD42ilmAXixVxbfQgZT8KDy5ESHSevUnG4beDCiUOx2OxSZYEd2
WecJ3ZL6564z/G4fc7Om0ZIOU9ng5EgK5ufct/8wDhJxhrKfWKF8oGMAz/NIeDg+KDpnnOd9TWC8
m1C/nAlPRFVJESuKzp85N/iFta4ERlbMXC3KbBhJx19efD9AzC6BaiST96FqCaEQ0gbAZg+5M0vd
sd4uARkYKVZ+saEmK10NttpOf8+fMTy+o11z0fGYxK7evc99er/Gbpf39qG9yEfmAEVRfphmZPIn
SQf7u15eABhrE65ulYC9cW/1kD9cckhW3Ca6Fmggjt0dr5f0xyY9FGPQPcKlXF41lN5BHyQxsQIA
iGo9RSECpzORa/a8M6ZNFsEFb1RNk7PIJWUUTwA3yGJ86kp56QxDSwHJ3pphqBtvncSbkJA4qxYe
VYFrqoPM2y9CnuLtBx77VYq0P4lNlDZj2jk3mHJrjUoyGQJcNWMrbXeusyvrDBumKKKJuoCp8Ji0
/RMJ+8HFg8+R4uKqYvpIJg8NyYQ8vYA5vtYccRW0jvZP/i0U6PWDFr9Jttd7mvkTVOZWVQzQwIa1
CX0sZXUqWjeUdWRk0PgpbprIfHUzRGF/71Zzu1yRW2GCnx767EQ5qKMpDIk0GPjYaqO4xoSoi9aM
1yz/MP17scsZFRtDTEX3mlGXuzvOXzoZuF1pv+cx/HZyvxTWVigsZvXDBZjLh/wgy0creA+fBV1k
8fkV6zAuCk5dk5WqKFfYd+1UeCPMcZKIBp4CT4CSOy97C7PdZOfTtjBE2N1HOoaQ2ZxOQQfwlT7T
fBNkY0FZvjuckL0I+G/gCuS39PwVULFYbFIzpXBM1Nbej2d5BRC9Qd2AZu9sxMPtcZKUu95Tnwhz
RLTAtWmI3jpVmutYnGnpM5mKwhhOdMO3VOC5v3YpF592DzT+6/6Acs5ks+nnzpA1Us36PVKcWGkE
M1WjUqhQAuy5AFtL3rF2Roudc62UHxBXUcrRUznmTU0m6HWy5ij6umKW8aSGQEAuTFkgHG+/QK3t
lkny9IyYFmqLI8pYvOJTBRa/mUHj/dj/6NbKzslOo2YhiygO1nVPUAcgCQY4cgBaV1HZAFPnSrue
xDDcyoDCQ9XAq7HtK2PK5zi3RkeZ2APBYNWexQi62G+cTV00wfk/mJEXllv7M1McZl6EYNB7w7Wy
NSFsKlLu8YEu9N+Kz6RKVjxTNxRK8PL4e5PF+lnFbOzA7pjA2WZ8s4rN/GBsDQxj+iRTW9eFFwkI
55pwh0HyA5SIW3FjpJUf7cIrlGZ4oEXT7+1t1T2BK+cZECsvU3yQPWI0wujjI3BHqX2Avcr6Gfjj
Zt/BOCeLm3WPYbVnr5JtETvK2x7GxSyH+9LMO852zV25Cd+48P/c6S2Kw0ca728Ny1Y6KGbL3qlP
4EvN/TZ7etw5UKea706IUXwIQVwpP5jQ938y0oHDYwffAWQlBszHIVreDFPDhRH7grduFfXwkAZq
Xg1+sBIztw+hxqlMs53QCz42G+g9RWycycylepEsvcSk9fVNm6VmgeZfgi6X66giRnNJpU2PIBAF
TmbPAcrMrGqiw6Igp/NT9dLv+HdaubjRbMktYivcwKhtfvRJxOMuhYot4wWlUUavaDQbJmW24VmJ
ZwCVPPi6rQ4Nhst/OnX8HNiq2U/gTHWXorogGqfyr8Y6nwQ1i/rMdmxoA7b/GE1m9P5/B6xamFQg
EwXo+CxJrOCPsGlEdrtI/EomayDvxVj5CfvkkF3AfbS1sQsfyGGG1tUvsuzyG6HbCWTS0DgHLYKw
mLw/kac2HudY+pRGugwjN7CsZhMmmjhzcrMq0IOLuASVzEQ07NRtu7qYo3gXq8qnNgGi3DQKDYrw
SYfT6Pwt/XDOLV/1Nwm7lrkBfprfCHgW0qbPVabJczWZCD+LcxtBQw3gU2094NvU7pb7yPhlgrq0
cS5wrnWHRgkSVTP2nTdECUOf2uvdv6UAYuKZB+WHxfuNgMuJy+NNx5KfDuofgKn+lYGw6REYH3Ka
ZOfYztF8bAdIPEvwSawpzhGQAiNBWeC79fEj8BBPy695w6r/wK/tqaFZeWkyTtf0I3GsKFAFjoZf
KzKY+NxdAAJi0qPk4lVk75CJ8kptfpPfFywJQmfyBb975TcM5vpsuS0OLQ7PPrjlQ3gHCKvA+H4n
QPQpKtQRoRv3axSt2d5bX+nHX7sDe0XLK+YohWnf6W2r8ED9onbhdOXu/KX2OHKoCbv/dCpO3JIs
yPgJIlcsES6Z7VNPf7AG2iCOhM8IJc2rkfWNF05kCosrhh9zj72ovE8RIohjbE6NHLiuUlA8oede
e6MJsIbj7L6BcoK50YtZJ47mkqQ53XN8aAc4J/rI7owAq6S9g50tYefm3L0nPbuCGWHERzd2gjBj
eixz+xrcNM7tnJIQKf3BHG5GEXQzMr8loXRSFArDmZxS3+X0oRJlIt5ZBx6wPaJLw/47C403FaVO
IQ7rKIj1J78aFfPu3+RUWyAxXdSUla9IOrNugivXxl+/pixnEdfqFhdGh7sINrMDr3Gva7MydLld
aT6Xxy2ZXoCIrn3QUJYKAx8iSWuYEwP4DqSnDEcIzqyptarJmsEalMCp9GrYMqhCwNqKhm7QFRVH
EJZYkgW+8UMhys0ogbrtFGbOrQzAPtBJbeUFIniW3mJQMXc79i1yiE21ixQ8ixak+mrYSNslA3e6
hUZFTZJoh5xpuHQYY1nBk5twjasanafpLNUSwBeNbZ44LL0/WMXxVmEI+OffB5P3t3OhAtcLuUmq
dmfqUu5wfet7GcTzjZMame10OMV+omk6zhW4JKpGLlaOc5wx6/zoGhGWuaT+cWFv7j06y/IK1Ge5
VwYmkjNekZd73ikRPgWbiiTGW9uE4WwlB6bawr+FtFUk26pt7kv3iGZfcaexkYk3gFuoCjMatcxm
5iJBYNcSz8AWR2X2L+XKSxtSf0hQgxgqoTL2UfsFHmKChrS4gCUThdVlzTQXUx4eyHaIJJH9DnFE
M5L/7tl89MeROUUOeAtes3QIlHeFFHBL/Ji3cfap8ryGMN1/gtgWdRFkXnoX+G6hQhXwma8qXikA
LWFDlKPRFEnz45o+6OCrGzLwe/otDBFLGfQ+GWVpN0kV/uZQ75Sf0e/PsUXpFnaLewiSKank6gwi
8yF+WH1FQE9YQ18xUl4fwH8mizCAxcpFYsA0t+RbSUT3n/4OMU5Qp9o7PN7lBGRIO5p6cMtXRnXC
JfW5MAwmEbuYLebmtXFTuJDEJn0GyquYWPiwpRZnv1ziMZpHifvHl8+OztIxJd2mYoB0qILovXrv
p+sSoT6d+Qt2nOaFyPi/m6CB3U6EZTDb/lY9CEtizEw/HAA/6VwkE8uIX7K7vI/hr2H0tduoiiNC
Z7Qlv61NGDw+Zsk5lf/EB3d4KiMTGGR+U3OwHtOnm6VYC8rcu1iaHeniGKq68Pd4RNabdW0SEWBG
SCsEB5twlwDDXXKD7ZjGPdrzFL4xeUQOh7FvLbwmC9sr/yhddMvrFkA2V9wW905QTisuA8OW3JSB
AUh4iRU5p3eIXnK4bV5DGLg5qrBMXKp7ITgTUsrz1GkN0djgyFC0XYoOcjI7B/yHlOip+3I0y4mv
lvXPbxrefN6gyKaXEaeKqc8lkTrapgWmcul9IqE2dc62oipP4yfF9dyU9mxlW10geK1g24KEyzGo
BeRphtKG4Qmo+nfR7liloRHvowONq++DWCDl7U64lFtPGM8DVJ8L3f2O4dZ63W280QNqOHfM+D3v
oYV1BCKRuIDzGPh+aSQpVALS7SpCpa9vz5n7NadTJvhdFlHr4KfuJX3Dh2oImi+n71N0Qn84euc1
fOD4vRyV2dyrbvpf8ZyzqYuhxBpx4gleNeoUIVPfagb2FoQQ+bskrJ9Fzaop3uYeyYjVHHz9Hn/v
kD96iS4c3YZAm2tkHGVHg07+rB7CjCZASOlDUuBZBYy/Vf49Oo6ZIbyPX6zKW1HIZX6TCXgL2RMD
Z18i6bS4dVWdamjHoVM2FEWy0zWmP48ZzqIofGQ35eZ/S/W7DX9ElshVXWSoz2DnttgcYeQP85Uy
g9m+ziCUZIcadRW964AoRUA3+eqQFMd4s3bDuqBW3XcuFpHSRPXh6t0Fs16Zxakn48FFt53gPuPn
kWccmrUbXLvLcqhA8NtpSsiryUclKgessi+7wqGZwaOZ/56iVBpZqOJwABqb37gDS4naRX5Lhm3s
m3HaTaYcXMsCHqn0auTQIir/uX4q5UPZFQ8Bz8UC3UKxfj5ULvWsnpZTirNjNzizmAgQT8RVbgzU
2G5ppcdSvbuZsNpQGRd4Pb6lyI9TgsK+1nbLlHGhemrdiL/34MiuObwmSLc73QRRBxNgFET6e1Lv
o6xWN/l6TErNc+6EiEwrxgHsEDYFHeG6qnW1ueS9Lpmo4/z7e+6wy6Tl/b5WouFHRr5e9BLEbuxz
42BX4dBB1w/PfHqyvQ9VWKQ2jLS19zH4agGu55yMenuP9MgLtErIMJT+Bl4ELPGwB6MlUUqTZB3t
VQC2OppjbtSjETZroDDv09xkwKjiHqEFViOwEy3sF9EdAetnX005D6kuc/K3fTbQi+m6fMRiKN2Z
BiUYhf8XENvED3ZMQxboABD11DmJ1e9Fs74DiyxWCij5drQwOkqqstt1vqKAB5y7Yfz7BEDaiFt4
N/hwftM3GyDIag16EDHX9KUEehn7+WAQVjm8M9q3X05bEsi+YJzDYvQ1YUMmCywjgkrU+we6Zlfj
jwHfaDlARpdR7SkNfEHejmsi+v6oKmporsGFi/PV6Zto0tsGqVmsM4rG7ACZ9Rr67LZv2ZBYmau9
YMgEVa7MgE7o+XRH98+6g76U+vPo8sDSXBzjLxrUWj7LbaLAwHwCiaHAk2NE6S11a38XlxU9q4Rc
V/ZeXX8H7FNqwpWafLtSUSFGjVEl2UPuR+LqiFTtg5pDbXTI3RUZ/1FTQXdKgs8mgkiZobQpzFE/
rrjhpfu5U2VFgUt175KUgZwXZkH/mSNkaexiOIwbfcsZBAy/tKw0ZMHpRgmxVxs6aDNEnWMppYML
mirp99KtxeiB4YkVvhoCIgRH9rd9f8SjF4hpmqeG33F+I/8aGa/B9TDn9mIOB0MkA9G27OhNWHti
BhiDpachcuiKHNRXtROW2tZ6QSKltulLhEE2tKS5ySwwxUggM23fjcafEriJsOg/75JPoP0f7KSD
GKya9azUZuLQNLPDToOlCvYyOgxC7DwAJSzAineFxmxudrjNaala4ME5f7ber08k0H7a98KpnWhr
7Wj2/ZJ+vEdRg5LF5JobYzKvmpaM7hGgOO0Y0TDtIOO7HUt3HbEwZQnXW67gaNwbS1SMvRGswaYx
K6wkNU8q8NKtgBuc+BLolYfLBZRJcyR4yNDpU2ZjHuWIT4ts/OFFXInD84SDkSXjHApALHfZxsnt
cTfPbSH8fDmCJm8Vuoqw1xgU6RGcrAVPTlI/Bq6t7tCPO+YaS7Zc7owdZvEsNMbqoZsmDCFe8doV
8cVthfoNVR0f3SFwHIhWyLqcudCO3w5Kbmclzjof/qugz7XI3W4up1D76MJKqi3dcnruoFlabFxm
tSwx3GSlL+5B2O2YixhTq2xSfw1sszftRCihJ0NMSoRqkcjUCZWV/isTBo0MmbQfNmdasTOjZ7ew
2BGPXSHQT6V3s6XY14QEqIGMHPF5erZNNQZhY8yMaHagYfd2U+nuwBd7aS4EyGQFpNTw3QcKE37V
hGX17EZiG8Wq6MY/44BXOfTCtCeKo/byhuif/pVMsu+ca4R5zGuY3CiVWYEsPvzxF/qKifpxZi51
XRmtFk0dvxCb9LZijwdOxnyH8ZiWDHs7mJnDVpcWUMPZU8IvqumksK95mbWFPl5LqmMFM0jEs8PD
mTfV2GTjPFDNIyUlS5wgr5mAkFV9aGhFTJyxgym8HJTFTPnH5yHrrcc8JJLtN4hU1di3Xn1fE3uT
opoRvS0bdUapON9OlwVhd26jM7wCZBYB6trMJ8Mp76myBkkv39NINwvcNz0C9PjTC2KxxPuukWtR
w/yhSCjv3HZENtmeUszZgrIUGEER9oAiD+owYoWYlewK0ILXabNAqrhmEBqBHrr9oqgbcYRDzuYy
tXp0TFqhsCtk673OJdQGB6Oio70EYcvfK2+/+lQbm8RY3MMrGTIdFT56B/KY7jNhS0GK2TQxwqhs
TRZFKV/ZJk4siqHTytH15d/JDe5gR0ZT6YLiWctRZ0o7rDFAuWGOts2T5plZkYkKlicuij/brRUE
VoPwjXc21Asul2nGZ4oqWITvNNvqsSj3pZcib/NkEb/ywxjqeutPrWHdY2z9bYYV0afl6iN+OJPF
mRYM7kLjlkifzhHkjMHeNI/3PFm0mygSZsjtHDrFRcYjNY27pFqwHt2ydv+Y8I0N1SDHvn9BLNJu
oFVKeuo90KYeeut8r9DrRTYqFOonG2OEQDDLAFRufZ3qQCoZzCVAz2808ZTxpmyZlUrqqRB5eNoR
fjg1JW2zKpsRpYXTmNQeMRdldk+Feri5oq9cGD5YRVbI8qXrgCFVgnHaSb6bgNKjoxu7ljGDhDlA
fyljqWnwjpwLnJrnLEEPxCA0T5/et2QButOgW3nnwmS1l46RTyIuJvDC37QKPJAoZiXW3NONxQ4S
VMkIxUni4WFNp61+I8ALmhKWYBMnSF2olRUJgjx/5EoFbnaRnuG71h4SLeOPIDGWQZc0jBwrQoy/
p39/L/g1wLZ3FqNDV7qggQZ0GMY0PqS78funhvJ8e59DeuguR3c8Qw2C0tcThu571K4wpX/OFbnY
beeizjT0zdkHhRSex+8gBUGhTbaSXFA+qwXR9xCY+C7zYRTKO8Nx+cPPqtw9pP9PxBswmjqhEKt6
3Ck/ADyCLZdGREp/A68XVGVvHb/JvfOg35vhDTnY5YS2yaSxtOlTrfweIjcpHNm/KYIfyfc8tE37
vQgFgsHKTN1WfK5wTNKf7aRiY0HC8102JHI+A45viX2RWjDbdLJq2Y7F5ppx0BUGXajkekHFHtTP
zGH4mWnc+ZM9cxpDbZHg9CWY03g1SIePCaPv+IQWravG0Y5/FjoT60o3H5FyFBudgMVZ3cp8VzJe
LvD1NXLx34aC55OogymYf2wimfHqDswutWmnj+tuNMEDOInqQNq9UcHM/OyxxtX8wTTT/NRUFeVm
VeKtfofxOPU4GgEr7q/dgpmmyUwpJdTmUIWgEo/EFBgHOpfX6wnVmKNZLK/35u6h5zONTzL/dQna
H6zFQ6I+cQKT5ug+al7l3k03OO7iBB2zXBSdPjOWpTtDodnsbHMw86WcpUsjoqFkiDJh0K9pAiTs
yu0YtLXYhpLRc8vLx+nlNPLnBlewheD6Rsel2vUITR+Y0R+LTIVcFizL3RkCWpgT8Mv7GFBus0bs
tXa7x74NoVvDOv16dK5Bp6co4kem5MjsBMqulNnb5qAiSRSAHjJVEcbgiN/ejphUzKhhnQ2rLlmR
J0srKz5SDkt9GoLIIQYs5LiQz7IybWCgpgj6AsAgzJv8o1wGzGOJFcuutKhU3byY8gX4mvT1mcoL
+oV0fltqMUZ5+7fYGYXRzx+IoKYTulFlekV7KaIy6pn9anlT85vVRhfq3tNZZRGuUALVSiHKp1Bv
hSH5jlo6taMLCDODPF39Tqvftq6OemOjXklUiPQyYpE3hA7qrG4TTmxYZzDSMPUrCpTcgg6vjYA+
icfYFMU1pgr4fLmYJ0fROfPHuGJh8j+aeRnjdDL1S9T5mRS4VQFv2nBpMet9lpa4++KbevKGFfwJ
BO0QF4h8xYmLMoxmJE4LfilYtw9dGxV5baelDnfq58HheZD2ds1QdE7sNtEpXV6y/daqe+F0IrwO
EggItvtulBViDAFHzzEs4Ors+9e3U7TiRkh+FQouUA4zwFshY6xGA6Dbnol3ZBzdaBUiUM72DESu
4f8i55WEiA1ksZPV3YoWd/4fFxoy40yp+YAThVsC3PUgYwIJd+HeGGy4QmzfwbeK+mDAR9fhkgPx
nzDL3LV2Gv3HmCCLPBRF3HWk89YHpBOvD6r+uOVfqkM48561HfV7l3A6apzVHxEOEh1IyTyiN4f6
3KVzCDqCvavPKeaSnkFs20XLbL+sYELy1lix4/B4BOvvSBa6muSI5EwkO9IYHRp4SldDU/BoT6Cf
qRS1nv1bScZ42MttKPlYo5C+D45g6wpNReoA61TtaIEPBZNYtLw4TsZyYTF8v5ZzdClRynhRzcCS
TDxMcqXxYDSNoJqUrB7zcYe4AU3uO+Tj6wXoA39LLbsKtK1EY16dK5eicLPwSoFRhW+yHzcF2R0r
WPJGyuHI7ddZdu81doAYgdtje29f2PoQ7UdSTUx5TaBtDIJ3Rj9hzUirGokvUqbl7/aQny41+3XL
F7yI+f+1hfB0KztcysNAoH/Ef6mEeMnfNIZ1MWfgKXi2mHySkygQ6NWZ6vvA1E4qyMJXH6Ff48/K
gOLCxf9q2hiWqZQnp6Xn75CfUcw3BVuhzDPyLdr0RuUnInmBo6zzYXmuhUgWD3UZOwbOLMbQde1E
4+ppigWbA6D8yjjDH5d///Ez3Ge5UANdGKtn5+zwt6sVz/UnNbLaIxHavGC/XYYHjVzK8UBa1goj
rRjxZYq+/vP9jTUVM/We05Tuu6Vhr8Xqgqbs4LxdLvSY5ZRtfkiZ4ZCcUX6PAd4EH3/mr2iiXXwk
MaHxtETB5c92jL0MYVhAngHcoQp4PXcVgMM53uyhUPz7f2ILQV2YDlsJucEYfDq13cpM0FlEQd0h
5mhrSC7d1cT9pzwN/S9h7Qh/HzA8ELwUmuPuJDo2/TpqVz3rFrdQd6zrjucPEC8bNXyMJ4KKbI8D
jSOb8qPFWrNmF54vmxSvOh/OuuWoD9f3nVoFgkV+u9aHOriGCvKVf9fo+9RKQjPtDXcFXUfhU3Cv
MzmWBqGndqHMPSFCJwZft7uzO4LOPPH0VfFoxWhRynQwCPBocMx6x0YUJV+M3EFU6Vu7E3kJrFsl
y1fn4yO53dC25b8g4zcCCiBPZyfjr/dEPpI56AfsYVso/JiXvsCGk4Q44hgxk7E2o05UqQCMycBS
ygQjxTdflOik9YO+XOKbMzwwOKB9IrJf7iEl2lQF2K+TkGRUH4+zgS1JhcVqHPMQR+DJxVpWfM0M
H47wPKt6giCxmkkimy+FeHTdZ6hz+24lzsFu3UbXHAwWbAtim+kz7tWoUwDCuWtRez90LMVibV03
s9OTE0S01WDnqkPCfv23N97xtDZeKpUclYjzfg8WN4IphB+xKA760It6EE+vAg6sslhPeEtILCY4
Uo32QdRhD4sEjjub54P8JzSNxRxNbgJXU+8ynehszPSEyuxl5dDi1AscV5lkhXQ99VE3kbMI8ilh
QVUy1qYXE9K5fiRAV0MgOjL6GGRYoTf4n43A3FTs90xm2IHT/tG6dfy45aY7VCkDyOLAsNg6qbjb
S+am1g2mbZSI1nM9RhmFc/sBTe78Kgm7HWfCi6EV9WsWjqKGa5AaRsASsm7bd1npnUKXCxM53zTI
77Gkmb968Gfj1eaXjJQdf892eoN9RwJPsCC18O81xXkHoHW9rpUzV/NkTfGJToNKY6n8O/U/gp3y
AG4NmQb+ohRjIbQrMorHExbrqsFGL4eC3yc69mOV+v1CTYsqda7U3Kustm/djGTSpFqDUaNUmNv7
s59H+WB4s7H0P4v0ac2cjyGb2JiekKYXjqytCQsMiVJwOtyNM7tOjPKEr5DFyVazHv2pRLOhaGVG
87WLyoRqDpuHLeZLjrkoa33bl1FYrCa3J6+jJ7/V3xNnIZQChJxZvKwYAjZaE4fMV2ZZJnThqFaV
jzThXMsUKhts7V+pxPK+9zyGMAfbJb+gqTodEbZFGJ3uAmuFe4/D7u5r4ULee1EtBh9bcw2j+Ola
cNtHZu9ufBxtKXSETdazieWpvDhS+w9bsCl/1kwyTaNvigZTEXWAX7zN8t/Lv3wG6d57wx/BxB+E
F8OAUdaEA/l/kXOG0XbxRG2wQEbzuLgDFSmrE62VEjJinXmf1q7lMpmlsJOGH0t6Vpx6OC8xz8e0
9F6q/ODk0dxRYn1TlLWz5oHLnk5CLNiWA8DqRrYx16q9uzU6zk/7a2dB6MGsTzhiIU00omSXkLY3
uhJSd6oKTQspc9w3uPCrB095lhsz+vGhD4iM4/CS2HsS0zXvKKDnVX6r6sYwhAYS1txJn8cHejTS
33a3FzrLh/Lr8tihbnmzdHQJtk+sq7tZb72rWrEbk48sbF9yJahsTCRqNmxxIiHoM81CkKoI+Lxh
cfc0D5Yp/MomiNvkLGAQL9gJNP3W0OyucO7MynZvbq3xjQW7UGuTkM+U7elqqbUSHoc+YvoRMbS0
Wra3OUa9vgiPvfWOPUXkCzQ+GZz5oh+zUdgV9KFSEg78gDsnyyeW/ilBD6TtAk9pe6QKH83lGlA/
2bWItSalCQk+8HJxYzEowKqYFGa6IaIc9tMb8mXj8fSJrYpmGSaaPDJJbiFsHkgzUgKFO56A6/eF
ldbJbZmhU48DLTEq3y10q679uNFxpRjMbj1VLTSaUJ5hhfLgA9jgL7ku8ypfmsyML/AFtmtYlAYS
x/hfNfqd/HxrFDj4suOVtrsEgFli/p8rQFuk8bUKKi+qMACYCmucfH6KPKuWAuxGCuqam7J+SLhy
F6DV5jjns6q2TiCqwQ/SFDGGwNWkiXwsljkpcugaJxrggWO350nMbF0QYxh1wDeVmRmPTvIktQeN
C2vym6ToRxoNYTF2Tp4Y99bkBeDapsuHhs2C3sEBcQs8X6JL4hEvCnkrhPhAFYDvUWiWd97v1xEF
JXyVXUJkVG9BXgkFfhxRC6VBtIUPWaRXjsqkEhgA4GfNh9Ato1kt2NsNy0Yk0TuxhhyZVCo9JfjN
xOUbhJqEzzlTH8+IdmNPKx43EGDT0Lrsk/UOaUPBvFWdb3GqIMg4TchPjXgWpuyR85DLNpqWKB3K
K2K8dzks0hfLCIP0o1ZrJyaV6vTRLX6GDJX6JZRDQIcYVYCtM38a642Um1FZz9czprkChHqQfL3B
NzQrdtyK7LIW3fUDo5pKTkFMk/BrlxVPsmRbDFKf4rxCbgZA+dTNUmlpBauC7VYTM5YFkM6wgAQf
kvhXW9lkApSLz8wKN03C6wRC66r8yh/YqKG+OjTUsFovJrTDokQK8MgWGIzpNPRCNORK91DK5GNY
HEXIaZzdLIwnRbeaVleFh1M2/3aFZkINsBeVqebQim1r/XodkwvYfRJymSowdoWJn6/gXjWYYZGh
nHpo+U87TYAoe/0bNSftOYIRvEYmlBQPHk/YuQ7Jdb5hXqiv8iaBtaRv3kWfgGc6JF0PyuLIJmQz
sePGBoxGEAi/gTPFAp5q7bYdVvVh+ebZ1KPCkgVP67PIAZMIBdM7ytHOVT5vyhBUSnzHGj7tsaK/
AqD6UoWrkSts4FsZnh9O4M8pkE8Vm26V8YWdgHnDnz87zqQ/CBdX9Nf6pLsk7Gm/k4IQqgnaYV3Q
djGKNtk3QKG8x7u/AfFVjfC3uxos9Lej1HjxSt7yMGU5UStm3a89d3ADmdllSmHXG8oaJwgC5yD+
6ZyoV+S6O/inHAAITWTqNss+CZq3wQ2fSPRm3iMIYujSFh49ZWF6Y5hhATGZ7puV05IkX1gc8Ela
qcxST2cD5iqJ2QwgOpu3pXIdq8sop2UlJ2ii2/Ct6PF84r15S+LX3gLwJ/KnCGF+GUwOWmRkx3Hu
v4EWljx5OFiNNQjpL6/VF8J8mZgV0Yatyn1p4Zb53UROPaTcM7aRopMguRKwhgpbxYt/+eTJW6XO
DU2onCq+kdiW47TN2oEGrRxvPPPOq8/oSOfJtP28+4j2QIWKpNEEkyM1waSHRIK9ySAFcsxROSmZ
y5VUaZHpge4mjt4o3wek/wS6MwWVPMsAu3hEPxAU1KQr/u9URt3MMa2fLlo4iYegrEEYe2yLrrAN
jfOlfFl2WAfnBn0q9dqaZPhtJGkjLcv87aMFcrI8E5sRxgPWXNHe5E3yM7fFaxtQ9czAwy5HBQ7T
gJgBJSPfEfU8e3x0JPGyrdeTDJ3A7ttFutTZr1mNDvkDS1bKipmWU7JPSOW9iMIXgy8z3KaMV17o
y3aq0spIkFtfHwEMlx5tdEz8T/iwPwSqX7cnQdq/VsqDUNNb4SVzr+cYcHaGI1VbX/0HzDuMomQP
8bBDfD6NPr3YWlufkhrsbQfYW7WwfFtn5mraBA8+uYpAnFvNL1nN6ushsbMR1N+vSXjcYN5NACl/
H2124SzQrgKMKsLqQRU44LOU1vbHbBKDecnaquvebNH7p2feemLLqYcfbhQerM8RTzfGlW92BjUa
pGu7s0UvPCSvVvGLI6kKWChXl/Ug0dnDJutwDJbPGIIKIcK+2NPBDWx7NvZcgk1vLArNWzWWN5i0
Z8dDhZ6CzgsX9JZYvHPLyXwjLrgSDXp6EkJ3xaVltlxsSPjIWuSJ5UR2t3a5j70+y53DA5hawRIJ
BflpJHyKmzPzoIY+XozhC5geLbq+MLSTkXTA+Md2N7j1po0WdpbtlNFxKyHKeOmAG5tXoFNxuonX
NfKY106GmQh1ErXt/sv1FnwsfMlB1zi1P2UI7BNRKZFKqOrCBbJHJCnZXGXx5HE1jHd9qZY8pcf/
raU+1iunjRWFwqi0m4Q/8gbHQTiFqXI0Vta3iD7PfOvOLzc9cuejpa4JY/ddtS3kX2TIpZRySbii
XgeFxsoRZG/o05PSNLi9egYTmlUgVS8d+uK+3hIvzh7l7GM7KBHA/q9Nsn2MXkbuM26NH3qxiAea
Dn32PsY77N/kRaam/N0h1Zw1y+Yze0k6Xo7SvXAa3PeIHINvxYjsqA0DUbJAr2qJQ9ez9vPSqTOB
Dhbd/08MfHVAhXHpF3fM+00YOk9kcYkG9Ri/eeixt2oEDZaKzJLnnoqvFxeWkGjVuZfdk5dOu9v7
ExEKEHZo+ZvJiEXLjjzmDtZFould5AIW+q3ME1xdRFAo48yScl3GdhltW7oIIwCbxONHp6pPH1DB
UKn3Dh2Z6TWDBMdTMe2/L9TS7lojLF/dKkQy/l5IxcOXSsyxUWAVpL5ZrB9DtijZUUpLiHlAFei9
Y9Z+k80OmqZhY2yO5s8R0ALs1Ft48o5GjKhCgHF72iPb/y0d1jf95FfmUoxwezzrhskMaOCfFgg8
AphxbFX/k+52qiLuQkjtJScwGnNfZDEzWfMjSThKXVI/arwQ7Tn55JqubDkyP18b3uYJ3czC/KiX
yv+ED9+8d35HV+DzUtygwZY7rrisICcU3NFk7cc8i1jdolvkOva04x34YiSWT+zjbKj39iDgMJfP
nq1M1Ah0h3m9u3TgvvOjbzfU5dUNe5/RyIdK0LTLLKGFZO1jZL2P6ntEgfg507gCdVHVavN3mTHX
IPwxe6Y6aJ52LnrwSvqTlTplUK3PXqyywVm3ukSQ8najZI5ITtibqu8sJzJxPESP1h/CGEy2irf0
tKuFjzq4iUmlE08KwGR6AdQ90uUyDZ7BInDpap0TUFE2yqj+Cmg/RLdONz44miMbIJ+DAxSUi2MS
CVoaEGRDgZX7L+1GCwlSyMt9OauSexn2E56pMGI/A/PNjcGrIdxkutQoK2YRlg7i6f+wNb9Y2gcM
YzNWLYz5uyo3rNjHRcKm7HEbiWcCdoOlOc1k1c55wLySin4bgMGuA9UXa2pj15QXYNFMeJbtfhwm
ar4+eZn5WyZ6Q7DhbN8CKPpHO9TyDPvVgQmrAQcWSBAx1hC6wirnvf7ATJlrz+DmfHI9E026mId6
KH40lG9jMqfrWu7g7s8wz6nIBiamEhcd5objUHUEmMKbsASQjGVhZA6QbCbgAukMJWUtjQs3kGXc
FgiOMoJpGeYNPE8MJgGTMl4eB3OVuQh36cD5wqXzYC8GP17NZ/0WINIk6TBXOsOpv1WCDSwhzshP
zuOsK8lBIWHJFZMEZp1ygQP/cGs0RyCqkD8ulUBTV+K+EZcy6DXjw67oee/ALKZrhgkjW/cAGZxd
eGZowjoQwZjMCPMMu4WX0cMnUwzIo4hU1IQi+ktIpNRZkliY3/li31LBpNye1mMA1I1p7/jq9Rb+
No3LbhHCont+fMEy734+6OiLsjBXts+/ro+qRqYFtjyT+k0RFo619T77Yp2untdxkjuR6be0s93j
vPwKi2VrjYaTCJbKSM0oj0YtWmM4nSWlNLkS2h2rjbGdujgcDPlU8I44Bo2G1oMGiCui9FodkZtG
kOBqtjbv1R/z+321jpGACzq25FPJUSd1xst7U+0GLp/EzuEpptq4ISk5nnvG8OpY7afVlV5aPFsj
MBQKt8uSzd/dHgxVjmPeqp1cV0WABPcaLzC/ehxbi04Q
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IVxyk7XRM4VsQcD0QPYws4xsTeDPKdwWYfreQJ7l1z8C+G+JAKZ2psrNI+b5ecZ2ziPH9MBGr/oY
8XtzCKmjJw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VO3Jpo4aYF9TyVwyAUb3a/oDy8Yhm9ea/9mAjNtuOBRL0qoy0/CWzL7D+bc1SnZvEP4BG903Ildl
dM2y4TNyVTBUaU7Cz+LzZfu9kCPWnmttlx92LcMKLNuvGUMPXmV5jr3PzSFEvoDuCinMqNc8uKFO
Ux/aX6fmBD8AbQfpK30=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qOkimDe0rSU5f1zKvoE8a4lZw1WOOUxh8wtTIN0ys09AXuQuNNCdfu6VL2Xuj0Xus09sBU1FazgW
XpQHuw7XcozHRlnUFKPJg2P12yPJsLRkOqUWtHTUXmH/8s2RglOoEcmFeX9FVh1IRMdnp+D/F4GX
/80OwH0Jtm4eUDa5EFkNoIfhlOG4JOG/JCsYRnsAoZAbyHMEk6qPxdOGDrYzkbA3CMCikTuE6wOm
0j69ZgENzpWR5aludQDu44oKZqgkdMKNm6Mvk//s2aUOTBYWabbSKe/I/+cEp1tWS7+9AAmaVwO+
KwmsZsNR4Ztb6OH4hCq0936o+bycwR0b+Wr1VA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4df1QYXbx3PmA5i1scwSy/ZAJgZ0wNtl21eeCeUI5h4IQD2UalJOUkc5a5UR/j7lX9ToyF2yFHzK
L4EoH+xXm54bGihfoaTvocQQsWhCDObbmBOtqB6WS1/bog7FNgoEObi/E19vJsjPSd6nCCdhglZ1
j33mJRkZed+lVziTR/s=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Rtu5N6w0tnewss9ZQUyM3gMzu1D5Ba/+qJO2rdGgk0QN5Nm+4TaVyiEXzVM5DP8z3mycaRD+z4HG
QXarW6RH4GHKahoLlSY8cryjSJRWS6D7/Z1joY2fgJb8apydMguGWjRZ/uW6R7BEimGxB3Xuon63
ZdpcvKZmoyvfg0kjAjor/DxtP3SP6DKxH3BeegGQKpP/+5EmCrAhhPu+NA21340wcbghotvyYusJ
ErSZhtj+1FLwV2sO7TUt1etBG8nf/yETDQPE7Q+zX+BzOktmY3tIKds/9qdyDt6Qb5WIxLMyaMa3
eyi0SGAuZdeDtK8Os3w2ajEZI+VjufruVqtCCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17760)
`protect data_block
yvvRtu+tA91Rtyv3I35O4K6BiUlBjs7LTFLRc9twWgYZkATXrSpXZut2NlvE8mcC7mB31ueT2vlU
P9hzhGYaJ5GcmScpsC1FKNndMfl3Ug9Pqiw49YT0Xp/AQWIr+q38Pu2DmkLm87YVBi0HN6JMSu6G
rwJt5qvXJYVA5oSnqcy27I93z0KCdBaCW4BhEaXbMLEY+qzcYsWxGhgjRzVfC2OhOSpdpDr2MKHw
1YDri1cTZAVy/b3L8VUTlyQx4YRG+qS3u0Cz3dOLm9nglzh9Pa9XJC4+Lnpli7w7vpvakaXaH9W9
I9Xs/9ShuVul4UrHUMsoz9V5jcPh1iHPT9m0ZTeLUdfod7NEEFDW47vWU8XjL6iEqBvA/DrJKrri
hjJ//n7fbl9gjxGZT+IKqHleRVz+dRiS/uTuRo22UsAcWrLoCdroE0x4MAJ9vC0vScZa86PQBj0m
ixJFhU15XHesAUmaWmkIVFZdUdZL6n63C2nZpQmpBX8G1td46ib/xrjcP1HPzbr1hPb30S/GA95D
4e3ICss1yPb8NZCwvzZHNKYRJlVJ6EOWwDxLeBOjWmUySMUcywo+toi8FWztPmB/Fzs/gyRSBxsb
FBe82kj2NTjDK0dD4XCcU8bGjVOKNJ3KoJmC+0UD0jihX5N1CdPg7+/bvmP+MCdk3ondXZKJzYI3
9YFYkr0RM2BhF57jZwHcHHmFJrakmG38Lap7lsdonuIO5mfOOuicr4JGW8Qijs1+c7VMc6LUwGDt
YKznnHTq75vwwVLxmtGYpW4RTIuqlZmOJwC34kp9oVx0+wFtUxMvQgXry9FwUwb2gSWRseSfbmMB
auDz+22lW+enEoOu3PzG3plNq4oQP2K2H++ZU7HNTNGSA6VpJWDQ1c8o+i7+XEkyIqt9DZHUxb+3
HlbwgxRkMYX88B7lb3GnNDLF2YzkJMgQjpyPi+t3N2MtquCFuqNuaKv0LoD6+mwRceg/hAylp3x1
m9DKQ0DcKuhctFlcx3aOGMXc0mzgjh9Umxn2Ng7JEliL6/L086w36Jar0AAtsKsXZ1NsDDBpiIeT
c9pWEQj9ud2144CtZKOT9/hr1wy8/jpi1lQaHanlWWtc/eb1aDpSY58hPbltVjUTyizUFFWsqQAC
PGoqDXF3N036pR2Ipsz0lKGQE6qHOZ9IQByoJkJfVJQFD7arWnGsW4G4I9tdTj8LBH1I0/XQKvur
lSNx9C6iPx8J8GemXPHqEIipG+GgoeMURYc7ft3GzrBdwbTFPm/qrxT/0vdju3tRDBl4JSzWO+do
z/s/CD6wNYNcDBCSDKcprRdML0+tkUYr6Jexl5rxIe2GBG2XGRgBDqc+wBSNJY7VVfutmSr3NjPK
RJK5NldZFn8fT/rjewbLV4flhMn1tgsE6HhNm8GuRS52PpzP+BK3fCtYvb1mnkFy+e3mwc3RgZ45
5iaZGmsBwnJwI9GcgMGoWSDkSaL/1PrI03WtUczFAidTPvIY08FA8CTdX8Bo/j1vK5yj8spVzrNq
2YNw08dzyQOA6p4yaEO8Raki3qlKk9oCGUe72zvHFj8EIo6DPYz7MTOBMZh7qLr1JDqBA+iyQCSU
UO9dElHR49OYArhLqejxnXEbJqi2McLLRKhJoiH7B/feWKz5mjNEjtWpHgiwx6VhyEKkL6UZ1Rib
ZtiEI9gtUbhZ6XzaYm3TiIRoYgTzxH0j8bAv7Zy61YnOi5ds35hrlF48AdxPXK/eT9RxLQ9JC4D+
xhLyqoQdstrt5DgaM3NxG2mKEJVH9uc9wj8j/rmn9YrBedhVek2F8Uvojvb9UP2S80Gz13xgD5DT
uHlDBG0pjratONtNE06BnMLwZRtD8fOAmitaJqr+uurpGUSmFSP1C9+FHTWgzBTdRwxLO8vYdEOz
WFiLspZhFCxJpRdUt6N09XI21qtC+0+ZgVoJcuL102pig2HCGw+mVSkibp2ZzBHApj3TyyQWeR0T
soE6qVGrU0cCA6w+mgSp/LpLjFALA+nFAG3lXPvfyzy3nWkgcWbCXiItZJY+SdblaE3tEF0j7zRy
QEv4a8Rg+L6tHbS4IhpoHW2u/3VbDszbEYb4sRKfYUA0hAwJaM8jOAxyu4YRtJsjn94Jek1Taiie
hp0Ndlnhy5vlx4q5I6i8Nc99UyR9uhRu8iqRtT7nCYuJSAzDby3Uxqh6srwmKPrb31KF5pRhTgEE
hoDR5pRAhvr+p6GEHRm1IAJTB/vA3Cmck+beIM8DaYRIdaZnzC9N04oH+sWVHExAUc9WW2ZHotPC
yowKFvokfu+7look6EHxqKtkI6qUIsFrQgy755fSnh7+GR8EVZFKqkRCDv0zQz3m3MIaUQ9GzxNA
nVZg02l+SgGZHXvy8wOZE4ONpWcUccgX9k8Mqf2VrJEhn7FTdwr/L68VLWlWyJ51gTID4qsEbmQR
eUcVhXwZ8J6/Jr+tfQkihSE/r9/FrMS9DtCeXZFSTXFkRXX3jwy08FYzVkX1AU3nfi5uob/pWe44
jJ4c+H4TgTK/YFd0U9+b9+hcQ/PKCmyuUWlZMD2jh2m6YaM0tRHT7pTE3k+5NorK0KIzBPhuhR0P
kwadh+BfDa9Ed/g8FI4r9aO+bzUYkbubz1m2BkiyrHNUN4b/jhDQyeuJYsvVZmik7vXZ6GcS1rnC
ZJpUE1bWR8FcYhqQoncmXGI126qn791BoIP3g9UyBSGDJ/hK/eFW6lylhaaJjjVsKepmxGzcVN1B
mCwVpKVdTSGBmK72htH5om7KKA2S1rC5U1UUj3MbiW7ZNwfDd0USkl8imBDLwgYFtoEE1ko8C7Jc
eUprl5A05bpIwcNw4M1zuvcSJzD1rtWdZQl2vo3uekE+ox++ptfYE1O4Xj/2TqSRnKWmvElAWcGk
d1P93oZ45PNjviXZ8GjPM3O0qWdvlgjvAq0xdzA6x0TysB9PpseLW+g8nB6svNvi0GhK/LLkeLYg
V+VOQradYifDOr8PNb0cqid1ncvsR8+c0tlZfcJr23pLfcE3Vqz5wPmHYoK484/vAUmQUEHiXjLv
MiKyjk8ywnYHQ/TOYWuO5OiF3b4XtDucLmEyRzxNB7rY1i7qaj6wGs15PP5RLOMaDOI9Kg6163IT
YHmjt12E1isvBtgqS4df/zN19hcUsAr+Hd+fpoCiaRD8qfZT7eD2F7aDUpS5tVOH7gVSyJWqzQ5q
Obv9Yhw7rja/O45RtfCLUeQNveIdOxbYJdxtkbtNUL4THMOaUooUKNDHf2XRJ/IU29P3yYsch8DL
w6GDueFKcmhtTaLLsoIw5tztfz1OnR/Ji8//265ufazAczEkWZEuwDJ820UjB8sYf6rqgnsGaFMq
k4/RqF2vivZ5ejxFZq4j5HxYIkrT0dvfR14iHiz1gFBjRkaPy0KB92AudlRi5GguJSj9i9apnV0C
9Q8mNjw2IhqKOYuyV9e6QbBpKJ96If+glayPM19wkoNu3wYrQpc35Fto6fYKFdY6dhE8nKPhcitV
/uItKlA/SbBd82Zd2+R5YPNcmQq0sWFXHgntGjncAGogKw7gdfoVMOM8623k3ZSxgx+hl1hERb55
2VAlad1Z2TVWotbB4SU6fYbYbkgvMzH5sJuCqbAAKfcoPFz1nWbbyWa08tpLEd7dFgSfxRMD6emG
vbRwvFQQjTUHayp8X4YhTp75/cn7s7BNav/nMANVwbzv+7PlcCBDE/FAkBmre/mWCARVoeNQi9yk
Lmy+/QFbBCSDmgH9dT+J0qyptUReayys26DpOx3zpnRbUVqoevpDLpdsoEIttEWQIhHlgFCwxqwE
aRk/jq630RhYJrspYYhMKJx7vBModJIEGer5px3GFiyOMr4+4I2Loz4N0yOCB4NxzVtMSM+DMFzb
Yqmp3TY7W03MSy4BUlptWvy4cfrCDCrea8duJ43frMTKFTfbW+IerIgRfu6o1EW2xXm1cTpBK1C5
GDw5N3ENOo9k6+Og7Rv6BqrZrvmt4KofAZpoRQwtrvIUEswUfZzexMH0dWDua0IDEUztjkju9U3k
MYVajimuyW6IXCYU0qQCvsz9sBM2LLZ1x1Vup7fB1Ec5aPwU/UHatOkTm3aX0ZLYdmaCrVM88w9G
XHeo1x2sSQwb3bclHeYGqJ5KFtGY8NkrjA2kOqD+X2jo651hd0o8X/ii6dRA1MaQa3XRL48KOtEM
HH0PUmnhNz19o5YiXS60R4NMyF8DBJ2arUQqgtrBdHpYd+zsNwOO4FJe/HVkB0g9fp75mEMH5PiJ
iCp8PJo1jsqW1yWtRGUFGwq3z88uUmySC3W8F4jZcCA/IVM3H1z/nL/Xi6GkPU3ho614p2M5bRq2
14TEYUDIUMMz5OS3VFeKp3NLgKmCpVj7tbmiZi9T8Yde5BbWfETD2YjKPY4NPYiw4TNz+908oHc2
yTbewFueWvL/NaEUrh1xMwQw0DRkd8xsxovrukJPMeMMIOpJVuHAqxeQFIhjwyO05shLRO+8ICOY
lVC8RDu4KIeHaBIdj78ETsgHAau5157cMpNdCv1z6u/eAEhsPNaTpoYf5z4Ulz5+vbrw+Ig6ywPW
AC3chkAwdqF9uooKaqUaS0uaMYKHDaK2y5UfVCBUcfko4mCk+jjZbqPR4oE/RY4mRKF+S5KVRb51
goeafsPpARmOwOZcbpLNMXGonqOUJEFV7nFBn0sn+mMycGAzE+JXd2B03sI8g6vqICD4805s8/Q7
Q9RvYQCBXt2A6pU5gu9eZBujlJ5yteDEmqSPNTNLHzUtnYMoAcOjjRN+mnEfti3CP2YaqZYc7AEK
EmGhccCK28g3Iq3fyEIwqSG5ZMQqTqoqd2RXD5hdEa8/QoSw8h+tBDysQ5iCskiecYnVoVm2sJ9g
EiFptSQHJIy0hyW5bqu4IBzo173gYuxltoA/x0vJsCyFYs77QhbyJAFsJLmGHqO3cT9lndY5RmIe
G2IsYZVzwYIn/hCH0vy7GSobNYDvEMIvGBaU5p1UTsf1zLoaBwNW5il64Rmt8mWVqr6Q4Cv07zk7
YKXZHTXhEeAgsPcWekKsDPhosTQ1OG/Lbmqe6Xtt932gr1mKpZC9HDG0zXIrXY+2oSE8WilO1BRy
J88nrrr7Yu0oYnF4wZWHuAWIyjgLKyWWX4IP/WRaze8T+DWjRzYC+x719Lw3Own8W4ws2iTfKhys
/AoSQctmniBEUleebvUzkP/54oUfgrmlSFnT+LQI1wpo2T+VfQtutqXZD+Q9onWKVVV4HeEbkZlD
NiZEFqgI7BCHMNKvyQsr+gN3d1+ljxpDWwjLTifh1kNDK1FTX628L7Esv/ze15vf2ojo/9c1/gl/
t1SV+B85OJEVM2ghrmoVc/L4ECZPJK0ZQo5F/4K6TFqIGKCvu6JvWCTXCXXQuvIJWVCf3yQ+xB28
CnIRjnpjYhPYNojhQfb5Zv+GZ7LFqZZ1/o78veE9yuWl0lUlNLkf7AciAMp2qc67QqLSzbmp+IIZ
GRPGcMLDzgqZMu5UoNLRtDcIK4IdO68RfVU+DfGj7azU8UasdLC7EXFxENSmQ/djh/0I4Ci41R+q
wsa+kmx3eYs+rFXPF/gpMof9+m7gcNIlaKRiKrmGwaefZwbiLS2b5ZrIZ6dIXfBst6s3VP1CYaaa
+z49NTCU0GqV80EBrXnRQ63CMSRECEHoQlN/WGzyaldjxjHPYO9Hmx4A4l37hy0X4CBEgwcgcLmn
2IaYATXcAYJj2x+86KLB5ybH7SyK4Ew14BYjahhIhbE/HpiaKw6srEVCnQJsybU/L8kpmLrJFJJB
A7L0H6rsyqypQ0Gw1vYRNT/Iq1SfeeCbJucKyPaC8FIIMxhLscoBs871BAGV6PnoCQwWlPdh7wt/
cV+rFe76p7fOp7y/iWBGEIZ3hi+nWA/1wg/Gwy2n5z+TL5zSsOLvSN/UaFnaFFlJfzsshhbbzRjm
u8HmR4iISYlZfg+PuCGg4qWDzTm+W3rHe0IKKFdTl4GXGM1/EpTtOAqbIDIWKEIZkJ5l8b15nkSy
kXA7m+xG+B2kCr6obeLcnH/Kll+3TvkRO20Bb17nVNUb9o9OAtuAZf0dsN0dkMWVbDBmARX5RrB8
Xaso0jhmy2GD0839FOGPRmjq0itlZIHy9gyGxFuelbdXGBP7YJlreCebt5nS69xLW/ntBMeaobHB
+fuRF9ZeLz6NIAjircenBW7v07uWGziq8CV4rmH/bVbBQVpgNLXkN8+irSvzIih6+uQU+4qnhkGf
6DPM1CIN42m9ynyzhboG0MwLmsmxfHNu6W7pdDbuQK0nD+bziOLzzqrXLBnyPXGnwpO2QuvUEpHz
JbvGAC0fH3+ZHVgO2K75xWmD0ckLOS8k2Z5yXiDsc+mex5g46t0h1hrH4Yyvs+xHhn22sZ5vmAd9
z+TAxX31wRoiRQvb/b9h8k+DfNRbYFTRb2ARM5f0wglZ2CBCHU3UDca46UnCcX0s2i8dCJiik+U8
1YIMvzM1YeyL3p4mMj0N+JIFkUtiWw2Iimbj4Zp6ofh5N27FA2Lw2SNpuIQppGII0um+Cd8fl8LJ
wmvWzSxiUir0Ax11Yq2EPE4jm3nKtv2sY0E6lx8WJYJydjXzqOwe7I/q8cblI4Vw7LJj+vuX/Vac
5mEUxAfQSPmHwmPnz7dWxElLo7zN511DK5ZEC8GBtiK9/m3RoIfI1+3Csl/GLaL5uWLV5jg3nmav
Y0x1hldBRI4gGM/8vCOKB1q8BY8TbeB6wETtrgJDpKK2w6lzrgVWA5wHTPjCuFeJZQKurXZeL80g
JJpIX8UxxYd+U6Gg7ji8gqW9cjciYoznCFRSJAcwiV6/RLQ7TMkMWTU2UPbgRRUhP5AJaTlsHLBG
kDpRv5sUys85ONbc5+pksLhtG+6Vd/mWvnomEBms1/e+jX8+Af6n98WPo67PSdCntlBBB0GpSw77
A58uptTtJh3ZnWGQRMSuQLMvad/WJZKosSXA1e4gAi8brVgIYmbIc2kzpFVAw8CT8ZJVQt0dh7lh
8tVc9ifnMjHMk7eBB/kSfTmYqiH66g/FPPIMThz2zJc8uB+JcA65L3cTruK5TAIZfFjQsRhDD+jo
+IQSPEMe5sSQGn6lLvuEYseLQbSEswNwE1xM0mWOmQTgipmdzDR1ApQU7CJ3glXHI7CVSZ+Ptc0x
tMhQKU+3nMUBMdbrbWczDZr8+LtuVq79gy6RjWSEvDiU8k/C2jfU7gvAAhYeQmEWA2ZDfrBZGMUe
ctwS4RKrBsgrdotouRos6i7rnUYet3BfSROrkb0kSdMZRGxAyAEEU/HXaAAC8PBph61GdBPOjY2o
ucgy4/5j59ePvr2AHV13YPvzcUThetgzbOE/iQtfdAyChyoVx/t7MUXlzDXK9YyFeO5akcWlv5cV
/tZmdn+0Ip2LqVVRXFEBSoKdQdXJdPtlxjfAelCI04ov4YoJ58o+t0nhwgO7bkbIx87oHNgrzQ2M
F9Nx7WUW7kGIwr83dm82aDD3MxmSYxoppKine4XFBSQuB5OgrdtAHhsoSTFIgdLrqVtjPempXbGk
sAGCyeTTFU5G+XjRzr/5F6bDtFizNprxJBKDaht1ZHz7ETvgFDqUE1wXMVV/4EQdWo3mWO3IzFHy
MHtIRlXUch3GQNXGHB3VG9FfABO63ISUv+i8letcphRuJGaIqd6D140yb1j9b65V/pllsmcXjxZI
Ah43oD+OViZ853FMzqnn1m6QUPSsMZIRyqrAz1NPtluN+CJrw1FCZVpiTakwpdxU24wYPLdzkJVt
MpfNjTp4CfPgAm7JSZ8uNwQriV6W+lMhO/nOlWDmWdpkvsTuaEmfMCDUgnSLOZS+lGvmuwQqc4c7
zpaP6+TmfafMbg199BGBGKHnAzZYORNMzqGduqQH2rfIjXYsYhgEvrviZ02MrjLaQZP6+Ut5Alf8
E/kL+HVFFRph1szoSkmJ7EBXybrGUR5qMCQirKzjN+9O+mZGlpjLRjEm9OvwEI2YBAdnbEy2PUIS
EppQU9iHilUApIhfes6nYf+wBw90smvQ+ggytyPZpyUuHI4qtFg7oOfeQJsHmMUTERb3j27kJedP
2tYr9qiiRWvUkdwJ4KJwqWf4pQgGognpwYEamf+1nPv2wTMMQK8Xx/yjdn10Y0/KWTAYXLQMmYjz
1frZ7sNr9m2G1bncTeAGzAAYatbj5nvolqrKxgG3z0xhGVUVc40Ki2Nepm+7jD8G0IY0ml5LLddn
YbZpN/8M3Qhx3Xq5oGiH/2TnC8sMX0iYn2UCyLxrWczitSRdquyZOivyQrbiaox+Q14RjH2RZNd5
aQF0j+++AlFnkxA005oCTlPjkpfMTIc4RxeeLQJ/tOK503oFkgsrCogo+yF12lnKy6igucSzbMPn
3Wor45sypUNSbvvkuBCYT1dqOqZXmmu2OwrJxxib2arzDMD+Od3/2YCFIL50cnXvoIjhEB0DXR9K
/K7a88aV7qbJ4DHBzJ3f0XIdiFQ8SQgz7J1rbVBgheu6FymoZephdjJLqZb90iDDQWVJmojtbzXg
gFOUIz5M7rwsn1szvg6OQvvyk2BO7F4pzU/gosxylIy+ZgksSmVFg/qaV20rZ1k+aSKwrFaoQyeZ
RFL+1rHpj+IbGKJ0T6azxeZPrSBdULXO4GIJdvr3Qb7m1uZp95FUpJBDu9qVsBeW+e88fCT6V8gX
VS6NTuR49358rzHdu4P84iHiJvQ86U9hTj3lb3jjwQAZN8p0kHLIhJ/OK3HNXw+RTjLj3vFhUR/i
IRh025GWPgCvLKW/Fcjs6l17Yf4iBubssKiYf8wlCs3fcp9iubVKMP7pRHwefSdGrCymu6kYmLgw
mqeCa1xHRtdyJWo9Qe40/RZF/z5wrG4kAL6/QY4JsNK5IuaqdL11AZL2SCSWi+If9d6xMChOcgdO
Kz8rL/ul1zVN4v9usZdnQoWuT37LkO/XTV67Fotcg6wt/2SklpnESLjZ8scuc4uMPNBaKqJxjusu
l1vSBAc0RfX+94qdKAB1kZkl5L/0wR4MeVpy7u7MCHssLTOzpzCO9upNisBXiFFPDC00CfVouYZN
XXF0RkU9ILKEeChv27SW6Gi7Qy+jku7OC4OkwVTtOeSe3uN21fa0MxUAVDqDcSYih33eUdQ2UgQt
L6AkF4QraqjCQmkNLaNY6/FADaaIph2sC0y2v4R6EliBhBDUC/ueMaaLEicWDYdky6CenbfyuZOC
Uvu3Y/IwIV5G1ioj22TVv+/LM2NMXlM3efeBXVFLlpk0glMoySXNMXgPIwpcUbWKr9MvEuUqvHfU
Ua+EPFCKPWY+MPtNhxODgEaf5SD42ilmAXixVxbfQgZT8KDy5ESHSevUnG4beDCiUOx2OxSZYEd2
WecJ3ZL6564z/G4fc7Om0ZIOU9ng5EgK5ufct/8wDhJxhrKfWKF8oGMAz/NIeDg+KDpnnOd9TWC8
m1C/nAlPRFVJESuKzp85N/iFta4ERlbMXC3KbBhJx19efD9AzC6BaiST96FqCaEQ0gbAZg+5M0vd
sd4uARkYKVZ+saEmK10NttpOf8+fMTy+o11z0fGYxK7evc99er/Gbpf39qG9yEfmAEVRfphmZPIn
SQf7u15eABhrE65ulYC9cW/1kD9cckhW3Ca6Fmggjt0dr5f0xyY9FGPQPcKlXF41lN5BHyQxsQIA
iGo9RSECpzORa/a8M6ZNFsEFb1RNk7PIJWUUTwA3yGJ86kp56QxDSwHJ3pphqBtvncSbkJA4qxYe
VYFrqoPM2y9CnuLtBx77VYq0P4lNlDZj2jk3mHJrjUoyGQJcNWMrbXeusyvrDBumKKKJuoCp8Ji0
/RMJ+8HFg8+R4uKqYvpIJg8NyYQ8vYA5vtYccRW0jvZP/i0U6PWDFr9Jttd7mvkTVOZWVQzQwIa1
CX0sZXUqWjeUdWRk0PgpbprIfHUzRGF/71Zzu1yRW2GCnx767EQ5qKMpDIk0GPjYaqO4xoSoi9aM
1yz/MP17scsZFRtDTEX3mlGXuzvOXzoZuF1pv+cx/HZyvxTWVigsZvXDBZjLh/wgy0creA+fBV1k
8fkV6zAuCk5dk5WqKFfYd+1UeCPMcZKIBp4CT4CSOy97C7PdZOfTtjBE2N1HOoaQ2ZxOQQfwlT7T
fBNkY0FZvjuckL0I+G/gCuS39PwVULFYbFIzpXBM1Nbej2d5BRC9Qd2AZu9sxMPtcZKUu95Tnwhz
RLTAtWmI3jpVmutYnGnpM5mKwhhOdMO3VOC5v3YpF592DzT+6/6Acs5ks+nnzpA1Us36PVKcWGkE
M1WjUqhQAuy5AFtL3rF2Roudc62UHxBXUcrRUznmTU0m6HWy5ij6umKW8aSGQEAuTFkgHG+/QK3t
lkny9IyYFmqLI8pYvOJTBRa/mUHj/dj/6NbKzslOo2YhiygO1nVPUAcgCQY4cgBaV1HZAFPnSrue
xDDcyoDCQ9XAq7HtK2PK5zi3RkeZ2APBYNWexQi62G+cTV00wfk/mJEXllv7M1McZl6EYNB7w7Wy
NSFsKlLu8YEu9N+Kz6RKVjxTNxRK8PL4e5PF+lnFbOzA7pjA2WZ8s4rN/GBsDQxj+iRTW9eFFwkI
55pwh0HyA5SIW3FjpJUf7cIrlGZ4oEXT7+1t1T2BK+cZECsvU3yQPWI0wujjI3BHqX2Avcr6Gfjj
Zt/BOCeLm3WPYbVnr5JtETvK2x7GxSyH+9LMO852zV25Cd+48P/c6S2Kw0ca728Ny1Y6KGbL3qlP
4EvN/TZ7etw5UKea706IUXwIQVwpP5jQ938y0oHDYwffAWQlBszHIVreDFPDhRH7grduFfXwkAZq
Xg1+sBIztw+hxqlMs53QCz42G+g9RWycycylepEsvcSk9fVNm6VmgeZfgi6X66giRnNJpU2PIBAF
TmbPAcrMrGqiw6Igp/NT9dLv+HdaubjRbMktYivcwKhtfvRJxOMuhYot4wWlUUavaDQbJmW24VmJ
ZwCVPPi6rQ4Nhst/OnX8HNiq2U/gTHWXorogGqfyr8Y6nwQ1i/rMdmxoA7b/GE1m9P5/B6xamFQg
EwXo+CxJrOCPsGlEdrtI/EomayDvxVj5CfvkkF3AfbS1sQsfyGGG1tUvsuzyG6HbCWTS0DgHLYKw
mLw/kac2HudY+pRGugwjN7CsZhMmmjhzcrMq0IOLuASVzEQ07NRtu7qYo3gXq8qnNgGi3DQKDYrw
SYfT6Pwt/XDOLV/1Nwm7lrkBfprfCHgW0qbPVabJczWZCD+LcxtBQw3gU2094NvU7pb7yPhlgrq0
cS5wrnWHRgkSVTP2nTdECUOf2uvdv6UAYuKZB+WHxfuNgMuJy+NNx5KfDuofgKn+lYGw6REYH3Ka
ZOfYztF8bAdIPEvwSawpzhGQAiNBWeC79fEj8BBPy695w6r/wK/tqaFZeWkyTtf0I3GsKFAFjoZf
KzKY+NxdAAJi0qPk4lVk75CJ8kptfpPfFywJQmfyBb975TcM5vpsuS0OLQ7PPrjlQ3gHCKvA+H4n
QPQpKtQRoRv3axSt2d5bX+nHX7sDe0XLK+YohWnf6W2r8ED9onbhdOXu/KX2OHKoCbv/dCpO3JIs
yPgJIlcsES6Z7VNPf7AG2iCOhM8IJc2rkfWNF05kCosrhh9zj72ovE8RIohjbE6NHLiuUlA8oede
e6MJsIbj7L6BcoK50YtZJ47mkqQ53XN8aAc4J/rI7owAq6S9g50tYefm3L0nPbuCGWHERzd2gjBj
eixz+xrcNM7tnJIQKf3BHG5GEXQzMr8loXRSFArDmZxS3+X0oRJlIt5ZBx6wPaJLw/47C403FaVO
IQ7rKIj1J78aFfPu3+RUWyAxXdSUla9IOrNugivXxl+/pixnEdfqFhdGh7sINrMDr3Gva7MydLld
aT6Xxy2ZXoCIrn3QUJYKAx8iSWuYEwP4DqSnDEcIzqyptarJmsEalMCp9GrYMqhCwNqKhm7QFRVH
EJZYkgW+8UMhys0ogbrtFGbOrQzAPtBJbeUFIniW3mJQMXc79i1yiE21ixQ8ixak+mrYSNslA3e6
hUZFTZJoh5xpuHQYY1nBk5twjasanafpLNUSwBeNbZ44LL0/WMXxVmEI+OffB5P3t3OhAtcLuUmq
dmfqUu5wfet7GcTzjZMame10OMV+omk6zhW4JKpGLlaOc5wx6/zoGhGWuaT+cWFv7j06y/IK1Ge5
VwYmkjNekZd73ikRPgWbiiTGW9uE4WwlB6bawr+FtFUk26pt7kv3iGZfcaexkYk3gFuoCjMatcxm
5iJBYNcSz8AWR2X2L+XKSxtSf0hQgxgqoTL2UfsFHmKChrS4gCUThdVlzTQXUx4eyHaIJJH9DnFE
M5L/7tl89MeROUUOeAtes3QIlHeFFHBL/Ji3cfap8ryGMN1/gtgWdRFkXnoX+G6hQhXwma8qXikA
LWFDlKPRFEnz45o+6OCrGzLwe/otDBFLGfQ+GWVpN0kV/uZQ75Sf0e/PsUXpFnaLewiSKank6gwi
8yF+WH1FQE9YQ18xUl4fwH8mizCAxcpFYsA0t+RbSUT3n/4OMU5Qp9o7PN7lBGRIO5p6cMtXRnXC
JfW5MAwmEbuYLebmtXFTuJDEJn0GyquYWPiwpRZnv1ziMZpHifvHl8+OztIxJd2mYoB0qILovXrv
p+sSoT6d+Qt2nOaFyPi/m6CB3U6EZTDb/lY9CEtizEw/HAA/6VwkE8uIX7K7vI/hr2H0tduoiiNC
Z7Qlv61NGDw+Zsk5lf/EB3d4KiMTGGR+U3OwHtOnm6VYC8rcu1iaHeniGKq68Pd4RNabdW0SEWBG
SCsEB5twlwDDXXKD7ZjGPdrzFL4xeUQOh7FvLbwmC9sr/yhddMvrFkA2V9wW905QTisuA8OW3JSB
AUh4iRU5p3eIXnK4bV5DGLg5qrBMXKp7ITgTUsrz1GkN0djgyFC0XYoOcjI7B/yHlOip+3I0y4mv
lvXPbxrefN6gyKaXEaeKqc8lkTrapgWmcul9IqE2dc62oipP4yfF9dyU9mxlW10geK1g24KEyzGo
BeRphtKG4Qmo+nfR7liloRHvowONq++DWCDl7U64lFtPGM8DVJ8L3f2O4dZ63W280QNqOHfM+D3v
oYV1BCKRuIDzGPh+aSQpVALS7SpCpa9vz5n7NadTJvhdFlHr4KfuJX3Dh2oImi+n71N0Qn84euc1
fOD4vRyV2dyrbvpf8ZyzqYuhxBpx4gleNeoUIVPfagb2FoQQ+bskrJ9Fzaop3uYeyYjVHHz9Hn/v
kD96iS4c3YZAm2tkHGVHg07+rB7CjCZASOlDUuBZBYy/Vf49Oo6ZIbyPX6zKW1HIZX6TCXgL2RMD
Z18i6bS4dVWdamjHoVM2FEWy0zWmP48ZzqIofGQ35eZ/S/W7DX9ElshVXWSoz2DnttgcYeQP85Uy
g9m+ziCUZIcadRW964AoRUA3+eqQFMd4s3bDuqBW3XcuFpHSRPXh6t0Fs16Zxakn48FFt53gPuPn
kWccmrUbXLvLcqhA8NtpSsiryUclKgessi+7wqGZwaOZ/56iVBpZqOJwABqb37gDS4naRX5Lhm3s
m3HaTaYcXMsCHqn0auTQIir/uX4q5UPZFQ8Bz8UC3UKxfj5ULvWsnpZTirNjNzizmAgQT8RVbgzU
2G5ppcdSvbuZsNpQGRd4Pb6lyI9TgsK+1nbLlHGhemrdiL/34MiuObwmSLc73QRRBxNgFET6e1Lv
o6xWN/l6TErNc+6EiEwrxgHsEDYFHeG6qnW1ueS9Lpmo4/z7e+6wy6Tl/b5WouFHRr5e9BLEbuxz
42BX4dBB1w/PfHqyvQ9VWKQ2jLS19zH4agGu55yMenuP9MgLtErIMJT+Bl4ELPGwB6MlUUqTZB3t
VQC2OppjbtSjETZroDDv09xkwKjiHqEFViOwEy3sF9EdAetnX005D6kuc/K3fTbQi+m6fMRiKN2Z
BiUYhf8XENvED3ZMQxboABD11DmJ1e9Fs74DiyxWCij5drQwOkqqstt1vqKAB5y7Yfz7BEDaiFt4
N/hwftM3GyDIag16EDHX9KUEehn7+WAQVjm8M9q3X05bEsi+YJzDYvQ1YUMmCywjgkrU+we6Zlfj
jwHfaDlARpdR7SkNfEHejmsi+v6oKmporsGFi/PV6Zto0tsGqVmsM4rG7ACZ9Rr67LZv2ZBYmau9
YMgEVa7MgE7o+XRH98+6g76U+vPo8sDSXBzjLxrUWj7LbaLAwHwCiaHAk2NE6S11a38XlxU9q4Rc
V/ZeXX8H7FNqwpWafLtSUSFGjVEl2UPuR+LqiFTtg5pDbXTI3RUZ/1FTQXdKgs8mgkiZobQpzFE/
rrjhpfu5U2VFgUt175KUgZwXZkH/mSNkaexiOIwbfcsZBAy/tKw0ZMHpRgmxVxs6aDNEnWMppYML
mirp99KtxeiB4YkVvhoCIgRH9rd9f8SjF4hpmqeG33F+I/8aGa/B9TDn9mIOB0MkA9G27OhNWHti
BhiDpachcuiKHNRXtROW2tZ6QSKltulLhEE2tKS5ySwwxUggM23fjcafEriJsOg/75JPoP0f7KSD
GKya9azUZuLQNLPDToOlCvYyOgxC7DwAJSzAineFxmxudrjNaala4ME5f7ber08k0H7a98KpnWhr
7Wj2/ZJ+vEdRg5LF5JobYzKvmpaM7hGgOO0Y0TDtIOO7HUt3HbEwZQnXW67gaNwbS1SMvRGswaYx
K6wkNU8q8NKtgBuc+BLolYfLBZRJcyR4yNDpU2ZjHuWIT4ts/OFFXInD84SDkSXjHApALHfZxsnt
cTfPbSH8fDmCJm8Vuoqw1xgU6RGcrAVPTlI/Bq6t7tCPO+YaS7Zc7owdZvEsNMbqoZsmDCFe8doV
8cVthfoNVR0f3SFwHIhWyLqcudCO3w5Kbmclzjof/qugz7XI3W4up1D76MJKqi3dcnruoFlabFxm
tSwx3GSlL+5B2O2YixhTq2xSfw1sszftRCihJ0NMSoRqkcjUCZWV/isTBo0MmbQfNmdasTOjZ7ew
2BGPXSHQT6V3s6XY14QEqIGMHPF5erZNNQZhY8yMaHagYfd2U+nuwBd7aS4EyGQFpNTw3QcKE37V
hGX17EZiG8Wq6MY/44BXOfTCtCeKo/byhuif/pVMsu+ca4R5zGuY3CiVWYEsPvzxF/qKifpxZi51
XRmtFk0dvxCb9LZijwdOxnyH8ZiWDHs7mJnDVpcWUMPZU8IvqumksK95mbWFPl5LqmMFM0jEs8PD
mTfV2GTjPFDNIyUlS5wgr5mAkFV9aGhFTJyxgym8HJTFTPnH5yHrrcc8JJLtN4hU1di3Xn1fE3uT
opoRvS0bdUapON9OlwVhd26jM7wCZBYB6trMJ8Mp76myBkkv39NINwvcNz0C9PjTC2KxxPuukWtR
w/yhSCjv3HZENtmeUszZgrIUGEER9oAiD+owYoWYlewK0ILXabNAqrhmEBqBHrr9oqgbcYRDzuYy
tXp0TFqhsCtk673OJdQGB6Oio70EYcvfK2+/+lQbm8RY3MMrGTIdFT56B/KY7jNhS0GK2TQxwqhs
TRZFKV/ZJk4siqHTytH15d/JDe5gR0ZT6YLiWctRZ0o7rDFAuWGOts2T5plZkYkKlicuij/brRUE
VoPwjXc21Asul2nGZ4oqWITvNNvqsSj3pZcib/NkEb/ywxjqeutPrWHdY2z9bYYV0afl6iN+OJPF
mRYM7kLjlkifzhHkjMHeNI/3PFm0mygSZsjtHDrFRcYjNY27pFqwHt2ydv+Y8I0N1SDHvn9BLNJu
oFVKeuo90KYeeut8r9DrRTYqFOonG2OEQDDLAFRufZ3qQCoZzCVAz2808ZTxpmyZlUrqqRB5eNoR
fjg1JW2zKpsRpYXTmNQeMRdldk+Feri5oq9cGD5YRVbI8qXrgCFVgnHaSb6bgNKjoxu7ljGDhDlA
fyljqWnwjpwLnJrnLEEPxCA0T5/et2QButOgW3nnwmS1l46RTyIuJvDC37QKPJAoZiXW3NONxQ4S
VMkIxUni4WFNp61+I8ALmhKWYBMnSF2olRUJgjx/5EoFbnaRnuG71h4SLeOPIDGWQZc0jBwrQoy/
p39/L/g1wLZ3FqNDV7qggQZ0GMY0PqS78funhvJ8e59DeuguR3c8Qw2C0tcThu571K4wpX/OFbnY
beeizjT0zdkHhRSex+8gBUGhTbaSXFA+qwXR9xCY+C7zYRTKO8Nx+cPPqtw9pP9PxBswmjqhEKt6
3Ck/ADyCLZdGREp/A68XVGVvHb/JvfOg35vhDTnY5YS2yaSxtOlTrfweIjcpHNm/KYIfyfc8tE37
vQgFgsHKTN1WfK5wTNKf7aRiY0HC8102JHI+A45viX2RWjDbdLJq2Y7F5ppx0BUGXajkekHFHtTP
zGH4mWnc+ZM9cxpDbZHg9CWY03g1SIePCaPv+IQWravG0Y5/FjoT60o3H5FyFBudgMVZ3cp8VzJe
LvD1NXLx34aC55OogymYf2wimfHqDswutWmnj+tuNMEDOInqQNq9UcHM/OyxxtX8wTTT/NRUFeVm
VeKtfofxOPU4GgEr7q/dgpmmyUwpJdTmUIWgEo/EFBgHOpfX6wnVmKNZLK/35u6h5zONTzL/dQna
H6zFQ6I+cQKT5ug+al7l3k03OO7iBB2zXBSdPjOWpTtDodnsbHMw86WcpUsjoqFkiDJh0K9pAiTs
yu0YtLXYhpLRc8vLx+nlNPLnBlewheD6Rsel2vUITR+Y0R+LTIVcFizL3RkCWpgT8Mv7GFBus0bs
tXa7x74NoVvDOv16dK5Bp6co4kem5MjsBMqulNnb5qAiSRSAHjJVEcbgiN/ejphUzKhhnQ2rLlmR
J0srKz5SDkt9GoLIIQYs5LiQz7IybWCgpgj6AsAgzJv8o1wGzGOJFcuutKhU3byY8gX4mvT1mcoL
+oV0fltqMUZ5+7fYGYXRzx+IoKYTulFlekV7KaIy6pn9anlT85vVRhfq3tNZZRGuUALVSiHKp1Bv
hSH5jlo6taMLCDODPF39Tqvftq6OemOjXklUiPQyYpE3hA7qrG4TTmxYZzDSMPUrCpTcgg6vjYA+
icfYFMU1pgr4fLmYJ0fROfPHuGJh8j+aeRnjdDL1S9T5mRS4VQFv2nBpMet9lpa4++KbevKGFfwJ
BO0QF4h8xYmLMoxmJE4LfilYtw9dGxV5baelDnfq58HheZD2ds1QdE7sNtEpXV6y/daqe+F0IrwO
EggItvtulBViDAFHzzEs4Ors+9e3U7TiRkh+FQouUA4zwFshY6xGA6Dbnol3ZBzdaBUiUM72DESu
4f8i55WEiA1ksZPV3YoWd/4fFxoy40yp+YAThVsC3PUgYwIJd+HeGGy4QmzfwbeK+mDAR9fhkgPx
nzDL3LV2Gv3HmCCLPBRF3HWk89YHpBOvD6r+uOVfqkM48561HfV7l3A6apzVHxEOEh1IyTyiN4f6
3KVzCDqCvavPKeaSnkFs20XLbL+sYELy1lix4/B4BOvvSBa6muSI5EwkO9IYHRp4SldDU/BoT6Cf
qRS1nv1bScZ42MttKPlYo5C+D45g6wpNReoA61TtaIEPBZNYtLw4TsZyYTF8v5ZzdClRynhRzcCS
TDxMcqXxYDSNoJqUrB7zcYe4AU3uO+Tj6wXoA39LLbsKtK1EY16dK5eicLPwSoFRhW+yHzcF2R0r
WPJGyuHI7ddZdu81doAYgdtje29f2PoQ7UdSTUx5TaBtDIJ3Rj9hzUirGokvUqbl7/aQny41+3XL
F7yI+f+1hfB0KztcysNAoH/Ef6mEeMnfNIZ1MWfgKXi2mHySkygQ6NWZ6vvA1E4qyMJXH6Ff48/K
gOLCxf9q2hiWqZQnp6Xn75CfUcw3BVuhzDPyLdr0RuUnInmBo6zzYXmuhUgWD3UZOwbOLMbQde1E
4+ppigWbA6D8yjjDH5d///Ez3Ge5UANdGKtn5+zwt6sVz/UnNbLaIxHavGC/XYYHjVzK8UBa1goj
rRjxZYq+/vP9jTUVM/We05Tuu6Vhr8Xqgqbs4LxdLvSY5ZRtfkiZ4ZCcUX6PAd4EH3/mr2iiXXwk
MaHxtETB5c92jL0MYVhAngHcoQp4PXcVgMM53uyhUPz7f2ILQV2YDlsJucEYfDq13cpM0FlEQd0h
5mhrSC7d1cT9pzwN/S9h7Qh/HzA8ELwUmuPuJDo2/TpqVz3rFrdQd6zrjucPEC8bNXyMJ4KKbI8D
jSOb8qPFWrNmF54vmxSvOh/OuuWoD9f3nVoFgkV+u9aHOriGCvKVf9fo+9RKQjPtDXcFXUfhU3Cv
MzmWBqGndqHMPSFCJwZft7uzO4LOPPH0VfFoxWhRynQwCPBocMx6x0YUJV+M3EFU6Vu7E3kJrFsl
y1fn4yO53dC25b8g4zcCCiBPZyfjr/dEPpI56AfsYVso/JiXvsCGk4Q44hgxk7E2o05UqQCMycBS
ygQjxTdflOik9YO+XOKbMzwwOKB9IrJf7iEl2lQF2K+TkGRUH4+zgS1JhcVqHPMQR+DJxVpWfM0M
H47wPKt6giCxmkkimy+FeHTdZ6hz+24lzsFu3UbXHAwWbAtim+kz7tWoUwDCuWtRez90LMVibV03
s9OTE0S01WDnqkPCfv23N97xtDZeKpUclYjzfg8WN4IphB+xKA760It6EE+vAg6sslhPeEtILCY4
Uo32QdRhD4sEjjub54P8JzSNxRxNbgJXU+8ynehszPSEyuxl5dDi1AscV5lkhXQ99VE3kbMI8ilh
QVUy1qYXE9K5fiRAV0MgOjL6GGRYoTf4n43A3FTs90xm2IHT/tG6dfy45aY7VCkDyOLAsNg6qbjb
S+am1g2mbZSI1nM9RhmFc/sBTe78Kgm7HWfCi6EV9WsWjqKGa5AaRsASsm7bd1npnUKXCxM53zTI
77Gkmb968Gfj1eaXjJQdf892eoN9RwJPsCC18O81xXkHoHW9rpUzV/NkTfGJToNKY6n8O/U/gp3y
AG4NmQb+ohRjIbQrMorHExbrqsFGL4eC3yc69mOV+v1CTYsqda7U3Kustm/djGTSpFqDUaNUmNv7
s59H+WB4s7H0P4v0ac2cjyGb2JiekKYXjqytCQsMiVJwOtyNM7tOjPKEr5DFyVazHv2pRLOhaGVG
87WLyoRqDpuHLeZLjrkoa33bl1FYrCa3J6+jJ7/V3xNnIZQChJxZvKwYAjZaE4fMV2ZZJnThqFaV
jzThXMsUKhts7V+pxPK+9zyGMAfbJb+gqTodEbZFGJ3uAmuFe4/D7u5r4ULee1EtBh9bcw2j+Ola
cNtHZu9ufBxtKXSETdazieWpvDhS+w9bsCl/1kwyTaNvigZTEXWAX7zN8t/Lv3wG6d57wx/BxB+E
F8OAUdaEA/l/kXOG0XbxRG2wQEbzuLgDFSmrE62VEjJinXmf1q7lMpmlsJOGH0t6Vpx6OC8xz8e0
9F6q/ODk0dxRYn1TlLWz5oHLnk5CLNiWA8DqRrYx16q9uzU6zk/7a2dB6MGsTzhiIU00omSXkLY3
uhJSd6oKTQspc9w3uPCrB095lhsz+vGhD4iM4/CS2HsS0zXvKKDnVX6r6sYwhAYS1txJn8cHejTS
33a3FzrLh/Lr8tihbnmzdHQJtk+sq7tZb72rWrEbk48sbF9yJahsTCRqNmxxIiHoM81CkKoI+Lxh
cfc0D5Yp/MomiNvkLGAQL9gJNP3W0OyucO7MynZvbq3xjQW7UGuTkM+U7elqqbUSHoc+YvoRMbS0
Wra3OUa9vgiPvfWOPUXkCzQ+GZz5oh+zUdgV9KFSEg78gDsnyyeW/ilBD6TtAk9pe6QKH83lGlA/
2bWItSalCQk+8HJxYzEowKqYFGa6IaIc9tMb8mXj8fSJrYpmGSaaPDJJbiFsHkgzUgKFO56A6/eF
ldbJbZmhU48DLTEq3y10q679uNFxpRjMbj1VLTSaUJ5hhfLgA9jgL7ku8ypfmsyML/AFtmtYlAYS
x/hfNfqd/HxrFDj4suOVtrsEgFli/p8rQFuk8bUKKi+qMACYCmucfH6KPKuWAuxGCuqam7J+SLhy
F6DV5jjns6q2TiCqwQ/SFDGGwNWkiXwsljkpcugaJxrggWO350nMbF0QYxh1wDeVmRmPTvIktQeN
C2vym6ToRxoNYTF2Tp4Y99bkBeDapsuHhs2C3sEBcQs8X6JL4hEvCnkrhPhAFYDvUWiWd97v1xEF
JXyVXUJkVG9BXgkFfhxRC6VBtIUPWaRXjsqkEhgA4GfNh9Ato1kt2NsNy0Yk0TuxhhyZVCo9JfjN
xOUbhJqEzzlTH8+IdmNPKx43EGDT0Lrsk/UOaUPBvFWdb3GqIMg4TchPjXgWpuyR85DLNpqWKB3K
K2K8dzks0hfLCIP0o1ZrJyaV6vTRLX6GDJX6JZRDQIcYVYCtM38a642Um1FZz9czprkChHqQfL3B
NzQrdtyK7LIW3fUDo5pKTkFMk/BrlxVPsmRbDFKf4rxCbgZA+dTNUmlpBauC7VYTM5YFkM6wgAQf
kvhXW9lkApSLz8wKN03C6wRC66r8yh/YqKG+OjTUsFovJrTDokQK8MgWGIzpNPRCNORK91DK5GNY
HEXIaZzdLIwnRbeaVleFh1M2/3aFZkINsBeVqebQim1r/XodkwvYfRJymSowdoWJn6/gXjWYYZGh
nHpo+U87TYAoe/0bNSftOYIRvEYmlBQPHk/YuQ7Jdb5hXqiv8iaBtaRv3kWfgGc6JF0PyuLIJmQz
sePGBoxGEAi/gTPFAp5q7bYdVvVh+ebZ1KPCkgVP67PIAZMIBdM7ytHOVT5vyhBUSnzHGj7tsaK/
AqD6UoWrkSts4FsZnh9O4M8pkE8Vm26V8YWdgHnDnz87zqQ/CBdX9Nf6pLsk7Gm/k4IQqgnaYV3Q
djGKNtk3QKG8x7u/AfFVjfC3uxos9Lej1HjxSt7yMGU5UStm3a89d3ADmdllSmHXG8oaJwgC5yD+
6ZyoV+S6O/inHAAITWTqNss+CZq3wQ2fSPRm3iMIYujSFh49ZWF6Y5hhATGZ7puV05IkX1gc8Ela
qcxST2cD5iqJ2QwgOpu3pXIdq8sop2UlJ2ii2/Ct6PF84r15S+LX3gLwJ/KnCGF+GUwOWmRkx3Hu
v4EWljx5OFiNNQjpL6/VF8J8mZgV0Yatyn1p4Zb53UROPaTcM7aRopMguRKwhgpbxYt/+eTJW6XO
DU2onCq+kdiW47TN2oEGrRxvPPPOq8/oSOfJtP28+4j2QIWKpNEEkyM1waSHRIK9ySAFcsxROSmZ
y5VUaZHpge4mjt4o3wek/wS6MwWVPMsAu3hEPxAU1KQr/u9URt3MMa2fLlo4iYegrEEYe2yLrrAN
jfOlfFl2WAfnBn0q9dqaZPhtJGkjLcv87aMFcrI8E5sRxgPWXNHe5E3yM7fFaxtQ9czAwy5HBQ7T
gJgBJSPfEfU8e3x0JPGyrdeTDJ3A7ttFutTZr1mNDvkDS1bKipmWU7JPSOW9iMIXgy8z3KaMV17o
y3aq0spIkFtfHwEMlx5tdEz8T/iwPwSqX7cnQdq/VsqDUNNb4SVzr+cYcHaGI1VbX/0HzDuMomQP
8bBDfD6NPr3YWlufkhrsbQfYW7WwfFtn5mraBA8+uYpAnFvNL1nN6ushsbMR1N+vSXjcYN5NACl/
H2124SzQrgKMKsLqQRU44LOU1vbHbBKDecnaquvebNH7p2feemLLqYcfbhQerM8RTzfGlW92BjUa
pGu7s0UvPCSvVvGLI6kKWChXl/Ug0dnDJutwDJbPGIIKIcK+2NPBDWx7NvZcgk1vLArNWzWWN5i0
Z8dDhZ6CzgsX9JZYvHPLyXwjLrgSDXp6EkJ3xaVltlxsSPjIWuSJ5UR2t3a5j70+y53DA5hawRIJ
BflpJHyKmzPzoIY+XozhC5geLbq+MLSTkXTA+Md2N7j1po0WdpbtlNFxKyHKeOmAG5tXoFNxuonX
NfKY106GmQh1ErXt/sv1FnwsfMlB1zi1P2UI7BNRKZFKqOrCBbJHJCnZXGXx5HE1jHd9qZY8pcf/
raU+1iunjRWFwqi0m4Q/8gbHQTiFqXI0Vta3iD7PfOvOLzc9cuejpa4JY/ddtS3kX2TIpZRySbii
XgeFxsoRZG/o05PSNLi9egYTmlUgVS8d+uK+3hIvzh7l7GM7KBHA/q9Nsn2MXkbuM26NH3qxiAea
Dn32PsY77N/kRaam/N0h1Zw1y+Yze0k6Xo7SvXAa3PeIHINvxYjsqA0DUbJAr2qJQ9ez9vPSqTOB
Dhbd/08MfHVAhXHpF3fM+00YOk9kcYkG9Ri/eeixt2oEDZaKzJLnnoqvFxeWkGjVuZfdk5dOu9v7
ExEKEHZo+ZvJiEXLjjzmDtZFould5AIW+q3ME1xdRFAo48yScl3GdhltW7oIIwCbxONHp6pPH1DB
UKn3Dh2Z6TWDBMdTMe2/L9TS7lojLF/dKkQy/l5IxcOXSsyxUWAVpL5ZrB9DtijZUUpLiHlAFei9
Y9Z+k80OmqZhY2yO5s8R0ALs1Ft48o5GjKhCgHF72iPb/y0d1jf95FfmUoxwezzrhskMaOCfFgg8
AphxbFX/k+52qiLuQkjtJScwGnNfZDEzWfMjSThKXVI/arwQ7Tn55JqubDkyP18b3uYJ3czC/KiX
yv+ED9+8d35HV+DzUtygwZY7rrisICcU3NFk7cc8i1jdolvkOva04x34YiSWT+zjbKj39iDgMJfP
nq1M1Ah0h3m9u3TgvvOjbzfU5dUNe5/RyIdK0LTLLKGFZO1jZL2P6ntEgfg507gCdVHVavN3mTHX
IPwxe6Y6aJ52LnrwSvqTlTplUK3PXqyywVm3ukSQ8najZI5ITtibqu8sJzJxPESP1h/CGEy2irf0
tKuFjzq4iUmlE08KwGR6AdQ90uUyDZ7BInDpap0TUFE2yqj+Cmg/RLdONz44miMbIJ+DAxSUi2MS
CVoaEGRDgZX7L+1GCwlSyMt9OauSexn2E56pMGI/A/PNjcGrIdxkutQoK2YRlg7i6f+wNb9Y2gcM
YzNWLYz5uyo3rNjHRcKm7HEbiWcCdoOlOc1k1c55wLySin4bgMGuA9UXa2pj15QXYNFMeJbtfhwm
ar4+eZn5WyZ6Q7DhbN8CKPpHO9TyDPvVgQmrAQcWSBAx1hC6wirnvf7ATJlrz+DmfHI9E026mId6
KH40lG9jMqfrWu7g7s8wz6nIBiamEhcd5objUHUEmMKbsASQjGVhZA6QbCbgAukMJWUtjQs3kGXc
FgiOMoJpGeYNPE8MJgGTMl4eB3OVuQh36cD5wqXzYC8GP17NZ/0WINIk6TBXOsOpv1WCDSwhzshP
zuOsK8lBIWHJFZMEZp1ygQP/cGs0RyCqkD8ulUBTV+K+EZcy6DXjw67oee/ALKZrhgkjW/cAGZxd
eGZowjoQwZjMCPMMu4WX0cMnUwzIo4hU1IQi+ktIpNRZkliY3/li31LBpNye1mMA1I1p7/jq9Rb+
No3LbhHCont+fMEy734+6OiLsjBXts+/ro+qRqYFtjyT+k0RFo619T77Yp2untdxkjuR6be0s93j
vPwKi2VrjYaTCJbKSM0oj0YtWmM4nSWlNLkS2h2rjbGdujgcDPlU8I44Bo2G1oMGiCui9FodkZtG
kOBqtjbv1R/z+321jpGACzq25FPJUSd1xst7U+0GLp/EzuEpptq4ISk5nnvG8OpY7afVlV5aPFsj
MBQKt8uSzd/dHgxVjmPeqp1cV0WABPcaLzC/ehxbi04Q
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IVxyk7XRM4VsQcD0QPYws4xsTeDPKdwWYfreQJ7l1z8C+G+JAKZ2psrNI+b5ecZ2ziPH9MBGr/oY
8XtzCKmjJw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VO3Jpo4aYF9TyVwyAUb3a/oDy8Yhm9ea/9mAjNtuOBRL0qoy0/CWzL7D+bc1SnZvEP4BG903Ildl
dM2y4TNyVTBUaU7Cz+LzZfu9kCPWnmttlx92LcMKLNuvGUMPXmV5jr3PzSFEvoDuCinMqNc8uKFO
Ux/aX6fmBD8AbQfpK30=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qOkimDe0rSU5f1zKvoE8a4lZw1WOOUxh8wtTIN0ys09AXuQuNNCdfu6VL2Xuj0Xus09sBU1FazgW
XpQHuw7XcozHRlnUFKPJg2P12yPJsLRkOqUWtHTUXmH/8s2RglOoEcmFeX9FVh1IRMdnp+D/F4GX
/80OwH0Jtm4eUDa5EFkNoIfhlOG4JOG/JCsYRnsAoZAbyHMEk6qPxdOGDrYzkbA3CMCikTuE6wOm
0j69ZgENzpWR5aludQDu44oKZqgkdMKNm6Mvk//s2aUOTBYWabbSKe/I/+cEp1tWS7+9AAmaVwO+
KwmsZsNR4Ztb6OH4hCq0936o+bycwR0b+Wr1VA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4df1QYXbx3PmA5i1scwSy/ZAJgZ0wNtl21eeCeUI5h4IQD2UalJOUkc5a5UR/j7lX9ToyF2yFHzK
L4EoH+xXm54bGihfoaTvocQQsWhCDObbmBOtqB6WS1/bog7FNgoEObi/E19vJsjPSd6nCCdhglZ1
j33mJRkZed+lVziTR/s=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Rtu5N6w0tnewss9ZQUyM3gMzu1D5Ba/+qJO2rdGgk0QN5Nm+4TaVyiEXzVM5DP8z3mycaRD+z4HG
QXarW6RH4GHKahoLlSY8cryjSJRWS6D7/Z1joY2fgJb8apydMguGWjRZ/uW6R7BEimGxB3Xuon63
ZdpcvKZmoyvfg0kjAjor/DxtP3SP6DKxH3BeegGQKpP/+5EmCrAhhPu+NA21340wcbghotvyYusJ
ErSZhtj+1FLwV2sO7TUt1etBG8nf/yETDQPE7Q+zX+BzOktmY3tIKds/9qdyDt6Qb5WIxLMyaMa3
eyi0SGAuZdeDtK8Os3w2ajEZI+VjufruVqtCCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17760)
`protect data_block
yvvRtu+tA91Rtyv3I35O4K6BiUlBjs7LTFLRc9twWgYZkATXrSpXZut2NlvE8mcC7mB31ueT2vlU
P9hzhGYaJ5GcmScpsC1FKNndMfl3Ug9Pqiw49YT0Xp/AQWIr+q38Pu2DmkLm87YVBi0HN6JMSu6G
rwJt5qvXJYVA5oSnqcy27I93z0KCdBaCW4BhEaXbMLEY+qzcYsWxGhgjRzVfC2OhOSpdpDr2MKHw
1YDri1cTZAVy/b3L8VUTlyQx4YRG+qS3u0Cz3dOLm9nglzh9Pa9XJC4+Lnpli7w7vpvakaXaH9W9
I9Xs/9ShuVul4UrHUMsoz9V5jcPh1iHPT9m0ZTeLUdfod7NEEFDW47vWU8XjL6iEqBvA/DrJKrri
hjJ//n7fbl9gjxGZT+IKqHleRVz+dRiS/uTuRo22UsAcWrLoCdroE0x4MAJ9vC0vScZa86PQBj0m
ixJFhU15XHesAUmaWmkIVFZdUdZL6n63C2nZpQmpBX8G1td46ib/xrjcP1HPzbr1hPb30S/GA95D
4e3ICss1yPb8NZCwvzZHNKYRJlVJ6EOWwDxLeBOjWmUySMUcywo+toi8FWztPmB/Fzs/gyRSBxsb
FBe82kj2NTjDK0dD4XCcU8bGjVOKNJ3KoJmC+0UD0jihX5N1CdPg7+/bvmP+MCdk3ondXZKJzYI3
9YFYkr0RM2BhF57jZwHcHHmFJrakmG38Lap7lsdonuIO5mfOOuicr4JGW8Qijs1+c7VMc6LUwGDt
YKznnHTq75vwwVLxmtGYpW4RTIuqlZmOJwC34kp9oVx0+wFtUxMvQgXry9FwUwb2gSWRseSfbmMB
auDz+22lW+enEoOu3PzG3plNq4oQP2K2H++ZU7HNTNGSA6VpJWDQ1c8o+i7+XEkyIqt9DZHUxb+3
HlbwgxRkMYX88B7lb3GnNDLF2YzkJMgQjpyPi+t3N2MtquCFuqNuaKv0LoD6+mwRceg/hAylp3x1
m9DKQ0DcKuhctFlcx3aOGMXc0mzgjh9Umxn2Ng7JEliL6/L086w36Jar0AAtsKsXZ1NsDDBpiIeT
c9pWEQj9ud2144CtZKOT9/hr1wy8/jpi1lQaHanlWWtc/eb1aDpSY58hPbltVjUTyizUFFWsqQAC
PGoqDXF3N036pR2Ipsz0lKGQE6qHOZ9IQByoJkJfVJQFD7arWnGsW4G4I9tdTj8LBH1I0/XQKvur
lSNx9C6iPx8J8GemXPHqEIipG+GgoeMURYc7ft3GzrBdwbTFPm/qrxT/0vdju3tRDBl4JSzWO+do
z/s/CD6wNYNcDBCSDKcprRdML0+tkUYr6Jexl5rxIe2GBG2XGRgBDqc+wBSNJY7VVfutmSr3NjPK
RJK5NldZFn8fT/rjewbLV4flhMn1tgsE6HhNm8GuRS52PpzP+BK3fCtYvb1mnkFy+e3mwc3RgZ45
5iaZGmsBwnJwI9GcgMGoWSDkSaL/1PrI03WtUczFAidTPvIY08FA8CTdX8Bo/j1vK5yj8spVzrNq
2YNw08dzyQOA6p4yaEO8Raki3qlKk9oCGUe72zvHFj8EIo6DPYz7MTOBMZh7qLr1JDqBA+iyQCSU
UO9dElHR49OYArhLqejxnXEbJqi2McLLRKhJoiH7B/feWKz5mjNEjtWpHgiwx6VhyEKkL6UZ1Rib
ZtiEI9gtUbhZ6XzaYm3TiIRoYgTzxH0j8bAv7Zy61YnOi5ds35hrlF48AdxPXK/eT9RxLQ9JC4D+
xhLyqoQdstrt5DgaM3NxG2mKEJVH9uc9wj8j/rmn9YrBedhVek2F8Uvojvb9UP2S80Gz13xgD5DT
uHlDBG0pjratONtNE06BnMLwZRtD8fOAmitaJqr+uurpGUSmFSP1C9+FHTWgzBTdRwxLO8vYdEOz
WFiLspZhFCxJpRdUt6N09XI21qtC+0+ZgVoJcuL102pig2HCGw+mVSkibp2ZzBHApj3TyyQWeR0T
soE6qVGrU0cCA6w+mgSp/LpLjFALA+nFAG3lXPvfyzy3nWkgcWbCXiItZJY+SdblaE3tEF0j7zRy
QEv4a8Rg+L6tHbS4IhpoHW2u/3VbDszbEYb4sRKfYUA0hAwJaM8jOAxyu4YRtJsjn94Jek1Taiie
hp0Ndlnhy5vlx4q5I6i8Nc99UyR9uhRu8iqRtT7nCYuJSAzDby3Uxqh6srwmKPrb31KF5pRhTgEE
hoDR5pRAhvr+p6GEHRm1IAJTB/vA3Cmck+beIM8DaYRIdaZnzC9N04oH+sWVHExAUc9WW2ZHotPC
yowKFvokfu+7look6EHxqKtkI6qUIsFrQgy755fSnh7+GR8EVZFKqkRCDv0zQz3m3MIaUQ9GzxNA
nVZg02l+SgGZHXvy8wOZE4ONpWcUccgX9k8Mqf2VrJEhn7FTdwr/L68VLWlWyJ51gTID4qsEbmQR
eUcVhXwZ8J6/Jr+tfQkihSE/r9/FrMS9DtCeXZFSTXFkRXX3jwy08FYzVkX1AU3nfi5uob/pWe44
jJ4c+H4TgTK/YFd0U9+b9+hcQ/PKCmyuUWlZMD2jh2m6YaM0tRHT7pTE3k+5NorK0KIzBPhuhR0P
kwadh+BfDa9Ed/g8FI4r9aO+bzUYkbubz1m2BkiyrHNUN4b/jhDQyeuJYsvVZmik7vXZ6GcS1rnC
ZJpUE1bWR8FcYhqQoncmXGI126qn791BoIP3g9UyBSGDJ/hK/eFW6lylhaaJjjVsKepmxGzcVN1B
mCwVpKVdTSGBmK72htH5om7KKA2S1rC5U1UUj3MbiW7ZNwfDd0USkl8imBDLwgYFtoEE1ko8C7Jc
eUprl5A05bpIwcNw4M1zuvcSJzD1rtWdZQl2vo3uekE+ox++ptfYE1O4Xj/2TqSRnKWmvElAWcGk
d1P93oZ45PNjviXZ8GjPM3O0qWdvlgjvAq0xdzA6x0TysB9PpseLW+g8nB6svNvi0GhK/LLkeLYg
V+VOQradYifDOr8PNb0cqid1ncvsR8+c0tlZfcJr23pLfcE3Vqz5wPmHYoK484/vAUmQUEHiXjLv
MiKyjk8ywnYHQ/TOYWuO5OiF3b4XtDucLmEyRzxNB7rY1i7qaj6wGs15PP5RLOMaDOI9Kg6163IT
YHmjt12E1isvBtgqS4df/zN19hcUsAr+Hd+fpoCiaRD8qfZT7eD2F7aDUpS5tVOH7gVSyJWqzQ5q
Obv9Yhw7rja/O45RtfCLUeQNveIdOxbYJdxtkbtNUL4THMOaUooUKNDHf2XRJ/IU29P3yYsch8DL
w6GDueFKcmhtTaLLsoIw5tztfz1OnR/Ji8//265ufazAczEkWZEuwDJ820UjB8sYf6rqgnsGaFMq
k4/RqF2vivZ5ejxFZq4j5HxYIkrT0dvfR14iHiz1gFBjRkaPy0KB92AudlRi5GguJSj9i9apnV0C
9Q8mNjw2IhqKOYuyV9e6QbBpKJ96If+glayPM19wkoNu3wYrQpc35Fto6fYKFdY6dhE8nKPhcitV
/uItKlA/SbBd82Zd2+R5YPNcmQq0sWFXHgntGjncAGogKw7gdfoVMOM8623k3ZSxgx+hl1hERb55
2VAlad1Z2TVWotbB4SU6fYbYbkgvMzH5sJuCqbAAKfcoPFz1nWbbyWa08tpLEd7dFgSfxRMD6emG
vbRwvFQQjTUHayp8X4YhTp75/cn7s7BNav/nMANVwbzv+7PlcCBDE/FAkBmre/mWCARVoeNQi9yk
Lmy+/QFbBCSDmgH9dT+J0qyptUReayys26DpOx3zpnRbUVqoevpDLpdsoEIttEWQIhHlgFCwxqwE
aRk/jq630RhYJrspYYhMKJx7vBModJIEGer5px3GFiyOMr4+4I2Loz4N0yOCB4NxzVtMSM+DMFzb
Yqmp3TY7W03MSy4BUlptWvy4cfrCDCrea8duJ43frMTKFTfbW+IerIgRfu6o1EW2xXm1cTpBK1C5
GDw5N3ENOo9k6+Og7Rv6BqrZrvmt4KofAZpoRQwtrvIUEswUfZzexMH0dWDua0IDEUztjkju9U3k
MYVajimuyW6IXCYU0qQCvsz9sBM2LLZ1x1Vup7fB1Ec5aPwU/UHatOkTm3aX0ZLYdmaCrVM88w9G
XHeo1x2sSQwb3bclHeYGqJ5KFtGY8NkrjA2kOqD+X2jo651hd0o8X/ii6dRA1MaQa3XRL48KOtEM
HH0PUmnhNz19o5YiXS60R4NMyF8DBJ2arUQqgtrBdHpYd+zsNwOO4FJe/HVkB0g9fp75mEMH5PiJ
iCp8PJo1jsqW1yWtRGUFGwq3z88uUmySC3W8F4jZcCA/IVM3H1z/nL/Xi6GkPU3ho614p2M5bRq2
14TEYUDIUMMz5OS3VFeKp3NLgKmCpVj7tbmiZi9T8Yde5BbWfETD2YjKPY4NPYiw4TNz+908oHc2
yTbewFueWvL/NaEUrh1xMwQw0DRkd8xsxovrukJPMeMMIOpJVuHAqxeQFIhjwyO05shLRO+8ICOY
lVC8RDu4KIeHaBIdj78ETsgHAau5157cMpNdCv1z6u/eAEhsPNaTpoYf5z4Ulz5+vbrw+Ig6ywPW
AC3chkAwdqF9uooKaqUaS0uaMYKHDaK2y5UfVCBUcfko4mCk+jjZbqPR4oE/RY4mRKF+S5KVRb51
goeafsPpARmOwOZcbpLNMXGonqOUJEFV7nFBn0sn+mMycGAzE+JXd2B03sI8g6vqICD4805s8/Q7
Q9RvYQCBXt2A6pU5gu9eZBujlJ5yteDEmqSPNTNLHzUtnYMoAcOjjRN+mnEfti3CP2YaqZYc7AEK
EmGhccCK28g3Iq3fyEIwqSG5ZMQqTqoqd2RXD5hdEa8/QoSw8h+tBDysQ5iCskiecYnVoVm2sJ9g
EiFptSQHJIy0hyW5bqu4IBzo173gYuxltoA/x0vJsCyFYs77QhbyJAFsJLmGHqO3cT9lndY5RmIe
G2IsYZVzwYIn/hCH0vy7GSobNYDvEMIvGBaU5p1UTsf1zLoaBwNW5il64Rmt8mWVqr6Q4Cv07zk7
YKXZHTXhEeAgsPcWekKsDPhosTQ1OG/Lbmqe6Xtt932gr1mKpZC9HDG0zXIrXY+2oSE8WilO1BRy
J88nrrr7Yu0oYnF4wZWHuAWIyjgLKyWWX4IP/WRaze8T+DWjRzYC+x719Lw3Own8W4ws2iTfKhys
/AoSQctmniBEUleebvUzkP/54oUfgrmlSFnT+LQI1wpo2T+VfQtutqXZD+Q9onWKVVV4HeEbkZlD
NiZEFqgI7BCHMNKvyQsr+gN3d1+ljxpDWwjLTifh1kNDK1FTX628L7Esv/ze15vf2ojo/9c1/gl/
t1SV+B85OJEVM2ghrmoVc/L4ECZPJK0ZQo5F/4K6TFqIGKCvu6JvWCTXCXXQuvIJWVCf3yQ+xB28
CnIRjnpjYhPYNojhQfb5Zv+GZ7LFqZZ1/o78veE9yuWl0lUlNLkf7AciAMp2qc67QqLSzbmp+IIZ
GRPGcMLDzgqZMu5UoNLRtDcIK4IdO68RfVU+DfGj7azU8UasdLC7EXFxENSmQ/djh/0I4Ci41R+q
wsa+kmx3eYs+rFXPF/gpMof9+m7gcNIlaKRiKrmGwaefZwbiLS2b5ZrIZ6dIXfBst6s3VP1CYaaa
+z49NTCU0GqV80EBrXnRQ63CMSRECEHoQlN/WGzyaldjxjHPYO9Hmx4A4l37hy0X4CBEgwcgcLmn
2IaYATXcAYJj2x+86KLB5ybH7SyK4Ew14BYjahhIhbE/HpiaKw6srEVCnQJsybU/L8kpmLrJFJJB
A7L0H6rsyqypQ0Gw1vYRNT/Iq1SfeeCbJucKyPaC8FIIMxhLscoBs871BAGV6PnoCQwWlPdh7wt/
cV+rFe76p7fOp7y/iWBGEIZ3hi+nWA/1wg/Gwy2n5z+TL5zSsOLvSN/UaFnaFFlJfzsshhbbzRjm
u8HmR4iISYlZfg+PuCGg4qWDzTm+W3rHe0IKKFdTl4GXGM1/EpTtOAqbIDIWKEIZkJ5l8b15nkSy
kXA7m+xG+B2kCr6obeLcnH/Kll+3TvkRO20Bb17nVNUb9o9OAtuAZf0dsN0dkMWVbDBmARX5RrB8
Xaso0jhmy2GD0839FOGPRmjq0itlZIHy9gyGxFuelbdXGBP7YJlreCebt5nS69xLW/ntBMeaobHB
+fuRF9ZeLz6NIAjircenBW7v07uWGziq8CV4rmH/bVbBQVpgNLXkN8+irSvzIih6+uQU+4qnhkGf
6DPM1CIN42m9ynyzhboG0MwLmsmxfHNu6W7pdDbuQK0nD+bziOLzzqrXLBnyPXGnwpO2QuvUEpHz
JbvGAC0fH3+ZHVgO2K75xWmD0ckLOS8k2Z5yXiDsc+mex5g46t0h1hrH4Yyvs+xHhn22sZ5vmAd9
z+TAxX31wRoiRQvb/b9h8k+DfNRbYFTRb2ARM5f0wglZ2CBCHU3UDca46UnCcX0s2i8dCJiik+U8
1YIMvzM1YeyL3p4mMj0N+JIFkUtiWw2Iimbj4Zp6ofh5N27FA2Lw2SNpuIQppGII0um+Cd8fl8LJ
wmvWzSxiUir0Ax11Yq2EPE4jm3nKtv2sY0E6lx8WJYJydjXzqOwe7I/q8cblI4Vw7LJj+vuX/Vac
5mEUxAfQSPmHwmPnz7dWxElLo7zN511DK5ZEC8GBtiK9/m3RoIfI1+3Csl/GLaL5uWLV5jg3nmav
Y0x1hldBRI4gGM/8vCOKB1q8BY8TbeB6wETtrgJDpKK2w6lzrgVWA5wHTPjCuFeJZQKurXZeL80g
JJpIX8UxxYd+U6Gg7ji8gqW9cjciYoznCFRSJAcwiV6/RLQ7TMkMWTU2UPbgRRUhP5AJaTlsHLBG
kDpRv5sUys85ONbc5+pksLhtG+6Vd/mWvnomEBms1/e+jX8+Af6n98WPo67PSdCntlBBB0GpSw77
A58uptTtJh3ZnWGQRMSuQLMvad/WJZKosSXA1e4gAi8brVgIYmbIc2kzpFVAw8CT8ZJVQt0dh7lh
8tVc9ifnMjHMk7eBB/kSfTmYqiH66g/FPPIMThz2zJc8uB+JcA65L3cTruK5TAIZfFjQsRhDD+jo
+IQSPEMe5sSQGn6lLvuEYseLQbSEswNwE1xM0mWOmQTgipmdzDR1ApQU7CJ3glXHI7CVSZ+Ptc0x
tMhQKU+3nMUBMdbrbWczDZr8+LtuVq79gy6RjWSEvDiU8k/C2jfU7gvAAhYeQmEWA2ZDfrBZGMUe
ctwS4RKrBsgrdotouRos6i7rnUYet3BfSROrkb0kSdMZRGxAyAEEU/HXaAAC8PBph61GdBPOjY2o
ucgy4/5j59ePvr2AHV13YPvzcUThetgzbOE/iQtfdAyChyoVx/t7MUXlzDXK9YyFeO5akcWlv5cV
/tZmdn+0Ip2LqVVRXFEBSoKdQdXJdPtlxjfAelCI04ov4YoJ58o+t0nhwgO7bkbIx87oHNgrzQ2M
F9Nx7WUW7kGIwr83dm82aDD3MxmSYxoppKine4XFBSQuB5OgrdtAHhsoSTFIgdLrqVtjPempXbGk
sAGCyeTTFU5G+XjRzr/5F6bDtFizNprxJBKDaht1ZHz7ETvgFDqUE1wXMVV/4EQdWo3mWO3IzFHy
MHtIRlXUch3GQNXGHB3VG9FfABO63ISUv+i8letcphRuJGaIqd6D140yb1j9b65V/pllsmcXjxZI
Ah43oD+OViZ853FMzqnn1m6QUPSsMZIRyqrAz1NPtluN+CJrw1FCZVpiTakwpdxU24wYPLdzkJVt
MpfNjTp4CfPgAm7JSZ8uNwQriV6W+lMhO/nOlWDmWdpkvsTuaEmfMCDUgnSLOZS+lGvmuwQqc4c7
zpaP6+TmfafMbg199BGBGKHnAzZYORNMzqGduqQH2rfIjXYsYhgEvrviZ02MrjLaQZP6+Ut5Alf8
E/kL+HVFFRph1szoSkmJ7EBXybrGUR5qMCQirKzjN+9O+mZGlpjLRjEm9OvwEI2YBAdnbEy2PUIS
EppQU9iHilUApIhfes6nYf+wBw90smvQ+ggytyPZpyUuHI4qtFg7oOfeQJsHmMUTERb3j27kJedP
2tYr9qiiRWvUkdwJ4KJwqWf4pQgGognpwYEamf+1nPv2wTMMQK8Xx/yjdn10Y0/KWTAYXLQMmYjz
1frZ7sNr9m2G1bncTeAGzAAYatbj5nvolqrKxgG3z0xhGVUVc40Ki2Nepm+7jD8G0IY0ml5LLddn
YbZpN/8M3Qhx3Xq5oGiH/2TnC8sMX0iYn2UCyLxrWczitSRdquyZOivyQrbiaox+Q14RjH2RZNd5
aQF0j+++AlFnkxA005oCTlPjkpfMTIc4RxeeLQJ/tOK503oFkgsrCogo+yF12lnKy6igucSzbMPn
3Wor45sypUNSbvvkuBCYT1dqOqZXmmu2OwrJxxib2arzDMD+Od3/2YCFIL50cnXvoIjhEB0DXR9K
/K7a88aV7qbJ4DHBzJ3f0XIdiFQ8SQgz7J1rbVBgheu6FymoZephdjJLqZb90iDDQWVJmojtbzXg
gFOUIz5M7rwsn1szvg6OQvvyk2BO7F4pzU/gosxylIy+ZgksSmVFg/qaV20rZ1k+aSKwrFaoQyeZ
RFL+1rHpj+IbGKJ0T6azxeZPrSBdULXO4GIJdvr3Qb7m1uZp95FUpJBDu9qVsBeW+e88fCT6V8gX
VS6NTuR49358rzHdu4P84iHiJvQ86U9hTj3lb3jjwQAZN8p0kHLIhJ/OK3HNXw+RTjLj3vFhUR/i
IRh025GWPgCvLKW/Fcjs6l17Yf4iBubssKiYf8wlCs3fcp9iubVKMP7pRHwefSdGrCymu6kYmLgw
mqeCa1xHRtdyJWo9Qe40/RZF/z5wrG4kAL6/QY4JsNK5IuaqdL11AZL2SCSWi+If9d6xMChOcgdO
Kz8rL/ul1zVN4v9usZdnQoWuT37LkO/XTV67Fotcg6wt/2SklpnESLjZ8scuc4uMPNBaKqJxjusu
l1vSBAc0RfX+94qdKAB1kZkl5L/0wR4MeVpy7u7MCHssLTOzpzCO9upNisBXiFFPDC00CfVouYZN
XXF0RkU9ILKEeChv27SW6Gi7Qy+jku7OC4OkwVTtOeSe3uN21fa0MxUAVDqDcSYih33eUdQ2UgQt
L6AkF4QraqjCQmkNLaNY6/FADaaIph2sC0y2v4R6EliBhBDUC/ueMaaLEicWDYdky6CenbfyuZOC
Uvu3Y/IwIV5G1ioj22TVv+/LM2NMXlM3efeBXVFLlpk0glMoySXNMXgPIwpcUbWKr9MvEuUqvHfU
Ua+EPFCKPWY+MPtNhxODgEaf5SD42ilmAXixVxbfQgZT8KDy5ESHSevUnG4beDCiUOx2OxSZYEd2
WecJ3ZL6564z/G4fc7Om0ZIOU9ng5EgK5ufct/8wDhJxhrKfWKF8oGMAz/NIeDg+KDpnnOd9TWC8
m1C/nAlPRFVJESuKzp85N/iFta4ERlbMXC3KbBhJx19efD9AzC6BaiST96FqCaEQ0gbAZg+5M0vd
sd4uARkYKVZ+saEmK10NttpOf8+fMTy+o11z0fGYxK7evc99er/Gbpf39qG9yEfmAEVRfphmZPIn
SQf7u15eABhrE65ulYC9cW/1kD9cckhW3Ca6Fmggjt0dr5f0xyY9FGPQPcKlXF41lN5BHyQxsQIA
iGo9RSECpzORa/a8M6ZNFsEFb1RNk7PIJWUUTwA3yGJ86kp56QxDSwHJ3pphqBtvncSbkJA4qxYe
VYFrqoPM2y9CnuLtBx77VYq0P4lNlDZj2jk3mHJrjUoyGQJcNWMrbXeusyvrDBumKKKJuoCp8Ji0
/RMJ+8HFg8+R4uKqYvpIJg8NyYQ8vYA5vtYccRW0jvZP/i0U6PWDFr9Jttd7mvkTVOZWVQzQwIa1
CX0sZXUqWjeUdWRk0PgpbprIfHUzRGF/71Zzu1yRW2GCnx767EQ5qKMpDIk0GPjYaqO4xoSoi9aM
1yz/MP17scsZFRtDTEX3mlGXuzvOXzoZuF1pv+cx/HZyvxTWVigsZvXDBZjLh/wgy0creA+fBV1k
8fkV6zAuCk5dk5WqKFfYd+1UeCPMcZKIBp4CT4CSOy97C7PdZOfTtjBE2N1HOoaQ2ZxOQQfwlT7T
fBNkY0FZvjuckL0I+G/gCuS39PwVULFYbFIzpXBM1Nbej2d5BRC9Qd2AZu9sxMPtcZKUu95Tnwhz
RLTAtWmI3jpVmutYnGnpM5mKwhhOdMO3VOC5v3YpF592DzT+6/6Acs5ks+nnzpA1Us36PVKcWGkE
M1WjUqhQAuy5AFtL3rF2Roudc62UHxBXUcrRUznmTU0m6HWy5ij6umKW8aSGQEAuTFkgHG+/QK3t
lkny9IyYFmqLI8pYvOJTBRa/mUHj/dj/6NbKzslOo2YhiygO1nVPUAcgCQY4cgBaV1HZAFPnSrue
xDDcyoDCQ9XAq7HtK2PK5zi3RkeZ2APBYNWexQi62G+cTV00wfk/mJEXllv7M1McZl6EYNB7w7Wy
NSFsKlLu8YEu9N+Kz6RKVjxTNxRK8PL4e5PF+lnFbOzA7pjA2WZ8s4rN/GBsDQxj+iRTW9eFFwkI
55pwh0HyA5SIW3FjpJUf7cIrlGZ4oEXT7+1t1T2BK+cZECsvU3yQPWI0wujjI3BHqX2Avcr6Gfjj
Zt/BOCeLm3WPYbVnr5JtETvK2x7GxSyH+9LMO852zV25Cd+48P/c6S2Kw0ca728Ny1Y6KGbL3qlP
4EvN/TZ7etw5UKea706IUXwIQVwpP5jQ938y0oHDYwffAWQlBszHIVreDFPDhRH7grduFfXwkAZq
Xg1+sBIztw+hxqlMs53QCz42G+g9RWycycylepEsvcSk9fVNm6VmgeZfgi6X66giRnNJpU2PIBAF
TmbPAcrMrGqiw6Igp/NT9dLv+HdaubjRbMktYivcwKhtfvRJxOMuhYot4wWlUUavaDQbJmW24VmJ
ZwCVPPi6rQ4Nhst/OnX8HNiq2U/gTHWXorogGqfyr8Y6nwQ1i/rMdmxoA7b/GE1m9P5/B6xamFQg
EwXo+CxJrOCPsGlEdrtI/EomayDvxVj5CfvkkF3AfbS1sQsfyGGG1tUvsuzyG6HbCWTS0DgHLYKw
mLw/kac2HudY+pRGugwjN7CsZhMmmjhzcrMq0IOLuASVzEQ07NRtu7qYo3gXq8qnNgGi3DQKDYrw
SYfT6Pwt/XDOLV/1Nwm7lrkBfprfCHgW0qbPVabJczWZCD+LcxtBQw3gU2094NvU7pb7yPhlgrq0
cS5wrnWHRgkSVTP2nTdECUOf2uvdv6UAYuKZB+WHxfuNgMuJy+NNx5KfDuofgKn+lYGw6REYH3Ka
ZOfYztF8bAdIPEvwSawpzhGQAiNBWeC79fEj8BBPy695w6r/wK/tqaFZeWkyTtf0I3GsKFAFjoZf
KzKY+NxdAAJi0qPk4lVk75CJ8kptfpPfFywJQmfyBb975TcM5vpsuS0OLQ7PPrjlQ3gHCKvA+H4n
QPQpKtQRoRv3axSt2d5bX+nHX7sDe0XLK+YohWnf6W2r8ED9onbhdOXu/KX2OHKoCbv/dCpO3JIs
yPgJIlcsES6Z7VNPf7AG2iCOhM8IJc2rkfWNF05kCosrhh9zj72ovE8RIohjbE6NHLiuUlA8oede
e6MJsIbj7L6BcoK50YtZJ47mkqQ53XN8aAc4J/rI7owAq6S9g50tYefm3L0nPbuCGWHERzd2gjBj
eixz+xrcNM7tnJIQKf3BHG5GEXQzMr8loXRSFArDmZxS3+X0oRJlIt5ZBx6wPaJLw/47C403FaVO
IQ7rKIj1J78aFfPu3+RUWyAxXdSUla9IOrNugivXxl+/pixnEdfqFhdGh7sINrMDr3Gva7MydLld
aT6Xxy2ZXoCIrn3QUJYKAx8iSWuYEwP4DqSnDEcIzqyptarJmsEalMCp9GrYMqhCwNqKhm7QFRVH
EJZYkgW+8UMhys0ogbrtFGbOrQzAPtBJbeUFIniW3mJQMXc79i1yiE21ixQ8ixak+mrYSNslA3e6
hUZFTZJoh5xpuHQYY1nBk5twjasanafpLNUSwBeNbZ44LL0/WMXxVmEI+OffB5P3t3OhAtcLuUmq
dmfqUu5wfet7GcTzjZMame10OMV+omk6zhW4JKpGLlaOc5wx6/zoGhGWuaT+cWFv7j06y/IK1Ge5
VwYmkjNekZd73ikRPgWbiiTGW9uE4WwlB6bawr+FtFUk26pt7kv3iGZfcaexkYk3gFuoCjMatcxm
5iJBYNcSz8AWR2X2L+XKSxtSf0hQgxgqoTL2UfsFHmKChrS4gCUThdVlzTQXUx4eyHaIJJH9DnFE
M5L/7tl89MeROUUOeAtes3QIlHeFFHBL/Ji3cfap8ryGMN1/gtgWdRFkXnoX+G6hQhXwma8qXikA
LWFDlKPRFEnz45o+6OCrGzLwe/otDBFLGfQ+GWVpN0kV/uZQ75Sf0e/PsUXpFnaLewiSKank6gwi
8yF+WH1FQE9YQ18xUl4fwH8mizCAxcpFYsA0t+RbSUT3n/4OMU5Qp9o7PN7lBGRIO5p6cMtXRnXC
JfW5MAwmEbuYLebmtXFTuJDEJn0GyquYWPiwpRZnv1ziMZpHifvHl8+OztIxJd2mYoB0qILovXrv
p+sSoT6d+Qt2nOaFyPi/m6CB3U6EZTDb/lY9CEtizEw/HAA/6VwkE8uIX7K7vI/hr2H0tduoiiNC
Z7Qlv61NGDw+Zsk5lf/EB3d4KiMTGGR+U3OwHtOnm6VYC8rcu1iaHeniGKq68Pd4RNabdW0SEWBG
SCsEB5twlwDDXXKD7ZjGPdrzFL4xeUQOh7FvLbwmC9sr/yhddMvrFkA2V9wW905QTisuA8OW3JSB
AUh4iRU5p3eIXnK4bV5DGLg5qrBMXKp7ITgTUsrz1GkN0djgyFC0XYoOcjI7B/yHlOip+3I0y4mv
lvXPbxrefN6gyKaXEaeKqc8lkTrapgWmcul9IqE2dc62oipP4yfF9dyU9mxlW10geK1g24KEyzGo
BeRphtKG4Qmo+nfR7liloRHvowONq++DWCDl7U64lFtPGM8DVJ8L3f2O4dZ63W280QNqOHfM+D3v
oYV1BCKRuIDzGPh+aSQpVALS7SpCpa9vz5n7NadTJvhdFlHr4KfuJX3Dh2oImi+n71N0Qn84euc1
fOD4vRyV2dyrbvpf8ZyzqYuhxBpx4gleNeoUIVPfagb2FoQQ+bskrJ9Fzaop3uYeyYjVHHz9Hn/v
kD96iS4c3YZAm2tkHGVHg07+rB7CjCZASOlDUuBZBYy/Vf49Oo6ZIbyPX6zKW1HIZX6TCXgL2RMD
Z18i6bS4dVWdamjHoVM2FEWy0zWmP48ZzqIofGQ35eZ/S/W7DX9ElshVXWSoz2DnttgcYeQP85Uy
g9m+ziCUZIcadRW964AoRUA3+eqQFMd4s3bDuqBW3XcuFpHSRPXh6t0Fs16Zxakn48FFt53gPuPn
kWccmrUbXLvLcqhA8NtpSsiryUclKgessi+7wqGZwaOZ/56iVBpZqOJwABqb37gDS4naRX5Lhm3s
m3HaTaYcXMsCHqn0auTQIir/uX4q5UPZFQ8Bz8UC3UKxfj5ULvWsnpZTirNjNzizmAgQT8RVbgzU
2G5ppcdSvbuZsNpQGRd4Pb6lyI9TgsK+1nbLlHGhemrdiL/34MiuObwmSLc73QRRBxNgFET6e1Lv
o6xWN/l6TErNc+6EiEwrxgHsEDYFHeG6qnW1ueS9Lpmo4/z7e+6wy6Tl/b5WouFHRr5e9BLEbuxz
42BX4dBB1w/PfHqyvQ9VWKQ2jLS19zH4agGu55yMenuP9MgLtErIMJT+Bl4ELPGwB6MlUUqTZB3t
VQC2OppjbtSjETZroDDv09xkwKjiHqEFViOwEy3sF9EdAetnX005D6kuc/K3fTbQi+m6fMRiKN2Z
BiUYhf8XENvED3ZMQxboABD11DmJ1e9Fs74DiyxWCij5drQwOkqqstt1vqKAB5y7Yfz7BEDaiFt4
N/hwftM3GyDIag16EDHX9KUEehn7+WAQVjm8M9q3X05bEsi+YJzDYvQ1YUMmCywjgkrU+we6Zlfj
jwHfaDlARpdR7SkNfEHejmsi+v6oKmporsGFi/PV6Zto0tsGqVmsM4rG7ACZ9Rr67LZv2ZBYmau9
YMgEVa7MgE7o+XRH98+6g76U+vPo8sDSXBzjLxrUWj7LbaLAwHwCiaHAk2NE6S11a38XlxU9q4Rc
V/ZeXX8H7FNqwpWafLtSUSFGjVEl2UPuR+LqiFTtg5pDbXTI3RUZ/1FTQXdKgs8mgkiZobQpzFE/
rrjhpfu5U2VFgUt175KUgZwXZkH/mSNkaexiOIwbfcsZBAy/tKw0ZMHpRgmxVxs6aDNEnWMppYML
mirp99KtxeiB4YkVvhoCIgRH9rd9f8SjF4hpmqeG33F+I/8aGa/B9TDn9mIOB0MkA9G27OhNWHti
BhiDpachcuiKHNRXtROW2tZ6QSKltulLhEE2tKS5ySwwxUggM23fjcafEriJsOg/75JPoP0f7KSD
GKya9azUZuLQNLPDToOlCvYyOgxC7DwAJSzAineFxmxudrjNaala4ME5f7ber08k0H7a98KpnWhr
7Wj2/ZJ+vEdRg5LF5JobYzKvmpaM7hGgOO0Y0TDtIOO7HUt3HbEwZQnXW67gaNwbS1SMvRGswaYx
K6wkNU8q8NKtgBuc+BLolYfLBZRJcyR4yNDpU2ZjHuWIT4ts/OFFXInD84SDkSXjHApALHfZxsnt
cTfPbSH8fDmCJm8Vuoqw1xgU6RGcrAVPTlI/Bq6t7tCPO+YaS7Zc7owdZvEsNMbqoZsmDCFe8doV
8cVthfoNVR0f3SFwHIhWyLqcudCO3w5Kbmclzjof/qugz7XI3W4up1D76MJKqi3dcnruoFlabFxm
tSwx3GSlL+5B2O2YixhTq2xSfw1sszftRCihJ0NMSoRqkcjUCZWV/isTBo0MmbQfNmdasTOjZ7ew
2BGPXSHQT6V3s6XY14QEqIGMHPF5erZNNQZhY8yMaHagYfd2U+nuwBd7aS4EyGQFpNTw3QcKE37V
hGX17EZiG8Wq6MY/44BXOfTCtCeKo/byhuif/pVMsu+ca4R5zGuY3CiVWYEsPvzxF/qKifpxZi51
XRmtFk0dvxCb9LZijwdOxnyH8ZiWDHs7mJnDVpcWUMPZU8IvqumksK95mbWFPl5LqmMFM0jEs8PD
mTfV2GTjPFDNIyUlS5wgr5mAkFV9aGhFTJyxgym8HJTFTPnH5yHrrcc8JJLtN4hU1di3Xn1fE3uT
opoRvS0bdUapON9OlwVhd26jM7wCZBYB6trMJ8Mp76myBkkv39NINwvcNz0C9PjTC2KxxPuukWtR
w/yhSCjv3HZENtmeUszZgrIUGEER9oAiD+owYoWYlewK0ILXabNAqrhmEBqBHrr9oqgbcYRDzuYy
tXp0TFqhsCtk673OJdQGB6Oio70EYcvfK2+/+lQbm8RY3MMrGTIdFT56B/KY7jNhS0GK2TQxwqhs
TRZFKV/ZJk4siqHTytH15d/JDe5gR0ZT6YLiWctRZ0o7rDFAuWGOts2T5plZkYkKlicuij/brRUE
VoPwjXc21Asul2nGZ4oqWITvNNvqsSj3pZcib/NkEb/ywxjqeutPrWHdY2z9bYYV0afl6iN+OJPF
mRYM7kLjlkifzhHkjMHeNI/3PFm0mygSZsjtHDrFRcYjNY27pFqwHt2ydv+Y8I0N1SDHvn9BLNJu
oFVKeuo90KYeeut8r9DrRTYqFOonG2OEQDDLAFRufZ3qQCoZzCVAz2808ZTxpmyZlUrqqRB5eNoR
fjg1JW2zKpsRpYXTmNQeMRdldk+Feri5oq9cGD5YRVbI8qXrgCFVgnHaSb6bgNKjoxu7ljGDhDlA
fyljqWnwjpwLnJrnLEEPxCA0T5/et2QButOgW3nnwmS1l46RTyIuJvDC37QKPJAoZiXW3NONxQ4S
VMkIxUni4WFNp61+I8ALmhKWYBMnSF2olRUJgjx/5EoFbnaRnuG71h4SLeOPIDGWQZc0jBwrQoy/
p39/L/g1wLZ3FqNDV7qggQZ0GMY0PqS78funhvJ8e59DeuguR3c8Qw2C0tcThu571K4wpX/OFbnY
beeizjT0zdkHhRSex+8gBUGhTbaSXFA+qwXR9xCY+C7zYRTKO8Nx+cPPqtw9pP9PxBswmjqhEKt6
3Ck/ADyCLZdGREp/A68XVGVvHb/JvfOg35vhDTnY5YS2yaSxtOlTrfweIjcpHNm/KYIfyfc8tE37
vQgFgsHKTN1WfK5wTNKf7aRiY0HC8102JHI+A45viX2RWjDbdLJq2Y7F5ppx0BUGXajkekHFHtTP
zGH4mWnc+ZM9cxpDbZHg9CWY03g1SIePCaPv+IQWravG0Y5/FjoT60o3H5FyFBudgMVZ3cp8VzJe
LvD1NXLx34aC55OogymYf2wimfHqDswutWmnj+tuNMEDOInqQNq9UcHM/OyxxtX8wTTT/NRUFeVm
VeKtfofxOPU4GgEr7q/dgpmmyUwpJdTmUIWgEo/EFBgHOpfX6wnVmKNZLK/35u6h5zONTzL/dQna
H6zFQ6I+cQKT5ug+al7l3k03OO7iBB2zXBSdPjOWpTtDodnsbHMw86WcpUsjoqFkiDJh0K9pAiTs
yu0YtLXYhpLRc8vLx+nlNPLnBlewheD6Rsel2vUITR+Y0R+LTIVcFizL3RkCWpgT8Mv7GFBus0bs
tXa7x74NoVvDOv16dK5Bp6co4kem5MjsBMqulNnb5qAiSRSAHjJVEcbgiN/ejphUzKhhnQ2rLlmR
J0srKz5SDkt9GoLIIQYs5LiQz7IybWCgpgj6AsAgzJv8o1wGzGOJFcuutKhU3byY8gX4mvT1mcoL
+oV0fltqMUZ5+7fYGYXRzx+IoKYTulFlekV7KaIy6pn9anlT85vVRhfq3tNZZRGuUALVSiHKp1Bv
hSH5jlo6taMLCDODPF39Tqvftq6OemOjXklUiPQyYpE3hA7qrG4TTmxYZzDSMPUrCpTcgg6vjYA+
icfYFMU1pgr4fLmYJ0fROfPHuGJh8j+aeRnjdDL1S9T5mRS4VQFv2nBpMet9lpa4++KbevKGFfwJ
BO0QF4h8xYmLMoxmJE4LfilYtw9dGxV5baelDnfq58HheZD2ds1QdE7sNtEpXV6y/daqe+F0IrwO
EggItvtulBViDAFHzzEs4Ors+9e3U7TiRkh+FQouUA4zwFshY6xGA6Dbnol3ZBzdaBUiUM72DESu
4f8i55WEiA1ksZPV3YoWd/4fFxoy40yp+YAThVsC3PUgYwIJd+HeGGy4QmzfwbeK+mDAR9fhkgPx
nzDL3LV2Gv3HmCCLPBRF3HWk89YHpBOvD6r+uOVfqkM48561HfV7l3A6apzVHxEOEh1IyTyiN4f6
3KVzCDqCvavPKeaSnkFs20XLbL+sYELy1lix4/B4BOvvSBa6muSI5EwkO9IYHRp4SldDU/BoT6Cf
qRS1nv1bScZ42MttKPlYo5C+D45g6wpNReoA61TtaIEPBZNYtLw4TsZyYTF8v5ZzdClRynhRzcCS
TDxMcqXxYDSNoJqUrB7zcYe4AU3uO+Tj6wXoA39LLbsKtK1EY16dK5eicLPwSoFRhW+yHzcF2R0r
WPJGyuHI7ddZdu81doAYgdtje29f2PoQ7UdSTUx5TaBtDIJ3Rj9hzUirGokvUqbl7/aQny41+3XL
F7yI+f+1hfB0KztcysNAoH/Ef6mEeMnfNIZ1MWfgKXi2mHySkygQ6NWZ6vvA1E4qyMJXH6Ff48/K
gOLCxf9q2hiWqZQnp6Xn75CfUcw3BVuhzDPyLdr0RuUnInmBo6zzYXmuhUgWD3UZOwbOLMbQde1E
4+ppigWbA6D8yjjDH5d///Ez3Ge5UANdGKtn5+zwt6sVz/UnNbLaIxHavGC/XYYHjVzK8UBa1goj
rRjxZYq+/vP9jTUVM/We05Tuu6Vhr8Xqgqbs4LxdLvSY5ZRtfkiZ4ZCcUX6PAd4EH3/mr2iiXXwk
MaHxtETB5c92jL0MYVhAngHcoQp4PXcVgMM53uyhUPz7f2ILQV2YDlsJucEYfDq13cpM0FlEQd0h
5mhrSC7d1cT9pzwN/S9h7Qh/HzA8ELwUmuPuJDo2/TpqVz3rFrdQd6zrjucPEC8bNXyMJ4KKbI8D
jSOb8qPFWrNmF54vmxSvOh/OuuWoD9f3nVoFgkV+u9aHOriGCvKVf9fo+9RKQjPtDXcFXUfhU3Cv
MzmWBqGndqHMPSFCJwZft7uzO4LOPPH0VfFoxWhRynQwCPBocMx6x0YUJV+M3EFU6Vu7E3kJrFsl
y1fn4yO53dC25b8g4zcCCiBPZyfjr/dEPpI56AfsYVso/JiXvsCGk4Q44hgxk7E2o05UqQCMycBS
ygQjxTdflOik9YO+XOKbMzwwOKB9IrJf7iEl2lQF2K+TkGRUH4+zgS1JhcVqHPMQR+DJxVpWfM0M
H47wPKt6giCxmkkimy+FeHTdZ6hz+24lzsFu3UbXHAwWbAtim+kz7tWoUwDCuWtRez90LMVibV03
s9OTE0S01WDnqkPCfv23N97xtDZeKpUclYjzfg8WN4IphB+xKA760It6EE+vAg6sslhPeEtILCY4
Uo32QdRhD4sEjjub54P8JzSNxRxNbgJXU+8ynehszPSEyuxl5dDi1AscV5lkhXQ99VE3kbMI8ilh
QVUy1qYXE9K5fiRAV0MgOjL6GGRYoTf4n43A3FTs90xm2IHT/tG6dfy45aY7VCkDyOLAsNg6qbjb
S+am1g2mbZSI1nM9RhmFc/sBTe78Kgm7HWfCi6EV9WsWjqKGa5AaRsASsm7bd1npnUKXCxM53zTI
77Gkmb968Gfj1eaXjJQdf892eoN9RwJPsCC18O81xXkHoHW9rpUzV/NkTfGJToNKY6n8O/U/gp3y
AG4NmQb+ohRjIbQrMorHExbrqsFGL4eC3yc69mOV+v1CTYsqda7U3Kustm/djGTSpFqDUaNUmNv7
s59H+WB4s7H0P4v0ac2cjyGb2JiekKYXjqytCQsMiVJwOtyNM7tOjPKEr5DFyVazHv2pRLOhaGVG
87WLyoRqDpuHLeZLjrkoa33bl1FYrCa3J6+jJ7/V3xNnIZQChJxZvKwYAjZaE4fMV2ZZJnThqFaV
jzThXMsUKhts7V+pxPK+9zyGMAfbJb+gqTodEbZFGJ3uAmuFe4/D7u5r4ULee1EtBh9bcw2j+Ola
cNtHZu9ufBxtKXSETdazieWpvDhS+w9bsCl/1kwyTaNvigZTEXWAX7zN8t/Lv3wG6d57wx/BxB+E
F8OAUdaEA/l/kXOG0XbxRG2wQEbzuLgDFSmrE62VEjJinXmf1q7lMpmlsJOGH0t6Vpx6OC8xz8e0
9F6q/ODk0dxRYn1TlLWz5oHLnk5CLNiWA8DqRrYx16q9uzU6zk/7a2dB6MGsTzhiIU00omSXkLY3
uhJSd6oKTQspc9w3uPCrB095lhsz+vGhD4iM4/CS2HsS0zXvKKDnVX6r6sYwhAYS1txJn8cHejTS
33a3FzrLh/Lr8tihbnmzdHQJtk+sq7tZb72rWrEbk48sbF9yJahsTCRqNmxxIiHoM81CkKoI+Lxh
cfc0D5Yp/MomiNvkLGAQL9gJNP3W0OyucO7MynZvbq3xjQW7UGuTkM+U7elqqbUSHoc+YvoRMbS0
Wra3OUa9vgiPvfWOPUXkCzQ+GZz5oh+zUdgV9KFSEg78gDsnyyeW/ilBD6TtAk9pe6QKH83lGlA/
2bWItSalCQk+8HJxYzEowKqYFGa6IaIc9tMb8mXj8fSJrYpmGSaaPDJJbiFsHkgzUgKFO56A6/eF
ldbJbZmhU48DLTEq3y10q679uNFxpRjMbj1VLTSaUJ5hhfLgA9jgL7ku8ypfmsyML/AFtmtYlAYS
x/hfNfqd/HxrFDj4suOVtrsEgFli/p8rQFuk8bUKKi+qMACYCmucfH6KPKuWAuxGCuqam7J+SLhy
F6DV5jjns6q2TiCqwQ/SFDGGwNWkiXwsljkpcugaJxrggWO350nMbF0QYxh1wDeVmRmPTvIktQeN
C2vym6ToRxoNYTF2Tp4Y99bkBeDapsuHhs2C3sEBcQs8X6JL4hEvCnkrhPhAFYDvUWiWd97v1xEF
JXyVXUJkVG9BXgkFfhxRC6VBtIUPWaRXjsqkEhgA4GfNh9Ato1kt2NsNy0Yk0TuxhhyZVCo9JfjN
xOUbhJqEzzlTH8+IdmNPKx43EGDT0Lrsk/UOaUPBvFWdb3GqIMg4TchPjXgWpuyR85DLNpqWKB3K
K2K8dzks0hfLCIP0o1ZrJyaV6vTRLX6GDJX6JZRDQIcYVYCtM38a642Um1FZz9czprkChHqQfL3B
NzQrdtyK7LIW3fUDo5pKTkFMk/BrlxVPsmRbDFKf4rxCbgZA+dTNUmlpBauC7VYTM5YFkM6wgAQf
kvhXW9lkApSLz8wKN03C6wRC66r8yh/YqKG+OjTUsFovJrTDokQK8MgWGIzpNPRCNORK91DK5GNY
HEXIaZzdLIwnRbeaVleFh1M2/3aFZkINsBeVqebQim1r/XodkwvYfRJymSowdoWJn6/gXjWYYZGh
nHpo+U87TYAoe/0bNSftOYIRvEYmlBQPHk/YuQ7Jdb5hXqiv8iaBtaRv3kWfgGc6JF0PyuLIJmQz
sePGBoxGEAi/gTPFAp5q7bYdVvVh+ebZ1KPCkgVP67PIAZMIBdM7ytHOVT5vyhBUSnzHGj7tsaK/
AqD6UoWrkSts4FsZnh9O4M8pkE8Vm26V8YWdgHnDnz87zqQ/CBdX9Nf6pLsk7Gm/k4IQqgnaYV3Q
djGKNtk3QKG8x7u/AfFVjfC3uxos9Lej1HjxSt7yMGU5UStm3a89d3ADmdllSmHXG8oaJwgC5yD+
6ZyoV+S6O/inHAAITWTqNss+CZq3wQ2fSPRm3iMIYujSFh49ZWF6Y5hhATGZ7puV05IkX1gc8Ela
qcxST2cD5iqJ2QwgOpu3pXIdq8sop2UlJ2ii2/Ct6PF84r15S+LX3gLwJ/KnCGF+GUwOWmRkx3Hu
v4EWljx5OFiNNQjpL6/VF8J8mZgV0Yatyn1p4Zb53UROPaTcM7aRopMguRKwhgpbxYt/+eTJW6XO
DU2onCq+kdiW47TN2oEGrRxvPPPOq8/oSOfJtP28+4j2QIWKpNEEkyM1waSHRIK9ySAFcsxROSmZ
y5VUaZHpge4mjt4o3wek/wS6MwWVPMsAu3hEPxAU1KQr/u9URt3MMa2fLlo4iYegrEEYe2yLrrAN
jfOlfFl2WAfnBn0q9dqaZPhtJGkjLcv87aMFcrI8E5sRxgPWXNHe5E3yM7fFaxtQ9czAwy5HBQ7T
gJgBJSPfEfU8e3x0JPGyrdeTDJ3A7ttFutTZr1mNDvkDS1bKipmWU7JPSOW9iMIXgy8z3KaMV17o
y3aq0spIkFtfHwEMlx5tdEz8T/iwPwSqX7cnQdq/VsqDUNNb4SVzr+cYcHaGI1VbX/0HzDuMomQP
8bBDfD6NPr3YWlufkhrsbQfYW7WwfFtn5mraBA8+uYpAnFvNL1nN6ushsbMR1N+vSXjcYN5NACl/
H2124SzQrgKMKsLqQRU44LOU1vbHbBKDecnaquvebNH7p2feemLLqYcfbhQerM8RTzfGlW92BjUa
pGu7s0UvPCSvVvGLI6kKWChXl/Ug0dnDJutwDJbPGIIKIcK+2NPBDWx7NvZcgk1vLArNWzWWN5i0
Z8dDhZ6CzgsX9JZYvHPLyXwjLrgSDXp6EkJ3xaVltlxsSPjIWuSJ5UR2t3a5j70+y53DA5hawRIJ
BflpJHyKmzPzoIY+XozhC5geLbq+MLSTkXTA+Md2N7j1po0WdpbtlNFxKyHKeOmAG5tXoFNxuonX
NfKY106GmQh1ErXt/sv1FnwsfMlB1zi1P2UI7BNRKZFKqOrCBbJHJCnZXGXx5HE1jHd9qZY8pcf/
raU+1iunjRWFwqi0m4Q/8gbHQTiFqXI0Vta3iD7PfOvOLzc9cuejpa4JY/ddtS3kX2TIpZRySbii
XgeFxsoRZG/o05PSNLi9egYTmlUgVS8d+uK+3hIvzh7l7GM7KBHA/q9Nsn2MXkbuM26NH3qxiAea
Dn32PsY77N/kRaam/N0h1Zw1y+Yze0k6Xo7SvXAa3PeIHINvxYjsqA0DUbJAr2qJQ9ez9vPSqTOB
Dhbd/08MfHVAhXHpF3fM+00YOk9kcYkG9Ri/eeixt2oEDZaKzJLnnoqvFxeWkGjVuZfdk5dOu9v7
ExEKEHZo+ZvJiEXLjjzmDtZFould5AIW+q3ME1xdRFAo48yScl3GdhltW7oIIwCbxONHp6pPH1DB
UKn3Dh2Z6TWDBMdTMe2/L9TS7lojLF/dKkQy/l5IxcOXSsyxUWAVpL5ZrB9DtijZUUpLiHlAFei9
Y9Z+k80OmqZhY2yO5s8R0ALs1Ft48o5GjKhCgHF72iPb/y0d1jf95FfmUoxwezzrhskMaOCfFgg8
AphxbFX/k+52qiLuQkjtJScwGnNfZDEzWfMjSThKXVI/arwQ7Tn55JqubDkyP18b3uYJ3czC/KiX
yv+ED9+8d35HV+DzUtygwZY7rrisICcU3NFk7cc8i1jdolvkOva04x34YiSWT+zjbKj39iDgMJfP
nq1M1Ah0h3m9u3TgvvOjbzfU5dUNe5/RyIdK0LTLLKGFZO1jZL2P6ntEgfg507gCdVHVavN3mTHX
IPwxe6Y6aJ52LnrwSvqTlTplUK3PXqyywVm3ukSQ8najZI5ITtibqu8sJzJxPESP1h/CGEy2irf0
tKuFjzq4iUmlE08KwGR6AdQ90uUyDZ7BInDpap0TUFE2yqj+Cmg/RLdONz44miMbIJ+DAxSUi2MS
CVoaEGRDgZX7L+1GCwlSyMt9OauSexn2E56pMGI/A/PNjcGrIdxkutQoK2YRlg7i6f+wNb9Y2gcM
YzNWLYz5uyo3rNjHRcKm7HEbiWcCdoOlOc1k1c55wLySin4bgMGuA9UXa2pj15QXYNFMeJbtfhwm
ar4+eZn5WyZ6Q7DhbN8CKPpHO9TyDPvVgQmrAQcWSBAx1hC6wirnvf7ATJlrz+DmfHI9E026mId6
KH40lG9jMqfrWu7g7s8wz6nIBiamEhcd5objUHUEmMKbsASQjGVhZA6QbCbgAukMJWUtjQs3kGXc
FgiOMoJpGeYNPE8MJgGTMl4eB3OVuQh36cD5wqXzYC8GP17NZ/0WINIk6TBXOsOpv1WCDSwhzshP
zuOsK8lBIWHJFZMEZp1ygQP/cGs0RyCqkD8ulUBTV+K+EZcy6DXjw67oee/ALKZrhgkjW/cAGZxd
eGZowjoQwZjMCPMMu4WX0cMnUwzIo4hU1IQi+ktIpNRZkliY3/li31LBpNye1mMA1I1p7/jq9Rb+
No3LbhHCont+fMEy734+6OiLsjBXts+/ro+qRqYFtjyT+k0RFo619T77Yp2untdxkjuR6be0s93j
vPwKi2VrjYaTCJbKSM0oj0YtWmM4nSWlNLkS2h2rjbGdujgcDPlU8I44Bo2G1oMGiCui9FodkZtG
kOBqtjbv1R/z+321jpGACzq25FPJUSd1xst7U+0GLp/EzuEpptq4ISk5nnvG8OpY7afVlV5aPFsj
MBQKt8uSzd/dHgxVjmPeqp1cV0WABPcaLzC/ehxbi04Q
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IVxyk7XRM4VsQcD0QPYws4xsTeDPKdwWYfreQJ7l1z8C+G+JAKZ2psrNI+b5ecZ2ziPH9MBGr/oY
8XtzCKmjJw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VO3Jpo4aYF9TyVwyAUb3a/oDy8Yhm9ea/9mAjNtuOBRL0qoy0/CWzL7D+bc1SnZvEP4BG903Ildl
dM2y4TNyVTBUaU7Cz+LzZfu9kCPWnmttlx92LcMKLNuvGUMPXmV5jr3PzSFEvoDuCinMqNc8uKFO
Ux/aX6fmBD8AbQfpK30=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qOkimDe0rSU5f1zKvoE8a4lZw1WOOUxh8wtTIN0ys09AXuQuNNCdfu6VL2Xuj0Xus09sBU1FazgW
XpQHuw7XcozHRlnUFKPJg2P12yPJsLRkOqUWtHTUXmH/8s2RglOoEcmFeX9FVh1IRMdnp+D/F4GX
/80OwH0Jtm4eUDa5EFkNoIfhlOG4JOG/JCsYRnsAoZAbyHMEk6qPxdOGDrYzkbA3CMCikTuE6wOm
0j69ZgENzpWR5aludQDu44oKZqgkdMKNm6Mvk//s2aUOTBYWabbSKe/I/+cEp1tWS7+9AAmaVwO+
KwmsZsNR4Ztb6OH4hCq0936o+bycwR0b+Wr1VA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4df1QYXbx3PmA5i1scwSy/ZAJgZ0wNtl21eeCeUI5h4IQD2UalJOUkc5a5UR/j7lX9ToyF2yFHzK
L4EoH+xXm54bGihfoaTvocQQsWhCDObbmBOtqB6WS1/bog7FNgoEObi/E19vJsjPSd6nCCdhglZ1
j33mJRkZed+lVziTR/s=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Rtu5N6w0tnewss9ZQUyM3gMzu1D5Ba/+qJO2rdGgk0QN5Nm+4TaVyiEXzVM5DP8z3mycaRD+z4HG
QXarW6RH4GHKahoLlSY8cryjSJRWS6D7/Z1joY2fgJb8apydMguGWjRZ/uW6R7BEimGxB3Xuon63
ZdpcvKZmoyvfg0kjAjor/DxtP3SP6DKxH3BeegGQKpP/+5EmCrAhhPu+NA21340wcbghotvyYusJ
ErSZhtj+1FLwV2sO7TUt1etBG8nf/yETDQPE7Q+zX+BzOktmY3tIKds/9qdyDt6Qb5WIxLMyaMa3
eyi0SGAuZdeDtK8Os3w2ajEZI+VjufruVqtCCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17760)
`protect data_block
yvvRtu+tA91Rtyv3I35O4K6BiUlBjs7LTFLRc9twWgYZkATXrSpXZut2NlvE8mcC7mB31ueT2vlU
P9hzhGYaJ5GcmScpsC1FKNndMfl3Ug9Pqiw49YT0Xp/AQWIr+q38Pu2DmkLm87YVBi0HN6JMSu6G
rwJt5qvXJYVA5oSnqcy27I93z0KCdBaCW4BhEaXbMLEY+qzcYsWxGhgjRzVfC2OhOSpdpDr2MKHw
1YDri1cTZAVy/b3L8VUTlyQx4YRG+qS3u0Cz3dOLm9nglzh9Pa9XJC4+Lnpli7w7vpvakaXaH9W9
I9Xs/9ShuVul4UrHUMsoz9V5jcPh1iHPT9m0ZTeLUdfod7NEEFDW47vWU8XjL6iEqBvA/DrJKrri
hjJ//n7fbl9gjxGZT+IKqHleRVz+dRiS/uTuRo22UsAcWrLoCdroE0x4MAJ9vC0vScZa86PQBj0m
ixJFhU15XHesAUmaWmkIVFZdUdZL6n63C2nZpQmpBX8G1td46ib/xrjcP1HPzbr1hPb30S/GA95D
4e3ICss1yPb8NZCwvzZHNKYRJlVJ6EOWwDxLeBOjWmUySMUcywo+toi8FWztPmB/Fzs/gyRSBxsb
FBe82kj2NTjDK0dD4XCcU8bGjVOKNJ3KoJmC+0UD0jihX5N1CdPg7+/bvmP+MCdk3ondXZKJzYI3
9YFYkr0RM2BhF57jZwHcHHmFJrakmG38Lap7lsdonuIO5mfOOuicr4JGW8Qijs1+c7VMc6LUwGDt
YKznnHTq75vwwVLxmtGYpW4RTIuqlZmOJwC34kp9oVx0+wFtUxMvQgXry9FwUwb2gSWRseSfbmMB
auDz+22lW+enEoOu3PzG3plNq4oQP2K2H++ZU7HNTNGSA6VpJWDQ1c8o+i7+XEkyIqt9DZHUxb+3
HlbwgxRkMYX88B7lb3GnNDLF2YzkJMgQjpyPi+t3N2MtquCFuqNuaKv0LoD6+mwRceg/hAylp3x1
m9DKQ0DcKuhctFlcx3aOGMXc0mzgjh9Umxn2Ng7JEliL6/L086w36Jar0AAtsKsXZ1NsDDBpiIeT
c9pWEQj9ud2144CtZKOT9/hr1wy8/jpi1lQaHanlWWtc/eb1aDpSY58hPbltVjUTyizUFFWsqQAC
PGoqDXF3N036pR2Ipsz0lKGQE6qHOZ9IQByoJkJfVJQFD7arWnGsW4G4I9tdTj8LBH1I0/XQKvur
lSNx9C6iPx8J8GemXPHqEIipG+GgoeMURYc7ft3GzrBdwbTFPm/qrxT/0vdju3tRDBl4JSzWO+do
z/s/CD6wNYNcDBCSDKcprRdML0+tkUYr6Jexl5rxIe2GBG2XGRgBDqc+wBSNJY7VVfutmSr3NjPK
RJK5NldZFn8fT/rjewbLV4flhMn1tgsE6HhNm8GuRS52PpzP+BK3fCtYvb1mnkFy+e3mwc3RgZ45
5iaZGmsBwnJwI9GcgMGoWSDkSaL/1PrI03WtUczFAidTPvIY08FA8CTdX8Bo/j1vK5yj8spVzrNq
2YNw08dzyQOA6p4yaEO8Raki3qlKk9oCGUe72zvHFj8EIo6DPYz7MTOBMZh7qLr1JDqBA+iyQCSU
UO9dElHR49OYArhLqejxnXEbJqi2McLLRKhJoiH7B/feWKz5mjNEjtWpHgiwx6VhyEKkL6UZ1Rib
ZtiEI9gtUbhZ6XzaYm3TiIRoYgTzxH0j8bAv7Zy61YnOi5ds35hrlF48AdxPXK/eT9RxLQ9JC4D+
xhLyqoQdstrt5DgaM3NxG2mKEJVH9uc9wj8j/rmn9YrBedhVek2F8Uvojvb9UP2S80Gz13xgD5DT
uHlDBG0pjratONtNE06BnMLwZRtD8fOAmitaJqr+uurpGUSmFSP1C9+FHTWgzBTdRwxLO8vYdEOz
WFiLspZhFCxJpRdUt6N09XI21qtC+0+ZgVoJcuL102pig2HCGw+mVSkibp2ZzBHApj3TyyQWeR0T
soE6qVGrU0cCA6w+mgSp/LpLjFALA+nFAG3lXPvfyzy3nWkgcWbCXiItZJY+SdblaE3tEF0j7zRy
QEv4a8Rg+L6tHbS4IhpoHW2u/3VbDszbEYb4sRKfYUA0hAwJaM8jOAxyu4YRtJsjn94Jek1Taiie
hp0Ndlnhy5vlx4q5I6i8Nc99UyR9uhRu8iqRtT7nCYuJSAzDby3Uxqh6srwmKPrb31KF5pRhTgEE
hoDR5pRAhvr+p6GEHRm1IAJTB/vA3Cmck+beIM8DaYRIdaZnzC9N04oH+sWVHExAUc9WW2ZHotPC
yowKFvokfu+7look6EHxqKtkI6qUIsFrQgy755fSnh7+GR8EVZFKqkRCDv0zQz3m3MIaUQ9GzxNA
nVZg02l+SgGZHXvy8wOZE4ONpWcUccgX9k8Mqf2VrJEhn7FTdwr/L68VLWlWyJ51gTID4qsEbmQR
eUcVhXwZ8J6/Jr+tfQkihSE/r9/FrMS9DtCeXZFSTXFkRXX3jwy08FYzVkX1AU3nfi5uob/pWe44
jJ4c+H4TgTK/YFd0U9+b9+hcQ/PKCmyuUWlZMD2jh2m6YaM0tRHT7pTE3k+5NorK0KIzBPhuhR0P
kwadh+BfDa9Ed/g8FI4r9aO+bzUYkbubz1m2BkiyrHNUN4b/jhDQyeuJYsvVZmik7vXZ6GcS1rnC
ZJpUE1bWR8FcYhqQoncmXGI126qn791BoIP3g9UyBSGDJ/hK/eFW6lylhaaJjjVsKepmxGzcVN1B
mCwVpKVdTSGBmK72htH5om7KKA2S1rC5U1UUj3MbiW7ZNwfDd0USkl8imBDLwgYFtoEE1ko8C7Jc
eUprl5A05bpIwcNw4M1zuvcSJzD1rtWdZQl2vo3uekE+ox++ptfYE1O4Xj/2TqSRnKWmvElAWcGk
d1P93oZ45PNjviXZ8GjPM3O0qWdvlgjvAq0xdzA6x0TysB9PpseLW+g8nB6svNvi0GhK/LLkeLYg
V+VOQradYifDOr8PNb0cqid1ncvsR8+c0tlZfcJr23pLfcE3Vqz5wPmHYoK484/vAUmQUEHiXjLv
MiKyjk8ywnYHQ/TOYWuO5OiF3b4XtDucLmEyRzxNB7rY1i7qaj6wGs15PP5RLOMaDOI9Kg6163IT
YHmjt12E1isvBtgqS4df/zN19hcUsAr+Hd+fpoCiaRD8qfZT7eD2F7aDUpS5tVOH7gVSyJWqzQ5q
Obv9Yhw7rja/O45RtfCLUeQNveIdOxbYJdxtkbtNUL4THMOaUooUKNDHf2XRJ/IU29P3yYsch8DL
w6GDueFKcmhtTaLLsoIw5tztfz1OnR/Ji8//265ufazAczEkWZEuwDJ820UjB8sYf6rqgnsGaFMq
k4/RqF2vivZ5ejxFZq4j5HxYIkrT0dvfR14iHiz1gFBjRkaPy0KB92AudlRi5GguJSj9i9apnV0C
9Q8mNjw2IhqKOYuyV9e6QbBpKJ96If+glayPM19wkoNu3wYrQpc35Fto6fYKFdY6dhE8nKPhcitV
/uItKlA/SbBd82Zd2+R5YPNcmQq0sWFXHgntGjncAGogKw7gdfoVMOM8623k3ZSxgx+hl1hERb55
2VAlad1Z2TVWotbB4SU6fYbYbkgvMzH5sJuCqbAAKfcoPFz1nWbbyWa08tpLEd7dFgSfxRMD6emG
vbRwvFQQjTUHayp8X4YhTp75/cn7s7BNav/nMANVwbzv+7PlcCBDE/FAkBmre/mWCARVoeNQi9yk
Lmy+/QFbBCSDmgH9dT+J0qyptUReayys26DpOx3zpnRbUVqoevpDLpdsoEIttEWQIhHlgFCwxqwE
aRk/jq630RhYJrspYYhMKJx7vBModJIEGer5px3GFiyOMr4+4I2Loz4N0yOCB4NxzVtMSM+DMFzb
Yqmp3TY7W03MSy4BUlptWvy4cfrCDCrea8duJ43frMTKFTfbW+IerIgRfu6o1EW2xXm1cTpBK1C5
GDw5N3ENOo9k6+Og7Rv6BqrZrvmt4KofAZpoRQwtrvIUEswUfZzexMH0dWDua0IDEUztjkju9U3k
MYVajimuyW6IXCYU0qQCvsz9sBM2LLZ1x1Vup7fB1Ec5aPwU/UHatOkTm3aX0ZLYdmaCrVM88w9G
XHeo1x2sSQwb3bclHeYGqJ5KFtGY8NkrjA2kOqD+X2jo651hd0o8X/ii6dRA1MaQa3XRL48KOtEM
HH0PUmnhNz19o5YiXS60R4NMyF8DBJ2arUQqgtrBdHpYd+zsNwOO4FJe/HVkB0g9fp75mEMH5PiJ
iCp8PJo1jsqW1yWtRGUFGwq3z88uUmySC3W8F4jZcCA/IVM3H1z/nL/Xi6GkPU3ho614p2M5bRq2
14TEYUDIUMMz5OS3VFeKp3NLgKmCpVj7tbmiZi9T8Yde5BbWfETD2YjKPY4NPYiw4TNz+908oHc2
yTbewFueWvL/NaEUrh1xMwQw0DRkd8xsxovrukJPMeMMIOpJVuHAqxeQFIhjwyO05shLRO+8ICOY
lVC8RDu4KIeHaBIdj78ETsgHAau5157cMpNdCv1z6u/eAEhsPNaTpoYf5z4Ulz5+vbrw+Ig6ywPW
AC3chkAwdqF9uooKaqUaS0uaMYKHDaK2y5UfVCBUcfko4mCk+jjZbqPR4oE/RY4mRKF+S5KVRb51
goeafsPpARmOwOZcbpLNMXGonqOUJEFV7nFBn0sn+mMycGAzE+JXd2B03sI8g6vqICD4805s8/Q7
Q9RvYQCBXt2A6pU5gu9eZBujlJ5yteDEmqSPNTNLHzUtnYMoAcOjjRN+mnEfti3CP2YaqZYc7AEK
EmGhccCK28g3Iq3fyEIwqSG5ZMQqTqoqd2RXD5hdEa8/QoSw8h+tBDysQ5iCskiecYnVoVm2sJ9g
EiFptSQHJIy0hyW5bqu4IBzo173gYuxltoA/x0vJsCyFYs77QhbyJAFsJLmGHqO3cT9lndY5RmIe
G2IsYZVzwYIn/hCH0vy7GSobNYDvEMIvGBaU5p1UTsf1zLoaBwNW5il64Rmt8mWVqr6Q4Cv07zk7
YKXZHTXhEeAgsPcWekKsDPhosTQ1OG/Lbmqe6Xtt932gr1mKpZC9HDG0zXIrXY+2oSE8WilO1BRy
J88nrrr7Yu0oYnF4wZWHuAWIyjgLKyWWX4IP/WRaze8T+DWjRzYC+x719Lw3Own8W4ws2iTfKhys
/AoSQctmniBEUleebvUzkP/54oUfgrmlSFnT+LQI1wpo2T+VfQtutqXZD+Q9onWKVVV4HeEbkZlD
NiZEFqgI7BCHMNKvyQsr+gN3d1+ljxpDWwjLTifh1kNDK1FTX628L7Esv/ze15vf2ojo/9c1/gl/
t1SV+B85OJEVM2ghrmoVc/L4ECZPJK0ZQo5F/4K6TFqIGKCvu6JvWCTXCXXQuvIJWVCf3yQ+xB28
CnIRjnpjYhPYNojhQfb5Zv+GZ7LFqZZ1/o78veE9yuWl0lUlNLkf7AciAMp2qc67QqLSzbmp+IIZ
GRPGcMLDzgqZMu5UoNLRtDcIK4IdO68RfVU+DfGj7azU8UasdLC7EXFxENSmQ/djh/0I4Ci41R+q
wsa+kmx3eYs+rFXPF/gpMof9+m7gcNIlaKRiKrmGwaefZwbiLS2b5ZrIZ6dIXfBst6s3VP1CYaaa
+z49NTCU0GqV80EBrXnRQ63CMSRECEHoQlN/WGzyaldjxjHPYO9Hmx4A4l37hy0X4CBEgwcgcLmn
2IaYATXcAYJj2x+86KLB5ybH7SyK4Ew14BYjahhIhbE/HpiaKw6srEVCnQJsybU/L8kpmLrJFJJB
A7L0H6rsyqypQ0Gw1vYRNT/Iq1SfeeCbJucKyPaC8FIIMxhLscoBs871BAGV6PnoCQwWlPdh7wt/
cV+rFe76p7fOp7y/iWBGEIZ3hi+nWA/1wg/Gwy2n5z+TL5zSsOLvSN/UaFnaFFlJfzsshhbbzRjm
u8HmR4iISYlZfg+PuCGg4qWDzTm+W3rHe0IKKFdTl4GXGM1/EpTtOAqbIDIWKEIZkJ5l8b15nkSy
kXA7m+xG+B2kCr6obeLcnH/Kll+3TvkRO20Bb17nVNUb9o9OAtuAZf0dsN0dkMWVbDBmARX5RrB8
Xaso0jhmy2GD0839FOGPRmjq0itlZIHy9gyGxFuelbdXGBP7YJlreCebt5nS69xLW/ntBMeaobHB
+fuRF9ZeLz6NIAjircenBW7v07uWGziq8CV4rmH/bVbBQVpgNLXkN8+irSvzIih6+uQU+4qnhkGf
6DPM1CIN42m9ynyzhboG0MwLmsmxfHNu6W7pdDbuQK0nD+bziOLzzqrXLBnyPXGnwpO2QuvUEpHz
JbvGAC0fH3+ZHVgO2K75xWmD0ckLOS8k2Z5yXiDsc+mex5g46t0h1hrH4Yyvs+xHhn22sZ5vmAd9
z+TAxX31wRoiRQvb/b9h8k+DfNRbYFTRb2ARM5f0wglZ2CBCHU3UDca46UnCcX0s2i8dCJiik+U8
1YIMvzM1YeyL3p4mMj0N+JIFkUtiWw2Iimbj4Zp6ofh5N27FA2Lw2SNpuIQppGII0um+Cd8fl8LJ
wmvWzSxiUir0Ax11Yq2EPE4jm3nKtv2sY0E6lx8WJYJydjXzqOwe7I/q8cblI4Vw7LJj+vuX/Vac
5mEUxAfQSPmHwmPnz7dWxElLo7zN511DK5ZEC8GBtiK9/m3RoIfI1+3Csl/GLaL5uWLV5jg3nmav
Y0x1hldBRI4gGM/8vCOKB1q8BY8TbeB6wETtrgJDpKK2w6lzrgVWA5wHTPjCuFeJZQKurXZeL80g
JJpIX8UxxYd+U6Gg7ji8gqW9cjciYoznCFRSJAcwiV6/RLQ7TMkMWTU2UPbgRRUhP5AJaTlsHLBG
kDpRv5sUys85ONbc5+pksLhtG+6Vd/mWvnomEBms1/e+jX8+Af6n98WPo67PSdCntlBBB0GpSw77
A58uptTtJh3ZnWGQRMSuQLMvad/WJZKosSXA1e4gAi8brVgIYmbIc2kzpFVAw8CT8ZJVQt0dh7lh
8tVc9ifnMjHMk7eBB/kSfTmYqiH66g/FPPIMThz2zJc8uB+JcA65L3cTruK5TAIZfFjQsRhDD+jo
+IQSPEMe5sSQGn6lLvuEYseLQbSEswNwE1xM0mWOmQTgipmdzDR1ApQU7CJ3glXHI7CVSZ+Ptc0x
tMhQKU+3nMUBMdbrbWczDZr8+LtuVq79gy6RjWSEvDiU8k/C2jfU7gvAAhYeQmEWA2ZDfrBZGMUe
ctwS4RKrBsgrdotouRos6i7rnUYet3BfSROrkb0kSdMZRGxAyAEEU/HXaAAC8PBph61GdBPOjY2o
ucgy4/5j59ePvr2AHV13YPvzcUThetgzbOE/iQtfdAyChyoVx/t7MUXlzDXK9YyFeO5akcWlv5cV
/tZmdn+0Ip2LqVVRXFEBSoKdQdXJdPtlxjfAelCI04ov4YoJ58o+t0nhwgO7bkbIx87oHNgrzQ2M
F9Nx7WUW7kGIwr83dm82aDD3MxmSYxoppKine4XFBSQuB5OgrdtAHhsoSTFIgdLrqVtjPempXbGk
sAGCyeTTFU5G+XjRzr/5F6bDtFizNprxJBKDaht1ZHz7ETvgFDqUE1wXMVV/4EQdWo3mWO3IzFHy
MHtIRlXUch3GQNXGHB3VG9FfABO63ISUv+i8letcphRuJGaIqd6D140yb1j9b65V/pllsmcXjxZI
Ah43oD+OViZ853FMzqnn1m6QUPSsMZIRyqrAz1NPtluN+CJrw1FCZVpiTakwpdxU24wYPLdzkJVt
MpfNjTp4CfPgAm7JSZ8uNwQriV6W+lMhO/nOlWDmWdpkvsTuaEmfMCDUgnSLOZS+lGvmuwQqc4c7
zpaP6+TmfafMbg199BGBGKHnAzZYORNMzqGduqQH2rfIjXYsYhgEvrviZ02MrjLaQZP6+Ut5Alf8
E/kL+HVFFRph1szoSkmJ7EBXybrGUR5qMCQirKzjN+9O+mZGlpjLRjEm9OvwEI2YBAdnbEy2PUIS
EppQU9iHilUApIhfes6nYf+wBw90smvQ+ggytyPZpyUuHI4qtFg7oOfeQJsHmMUTERb3j27kJedP
2tYr9qiiRWvUkdwJ4KJwqWf4pQgGognpwYEamf+1nPv2wTMMQK8Xx/yjdn10Y0/KWTAYXLQMmYjz
1frZ7sNr9m2G1bncTeAGzAAYatbj5nvolqrKxgG3z0xhGVUVc40Ki2Nepm+7jD8G0IY0ml5LLddn
YbZpN/8M3Qhx3Xq5oGiH/2TnC8sMX0iYn2UCyLxrWczitSRdquyZOivyQrbiaox+Q14RjH2RZNd5
aQF0j+++AlFnkxA005oCTlPjkpfMTIc4RxeeLQJ/tOK503oFkgsrCogo+yF12lnKy6igucSzbMPn
3Wor45sypUNSbvvkuBCYT1dqOqZXmmu2OwrJxxib2arzDMD+Od3/2YCFIL50cnXvoIjhEB0DXR9K
/K7a88aV7qbJ4DHBzJ3f0XIdiFQ8SQgz7J1rbVBgheu6FymoZephdjJLqZb90iDDQWVJmojtbzXg
gFOUIz5M7rwsn1szvg6OQvvyk2BO7F4pzU/gosxylIy+ZgksSmVFg/qaV20rZ1k+aSKwrFaoQyeZ
RFL+1rHpj+IbGKJ0T6azxeZPrSBdULXO4GIJdvr3Qb7m1uZp95FUpJBDu9qVsBeW+e88fCT6V8gX
VS6NTuR49358rzHdu4P84iHiJvQ86U9hTj3lb3jjwQAZN8p0kHLIhJ/OK3HNXw+RTjLj3vFhUR/i
IRh025GWPgCvLKW/Fcjs6l17Yf4iBubssKiYf8wlCs3fcp9iubVKMP7pRHwefSdGrCymu6kYmLgw
mqeCa1xHRtdyJWo9Qe40/RZF/z5wrG4kAL6/QY4JsNK5IuaqdL11AZL2SCSWi+If9d6xMChOcgdO
Kz8rL/ul1zVN4v9usZdnQoWuT37LkO/XTV67Fotcg6wt/2SklpnESLjZ8scuc4uMPNBaKqJxjusu
l1vSBAc0RfX+94qdKAB1kZkl5L/0wR4MeVpy7u7MCHssLTOzpzCO9upNisBXiFFPDC00CfVouYZN
XXF0RkU9ILKEeChv27SW6Gi7Qy+jku7OC4OkwVTtOeSe3uN21fa0MxUAVDqDcSYih33eUdQ2UgQt
L6AkF4QraqjCQmkNLaNY6/FADaaIph2sC0y2v4R6EliBhBDUC/ueMaaLEicWDYdky6CenbfyuZOC
Uvu3Y/IwIV5G1ioj22TVv+/LM2NMXlM3efeBXVFLlpk0glMoySXNMXgPIwpcUbWKr9MvEuUqvHfU
Ua+EPFCKPWY+MPtNhxODgEaf5SD42ilmAXixVxbfQgZT8KDy5ESHSevUnG4beDCiUOx2OxSZYEd2
WecJ3ZL6564z/G4fc7Om0ZIOU9ng5EgK5ufct/8wDhJxhrKfWKF8oGMAz/NIeDg+KDpnnOd9TWC8
m1C/nAlPRFVJESuKzp85N/iFta4ERlbMXC3KbBhJx19efD9AzC6BaiST96FqCaEQ0gbAZg+5M0vd
sd4uARkYKVZ+saEmK10NttpOf8+fMTy+o11z0fGYxK7evc99er/Gbpf39qG9yEfmAEVRfphmZPIn
SQf7u15eABhrE65ulYC9cW/1kD9cckhW3Ca6Fmggjt0dr5f0xyY9FGPQPcKlXF41lN5BHyQxsQIA
iGo9RSECpzORa/a8M6ZNFsEFb1RNk7PIJWUUTwA3yGJ86kp56QxDSwHJ3pphqBtvncSbkJA4qxYe
VYFrqoPM2y9CnuLtBx77VYq0P4lNlDZj2jk3mHJrjUoyGQJcNWMrbXeusyvrDBumKKKJuoCp8Ji0
/RMJ+8HFg8+R4uKqYvpIJg8NyYQ8vYA5vtYccRW0jvZP/i0U6PWDFr9Jttd7mvkTVOZWVQzQwIa1
CX0sZXUqWjeUdWRk0PgpbprIfHUzRGF/71Zzu1yRW2GCnx767EQ5qKMpDIk0GPjYaqO4xoSoi9aM
1yz/MP17scsZFRtDTEX3mlGXuzvOXzoZuF1pv+cx/HZyvxTWVigsZvXDBZjLh/wgy0creA+fBV1k
8fkV6zAuCk5dk5WqKFfYd+1UeCPMcZKIBp4CT4CSOy97C7PdZOfTtjBE2N1HOoaQ2ZxOQQfwlT7T
fBNkY0FZvjuckL0I+G/gCuS39PwVULFYbFIzpXBM1Nbej2d5BRC9Qd2AZu9sxMPtcZKUu95Tnwhz
RLTAtWmI3jpVmutYnGnpM5mKwhhOdMO3VOC5v3YpF592DzT+6/6Acs5ks+nnzpA1Us36PVKcWGkE
M1WjUqhQAuy5AFtL3rF2Roudc62UHxBXUcrRUznmTU0m6HWy5ij6umKW8aSGQEAuTFkgHG+/QK3t
lkny9IyYFmqLI8pYvOJTBRa/mUHj/dj/6NbKzslOo2YhiygO1nVPUAcgCQY4cgBaV1HZAFPnSrue
xDDcyoDCQ9XAq7HtK2PK5zi3RkeZ2APBYNWexQi62G+cTV00wfk/mJEXllv7M1McZl6EYNB7w7Wy
NSFsKlLu8YEu9N+Kz6RKVjxTNxRK8PL4e5PF+lnFbOzA7pjA2WZ8s4rN/GBsDQxj+iRTW9eFFwkI
55pwh0HyA5SIW3FjpJUf7cIrlGZ4oEXT7+1t1T2BK+cZECsvU3yQPWI0wujjI3BHqX2Avcr6Gfjj
Zt/BOCeLm3WPYbVnr5JtETvK2x7GxSyH+9LMO852zV25Cd+48P/c6S2Kw0ca728Ny1Y6KGbL3qlP
4EvN/TZ7etw5UKea706IUXwIQVwpP5jQ938y0oHDYwffAWQlBszHIVreDFPDhRH7grduFfXwkAZq
Xg1+sBIztw+hxqlMs53QCz42G+g9RWycycylepEsvcSk9fVNm6VmgeZfgi6X66giRnNJpU2PIBAF
TmbPAcrMrGqiw6Igp/NT9dLv+HdaubjRbMktYivcwKhtfvRJxOMuhYot4wWlUUavaDQbJmW24VmJ
ZwCVPPi6rQ4Nhst/OnX8HNiq2U/gTHWXorogGqfyr8Y6nwQ1i/rMdmxoA7b/GE1m9P5/B6xamFQg
EwXo+CxJrOCPsGlEdrtI/EomayDvxVj5CfvkkF3AfbS1sQsfyGGG1tUvsuzyG6HbCWTS0DgHLYKw
mLw/kac2HudY+pRGugwjN7CsZhMmmjhzcrMq0IOLuASVzEQ07NRtu7qYo3gXq8qnNgGi3DQKDYrw
SYfT6Pwt/XDOLV/1Nwm7lrkBfprfCHgW0qbPVabJczWZCD+LcxtBQw3gU2094NvU7pb7yPhlgrq0
cS5wrnWHRgkSVTP2nTdECUOf2uvdv6UAYuKZB+WHxfuNgMuJy+NNx5KfDuofgKn+lYGw6REYH3Ka
ZOfYztF8bAdIPEvwSawpzhGQAiNBWeC79fEj8BBPy695w6r/wK/tqaFZeWkyTtf0I3GsKFAFjoZf
KzKY+NxdAAJi0qPk4lVk75CJ8kptfpPfFywJQmfyBb975TcM5vpsuS0OLQ7PPrjlQ3gHCKvA+H4n
QPQpKtQRoRv3axSt2d5bX+nHX7sDe0XLK+YohWnf6W2r8ED9onbhdOXu/KX2OHKoCbv/dCpO3JIs
yPgJIlcsES6Z7VNPf7AG2iCOhM8IJc2rkfWNF05kCosrhh9zj72ovE8RIohjbE6NHLiuUlA8oede
e6MJsIbj7L6BcoK50YtZJ47mkqQ53XN8aAc4J/rI7owAq6S9g50tYefm3L0nPbuCGWHERzd2gjBj
eixz+xrcNM7tnJIQKf3BHG5GEXQzMr8loXRSFArDmZxS3+X0oRJlIt5ZBx6wPaJLw/47C403FaVO
IQ7rKIj1J78aFfPu3+RUWyAxXdSUla9IOrNugivXxl+/pixnEdfqFhdGh7sINrMDr3Gva7MydLld
aT6Xxy2ZXoCIrn3QUJYKAx8iSWuYEwP4DqSnDEcIzqyptarJmsEalMCp9GrYMqhCwNqKhm7QFRVH
EJZYkgW+8UMhys0ogbrtFGbOrQzAPtBJbeUFIniW3mJQMXc79i1yiE21ixQ8ixak+mrYSNslA3e6
hUZFTZJoh5xpuHQYY1nBk5twjasanafpLNUSwBeNbZ44LL0/WMXxVmEI+OffB5P3t3OhAtcLuUmq
dmfqUu5wfet7GcTzjZMame10OMV+omk6zhW4JKpGLlaOc5wx6/zoGhGWuaT+cWFv7j06y/IK1Ge5
VwYmkjNekZd73ikRPgWbiiTGW9uE4WwlB6bawr+FtFUk26pt7kv3iGZfcaexkYk3gFuoCjMatcxm
5iJBYNcSz8AWR2X2L+XKSxtSf0hQgxgqoTL2UfsFHmKChrS4gCUThdVlzTQXUx4eyHaIJJH9DnFE
M5L/7tl89MeROUUOeAtes3QIlHeFFHBL/Ji3cfap8ryGMN1/gtgWdRFkXnoX+G6hQhXwma8qXikA
LWFDlKPRFEnz45o+6OCrGzLwe/otDBFLGfQ+GWVpN0kV/uZQ75Sf0e/PsUXpFnaLewiSKank6gwi
8yF+WH1FQE9YQ18xUl4fwH8mizCAxcpFYsA0t+RbSUT3n/4OMU5Qp9o7PN7lBGRIO5p6cMtXRnXC
JfW5MAwmEbuYLebmtXFTuJDEJn0GyquYWPiwpRZnv1ziMZpHifvHl8+OztIxJd2mYoB0qILovXrv
p+sSoT6d+Qt2nOaFyPi/m6CB3U6EZTDb/lY9CEtizEw/HAA/6VwkE8uIX7K7vI/hr2H0tduoiiNC
Z7Qlv61NGDw+Zsk5lf/EB3d4KiMTGGR+U3OwHtOnm6VYC8rcu1iaHeniGKq68Pd4RNabdW0SEWBG
SCsEB5twlwDDXXKD7ZjGPdrzFL4xeUQOh7FvLbwmC9sr/yhddMvrFkA2V9wW905QTisuA8OW3JSB
AUh4iRU5p3eIXnK4bV5DGLg5qrBMXKp7ITgTUsrz1GkN0djgyFC0XYoOcjI7B/yHlOip+3I0y4mv
lvXPbxrefN6gyKaXEaeKqc8lkTrapgWmcul9IqE2dc62oipP4yfF9dyU9mxlW10geK1g24KEyzGo
BeRphtKG4Qmo+nfR7liloRHvowONq++DWCDl7U64lFtPGM8DVJ8L3f2O4dZ63W280QNqOHfM+D3v
oYV1BCKRuIDzGPh+aSQpVALS7SpCpa9vz5n7NadTJvhdFlHr4KfuJX3Dh2oImi+n71N0Qn84euc1
fOD4vRyV2dyrbvpf8ZyzqYuhxBpx4gleNeoUIVPfagb2FoQQ+bskrJ9Fzaop3uYeyYjVHHz9Hn/v
kD96iS4c3YZAm2tkHGVHg07+rB7CjCZASOlDUuBZBYy/Vf49Oo6ZIbyPX6zKW1HIZX6TCXgL2RMD
Z18i6bS4dVWdamjHoVM2FEWy0zWmP48ZzqIofGQ35eZ/S/W7DX9ElshVXWSoz2DnttgcYeQP85Uy
g9m+ziCUZIcadRW964AoRUA3+eqQFMd4s3bDuqBW3XcuFpHSRPXh6t0Fs16Zxakn48FFt53gPuPn
kWccmrUbXLvLcqhA8NtpSsiryUclKgessi+7wqGZwaOZ/56iVBpZqOJwABqb37gDS4naRX5Lhm3s
m3HaTaYcXMsCHqn0auTQIir/uX4q5UPZFQ8Bz8UC3UKxfj5ULvWsnpZTirNjNzizmAgQT8RVbgzU
2G5ppcdSvbuZsNpQGRd4Pb6lyI9TgsK+1nbLlHGhemrdiL/34MiuObwmSLc73QRRBxNgFET6e1Lv
o6xWN/l6TErNc+6EiEwrxgHsEDYFHeG6qnW1ueS9Lpmo4/z7e+6wy6Tl/b5WouFHRr5e9BLEbuxz
42BX4dBB1w/PfHqyvQ9VWKQ2jLS19zH4agGu55yMenuP9MgLtErIMJT+Bl4ELPGwB6MlUUqTZB3t
VQC2OppjbtSjETZroDDv09xkwKjiHqEFViOwEy3sF9EdAetnX005D6kuc/K3fTbQi+m6fMRiKN2Z
BiUYhf8XENvED3ZMQxboABD11DmJ1e9Fs74DiyxWCij5drQwOkqqstt1vqKAB5y7Yfz7BEDaiFt4
N/hwftM3GyDIag16EDHX9KUEehn7+WAQVjm8M9q3X05bEsi+YJzDYvQ1YUMmCywjgkrU+we6Zlfj
jwHfaDlARpdR7SkNfEHejmsi+v6oKmporsGFi/PV6Zto0tsGqVmsM4rG7ACZ9Rr67LZv2ZBYmau9
YMgEVa7MgE7o+XRH98+6g76U+vPo8sDSXBzjLxrUWj7LbaLAwHwCiaHAk2NE6S11a38XlxU9q4Rc
V/ZeXX8H7FNqwpWafLtSUSFGjVEl2UPuR+LqiFTtg5pDbXTI3RUZ/1FTQXdKgs8mgkiZobQpzFE/
rrjhpfu5U2VFgUt175KUgZwXZkH/mSNkaexiOIwbfcsZBAy/tKw0ZMHpRgmxVxs6aDNEnWMppYML
mirp99KtxeiB4YkVvhoCIgRH9rd9f8SjF4hpmqeG33F+I/8aGa/B9TDn9mIOB0MkA9G27OhNWHti
BhiDpachcuiKHNRXtROW2tZ6QSKltulLhEE2tKS5ySwwxUggM23fjcafEriJsOg/75JPoP0f7KSD
GKya9azUZuLQNLPDToOlCvYyOgxC7DwAJSzAineFxmxudrjNaala4ME5f7ber08k0H7a98KpnWhr
7Wj2/ZJ+vEdRg5LF5JobYzKvmpaM7hGgOO0Y0TDtIOO7HUt3HbEwZQnXW67gaNwbS1SMvRGswaYx
K6wkNU8q8NKtgBuc+BLolYfLBZRJcyR4yNDpU2ZjHuWIT4ts/OFFXInD84SDkSXjHApALHfZxsnt
cTfPbSH8fDmCJm8Vuoqw1xgU6RGcrAVPTlI/Bq6t7tCPO+YaS7Zc7owdZvEsNMbqoZsmDCFe8doV
8cVthfoNVR0f3SFwHIhWyLqcudCO3w5Kbmclzjof/qugz7XI3W4up1D76MJKqi3dcnruoFlabFxm
tSwx3GSlL+5B2O2YixhTq2xSfw1sszftRCihJ0NMSoRqkcjUCZWV/isTBo0MmbQfNmdasTOjZ7ew
2BGPXSHQT6V3s6XY14QEqIGMHPF5erZNNQZhY8yMaHagYfd2U+nuwBd7aS4EyGQFpNTw3QcKE37V
hGX17EZiG8Wq6MY/44BXOfTCtCeKo/byhuif/pVMsu+ca4R5zGuY3CiVWYEsPvzxF/qKifpxZi51
XRmtFk0dvxCb9LZijwdOxnyH8ZiWDHs7mJnDVpcWUMPZU8IvqumksK95mbWFPl5LqmMFM0jEs8PD
mTfV2GTjPFDNIyUlS5wgr5mAkFV9aGhFTJyxgym8HJTFTPnH5yHrrcc8JJLtN4hU1di3Xn1fE3uT
opoRvS0bdUapON9OlwVhd26jM7wCZBYB6trMJ8Mp76myBkkv39NINwvcNz0C9PjTC2KxxPuukWtR
w/yhSCjv3HZENtmeUszZgrIUGEER9oAiD+owYoWYlewK0ILXabNAqrhmEBqBHrr9oqgbcYRDzuYy
tXp0TFqhsCtk673OJdQGB6Oio70EYcvfK2+/+lQbm8RY3MMrGTIdFT56B/KY7jNhS0GK2TQxwqhs
TRZFKV/ZJk4siqHTytH15d/JDe5gR0ZT6YLiWctRZ0o7rDFAuWGOts2T5plZkYkKlicuij/brRUE
VoPwjXc21Asul2nGZ4oqWITvNNvqsSj3pZcib/NkEb/ywxjqeutPrWHdY2z9bYYV0afl6iN+OJPF
mRYM7kLjlkifzhHkjMHeNI/3PFm0mygSZsjtHDrFRcYjNY27pFqwHt2ydv+Y8I0N1SDHvn9BLNJu
oFVKeuo90KYeeut8r9DrRTYqFOonG2OEQDDLAFRufZ3qQCoZzCVAz2808ZTxpmyZlUrqqRB5eNoR
fjg1JW2zKpsRpYXTmNQeMRdldk+Feri5oq9cGD5YRVbI8qXrgCFVgnHaSb6bgNKjoxu7ljGDhDlA
fyljqWnwjpwLnJrnLEEPxCA0T5/et2QButOgW3nnwmS1l46RTyIuJvDC37QKPJAoZiXW3NONxQ4S
VMkIxUni4WFNp61+I8ALmhKWYBMnSF2olRUJgjx/5EoFbnaRnuG71h4SLeOPIDGWQZc0jBwrQoy/
p39/L/g1wLZ3FqNDV7qggQZ0GMY0PqS78funhvJ8e59DeuguR3c8Qw2C0tcThu571K4wpX/OFbnY
beeizjT0zdkHhRSex+8gBUGhTbaSXFA+qwXR9xCY+C7zYRTKO8Nx+cPPqtw9pP9PxBswmjqhEKt6
3Ck/ADyCLZdGREp/A68XVGVvHb/JvfOg35vhDTnY5YS2yaSxtOlTrfweIjcpHNm/KYIfyfc8tE37
vQgFgsHKTN1WfK5wTNKf7aRiY0HC8102JHI+A45viX2RWjDbdLJq2Y7F5ppx0BUGXajkekHFHtTP
zGH4mWnc+ZM9cxpDbZHg9CWY03g1SIePCaPv+IQWravG0Y5/FjoT60o3H5FyFBudgMVZ3cp8VzJe
LvD1NXLx34aC55OogymYf2wimfHqDswutWmnj+tuNMEDOInqQNq9UcHM/OyxxtX8wTTT/NRUFeVm
VeKtfofxOPU4GgEr7q/dgpmmyUwpJdTmUIWgEo/EFBgHOpfX6wnVmKNZLK/35u6h5zONTzL/dQna
H6zFQ6I+cQKT5ug+al7l3k03OO7iBB2zXBSdPjOWpTtDodnsbHMw86WcpUsjoqFkiDJh0K9pAiTs
yu0YtLXYhpLRc8vLx+nlNPLnBlewheD6Rsel2vUITR+Y0R+LTIVcFizL3RkCWpgT8Mv7GFBus0bs
tXa7x74NoVvDOv16dK5Bp6co4kem5MjsBMqulNnb5qAiSRSAHjJVEcbgiN/ejphUzKhhnQ2rLlmR
J0srKz5SDkt9GoLIIQYs5LiQz7IybWCgpgj6AsAgzJv8o1wGzGOJFcuutKhU3byY8gX4mvT1mcoL
+oV0fltqMUZ5+7fYGYXRzx+IoKYTulFlekV7KaIy6pn9anlT85vVRhfq3tNZZRGuUALVSiHKp1Bv
hSH5jlo6taMLCDODPF39Tqvftq6OemOjXklUiPQyYpE3hA7qrG4TTmxYZzDSMPUrCpTcgg6vjYA+
icfYFMU1pgr4fLmYJ0fROfPHuGJh8j+aeRnjdDL1S9T5mRS4VQFv2nBpMet9lpa4++KbevKGFfwJ
BO0QF4h8xYmLMoxmJE4LfilYtw9dGxV5baelDnfq58HheZD2ds1QdE7sNtEpXV6y/daqe+F0IrwO
EggItvtulBViDAFHzzEs4Ors+9e3U7TiRkh+FQouUA4zwFshY6xGA6Dbnol3ZBzdaBUiUM72DESu
4f8i55WEiA1ksZPV3YoWd/4fFxoy40yp+YAThVsC3PUgYwIJd+HeGGy4QmzfwbeK+mDAR9fhkgPx
nzDL3LV2Gv3HmCCLPBRF3HWk89YHpBOvD6r+uOVfqkM48561HfV7l3A6apzVHxEOEh1IyTyiN4f6
3KVzCDqCvavPKeaSnkFs20XLbL+sYELy1lix4/B4BOvvSBa6muSI5EwkO9IYHRp4SldDU/BoT6Cf
qRS1nv1bScZ42MttKPlYo5C+D45g6wpNReoA61TtaIEPBZNYtLw4TsZyYTF8v5ZzdClRynhRzcCS
TDxMcqXxYDSNoJqUrB7zcYe4AU3uO+Tj6wXoA39LLbsKtK1EY16dK5eicLPwSoFRhW+yHzcF2R0r
WPJGyuHI7ddZdu81doAYgdtje29f2PoQ7UdSTUx5TaBtDIJ3Rj9hzUirGokvUqbl7/aQny41+3XL
F7yI+f+1hfB0KztcysNAoH/Ef6mEeMnfNIZ1MWfgKXi2mHySkygQ6NWZ6vvA1E4qyMJXH6Ff48/K
gOLCxf9q2hiWqZQnp6Xn75CfUcw3BVuhzDPyLdr0RuUnInmBo6zzYXmuhUgWD3UZOwbOLMbQde1E
4+ppigWbA6D8yjjDH5d///Ez3Ge5UANdGKtn5+zwt6sVz/UnNbLaIxHavGC/XYYHjVzK8UBa1goj
rRjxZYq+/vP9jTUVM/We05Tuu6Vhr8Xqgqbs4LxdLvSY5ZRtfkiZ4ZCcUX6PAd4EH3/mr2iiXXwk
MaHxtETB5c92jL0MYVhAngHcoQp4PXcVgMM53uyhUPz7f2ILQV2YDlsJucEYfDq13cpM0FlEQd0h
5mhrSC7d1cT9pzwN/S9h7Qh/HzA8ELwUmuPuJDo2/TpqVz3rFrdQd6zrjucPEC8bNXyMJ4KKbI8D
jSOb8qPFWrNmF54vmxSvOh/OuuWoD9f3nVoFgkV+u9aHOriGCvKVf9fo+9RKQjPtDXcFXUfhU3Cv
MzmWBqGndqHMPSFCJwZft7uzO4LOPPH0VfFoxWhRynQwCPBocMx6x0YUJV+M3EFU6Vu7E3kJrFsl
y1fn4yO53dC25b8g4zcCCiBPZyfjr/dEPpI56AfsYVso/JiXvsCGk4Q44hgxk7E2o05UqQCMycBS
ygQjxTdflOik9YO+XOKbMzwwOKB9IrJf7iEl2lQF2K+TkGRUH4+zgS1JhcVqHPMQR+DJxVpWfM0M
H47wPKt6giCxmkkimy+FeHTdZ6hz+24lzsFu3UbXHAwWbAtim+kz7tWoUwDCuWtRez90LMVibV03
s9OTE0S01WDnqkPCfv23N97xtDZeKpUclYjzfg8WN4IphB+xKA760It6EE+vAg6sslhPeEtILCY4
Uo32QdRhD4sEjjub54P8JzSNxRxNbgJXU+8ynehszPSEyuxl5dDi1AscV5lkhXQ99VE3kbMI8ilh
QVUy1qYXE9K5fiRAV0MgOjL6GGRYoTf4n43A3FTs90xm2IHT/tG6dfy45aY7VCkDyOLAsNg6qbjb
S+am1g2mbZSI1nM9RhmFc/sBTe78Kgm7HWfCi6EV9WsWjqKGa5AaRsASsm7bd1npnUKXCxM53zTI
77Gkmb968Gfj1eaXjJQdf892eoN9RwJPsCC18O81xXkHoHW9rpUzV/NkTfGJToNKY6n8O/U/gp3y
AG4NmQb+ohRjIbQrMorHExbrqsFGL4eC3yc69mOV+v1CTYsqda7U3Kustm/djGTSpFqDUaNUmNv7
s59H+WB4s7H0P4v0ac2cjyGb2JiekKYXjqytCQsMiVJwOtyNM7tOjPKEr5DFyVazHv2pRLOhaGVG
87WLyoRqDpuHLeZLjrkoa33bl1FYrCa3J6+jJ7/V3xNnIZQChJxZvKwYAjZaE4fMV2ZZJnThqFaV
jzThXMsUKhts7V+pxPK+9zyGMAfbJb+gqTodEbZFGJ3uAmuFe4/D7u5r4ULee1EtBh9bcw2j+Ola
cNtHZu9ufBxtKXSETdazieWpvDhS+w9bsCl/1kwyTaNvigZTEXWAX7zN8t/Lv3wG6d57wx/BxB+E
F8OAUdaEA/l/kXOG0XbxRG2wQEbzuLgDFSmrE62VEjJinXmf1q7lMpmlsJOGH0t6Vpx6OC8xz8e0
9F6q/ODk0dxRYn1TlLWz5oHLnk5CLNiWA8DqRrYx16q9uzU6zk/7a2dB6MGsTzhiIU00omSXkLY3
uhJSd6oKTQspc9w3uPCrB095lhsz+vGhD4iM4/CS2HsS0zXvKKDnVX6r6sYwhAYS1txJn8cHejTS
33a3FzrLh/Lr8tihbnmzdHQJtk+sq7tZb72rWrEbk48sbF9yJahsTCRqNmxxIiHoM81CkKoI+Lxh
cfc0D5Yp/MomiNvkLGAQL9gJNP3W0OyucO7MynZvbq3xjQW7UGuTkM+U7elqqbUSHoc+YvoRMbS0
Wra3OUa9vgiPvfWOPUXkCzQ+GZz5oh+zUdgV9KFSEg78gDsnyyeW/ilBD6TtAk9pe6QKH83lGlA/
2bWItSalCQk+8HJxYzEowKqYFGa6IaIc9tMb8mXj8fSJrYpmGSaaPDJJbiFsHkgzUgKFO56A6/eF
ldbJbZmhU48DLTEq3y10q679uNFxpRjMbj1VLTSaUJ5hhfLgA9jgL7ku8ypfmsyML/AFtmtYlAYS
x/hfNfqd/HxrFDj4suOVtrsEgFli/p8rQFuk8bUKKi+qMACYCmucfH6KPKuWAuxGCuqam7J+SLhy
F6DV5jjns6q2TiCqwQ/SFDGGwNWkiXwsljkpcugaJxrggWO350nMbF0QYxh1wDeVmRmPTvIktQeN
C2vym6ToRxoNYTF2Tp4Y99bkBeDapsuHhs2C3sEBcQs8X6JL4hEvCnkrhPhAFYDvUWiWd97v1xEF
JXyVXUJkVG9BXgkFfhxRC6VBtIUPWaRXjsqkEhgA4GfNh9Ato1kt2NsNy0Yk0TuxhhyZVCo9JfjN
xOUbhJqEzzlTH8+IdmNPKx43EGDT0Lrsk/UOaUPBvFWdb3GqIMg4TchPjXgWpuyR85DLNpqWKB3K
K2K8dzks0hfLCIP0o1ZrJyaV6vTRLX6GDJX6JZRDQIcYVYCtM38a642Um1FZz9czprkChHqQfL3B
NzQrdtyK7LIW3fUDo5pKTkFMk/BrlxVPsmRbDFKf4rxCbgZA+dTNUmlpBauC7VYTM5YFkM6wgAQf
kvhXW9lkApSLz8wKN03C6wRC66r8yh/YqKG+OjTUsFovJrTDokQK8MgWGIzpNPRCNORK91DK5GNY
HEXIaZzdLIwnRbeaVleFh1M2/3aFZkINsBeVqebQim1r/XodkwvYfRJymSowdoWJn6/gXjWYYZGh
nHpo+U87TYAoe/0bNSftOYIRvEYmlBQPHk/YuQ7Jdb5hXqiv8iaBtaRv3kWfgGc6JF0PyuLIJmQz
sePGBoxGEAi/gTPFAp5q7bYdVvVh+ebZ1KPCkgVP67PIAZMIBdM7ytHOVT5vyhBUSnzHGj7tsaK/
AqD6UoWrkSts4FsZnh9O4M8pkE8Vm26V8YWdgHnDnz87zqQ/CBdX9Nf6pLsk7Gm/k4IQqgnaYV3Q
djGKNtk3QKG8x7u/AfFVjfC3uxos9Lej1HjxSt7yMGU5UStm3a89d3ADmdllSmHXG8oaJwgC5yD+
6ZyoV+S6O/inHAAITWTqNss+CZq3wQ2fSPRm3iMIYujSFh49ZWF6Y5hhATGZ7puV05IkX1gc8Ela
qcxST2cD5iqJ2QwgOpu3pXIdq8sop2UlJ2ii2/Ct6PF84r15S+LX3gLwJ/KnCGF+GUwOWmRkx3Hu
v4EWljx5OFiNNQjpL6/VF8J8mZgV0Yatyn1p4Zb53UROPaTcM7aRopMguRKwhgpbxYt/+eTJW6XO
DU2onCq+kdiW47TN2oEGrRxvPPPOq8/oSOfJtP28+4j2QIWKpNEEkyM1waSHRIK9ySAFcsxROSmZ
y5VUaZHpge4mjt4o3wek/wS6MwWVPMsAu3hEPxAU1KQr/u9URt3MMa2fLlo4iYegrEEYe2yLrrAN
jfOlfFl2WAfnBn0q9dqaZPhtJGkjLcv87aMFcrI8E5sRxgPWXNHe5E3yM7fFaxtQ9czAwy5HBQ7T
gJgBJSPfEfU8e3x0JPGyrdeTDJ3A7ttFutTZr1mNDvkDS1bKipmWU7JPSOW9iMIXgy8z3KaMV17o
y3aq0spIkFtfHwEMlx5tdEz8T/iwPwSqX7cnQdq/VsqDUNNb4SVzr+cYcHaGI1VbX/0HzDuMomQP
8bBDfD6NPr3YWlufkhrsbQfYW7WwfFtn5mraBA8+uYpAnFvNL1nN6ushsbMR1N+vSXjcYN5NACl/
H2124SzQrgKMKsLqQRU44LOU1vbHbBKDecnaquvebNH7p2feemLLqYcfbhQerM8RTzfGlW92BjUa
pGu7s0UvPCSvVvGLI6kKWChXl/Ug0dnDJutwDJbPGIIKIcK+2NPBDWx7NvZcgk1vLArNWzWWN5i0
Z8dDhZ6CzgsX9JZYvHPLyXwjLrgSDXp6EkJ3xaVltlxsSPjIWuSJ5UR2t3a5j70+y53DA5hawRIJ
BflpJHyKmzPzoIY+XozhC5geLbq+MLSTkXTA+Md2N7j1po0WdpbtlNFxKyHKeOmAG5tXoFNxuonX
NfKY106GmQh1ErXt/sv1FnwsfMlB1zi1P2UI7BNRKZFKqOrCBbJHJCnZXGXx5HE1jHd9qZY8pcf/
raU+1iunjRWFwqi0m4Q/8gbHQTiFqXI0Vta3iD7PfOvOLzc9cuejpa4JY/ddtS3kX2TIpZRySbii
XgeFxsoRZG/o05PSNLi9egYTmlUgVS8d+uK+3hIvzh7l7GM7KBHA/q9Nsn2MXkbuM26NH3qxiAea
Dn32PsY77N/kRaam/N0h1Zw1y+Yze0k6Xo7SvXAa3PeIHINvxYjsqA0DUbJAr2qJQ9ez9vPSqTOB
Dhbd/08MfHVAhXHpF3fM+00YOk9kcYkG9Ri/eeixt2oEDZaKzJLnnoqvFxeWkGjVuZfdk5dOu9v7
ExEKEHZo+ZvJiEXLjjzmDtZFould5AIW+q3ME1xdRFAo48yScl3GdhltW7oIIwCbxONHp6pPH1DB
UKn3Dh2Z6TWDBMdTMe2/L9TS7lojLF/dKkQy/l5IxcOXSsyxUWAVpL5ZrB9DtijZUUpLiHlAFei9
Y9Z+k80OmqZhY2yO5s8R0ALs1Ft48o5GjKhCgHF72iPb/y0d1jf95FfmUoxwezzrhskMaOCfFgg8
AphxbFX/k+52qiLuQkjtJScwGnNfZDEzWfMjSThKXVI/arwQ7Tn55JqubDkyP18b3uYJ3czC/KiX
yv+ED9+8d35HV+DzUtygwZY7rrisICcU3NFk7cc8i1jdolvkOva04x34YiSWT+zjbKj39iDgMJfP
nq1M1Ah0h3m9u3TgvvOjbzfU5dUNe5/RyIdK0LTLLKGFZO1jZL2P6ntEgfg507gCdVHVavN3mTHX
IPwxe6Y6aJ52LnrwSvqTlTplUK3PXqyywVm3ukSQ8najZI5ITtibqu8sJzJxPESP1h/CGEy2irf0
tKuFjzq4iUmlE08KwGR6AdQ90uUyDZ7BInDpap0TUFE2yqj+Cmg/RLdONz44miMbIJ+DAxSUi2MS
CVoaEGRDgZX7L+1GCwlSyMt9OauSexn2E56pMGI/A/PNjcGrIdxkutQoK2YRlg7i6f+wNb9Y2gcM
YzNWLYz5uyo3rNjHRcKm7HEbiWcCdoOlOc1k1c55wLySin4bgMGuA9UXa2pj15QXYNFMeJbtfhwm
ar4+eZn5WyZ6Q7DhbN8CKPpHO9TyDPvVgQmrAQcWSBAx1hC6wirnvf7ATJlrz+DmfHI9E026mId6
KH40lG9jMqfrWu7g7s8wz6nIBiamEhcd5objUHUEmMKbsASQjGVhZA6QbCbgAukMJWUtjQs3kGXc
FgiOMoJpGeYNPE8MJgGTMl4eB3OVuQh36cD5wqXzYC8GP17NZ/0WINIk6TBXOsOpv1WCDSwhzshP
zuOsK8lBIWHJFZMEZp1ygQP/cGs0RyCqkD8ulUBTV+K+EZcy6DXjw67oee/ALKZrhgkjW/cAGZxd
eGZowjoQwZjMCPMMu4WX0cMnUwzIo4hU1IQi+ktIpNRZkliY3/li31LBpNye1mMA1I1p7/jq9Rb+
No3LbhHCont+fMEy734+6OiLsjBXts+/ro+qRqYFtjyT+k0RFo619T77Yp2untdxkjuR6be0s93j
vPwKi2VrjYaTCJbKSM0oj0YtWmM4nSWlNLkS2h2rjbGdujgcDPlU8I44Bo2G1oMGiCui9FodkZtG
kOBqtjbv1R/z+321jpGACzq25FPJUSd1xst7U+0GLp/EzuEpptq4ISk5nnvG8OpY7afVlV5aPFsj
MBQKt8uSzd/dHgxVjmPeqp1cV0WABPcaLzC/ehxbi04Q
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IVxyk7XRM4VsQcD0QPYws4xsTeDPKdwWYfreQJ7l1z8C+G+JAKZ2psrNI+b5ecZ2ziPH9MBGr/oY
8XtzCKmjJw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VO3Jpo4aYF9TyVwyAUb3a/oDy8Yhm9ea/9mAjNtuOBRL0qoy0/CWzL7D+bc1SnZvEP4BG903Ildl
dM2y4TNyVTBUaU7Cz+LzZfu9kCPWnmttlx92LcMKLNuvGUMPXmV5jr3PzSFEvoDuCinMqNc8uKFO
Ux/aX6fmBD8AbQfpK30=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qOkimDe0rSU5f1zKvoE8a4lZw1WOOUxh8wtTIN0ys09AXuQuNNCdfu6VL2Xuj0Xus09sBU1FazgW
XpQHuw7XcozHRlnUFKPJg2P12yPJsLRkOqUWtHTUXmH/8s2RglOoEcmFeX9FVh1IRMdnp+D/F4GX
/80OwH0Jtm4eUDa5EFkNoIfhlOG4JOG/JCsYRnsAoZAbyHMEk6qPxdOGDrYzkbA3CMCikTuE6wOm
0j69ZgENzpWR5aludQDu44oKZqgkdMKNm6Mvk//s2aUOTBYWabbSKe/I/+cEp1tWS7+9AAmaVwO+
KwmsZsNR4Ztb6OH4hCq0936o+bycwR0b+Wr1VA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4df1QYXbx3PmA5i1scwSy/ZAJgZ0wNtl21eeCeUI5h4IQD2UalJOUkc5a5UR/j7lX9ToyF2yFHzK
L4EoH+xXm54bGihfoaTvocQQsWhCDObbmBOtqB6WS1/bog7FNgoEObi/E19vJsjPSd6nCCdhglZ1
j33mJRkZed+lVziTR/s=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Rtu5N6w0tnewss9ZQUyM3gMzu1D5Ba/+qJO2rdGgk0QN5Nm+4TaVyiEXzVM5DP8z3mycaRD+z4HG
QXarW6RH4GHKahoLlSY8cryjSJRWS6D7/Z1joY2fgJb8apydMguGWjRZ/uW6R7BEimGxB3Xuon63
ZdpcvKZmoyvfg0kjAjor/DxtP3SP6DKxH3BeegGQKpP/+5EmCrAhhPu+NA21340wcbghotvyYusJ
ErSZhtj+1FLwV2sO7TUt1etBG8nf/yETDQPE7Q+zX+BzOktmY3tIKds/9qdyDt6Qb5WIxLMyaMa3
eyi0SGAuZdeDtK8Os3w2ajEZI+VjufruVqtCCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17760)
`protect data_block
yvvRtu+tA91Rtyv3I35O4K6BiUlBjs7LTFLRc9twWgYZkATXrSpXZut2NlvE8mcC7mB31ueT2vlU
P9hzhGYaJ5GcmScpsC1FKNndMfl3Ug9Pqiw49YT0Xp/AQWIr+q38Pu2DmkLm87YVBi0HN6JMSu6G
rwJt5qvXJYVA5oSnqcy27I93z0KCdBaCW4BhEaXbMLEY+qzcYsWxGhgjRzVfC2OhOSpdpDr2MKHw
1YDri1cTZAVy/b3L8VUTlyQx4YRG+qS3u0Cz3dOLm9nglzh9Pa9XJC4+Lnpli7w7vpvakaXaH9W9
I9Xs/9ShuVul4UrHUMsoz9V5jcPh1iHPT9m0ZTeLUdfod7NEEFDW47vWU8XjL6iEqBvA/DrJKrri
hjJ//n7fbl9gjxGZT+IKqHleRVz+dRiS/uTuRo22UsAcWrLoCdroE0x4MAJ9vC0vScZa86PQBj0m
ixJFhU15XHesAUmaWmkIVFZdUdZL6n63C2nZpQmpBX8G1td46ib/xrjcP1HPzbr1hPb30S/GA95D
4e3ICss1yPb8NZCwvzZHNKYRJlVJ6EOWwDxLeBOjWmUySMUcywo+toi8FWztPmB/Fzs/gyRSBxsb
FBe82kj2NTjDK0dD4XCcU8bGjVOKNJ3KoJmC+0UD0jihX5N1CdPg7+/bvmP+MCdk3ondXZKJzYI3
9YFYkr0RM2BhF57jZwHcHHmFJrakmG38Lap7lsdonuIO5mfOOuicr4JGW8Qijs1+c7VMc6LUwGDt
YKznnHTq75vwwVLxmtGYpW4RTIuqlZmOJwC34kp9oVx0+wFtUxMvQgXry9FwUwb2gSWRseSfbmMB
auDz+22lW+enEoOu3PzG3plNq4oQP2K2H++ZU7HNTNGSA6VpJWDQ1c8o+i7+XEkyIqt9DZHUxb+3
HlbwgxRkMYX88B7lb3GnNDLF2YzkJMgQjpyPi+t3N2MtquCFuqNuaKv0LoD6+mwRceg/hAylp3x1
m9DKQ0DcKuhctFlcx3aOGMXc0mzgjh9Umxn2Ng7JEliL6/L086w36Jar0AAtsKsXZ1NsDDBpiIeT
c9pWEQj9ud2144CtZKOT9/hr1wy8/jpi1lQaHanlWWtc/eb1aDpSY58hPbltVjUTyizUFFWsqQAC
PGoqDXF3N036pR2Ipsz0lKGQE6qHOZ9IQByoJkJfVJQFD7arWnGsW4G4I9tdTj8LBH1I0/XQKvur
lSNx9C6iPx8J8GemXPHqEIipG+GgoeMURYc7ft3GzrBdwbTFPm/qrxT/0vdju3tRDBl4JSzWO+do
z/s/CD6wNYNcDBCSDKcprRdML0+tkUYr6Jexl5rxIe2GBG2XGRgBDqc+wBSNJY7VVfutmSr3NjPK
RJK5NldZFn8fT/rjewbLV4flhMn1tgsE6HhNm8GuRS52PpzP+BK3fCtYvb1mnkFy+e3mwc3RgZ45
5iaZGmsBwnJwI9GcgMGoWSDkSaL/1PrI03WtUczFAidTPvIY08FA8CTdX8Bo/j1vK5yj8spVzrNq
2YNw08dzyQOA6p4yaEO8Raki3qlKk9oCGUe72zvHFj8EIo6DPYz7MTOBMZh7qLr1JDqBA+iyQCSU
UO9dElHR49OYArhLqejxnXEbJqi2McLLRKhJoiH7B/feWKz5mjNEjtWpHgiwx6VhyEKkL6UZ1Rib
ZtiEI9gtUbhZ6XzaYm3TiIRoYgTzxH0j8bAv7Zy61YnOi5ds35hrlF48AdxPXK/eT9RxLQ9JC4D+
xhLyqoQdstrt5DgaM3NxG2mKEJVH9uc9wj8j/rmn9YrBedhVek2F8Uvojvb9UP2S80Gz13xgD5DT
uHlDBG0pjratONtNE06BnMLwZRtD8fOAmitaJqr+uurpGUSmFSP1C9+FHTWgzBTdRwxLO8vYdEOz
WFiLspZhFCxJpRdUt6N09XI21qtC+0+ZgVoJcuL102pig2HCGw+mVSkibp2ZzBHApj3TyyQWeR0T
soE6qVGrU0cCA6w+mgSp/LpLjFALA+nFAG3lXPvfyzy3nWkgcWbCXiItZJY+SdblaE3tEF0j7zRy
QEv4a8Rg+L6tHbS4IhpoHW2u/3VbDszbEYb4sRKfYUA0hAwJaM8jOAxyu4YRtJsjn94Jek1Taiie
hp0Ndlnhy5vlx4q5I6i8Nc99UyR9uhRu8iqRtT7nCYuJSAzDby3Uxqh6srwmKPrb31KF5pRhTgEE
hoDR5pRAhvr+p6GEHRm1IAJTB/vA3Cmck+beIM8DaYRIdaZnzC9N04oH+sWVHExAUc9WW2ZHotPC
yowKFvokfu+7look6EHxqKtkI6qUIsFrQgy755fSnh7+GR8EVZFKqkRCDv0zQz3m3MIaUQ9GzxNA
nVZg02l+SgGZHXvy8wOZE4ONpWcUccgX9k8Mqf2VrJEhn7FTdwr/L68VLWlWyJ51gTID4qsEbmQR
eUcVhXwZ8J6/Jr+tfQkihSE/r9/FrMS9DtCeXZFSTXFkRXX3jwy08FYzVkX1AU3nfi5uob/pWe44
jJ4c+H4TgTK/YFd0U9+b9+hcQ/PKCmyuUWlZMD2jh2m6YaM0tRHT7pTE3k+5NorK0KIzBPhuhR0P
kwadh+BfDa9Ed/g8FI4r9aO+bzUYkbubz1m2BkiyrHNUN4b/jhDQyeuJYsvVZmik7vXZ6GcS1rnC
ZJpUE1bWR8FcYhqQoncmXGI126qn791BoIP3g9UyBSGDJ/hK/eFW6lylhaaJjjVsKepmxGzcVN1B
mCwVpKVdTSGBmK72htH5om7KKA2S1rC5U1UUj3MbiW7ZNwfDd0USkl8imBDLwgYFtoEE1ko8C7Jc
eUprl5A05bpIwcNw4M1zuvcSJzD1rtWdZQl2vo3uekE+ox++ptfYE1O4Xj/2TqSRnKWmvElAWcGk
d1P93oZ45PNjviXZ8GjPM3O0qWdvlgjvAq0xdzA6x0TysB9PpseLW+g8nB6svNvi0GhK/LLkeLYg
V+VOQradYifDOr8PNb0cqid1ncvsR8+c0tlZfcJr23pLfcE3Vqz5wPmHYoK484/vAUmQUEHiXjLv
MiKyjk8ywnYHQ/TOYWuO5OiF3b4XtDucLmEyRzxNB7rY1i7qaj6wGs15PP5RLOMaDOI9Kg6163IT
YHmjt12E1isvBtgqS4df/zN19hcUsAr+Hd+fpoCiaRD8qfZT7eD2F7aDUpS5tVOH7gVSyJWqzQ5q
Obv9Yhw7rja/O45RtfCLUeQNveIdOxbYJdxtkbtNUL4THMOaUooUKNDHf2XRJ/IU29P3yYsch8DL
w6GDueFKcmhtTaLLsoIw5tztfz1OnR/Ji8//265ufazAczEkWZEuwDJ820UjB8sYf6rqgnsGaFMq
k4/RqF2vivZ5ejxFZq4j5HxYIkrT0dvfR14iHiz1gFBjRkaPy0KB92AudlRi5GguJSj9i9apnV0C
9Q8mNjw2IhqKOYuyV9e6QbBpKJ96If+glayPM19wkoNu3wYrQpc35Fto6fYKFdY6dhE8nKPhcitV
/uItKlA/SbBd82Zd2+R5YPNcmQq0sWFXHgntGjncAGogKw7gdfoVMOM8623k3ZSxgx+hl1hERb55
2VAlad1Z2TVWotbB4SU6fYbYbkgvMzH5sJuCqbAAKfcoPFz1nWbbyWa08tpLEd7dFgSfxRMD6emG
vbRwvFQQjTUHayp8X4YhTp75/cn7s7BNav/nMANVwbzv+7PlcCBDE/FAkBmre/mWCARVoeNQi9yk
Lmy+/QFbBCSDmgH9dT+J0qyptUReayys26DpOx3zpnRbUVqoevpDLpdsoEIttEWQIhHlgFCwxqwE
aRk/jq630RhYJrspYYhMKJx7vBModJIEGer5px3GFiyOMr4+4I2Loz4N0yOCB4NxzVtMSM+DMFzb
Yqmp3TY7W03MSy4BUlptWvy4cfrCDCrea8duJ43frMTKFTfbW+IerIgRfu6o1EW2xXm1cTpBK1C5
GDw5N3ENOo9k6+Og7Rv6BqrZrvmt4KofAZpoRQwtrvIUEswUfZzexMH0dWDua0IDEUztjkju9U3k
MYVajimuyW6IXCYU0qQCvsz9sBM2LLZ1x1Vup7fB1Ec5aPwU/UHatOkTm3aX0ZLYdmaCrVM88w9G
XHeo1x2sSQwb3bclHeYGqJ5KFtGY8NkrjA2kOqD+X2jo651hd0o8X/ii6dRA1MaQa3XRL48KOtEM
HH0PUmnhNz19o5YiXS60R4NMyF8DBJ2arUQqgtrBdHpYd+zsNwOO4FJe/HVkB0g9fp75mEMH5PiJ
iCp8PJo1jsqW1yWtRGUFGwq3z88uUmySC3W8F4jZcCA/IVM3H1z/nL/Xi6GkPU3ho614p2M5bRq2
14TEYUDIUMMz5OS3VFeKp3NLgKmCpVj7tbmiZi9T8Yde5BbWfETD2YjKPY4NPYiw4TNz+908oHc2
yTbewFueWvL/NaEUrh1xMwQw0DRkd8xsxovrukJPMeMMIOpJVuHAqxeQFIhjwyO05shLRO+8ICOY
lVC8RDu4KIeHaBIdj78ETsgHAau5157cMpNdCv1z6u/eAEhsPNaTpoYf5z4Ulz5+vbrw+Ig6ywPW
AC3chkAwdqF9uooKaqUaS0uaMYKHDaK2y5UfVCBUcfko4mCk+jjZbqPR4oE/RY4mRKF+S5KVRb51
goeafsPpARmOwOZcbpLNMXGonqOUJEFV7nFBn0sn+mMycGAzE+JXd2B03sI8g6vqICD4805s8/Q7
Q9RvYQCBXt2A6pU5gu9eZBujlJ5yteDEmqSPNTNLHzUtnYMoAcOjjRN+mnEfti3CP2YaqZYc7AEK
EmGhccCK28g3Iq3fyEIwqSG5ZMQqTqoqd2RXD5hdEa8/QoSw8h+tBDysQ5iCskiecYnVoVm2sJ9g
EiFptSQHJIy0hyW5bqu4IBzo173gYuxltoA/x0vJsCyFYs77QhbyJAFsJLmGHqO3cT9lndY5RmIe
G2IsYZVzwYIn/hCH0vy7GSobNYDvEMIvGBaU5p1UTsf1zLoaBwNW5il64Rmt8mWVqr6Q4Cv07zk7
YKXZHTXhEeAgsPcWekKsDPhosTQ1OG/Lbmqe6Xtt932gr1mKpZC9HDG0zXIrXY+2oSE8WilO1BRy
J88nrrr7Yu0oYnF4wZWHuAWIyjgLKyWWX4IP/WRaze8T+DWjRzYC+x719Lw3Own8W4ws2iTfKhys
/AoSQctmniBEUleebvUzkP/54oUfgrmlSFnT+LQI1wpo2T+VfQtutqXZD+Q9onWKVVV4HeEbkZlD
NiZEFqgI7BCHMNKvyQsr+gN3d1+ljxpDWwjLTifh1kNDK1FTX628L7Esv/ze15vf2ojo/9c1/gl/
t1SV+B85OJEVM2ghrmoVc/L4ECZPJK0ZQo5F/4K6TFqIGKCvu6JvWCTXCXXQuvIJWVCf3yQ+xB28
CnIRjnpjYhPYNojhQfb5Zv+GZ7LFqZZ1/o78veE9yuWl0lUlNLkf7AciAMp2qc67QqLSzbmp+IIZ
GRPGcMLDzgqZMu5UoNLRtDcIK4IdO68RfVU+DfGj7azU8UasdLC7EXFxENSmQ/djh/0I4Ci41R+q
wsa+kmx3eYs+rFXPF/gpMof9+m7gcNIlaKRiKrmGwaefZwbiLS2b5ZrIZ6dIXfBst6s3VP1CYaaa
+z49NTCU0GqV80EBrXnRQ63CMSRECEHoQlN/WGzyaldjxjHPYO9Hmx4A4l37hy0X4CBEgwcgcLmn
2IaYATXcAYJj2x+86KLB5ybH7SyK4Ew14BYjahhIhbE/HpiaKw6srEVCnQJsybU/L8kpmLrJFJJB
A7L0H6rsyqypQ0Gw1vYRNT/Iq1SfeeCbJucKyPaC8FIIMxhLscoBs871BAGV6PnoCQwWlPdh7wt/
cV+rFe76p7fOp7y/iWBGEIZ3hi+nWA/1wg/Gwy2n5z+TL5zSsOLvSN/UaFnaFFlJfzsshhbbzRjm
u8HmR4iISYlZfg+PuCGg4qWDzTm+W3rHe0IKKFdTl4GXGM1/EpTtOAqbIDIWKEIZkJ5l8b15nkSy
kXA7m+xG+B2kCr6obeLcnH/Kll+3TvkRO20Bb17nVNUb9o9OAtuAZf0dsN0dkMWVbDBmARX5RrB8
Xaso0jhmy2GD0839FOGPRmjq0itlZIHy9gyGxFuelbdXGBP7YJlreCebt5nS69xLW/ntBMeaobHB
+fuRF9ZeLz6NIAjircenBW7v07uWGziq8CV4rmH/bVbBQVpgNLXkN8+irSvzIih6+uQU+4qnhkGf
6DPM1CIN42m9ynyzhboG0MwLmsmxfHNu6W7pdDbuQK0nD+bziOLzzqrXLBnyPXGnwpO2QuvUEpHz
JbvGAC0fH3+ZHVgO2K75xWmD0ckLOS8k2Z5yXiDsc+mex5g46t0h1hrH4Yyvs+xHhn22sZ5vmAd9
z+TAxX31wRoiRQvb/b9h8k+DfNRbYFTRb2ARM5f0wglZ2CBCHU3UDca46UnCcX0s2i8dCJiik+U8
1YIMvzM1YeyL3p4mMj0N+JIFkUtiWw2Iimbj4Zp6ofh5N27FA2Lw2SNpuIQppGII0um+Cd8fl8LJ
wmvWzSxiUir0Ax11Yq2EPE4jm3nKtv2sY0E6lx8WJYJydjXzqOwe7I/q8cblI4Vw7LJj+vuX/Vac
5mEUxAfQSPmHwmPnz7dWxElLo7zN511DK5ZEC8GBtiK9/m3RoIfI1+3Csl/GLaL5uWLV5jg3nmav
Y0x1hldBRI4gGM/8vCOKB1q8BY8TbeB6wETtrgJDpKK2w6lzrgVWA5wHTPjCuFeJZQKurXZeL80g
JJpIX8UxxYd+U6Gg7ji8gqW9cjciYoznCFRSJAcwiV6/RLQ7TMkMWTU2UPbgRRUhP5AJaTlsHLBG
kDpRv5sUys85ONbc5+pksLhtG+6Vd/mWvnomEBms1/e+jX8+Af6n98WPo67PSdCntlBBB0GpSw77
A58uptTtJh3ZnWGQRMSuQLMvad/WJZKosSXA1e4gAi8brVgIYmbIc2kzpFVAw8CT8ZJVQt0dh7lh
8tVc9ifnMjHMk7eBB/kSfTmYqiH66g/FPPIMThz2zJc8uB+JcA65L3cTruK5TAIZfFjQsRhDD+jo
+IQSPEMe5sSQGn6lLvuEYseLQbSEswNwE1xM0mWOmQTgipmdzDR1ApQU7CJ3glXHI7CVSZ+Ptc0x
tMhQKU+3nMUBMdbrbWczDZr8+LtuVq79gy6RjWSEvDiU8k/C2jfU7gvAAhYeQmEWA2ZDfrBZGMUe
ctwS4RKrBsgrdotouRos6i7rnUYet3BfSROrkb0kSdMZRGxAyAEEU/HXaAAC8PBph61GdBPOjY2o
ucgy4/5j59ePvr2AHV13YPvzcUThetgzbOE/iQtfdAyChyoVx/t7MUXlzDXK9YyFeO5akcWlv5cV
/tZmdn+0Ip2LqVVRXFEBSoKdQdXJdPtlxjfAelCI04ov4YoJ58o+t0nhwgO7bkbIx87oHNgrzQ2M
F9Nx7WUW7kGIwr83dm82aDD3MxmSYxoppKine4XFBSQuB5OgrdtAHhsoSTFIgdLrqVtjPempXbGk
sAGCyeTTFU5G+XjRzr/5F6bDtFizNprxJBKDaht1ZHz7ETvgFDqUE1wXMVV/4EQdWo3mWO3IzFHy
MHtIRlXUch3GQNXGHB3VG9FfABO63ISUv+i8letcphRuJGaIqd6D140yb1j9b65V/pllsmcXjxZI
Ah43oD+OViZ853FMzqnn1m6QUPSsMZIRyqrAz1NPtluN+CJrw1FCZVpiTakwpdxU24wYPLdzkJVt
MpfNjTp4CfPgAm7JSZ8uNwQriV6W+lMhO/nOlWDmWdpkvsTuaEmfMCDUgnSLOZS+lGvmuwQqc4c7
zpaP6+TmfafMbg199BGBGKHnAzZYORNMzqGduqQH2rfIjXYsYhgEvrviZ02MrjLaQZP6+Ut5Alf8
E/kL+HVFFRph1szoSkmJ7EBXybrGUR5qMCQirKzjN+9O+mZGlpjLRjEm9OvwEI2YBAdnbEy2PUIS
EppQU9iHilUApIhfes6nYf+wBw90smvQ+ggytyPZpyUuHI4qtFg7oOfeQJsHmMUTERb3j27kJedP
2tYr9qiiRWvUkdwJ4KJwqWf4pQgGognpwYEamf+1nPv2wTMMQK8Xx/yjdn10Y0/KWTAYXLQMmYjz
1frZ7sNr9m2G1bncTeAGzAAYatbj5nvolqrKxgG3z0xhGVUVc40Ki2Nepm+7jD8G0IY0ml5LLddn
YbZpN/8M3Qhx3Xq5oGiH/2TnC8sMX0iYn2UCyLxrWczitSRdquyZOivyQrbiaox+Q14RjH2RZNd5
aQF0j+++AlFnkxA005oCTlPjkpfMTIc4RxeeLQJ/tOK503oFkgsrCogo+yF12lnKy6igucSzbMPn
3Wor45sypUNSbvvkuBCYT1dqOqZXmmu2OwrJxxib2arzDMD+Od3/2YCFIL50cnXvoIjhEB0DXR9K
/K7a88aV7qbJ4DHBzJ3f0XIdiFQ8SQgz7J1rbVBgheu6FymoZephdjJLqZb90iDDQWVJmojtbzXg
gFOUIz5M7rwsn1szvg6OQvvyk2BO7F4pzU/gosxylIy+ZgksSmVFg/qaV20rZ1k+aSKwrFaoQyeZ
RFL+1rHpj+IbGKJ0T6azxeZPrSBdULXO4GIJdvr3Qb7m1uZp95FUpJBDu9qVsBeW+e88fCT6V8gX
VS6NTuR49358rzHdu4P84iHiJvQ86U9hTj3lb3jjwQAZN8p0kHLIhJ/OK3HNXw+RTjLj3vFhUR/i
IRh025GWPgCvLKW/Fcjs6l17Yf4iBubssKiYf8wlCs3fcp9iubVKMP7pRHwefSdGrCymu6kYmLgw
mqeCa1xHRtdyJWo9Qe40/RZF/z5wrG4kAL6/QY4JsNK5IuaqdL11AZL2SCSWi+If9d6xMChOcgdO
Kz8rL/ul1zVN4v9usZdnQoWuT37LkO/XTV67Fotcg6wt/2SklpnESLjZ8scuc4uMPNBaKqJxjusu
l1vSBAc0RfX+94qdKAB1kZkl5L/0wR4MeVpy7u7MCHssLTOzpzCO9upNisBXiFFPDC00CfVouYZN
XXF0RkU9ILKEeChv27SW6Gi7Qy+jku7OC4OkwVTtOeSe3uN21fa0MxUAVDqDcSYih33eUdQ2UgQt
L6AkF4QraqjCQmkNLaNY6/FADaaIph2sC0y2v4R6EliBhBDUC/ueMaaLEicWDYdky6CenbfyuZOC
Uvu3Y/IwIV5G1ioj22TVv+/LM2NMXlM3efeBXVFLlpk0glMoySXNMXgPIwpcUbWKr9MvEuUqvHfU
Ua+EPFCKPWY+MPtNhxODgEaf5SD42ilmAXixVxbfQgZT8KDy5ESHSevUnG4beDCiUOx2OxSZYEd2
WecJ3ZL6564z/G4fc7Om0ZIOU9ng5EgK5ufct/8wDhJxhrKfWKF8oGMAz/NIeDg+KDpnnOd9TWC8
m1C/nAlPRFVJESuKzp85N/iFta4ERlbMXC3KbBhJx19efD9AzC6BaiST96FqCaEQ0gbAZg+5M0vd
sd4uARkYKVZ+saEmK10NttpOf8+fMTy+o11z0fGYxK7evc99er/Gbpf39qG9yEfmAEVRfphmZPIn
SQf7u15eABhrE65ulYC9cW/1kD9cckhW3Ca6Fmggjt0dr5f0xyY9FGPQPcKlXF41lN5BHyQxsQIA
iGo9RSECpzORa/a8M6ZNFsEFb1RNk7PIJWUUTwA3yGJ86kp56QxDSwHJ3pphqBtvncSbkJA4qxYe
VYFrqoPM2y9CnuLtBx77VYq0P4lNlDZj2jk3mHJrjUoyGQJcNWMrbXeusyvrDBumKKKJuoCp8Ji0
/RMJ+8HFg8+R4uKqYvpIJg8NyYQ8vYA5vtYccRW0jvZP/i0U6PWDFr9Jttd7mvkTVOZWVQzQwIa1
CX0sZXUqWjeUdWRk0PgpbprIfHUzRGF/71Zzu1yRW2GCnx767EQ5qKMpDIk0GPjYaqO4xoSoi9aM
1yz/MP17scsZFRtDTEX3mlGXuzvOXzoZuF1pv+cx/HZyvxTWVigsZvXDBZjLh/wgy0creA+fBV1k
8fkV6zAuCk5dk5WqKFfYd+1UeCPMcZKIBp4CT4CSOy97C7PdZOfTtjBE2N1HOoaQ2ZxOQQfwlT7T
fBNkY0FZvjuckL0I+G/gCuS39PwVULFYbFIzpXBM1Nbej2d5BRC9Qd2AZu9sxMPtcZKUu95Tnwhz
RLTAtWmI3jpVmutYnGnpM5mKwhhOdMO3VOC5v3YpF592DzT+6/6Acs5ks+nnzpA1Us36PVKcWGkE
M1WjUqhQAuy5AFtL3rF2Roudc62UHxBXUcrRUznmTU0m6HWy5ij6umKW8aSGQEAuTFkgHG+/QK3t
lkny9IyYFmqLI8pYvOJTBRa/mUHj/dj/6NbKzslOo2YhiygO1nVPUAcgCQY4cgBaV1HZAFPnSrue
xDDcyoDCQ9XAq7HtK2PK5zi3RkeZ2APBYNWexQi62G+cTV00wfk/mJEXllv7M1McZl6EYNB7w7Wy
NSFsKlLu8YEu9N+Kz6RKVjxTNxRK8PL4e5PF+lnFbOzA7pjA2WZ8s4rN/GBsDQxj+iRTW9eFFwkI
55pwh0HyA5SIW3FjpJUf7cIrlGZ4oEXT7+1t1T2BK+cZECsvU3yQPWI0wujjI3BHqX2Avcr6Gfjj
Zt/BOCeLm3WPYbVnr5JtETvK2x7GxSyH+9LMO852zV25Cd+48P/c6S2Kw0ca728Ny1Y6KGbL3qlP
4EvN/TZ7etw5UKea706IUXwIQVwpP5jQ938y0oHDYwffAWQlBszHIVreDFPDhRH7grduFfXwkAZq
Xg1+sBIztw+hxqlMs53QCz42G+g9RWycycylepEsvcSk9fVNm6VmgeZfgi6X66giRnNJpU2PIBAF
TmbPAcrMrGqiw6Igp/NT9dLv+HdaubjRbMktYivcwKhtfvRJxOMuhYot4wWlUUavaDQbJmW24VmJ
ZwCVPPi6rQ4Nhst/OnX8HNiq2U/gTHWXorogGqfyr8Y6nwQ1i/rMdmxoA7b/GE1m9P5/B6xamFQg
EwXo+CxJrOCPsGlEdrtI/EomayDvxVj5CfvkkF3AfbS1sQsfyGGG1tUvsuzyG6HbCWTS0DgHLYKw
mLw/kac2HudY+pRGugwjN7CsZhMmmjhzcrMq0IOLuASVzEQ07NRtu7qYo3gXq8qnNgGi3DQKDYrw
SYfT6Pwt/XDOLV/1Nwm7lrkBfprfCHgW0qbPVabJczWZCD+LcxtBQw3gU2094NvU7pb7yPhlgrq0
cS5wrnWHRgkSVTP2nTdECUOf2uvdv6UAYuKZB+WHxfuNgMuJy+NNx5KfDuofgKn+lYGw6REYH3Ka
ZOfYztF8bAdIPEvwSawpzhGQAiNBWeC79fEj8BBPy695w6r/wK/tqaFZeWkyTtf0I3GsKFAFjoZf
KzKY+NxdAAJi0qPk4lVk75CJ8kptfpPfFywJQmfyBb975TcM5vpsuS0OLQ7PPrjlQ3gHCKvA+H4n
QPQpKtQRoRv3axSt2d5bX+nHX7sDe0XLK+YohWnf6W2r8ED9onbhdOXu/KX2OHKoCbv/dCpO3JIs
yPgJIlcsES6Z7VNPf7AG2iCOhM8IJc2rkfWNF05kCosrhh9zj72ovE8RIohjbE6NHLiuUlA8oede
e6MJsIbj7L6BcoK50YtZJ47mkqQ53XN8aAc4J/rI7owAq6S9g50tYefm3L0nPbuCGWHERzd2gjBj
eixz+xrcNM7tnJIQKf3BHG5GEXQzMr8loXRSFArDmZxS3+X0oRJlIt5ZBx6wPaJLw/47C403FaVO
IQ7rKIj1J78aFfPu3+RUWyAxXdSUla9IOrNugivXxl+/pixnEdfqFhdGh7sINrMDr3Gva7MydLld
aT6Xxy2ZXoCIrn3QUJYKAx8iSWuYEwP4DqSnDEcIzqyptarJmsEalMCp9GrYMqhCwNqKhm7QFRVH
EJZYkgW+8UMhys0ogbrtFGbOrQzAPtBJbeUFIniW3mJQMXc79i1yiE21ixQ8ixak+mrYSNslA3e6
hUZFTZJoh5xpuHQYY1nBk5twjasanafpLNUSwBeNbZ44LL0/WMXxVmEI+OffB5P3t3OhAtcLuUmq
dmfqUu5wfet7GcTzjZMame10OMV+omk6zhW4JKpGLlaOc5wx6/zoGhGWuaT+cWFv7j06y/IK1Ge5
VwYmkjNekZd73ikRPgWbiiTGW9uE4WwlB6bawr+FtFUk26pt7kv3iGZfcaexkYk3gFuoCjMatcxm
5iJBYNcSz8AWR2X2L+XKSxtSf0hQgxgqoTL2UfsFHmKChrS4gCUThdVlzTQXUx4eyHaIJJH9DnFE
M5L/7tl89MeROUUOeAtes3QIlHeFFHBL/Ji3cfap8ryGMN1/gtgWdRFkXnoX+G6hQhXwma8qXikA
LWFDlKPRFEnz45o+6OCrGzLwe/otDBFLGfQ+GWVpN0kV/uZQ75Sf0e/PsUXpFnaLewiSKank6gwi
8yF+WH1FQE9YQ18xUl4fwH8mizCAxcpFYsA0t+RbSUT3n/4OMU5Qp9o7PN7lBGRIO5p6cMtXRnXC
JfW5MAwmEbuYLebmtXFTuJDEJn0GyquYWPiwpRZnv1ziMZpHifvHl8+OztIxJd2mYoB0qILovXrv
p+sSoT6d+Qt2nOaFyPi/m6CB3U6EZTDb/lY9CEtizEw/HAA/6VwkE8uIX7K7vI/hr2H0tduoiiNC
Z7Qlv61NGDw+Zsk5lf/EB3d4KiMTGGR+U3OwHtOnm6VYC8rcu1iaHeniGKq68Pd4RNabdW0SEWBG
SCsEB5twlwDDXXKD7ZjGPdrzFL4xeUQOh7FvLbwmC9sr/yhddMvrFkA2V9wW905QTisuA8OW3JSB
AUh4iRU5p3eIXnK4bV5DGLg5qrBMXKp7ITgTUsrz1GkN0djgyFC0XYoOcjI7B/yHlOip+3I0y4mv
lvXPbxrefN6gyKaXEaeKqc8lkTrapgWmcul9IqE2dc62oipP4yfF9dyU9mxlW10geK1g24KEyzGo
BeRphtKG4Qmo+nfR7liloRHvowONq++DWCDl7U64lFtPGM8DVJ8L3f2O4dZ63W280QNqOHfM+D3v
oYV1BCKRuIDzGPh+aSQpVALS7SpCpa9vz5n7NadTJvhdFlHr4KfuJX3Dh2oImi+n71N0Qn84euc1
fOD4vRyV2dyrbvpf8ZyzqYuhxBpx4gleNeoUIVPfagb2FoQQ+bskrJ9Fzaop3uYeyYjVHHz9Hn/v
kD96iS4c3YZAm2tkHGVHg07+rB7CjCZASOlDUuBZBYy/Vf49Oo6ZIbyPX6zKW1HIZX6TCXgL2RMD
Z18i6bS4dVWdamjHoVM2FEWy0zWmP48ZzqIofGQ35eZ/S/W7DX9ElshVXWSoz2DnttgcYeQP85Uy
g9m+ziCUZIcadRW964AoRUA3+eqQFMd4s3bDuqBW3XcuFpHSRPXh6t0Fs16Zxakn48FFt53gPuPn
kWccmrUbXLvLcqhA8NtpSsiryUclKgessi+7wqGZwaOZ/56iVBpZqOJwABqb37gDS4naRX5Lhm3s
m3HaTaYcXMsCHqn0auTQIir/uX4q5UPZFQ8Bz8UC3UKxfj5ULvWsnpZTirNjNzizmAgQT8RVbgzU
2G5ppcdSvbuZsNpQGRd4Pb6lyI9TgsK+1nbLlHGhemrdiL/34MiuObwmSLc73QRRBxNgFET6e1Lv
o6xWN/l6TErNc+6EiEwrxgHsEDYFHeG6qnW1ueS9Lpmo4/z7e+6wy6Tl/b5WouFHRr5e9BLEbuxz
42BX4dBB1w/PfHqyvQ9VWKQ2jLS19zH4agGu55yMenuP9MgLtErIMJT+Bl4ELPGwB6MlUUqTZB3t
VQC2OppjbtSjETZroDDv09xkwKjiHqEFViOwEy3sF9EdAetnX005D6kuc/K3fTbQi+m6fMRiKN2Z
BiUYhf8XENvED3ZMQxboABD11DmJ1e9Fs74DiyxWCij5drQwOkqqstt1vqKAB5y7Yfz7BEDaiFt4
N/hwftM3GyDIag16EDHX9KUEehn7+WAQVjm8M9q3X05bEsi+YJzDYvQ1YUMmCywjgkrU+we6Zlfj
jwHfaDlARpdR7SkNfEHejmsi+v6oKmporsGFi/PV6Zto0tsGqVmsM4rG7ACZ9Rr67LZv2ZBYmau9
YMgEVa7MgE7o+XRH98+6g76U+vPo8sDSXBzjLxrUWj7LbaLAwHwCiaHAk2NE6S11a38XlxU9q4Rc
V/ZeXX8H7FNqwpWafLtSUSFGjVEl2UPuR+LqiFTtg5pDbXTI3RUZ/1FTQXdKgs8mgkiZobQpzFE/
rrjhpfu5U2VFgUt175KUgZwXZkH/mSNkaexiOIwbfcsZBAy/tKw0ZMHpRgmxVxs6aDNEnWMppYML
mirp99KtxeiB4YkVvhoCIgRH9rd9f8SjF4hpmqeG33F+I/8aGa/B9TDn9mIOB0MkA9G27OhNWHti
BhiDpachcuiKHNRXtROW2tZ6QSKltulLhEE2tKS5ySwwxUggM23fjcafEriJsOg/75JPoP0f7KSD
GKya9azUZuLQNLPDToOlCvYyOgxC7DwAJSzAineFxmxudrjNaala4ME5f7ber08k0H7a98KpnWhr
7Wj2/ZJ+vEdRg5LF5JobYzKvmpaM7hGgOO0Y0TDtIOO7HUt3HbEwZQnXW67gaNwbS1SMvRGswaYx
K6wkNU8q8NKtgBuc+BLolYfLBZRJcyR4yNDpU2ZjHuWIT4ts/OFFXInD84SDkSXjHApALHfZxsnt
cTfPbSH8fDmCJm8Vuoqw1xgU6RGcrAVPTlI/Bq6t7tCPO+YaS7Zc7owdZvEsNMbqoZsmDCFe8doV
8cVthfoNVR0f3SFwHIhWyLqcudCO3w5Kbmclzjof/qugz7XI3W4up1D76MJKqi3dcnruoFlabFxm
tSwx3GSlL+5B2O2YixhTq2xSfw1sszftRCihJ0NMSoRqkcjUCZWV/isTBo0MmbQfNmdasTOjZ7ew
2BGPXSHQT6V3s6XY14QEqIGMHPF5erZNNQZhY8yMaHagYfd2U+nuwBd7aS4EyGQFpNTw3QcKE37V
hGX17EZiG8Wq6MY/44BXOfTCtCeKo/byhuif/pVMsu+ca4R5zGuY3CiVWYEsPvzxF/qKifpxZi51
XRmtFk0dvxCb9LZijwdOxnyH8ZiWDHs7mJnDVpcWUMPZU8IvqumksK95mbWFPl5LqmMFM0jEs8PD
mTfV2GTjPFDNIyUlS5wgr5mAkFV9aGhFTJyxgym8HJTFTPnH5yHrrcc8JJLtN4hU1di3Xn1fE3uT
opoRvS0bdUapON9OlwVhd26jM7wCZBYB6trMJ8Mp76myBkkv39NINwvcNz0C9PjTC2KxxPuukWtR
w/yhSCjv3HZENtmeUszZgrIUGEER9oAiD+owYoWYlewK0ILXabNAqrhmEBqBHrr9oqgbcYRDzuYy
tXp0TFqhsCtk673OJdQGB6Oio70EYcvfK2+/+lQbm8RY3MMrGTIdFT56B/KY7jNhS0GK2TQxwqhs
TRZFKV/ZJk4siqHTytH15d/JDe5gR0ZT6YLiWctRZ0o7rDFAuWGOts2T5plZkYkKlicuij/brRUE
VoPwjXc21Asul2nGZ4oqWITvNNvqsSj3pZcib/NkEb/ywxjqeutPrWHdY2z9bYYV0afl6iN+OJPF
mRYM7kLjlkifzhHkjMHeNI/3PFm0mygSZsjtHDrFRcYjNY27pFqwHt2ydv+Y8I0N1SDHvn9BLNJu
oFVKeuo90KYeeut8r9DrRTYqFOonG2OEQDDLAFRufZ3qQCoZzCVAz2808ZTxpmyZlUrqqRB5eNoR
fjg1JW2zKpsRpYXTmNQeMRdldk+Feri5oq9cGD5YRVbI8qXrgCFVgnHaSb6bgNKjoxu7ljGDhDlA
fyljqWnwjpwLnJrnLEEPxCA0T5/et2QButOgW3nnwmS1l46RTyIuJvDC37QKPJAoZiXW3NONxQ4S
VMkIxUni4WFNp61+I8ALmhKWYBMnSF2olRUJgjx/5EoFbnaRnuG71h4SLeOPIDGWQZc0jBwrQoy/
p39/L/g1wLZ3FqNDV7qggQZ0GMY0PqS78funhvJ8e59DeuguR3c8Qw2C0tcThu571K4wpX/OFbnY
beeizjT0zdkHhRSex+8gBUGhTbaSXFA+qwXR9xCY+C7zYRTKO8Nx+cPPqtw9pP9PxBswmjqhEKt6
3Ck/ADyCLZdGREp/A68XVGVvHb/JvfOg35vhDTnY5YS2yaSxtOlTrfweIjcpHNm/KYIfyfc8tE37
vQgFgsHKTN1WfK5wTNKf7aRiY0HC8102JHI+A45viX2RWjDbdLJq2Y7F5ppx0BUGXajkekHFHtTP
zGH4mWnc+ZM9cxpDbZHg9CWY03g1SIePCaPv+IQWravG0Y5/FjoT60o3H5FyFBudgMVZ3cp8VzJe
LvD1NXLx34aC55OogymYf2wimfHqDswutWmnj+tuNMEDOInqQNq9UcHM/OyxxtX8wTTT/NRUFeVm
VeKtfofxOPU4GgEr7q/dgpmmyUwpJdTmUIWgEo/EFBgHOpfX6wnVmKNZLK/35u6h5zONTzL/dQna
H6zFQ6I+cQKT5ug+al7l3k03OO7iBB2zXBSdPjOWpTtDodnsbHMw86WcpUsjoqFkiDJh0K9pAiTs
yu0YtLXYhpLRc8vLx+nlNPLnBlewheD6Rsel2vUITR+Y0R+LTIVcFizL3RkCWpgT8Mv7GFBus0bs
tXa7x74NoVvDOv16dK5Bp6co4kem5MjsBMqulNnb5qAiSRSAHjJVEcbgiN/ejphUzKhhnQ2rLlmR
J0srKz5SDkt9GoLIIQYs5LiQz7IybWCgpgj6AsAgzJv8o1wGzGOJFcuutKhU3byY8gX4mvT1mcoL
+oV0fltqMUZ5+7fYGYXRzx+IoKYTulFlekV7KaIy6pn9anlT85vVRhfq3tNZZRGuUALVSiHKp1Bv
hSH5jlo6taMLCDODPF39Tqvftq6OemOjXklUiPQyYpE3hA7qrG4TTmxYZzDSMPUrCpTcgg6vjYA+
icfYFMU1pgr4fLmYJ0fROfPHuGJh8j+aeRnjdDL1S9T5mRS4VQFv2nBpMet9lpa4++KbevKGFfwJ
BO0QF4h8xYmLMoxmJE4LfilYtw9dGxV5baelDnfq58HheZD2ds1QdE7sNtEpXV6y/daqe+F0IrwO
EggItvtulBViDAFHzzEs4Ors+9e3U7TiRkh+FQouUA4zwFshY6xGA6Dbnol3ZBzdaBUiUM72DESu
4f8i55WEiA1ksZPV3YoWd/4fFxoy40yp+YAThVsC3PUgYwIJd+HeGGy4QmzfwbeK+mDAR9fhkgPx
nzDL3LV2Gv3HmCCLPBRF3HWk89YHpBOvD6r+uOVfqkM48561HfV7l3A6apzVHxEOEh1IyTyiN4f6
3KVzCDqCvavPKeaSnkFs20XLbL+sYELy1lix4/B4BOvvSBa6muSI5EwkO9IYHRp4SldDU/BoT6Cf
qRS1nv1bScZ42MttKPlYo5C+D45g6wpNReoA61TtaIEPBZNYtLw4TsZyYTF8v5ZzdClRynhRzcCS
TDxMcqXxYDSNoJqUrB7zcYe4AU3uO+Tj6wXoA39LLbsKtK1EY16dK5eicLPwSoFRhW+yHzcF2R0r
WPJGyuHI7ddZdu81doAYgdtje29f2PoQ7UdSTUx5TaBtDIJ3Rj9hzUirGokvUqbl7/aQny41+3XL
F7yI+f+1hfB0KztcysNAoH/Ef6mEeMnfNIZ1MWfgKXi2mHySkygQ6NWZ6vvA1E4qyMJXH6Ff48/K
gOLCxf9q2hiWqZQnp6Xn75CfUcw3BVuhzDPyLdr0RuUnInmBo6zzYXmuhUgWD3UZOwbOLMbQde1E
4+ppigWbA6D8yjjDH5d///Ez3Ge5UANdGKtn5+zwt6sVz/UnNbLaIxHavGC/XYYHjVzK8UBa1goj
rRjxZYq+/vP9jTUVM/We05Tuu6Vhr8Xqgqbs4LxdLvSY5ZRtfkiZ4ZCcUX6PAd4EH3/mr2iiXXwk
MaHxtETB5c92jL0MYVhAngHcoQp4PXcVgMM53uyhUPz7f2ILQV2YDlsJucEYfDq13cpM0FlEQd0h
5mhrSC7d1cT9pzwN/S9h7Qh/HzA8ELwUmuPuJDo2/TpqVz3rFrdQd6zrjucPEC8bNXyMJ4KKbI8D
jSOb8qPFWrNmF54vmxSvOh/OuuWoD9f3nVoFgkV+u9aHOriGCvKVf9fo+9RKQjPtDXcFXUfhU3Cv
MzmWBqGndqHMPSFCJwZft7uzO4LOPPH0VfFoxWhRynQwCPBocMx6x0YUJV+M3EFU6Vu7E3kJrFsl
y1fn4yO53dC25b8g4zcCCiBPZyfjr/dEPpI56AfsYVso/JiXvsCGk4Q44hgxk7E2o05UqQCMycBS
ygQjxTdflOik9YO+XOKbMzwwOKB9IrJf7iEl2lQF2K+TkGRUH4+zgS1JhcVqHPMQR+DJxVpWfM0M
H47wPKt6giCxmkkimy+FeHTdZ6hz+24lzsFu3UbXHAwWbAtim+kz7tWoUwDCuWtRez90LMVibV03
s9OTE0S01WDnqkPCfv23N97xtDZeKpUclYjzfg8WN4IphB+xKA760It6EE+vAg6sslhPeEtILCY4
Uo32QdRhD4sEjjub54P8JzSNxRxNbgJXU+8ynehszPSEyuxl5dDi1AscV5lkhXQ99VE3kbMI8ilh
QVUy1qYXE9K5fiRAV0MgOjL6GGRYoTf4n43A3FTs90xm2IHT/tG6dfy45aY7VCkDyOLAsNg6qbjb
S+am1g2mbZSI1nM9RhmFc/sBTe78Kgm7HWfCi6EV9WsWjqKGa5AaRsASsm7bd1npnUKXCxM53zTI
77Gkmb968Gfj1eaXjJQdf892eoN9RwJPsCC18O81xXkHoHW9rpUzV/NkTfGJToNKY6n8O/U/gp3y
AG4NmQb+ohRjIbQrMorHExbrqsFGL4eC3yc69mOV+v1CTYsqda7U3Kustm/djGTSpFqDUaNUmNv7
s59H+WB4s7H0P4v0ac2cjyGb2JiekKYXjqytCQsMiVJwOtyNM7tOjPKEr5DFyVazHv2pRLOhaGVG
87WLyoRqDpuHLeZLjrkoa33bl1FYrCa3J6+jJ7/V3xNnIZQChJxZvKwYAjZaE4fMV2ZZJnThqFaV
jzThXMsUKhts7V+pxPK+9zyGMAfbJb+gqTodEbZFGJ3uAmuFe4/D7u5r4ULee1EtBh9bcw2j+Ola
cNtHZu9ufBxtKXSETdazieWpvDhS+w9bsCl/1kwyTaNvigZTEXWAX7zN8t/Lv3wG6d57wx/BxB+E
F8OAUdaEA/l/kXOG0XbxRG2wQEbzuLgDFSmrE62VEjJinXmf1q7lMpmlsJOGH0t6Vpx6OC8xz8e0
9F6q/ODk0dxRYn1TlLWz5oHLnk5CLNiWA8DqRrYx16q9uzU6zk/7a2dB6MGsTzhiIU00omSXkLY3
uhJSd6oKTQspc9w3uPCrB095lhsz+vGhD4iM4/CS2HsS0zXvKKDnVX6r6sYwhAYS1txJn8cHejTS
33a3FzrLh/Lr8tihbnmzdHQJtk+sq7tZb72rWrEbk48sbF9yJahsTCRqNmxxIiHoM81CkKoI+Lxh
cfc0D5Yp/MomiNvkLGAQL9gJNP3W0OyucO7MynZvbq3xjQW7UGuTkM+U7elqqbUSHoc+YvoRMbS0
Wra3OUa9vgiPvfWOPUXkCzQ+GZz5oh+zUdgV9KFSEg78gDsnyyeW/ilBD6TtAk9pe6QKH83lGlA/
2bWItSalCQk+8HJxYzEowKqYFGa6IaIc9tMb8mXj8fSJrYpmGSaaPDJJbiFsHkgzUgKFO56A6/eF
ldbJbZmhU48DLTEq3y10q679uNFxpRjMbj1VLTSaUJ5hhfLgA9jgL7ku8ypfmsyML/AFtmtYlAYS
x/hfNfqd/HxrFDj4suOVtrsEgFli/p8rQFuk8bUKKi+qMACYCmucfH6KPKuWAuxGCuqam7J+SLhy
F6DV5jjns6q2TiCqwQ/SFDGGwNWkiXwsljkpcugaJxrggWO350nMbF0QYxh1wDeVmRmPTvIktQeN
C2vym6ToRxoNYTF2Tp4Y99bkBeDapsuHhs2C3sEBcQs8X6JL4hEvCnkrhPhAFYDvUWiWd97v1xEF
JXyVXUJkVG9BXgkFfhxRC6VBtIUPWaRXjsqkEhgA4GfNh9Ato1kt2NsNy0Yk0TuxhhyZVCo9JfjN
xOUbhJqEzzlTH8+IdmNPKx43EGDT0Lrsk/UOaUPBvFWdb3GqIMg4TchPjXgWpuyR85DLNpqWKB3K
K2K8dzks0hfLCIP0o1ZrJyaV6vTRLX6GDJX6JZRDQIcYVYCtM38a642Um1FZz9czprkChHqQfL3B
NzQrdtyK7LIW3fUDo5pKTkFMk/BrlxVPsmRbDFKf4rxCbgZA+dTNUmlpBauC7VYTM5YFkM6wgAQf
kvhXW9lkApSLz8wKN03C6wRC66r8yh/YqKG+OjTUsFovJrTDokQK8MgWGIzpNPRCNORK91DK5GNY
HEXIaZzdLIwnRbeaVleFh1M2/3aFZkINsBeVqebQim1r/XodkwvYfRJymSowdoWJn6/gXjWYYZGh
nHpo+U87TYAoe/0bNSftOYIRvEYmlBQPHk/YuQ7Jdb5hXqiv8iaBtaRv3kWfgGc6JF0PyuLIJmQz
sePGBoxGEAi/gTPFAp5q7bYdVvVh+ebZ1KPCkgVP67PIAZMIBdM7ytHOVT5vyhBUSnzHGj7tsaK/
AqD6UoWrkSts4FsZnh9O4M8pkE8Vm26V8YWdgHnDnz87zqQ/CBdX9Nf6pLsk7Gm/k4IQqgnaYV3Q
djGKNtk3QKG8x7u/AfFVjfC3uxos9Lej1HjxSt7yMGU5UStm3a89d3ADmdllSmHXG8oaJwgC5yD+
6ZyoV+S6O/inHAAITWTqNss+CZq3wQ2fSPRm3iMIYujSFh49ZWF6Y5hhATGZ7puV05IkX1gc8Ela
qcxST2cD5iqJ2QwgOpu3pXIdq8sop2UlJ2ii2/Ct6PF84r15S+LX3gLwJ/KnCGF+GUwOWmRkx3Hu
v4EWljx5OFiNNQjpL6/VF8J8mZgV0Yatyn1p4Zb53UROPaTcM7aRopMguRKwhgpbxYt/+eTJW6XO
DU2onCq+kdiW47TN2oEGrRxvPPPOq8/oSOfJtP28+4j2QIWKpNEEkyM1waSHRIK9ySAFcsxROSmZ
y5VUaZHpge4mjt4o3wek/wS6MwWVPMsAu3hEPxAU1KQr/u9URt3MMa2fLlo4iYegrEEYe2yLrrAN
jfOlfFl2WAfnBn0q9dqaZPhtJGkjLcv87aMFcrI8E5sRxgPWXNHe5E3yM7fFaxtQ9czAwy5HBQ7T
gJgBJSPfEfU8e3x0JPGyrdeTDJ3A7ttFutTZr1mNDvkDS1bKipmWU7JPSOW9iMIXgy8z3KaMV17o
y3aq0spIkFtfHwEMlx5tdEz8T/iwPwSqX7cnQdq/VsqDUNNb4SVzr+cYcHaGI1VbX/0HzDuMomQP
8bBDfD6NPr3YWlufkhrsbQfYW7WwfFtn5mraBA8+uYpAnFvNL1nN6ushsbMR1N+vSXjcYN5NACl/
H2124SzQrgKMKsLqQRU44LOU1vbHbBKDecnaquvebNH7p2feemLLqYcfbhQerM8RTzfGlW92BjUa
pGu7s0UvPCSvVvGLI6kKWChXl/Ug0dnDJutwDJbPGIIKIcK+2NPBDWx7NvZcgk1vLArNWzWWN5i0
Z8dDhZ6CzgsX9JZYvHPLyXwjLrgSDXp6EkJ3xaVltlxsSPjIWuSJ5UR2t3a5j70+y53DA5hawRIJ
BflpJHyKmzPzoIY+XozhC5geLbq+MLSTkXTA+Md2N7j1po0WdpbtlNFxKyHKeOmAG5tXoFNxuonX
NfKY106GmQh1ErXt/sv1FnwsfMlB1zi1P2UI7BNRKZFKqOrCBbJHJCnZXGXx5HE1jHd9qZY8pcf/
raU+1iunjRWFwqi0m4Q/8gbHQTiFqXI0Vta3iD7PfOvOLzc9cuejpa4JY/ddtS3kX2TIpZRySbii
XgeFxsoRZG/o05PSNLi9egYTmlUgVS8d+uK+3hIvzh7l7GM7KBHA/q9Nsn2MXkbuM26NH3qxiAea
Dn32PsY77N/kRaam/N0h1Zw1y+Yze0k6Xo7SvXAa3PeIHINvxYjsqA0DUbJAr2qJQ9ez9vPSqTOB
Dhbd/08MfHVAhXHpF3fM+00YOk9kcYkG9Ri/eeixt2oEDZaKzJLnnoqvFxeWkGjVuZfdk5dOu9v7
ExEKEHZo+ZvJiEXLjjzmDtZFould5AIW+q3ME1xdRFAo48yScl3GdhltW7oIIwCbxONHp6pPH1DB
UKn3Dh2Z6TWDBMdTMe2/L9TS7lojLF/dKkQy/l5IxcOXSsyxUWAVpL5ZrB9DtijZUUpLiHlAFei9
Y9Z+k80OmqZhY2yO5s8R0ALs1Ft48o5GjKhCgHF72iPb/y0d1jf95FfmUoxwezzrhskMaOCfFgg8
AphxbFX/k+52qiLuQkjtJScwGnNfZDEzWfMjSThKXVI/arwQ7Tn55JqubDkyP18b3uYJ3czC/KiX
yv+ED9+8d35HV+DzUtygwZY7rrisICcU3NFk7cc8i1jdolvkOva04x34YiSWT+zjbKj39iDgMJfP
nq1M1Ah0h3m9u3TgvvOjbzfU5dUNe5/RyIdK0LTLLKGFZO1jZL2P6ntEgfg507gCdVHVavN3mTHX
IPwxe6Y6aJ52LnrwSvqTlTplUK3PXqyywVm3ukSQ8najZI5ITtibqu8sJzJxPESP1h/CGEy2irf0
tKuFjzq4iUmlE08KwGR6AdQ90uUyDZ7BInDpap0TUFE2yqj+Cmg/RLdONz44miMbIJ+DAxSUi2MS
CVoaEGRDgZX7L+1GCwlSyMt9OauSexn2E56pMGI/A/PNjcGrIdxkutQoK2YRlg7i6f+wNb9Y2gcM
YzNWLYz5uyo3rNjHRcKm7HEbiWcCdoOlOc1k1c55wLySin4bgMGuA9UXa2pj15QXYNFMeJbtfhwm
ar4+eZn5WyZ6Q7DhbN8CKPpHO9TyDPvVgQmrAQcWSBAx1hC6wirnvf7ATJlrz+DmfHI9E026mId6
KH40lG9jMqfrWu7g7s8wz6nIBiamEhcd5objUHUEmMKbsASQjGVhZA6QbCbgAukMJWUtjQs3kGXc
FgiOMoJpGeYNPE8MJgGTMl4eB3OVuQh36cD5wqXzYC8GP17NZ/0WINIk6TBXOsOpv1WCDSwhzshP
zuOsK8lBIWHJFZMEZp1ygQP/cGs0RyCqkD8ulUBTV+K+EZcy6DXjw67oee/ALKZrhgkjW/cAGZxd
eGZowjoQwZjMCPMMu4WX0cMnUwzIo4hU1IQi+ktIpNRZkliY3/li31LBpNye1mMA1I1p7/jq9Rb+
No3LbhHCont+fMEy734+6OiLsjBXts+/ro+qRqYFtjyT+k0RFo619T77Yp2untdxkjuR6be0s93j
vPwKi2VrjYaTCJbKSM0oj0YtWmM4nSWlNLkS2h2rjbGdujgcDPlU8I44Bo2G1oMGiCui9FodkZtG
kOBqtjbv1R/z+321jpGACzq25FPJUSd1xst7U+0GLp/EzuEpptq4ISk5nnvG8OpY7afVlV5aPFsj
MBQKt8uSzd/dHgxVjmPeqp1cV0WABPcaLzC/ehxbi04Q
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IVxyk7XRM4VsQcD0QPYws4xsTeDPKdwWYfreQJ7l1z8C+G+JAKZ2psrNI+b5ecZ2ziPH9MBGr/oY
8XtzCKmjJw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VO3Jpo4aYF9TyVwyAUb3a/oDy8Yhm9ea/9mAjNtuOBRL0qoy0/CWzL7D+bc1SnZvEP4BG903Ildl
dM2y4TNyVTBUaU7Cz+LzZfu9kCPWnmttlx92LcMKLNuvGUMPXmV5jr3PzSFEvoDuCinMqNc8uKFO
Ux/aX6fmBD8AbQfpK30=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qOkimDe0rSU5f1zKvoE8a4lZw1WOOUxh8wtTIN0ys09AXuQuNNCdfu6VL2Xuj0Xus09sBU1FazgW
XpQHuw7XcozHRlnUFKPJg2P12yPJsLRkOqUWtHTUXmH/8s2RglOoEcmFeX9FVh1IRMdnp+D/F4GX
/80OwH0Jtm4eUDa5EFkNoIfhlOG4JOG/JCsYRnsAoZAbyHMEk6qPxdOGDrYzkbA3CMCikTuE6wOm
0j69ZgENzpWR5aludQDu44oKZqgkdMKNm6Mvk//s2aUOTBYWabbSKe/I/+cEp1tWS7+9AAmaVwO+
KwmsZsNR4Ztb6OH4hCq0936o+bycwR0b+Wr1VA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4df1QYXbx3PmA5i1scwSy/ZAJgZ0wNtl21eeCeUI5h4IQD2UalJOUkc5a5UR/j7lX9ToyF2yFHzK
L4EoH+xXm54bGihfoaTvocQQsWhCDObbmBOtqB6WS1/bog7FNgoEObi/E19vJsjPSd6nCCdhglZ1
j33mJRkZed+lVziTR/s=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Rtu5N6w0tnewss9ZQUyM3gMzu1D5Ba/+qJO2rdGgk0QN5Nm+4TaVyiEXzVM5DP8z3mycaRD+z4HG
QXarW6RH4GHKahoLlSY8cryjSJRWS6D7/Z1joY2fgJb8apydMguGWjRZ/uW6R7BEimGxB3Xuon63
ZdpcvKZmoyvfg0kjAjor/DxtP3SP6DKxH3BeegGQKpP/+5EmCrAhhPu+NA21340wcbghotvyYusJ
ErSZhtj+1FLwV2sO7TUt1etBG8nf/yETDQPE7Q+zX+BzOktmY3tIKds/9qdyDt6Qb5WIxLMyaMa3
eyi0SGAuZdeDtK8Os3w2ajEZI+VjufruVqtCCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17760)
`protect data_block
yvvRtu+tA91Rtyv3I35O4K6BiUlBjs7LTFLRc9twWgYZkATXrSpXZut2NlvE8mcC7mB31ueT2vlU
P9hzhGYaJ5GcmScpsC1FKNndMfl3Ug9Pqiw49YT0Xp/AQWIr+q38Pu2DmkLm87YVBi0HN6JMSu6G
rwJt5qvXJYVA5oSnqcy27I93z0KCdBaCW4BhEaXbMLEY+qzcYsWxGhgjRzVfC2OhOSpdpDr2MKHw
1YDri1cTZAVy/b3L8VUTlyQx4YRG+qS3u0Cz3dOLm9nglzh9Pa9XJC4+Lnpli7w7vpvakaXaH9W9
I9Xs/9ShuVul4UrHUMsoz9V5jcPh1iHPT9m0ZTeLUdfod7NEEFDW47vWU8XjL6iEqBvA/DrJKrri
hjJ//n7fbl9gjxGZT+IKqHleRVz+dRiS/uTuRo22UsAcWrLoCdroE0x4MAJ9vC0vScZa86PQBj0m
ixJFhU15XHesAUmaWmkIVFZdUdZL6n63C2nZpQmpBX8G1td46ib/xrjcP1HPzbr1hPb30S/GA95D
4e3ICss1yPb8NZCwvzZHNKYRJlVJ6EOWwDxLeBOjWmUySMUcywo+toi8FWztPmB/Fzs/gyRSBxsb
FBe82kj2NTjDK0dD4XCcU8bGjVOKNJ3KoJmC+0UD0jihX5N1CdPg7+/bvmP+MCdk3ondXZKJzYI3
9YFYkr0RM2BhF57jZwHcHHmFJrakmG38Lap7lsdonuIO5mfOOuicr4JGW8Qijs1+c7VMc6LUwGDt
YKznnHTq75vwwVLxmtGYpW4RTIuqlZmOJwC34kp9oVx0+wFtUxMvQgXry9FwUwb2gSWRseSfbmMB
auDz+22lW+enEoOu3PzG3plNq4oQP2K2H++ZU7HNTNGSA6VpJWDQ1c8o+i7+XEkyIqt9DZHUxb+3
HlbwgxRkMYX88B7lb3GnNDLF2YzkJMgQjpyPi+t3N2MtquCFuqNuaKv0LoD6+mwRceg/hAylp3x1
m9DKQ0DcKuhctFlcx3aOGMXc0mzgjh9Umxn2Ng7JEliL6/L086w36Jar0AAtsKsXZ1NsDDBpiIeT
c9pWEQj9ud2144CtZKOT9/hr1wy8/jpi1lQaHanlWWtc/eb1aDpSY58hPbltVjUTyizUFFWsqQAC
PGoqDXF3N036pR2Ipsz0lKGQE6qHOZ9IQByoJkJfVJQFD7arWnGsW4G4I9tdTj8LBH1I0/XQKvur
lSNx9C6iPx8J8GemXPHqEIipG+GgoeMURYc7ft3GzrBdwbTFPm/qrxT/0vdju3tRDBl4JSzWO+do
z/s/CD6wNYNcDBCSDKcprRdML0+tkUYr6Jexl5rxIe2GBG2XGRgBDqc+wBSNJY7VVfutmSr3NjPK
RJK5NldZFn8fT/rjewbLV4flhMn1tgsE6HhNm8GuRS52PpzP+BK3fCtYvb1mnkFy+e3mwc3RgZ45
5iaZGmsBwnJwI9GcgMGoWSDkSaL/1PrI03WtUczFAidTPvIY08FA8CTdX8Bo/j1vK5yj8spVzrNq
2YNw08dzyQOA6p4yaEO8Raki3qlKk9oCGUe72zvHFj8EIo6DPYz7MTOBMZh7qLr1JDqBA+iyQCSU
UO9dElHR49OYArhLqejxnXEbJqi2McLLRKhJoiH7B/feWKz5mjNEjtWpHgiwx6VhyEKkL6UZ1Rib
ZtiEI9gtUbhZ6XzaYm3TiIRoYgTzxH0j8bAv7Zy61YnOi5ds35hrlF48AdxPXK/eT9RxLQ9JC4D+
xhLyqoQdstrt5DgaM3NxG2mKEJVH9uc9wj8j/rmn9YrBedhVek2F8Uvojvb9UP2S80Gz13xgD5DT
uHlDBG0pjratONtNE06BnMLwZRtD8fOAmitaJqr+uurpGUSmFSP1C9+FHTWgzBTdRwxLO8vYdEOz
WFiLspZhFCxJpRdUt6N09XI21qtC+0+ZgVoJcuL102pig2HCGw+mVSkibp2ZzBHApj3TyyQWeR0T
soE6qVGrU0cCA6w+mgSp/LpLjFALA+nFAG3lXPvfyzy3nWkgcWbCXiItZJY+SdblaE3tEF0j7zRy
QEv4a8Rg+L6tHbS4IhpoHW2u/3VbDszbEYb4sRKfYUA0hAwJaM8jOAxyu4YRtJsjn94Jek1Taiie
hp0Ndlnhy5vlx4q5I6i8Nc99UyR9uhRu8iqRtT7nCYuJSAzDby3Uxqh6srwmKPrb31KF5pRhTgEE
hoDR5pRAhvr+p6GEHRm1IAJTB/vA3Cmck+beIM8DaYRIdaZnzC9N04oH+sWVHExAUc9WW2ZHotPC
yowKFvokfu+7look6EHxqKtkI6qUIsFrQgy755fSnh7+GR8EVZFKqkRCDv0zQz3m3MIaUQ9GzxNA
nVZg02l+SgGZHXvy8wOZE4ONpWcUccgX9k8Mqf2VrJEhn7FTdwr/L68VLWlWyJ51gTID4qsEbmQR
eUcVhXwZ8J6/Jr+tfQkihSE/r9/FrMS9DtCeXZFSTXFkRXX3jwy08FYzVkX1AU3nfi5uob/pWe44
jJ4c+H4TgTK/YFd0U9+b9+hcQ/PKCmyuUWlZMD2jh2m6YaM0tRHT7pTE3k+5NorK0KIzBPhuhR0P
kwadh+BfDa9Ed/g8FI4r9aO+bzUYkbubz1m2BkiyrHNUN4b/jhDQyeuJYsvVZmik7vXZ6GcS1rnC
ZJpUE1bWR8FcYhqQoncmXGI126qn791BoIP3g9UyBSGDJ/hK/eFW6lylhaaJjjVsKepmxGzcVN1B
mCwVpKVdTSGBmK72htH5om7KKA2S1rC5U1UUj3MbiW7ZNwfDd0USkl8imBDLwgYFtoEE1ko8C7Jc
eUprl5A05bpIwcNw4M1zuvcSJzD1rtWdZQl2vo3uekE+ox++ptfYE1O4Xj/2TqSRnKWmvElAWcGk
d1P93oZ45PNjviXZ8GjPM3O0qWdvlgjvAq0xdzA6x0TysB9PpseLW+g8nB6svNvi0GhK/LLkeLYg
V+VOQradYifDOr8PNb0cqid1ncvsR8+c0tlZfcJr23pLfcE3Vqz5wPmHYoK484/vAUmQUEHiXjLv
MiKyjk8ywnYHQ/TOYWuO5OiF3b4XtDucLmEyRzxNB7rY1i7qaj6wGs15PP5RLOMaDOI9Kg6163IT
YHmjt12E1isvBtgqS4df/zN19hcUsAr+Hd+fpoCiaRD8qfZT7eD2F7aDUpS5tVOH7gVSyJWqzQ5q
Obv9Yhw7rja/O45RtfCLUeQNveIdOxbYJdxtkbtNUL4THMOaUooUKNDHf2XRJ/IU29P3yYsch8DL
w6GDueFKcmhtTaLLsoIw5tztfz1OnR/Ji8//265ufazAczEkWZEuwDJ820UjB8sYf6rqgnsGaFMq
k4/RqF2vivZ5ejxFZq4j5HxYIkrT0dvfR14iHiz1gFBjRkaPy0KB92AudlRi5GguJSj9i9apnV0C
9Q8mNjw2IhqKOYuyV9e6QbBpKJ96If+glayPM19wkoNu3wYrQpc35Fto6fYKFdY6dhE8nKPhcitV
/uItKlA/SbBd82Zd2+R5YPNcmQq0sWFXHgntGjncAGogKw7gdfoVMOM8623k3ZSxgx+hl1hERb55
2VAlad1Z2TVWotbB4SU6fYbYbkgvMzH5sJuCqbAAKfcoPFz1nWbbyWa08tpLEd7dFgSfxRMD6emG
vbRwvFQQjTUHayp8X4YhTp75/cn7s7BNav/nMANVwbzv+7PlcCBDE/FAkBmre/mWCARVoeNQi9yk
Lmy+/QFbBCSDmgH9dT+J0qyptUReayys26DpOx3zpnRbUVqoevpDLpdsoEIttEWQIhHlgFCwxqwE
aRk/jq630RhYJrspYYhMKJx7vBModJIEGer5px3GFiyOMr4+4I2Loz4N0yOCB4NxzVtMSM+DMFzb
Yqmp3TY7W03MSy4BUlptWvy4cfrCDCrea8duJ43frMTKFTfbW+IerIgRfu6o1EW2xXm1cTpBK1C5
GDw5N3ENOo9k6+Og7Rv6BqrZrvmt4KofAZpoRQwtrvIUEswUfZzexMH0dWDua0IDEUztjkju9U3k
MYVajimuyW6IXCYU0qQCvsz9sBM2LLZ1x1Vup7fB1Ec5aPwU/UHatOkTm3aX0ZLYdmaCrVM88w9G
XHeo1x2sSQwb3bclHeYGqJ5KFtGY8NkrjA2kOqD+X2jo651hd0o8X/ii6dRA1MaQa3XRL48KOtEM
HH0PUmnhNz19o5YiXS60R4NMyF8DBJ2arUQqgtrBdHpYd+zsNwOO4FJe/HVkB0g9fp75mEMH5PiJ
iCp8PJo1jsqW1yWtRGUFGwq3z88uUmySC3W8F4jZcCA/IVM3H1z/nL/Xi6GkPU3ho614p2M5bRq2
14TEYUDIUMMz5OS3VFeKp3NLgKmCpVj7tbmiZi9T8Yde5BbWfETD2YjKPY4NPYiw4TNz+908oHc2
yTbewFueWvL/NaEUrh1xMwQw0DRkd8xsxovrukJPMeMMIOpJVuHAqxeQFIhjwyO05shLRO+8ICOY
lVC8RDu4KIeHaBIdj78ETsgHAau5157cMpNdCv1z6u/eAEhsPNaTpoYf5z4Ulz5+vbrw+Ig6ywPW
AC3chkAwdqF9uooKaqUaS0uaMYKHDaK2y5UfVCBUcfko4mCk+jjZbqPR4oE/RY4mRKF+S5KVRb51
goeafsPpARmOwOZcbpLNMXGonqOUJEFV7nFBn0sn+mMycGAzE+JXd2B03sI8g6vqICD4805s8/Q7
Q9RvYQCBXt2A6pU5gu9eZBujlJ5yteDEmqSPNTNLHzUtnYMoAcOjjRN+mnEfti3CP2YaqZYc7AEK
EmGhccCK28g3Iq3fyEIwqSG5ZMQqTqoqd2RXD5hdEa8/QoSw8h+tBDysQ5iCskiecYnVoVm2sJ9g
EiFptSQHJIy0hyW5bqu4IBzo173gYuxltoA/x0vJsCyFYs77QhbyJAFsJLmGHqO3cT9lndY5RmIe
G2IsYZVzwYIn/hCH0vy7GSobNYDvEMIvGBaU5p1UTsf1zLoaBwNW5il64Rmt8mWVqr6Q4Cv07zk7
YKXZHTXhEeAgsPcWekKsDPhosTQ1OG/Lbmqe6Xtt932gr1mKpZC9HDG0zXIrXY+2oSE8WilO1BRy
J88nrrr7Yu0oYnF4wZWHuAWIyjgLKyWWX4IP/WRaze8T+DWjRzYC+x719Lw3Own8W4ws2iTfKhys
/AoSQctmniBEUleebvUzkP/54oUfgrmlSFnT+LQI1wpo2T+VfQtutqXZD+Q9onWKVVV4HeEbkZlD
NiZEFqgI7BCHMNKvyQsr+gN3d1+ljxpDWwjLTifh1kNDK1FTX628L7Esv/ze15vf2ojo/9c1/gl/
t1SV+B85OJEVM2ghrmoVc/L4ECZPJK0ZQo5F/4K6TFqIGKCvu6JvWCTXCXXQuvIJWVCf3yQ+xB28
CnIRjnpjYhPYNojhQfb5Zv+GZ7LFqZZ1/o78veE9yuWl0lUlNLkf7AciAMp2qc67QqLSzbmp+IIZ
GRPGcMLDzgqZMu5UoNLRtDcIK4IdO68RfVU+DfGj7azU8UasdLC7EXFxENSmQ/djh/0I4Ci41R+q
wsa+kmx3eYs+rFXPF/gpMof9+m7gcNIlaKRiKrmGwaefZwbiLS2b5ZrIZ6dIXfBst6s3VP1CYaaa
+z49NTCU0GqV80EBrXnRQ63CMSRECEHoQlN/WGzyaldjxjHPYO9Hmx4A4l37hy0X4CBEgwcgcLmn
2IaYATXcAYJj2x+86KLB5ybH7SyK4Ew14BYjahhIhbE/HpiaKw6srEVCnQJsybU/L8kpmLrJFJJB
A7L0H6rsyqypQ0Gw1vYRNT/Iq1SfeeCbJucKyPaC8FIIMxhLscoBs871BAGV6PnoCQwWlPdh7wt/
cV+rFe76p7fOp7y/iWBGEIZ3hi+nWA/1wg/Gwy2n5z+TL5zSsOLvSN/UaFnaFFlJfzsshhbbzRjm
u8HmR4iISYlZfg+PuCGg4qWDzTm+W3rHe0IKKFdTl4GXGM1/EpTtOAqbIDIWKEIZkJ5l8b15nkSy
kXA7m+xG+B2kCr6obeLcnH/Kll+3TvkRO20Bb17nVNUb9o9OAtuAZf0dsN0dkMWVbDBmARX5RrB8
Xaso0jhmy2GD0839FOGPRmjq0itlZIHy9gyGxFuelbdXGBP7YJlreCebt5nS69xLW/ntBMeaobHB
+fuRF9ZeLz6NIAjircenBW7v07uWGziq8CV4rmH/bVbBQVpgNLXkN8+irSvzIih6+uQU+4qnhkGf
6DPM1CIN42m9ynyzhboG0MwLmsmxfHNu6W7pdDbuQK0nD+bziOLzzqrXLBnyPXGnwpO2QuvUEpHz
JbvGAC0fH3+ZHVgO2K75xWmD0ckLOS8k2Z5yXiDsc+mex5g46t0h1hrH4Yyvs+xHhn22sZ5vmAd9
z+TAxX31wRoiRQvb/b9h8k+DfNRbYFTRb2ARM5f0wglZ2CBCHU3UDca46UnCcX0s2i8dCJiik+U8
1YIMvzM1YeyL3p4mMj0N+JIFkUtiWw2Iimbj4Zp6ofh5N27FA2Lw2SNpuIQppGII0um+Cd8fl8LJ
wmvWzSxiUir0Ax11Yq2EPE4jm3nKtv2sY0E6lx8WJYJydjXzqOwe7I/q8cblI4Vw7LJj+vuX/Vac
5mEUxAfQSPmHwmPnz7dWxElLo7zN511DK5ZEC8GBtiK9/m3RoIfI1+3Csl/GLaL5uWLV5jg3nmav
Y0x1hldBRI4gGM/8vCOKB1q8BY8TbeB6wETtrgJDpKK2w6lzrgVWA5wHTPjCuFeJZQKurXZeL80g
JJpIX8UxxYd+U6Gg7ji8gqW9cjciYoznCFRSJAcwiV6/RLQ7TMkMWTU2UPbgRRUhP5AJaTlsHLBG
kDpRv5sUys85ONbc5+pksLhtG+6Vd/mWvnomEBms1/e+jX8+Af6n98WPo67PSdCntlBBB0GpSw77
A58uptTtJh3ZnWGQRMSuQLMvad/WJZKosSXA1e4gAi8brVgIYmbIc2kzpFVAw8CT8ZJVQt0dh7lh
8tVc9ifnMjHMk7eBB/kSfTmYqiH66g/FPPIMThz2zJc8uB+JcA65L3cTruK5TAIZfFjQsRhDD+jo
+IQSPEMe5sSQGn6lLvuEYseLQbSEswNwE1xM0mWOmQTgipmdzDR1ApQU7CJ3glXHI7CVSZ+Ptc0x
tMhQKU+3nMUBMdbrbWczDZr8+LtuVq79gy6RjWSEvDiU8k/C2jfU7gvAAhYeQmEWA2ZDfrBZGMUe
ctwS4RKrBsgrdotouRos6i7rnUYet3BfSROrkb0kSdMZRGxAyAEEU/HXaAAC8PBph61GdBPOjY2o
ucgy4/5j59ePvr2AHV13YPvzcUThetgzbOE/iQtfdAyChyoVx/t7MUXlzDXK9YyFeO5akcWlv5cV
/tZmdn+0Ip2LqVVRXFEBSoKdQdXJdPtlxjfAelCI04ov4YoJ58o+t0nhwgO7bkbIx87oHNgrzQ2M
F9Nx7WUW7kGIwr83dm82aDD3MxmSYxoppKine4XFBSQuB5OgrdtAHhsoSTFIgdLrqVtjPempXbGk
sAGCyeTTFU5G+XjRzr/5F6bDtFizNprxJBKDaht1ZHz7ETvgFDqUE1wXMVV/4EQdWo3mWO3IzFHy
MHtIRlXUch3GQNXGHB3VG9FfABO63ISUv+i8letcphRuJGaIqd6D140yb1j9b65V/pllsmcXjxZI
Ah43oD+OViZ853FMzqnn1m6QUPSsMZIRyqrAz1NPtluN+CJrw1FCZVpiTakwpdxU24wYPLdzkJVt
MpfNjTp4CfPgAm7JSZ8uNwQriV6W+lMhO/nOlWDmWdpkvsTuaEmfMCDUgnSLOZS+lGvmuwQqc4c7
zpaP6+TmfafMbg199BGBGKHnAzZYORNMzqGduqQH2rfIjXYsYhgEvrviZ02MrjLaQZP6+Ut5Alf8
E/kL+HVFFRph1szoSkmJ7EBXybrGUR5qMCQirKzjN+9O+mZGlpjLRjEm9OvwEI2YBAdnbEy2PUIS
EppQU9iHilUApIhfes6nYf+wBw90smvQ+ggytyPZpyUuHI4qtFg7oOfeQJsHmMUTERb3j27kJedP
2tYr9qiiRWvUkdwJ4KJwqWf4pQgGognpwYEamf+1nPv2wTMMQK8Xx/yjdn10Y0/KWTAYXLQMmYjz
1frZ7sNr9m2G1bncTeAGzAAYatbj5nvolqrKxgG3z0xhGVUVc40Ki2Nepm+7jD8G0IY0ml5LLddn
YbZpN/8M3Qhx3Xq5oGiH/2TnC8sMX0iYn2UCyLxrWczitSRdquyZOivyQrbiaox+Q14RjH2RZNd5
aQF0j+++AlFnkxA005oCTlPjkpfMTIc4RxeeLQJ/tOK503oFkgsrCogo+yF12lnKy6igucSzbMPn
3Wor45sypUNSbvvkuBCYT1dqOqZXmmu2OwrJxxib2arzDMD+Od3/2YCFIL50cnXvoIjhEB0DXR9K
/K7a88aV7qbJ4DHBzJ3f0XIdiFQ8SQgz7J1rbVBgheu6FymoZephdjJLqZb90iDDQWVJmojtbzXg
gFOUIz5M7rwsn1szvg6OQvvyk2BO7F4pzU/gosxylIy+ZgksSmVFg/qaV20rZ1k+aSKwrFaoQyeZ
RFL+1rHpj+IbGKJ0T6azxeZPrSBdULXO4GIJdvr3Qb7m1uZp95FUpJBDu9qVsBeW+e88fCT6V8gX
VS6NTuR49358rzHdu4P84iHiJvQ86U9hTj3lb3jjwQAZN8p0kHLIhJ/OK3HNXw+RTjLj3vFhUR/i
IRh025GWPgCvLKW/Fcjs6l17Yf4iBubssKiYf8wlCs3fcp9iubVKMP7pRHwefSdGrCymu6kYmLgw
mqeCa1xHRtdyJWo9Qe40/RZF/z5wrG4kAL6/QY4JsNK5IuaqdL11AZL2SCSWi+If9d6xMChOcgdO
Kz8rL/ul1zVN4v9usZdnQoWuT37LkO/XTV67Fotcg6wt/2SklpnESLjZ8scuc4uMPNBaKqJxjusu
l1vSBAc0RfX+94qdKAB1kZkl5L/0wR4MeVpy7u7MCHssLTOzpzCO9upNisBXiFFPDC00CfVouYZN
XXF0RkU9ILKEeChv27SW6Gi7Qy+jku7OC4OkwVTtOeSe3uN21fa0MxUAVDqDcSYih33eUdQ2UgQt
L6AkF4QraqjCQmkNLaNY6/FADaaIph2sC0y2v4R6EliBhBDUC/ueMaaLEicWDYdky6CenbfyuZOC
Uvu3Y/IwIV5G1ioj22TVv+/LM2NMXlM3efeBXVFLlpk0glMoySXNMXgPIwpcUbWKr9MvEuUqvHfU
Ua+EPFCKPWY+MPtNhxODgEaf5SD42ilmAXixVxbfQgZT8KDy5ESHSevUnG4beDCiUOx2OxSZYEd2
WecJ3ZL6564z/G4fc7Om0ZIOU9ng5EgK5ufct/8wDhJxhrKfWKF8oGMAz/NIeDg+KDpnnOd9TWC8
m1C/nAlPRFVJESuKzp85N/iFta4ERlbMXC3KbBhJx19efD9AzC6BaiST96FqCaEQ0gbAZg+5M0vd
sd4uARkYKVZ+saEmK10NttpOf8+fMTy+o11z0fGYxK7evc99er/Gbpf39qG9yEfmAEVRfphmZPIn
SQf7u15eABhrE65ulYC9cW/1kD9cckhW3Ca6Fmggjt0dr5f0xyY9FGPQPcKlXF41lN5BHyQxsQIA
iGo9RSECpzORa/a8M6ZNFsEFb1RNk7PIJWUUTwA3yGJ86kp56QxDSwHJ3pphqBtvncSbkJA4qxYe
VYFrqoPM2y9CnuLtBx77VYq0P4lNlDZj2jk3mHJrjUoyGQJcNWMrbXeusyvrDBumKKKJuoCp8Ji0
/RMJ+8HFg8+R4uKqYvpIJg8NyYQ8vYA5vtYccRW0jvZP/i0U6PWDFr9Jttd7mvkTVOZWVQzQwIa1
CX0sZXUqWjeUdWRk0PgpbprIfHUzRGF/71Zzu1yRW2GCnx767EQ5qKMpDIk0GPjYaqO4xoSoi9aM
1yz/MP17scsZFRtDTEX3mlGXuzvOXzoZuF1pv+cx/HZyvxTWVigsZvXDBZjLh/wgy0creA+fBV1k
8fkV6zAuCk5dk5WqKFfYd+1UeCPMcZKIBp4CT4CSOy97C7PdZOfTtjBE2N1HOoaQ2ZxOQQfwlT7T
fBNkY0FZvjuckL0I+G/gCuS39PwVULFYbFIzpXBM1Nbej2d5BRC9Qd2AZu9sxMPtcZKUu95Tnwhz
RLTAtWmI3jpVmutYnGnpM5mKwhhOdMO3VOC5v3YpF592DzT+6/6Acs5ks+nnzpA1Us36PVKcWGkE
M1WjUqhQAuy5AFtL3rF2Roudc62UHxBXUcrRUznmTU0m6HWy5ij6umKW8aSGQEAuTFkgHG+/QK3t
lkny9IyYFmqLI8pYvOJTBRa/mUHj/dj/6NbKzslOo2YhiygO1nVPUAcgCQY4cgBaV1HZAFPnSrue
xDDcyoDCQ9XAq7HtK2PK5zi3RkeZ2APBYNWexQi62G+cTV00wfk/mJEXllv7M1McZl6EYNB7w7Wy
NSFsKlLu8YEu9N+Kz6RKVjxTNxRK8PL4e5PF+lnFbOzA7pjA2WZ8s4rN/GBsDQxj+iRTW9eFFwkI
55pwh0HyA5SIW3FjpJUf7cIrlGZ4oEXT7+1t1T2BK+cZECsvU3yQPWI0wujjI3BHqX2Avcr6Gfjj
Zt/BOCeLm3WPYbVnr5JtETvK2x7GxSyH+9LMO852zV25Cd+48P/c6S2Kw0ca728Ny1Y6KGbL3qlP
4EvN/TZ7etw5UKea706IUXwIQVwpP5jQ938y0oHDYwffAWQlBszHIVreDFPDhRH7grduFfXwkAZq
Xg1+sBIztw+hxqlMs53QCz42G+g9RWycycylepEsvcSk9fVNm6VmgeZfgi6X66giRnNJpU2PIBAF
TmbPAcrMrGqiw6Igp/NT9dLv+HdaubjRbMktYivcwKhtfvRJxOMuhYot4wWlUUavaDQbJmW24VmJ
ZwCVPPi6rQ4Nhst/OnX8HNiq2U/gTHWXorogGqfyr8Y6nwQ1i/rMdmxoA7b/GE1m9P5/B6xamFQg
EwXo+CxJrOCPsGlEdrtI/EomayDvxVj5CfvkkF3AfbS1sQsfyGGG1tUvsuzyG6HbCWTS0DgHLYKw
mLw/kac2HudY+pRGugwjN7CsZhMmmjhzcrMq0IOLuASVzEQ07NRtu7qYo3gXq8qnNgGi3DQKDYrw
SYfT6Pwt/XDOLV/1Nwm7lrkBfprfCHgW0qbPVabJczWZCD+LcxtBQw3gU2094NvU7pb7yPhlgrq0
cS5wrnWHRgkSVTP2nTdECUOf2uvdv6UAYuKZB+WHxfuNgMuJy+NNx5KfDuofgKn+lYGw6REYH3Ka
ZOfYztF8bAdIPEvwSawpzhGQAiNBWeC79fEj8BBPy695w6r/wK/tqaFZeWkyTtf0I3GsKFAFjoZf
KzKY+NxdAAJi0qPk4lVk75CJ8kptfpPfFywJQmfyBb975TcM5vpsuS0OLQ7PPrjlQ3gHCKvA+H4n
QPQpKtQRoRv3axSt2d5bX+nHX7sDe0XLK+YohWnf6W2r8ED9onbhdOXu/KX2OHKoCbv/dCpO3JIs
yPgJIlcsES6Z7VNPf7AG2iCOhM8IJc2rkfWNF05kCosrhh9zj72ovE8RIohjbE6NHLiuUlA8oede
e6MJsIbj7L6BcoK50YtZJ47mkqQ53XN8aAc4J/rI7owAq6S9g50tYefm3L0nPbuCGWHERzd2gjBj
eixz+xrcNM7tnJIQKf3BHG5GEXQzMr8loXRSFArDmZxS3+X0oRJlIt5ZBx6wPaJLw/47C403FaVO
IQ7rKIj1J78aFfPu3+RUWyAxXdSUla9IOrNugivXxl+/pixnEdfqFhdGh7sINrMDr3Gva7MydLld
aT6Xxy2ZXoCIrn3QUJYKAx8iSWuYEwP4DqSnDEcIzqyptarJmsEalMCp9GrYMqhCwNqKhm7QFRVH
EJZYkgW+8UMhys0ogbrtFGbOrQzAPtBJbeUFIniW3mJQMXc79i1yiE21ixQ8ixak+mrYSNslA3e6
hUZFTZJoh5xpuHQYY1nBk5twjasanafpLNUSwBeNbZ44LL0/WMXxVmEI+OffB5P3t3OhAtcLuUmq
dmfqUu5wfet7GcTzjZMame10OMV+omk6zhW4JKpGLlaOc5wx6/zoGhGWuaT+cWFv7j06y/IK1Ge5
VwYmkjNekZd73ikRPgWbiiTGW9uE4WwlB6bawr+FtFUk26pt7kv3iGZfcaexkYk3gFuoCjMatcxm
5iJBYNcSz8AWR2X2L+XKSxtSf0hQgxgqoTL2UfsFHmKChrS4gCUThdVlzTQXUx4eyHaIJJH9DnFE
M5L/7tl89MeROUUOeAtes3QIlHeFFHBL/Ji3cfap8ryGMN1/gtgWdRFkXnoX+G6hQhXwma8qXikA
LWFDlKPRFEnz45o+6OCrGzLwe/otDBFLGfQ+GWVpN0kV/uZQ75Sf0e/PsUXpFnaLewiSKank6gwi
8yF+WH1FQE9YQ18xUl4fwH8mizCAxcpFYsA0t+RbSUT3n/4OMU5Qp9o7PN7lBGRIO5p6cMtXRnXC
JfW5MAwmEbuYLebmtXFTuJDEJn0GyquYWPiwpRZnv1ziMZpHifvHl8+OztIxJd2mYoB0qILovXrv
p+sSoT6d+Qt2nOaFyPi/m6CB3U6EZTDb/lY9CEtizEw/HAA/6VwkE8uIX7K7vI/hr2H0tduoiiNC
Z7Qlv61NGDw+Zsk5lf/EB3d4KiMTGGR+U3OwHtOnm6VYC8rcu1iaHeniGKq68Pd4RNabdW0SEWBG
SCsEB5twlwDDXXKD7ZjGPdrzFL4xeUQOh7FvLbwmC9sr/yhddMvrFkA2V9wW905QTisuA8OW3JSB
AUh4iRU5p3eIXnK4bV5DGLg5qrBMXKp7ITgTUsrz1GkN0djgyFC0XYoOcjI7B/yHlOip+3I0y4mv
lvXPbxrefN6gyKaXEaeKqc8lkTrapgWmcul9IqE2dc62oipP4yfF9dyU9mxlW10geK1g24KEyzGo
BeRphtKG4Qmo+nfR7liloRHvowONq++DWCDl7U64lFtPGM8DVJ8L3f2O4dZ63W280QNqOHfM+D3v
oYV1BCKRuIDzGPh+aSQpVALS7SpCpa9vz5n7NadTJvhdFlHr4KfuJX3Dh2oImi+n71N0Qn84euc1
fOD4vRyV2dyrbvpf8ZyzqYuhxBpx4gleNeoUIVPfagb2FoQQ+bskrJ9Fzaop3uYeyYjVHHz9Hn/v
kD96iS4c3YZAm2tkHGVHg07+rB7CjCZASOlDUuBZBYy/Vf49Oo6ZIbyPX6zKW1HIZX6TCXgL2RMD
Z18i6bS4dVWdamjHoVM2FEWy0zWmP48ZzqIofGQ35eZ/S/W7DX9ElshVXWSoz2DnttgcYeQP85Uy
g9m+ziCUZIcadRW964AoRUA3+eqQFMd4s3bDuqBW3XcuFpHSRPXh6t0Fs16Zxakn48FFt53gPuPn
kWccmrUbXLvLcqhA8NtpSsiryUclKgessi+7wqGZwaOZ/56iVBpZqOJwABqb37gDS4naRX5Lhm3s
m3HaTaYcXMsCHqn0auTQIir/uX4q5UPZFQ8Bz8UC3UKxfj5ULvWsnpZTirNjNzizmAgQT8RVbgzU
2G5ppcdSvbuZsNpQGRd4Pb6lyI9TgsK+1nbLlHGhemrdiL/34MiuObwmSLc73QRRBxNgFET6e1Lv
o6xWN/l6TErNc+6EiEwrxgHsEDYFHeG6qnW1ueS9Lpmo4/z7e+6wy6Tl/b5WouFHRr5e9BLEbuxz
42BX4dBB1w/PfHqyvQ9VWKQ2jLS19zH4agGu55yMenuP9MgLtErIMJT+Bl4ELPGwB6MlUUqTZB3t
VQC2OppjbtSjETZroDDv09xkwKjiHqEFViOwEy3sF9EdAetnX005D6kuc/K3fTbQi+m6fMRiKN2Z
BiUYhf8XENvED3ZMQxboABD11DmJ1e9Fs74DiyxWCij5drQwOkqqstt1vqKAB5y7Yfz7BEDaiFt4
N/hwftM3GyDIag16EDHX9KUEehn7+WAQVjm8M9q3X05bEsi+YJzDYvQ1YUMmCywjgkrU+we6Zlfj
jwHfaDlARpdR7SkNfEHejmsi+v6oKmporsGFi/PV6Zto0tsGqVmsM4rG7ACZ9Rr67LZv2ZBYmau9
YMgEVa7MgE7o+XRH98+6g76U+vPo8sDSXBzjLxrUWj7LbaLAwHwCiaHAk2NE6S11a38XlxU9q4Rc
V/ZeXX8H7FNqwpWafLtSUSFGjVEl2UPuR+LqiFTtg5pDbXTI3RUZ/1FTQXdKgs8mgkiZobQpzFE/
rrjhpfu5U2VFgUt175KUgZwXZkH/mSNkaexiOIwbfcsZBAy/tKw0ZMHpRgmxVxs6aDNEnWMppYML
mirp99KtxeiB4YkVvhoCIgRH9rd9f8SjF4hpmqeG33F+I/8aGa/B9TDn9mIOB0MkA9G27OhNWHti
BhiDpachcuiKHNRXtROW2tZ6QSKltulLhEE2tKS5ySwwxUggM23fjcafEriJsOg/75JPoP0f7KSD
GKya9azUZuLQNLPDToOlCvYyOgxC7DwAJSzAineFxmxudrjNaala4ME5f7ber08k0H7a98KpnWhr
7Wj2/ZJ+vEdRg5LF5JobYzKvmpaM7hGgOO0Y0TDtIOO7HUt3HbEwZQnXW67gaNwbS1SMvRGswaYx
K6wkNU8q8NKtgBuc+BLolYfLBZRJcyR4yNDpU2ZjHuWIT4ts/OFFXInD84SDkSXjHApALHfZxsnt
cTfPbSH8fDmCJm8Vuoqw1xgU6RGcrAVPTlI/Bq6t7tCPO+YaS7Zc7owdZvEsNMbqoZsmDCFe8doV
8cVthfoNVR0f3SFwHIhWyLqcudCO3w5Kbmclzjof/qugz7XI3W4up1D76MJKqi3dcnruoFlabFxm
tSwx3GSlL+5B2O2YixhTq2xSfw1sszftRCihJ0NMSoRqkcjUCZWV/isTBo0MmbQfNmdasTOjZ7ew
2BGPXSHQT6V3s6XY14QEqIGMHPF5erZNNQZhY8yMaHagYfd2U+nuwBd7aS4EyGQFpNTw3QcKE37V
hGX17EZiG8Wq6MY/44BXOfTCtCeKo/byhuif/pVMsu+ca4R5zGuY3CiVWYEsPvzxF/qKifpxZi51
XRmtFk0dvxCb9LZijwdOxnyH8ZiWDHs7mJnDVpcWUMPZU8IvqumksK95mbWFPl5LqmMFM0jEs8PD
mTfV2GTjPFDNIyUlS5wgr5mAkFV9aGhFTJyxgym8HJTFTPnH5yHrrcc8JJLtN4hU1di3Xn1fE3uT
opoRvS0bdUapON9OlwVhd26jM7wCZBYB6trMJ8Mp76myBkkv39NINwvcNz0C9PjTC2KxxPuukWtR
w/yhSCjv3HZENtmeUszZgrIUGEER9oAiD+owYoWYlewK0ILXabNAqrhmEBqBHrr9oqgbcYRDzuYy
tXp0TFqhsCtk673OJdQGB6Oio70EYcvfK2+/+lQbm8RY3MMrGTIdFT56B/KY7jNhS0GK2TQxwqhs
TRZFKV/ZJk4siqHTytH15d/JDe5gR0ZT6YLiWctRZ0o7rDFAuWGOts2T5plZkYkKlicuij/brRUE
VoPwjXc21Asul2nGZ4oqWITvNNvqsSj3pZcib/NkEb/ywxjqeutPrWHdY2z9bYYV0afl6iN+OJPF
mRYM7kLjlkifzhHkjMHeNI/3PFm0mygSZsjtHDrFRcYjNY27pFqwHt2ydv+Y8I0N1SDHvn9BLNJu
oFVKeuo90KYeeut8r9DrRTYqFOonG2OEQDDLAFRufZ3qQCoZzCVAz2808ZTxpmyZlUrqqRB5eNoR
fjg1JW2zKpsRpYXTmNQeMRdldk+Feri5oq9cGD5YRVbI8qXrgCFVgnHaSb6bgNKjoxu7ljGDhDlA
fyljqWnwjpwLnJrnLEEPxCA0T5/et2QButOgW3nnwmS1l46RTyIuJvDC37QKPJAoZiXW3NONxQ4S
VMkIxUni4WFNp61+I8ALmhKWYBMnSF2olRUJgjx/5EoFbnaRnuG71h4SLeOPIDGWQZc0jBwrQoy/
p39/L/g1wLZ3FqNDV7qggQZ0GMY0PqS78funhvJ8e59DeuguR3c8Qw2C0tcThu571K4wpX/OFbnY
beeizjT0zdkHhRSex+8gBUGhTbaSXFA+qwXR9xCY+C7zYRTKO8Nx+cPPqtw9pP9PxBswmjqhEKt6
3Ck/ADyCLZdGREp/A68XVGVvHb/JvfOg35vhDTnY5YS2yaSxtOlTrfweIjcpHNm/KYIfyfc8tE37
vQgFgsHKTN1WfK5wTNKf7aRiY0HC8102JHI+A45viX2RWjDbdLJq2Y7F5ppx0BUGXajkekHFHtTP
zGH4mWnc+ZM9cxpDbZHg9CWY03g1SIePCaPv+IQWravG0Y5/FjoT60o3H5FyFBudgMVZ3cp8VzJe
LvD1NXLx34aC55OogymYf2wimfHqDswutWmnj+tuNMEDOInqQNq9UcHM/OyxxtX8wTTT/NRUFeVm
VeKtfofxOPU4GgEr7q/dgpmmyUwpJdTmUIWgEo/EFBgHOpfX6wnVmKNZLK/35u6h5zONTzL/dQna
H6zFQ6I+cQKT5ug+al7l3k03OO7iBB2zXBSdPjOWpTtDodnsbHMw86WcpUsjoqFkiDJh0K9pAiTs
yu0YtLXYhpLRc8vLx+nlNPLnBlewheD6Rsel2vUITR+Y0R+LTIVcFizL3RkCWpgT8Mv7GFBus0bs
tXa7x74NoVvDOv16dK5Bp6co4kem5MjsBMqulNnb5qAiSRSAHjJVEcbgiN/ejphUzKhhnQ2rLlmR
J0srKz5SDkt9GoLIIQYs5LiQz7IybWCgpgj6AsAgzJv8o1wGzGOJFcuutKhU3byY8gX4mvT1mcoL
+oV0fltqMUZ5+7fYGYXRzx+IoKYTulFlekV7KaIy6pn9anlT85vVRhfq3tNZZRGuUALVSiHKp1Bv
hSH5jlo6taMLCDODPF39Tqvftq6OemOjXklUiPQyYpE3hA7qrG4TTmxYZzDSMPUrCpTcgg6vjYA+
icfYFMU1pgr4fLmYJ0fROfPHuGJh8j+aeRnjdDL1S9T5mRS4VQFv2nBpMet9lpa4++KbevKGFfwJ
BO0QF4h8xYmLMoxmJE4LfilYtw9dGxV5baelDnfq58HheZD2ds1QdE7sNtEpXV6y/daqe+F0IrwO
EggItvtulBViDAFHzzEs4Ors+9e3U7TiRkh+FQouUA4zwFshY6xGA6Dbnol3ZBzdaBUiUM72DESu
4f8i55WEiA1ksZPV3YoWd/4fFxoy40yp+YAThVsC3PUgYwIJd+HeGGy4QmzfwbeK+mDAR9fhkgPx
nzDL3LV2Gv3HmCCLPBRF3HWk89YHpBOvD6r+uOVfqkM48561HfV7l3A6apzVHxEOEh1IyTyiN4f6
3KVzCDqCvavPKeaSnkFs20XLbL+sYELy1lix4/B4BOvvSBa6muSI5EwkO9IYHRp4SldDU/BoT6Cf
qRS1nv1bScZ42MttKPlYo5C+D45g6wpNReoA61TtaIEPBZNYtLw4TsZyYTF8v5ZzdClRynhRzcCS
TDxMcqXxYDSNoJqUrB7zcYe4AU3uO+Tj6wXoA39LLbsKtK1EY16dK5eicLPwSoFRhW+yHzcF2R0r
WPJGyuHI7ddZdu81doAYgdtje29f2PoQ7UdSTUx5TaBtDIJ3Rj9hzUirGokvUqbl7/aQny41+3XL
F7yI+f+1hfB0KztcysNAoH/Ef6mEeMnfNIZ1MWfgKXi2mHySkygQ6NWZ6vvA1E4qyMJXH6Ff48/K
gOLCxf9q2hiWqZQnp6Xn75CfUcw3BVuhzDPyLdr0RuUnInmBo6zzYXmuhUgWD3UZOwbOLMbQde1E
4+ppigWbA6D8yjjDH5d///Ez3Ge5UANdGKtn5+zwt6sVz/UnNbLaIxHavGC/XYYHjVzK8UBa1goj
rRjxZYq+/vP9jTUVM/We05Tuu6Vhr8Xqgqbs4LxdLvSY5ZRtfkiZ4ZCcUX6PAd4EH3/mr2iiXXwk
MaHxtETB5c92jL0MYVhAngHcoQp4PXcVgMM53uyhUPz7f2ILQV2YDlsJucEYfDq13cpM0FlEQd0h
5mhrSC7d1cT9pzwN/S9h7Qh/HzA8ELwUmuPuJDo2/TpqVz3rFrdQd6zrjucPEC8bNXyMJ4KKbI8D
jSOb8qPFWrNmF54vmxSvOh/OuuWoD9f3nVoFgkV+u9aHOriGCvKVf9fo+9RKQjPtDXcFXUfhU3Cv
MzmWBqGndqHMPSFCJwZft7uzO4LOPPH0VfFoxWhRynQwCPBocMx6x0YUJV+M3EFU6Vu7E3kJrFsl
y1fn4yO53dC25b8g4zcCCiBPZyfjr/dEPpI56AfsYVso/JiXvsCGk4Q44hgxk7E2o05UqQCMycBS
ygQjxTdflOik9YO+XOKbMzwwOKB9IrJf7iEl2lQF2K+TkGRUH4+zgS1JhcVqHPMQR+DJxVpWfM0M
H47wPKt6giCxmkkimy+FeHTdZ6hz+24lzsFu3UbXHAwWbAtim+kz7tWoUwDCuWtRez90LMVibV03
s9OTE0S01WDnqkPCfv23N97xtDZeKpUclYjzfg8WN4IphB+xKA760It6EE+vAg6sslhPeEtILCY4
Uo32QdRhD4sEjjub54P8JzSNxRxNbgJXU+8ynehszPSEyuxl5dDi1AscV5lkhXQ99VE3kbMI8ilh
QVUy1qYXE9K5fiRAV0MgOjL6GGRYoTf4n43A3FTs90xm2IHT/tG6dfy45aY7VCkDyOLAsNg6qbjb
S+am1g2mbZSI1nM9RhmFc/sBTe78Kgm7HWfCi6EV9WsWjqKGa5AaRsASsm7bd1npnUKXCxM53zTI
77Gkmb968Gfj1eaXjJQdf892eoN9RwJPsCC18O81xXkHoHW9rpUzV/NkTfGJToNKY6n8O/U/gp3y
AG4NmQb+ohRjIbQrMorHExbrqsFGL4eC3yc69mOV+v1CTYsqda7U3Kustm/djGTSpFqDUaNUmNv7
s59H+WB4s7H0P4v0ac2cjyGb2JiekKYXjqytCQsMiVJwOtyNM7tOjPKEr5DFyVazHv2pRLOhaGVG
87WLyoRqDpuHLeZLjrkoa33bl1FYrCa3J6+jJ7/V3xNnIZQChJxZvKwYAjZaE4fMV2ZZJnThqFaV
jzThXMsUKhts7V+pxPK+9zyGMAfbJb+gqTodEbZFGJ3uAmuFe4/D7u5r4ULee1EtBh9bcw2j+Ola
cNtHZu9ufBxtKXSETdazieWpvDhS+w9bsCl/1kwyTaNvigZTEXWAX7zN8t/Lv3wG6d57wx/BxB+E
F8OAUdaEA/l/kXOG0XbxRG2wQEbzuLgDFSmrE62VEjJinXmf1q7lMpmlsJOGH0t6Vpx6OC8xz8e0
9F6q/ODk0dxRYn1TlLWz5oHLnk5CLNiWA8DqRrYx16q9uzU6zk/7a2dB6MGsTzhiIU00omSXkLY3
uhJSd6oKTQspc9w3uPCrB095lhsz+vGhD4iM4/CS2HsS0zXvKKDnVX6r6sYwhAYS1txJn8cHejTS
33a3FzrLh/Lr8tihbnmzdHQJtk+sq7tZb72rWrEbk48sbF9yJahsTCRqNmxxIiHoM81CkKoI+Lxh
cfc0D5Yp/MomiNvkLGAQL9gJNP3W0OyucO7MynZvbq3xjQW7UGuTkM+U7elqqbUSHoc+YvoRMbS0
Wra3OUa9vgiPvfWOPUXkCzQ+GZz5oh+zUdgV9KFSEg78gDsnyyeW/ilBD6TtAk9pe6QKH83lGlA/
2bWItSalCQk+8HJxYzEowKqYFGa6IaIc9tMb8mXj8fSJrYpmGSaaPDJJbiFsHkgzUgKFO56A6/eF
ldbJbZmhU48DLTEq3y10q679uNFxpRjMbj1VLTSaUJ5hhfLgA9jgL7ku8ypfmsyML/AFtmtYlAYS
x/hfNfqd/HxrFDj4suOVtrsEgFli/p8rQFuk8bUKKi+qMACYCmucfH6KPKuWAuxGCuqam7J+SLhy
F6DV5jjns6q2TiCqwQ/SFDGGwNWkiXwsljkpcugaJxrggWO350nMbF0QYxh1wDeVmRmPTvIktQeN
C2vym6ToRxoNYTF2Tp4Y99bkBeDapsuHhs2C3sEBcQs8X6JL4hEvCnkrhPhAFYDvUWiWd97v1xEF
JXyVXUJkVG9BXgkFfhxRC6VBtIUPWaRXjsqkEhgA4GfNh9Ato1kt2NsNy0Yk0TuxhhyZVCo9JfjN
xOUbhJqEzzlTH8+IdmNPKx43EGDT0Lrsk/UOaUPBvFWdb3GqIMg4TchPjXgWpuyR85DLNpqWKB3K
K2K8dzks0hfLCIP0o1ZrJyaV6vTRLX6GDJX6JZRDQIcYVYCtM38a642Um1FZz9czprkChHqQfL3B
NzQrdtyK7LIW3fUDo5pKTkFMk/BrlxVPsmRbDFKf4rxCbgZA+dTNUmlpBauC7VYTM5YFkM6wgAQf
kvhXW9lkApSLz8wKN03C6wRC66r8yh/YqKG+OjTUsFovJrTDokQK8MgWGIzpNPRCNORK91DK5GNY
HEXIaZzdLIwnRbeaVleFh1M2/3aFZkINsBeVqebQim1r/XodkwvYfRJymSowdoWJn6/gXjWYYZGh
nHpo+U87TYAoe/0bNSftOYIRvEYmlBQPHk/YuQ7Jdb5hXqiv8iaBtaRv3kWfgGc6JF0PyuLIJmQz
sePGBoxGEAi/gTPFAp5q7bYdVvVh+ebZ1KPCkgVP67PIAZMIBdM7ytHOVT5vyhBUSnzHGj7tsaK/
AqD6UoWrkSts4FsZnh9O4M8pkE8Vm26V8YWdgHnDnz87zqQ/CBdX9Nf6pLsk7Gm/k4IQqgnaYV3Q
djGKNtk3QKG8x7u/AfFVjfC3uxos9Lej1HjxSt7yMGU5UStm3a89d3ADmdllSmHXG8oaJwgC5yD+
6ZyoV+S6O/inHAAITWTqNss+CZq3wQ2fSPRm3iMIYujSFh49ZWF6Y5hhATGZ7puV05IkX1gc8Ela
qcxST2cD5iqJ2QwgOpu3pXIdq8sop2UlJ2ii2/Ct6PF84r15S+LX3gLwJ/KnCGF+GUwOWmRkx3Hu
v4EWljx5OFiNNQjpL6/VF8J8mZgV0Yatyn1p4Zb53UROPaTcM7aRopMguRKwhgpbxYt/+eTJW6XO
DU2onCq+kdiW47TN2oEGrRxvPPPOq8/oSOfJtP28+4j2QIWKpNEEkyM1waSHRIK9ySAFcsxROSmZ
y5VUaZHpge4mjt4o3wek/wS6MwWVPMsAu3hEPxAU1KQr/u9URt3MMa2fLlo4iYegrEEYe2yLrrAN
jfOlfFl2WAfnBn0q9dqaZPhtJGkjLcv87aMFcrI8E5sRxgPWXNHe5E3yM7fFaxtQ9czAwy5HBQ7T
gJgBJSPfEfU8e3x0JPGyrdeTDJ3A7ttFutTZr1mNDvkDS1bKipmWU7JPSOW9iMIXgy8z3KaMV17o
y3aq0spIkFtfHwEMlx5tdEz8T/iwPwSqX7cnQdq/VsqDUNNb4SVzr+cYcHaGI1VbX/0HzDuMomQP
8bBDfD6NPr3YWlufkhrsbQfYW7WwfFtn5mraBA8+uYpAnFvNL1nN6ushsbMR1N+vSXjcYN5NACl/
H2124SzQrgKMKsLqQRU44LOU1vbHbBKDecnaquvebNH7p2feemLLqYcfbhQerM8RTzfGlW92BjUa
pGu7s0UvPCSvVvGLI6kKWChXl/Ug0dnDJutwDJbPGIIKIcK+2NPBDWx7NvZcgk1vLArNWzWWN5i0
Z8dDhZ6CzgsX9JZYvHPLyXwjLrgSDXp6EkJ3xaVltlxsSPjIWuSJ5UR2t3a5j70+y53DA5hawRIJ
BflpJHyKmzPzoIY+XozhC5geLbq+MLSTkXTA+Md2N7j1po0WdpbtlNFxKyHKeOmAG5tXoFNxuonX
NfKY106GmQh1ErXt/sv1FnwsfMlB1zi1P2UI7BNRKZFKqOrCBbJHJCnZXGXx5HE1jHd9qZY8pcf/
raU+1iunjRWFwqi0m4Q/8gbHQTiFqXI0Vta3iD7PfOvOLzc9cuejpa4JY/ddtS3kX2TIpZRySbii
XgeFxsoRZG/o05PSNLi9egYTmlUgVS8d+uK+3hIvzh7l7GM7KBHA/q9Nsn2MXkbuM26NH3qxiAea
Dn32PsY77N/kRaam/N0h1Zw1y+Yze0k6Xo7SvXAa3PeIHINvxYjsqA0DUbJAr2qJQ9ez9vPSqTOB
Dhbd/08MfHVAhXHpF3fM+00YOk9kcYkG9Ri/eeixt2oEDZaKzJLnnoqvFxeWkGjVuZfdk5dOu9v7
ExEKEHZo+ZvJiEXLjjzmDtZFould5AIW+q3ME1xdRFAo48yScl3GdhltW7oIIwCbxONHp6pPH1DB
UKn3Dh2Z6TWDBMdTMe2/L9TS7lojLF/dKkQy/l5IxcOXSsyxUWAVpL5ZrB9DtijZUUpLiHlAFei9
Y9Z+k80OmqZhY2yO5s8R0ALs1Ft48o5GjKhCgHF72iPb/y0d1jf95FfmUoxwezzrhskMaOCfFgg8
AphxbFX/k+52qiLuQkjtJScwGnNfZDEzWfMjSThKXVI/arwQ7Tn55JqubDkyP18b3uYJ3czC/KiX
yv+ED9+8d35HV+DzUtygwZY7rrisICcU3NFk7cc8i1jdolvkOva04x34YiSWT+zjbKj39iDgMJfP
nq1M1Ah0h3m9u3TgvvOjbzfU5dUNe5/RyIdK0LTLLKGFZO1jZL2P6ntEgfg507gCdVHVavN3mTHX
IPwxe6Y6aJ52LnrwSvqTlTplUK3PXqyywVm3ukSQ8najZI5ITtibqu8sJzJxPESP1h/CGEy2irf0
tKuFjzq4iUmlE08KwGR6AdQ90uUyDZ7BInDpap0TUFE2yqj+Cmg/RLdONz44miMbIJ+DAxSUi2MS
CVoaEGRDgZX7L+1GCwlSyMt9OauSexn2E56pMGI/A/PNjcGrIdxkutQoK2YRlg7i6f+wNb9Y2gcM
YzNWLYz5uyo3rNjHRcKm7HEbiWcCdoOlOc1k1c55wLySin4bgMGuA9UXa2pj15QXYNFMeJbtfhwm
ar4+eZn5WyZ6Q7DhbN8CKPpHO9TyDPvVgQmrAQcWSBAx1hC6wirnvf7ATJlrz+DmfHI9E026mId6
KH40lG9jMqfrWu7g7s8wz6nIBiamEhcd5objUHUEmMKbsASQjGVhZA6QbCbgAukMJWUtjQs3kGXc
FgiOMoJpGeYNPE8MJgGTMl4eB3OVuQh36cD5wqXzYC8GP17NZ/0WINIk6TBXOsOpv1WCDSwhzshP
zuOsK8lBIWHJFZMEZp1ygQP/cGs0RyCqkD8ulUBTV+K+EZcy6DXjw67oee/ALKZrhgkjW/cAGZxd
eGZowjoQwZjMCPMMu4WX0cMnUwzIo4hU1IQi+ktIpNRZkliY3/li31LBpNye1mMA1I1p7/jq9Rb+
No3LbhHCont+fMEy734+6OiLsjBXts+/ro+qRqYFtjyT+k0RFo619T77Yp2untdxkjuR6be0s93j
vPwKi2VrjYaTCJbKSM0oj0YtWmM4nSWlNLkS2h2rjbGdujgcDPlU8I44Bo2G1oMGiCui9FodkZtG
kOBqtjbv1R/z+321jpGACzq25FPJUSd1xst7U+0GLp/EzuEpptq4ISk5nnvG8OpY7afVlV5aPFsj
MBQKt8uSzd/dHgxVjmPeqp1cV0WABPcaLzC/ehxbi04Q
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IVxyk7XRM4VsQcD0QPYws4xsTeDPKdwWYfreQJ7l1z8C+G+JAKZ2psrNI+b5ecZ2ziPH9MBGr/oY
8XtzCKmjJw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VO3Jpo4aYF9TyVwyAUb3a/oDy8Yhm9ea/9mAjNtuOBRL0qoy0/CWzL7D+bc1SnZvEP4BG903Ildl
dM2y4TNyVTBUaU7Cz+LzZfu9kCPWnmttlx92LcMKLNuvGUMPXmV5jr3PzSFEvoDuCinMqNc8uKFO
Ux/aX6fmBD8AbQfpK30=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qOkimDe0rSU5f1zKvoE8a4lZw1WOOUxh8wtTIN0ys09AXuQuNNCdfu6VL2Xuj0Xus09sBU1FazgW
XpQHuw7XcozHRlnUFKPJg2P12yPJsLRkOqUWtHTUXmH/8s2RglOoEcmFeX9FVh1IRMdnp+D/F4GX
/80OwH0Jtm4eUDa5EFkNoIfhlOG4JOG/JCsYRnsAoZAbyHMEk6qPxdOGDrYzkbA3CMCikTuE6wOm
0j69ZgENzpWR5aludQDu44oKZqgkdMKNm6Mvk//s2aUOTBYWabbSKe/I/+cEp1tWS7+9AAmaVwO+
KwmsZsNR4Ztb6OH4hCq0936o+bycwR0b+Wr1VA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4df1QYXbx3PmA5i1scwSy/ZAJgZ0wNtl21eeCeUI5h4IQD2UalJOUkc5a5UR/j7lX9ToyF2yFHzK
L4EoH+xXm54bGihfoaTvocQQsWhCDObbmBOtqB6WS1/bog7FNgoEObi/E19vJsjPSd6nCCdhglZ1
j33mJRkZed+lVziTR/s=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Rtu5N6w0tnewss9ZQUyM3gMzu1D5Ba/+qJO2rdGgk0QN5Nm+4TaVyiEXzVM5DP8z3mycaRD+z4HG
QXarW6RH4GHKahoLlSY8cryjSJRWS6D7/Z1joY2fgJb8apydMguGWjRZ/uW6R7BEimGxB3Xuon63
ZdpcvKZmoyvfg0kjAjor/DxtP3SP6DKxH3BeegGQKpP/+5EmCrAhhPu+NA21340wcbghotvyYusJ
ErSZhtj+1FLwV2sO7TUt1etBG8nf/yETDQPE7Q+zX+BzOktmY3tIKds/9qdyDt6Qb5WIxLMyaMa3
eyi0SGAuZdeDtK8Os3w2ajEZI+VjufruVqtCCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17760)
`protect data_block
yvvRtu+tA91Rtyv3I35O4K6BiUlBjs7LTFLRc9twWgYZkATXrSpXZut2NlvE8mcC7mB31ueT2vlU
P9hzhGYaJ5GcmScpsC1FKNndMfl3Ug9Pqiw49YT0Xp/AQWIr+q38Pu2DmkLm87YVBi0HN6JMSu6G
rwJt5qvXJYVA5oSnqcy27I93z0KCdBaCW4BhEaXbMLEY+qzcYsWxGhgjRzVfC2OhOSpdpDr2MKHw
1YDri1cTZAVy/b3L8VUTlyQx4YRG+qS3u0Cz3dOLm9nglzh9Pa9XJC4+Lnpli7w7vpvakaXaH9W9
I9Xs/9ShuVul4UrHUMsoz9V5jcPh1iHPT9m0ZTeLUdfod7NEEFDW47vWU8XjL6iEqBvA/DrJKrri
hjJ//n7fbl9gjxGZT+IKqHleRVz+dRiS/uTuRo22UsAcWrLoCdroE0x4MAJ9vC0vScZa86PQBj0m
ixJFhU15XHesAUmaWmkIVFZdUdZL6n63C2nZpQmpBX8G1td46ib/xrjcP1HPzbr1hPb30S/GA95D
4e3ICss1yPb8NZCwvzZHNKYRJlVJ6EOWwDxLeBOjWmUySMUcywo+toi8FWztPmB/Fzs/gyRSBxsb
FBe82kj2NTjDK0dD4XCcU8bGjVOKNJ3KoJmC+0UD0jihX5N1CdPg7+/bvmP+MCdk3ondXZKJzYI3
9YFYkr0RM2BhF57jZwHcHHmFJrakmG38Lap7lsdonuIO5mfOOuicr4JGW8Qijs1+c7VMc6LUwGDt
YKznnHTq75vwwVLxmtGYpW4RTIuqlZmOJwC34kp9oVx0+wFtUxMvQgXry9FwUwb2gSWRseSfbmMB
auDz+22lW+enEoOu3PzG3plNq4oQP2K2H++ZU7HNTNGSA6VpJWDQ1c8o+i7+XEkyIqt9DZHUxb+3
HlbwgxRkMYX88B7lb3GnNDLF2YzkJMgQjpyPi+t3N2MtquCFuqNuaKv0LoD6+mwRceg/hAylp3x1
m9DKQ0DcKuhctFlcx3aOGMXc0mzgjh9Umxn2Ng7JEliL6/L086w36Jar0AAtsKsXZ1NsDDBpiIeT
c9pWEQj9ud2144CtZKOT9/hr1wy8/jpi1lQaHanlWWtc/eb1aDpSY58hPbltVjUTyizUFFWsqQAC
PGoqDXF3N036pR2Ipsz0lKGQE6qHOZ9IQByoJkJfVJQFD7arWnGsW4G4I9tdTj8LBH1I0/XQKvur
lSNx9C6iPx8J8GemXPHqEIipG+GgoeMURYc7ft3GzrBdwbTFPm/qrxT/0vdju3tRDBl4JSzWO+do
z/s/CD6wNYNcDBCSDKcprRdML0+tkUYr6Jexl5rxIe2GBG2XGRgBDqc+wBSNJY7VVfutmSr3NjPK
RJK5NldZFn8fT/rjewbLV4flhMn1tgsE6HhNm8GuRS52PpzP+BK3fCtYvb1mnkFy+e3mwc3RgZ45
5iaZGmsBwnJwI9GcgMGoWSDkSaL/1PrI03WtUczFAidTPvIY08FA8CTdX8Bo/j1vK5yj8spVzrNq
2YNw08dzyQOA6p4yaEO8Raki3qlKk9oCGUe72zvHFj8EIo6DPYz7MTOBMZh7qLr1JDqBA+iyQCSU
UO9dElHR49OYArhLqejxnXEbJqi2McLLRKhJoiH7B/feWKz5mjNEjtWpHgiwx6VhyEKkL6UZ1Rib
ZtiEI9gtUbhZ6XzaYm3TiIRoYgTzxH0j8bAv7Zy61YnOi5ds35hrlF48AdxPXK/eT9RxLQ9JC4D+
xhLyqoQdstrt5DgaM3NxG2mKEJVH9uc9wj8j/rmn9YrBedhVek2F8Uvojvb9UP2S80Gz13xgD5DT
uHlDBG0pjratONtNE06BnMLwZRtD8fOAmitaJqr+uurpGUSmFSP1C9+FHTWgzBTdRwxLO8vYdEOz
WFiLspZhFCxJpRdUt6N09XI21qtC+0+ZgVoJcuL102pig2HCGw+mVSkibp2ZzBHApj3TyyQWeR0T
soE6qVGrU0cCA6w+mgSp/LpLjFALA+nFAG3lXPvfyzy3nWkgcWbCXiItZJY+SdblaE3tEF0j7zRy
QEv4a8Rg+L6tHbS4IhpoHW2u/3VbDszbEYb4sRKfYUA0hAwJaM8jOAxyu4YRtJsjn94Jek1Taiie
hp0Ndlnhy5vlx4q5I6i8Nc99UyR9uhRu8iqRtT7nCYuJSAzDby3Uxqh6srwmKPrb31KF5pRhTgEE
hoDR5pRAhvr+p6GEHRm1IAJTB/vA3Cmck+beIM8DaYRIdaZnzC9N04oH+sWVHExAUc9WW2ZHotPC
yowKFvokfu+7look6EHxqKtkI6qUIsFrQgy755fSnh7+GR8EVZFKqkRCDv0zQz3m3MIaUQ9GzxNA
nVZg02l+SgGZHXvy8wOZE4ONpWcUccgX9k8Mqf2VrJEhn7FTdwr/L68VLWlWyJ51gTID4qsEbmQR
eUcVhXwZ8J6/Jr+tfQkihSE/r9/FrMS9DtCeXZFSTXFkRXX3jwy08FYzVkX1AU3nfi5uob/pWe44
jJ4c+H4TgTK/YFd0U9+b9+hcQ/PKCmyuUWlZMD2jh2m6YaM0tRHT7pTE3k+5NorK0KIzBPhuhR0P
kwadh+BfDa9Ed/g8FI4r9aO+bzUYkbubz1m2BkiyrHNUN4b/jhDQyeuJYsvVZmik7vXZ6GcS1rnC
ZJpUE1bWR8FcYhqQoncmXGI126qn791BoIP3g9UyBSGDJ/hK/eFW6lylhaaJjjVsKepmxGzcVN1B
mCwVpKVdTSGBmK72htH5om7KKA2S1rC5U1UUj3MbiW7ZNwfDd0USkl8imBDLwgYFtoEE1ko8C7Jc
eUprl5A05bpIwcNw4M1zuvcSJzD1rtWdZQl2vo3uekE+ox++ptfYE1O4Xj/2TqSRnKWmvElAWcGk
d1P93oZ45PNjviXZ8GjPM3O0qWdvlgjvAq0xdzA6x0TysB9PpseLW+g8nB6svNvi0GhK/LLkeLYg
V+VOQradYifDOr8PNb0cqid1ncvsR8+c0tlZfcJr23pLfcE3Vqz5wPmHYoK484/vAUmQUEHiXjLv
MiKyjk8ywnYHQ/TOYWuO5OiF3b4XtDucLmEyRzxNB7rY1i7qaj6wGs15PP5RLOMaDOI9Kg6163IT
YHmjt12E1isvBtgqS4df/zN19hcUsAr+Hd+fpoCiaRD8qfZT7eD2F7aDUpS5tVOH7gVSyJWqzQ5q
Obv9Yhw7rja/O45RtfCLUeQNveIdOxbYJdxtkbtNUL4THMOaUooUKNDHf2XRJ/IU29P3yYsch8DL
w6GDueFKcmhtTaLLsoIw5tztfz1OnR/Ji8//265ufazAczEkWZEuwDJ820UjB8sYf6rqgnsGaFMq
k4/RqF2vivZ5ejxFZq4j5HxYIkrT0dvfR14iHiz1gFBjRkaPy0KB92AudlRi5GguJSj9i9apnV0C
9Q8mNjw2IhqKOYuyV9e6QbBpKJ96If+glayPM19wkoNu3wYrQpc35Fto6fYKFdY6dhE8nKPhcitV
/uItKlA/SbBd82Zd2+R5YPNcmQq0sWFXHgntGjncAGogKw7gdfoVMOM8623k3ZSxgx+hl1hERb55
2VAlad1Z2TVWotbB4SU6fYbYbkgvMzH5sJuCqbAAKfcoPFz1nWbbyWa08tpLEd7dFgSfxRMD6emG
vbRwvFQQjTUHayp8X4YhTp75/cn7s7BNav/nMANVwbzv+7PlcCBDE/FAkBmre/mWCARVoeNQi9yk
Lmy+/QFbBCSDmgH9dT+J0qyptUReayys26DpOx3zpnRbUVqoevpDLpdsoEIttEWQIhHlgFCwxqwE
aRk/jq630RhYJrspYYhMKJx7vBModJIEGer5px3GFiyOMr4+4I2Loz4N0yOCB4NxzVtMSM+DMFzb
Yqmp3TY7W03MSy4BUlptWvy4cfrCDCrea8duJ43frMTKFTfbW+IerIgRfu6o1EW2xXm1cTpBK1C5
GDw5N3ENOo9k6+Og7Rv6BqrZrvmt4KofAZpoRQwtrvIUEswUfZzexMH0dWDua0IDEUztjkju9U3k
MYVajimuyW6IXCYU0qQCvsz9sBM2LLZ1x1Vup7fB1Ec5aPwU/UHatOkTm3aX0ZLYdmaCrVM88w9G
XHeo1x2sSQwb3bclHeYGqJ5KFtGY8NkrjA2kOqD+X2jo651hd0o8X/ii6dRA1MaQa3XRL48KOtEM
HH0PUmnhNz19o5YiXS60R4NMyF8DBJ2arUQqgtrBdHpYd+zsNwOO4FJe/HVkB0g9fp75mEMH5PiJ
iCp8PJo1jsqW1yWtRGUFGwq3z88uUmySC3W8F4jZcCA/IVM3H1z/nL/Xi6GkPU3ho614p2M5bRq2
14TEYUDIUMMz5OS3VFeKp3NLgKmCpVj7tbmiZi9T8Yde5BbWfETD2YjKPY4NPYiw4TNz+908oHc2
yTbewFueWvL/NaEUrh1xMwQw0DRkd8xsxovrukJPMeMMIOpJVuHAqxeQFIhjwyO05shLRO+8ICOY
lVC8RDu4KIeHaBIdj78ETsgHAau5157cMpNdCv1z6u/eAEhsPNaTpoYf5z4Ulz5+vbrw+Ig6ywPW
AC3chkAwdqF9uooKaqUaS0uaMYKHDaK2y5UfVCBUcfko4mCk+jjZbqPR4oE/RY4mRKF+S5KVRb51
goeafsPpARmOwOZcbpLNMXGonqOUJEFV7nFBn0sn+mMycGAzE+JXd2B03sI8g6vqICD4805s8/Q7
Q9RvYQCBXt2A6pU5gu9eZBujlJ5yteDEmqSPNTNLHzUtnYMoAcOjjRN+mnEfti3CP2YaqZYc7AEK
EmGhccCK28g3Iq3fyEIwqSG5ZMQqTqoqd2RXD5hdEa8/QoSw8h+tBDysQ5iCskiecYnVoVm2sJ9g
EiFptSQHJIy0hyW5bqu4IBzo173gYuxltoA/x0vJsCyFYs77QhbyJAFsJLmGHqO3cT9lndY5RmIe
G2IsYZVzwYIn/hCH0vy7GSobNYDvEMIvGBaU5p1UTsf1zLoaBwNW5il64Rmt8mWVqr6Q4Cv07zk7
YKXZHTXhEeAgsPcWekKsDPhosTQ1OG/Lbmqe6Xtt932gr1mKpZC9HDG0zXIrXY+2oSE8WilO1BRy
J88nrrr7Yu0oYnF4wZWHuAWIyjgLKyWWX4IP/WRaze8T+DWjRzYC+x719Lw3Own8W4ws2iTfKhys
/AoSQctmniBEUleebvUzkP/54oUfgrmlSFnT+LQI1wpo2T+VfQtutqXZD+Q9onWKVVV4HeEbkZlD
NiZEFqgI7BCHMNKvyQsr+gN3d1+ljxpDWwjLTifh1kNDK1FTX628L7Esv/ze15vf2ojo/9c1/gl/
t1SV+B85OJEVM2ghrmoVc/L4ECZPJK0ZQo5F/4K6TFqIGKCvu6JvWCTXCXXQuvIJWVCf3yQ+xB28
CnIRjnpjYhPYNojhQfb5Zv+GZ7LFqZZ1/o78veE9yuWl0lUlNLkf7AciAMp2qc67QqLSzbmp+IIZ
GRPGcMLDzgqZMu5UoNLRtDcIK4IdO68RfVU+DfGj7azU8UasdLC7EXFxENSmQ/djh/0I4Ci41R+q
wsa+kmx3eYs+rFXPF/gpMof9+m7gcNIlaKRiKrmGwaefZwbiLS2b5ZrIZ6dIXfBst6s3VP1CYaaa
+z49NTCU0GqV80EBrXnRQ63CMSRECEHoQlN/WGzyaldjxjHPYO9Hmx4A4l37hy0X4CBEgwcgcLmn
2IaYATXcAYJj2x+86KLB5ybH7SyK4Ew14BYjahhIhbE/HpiaKw6srEVCnQJsybU/L8kpmLrJFJJB
A7L0H6rsyqypQ0Gw1vYRNT/Iq1SfeeCbJucKyPaC8FIIMxhLscoBs871BAGV6PnoCQwWlPdh7wt/
cV+rFe76p7fOp7y/iWBGEIZ3hi+nWA/1wg/Gwy2n5z+TL5zSsOLvSN/UaFnaFFlJfzsshhbbzRjm
u8HmR4iISYlZfg+PuCGg4qWDzTm+W3rHe0IKKFdTl4GXGM1/EpTtOAqbIDIWKEIZkJ5l8b15nkSy
kXA7m+xG+B2kCr6obeLcnH/Kll+3TvkRO20Bb17nVNUb9o9OAtuAZf0dsN0dkMWVbDBmARX5RrB8
Xaso0jhmy2GD0839FOGPRmjq0itlZIHy9gyGxFuelbdXGBP7YJlreCebt5nS69xLW/ntBMeaobHB
+fuRF9ZeLz6NIAjircenBW7v07uWGziq8CV4rmH/bVbBQVpgNLXkN8+irSvzIih6+uQU+4qnhkGf
6DPM1CIN42m9ynyzhboG0MwLmsmxfHNu6W7pdDbuQK0nD+bziOLzzqrXLBnyPXGnwpO2QuvUEpHz
JbvGAC0fH3+ZHVgO2K75xWmD0ckLOS8k2Z5yXiDsc+mex5g46t0h1hrH4Yyvs+xHhn22sZ5vmAd9
z+TAxX31wRoiRQvb/b9h8k+DfNRbYFTRb2ARM5f0wglZ2CBCHU3UDca46UnCcX0s2i8dCJiik+U8
1YIMvzM1YeyL3p4mMj0N+JIFkUtiWw2Iimbj4Zp6ofh5N27FA2Lw2SNpuIQppGII0um+Cd8fl8LJ
wmvWzSxiUir0Ax11Yq2EPE4jm3nKtv2sY0E6lx8WJYJydjXzqOwe7I/q8cblI4Vw7LJj+vuX/Vac
5mEUxAfQSPmHwmPnz7dWxElLo7zN511DK5ZEC8GBtiK9/m3RoIfI1+3Csl/GLaL5uWLV5jg3nmav
Y0x1hldBRI4gGM/8vCOKB1q8BY8TbeB6wETtrgJDpKK2w6lzrgVWA5wHTPjCuFeJZQKurXZeL80g
JJpIX8UxxYd+U6Gg7ji8gqW9cjciYoznCFRSJAcwiV6/RLQ7TMkMWTU2UPbgRRUhP5AJaTlsHLBG
kDpRv5sUys85ONbc5+pksLhtG+6Vd/mWvnomEBms1/e+jX8+Af6n98WPo67PSdCntlBBB0GpSw77
A58uptTtJh3ZnWGQRMSuQLMvad/WJZKosSXA1e4gAi8brVgIYmbIc2kzpFVAw8CT8ZJVQt0dh7lh
8tVc9ifnMjHMk7eBB/kSfTmYqiH66g/FPPIMThz2zJc8uB+JcA65L3cTruK5TAIZfFjQsRhDD+jo
+IQSPEMe5sSQGn6lLvuEYseLQbSEswNwE1xM0mWOmQTgipmdzDR1ApQU7CJ3glXHI7CVSZ+Ptc0x
tMhQKU+3nMUBMdbrbWczDZr8+LtuVq79gy6RjWSEvDiU8k/C2jfU7gvAAhYeQmEWA2ZDfrBZGMUe
ctwS4RKrBsgrdotouRos6i7rnUYet3BfSROrkb0kSdMZRGxAyAEEU/HXaAAC8PBph61GdBPOjY2o
ucgy4/5j59ePvr2AHV13YPvzcUThetgzbOE/iQtfdAyChyoVx/t7MUXlzDXK9YyFeO5akcWlv5cV
/tZmdn+0Ip2LqVVRXFEBSoKdQdXJdPtlxjfAelCI04ov4YoJ58o+t0nhwgO7bkbIx87oHNgrzQ2M
F9Nx7WUW7kGIwr83dm82aDD3MxmSYxoppKine4XFBSQuB5OgrdtAHhsoSTFIgdLrqVtjPempXbGk
sAGCyeTTFU5G+XjRzr/5F6bDtFizNprxJBKDaht1ZHz7ETvgFDqUE1wXMVV/4EQdWo3mWO3IzFHy
MHtIRlXUch3GQNXGHB3VG9FfABO63ISUv+i8letcphRuJGaIqd6D140yb1j9b65V/pllsmcXjxZI
Ah43oD+OViZ853FMzqnn1m6QUPSsMZIRyqrAz1NPtluN+CJrw1FCZVpiTakwpdxU24wYPLdzkJVt
MpfNjTp4CfPgAm7JSZ8uNwQriV6W+lMhO/nOlWDmWdpkvsTuaEmfMCDUgnSLOZS+lGvmuwQqc4c7
zpaP6+TmfafMbg199BGBGKHnAzZYORNMzqGduqQH2rfIjXYsYhgEvrviZ02MrjLaQZP6+Ut5Alf8
E/kL+HVFFRph1szoSkmJ7EBXybrGUR5qMCQirKzjN+9O+mZGlpjLRjEm9OvwEI2YBAdnbEy2PUIS
EppQU9iHilUApIhfes6nYf+wBw90smvQ+ggytyPZpyUuHI4qtFg7oOfeQJsHmMUTERb3j27kJedP
2tYr9qiiRWvUkdwJ4KJwqWf4pQgGognpwYEamf+1nPv2wTMMQK8Xx/yjdn10Y0/KWTAYXLQMmYjz
1frZ7sNr9m2G1bncTeAGzAAYatbj5nvolqrKxgG3z0xhGVUVc40Ki2Nepm+7jD8G0IY0ml5LLddn
YbZpN/8M3Qhx3Xq5oGiH/2TnC8sMX0iYn2UCyLxrWczitSRdquyZOivyQrbiaox+Q14RjH2RZNd5
aQF0j+++AlFnkxA005oCTlPjkpfMTIc4RxeeLQJ/tOK503oFkgsrCogo+yF12lnKy6igucSzbMPn
3Wor45sypUNSbvvkuBCYT1dqOqZXmmu2OwrJxxib2arzDMD+Od3/2YCFIL50cnXvoIjhEB0DXR9K
/K7a88aV7qbJ4DHBzJ3f0XIdiFQ8SQgz7J1rbVBgheu6FymoZephdjJLqZb90iDDQWVJmojtbzXg
gFOUIz5M7rwsn1szvg6OQvvyk2BO7F4pzU/gosxylIy+ZgksSmVFg/qaV20rZ1k+aSKwrFaoQyeZ
RFL+1rHpj+IbGKJ0T6azxeZPrSBdULXO4GIJdvr3Qb7m1uZp95FUpJBDu9qVsBeW+e88fCT6V8gX
VS6NTuR49358rzHdu4P84iHiJvQ86U9hTj3lb3jjwQAZN8p0kHLIhJ/OK3HNXw+RTjLj3vFhUR/i
IRh025GWPgCvLKW/Fcjs6l17Yf4iBubssKiYf8wlCs3fcp9iubVKMP7pRHwefSdGrCymu6kYmLgw
mqeCa1xHRtdyJWo9Qe40/RZF/z5wrG4kAL6/QY4JsNK5IuaqdL11AZL2SCSWi+If9d6xMChOcgdO
Kz8rL/ul1zVN4v9usZdnQoWuT37LkO/XTV67Fotcg6wt/2SklpnESLjZ8scuc4uMPNBaKqJxjusu
l1vSBAc0RfX+94qdKAB1kZkl5L/0wR4MeVpy7u7MCHssLTOzpzCO9upNisBXiFFPDC00CfVouYZN
XXF0RkU9ILKEeChv27SW6Gi7Qy+jku7OC4OkwVTtOeSe3uN21fa0MxUAVDqDcSYih33eUdQ2UgQt
L6AkF4QraqjCQmkNLaNY6/FADaaIph2sC0y2v4R6EliBhBDUC/ueMaaLEicWDYdky6CenbfyuZOC
Uvu3Y/IwIV5G1ioj22TVv+/LM2NMXlM3efeBXVFLlpk0glMoySXNMXgPIwpcUbWKr9MvEuUqvHfU
Ua+EPFCKPWY+MPtNhxODgEaf5SD42ilmAXixVxbfQgZT8KDy5ESHSevUnG4beDCiUOx2OxSZYEd2
WecJ3ZL6564z/G4fc7Om0ZIOU9ng5EgK5ufct/8wDhJxhrKfWKF8oGMAz/NIeDg+KDpnnOd9TWC8
m1C/nAlPRFVJESuKzp85N/iFta4ERlbMXC3KbBhJx19efD9AzC6BaiST96FqCaEQ0gbAZg+5M0vd
sd4uARkYKVZ+saEmK10NttpOf8+fMTy+o11z0fGYxK7evc99er/Gbpf39qG9yEfmAEVRfphmZPIn
SQf7u15eABhrE65ulYC9cW/1kD9cckhW3Ca6Fmggjt0dr5f0xyY9FGPQPcKlXF41lN5BHyQxsQIA
iGo9RSECpzORa/a8M6ZNFsEFb1RNk7PIJWUUTwA3yGJ86kp56QxDSwHJ3pphqBtvncSbkJA4qxYe
VYFrqoPM2y9CnuLtBx77VYq0P4lNlDZj2jk3mHJrjUoyGQJcNWMrbXeusyvrDBumKKKJuoCp8Ji0
/RMJ+8HFg8+R4uKqYvpIJg8NyYQ8vYA5vtYccRW0jvZP/i0U6PWDFr9Jttd7mvkTVOZWVQzQwIa1
CX0sZXUqWjeUdWRk0PgpbprIfHUzRGF/71Zzu1yRW2GCnx767EQ5qKMpDIk0GPjYaqO4xoSoi9aM
1yz/MP17scsZFRtDTEX3mlGXuzvOXzoZuF1pv+cx/HZyvxTWVigsZvXDBZjLh/wgy0creA+fBV1k
8fkV6zAuCk5dk5WqKFfYd+1UeCPMcZKIBp4CT4CSOy97C7PdZOfTtjBE2N1HOoaQ2ZxOQQfwlT7T
fBNkY0FZvjuckL0I+G/gCuS39PwVULFYbFIzpXBM1Nbej2d5BRC9Qd2AZu9sxMPtcZKUu95Tnwhz
RLTAtWmI3jpVmutYnGnpM5mKwhhOdMO3VOC5v3YpF592DzT+6/6Acs5ks+nnzpA1Us36PVKcWGkE
M1WjUqhQAuy5AFtL3rF2Roudc62UHxBXUcrRUznmTU0m6HWy5ij6umKW8aSGQEAuTFkgHG+/QK3t
lkny9IyYFmqLI8pYvOJTBRa/mUHj/dj/6NbKzslOo2YhiygO1nVPUAcgCQY4cgBaV1HZAFPnSrue
xDDcyoDCQ9XAq7HtK2PK5zi3RkeZ2APBYNWexQi62G+cTV00wfk/mJEXllv7M1McZl6EYNB7w7Wy
NSFsKlLu8YEu9N+Kz6RKVjxTNxRK8PL4e5PF+lnFbOzA7pjA2WZ8s4rN/GBsDQxj+iRTW9eFFwkI
55pwh0HyA5SIW3FjpJUf7cIrlGZ4oEXT7+1t1T2BK+cZECsvU3yQPWI0wujjI3BHqX2Avcr6Gfjj
Zt/BOCeLm3WPYbVnr5JtETvK2x7GxSyH+9LMO852zV25Cd+48P/c6S2Kw0ca728Ny1Y6KGbL3qlP
4EvN/TZ7etw5UKea706IUXwIQVwpP5jQ938y0oHDYwffAWQlBszHIVreDFPDhRH7grduFfXwkAZq
Xg1+sBIztw+hxqlMs53QCz42G+g9RWycycylepEsvcSk9fVNm6VmgeZfgi6X66giRnNJpU2PIBAF
TmbPAcrMrGqiw6Igp/NT9dLv+HdaubjRbMktYivcwKhtfvRJxOMuhYot4wWlUUavaDQbJmW24VmJ
ZwCVPPi6rQ4Nhst/OnX8HNiq2U/gTHWXorogGqfyr8Y6nwQ1i/rMdmxoA7b/GE1m9P5/B6xamFQg
EwXo+CxJrOCPsGlEdrtI/EomayDvxVj5CfvkkF3AfbS1sQsfyGGG1tUvsuzyG6HbCWTS0DgHLYKw
mLw/kac2HudY+pRGugwjN7CsZhMmmjhzcrMq0IOLuASVzEQ07NRtu7qYo3gXq8qnNgGi3DQKDYrw
SYfT6Pwt/XDOLV/1Nwm7lrkBfprfCHgW0qbPVabJczWZCD+LcxtBQw3gU2094NvU7pb7yPhlgrq0
cS5wrnWHRgkSVTP2nTdECUOf2uvdv6UAYuKZB+WHxfuNgMuJy+NNx5KfDuofgKn+lYGw6REYH3Ka
ZOfYztF8bAdIPEvwSawpzhGQAiNBWeC79fEj8BBPy695w6r/wK/tqaFZeWkyTtf0I3GsKFAFjoZf
KzKY+NxdAAJi0qPk4lVk75CJ8kptfpPfFywJQmfyBb975TcM5vpsuS0OLQ7PPrjlQ3gHCKvA+H4n
QPQpKtQRoRv3axSt2d5bX+nHX7sDe0XLK+YohWnf6W2r8ED9onbhdOXu/KX2OHKoCbv/dCpO3JIs
yPgJIlcsES6Z7VNPf7AG2iCOhM8IJc2rkfWNF05kCosrhh9zj72ovE8RIohjbE6NHLiuUlA8oede
e6MJsIbj7L6BcoK50YtZJ47mkqQ53XN8aAc4J/rI7owAq6S9g50tYefm3L0nPbuCGWHERzd2gjBj
eixz+xrcNM7tnJIQKf3BHG5GEXQzMr8loXRSFArDmZxS3+X0oRJlIt5ZBx6wPaJLw/47C403FaVO
IQ7rKIj1J78aFfPu3+RUWyAxXdSUla9IOrNugivXxl+/pixnEdfqFhdGh7sINrMDr3Gva7MydLld
aT6Xxy2ZXoCIrn3QUJYKAx8iSWuYEwP4DqSnDEcIzqyptarJmsEalMCp9GrYMqhCwNqKhm7QFRVH
EJZYkgW+8UMhys0ogbrtFGbOrQzAPtBJbeUFIniW3mJQMXc79i1yiE21ixQ8ixak+mrYSNslA3e6
hUZFTZJoh5xpuHQYY1nBk5twjasanafpLNUSwBeNbZ44LL0/WMXxVmEI+OffB5P3t3OhAtcLuUmq
dmfqUu5wfet7GcTzjZMame10OMV+omk6zhW4JKpGLlaOc5wx6/zoGhGWuaT+cWFv7j06y/IK1Ge5
VwYmkjNekZd73ikRPgWbiiTGW9uE4WwlB6bawr+FtFUk26pt7kv3iGZfcaexkYk3gFuoCjMatcxm
5iJBYNcSz8AWR2X2L+XKSxtSf0hQgxgqoTL2UfsFHmKChrS4gCUThdVlzTQXUx4eyHaIJJH9DnFE
M5L/7tl89MeROUUOeAtes3QIlHeFFHBL/Ji3cfap8ryGMN1/gtgWdRFkXnoX+G6hQhXwma8qXikA
LWFDlKPRFEnz45o+6OCrGzLwe/otDBFLGfQ+GWVpN0kV/uZQ75Sf0e/PsUXpFnaLewiSKank6gwi
8yF+WH1FQE9YQ18xUl4fwH8mizCAxcpFYsA0t+RbSUT3n/4OMU5Qp9o7PN7lBGRIO5p6cMtXRnXC
JfW5MAwmEbuYLebmtXFTuJDEJn0GyquYWPiwpRZnv1ziMZpHifvHl8+OztIxJd2mYoB0qILovXrv
p+sSoT6d+Qt2nOaFyPi/m6CB3U6EZTDb/lY9CEtizEw/HAA/6VwkE8uIX7K7vI/hr2H0tduoiiNC
Z7Qlv61NGDw+Zsk5lf/EB3d4KiMTGGR+U3OwHtOnm6VYC8rcu1iaHeniGKq68Pd4RNabdW0SEWBG
SCsEB5twlwDDXXKD7ZjGPdrzFL4xeUQOh7FvLbwmC9sr/yhddMvrFkA2V9wW905QTisuA8OW3JSB
AUh4iRU5p3eIXnK4bV5DGLg5qrBMXKp7ITgTUsrz1GkN0djgyFC0XYoOcjI7B/yHlOip+3I0y4mv
lvXPbxrefN6gyKaXEaeKqc8lkTrapgWmcul9IqE2dc62oipP4yfF9dyU9mxlW10geK1g24KEyzGo
BeRphtKG4Qmo+nfR7liloRHvowONq++DWCDl7U64lFtPGM8DVJ8L3f2O4dZ63W280QNqOHfM+D3v
oYV1BCKRuIDzGPh+aSQpVALS7SpCpa9vz5n7NadTJvhdFlHr4KfuJX3Dh2oImi+n71N0Qn84euc1
fOD4vRyV2dyrbvpf8ZyzqYuhxBpx4gleNeoUIVPfagb2FoQQ+bskrJ9Fzaop3uYeyYjVHHz9Hn/v
kD96iS4c3YZAm2tkHGVHg07+rB7CjCZASOlDUuBZBYy/Vf49Oo6ZIbyPX6zKW1HIZX6TCXgL2RMD
Z18i6bS4dVWdamjHoVM2FEWy0zWmP48ZzqIofGQ35eZ/S/W7DX9ElshVXWSoz2DnttgcYeQP85Uy
g9m+ziCUZIcadRW964AoRUA3+eqQFMd4s3bDuqBW3XcuFpHSRPXh6t0Fs16Zxakn48FFt53gPuPn
kWccmrUbXLvLcqhA8NtpSsiryUclKgessi+7wqGZwaOZ/56iVBpZqOJwABqb37gDS4naRX5Lhm3s
m3HaTaYcXMsCHqn0auTQIir/uX4q5UPZFQ8Bz8UC3UKxfj5ULvWsnpZTirNjNzizmAgQT8RVbgzU
2G5ppcdSvbuZsNpQGRd4Pb6lyI9TgsK+1nbLlHGhemrdiL/34MiuObwmSLc73QRRBxNgFET6e1Lv
o6xWN/l6TErNc+6EiEwrxgHsEDYFHeG6qnW1ueS9Lpmo4/z7e+6wy6Tl/b5WouFHRr5e9BLEbuxz
42BX4dBB1w/PfHqyvQ9VWKQ2jLS19zH4agGu55yMenuP9MgLtErIMJT+Bl4ELPGwB6MlUUqTZB3t
VQC2OppjbtSjETZroDDv09xkwKjiHqEFViOwEy3sF9EdAetnX005D6kuc/K3fTbQi+m6fMRiKN2Z
BiUYhf8XENvED3ZMQxboABD11DmJ1e9Fs74DiyxWCij5drQwOkqqstt1vqKAB5y7Yfz7BEDaiFt4
N/hwftM3GyDIag16EDHX9KUEehn7+WAQVjm8M9q3X05bEsi+YJzDYvQ1YUMmCywjgkrU+we6Zlfj
jwHfaDlARpdR7SkNfEHejmsi+v6oKmporsGFi/PV6Zto0tsGqVmsM4rG7ACZ9Rr67LZv2ZBYmau9
YMgEVa7MgE7o+XRH98+6g76U+vPo8sDSXBzjLxrUWj7LbaLAwHwCiaHAk2NE6S11a38XlxU9q4Rc
V/ZeXX8H7FNqwpWafLtSUSFGjVEl2UPuR+LqiFTtg5pDbXTI3RUZ/1FTQXdKgs8mgkiZobQpzFE/
rrjhpfu5U2VFgUt175KUgZwXZkH/mSNkaexiOIwbfcsZBAy/tKw0ZMHpRgmxVxs6aDNEnWMppYML
mirp99KtxeiB4YkVvhoCIgRH9rd9f8SjF4hpmqeG33F+I/8aGa/B9TDn9mIOB0MkA9G27OhNWHti
BhiDpachcuiKHNRXtROW2tZ6QSKltulLhEE2tKS5ySwwxUggM23fjcafEriJsOg/75JPoP0f7KSD
GKya9azUZuLQNLPDToOlCvYyOgxC7DwAJSzAineFxmxudrjNaala4ME5f7ber08k0H7a98KpnWhr
7Wj2/ZJ+vEdRg5LF5JobYzKvmpaM7hGgOO0Y0TDtIOO7HUt3HbEwZQnXW67gaNwbS1SMvRGswaYx
K6wkNU8q8NKtgBuc+BLolYfLBZRJcyR4yNDpU2ZjHuWIT4ts/OFFXInD84SDkSXjHApALHfZxsnt
cTfPbSH8fDmCJm8Vuoqw1xgU6RGcrAVPTlI/Bq6t7tCPO+YaS7Zc7owdZvEsNMbqoZsmDCFe8doV
8cVthfoNVR0f3SFwHIhWyLqcudCO3w5Kbmclzjof/qugz7XI3W4up1D76MJKqi3dcnruoFlabFxm
tSwx3GSlL+5B2O2YixhTq2xSfw1sszftRCihJ0NMSoRqkcjUCZWV/isTBo0MmbQfNmdasTOjZ7ew
2BGPXSHQT6V3s6XY14QEqIGMHPF5erZNNQZhY8yMaHagYfd2U+nuwBd7aS4EyGQFpNTw3QcKE37V
hGX17EZiG8Wq6MY/44BXOfTCtCeKo/byhuif/pVMsu+ca4R5zGuY3CiVWYEsPvzxF/qKifpxZi51
XRmtFk0dvxCb9LZijwdOxnyH8ZiWDHs7mJnDVpcWUMPZU8IvqumksK95mbWFPl5LqmMFM0jEs8PD
mTfV2GTjPFDNIyUlS5wgr5mAkFV9aGhFTJyxgym8HJTFTPnH5yHrrcc8JJLtN4hU1di3Xn1fE3uT
opoRvS0bdUapON9OlwVhd26jM7wCZBYB6trMJ8Mp76myBkkv39NINwvcNz0C9PjTC2KxxPuukWtR
w/yhSCjv3HZENtmeUszZgrIUGEER9oAiD+owYoWYlewK0ILXabNAqrhmEBqBHrr9oqgbcYRDzuYy
tXp0TFqhsCtk673OJdQGB6Oio70EYcvfK2+/+lQbm8RY3MMrGTIdFT56B/KY7jNhS0GK2TQxwqhs
TRZFKV/ZJk4siqHTytH15d/JDe5gR0ZT6YLiWctRZ0o7rDFAuWGOts2T5plZkYkKlicuij/brRUE
VoPwjXc21Asul2nGZ4oqWITvNNvqsSj3pZcib/NkEb/ywxjqeutPrWHdY2z9bYYV0afl6iN+OJPF
mRYM7kLjlkifzhHkjMHeNI/3PFm0mygSZsjtHDrFRcYjNY27pFqwHt2ydv+Y8I0N1SDHvn9BLNJu
oFVKeuo90KYeeut8r9DrRTYqFOonG2OEQDDLAFRufZ3qQCoZzCVAz2808ZTxpmyZlUrqqRB5eNoR
fjg1JW2zKpsRpYXTmNQeMRdldk+Feri5oq9cGD5YRVbI8qXrgCFVgnHaSb6bgNKjoxu7ljGDhDlA
fyljqWnwjpwLnJrnLEEPxCA0T5/et2QButOgW3nnwmS1l46RTyIuJvDC37QKPJAoZiXW3NONxQ4S
VMkIxUni4WFNp61+I8ALmhKWYBMnSF2olRUJgjx/5EoFbnaRnuG71h4SLeOPIDGWQZc0jBwrQoy/
p39/L/g1wLZ3FqNDV7qggQZ0GMY0PqS78funhvJ8e59DeuguR3c8Qw2C0tcThu571K4wpX/OFbnY
beeizjT0zdkHhRSex+8gBUGhTbaSXFA+qwXR9xCY+C7zYRTKO8Nx+cPPqtw9pP9PxBswmjqhEKt6
3Ck/ADyCLZdGREp/A68XVGVvHb/JvfOg35vhDTnY5YS2yaSxtOlTrfweIjcpHNm/KYIfyfc8tE37
vQgFgsHKTN1WfK5wTNKf7aRiY0HC8102JHI+A45viX2RWjDbdLJq2Y7F5ppx0BUGXajkekHFHtTP
zGH4mWnc+ZM9cxpDbZHg9CWY03g1SIePCaPv+IQWravG0Y5/FjoT60o3H5FyFBudgMVZ3cp8VzJe
LvD1NXLx34aC55OogymYf2wimfHqDswutWmnj+tuNMEDOInqQNq9UcHM/OyxxtX8wTTT/NRUFeVm
VeKtfofxOPU4GgEr7q/dgpmmyUwpJdTmUIWgEo/EFBgHOpfX6wnVmKNZLK/35u6h5zONTzL/dQna
H6zFQ6I+cQKT5ug+al7l3k03OO7iBB2zXBSdPjOWpTtDodnsbHMw86WcpUsjoqFkiDJh0K9pAiTs
yu0YtLXYhpLRc8vLx+nlNPLnBlewheD6Rsel2vUITR+Y0R+LTIVcFizL3RkCWpgT8Mv7GFBus0bs
tXa7x74NoVvDOv16dK5Bp6co4kem5MjsBMqulNnb5qAiSRSAHjJVEcbgiN/ejphUzKhhnQ2rLlmR
J0srKz5SDkt9GoLIIQYs5LiQz7IybWCgpgj6AsAgzJv8o1wGzGOJFcuutKhU3byY8gX4mvT1mcoL
+oV0fltqMUZ5+7fYGYXRzx+IoKYTulFlekV7KaIy6pn9anlT85vVRhfq3tNZZRGuUALVSiHKp1Bv
hSH5jlo6taMLCDODPF39Tqvftq6OemOjXklUiPQyYpE3hA7qrG4TTmxYZzDSMPUrCpTcgg6vjYA+
icfYFMU1pgr4fLmYJ0fROfPHuGJh8j+aeRnjdDL1S9T5mRS4VQFv2nBpMet9lpa4++KbevKGFfwJ
BO0QF4h8xYmLMoxmJE4LfilYtw9dGxV5baelDnfq58HheZD2ds1QdE7sNtEpXV6y/daqe+F0IrwO
EggItvtulBViDAFHzzEs4Ors+9e3U7TiRkh+FQouUA4zwFshY6xGA6Dbnol3ZBzdaBUiUM72DESu
4f8i55WEiA1ksZPV3YoWd/4fFxoy40yp+YAThVsC3PUgYwIJd+HeGGy4QmzfwbeK+mDAR9fhkgPx
nzDL3LV2Gv3HmCCLPBRF3HWk89YHpBOvD6r+uOVfqkM48561HfV7l3A6apzVHxEOEh1IyTyiN4f6
3KVzCDqCvavPKeaSnkFs20XLbL+sYELy1lix4/B4BOvvSBa6muSI5EwkO9IYHRp4SldDU/BoT6Cf
qRS1nv1bScZ42MttKPlYo5C+D45g6wpNReoA61TtaIEPBZNYtLw4TsZyYTF8v5ZzdClRynhRzcCS
TDxMcqXxYDSNoJqUrB7zcYe4AU3uO+Tj6wXoA39LLbsKtK1EY16dK5eicLPwSoFRhW+yHzcF2R0r
WPJGyuHI7ddZdu81doAYgdtje29f2PoQ7UdSTUx5TaBtDIJ3Rj9hzUirGokvUqbl7/aQny41+3XL
F7yI+f+1hfB0KztcysNAoH/Ef6mEeMnfNIZ1MWfgKXi2mHySkygQ6NWZ6vvA1E4qyMJXH6Ff48/K
gOLCxf9q2hiWqZQnp6Xn75CfUcw3BVuhzDPyLdr0RuUnInmBo6zzYXmuhUgWD3UZOwbOLMbQde1E
4+ppigWbA6D8yjjDH5d///Ez3Ge5UANdGKtn5+zwt6sVz/UnNbLaIxHavGC/XYYHjVzK8UBa1goj
rRjxZYq+/vP9jTUVM/We05Tuu6Vhr8Xqgqbs4LxdLvSY5ZRtfkiZ4ZCcUX6PAd4EH3/mr2iiXXwk
MaHxtETB5c92jL0MYVhAngHcoQp4PXcVgMM53uyhUPz7f2ILQV2YDlsJucEYfDq13cpM0FlEQd0h
5mhrSC7d1cT9pzwN/S9h7Qh/HzA8ELwUmuPuJDo2/TpqVz3rFrdQd6zrjucPEC8bNXyMJ4KKbI8D
jSOb8qPFWrNmF54vmxSvOh/OuuWoD9f3nVoFgkV+u9aHOriGCvKVf9fo+9RKQjPtDXcFXUfhU3Cv
MzmWBqGndqHMPSFCJwZft7uzO4LOPPH0VfFoxWhRynQwCPBocMx6x0YUJV+M3EFU6Vu7E3kJrFsl
y1fn4yO53dC25b8g4zcCCiBPZyfjr/dEPpI56AfsYVso/JiXvsCGk4Q44hgxk7E2o05UqQCMycBS
ygQjxTdflOik9YO+XOKbMzwwOKB9IrJf7iEl2lQF2K+TkGRUH4+zgS1JhcVqHPMQR+DJxVpWfM0M
H47wPKt6giCxmkkimy+FeHTdZ6hz+24lzsFu3UbXHAwWbAtim+kz7tWoUwDCuWtRez90LMVibV03
s9OTE0S01WDnqkPCfv23N97xtDZeKpUclYjzfg8WN4IphB+xKA760It6EE+vAg6sslhPeEtILCY4
Uo32QdRhD4sEjjub54P8JzSNxRxNbgJXU+8ynehszPSEyuxl5dDi1AscV5lkhXQ99VE3kbMI8ilh
QVUy1qYXE9K5fiRAV0MgOjL6GGRYoTf4n43A3FTs90xm2IHT/tG6dfy45aY7VCkDyOLAsNg6qbjb
S+am1g2mbZSI1nM9RhmFc/sBTe78Kgm7HWfCi6EV9WsWjqKGa5AaRsASsm7bd1npnUKXCxM53zTI
77Gkmb968Gfj1eaXjJQdf892eoN9RwJPsCC18O81xXkHoHW9rpUzV/NkTfGJToNKY6n8O/U/gp3y
AG4NmQb+ohRjIbQrMorHExbrqsFGL4eC3yc69mOV+v1CTYsqda7U3Kustm/djGTSpFqDUaNUmNv7
s59H+WB4s7H0P4v0ac2cjyGb2JiekKYXjqytCQsMiVJwOtyNM7tOjPKEr5DFyVazHv2pRLOhaGVG
87WLyoRqDpuHLeZLjrkoa33bl1FYrCa3J6+jJ7/V3xNnIZQChJxZvKwYAjZaE4fMV2ZZJnThqFaV
jzThXMsUKhts7V+pxPK+9zyGMAfbJb+gqTodEbZFGJ3uAmuFe4/D7u5r4ULee1EtBh9bcw2j+Ola
cNtHZu9ufBxtKXSETdazieWpvDhS+w9bsCl/1kwyTaNvigZTEXWAX7zN8t/Lv3wG6d57wx/BxB+E
F8OAUdaEA/l/kXOG0XbxRG2wQEbzuLgDFSmrE62VEjJinXmf1q7lMpmlsJOGH0t6Vpx6OC8xz8e0
9F6q/ODk0dxRYn1TlLWz5oHLnk5CLNiWA8DqRrYx16q9uzU6zk/7a2dB6MGsTzhiIU00omSXkLY3
uhJSd6oKTQspc9w3uPCrB095lhsz+vGhD4iM4/CS2HsS0zXvKKDnVX6r6sYwhAYS1txJn8cHejTS
33a3FzrLh/Lr8tihbnmzdHQJtk+sq7tZb72rWrEbk48sbF9yJahsTCRqNmxxIiHoM81CkKoI+Lxh
cfc0D5Yp/MomiNvkLGAQL9gJNP3W0OyucO7MynZvbq3xjQW7UGuTkM+U7elqqbUSHoc+YvoRMbS0
Wra3OUa9vgiPvfWOPUXkCzQ+GZz5oh+zUdgV9KFSEg78gDsnyyeW/ilBD6TtAk9pe6QKH83lGlA/
2bWItSalCQk+8HJxYzEowKqYFGa6IaIc9tMb8mXj8fSJrYpmGSaaPDJJbiFsHkgzUgKFO56A6/eF
ldbJbZmhU48DLTEq3y10q679uNFxpRjMbj1VLTSaUJ5hhfLgA9jgL7ku8ypfmsyML/AFtmtYlAYS
x/hfNfqd/HxrFDj4suOVtrsEgFli/p8rQFuk8bUKKi+qMACYCmucfH6KPKuWAuxGCuqam7J+SLhy
F6DV5jjns6q2TiCqwQ/SFDGGwNWkiXwsljkpcugaJxrggWO350nMbF0QYxh1wDeVmRmPTvIktQeN
C2vym6ToRxoNYTF2Tp4Y99bkBeDapsuHhs2C3sEBcQs8X6JL4hEvCnkrhPhAFYDvUWiWd97v1xEF
JXyVXUJkVG9BXgkFfhxRC6VBtIUPWaRXjsqkEhgA4GfNh9Ato1kt2NsNy0Yk0TuxhhyZVCo9JfjN
xOUbhJqEzzlTH8+IdmNPKx43EGDT0Lrsk/UOaUPBvFWdb3GqIMg4TchPjXgWpuyR85DLNpqWKB3K
K2K8dzks0hfLCIP0o1ZrJyaV6vTRLX6GDJX6JZRDQIcYVYCtM38a642Um1FZz9czprkChHqQfL3B
NzQrdtyK7LIW3fUDo5pKTkFMk/BrlxVPsmRbDFKf4rxCbgZA+dTNUmlpBauC7VYTM5YFkM6wgAQf
kvhXW9lkApSLz8wKN03C6wRC66r8yh/YqKG+OjTUsFovJrTDokQK8MgWGIzpNPRCNORK91DK5GNY
HEXIaZzdLIwnRbeaVleFh1M2/3aFZkINsBeVqebQim1r/XodkwvYfRJymSowdoWJn6/gXjWYYZGh
nHpo+U87TYAoe/0bNSftOYIRvEYmlBQPHk/YuQ7Jdb5hXqiv8iaBtaRv3kWfgGc6JF0PyuLIJmQz
sePGBoxGEAi/gTPFAp5q7bYdVvVh+ebZ1KPCkgVP67PIAZMIBdM7ytHOVT5vyhBUSnzHGj7tsaK/
AqD6UoWrkSts4FsZnh9O4M8pkE8Vm26V8YWdgHnDnz87zqQ/CBdX9Nf6pLsk7Gm/k4IQqgnaYV3Q
djGKNtk3QKG8x7u/AfFVjfC3uxos9Lej1HjxSt7yMGU5UStm3a89d3ADmdllSmHXG8oaJwgC5yD+
6ZyoV+S6O/inHAAITWTqNss+CZq3wQ2fSPRm3iMIYujSFh49ZWF6Y5hhATGZ7puV05IkX1gc8Ela
qcxST2cD5iqJ2QwgOpu3pXIdq8sop2UlJ2ii2/Ct6PF84r15S+LX3gLwJ/KnCGF+GUwOWmRkx3Hu
v4EWljx5OFiNNQjpL6/VF8J8mZgV0Yatyn1p4Zb53UROPaTcM7aRopMguRKwhgpbxYt/+eTJW6XO
DU2onCq+kdiW47TN2oEGrRxvPPPOq8/oSOfJtP28+4j2QIWKpNEEkyM1waSHRIK9ySAFcsxROSmZ
y5VUaZHpge4mjt4o3wek/wS6MwWVPMsAu3hEPxAU1KQr/u9URt3MMa2fLlo4iYegrEEYe2yLrrAN
jfOlfFl2WAfnBn0q9dqaZPhtJGkjLcv87aMFcrI8E5sRxgPWXNHe5E3yM7fFaxtQ9czAwy5HBQ7T
gJgBJSPfEfU8e3x0JPGyrdeTDJ3A7ttFutTZr1mNDvkDS1bKipmWU7JPSOW9iMIXgy8z3KaMV17o
y3aq0spIkFtfHwEMlx5tdEz8T/iwPwSqX7cnQdq/VsqDUNNb4SVzr+cYcHaGI1VbX/0HzDuMomQP
8bBDfD6NPr3YWlufkhrsbQfYW7WwfFtn5mraBA8+uYpAnFvNL1nN6ushsbMR1N+vSXjcYN5NACl/
H2124SzQrgKMKsLqQRU44LOU1vbHbBKDecnaquvebNH7p2feemLLqYcfbhQerM8RTzfGlW92BjUa
pGu7s0UvPCSvVvGLI6kKWChXl/Ug0dnDJutwDJbPGIIKIcK+2NPBDWx7NvZcgk1vLArNWzWWN5i0
Z8dDhZ6CzgsX9JZYvHPLyXwjLrgSDXp6EkJ3xaVltlxsSPjIWuSJ5UR2t3a5j70+y53DA5hawRIJ
BflpJHyKmzPzoIY+XozhC5geLbq+MLSTkXTA+Md2N7j1po0WdpbtlNFxKyHKeOmAG5tXoFNxuonX
NfKY106GmQh1ErXt/sv1FnwsfMlB1zi1P2UI7BNRKZFKqOrCBbJHJCnZXGXx5HE1jHd9qZY8pcf/
raU+1iunjRWFwqi0m4Q/8gbHQTiFqXI0Vta3iD7PfOvOLzc9cuejpa4JY/ddtS3kX2TIpZRySbii
XgeFxsoRZG/o05PSNLi9egYTmlUgVS8d+uK+3hIvzh7l7GM7KBHA/q9Nsn2MXkbuM26NH3qxiAea
Dn32PsY77N/kRaam/N0h1Zw1y+Yze0k6Xo7SvXAa3PeIHINvxYjsqA0DUbJAr2qJQ9ez9vPSqTOB
Dhbd/08MfHVAhXHpF3fM+00YOk9kcYkG9Ri/eeixt2oEDZaKzJLnnoqvFxeWkGjVuZfdk5dOu9v7
ExEKEHZo+ZvJiEXLjjzmDtZFould5AIW+q3ME1xdRFAo48yScl3GdhltW7oIIwCbxONHp6pPH1DB
UKn3Dh2Z6TWDBMdTMe2/L9TS7lojLF/dKkQy/l5IxcOXSsyxUWAVpL5ZrB9DtijZUUpLiHlAFei9
Y9Z+k80OmqZhY2yO5s8R0ALs1Ft48o5GjKhCgHF72iPb/y0d1jf95FfmUoxwezzrhskMaOCfFgg8
AphxbFX/k+52qiLuQkjtJScwGnNfZDEzWfMjSThKXVI/arwQ7Tn55JqubDkyP18b3uYJ3czC/KiX
yv+ED9+8d35HV+DzUtygwZY7rrisICcU3NFk7cc8i1jdolvkOva04x34YiSWT+zjbKj39iDgMJfP
nq1M1Ah0h3m9u3TgvvOjbzfU5dUNe5/RyIdK0LTLLKGFZO1jZL2P6ntEgfg507gCdVHVavN3mTHX
IPwxe6Y6aJ52LnrwSvqTlTplUK3PXqyywVm3ukSQ8najZI5ITtibqu8sJzJxPESP1h/CGEy2irf0
tKuFjzq4iUmlE08KwGR6AdQ90uUyDZ7BInDpap0TUFE2yqj+Cmg/RLdONz44miMbIJ+DAxSUi2MS
CVoaEGRDgZX7L+1GCwlSyMt9OauSexn2E56pMGI/A/PNjcGrIdxkutQoK2YRlg7i6f+wNb9Y2gcM
YzNWLYz5uyo3rNjHRcKm7HEbiWcCdoOlOc1k1c55wLySin4bgMGuA9UXa2pj15QXYNFMeJbtfhwm
ar4+eZn5WyZ6Q7DhbN8CKPpHO9TyDPvVgQmrAQcWSBAx1hC6wirnvf7ATJlrz+DmfHI9E026mId6
KH40lG9jMqfrWu7g7s8wz6nIBiamEhcd5objUHUEmMKbsASQjGVhZA6QbCbgAukMJWUtjQs3kGXc
FgiOMoJpGeYNPE8MJgGTMl4eB3OVuQh36cD5wqXzYC8GP17NZ/0WINIk6TBXOsOpv1WCDSwhzshP
zuOsK8lBIWHJFZMEZp1ygQP/cGs0RyCqkD8ulUBTV+K+EZcy6DXjw67oee/ALKZrhgkjW/cAGZxd
eGZowjoQwZjMCPMMu4WX0cMnUwzIo4hU1IQi+ktIpNRZkliY3/li31LBpNye1mMA1I1p7/jq9Rb+
No3LbhHCont+fMEy734+6OiLsjBXts+/ro+qRqYFtjyT+k0RFo619T77Yp2untdxkjuR6be0s93j
vPwKi2VrjYaTCJbKSM0oj0YtWmM4nSWlNLkS2h2rjbGdujgcDPlU8I44Bo2G1oMGiCui9FodkZtG
kOBqtjbv1R/z+321jpGACzq25FPJUSd1xst7U+0GLp/EzuEpptq4ISk5nnvG8OpY7afVlV5aPFsj
MBQKt8uSzd/dHgxVjmPeqp1cV0WABPcaLzC/ehxbi04Q
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IVxyk7XRM4VsQcD0QPYws4xsTeDPKdwWYfreQJ7l1z8C+G+JAKZ2psrNI+b5ecZ2ziPH9MBGr/oY
8XtzCKmjJw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VO3Jpo4aYF9TyVwyAUb3a/oDy8Yhm9ea/9mAjNtuOBRL0qoy0/CWzL7D+bc1SnZvEP4BG903Ildl
dM2y4TNyVTBUaU7Cz+LzZfu9kCPWnmttlx92LcMKLNuvGUMPXmV5jr3PzSFEvoDuCinMqNc8uKFO
Ux/aX6fmBD8AbQfpK30=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qOkimDe0rSU5f1zKvoE8a4lZw1WOOUxh8wtTIN0ys09AXuQuNNCdfu6VL2Xuj0Xus09sBU1FazgW
XpQHuw7XcozHRlnUFKPJg2P12yPJsLRkOqUWtHTUXmH/8s2RglOoEcmFeX9FVh1IRMdnp+D/F4GX
/80OwH0Jtm4eUDa5EFkNoIfhlOG4JOG/JCsYRnsAoZAbyHMEk6qPxdOGDrYzkbA3CMCikTuE6wOm
0j69ZgENzpWR5aludQDu44oKZqgkdMKNm6Mvk//s2aUOTBYWabbSKe/I/+cEp1tWS7+9AAmaVwO+
KwmsZsNR4Ztb6OH4hCq0936o+bycwR0b+Wr1VA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4df1QYXbx3PmA5i1scwSy/ZAJgZ0wNtl21eeCeUI5h4IQD2UalJOUkc5a5UR/j7lX9ToyF2yFHzK
L4EoH+xXm54bGihfoaTvocQQsWhCDObbmBOtqB6WS1/bog7FNgoEObi/E19vJsjPSd6nCCdhglZ1
j33mJRkZed+lVziTR/s=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Rtu5N6w0tnewss9ZQUyM3gMzu1D5Ba/+qJO2rdGgk0QN5Nm+4TaVyiEXzVM5DP8z3mycaRD+z4HG
QXarW6RH4GHKahoLlSY8cryjSJRWS6D7/Z1joY2fgJb8apydMguGWjRZ/uW6R7BEimGxB3Xuon63
ZdpcvKZmoyvfg0kjAjor/DxtP3SP6DKxH3BeegGQKpP/+5EmCrAhhPu+NA21340wcbghotvyYusJ
ErSZhtj+1FLwV2sO7TUt1etBG8nf/yETDQPE7Q+zX+BzOktmY3tIKds/9qdyDt6Qb5WIxLMyaMa3
eyi0SGAuZdeDtK8Os3w2ajEZI+VjufruVqtCCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17760)
`protect data_block
yvvRtu+tA91Rtyv3I35O4K6BiUlBjs7LTFLRc9twWgYZkATXrSpXZut2NlvE8mcC7mB31ueT2vlU
P9hzhGYaJ5GcmScpsC1FKNndMfl3Ug9Pqiw49YT0Xp/AQWIr+q38Pu2DmkLm87YVBi0HN6JMSu6G
rwJt5qvXJYVA5oSnqcy27I93z0KCdBaCW4BhEaXbMLEY+qzcYsWxGhgjRzVfC2OhOSpdpDr2MKHw
1YDri1cTZAVy/b3L8VUTlyQx4YRG+qS3u0Cz3dOLm9nglzh9Pa9XJC4+Lnpli7w7vpvakaXaH9W9
I9Xs/9ShuVul4UrHUMsoz9V5jcPh1iHPT9m0ZTeLUdfod7NEEFDW47vWU8XjL6iEqBvA/DrJKrri
hjJ//n7fbl9gjxGZT+IKqHleRVz+dRiS/uTuRo22UsAcWrLoCdroE0x4MAJ9vC0vScZa86PQBj0m
ixJFhU15XHesAUmaWmkIVFZdUdZL6n63C2nZpQmpBX8G1td46ib/xrjcP1HPzbr1hPb30S/GA95D
4e3ICss1yPb8NZCwvzZHNKYRJlVJ6EOWwDxLeBOjWmUySMUcywo+toi8FWztPmB/Fzs/gyRSBxsb
FBe82kj2NTjDK0dD4XCcU8bGjVOKNJ3KoJmC+0UD0jihX5N1CdPg7+/bvmP+MCdk3ondXZKJzYI3
9YFYkr0RM2BhF57jZwHcHHmFJrakmG38Lap7lsdonuIO5mfOOuicr4JGW8Qijs1+c7VMc6LUwGDt
YKznnHTq75vwwVLxmtGYpW4RTIuqlZmOJwC34kp9oVx0+wFtUxMvQgXry9FwUwb2gSWRseSfbmMB
auDz+22lW+enEoOu3PzG3plNq4oQP2K2H++ZU7HNTNGSA6VpJWDQ1c8o+i7+XEkyIqt9DZHUxb+3
HlbwgxRkMYX88B7lb3GnNDLF2YzkJMgQjpyPi+t3N2MtquCFuqNuaKv0LoD6+mwRceg/hAylp3x1
m9DKQ0DcKuhctFlcx3aOGMXc0mzgjh9Umxn2Ng7JEliL6/L086w36Jar0AAtsKsXZ1NsDDBpiIeT
c9pWEQj9ud2144CtZKOT9/hr1wy8/jpi1lQaHanlWWtc/eb1aDpSY58hPbltVjUTyizUFFWsqQAC
PGoqDXF3N036pR2Ipsz0lKGQE6qHOZ9IQByoJkJfVJQFD7arWnGsW4G4I9tdTj8LBH1I0/XQKvur
lSNx9C6iPx8J8GemXPHqEIipG+GgoeMURYc7ft3GzrBdwbTFPm/qrxT/0vdju3tRDBl4JSzWO+do
z/s/CD6wNYNcDBCSDKcprRdML0+tkUYr6Jexl5rxIe2GBG2XGRgBDqc+wBSNJY7VVfutmSr3NjPK
RJK5NldZFn8fT/rjewbLV4flhMn1tgsE6HhNm8GuRS52PpzP+BK3fCtYvb1mnkFy+e3mwc3RgZ45
5iaZGmsBwnJwI9GcgMGoWSDkSaL/1PrI03WtUczFAidTPvIY08FA8CTdX8Bo/j1vK5yj8spVzrNq
2YNw08dzyQOA6p4yaEO8Raki3qlKk9oCGUe72zvHFj8EIo6DPYz7MTOBMZh7qLr1JDqBA+iyQCSU
UO9dElHR49OYArhLqejxnXEbJqi2McLLRKhJoiH7B/feWKz5mjNEjtWpHgiwx6VhyEKkL6UZ1Rib
ZtiEI9gtUbhZ6XzaYm3TiIRoYgTzxH0j8bAv7Zy61YnOi5ds35hrlF48AdxPXK/eT9RxLQ9JC4D+
xhLyqoQdstrt5DgaM3NxG2mKEJVH9uc9wj8j/rmn9YrBedhVek2F8Uvojvb9UP2S80Gz13xgD5DT
uHlDBG0pjratONtNE06BnMLwZRtD8fOAmitaJqr+uurpGUSmFSP1C9+FHTWgzBTdRwxLO8vYdEOz
WFiLspZhFCxJpRdUt6N09XI21qtC+0+ZgVoJcuL102pig2HCGw+mVSkibp2ZzBHApj3TyyQWeR0T
soE6qVGrU0cCA6w+mgSp/LpLjFALA+nFAG3lXPvfyzy3nWkgcWbCXiItZJY+SdblaE3tEF0j7zRy
QEv4a8Rg+L6tHbS4IhpoHW2u/3VbDszbEYb4sRKfYUA0hAwJaM8jOAxyu4YRtJsjn94Jek1Taiie
hp0Ndlnhy5vlx4q5I6i8Nc99UyR9uhRu8iqRtT7nCYuJSAzDby3Uxqh6srwmKPrb31KF5pRhTgEE
hoDR5pRAhvr+p6GEHRm1IAJTB/vA3Cmck+beIM8DaYRIdaZnzC9N04oH+sWVHExAUc9WW2ZHotPC
yowKFvokfu+7look6EHxqKtkI6qUIsFrQgy755fSnh7+GR8EVZFKqkRCDv0zQz3m3MIaUQ9GzxNA
nVZg02l+SgGZHXvy8wOZE4ONpWcUccgX9k8Mqf2VrJEhn7FTdwr/L68VLWlWyJ51gTID4qsEbmQR
eUcVhXwZ8J6/Jr+tfQkihSE/r9/FrMS9DtCeXZFSTXFkRXX3jwy08FYzVkX1AU3nfi5uob/pWe44
jJ4c+H4TgTK/YFd0U9+b9+hcQ/PKCmyuUWlZMD2jh2m6YaM0tRHT7pTE3k+5NorK0KIzBPhuhR0P
kwadh+BfDa9Ed/g8FI4r9aO+bzUYkbubz1m2BkiyrHNUN4b/jhDQyeuJYsvVZmik7vXZ6GcS1rnC
ZJpUE1bWR8FcYhqQoncmXGI126qn791BoIP3g9UyBSGDJ/hK/eFW6lylhaaJjjVsKepmxGzcVN1B
mCwVpKVdTSGBmK72htH5om7KKA2S1rC5U1UUj3MbiW7ZNwfDd0USkl8imBDLwgYFtoEE1ko8C7Jc
eUprl5A05bpIwcNw4M1zuvcSJzD1rtWdZQl2vo3uekE+ox++ptfYE1O4Xj/2TqSRnKWmvElAWcGk
d1P93oZ45PNjviXZ8GjPM3O0qWdvlgjvAq0xdzA6x0TysB9PpseLW+g8nB6svNvi0GhK/LLkeLYg
V+VOQradYifDOr8PNb0cqid1ncvsR8+c0tlZfcJr23pLfcE3Vqz5wPmHYoK484/vAUmQUEHiXjLv
MiKyjk8ywnYHQ/TOYWuO5OiF3b4XtDucLmEyRzxNB7rY1i7qaj6wGs15PP5RLOMaDOI9Kg6163IT
YHmjt12E1isvBtgqS4df/zN19hcUsAr+Hd+fpoCiaRD8qfZT7eD2F7aDUpS5tVOH7gVSyJWqzQ5q
Obv9Yhw7rja/O45RtfCLUeQNveIdOxbYJdxtkbtNUL4THMOaUooUKNDHf2XRJ/IU29P3yYsch8DL
w6GDueFKcmhtTaLLsoIw5tztfz1OnR/Ji8//265ufazAczEkWZEuwDJ820UjB8sYf6rqgnsGaFMq
k4/RqF2vivZ5ejxFZq4j5HxYIkrT0dvfR14iHiz1gFBjRkaPy0KB92AudlRi5GguJSj9i9apnV0C
9Q8mNjw2IhqKOYuyV9e6QbBpKJ96If+glayPM19wkoNu3wYrQpc35Fto6fYKFdY6dhE8nKPhcitV
/uItKlA/SbBd82Zd2+R5YPNcmQq0sWFXHgntGjncAGogKw7gdfoVMOM8623k3ZSxgx+hl1hERb55
2VAlad1Z2TVWotbB4SU6fYbYbkgvMzH5sJuCqbAAKfcoPFz1nWbbyWa08tpLEd7dFgSfxRMD6emG
vbRwvFQQjTUHayp8X4YhTp75/cn7s7BNav/nMANVwbzv+7PlcCBDE/FAkBmre/mWCARVoeNQi9yk
Lmy+/QFbBCSDmgH9dT+J0qyptUReayys26DpOx3zpnRbUVqoevpDLpdsoEIttEWQIhHlgFCwxqwE
aRk/jq630RhYJrspYYhMKJx7vBModJIEGer5px3GFiyOMr4+4I2Loz4N0yOCB4NxzVtMSM+DMFzb
Yqmp3TY7W03MSy4BUlptWvy4cfrCDCrea8duJ43frMTKFTfbW+IerIgRfu6o1EW2xXm1cTpBK1C5
GDw5N3ENOo9k6+Og7Rv6BqrZrvmt4KofAZpoRQwtrvIUEswUfZzexMH0dWDua0IDEUztjkju9U3k
MYVajimuyW6IXCYU0qQCvsz9sBM2LLZ1x1Vup7fB1Ec5aPwU/UHatOkTm3aX0ZLYdmaCrVM88w9G
XHeo1x2sSQwb3bclHeYGqJ5KFtGY8NkrjA2kOqD+X2jo651hd0o8X/ii6dRA1MaQa3XRL48KOtEM
HH0PUmnhNz19o5YiXS60R4NMyF8DBJ2arUQqgtrBdHpYd+zsNwOO4FJe/HVkB0g9fp75mEMH5PiJ
iCp8PJo1jsqW1yWtRGUFGwq3z88uUmySC3W8F4jZcCA/IVM3H1z/nL/Xi6GkPU3ho614p2M5bRq2
14TEYUDIUMMz5OS3VFeKp3NLgKmCpVj7tbmiZi9T8Yde5BbWfETD2YjKPY4NPYiw4TNz+908oHc2
yTbewFueWvL/NaEUrh1xMwQw0DRkd8xsxovrukJPMeMMIOpJVuHAqxeQFIhjwyO05shLRO+8ICOY
lVC8RDu4KIeHaBIdj78ETsgHAau5157cMpNdCv1z6u/eAEhsPNaTpoYf5z4Ulz5+vbrw+Ig6ywPW
AC3chkAwdqF9uooKaqUaS0uaMYKHDaK2y5UfVCBUcfko4mCk+jjZbqPR4oE/RY4mRKF+S5KVRb51
goeafsPpARmOwOZcbpLNMXGonqOUJEFV7nFBn0sn+mMycGAzE+JXd2B03sI8g6vqICD4805s8/Q7
Q9RvYQCBXt2A6pU5gu9eZBujlJ5yteDEmqSPNTNLHzUtnYMoAcOjjRN+mnEfti3CP2YaqZYc7AEK
EmGhccCK28g3Iq3fyEIwqSG5ZMQqTqoqd2RXD5hdEa8/QoSw8h+tBDysQ5iCskiecYnVoVm2sJ9g
EiFptSQHJIy0hyW5bqu4IBzo173gYuxltoA/x0vJsCyFYs77QhbyJAFsJLmGHqO3cT9lndY5RmIe
G2IsYZVzwYIn/hCH0vy7GSobNYDvEMIvGBaU5p1UTsf1zLoaBwNW5il64Rmt8mWVqr6Q4Cv07zk7
YKXZHTXhEeAgsPcWekKsDPhosTQ1OG/Lbmqe6Xtt932gr1mKpZC9HDG0zXIrXY+2oSE8WilO1BRy
J88nrrr7Yu0oYnF4wZWHuAWIyjgLKyWWX4IP/WRaze8T+DWjRzYC+x719Lw3Own8W4ws2iTfKhys
/AoSQctmniBEUleebvUzkP/54oUfgrmlSFnT+LQI1wpo2T+VfQtutqXZD+Q9onWKVVV4HeEbkZlD
NiZEFqgI7BCHMNKvyQsr+gN3d1+ljxpDWwjLTifh1kNDK1FTX628L7Esv/ze15vf2ojo/9c1/gl/
t1SV+B85OJEVM2ghrmoVc/L4ECZPJK0ZQo5F/4K6TFqIGKCvu6JvWCTXCXXQuvIJWVCf3yQ+xB28
CnIRjnpjYhPYNojhQfb5Zv+GZ7LFqZZ1/o78veE9yuWl0lUlNLkf7AciAMp2qc67QqLSzbmp+IIZ
GRPGcMLDzgqZMu5UoNLRtDcIK4IdO68RfVU+DfGj7azU8UasdLC7EXFxENSmQ/djh/0I4Ci41R+q
wsa+kmx3eYs+rFXPF/gpMof9+m7gcNIlaKRiKrmGwaefZwbiLS2b5ZrIZ6dIXfBst6s3VP1CYaaa
+z49NTCU0GqV80EBrXnRQ63CMSRECEHoQlN/WGzyaldjxjHPYO9Hmx4A4l37hy0X4CBEgwcgcLmn
2IaYATXcAYJj2x+86KLB5ybH7SyK4Ew14BYjahhIhbE/HpiaKw6srEVCnQJsybU/L8kpmLrJFJJB
A7L0H6rsyqypQ0Gw1vYRNT/Iq1SfeeCbJucKyPaC8FIIMxhLscoBs871BAGV6PnoCQwWlPdh7wt/
cV+rFe76p7fOp7y/iWBGEIZ3hi+nWA/1wg/Gwy2n5z+TL5zSsOLvSN/UaFnaFFlJfzsshhbbzRjm
u8HmR4iISYlZfg+PuCGg4qWDzTm+W3rHe0IKKFdTl4GXGM1/EpTtOAqbIDIWKEIZkJ5l8b15nkSy
kXA7m+xG+B2kCr6obeLcnH/Kll+3TvkRO20Bb17nVNUb9o9OAtuAZf0dsN0dkMWVbDBmARX5RrB8
Xaso0jhmy2GD0839FOGPRmjq0itlZIHy9gyGxFuelbdXGBP7YJlreCebt5nS69xLW/ntBMeaobHB
+fuRF9ZeLz6NIAjircenBW7v07uWGziq8CV4rmH/bVbBQVpgNLXkN8+irSvzIih6+uQU+4qnhkGf
6DPM1CIN42m9ynyzhboG0MwLmsmxfHNu6W7pdDbuQK0nD+bziOLzzqrXLBnyPXGnwpO2QuvUEpHz
JbvGAC0fH3+ZHVgO2K75xWmD0ckLOS8k2Z5yXiDsc+mex5g46t0h1hrH4Yyvs+xHhn22sZ5vmAd9
z+TAxX31wRoiRQvb/b9h8k+DfNRbYFTRb2ARM5f0wglZ2CBCHU3UDca46UnCcX0s2i8dCJiik+U8
1YIMvzM1YeyL3p4mMj0N+JIFkUtiWw2Iimbj4Zp6ofh5N27FA2Lw2SNpuIQppGII0um+Cd8fl8LJ
wmvWzSxiUir0Ax11Yq2EPE4jm3nKtv2sY0E6lx8WJYJydjXzqOwe7I/q8cblI4Vw7LJj+vuX/Vac
5mEUxAfQSPmHwmPnz7dWxElLo7zN511DK5ZEC8GBtiK9/m3RoIfI1+3Csl/GLaL5uWLV5jg3nmav
Y0x1hldBRI4gGM/8vCOKB1q8BY8TbeB6wETtrgJDpKK2w6lzrgVWA5wHTPjCuFeJZQKurXZeL80g
JJpIX8UxxYd+U6Gg7ji8gqW9cjciYoznCFRSJAcwiV6/RLQ7TMkMWTU2UPbgRRUhP5AJaTlsHLBG
kDpRv5sUys85ONbc5+pksLhtG+6Vd/mWvnomEBms1/e+jX8+Af6n98WPo67PSdCntlBBB0GpSw77
A58uptTtJh3ZnWGQRMSuQLMvad/WJZKosSXA1e4gAi8brVgIYmbIc2kzpFVAw8CT8ZJVQt0dh7lh
8tVc9ifnMjHMk7eBB/kSfTmYqiH66g/FPPIMThz2zJc8uB+JcA65L3cTruK5TAIZfFjQsRhDD+jo
+IQSPEMe5sSQGn6lLvuEYseLQbSEswNwE1xM0mWOmQTgipmdzDR1ApQU7CJ3glXHI7CVSZ+Ptc0x
tMhQKU+3nMUBMdbrbWczDZr8+LtuVq79gy6RjWSEvDiU8k/C2jfU7gvAAhYeQmEWA2ZDfrBZGMUe
ctwS4RKrBsgrdotouRos6i7rnUYet3BfSROrkb0kSdMZRGxAyAEEU/HXaAAC8PBph61GdBPOjY2o
ucgy4/5j59ePvr2AHV13YPvzcUThetgzbOE/iQtfdAyChyoVx/t7MUXlzDXK9YyFeO5akcWlv5cV
/tZmdn+0Ip2LqVVRXFEBSoKdQdXJdPtlxjfAelCI04ov4YoJ58o+t0nhwgO7bkbIx87oHNgrzQ2M
F9Nx7WUW7kGIwr83dm82aDD3MxmSYxoppKine4XFBSQuB5OgrdtAHhsoSTFIgdLrqVtjPempXbGk
sAGCyeTTFU5G+XjRzr/5F6bDtFizNprxJBKDaht1ZHz7ETvgFDqUE1wXMVV/4EQdWo3mWO3IzFHy
MHtIRlXUch3GQNXGHB3VG9FfABO63ISUv+i8letcphRuJGaIqd6D140yb1j9b65V/pllsmcXjxZI
Ah43oD+OViZ853FMzqnn1m6QUPSsMZIRyqrAz1NPtluN+CJrw1FCZVpiTakwpdxU24wYPLdzkJVt
MpfNjTp4CfPgAm7JSZ8uNwQriV6W+lMhO/nOlWDmWdpkvsTuaEmfMCDUgnSLOZS+lGvmuwQqc4c7
zpaP6+TmfafMbg199BGBGKHnAzZYORNMzqGduqQH2rfIjXYsYhgEvrviZ02MrjLaQZP6+Ut5Alf8
E/kL+HVFFRph1szoSkmJ7EBXybrGUR5qMCQirKzjN+9O+mZGlpjLRjEm9OvwEI2YBAdnbEy2PUIS
EppQU9iHilUApIhfes6nYf+wBw90smvQ+ggytyPZpyUuHI4qtFg7oOfeQJsHmMUTERb3j27kJedP
2tYr9qiiRWvUkdwJ4KJwqWf4pQgGognpwYEamf+1nPv2wTMMQK8Xx/yjdn10Y0/KWTAYXLQMmYjz
1frZ7sNr9m2G1bncTeAGzAAYatbj5nvolqrKxgG3z0xhGVUVc40Ki2Nepm+7jD8G0IY0ml5LLddn
YbZpN/8M3Qhx3Xq5oGiH/2TnC8sMX0iYn2UCyLxrWczitSRdquyZOivyQrbiaox+Q14RjH2RZNd5
aQF0j+++AlFnkxA005oCTlPjkpfMTIc4RxeeLQJ/tOK503oFkgsrCogo+yF12lnKy6igucSzbMPn
3Wor45sypUNSbvvkuBCYT1dqOqZXmmu2OwrJxxib2arzDMD+Od3/2YCFIL50cnXvoIjhEB0DXR9K
/K7a88aV7qbJ4DHBzJ3f0XIdiFQ8SQgz7J1rbVBgheu6FymoZephdjJLqZb90iDDQWVJmojtbzXg
gFOUIz5M7rwsn1szvg6OQvvyk2BO7F4pzU/gosxylIy+ZgksSmVFg/qaV20rZ1k+aSKwrFaoQyeZ
RFL+1rHpj+IbGKJ0T6azxeZPrSBdULXO4GIJdvr3Qb7m1uZp95FUpJBDu9qVsBeW+e88fCT6V8gX
VS6NTuR49358rzHdu4P84iHiJvQ86U9hTj3lb3jjwQAZN8p0kHLIhJ/OK3HNXw+RTjLj3vFhUR/i
IRh025GWPgCvLKW/Fcjs6l17Yf4iBubssKiYf8wlCs3fcp9iubVKMP7pRHwefSdGrCymu6kYmLgw
mqeCa1xHRtdyJWo9Qe40/RZF/z5wrG4kAL6/QY4JsNK5IuaqdL11AZL2SCSWi+If9d6xMChOcgdO
Kz8rL/ul1zVN4v9usZdnQoWuT37LkO/XTV67Fotcg6wt/2SklpnESLjZ8scuc4uMPNBaKqJxjusu
l1vSBAc0RfX+94qdKAB1kZkl5L/0wR4MeVpy7u7MCHssLTOzpzCO9upNisBXiFFPDC00CfVouYZN
XXF0RkU9ILKEeChv27SW6Gi7Qy+jku7OC4OkwVTtOeSe3uN21fa0MxUAVDqDcSYih33eUdQ2UgQt
L6AkF4QraqjCQmkNLaNY6/FADaaIph2sC0y2v4R6EliBhBDUC/ueMaaLEicWDYdky6CenbfyuZOC
Uvu3Y/IwIV5G1ioj22TVv+/LM2NMXlM3efeBXVFLlpk0glMoySXNMXgPIwpcUbWKr9MvEuUqvHfU
Ua+EPFCKPWY+MPtNhxODgEaf5SD42ilmAXixVxbfQgZT8KDy5ESHSevUnG4beDCiUOx2OxSZYEd2
WecJ3ZL6564z/G4fc7Om0ZIOU9ng5EgK5ufct/8wDhJxhrKfWKF8oGMAz/NIeDg+KDpnnOd9TWC8
m1C/nAlPRFVJESuKzp85N/iFta4ERlbMXC3KbBhJx19efD9AzC6BaiST96FqCaEQ0gbAZg+5M0vd
sd4uARkYKVZ+saEmK10NttpOf8+fMTy+o11z0fGYxK7evc99er/Gbpf39qG9yEfmAEVRfphmZPIn
SQf7u15eABhrE65ulYC9cW/1kD9cckhW3Ca6Fmggjt0dr5f0xyY9FGPQPcKlXF41lN5BHyQxsQIA
iGo9RSECpzORa/a8M6ZNFsEFb1RNk7PIJWUUTwA3yGJ86kp56QxDSwHJ3pphqBtvncSbkJA4qxYe
VYFrqoPM2y9CnuLtBx77VYq0P4lNlDZj2jk3mHJrjUoyGQJcNWMrbXeusyvrDBumKKKJuoCp8Ji0
/RMJ+8HFg8+R4uKqYvpIJg8NyYQ8vYA5vtYccRW0jvZP/i0U6PWDFr9Jttd7mvkTVOZWVQzQwIa1
CX0sZXUqWjeUdWRk0PgpbprIfHUzRGF/71Zzu1yRW2GCnx767EQ5qKMpDIk0GPjYaqO4xoSoi9aM
1yz/MP17scsZFRtDTEX3mlGXuzvOXzoZuF1pv+cx/HZyvxTWVigsZvXDBZjLh/wgy0creA+fBV1k
8fkV6zAuCk5dk5WqKFfYd+1UeCPMcZKIBp4CT4CSOy97C7PdZOfTtjBE2N1HOoaQ2ZxOQQfwlT7T
fBNkY0FZvjuckL0I+G/gCuS39PwVULFYbFIzpXBM1Nbej2d5BRC9Qd2AZu9sxMPtcZKUu95Tnwhz
RLTAtWmI3jpVmutYnGnpM5mKwhhOdMO3VOC5v3YpF592DzT+6/6Acs5ks+nnzpA1Us36PVKcWGkE
M1WjUqhQAuy5AFtL3rF2Roudc62UHxBXUcrRUznmTU0m6HWy5ij6umKW8aSGQEAuTFkgHG+/QK3t
lkny9IyYFmqLI8pYvOJTBRa/mUHj/dj/6NbKzslOo2YhiygO1nVPUAcgCQY4cgBaV1HZAFPnSrue
xDDcyoDCQ9XAq7HtK2PK5zi3RkeZ2APBYNWexQi62G+cTV00wfk/mJEXllv7M1McZl6EYNB7w7Wy
NSFsKlLu8YEu9N+Kz6RKVjxTNxRK8PL4e5PF+lnFbOzA7pjA2WZ8s4rN/GBsDQxj+iRTW9eFFwkI
55pwh0HyA5SIW3FjpJUf7cIrlGZ4oEXT7+1t1T2BK+cZECsvU3yQPWI0wujjI3BHqX2Avcr6Gfjj
Zt/BOCeLm3WPYbVnr5JtETvK2x7GxSyH+9LMO852zV25Cd+48P/c6S2Kw0ca728Ny1Y6KGbL3qlP
4EvN/TZ7etw5UKea706IUXwIQVwpP5jQ938y0oHDYwffAWQlBszHIVreDFPDhRH7grduFfXwkAZq
Xg1+sBIztw+hxqlMs53QCz42G+g9RWycycylepEsvcSk9fVNm6VmgeZfgi6X66giRnNJpU2PIBAF
TmbPAcrMrGqiw6Igp/NT9dLv+HdaubjRbMktYivcwKhtfvRJxOMuhYot4wWlUUavaDQbJmW24VmJ
ZwCVPPi6rQ4Nhst/OnX8HNiq2U/gTHWXorogGqfyr8Y6nwQ1i/rMdmxoA7b/GE1m9P5/B6xamFQg
EwXo+CxJrOCPsGlEdrtI/EomayDvxVj5CfvkkF3AfbS1sQsfyGGG1tUvsuzyG6HbCWTS0DgHLYKw
mLw/kac2HudY+pRGugwjN7CsZhMmmjhzcrMq0IOLuASVzEQ07NRtu7qYo3gXq8qnNgGi3DQKDYrw
SYfT6Pwt/XDOLV/1Nwm7lrkBfprfCHgW0qbPVabJczWZCD+LcxtBQw3gU2094NvU7pb7yPhlgrq0
cS5wrnWHRgkSVTP2nTdECUOf2uvdv6UAYuKZB+WHxfuNgMuJy+NNx5KfDuofgKn+lYGw6REYH3Ka
ZOfYztF8bAdIPEvwSawpzhGQAiNBWeC79fEj8BBPy695w6r/wK/tqaFZeWkyTtf0I3GsKFAFjoZf
KzKY+NxdAAJi0qPk4lVk75CJ8kptfpPfFywJQmfyBb975TcM5vpsuS0OLQ7PPrjlQ3gHCKvA+H4n
QPQpKtQRoRv3axSt2d5bX+nHX7sDe0XLK+YohWnf6W2r8ED9onbhdOXu/KX2OHKoCbv/dCpO3JIs
yPgJIlcsES6Z7VNPf7AG2iCOhM8IJc2rkfWNF05kCosrhh9zj72ovE8RIohjbE6NHLiuUlA8oede
e6MJsIbj7L6BcoK50YtZJ47mkqQ53XN8aAc4J/rI7owAq6S9g50tYefm3L0nPbuCGWHERzd2gjBj
eixz+xrcNM7tnJIQKf3BHG5GEXQzMr8loXRSFArDmZxS3+X0oRJlIt5ZBx6wPaJLw/47C403FaVO
IQ7rKIj1J78aFfPu3+RUWyAxXdSUla9IOrNugivXxl+/pixnEdfqFhdGh7sINrMDr3Gva7MydLld
aT6Xxy2ZXoCIrn3QUJYKAx8iSWuYEwP4DqSnDEcIzqyptarJmsEalMCp9GrYMqhCwNqKhm7QFRVH
EJZYkgW+8UMhys0ogbrtFGbOrQzAPtBJbeUFIniW3mJQMXc79i1yiE21ixQ8ixak+mrYSNslA3e6
hUZFTZJoh5xpuHQYY1nBk5twjasanafpLNUSwBeNbZ44LL0/WMXxVmEI+OffB5P3t3OhAtcLuUmq
dmfqUu5wfet7GcTzjZMame10OMV+omk6zhW4JKpGLlaOc5wx6/zoGhGWuaT+cWFv7j06y/IK1Ge5
VwYmkjNekZd73ikRPgWbiiTGW9uE4WwlB6bawr+FtFUk26pt7kv3iGZfcaexkYk3gFuoCjMatcxm
5iJBYNcSz8AWR2X2L+XKSxtSf0hQgxgqoTL2UfsFHmKChrS4gCUThdVlzTQXUx4eyHaIJJH9DnFE
M5L/7tl89MeROUUOeAtes3QIlHeFFHBL/Ji3cfap8ryGMN1/gtgWdRFkXnoX+G6hQhXwma8qXikA
LWFDlKPRFEnz45o+6OCrGzLwe/otDBFLGfQ+GWVpN0kV/uZQ75Sf0e/PsUXpFnaLewiSKank6gwi
8yF+WH1FQE9YQ18xUl4fwH8mizCAxcpFYsA0t+RbSUT3n/4OMU5Qp9o7PN7lBGRIO5p6cMtXRnXC
JfW5MAwmEbuYLebmtXFTuJDEJn0GyquYWPiwpRZnv1ziMZpHifvHl8+OztIxJd2mYoB0qILovXrv
p+sSoT6d+Qt2nOaFyPi/m6CB3U6EZTDb/lY9CEtizEw/HAA/6VwkE8uIX7K7vI/hr2H0tduoiiNC
Z7Qlv61NGDw+Zsk5lf/EB3d4KiMTGGR+U3OwHtOnm6VYC8rcu1iaHeniGKq68Pd4RNabdW0SEWBG
SCsEB5twlwDDXXKD7ZjGPdrzFL4xeUQOh7FvLbwmC9sr/yhddMvrFkA2V9wW905QTisuA8OW3JSB
AUh4iRU5p3eIXnK4bV5DGLg5qrBMXKp7ITgTUsrz1GkN0djgyFC0XYoOcjI7B/yHlOip+3I0y4mv
lvXPbxrefN6gyKaXEaeKqc8lkTrapgWmcul9IqE2dc62oipP4yfF9dyU9mxlW10geK1g24KEyzGo
BeRphtKG4Qmo+nfR7liloRHvowONq++DWCDl7U64lFtPGM8DVJ8L3f2O4dZ63W280QNqOHfM+D3v
oYV1BCKRuIDzGPh+aSQpVALS7SpCpa9vz5n7NadTJvhdFlHr4KfuJX3Dh2oImi+n71N0Qn84euc1
fOD4vRyV2dyrbvpf8ZyzqYuhxBpx4gleNeoUIVPfagb2FoQQ+bskrJ9Fzaop3uYeyYjVHHz9Hn/v
kD96iS4c3YZAm2tkHGVHg07+rB7CjCZASOlDUuBZBYy/Vf49Oo6ZIbyPX6zKW1HIZX6TCXgL2RMD
Z18i6bS4dVWdamjHoVM2FEWy0zWmP48ZzqIofGQ35eZ/S/W7DX9ElshVXWSoz2DnttgcYeQP85Uy
g9m+ziCUZIcadRW964AoRUA3+eqQFMd4s3bDuqBW3XcuFpHSRPXh6t0Fs16Zxakn48FFt53gPuPn
kWccmrUbXLvLcqhA8NtpSsiryUclKgessi+7wqGZwaOZ/56iVBpZqOJwABqb37gDS4naRX5Lhm3s
m3HaTaYcXMsCHqn0auTQIir/uX4q5UPZFQ8Bz8UC3UKxfj5ULvWsnpZTirNjNzizmAgQT8RVbgzU
2G5ppcdSvbuZsNpQGRd4Pb6lyI9TgsK+1nbLlHGhemrdiL/34MiuObwmSLc73QRRBxNgFET6e1Lv
o6xWN/l6TErNc+6EiEwrxgHsEDYFHeG6qnW1ueS9Lpmo4/z7e+6wy6Tl/b5WouFHRr5e9BLEbuxz
42BX4dBB1w/PfHqyvQ9VWKQ2jLS19zH4agGu55yMenuP9MgLtErIMJT+Bl4ELPGwB6MlUUqTZB3t
VQC2OppjbtSjETZroDDv09xkwKjiHqEFViOwEy3sF9EdAetnX005D6kuc/K3fTbQi+m6fMRiKN2Z
BiUYhf8XENvED3ZMQxboABD11DmJ1e9Fs74DiyxWCij5drQwOkqqstt1vqKAB5y7Yfz7BEDaiFt4
N/hwftM3GyDIag16EDHX9KUEehn7+WAQVjm8M9q3X05bEsi+YJzDYvQ1YUMmCywjgkrU+we6Zlfj
jwHfaDlARpdR7SkNfEHejmsi+v6oKmporsGFi/PV6Zto0tsGqVmsM4rG7ACZ9Rr67LZv2ZBYmau9
YMgEVa7MgE7o+XRH98+6g76U+vPo8sDSXBzjLxrUWj7LbaLAwHwCiaHAk2NE6S11a38XlxU9q4Rc
V/ZeXX8H7FNqwpWafLtSUSFGjVEl2UPuR+LqiFTtg5pDbXTI3RUZ/1FTQXdKgs8mgkiZobQpzFE/
rrjhpfu5U2VFgUt175KUgZwXZkH/mSNkaexiOIwbfcsZBAy/tKw0ZMHpRgmxVxs6aDNEnWMppYML
mirp99KtxeiB4YkVvhoCIgRH9rd9f8SjF4hpmqeG33F+I/8aGa/B9TDn9mIOB0MkA9G27OhNWHti
BhiDpachcuiKHNRXtROW2tZ6QSKltulLhEE2tKS5ySwwxUggM23fjcafEriJsOg/75JPoP0f7KSD
GKya9azUZuLQNLPDToOlCvYyOgxC7DwAJSzAineFxmxudrjNaala4ME5f7ber08k0H7a98KpnWhr
7Wj2/ZJ+vEdRg5LF5JobYzKvmpaM7hGgOO0Y0TDtIOO7HUt3HbEwZQnXW67gaNwbS1SMvRGswaYx
K6wkNU8q8NKtgBuc+BLolYfLBZRJcyR4yNDpU2ZjHuWIT4ts/OFFXInD84SDkSXjHApALHfZxsnt
cTfPbSH8fDmCJm8Vuoqw1xgU6RGcrAVPTlI/Bq6t7tCPO+YaS7Zc7owdZvEsNMbqoZsmDCFe8doV
8cVthfoNVR0f3SFwHIhWyLqcudCO3w5Kbmclzjof/qugz7XI3W4up1D76MJKqi3dcnruoFlabFxm
tSwx3GSlL+5B2O2YixhTq2xSfw1sszftRCihJ0NMSoRqkcjUCZWV/isTBo0MmbQfNmdasTOjZ7ew
2BGPXSHQT6V3s6XY14QEqIGMHPF5erZNNQZhY8yMaHagYfd2U+nuwBd7aS4EyGQFpNTw3QcKE37V
hGX17EZiG8Wq6MY/44BXOfTCtCeKo/byhuif/pVMsu+ca4R5zGuY3CiVWYEsPvzxF/qKifpxZi51
XRmtFk0dvxCb9LZijwdOxnyH8ZiWDHs7mJnDVpcWUMPZU8IvqumksK95mbWFPl5LqmMFM0jEs8PD
mTfV2GTjPFDNIyUlS5wgr5mAkFV9aGhFTJyxgym8HJTFTPnH5yHrrcc8JJLtN4hU1di3Xn1fE3uT
opoRvS0bdUapON9OlwVhd26jM7wCZBYB6trMJ8Mp76myBkkv39NINwvcNz0C9PjTC2KxxPuukWtR
w/yhSCjv3HZENtmeUszZgrIUGEER9oAiD+owYoWYlewK0ILXabNAqrhmEBqBHrr9oqgbcYRDzuYy
tXp0TFqhsCtk673OJdQGB6Oio70EYcvfK2+/+lQbm8RY3MMrGTIdFT56B/KY7jNhS0GK2TQxwqhs
TRZFKV/ZJk4siqHTytH15d/JDe5gR0ZT6YLiWctRZ0o7rDFAuWGOts2T5plZkYkKlicuij/brRUE
VoPwjXc21Asul2nGZ4oqWITvNNvqsSj3pZcib/NkEb/ywxjqeutPrWHdY2z9bYYV0afl6iN+OJPF
mRYM7kLjlkifzhHkjMHeNI/3PFm0mygSZsjtHDrFRcYjNY27pFqwHt2ydv+Y8I0N1SDHvn9BLNJu
oFVKeuo90KYeeut8r9DrRTYqFOonG2OEQDDLAFRufZ3qQCoZzCVAz2808ZTxpmyZlUrqqRB5eNoR
fjg1JW2zKpsRpYXTmNQeMRdldk+Feri5oq9cGD5YRVbI8qXrgCFVgnHaSb6bgNKjoxu7ljGDhDlA
fyljqWnwjpwLnJrnLEEPxCA0T5/et2QButOgW3nnwmS1l46RTyIuJvDC37QKPJAoZiXW3NONxQ4S
VMkIxUni4WFNp61+I8ALmhKWYBMnSF2olRUJgjx/5EoFbnaRnuG71h4SLeOPIDGWQZc0jBwrQoy/
p39/L/g1wLZ3FqNDV7qggQZ0GMY0PqS78funhvJ8e59DeuguR3c8Qw2C0tcThu571K4wpX/OFbnY
beeizjT0zdkHhRSex+8gBUGhTbaSXFA+qwXR9xCY+C7zYRTKO8Nx+cPPqtw9pP9PxBswmjqhEKt6
3Ck/ADyCLZdGREp/A68XVGVvHb/JvfOg35vhDTnY5YS2yaSxtOlTrfweIjcpHNm/KYIfyfc8tE37
vQgFgsHKTN1WfK5wTNKf7aRiY0HC8102JHI+A45viX2RWjDbdLJq2Y7F5ppx0BUGXajkekHFHtTP
zGH4mWnc+ZM9cxpDbZHg9CWY03g1SIePCaPv+IQWravG0Y5/FjoT60o3H5FyFBudgMVZ3cp8VzJe
LvD1NXLx34aC55OogymYf2wimfHqDswutWmnj+tuNMEDOInqQNq9UcHM/OyxxtX8wTTT/NRUFeVm
VeKtfofxOPU4GgEr7q/dgpmmyUwpJdTmUIWgEo/EFBgHOpfX6wnVmKNZLK/35u6h5zONTzL/dQna
H6zFQ6I+cQKT5ug+al7l3k03OO7iBB2zXBSdPjOWpTtDodnsbHMw86WcpUsjoqFkiDJh0K9pAiTs
yu0YtLXYhpLRc8vLx+nlNPLnBlewheD6Rsel2vUITR+Y0R+LTIVcFizL3RkCWpgT8Mv7GFBus0bs
tXa7x74NoVvDOv16dK5Bp6co4kem5MjsBMqulNnb5qAiSRSAHjJVEcbgiN/ejphUzKhhnQ2rLlmR
J0srKz5SDkt9GoLIIQYs5LiQz7IybWCgpgj6AsAgzJv8o1wGzGOJFcuutKhU3byY8gX4mvT1mcoL
+oV0fltqMUZ5+7fYGYXRzx+IoKYTulFlekV7KaIy6pn9anlT85vVRhfq3tNZZRGuUALVSiHKp1Bv
hSH5jlo6taMLCDODPF39Tqvftq6OemOjXklUiPQyYpE3hA7qrG4TTmxYZzDSMPUrCpTcgg6vjYA+
icfYFMU1pgr4fLmYJ0fROfPHuGJh8j+aeRnjdDL1S9T5mRS4VQFv2nBpMet9lpa4++KbevKGFfwJ
BO0QF4h8xYmLMoxmJE4LfilYtw9dGxV5baelDnfq58HheZD2ds1QdE7sNtEpXV6y/daqe+F0IrwO
EggItvtulBViDAFHzzEs4Ors+9e3U7TiRkh+FQouUA4zwFshY6xGA6Dbnol3ZBzdaBUiUM72DESu
4f8i55WEiA1ksZPV3YoWd/4fFxoy40yp+YAThVsC3PUgYwIJd+HeGGy4QmzfwbeK+mDAR9fhkgPx
nzDL3LV2Gv3HmCCLPBRF3HWk89YHpBOvD6r+uOVfqkM48561HfV7l3A6apzVHxEOEh1IyTyiN4f6
3KVzCDqCvavPKeaSnkFs20XLbL+sYELy1lix4/B4BOvvSBa6muSI5EwkO9IYHRp4SldDU/BoT6Cf
qRS1nv1bScZ42MttKPlYo5C+D45g6wpNReoA61TtaIEPBZNYtLw4TsZyYTF8v5ZzdClRynhRzcCS
TDxMcqXxYDSNoJqUrB7zcYe4AU3uO+Tj6wXoA39LLbsKtK1EY16dK5eicLPwSoFRhW+yHzcF2R0r
WPJGyuHI7ddZdu81doAYgdtje29f2PoQ7UdSTUx5TaBtDIJ3Rj9hzUirGokvUqbl7/aQny41+3XL
F7yI+f+1hfB0KztcysNAoH/Ef6mEeMnfNIZ1MWfgKXi2mHySkygQ6NWZ6vvA1E4qyMJXH6Ff48/K
gOLCxf9q2hiWqZQnp6Xn75CfUcw3BVuhzDPyLdr0RuUnInmBo6zzYXmuhUgWD3UZOwbOLMbQde1E
4+ppigWbA6D8yjjDH5d///Ez3Ge5UANdGKtn5+zwt6sVz/UnNbLaIxHavGC/XYYHjVzK8UBa1goj
rRjxZYq+/vP9jTUVM/We05Tuu6Vhr8Xqgqbs4LxdLvSY5ZRtfkiZ4ZCcUX6PAd4EH3/mr2iiXXwk
MaHxtETB5c92jL0MYVhAngHcoQp4PXcVgMM53uyhUPz7f2ILQV2YDlsJucEYfDq13cpM0FlEQd0h
5mhrSC7d1cT9pzwN/S9h7Qh/HzA8ELwUmuPuJDo2/TpqVz3rFrdQd6zrjucPEC8bNXyMJ4KKbI8D
jSOb8qPFWrNmF54vmxSvOh/OuuWoD9f3nVoFgkV+u9aHOriGCvKVf9fo+9RKQjPtDXcFXUfhU3Cv
MzmWBqGndqHMPSFCJwZft7uzO4LOPPH0VfFoxWhRynQwCPBocMx6x0YUJV+M3EFU6Vu7E3kJrFsl
y1fn4yO53dC25b8g4zcCCiBPZyfjr/dEPpI56AfsYVso/JiXvsCGk4Q44hgxk7E2o05UqQCMycBS
ygQjxTdflOik9YO+XOKbMzwwOKB9IrJf7iEl2lQF2K+TkGRUH4+zgS1JhcVqHPMQR+DJxVpWfM0M
H47wPKt6giCxmkkimy+FeHTdZ6hz+24lzsFu3UbXHAwWbAtim+kz7tWoUwDCuWtRez90LMVibV03
s9OTE0S01WDnqkPCfv23N97xtDZeKpUclYjzfg8WN4IphB+xKA760It6EE+vAg6sslhPeEtILCY4
Uo32QdRhD4sEjjub54P8JzSNxRxNbgJXU+8ynehszPSEyuxl5dDi1AscV5lkhXQ99VE3kbMI8ilh
QVUy1qYXE9K5fiRAV0MgOjL6GGRYoTf4n43A3FTs90xm2IHT/tG6dfy45aY7VCkDyOLAsNg6qbjb
S+am1g2mbZSI1nM9RhmFc/sBTe78Kgm7HWfCi6EV9WsWjqKGa5AaRsASsm7bd1npnUKXCxM53zTI
77Gkmb968Gfj1eaXjJQdf892eoN9RwJPsCC18O81xXkHoHW9rpUzV/NkTfGJToNKY6n8O/U/gp3y
AG4NmQb+ohRjIbQrMorHExbrqsFGL4eC3yc69mOV+v1CTYsqda7U3Kustm/djGTSpFqDUaNUmNv7
s59H+WB4s7H0P4v0ac2cjyGb2JiekKYXjqytCQsMiVJwOtyNM7tOjPKEr5DFyVazHv2pRLOhaGVG
87WLyoRqDpuHLeZLjrkoa33bl1FYrCa3J6+jJ7/V3xNnIZQChJxZvKwYAjZaE4fMV2ZZJnThqFaV
jzThXMsUKhts7V+pxPK+9zyGMAfbJb+gqTodEbZFGJ3uAmuFe4/D7u5r4ULee1EtBh9bcw2j+Ola
cNtHZu9ufBxtKXSETdazieWpvDhS+w9bsCl/1kwyTaNvigZTEXWAX7zN8t/Lv3wG6d57wx/BxB+E
F8OAUdaEA/l/kXOG0XbxRG2wQEbzuLgDFSmrE62VEjJinXmf1q7lMpmlsJOGH0t6Vpx6OC8xz8e0
9F6q/ODk0dxRYn1TlLWz5oHLnk5CLNiWA8DqRrYx16q9uzU6zk/7a2dB6MGsTzhiIU00omSXkLY3
uhJSd6oKTQspc9w3uPCrB095lhsz+vGhD4iM4/CS2HsS0zXvKKDnVX6r6sYwhAYS1txJn8cHejTS
33a3FzrLh/Lr8tihbnmzdHQJtk+sq7tZb72rWrEbk48sbF9yJahsTCRqNmxxIiHoM81CkKoI+Lxh
cfc0D5Yp/MomiNvkLGAQL9gJNP3W0OyucO7MynZvbq3xjQW7UGuTkM+U7elqqbUSHoc+YvoRMbS0
Wra3OUa9vgiPvfWOPUXkCzQ+GZz5oh+zUdgV9KFSEg78gDsnyyeW/ilBD6TtAk9pe6QKH83lGlA/
2bWItSalCQk+8HJxYzEowKqYFGa6IaIc9tMb8mXj8fSJrYpmGSaaPDJJbiFsHkgzUgKFO56A6/eF
ldbJbZmhU48DLTEq3y10q679uNFxpRjMbj1VLTSaUJ5hhfLgA9jgL7ku8ypfmsyML/AFtmtYlAYS
x/hfNfqd/HxrFDj4suOVtrsEgFli/p8rQFuk8bUKKi+qMACYCmucfH6KPKuWAuxGCuqam7J+SLhy
F6DV5jjns6q2TiCqwQ/SFDGGwNWkiXwsljkpcugaJxrggWO350nMbF0QYxh1wDeVmRmPTvIktQeN
C2vym6ToRxoNYTF2Tp4Y99bkBeDapsuHhs2C3sEBcQs8X6JL4hEvCnkrhPhAFYDvUWiWd97v1xEF
JXyVXUJkVG9BXgkFfhxRC6VBtIUPWaRXjsqkEhgA4GfNh9Ato1kt2NsNy0Yk0TuxhhyZVCo9JfjN
xOUbhJqEzzlTH8+IdmNPKx43EGDT0Lrsk/UOaUPBvFWdb3GqIMg4TchPjXgWpuyR85DLNpqWKB3K
K2K8dzks0hfLCIP0o1ZrJyaV6vTRLX6GDJX6JZRDQIcYVYCtM38a642Um1FZz9czprkChHqQfL3B
NzQrdtyK7LIW3fUDo5pKTkFMk/BrlxVPsmRbDFKf4rxCbgZA+dTNUmlpBauC7VYTM5YFkM6wgAQf
kvhXW9lkApSLz8wKN03C6wRC66r8yh/YqKG+OjTUsFovJrTDokQK8MgWGIzpNPRCNORK91DK5GNY
HEXIaZzdLIwnRbeaVleFh1M2/3aFZkINsBeVqebQim1r/XodkwvYfRJymSowdoWJn6/gXjWYYZGh
nHpo+U87TYAoe/0bNSftOYIRvEYmlBQPHk/YuQ7Jdb5hXqiv8iaBtaRv3kWfgGc6JF0PyuLIJmQz
sePGBoxGEAi/gTPFAp5q7bYdVvVh+ebZ1KPCkgVP67PIAZMIBdM7ytHOVT5vyhBUSnzHGj7tsaK/
AqD6UoWrkSts4FsZnh9O4M8pkE8Vm26V8YWdgHnDnz87zqQ/CBdX9Nf6pLsk7Gm/k4IQqgnaYV3Q
djGKNtk3QKG8x7u/AfFVjfC3uxos9Lej1HjxSt7yMGU5UStm3a89d3ADmdllSmHXG8oaJwgC5yD+
6ZyoV+S6O/inHAAITWTqNss+CZq3wQ2fSPRm3iMIYujSFh49ZWF6Y5hhATGZ7puV05IkX1gc8Ela
qcxST2cD5iqJ2QwgOpu3pXIdq8sop2UlJ2ii2/Ct6PF84r15S+LX3gLwJ/KnCGF+GUwOWmRkx3Hu
v4EWljx5OFiNNQjpL6/VF8J8mZgV0Yatyn1p4Zb53UROPaTcM7aRopMguRKwhgpbxYt/+eTJW6XO
DU2onCq+kdiW47TN2oEGrRxvPPPOq8/oSOfJtP28+4j2QIWKpNEEkyM1waSHRIK9ySAFcsxROSmZ
y5VUaZHpge4mjt4o3wek/wS6MwWVPMsAu3hEPxAU1KQr/u9URt3MMa2fLlo4iYegrEEYe2yLrrAN
jfOlfFl2WAfnBn0q9dqaZPhtJGkjLcv87aMFcrI8E5sRxgPWXNHe5E3yM7fFaxtQ9czAwy5HBQ7T
gJgBJSPfEfU8e3x0JPGyrdeTDJ3A7ttFutTZr1mNDvkDS1bKipmWU7JPSOW9iMIXgy8z3KaMV17o
y3aq0spIkFtfHwEMlx5tdEz8T/iwPwSqX7cnQdq/VsqDUNNb4SVzr+cYcHaGI1VbX/0HzDuMomQP
8bBDfD6NPr3YWlufkhrsbQfYW7WwfFtn5mraBA8+uYpAnFvNL1nN6ushsbMR1N+vSXjcYN5NACl/
H2124SzQrgKMKsLqQRU44LOU1vbHbBKDecnaquvebNH7p2feemLLqYcfbhQerM8RTzfGlW92BjUa
pGu7s0UvPCSvVvGLI6kKWChXl/Ug0dnDJutwDJbPGIIKIcK+2NPBDWx7NvZcgk1vLArNWzWWN5i0
Z8dDhZ6CzgsX9JZYvHPLyXwjLrgSDXp6EkJ3xaVltlxsSPjIWuSJ5UR2t3a5j70+y53DA5hawRIJ
BflpJHyKmzPzoIY+XozhC5geLbq+MLSTkXTA+Md2N7j1po0WdpbtlNFxKyHKeOmAG5tXoFNxuonX
NfKY106GmQh1ErXt/sv1FnwsfMlB1zi1P2UI7BNRKZFKqOrCBbJHJCnZXGXx5HE1jHd9qZY8pcf/
raU+1iunjRWFwqi0m4Q/8gbHQTiFqXI0Vta3iD7PfOvOLzc9cuejpa4JY/ddtS3kX2TIpZRySbii
XgeFxsoRZG/o05PSNLi9egYTmlUgVS8d+uK+3hIvzh7l7GM7KBHA/q9Nsn2MXkbuM26NH3qxiAea
Dn32PsY77N/kRaam/N0h1Zw1y+Yze0k6Xo7SvXAa3PeIHINvxYjsqA0DUbJAr2qJQ9ez9vPSqTOB
Dhbd/08MfHVAhXHpF3fM+00YOk9kcYkG9Ri/eeixt2oEDZaKzJLnnoqvFxeWkGjVuZfdk5dOu9v7
ExEKEHZo+ZvJiEXLjjzmDtZFould5AIW+q3ME1xdRFAo48yScl3GdhltW7oIIwCbxONHp6pPH1DB
UKn3Dh2Z6TWDBMdTMe2/L9TS7lojLF/dKkQy/l5IxcOXSsyxUWAVpL5ZrB9DtijZUUpLiHlAFei9
Y9Z+k80OmqZhY2yO5s8R0ALs1Ft48o5GjKhCgHF72iPb/y0d1jf95FfmUoxwezzrhskMaOCfFgg8
AphxbFX/k+52qiLuQkjtJScwGnNfZDEzWfMjSThKXVI/arwQ7Tn55JqubDkyP18b3uYJ3czC/KiX
yv+ED9+8d35HV+DzUtygwZY7rrisICcU3NFk7cc8i1jdolvkOva04x34YiSWT+zjbKj39iDgMJfP
nq1M1Ah0h3m9u3TgvvOjbzfU5dUNe5/RyIdK0LTLLKGFZO1jZL2P6ntEgfg507gCdVHVavN3mTHX
IPwxe6Y6aJ52LnrwSvqTlTplUK3PXqyywVm3ukSQ8najZI5ITtibqu8sJzJxPESP1h/CGEy2irf0
tKuFjzq4iUmlE08KwGR6AdQ90uUyDZ7BInDpap0TUFE2yqj+Cmg/RLdONz44miMbIJ+DAxSUi2MS
CVoaEGRDgZX7L+1GCwlSyMt9OauSexn2E56pMGI/A/PNjcGrIdxkutQoK2YRlg7i6f+wNb9Y2gcM
YzNWLYz5uyo3rNjHRcKm7HEbiWcCdoOlOc1k1c55wLySin4bgMGuA9UXa2pj15QXYNFMeJbtfhwm
ar4+eZn5WyZ6Q7DhbN8CKPpHO9TyDPvVgQmrAQcWSBAx1hC6wirnvf7ATJlrz+DmfHI9E026mId6
KH40lG9jMqfrWu7g7s8wz6nIBiamEhcd5objUHUEmMKbsASQjGVhZA6QbCbgAukMJWUtjQs3kGXc
FgiOMoJpGeYNPE8MJgGTMl4eB3OVuQh36cD5wqXzYC8GP17NZ/0WINIk6TBXOsOpv1WCDSwhzshP
zuOsK8lBIWHJFZMEZp1ygQP/cGs0RyCqkD8ulUBTV+K+EZcy6DXjw67oee/ALKZrhgkjW/cAGZxd
eGZowjoQwZjMCPMMu4WX0cMnUwzIo4hU1IQi+ktIpNRZkliY3/li31LBpNye1mMA1I1p7/jq9Rb+
No3LbhHCont+fMEy734+6OiLsjBXts+/ro+qRqYFtjyT+k0RFo619T77Yp2untdxkjuR6be0s93j
vPwKi2VrjYaTCJbKSM0oj0YtWmM4nSWlNLkS2h2rjbGdujgcDPlU8I44Bo2G1oMGiCui9FodkZtG
kOBqtjbv1R/z+321jpGACzq25FPJUSd1xst7U+0GLp/EzuEpptq4ISk5nnvG8OpY7afVlV5aPFsj
MBQKt8uSzd/dHgxVjmPeqp1cV0WABPcaLzC/ehxbi04Q
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IVxyk7XRM4VsQcD0QPYws4xsTeDPKdwWYfreQJ7l1z8C+G+JAKZ2psrNI+b5ecZ2ziPH9MBGr/oY
8XtzCKmjJw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VO3Jpo4aYF9TyVwyAUb3a/oDy8Yhm9ea/9mAjNtuOBRL0qoy0/CWzL7D+bc1SnZvEP4BG903Ildl
dM2y4TNyVTBUaU7Cz+LzZfu9kCPWnmttlx92LcMKLNuvGUMPXmV5jr3PzSFEvoDuCinMqNc8uKFO
Ux/aX6fmBD8AbQfpK30=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qOkimDe0rSU5f1zKvoE8a4lZw1WOOUxh8wtTIN0ys09AXuQuNNCdfu6VL2Xuj0Xus09sBU1FazgW
XpQHuw7XcozHRlnUFKPJg2P12yPJsLRkOqUWtHTUXmH/8s2RglOoEcmFeX9FVh1IRMdnp+D/F4GX
/80OwH0Jtm4eUDa5EFkNoIfhlOG4JOG/JCsYRnsAoZAbyHMEk6qPxdOGDrYzkbA3CMCikTuE6wOm
0j69ZgENzpWR5aludQDu44oKZqgkdMKNm6Mvk//s2aUOTBYWabbSKe/I/+cEp1tWS7+9AAmaVwO+
KwmsZsNR4Ztb6OH4hCq0936o+bycwR0b+Wr1VA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4df1QYXbx3PmA5i1scwSy/ZAJgZ0wNtl21eeCeUI5h4IQD2UalJOUkc5a5UR/j7lX9ToyF2yFHzK
L4EoH+xXm54bGihfoaTvocQQsWhCDObbmBOtqB6WS1/bog7FNgoEObi/E19vJsjPSd6nCCdhglZ1
j33mJRkZed+lVziTR/s=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Rtu5N6w0tnewss9ZQUyM3gMzu1D5Ba/+qJO2rdGgk0QN5Nm+4TaVyiEXzVM5DP8z3mycaRD+z4HG
QXarW6RH4GHKahoLlSY8cryjSJRWS6D7/Z1joY2fgJb8apydMguGWjRZ/uW6R7BEimGxB3Xuon63
ZdpcvKZmoyvfg0kjAjor/DxtP3SP6DKxH3BeegGQKpP/+5EmCrAhhPu+NA21340wcbghotvyYusJ
ErSZhtj+1FLwV2sO7TUt1etBG8nf/yETDQPE7Q+zX+BzOktmY3tIKds/9qdyDt6Qb5WIxLMyaMa3
eyi0SGAuZdeDtK8Os3w2ajEZI+VjufruVqtCCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17760)
`protect data_block
yvvRtu+tA91Rtyv3I35O4K6BiUlBjs7LTFLRc9twWgYZkATXrSpXZut2NlvE8mcC7mB31ueT2vlU
P9hzhGYaJ5GcmScpsC1FKNndMfl3Ug9Pqiw49YT0Xp/AQWIr+q38Pu2DmkLm87YVBi0HN6JMSu6G
rwJt5qvXJYVA5oSnqcy27I93z0KCdBaCW4BhEaXbMLEY+qzcYsWxGhgjRzVfC2OhOSpdpDr2MKHw
1YDri1cTZAVy/b3L8VUTlyQx4YRG+qS3u0Cz3dOLm9nglzh9Pa9XJC4+Lnpli7w7vpvakaXaH9W9
I9Xs/9ShuVul4UrHUMsoz9V5jcPh1iHPT9m0ZTeLUdfod7NEEFDW47vWU8XjL6iEqBvA/DrJKrri
hjJ//n7fbl9gjxGZT+IKqHleRVz+dRiS/uTuRo22UsAcWrLoCdroE0x4MAJ9vC0vScZa86PQBj0m
ixJFhU15XHesAUmaWmkIVFZdUdZL6n63C2nZpQmpBX8G1td46ib/xrjcP1HPzbr1hPb30S/GA95D
4e3ICss1yPb8NZCwvzZHNKYRJlVJ6EOWwDxLeBOjWmUySMUcywo+toi8FWztPmB/Fzs/gyRSBxsb
FBe82kj2NTjDK0dD4XCcU8bGjVOKNJ3KoJmC+0UD0jihX5N1CdPg7+/bvmP+MCdk3ondXZKJzYI3
9YFYkr0RM2BhF57jZwHcHHmFJrakmG38Lap7lsdonuIO5mfOOuicr4JGW8Qijs1+c7VMc6LUwGDt
YKznnHTq75vwwVLxmtGYpW4RTIuqlZmOJwC34kp9oVx0+wFtUxMvQgXry9FwUwb2gSWRseSfbmMB
auDz+22lW+enEoOu3PzG3plNq4oQP2K2H++ZU7HNTNGSA6VpJWDQ1c8o+i7+XEkyIqt9DZHUxb+3
HlbwgxRkMYX88B7lb3GnNDLF2YzkJMgQjpyPi+t3N2MtquCFuqNuaKv0LoD6+mwRceg/hAylp3x1
m9DKQ0DcKuhctFlcx3aOGMXc0mzgjh9Umxn2Ng7JEliL6/L086w36Jar0AAtsKsXZ1NsDDBpiIeT
c9pWEQj9ud2144CtZKOT9/hr1wy8/jpi1lQaHanlWWtc/eb1aDpSY58hPbltVjUTyizUFFWsqQAC
PGoqDXF3N036pR2Ipsz0lKGQE6qHOZ9IQByoJkJfVJQFD7arWnGsW4G4I9tdTj8LBH1I0/XQKvur
lSNx9C6iPx8J8GemXPHqEIipG+GgoeMURYc7ft3GzrBdwbTFPm/qrxT/0vdju3tRDBl4JSzWO+do
z/s/CD6wNYNcDBCSDKcprRdML0+tkUYr6Jexl5rxIe2GBG2XGRgBDqc+wBSNJY7VVfutmSr3NjPK
RJK5NldZFn8fT/rjewbLV4flhMn1tgsE6HhNm8GuRS52PpzP+BK3fCtYvb1mnkFy+e3mwc3RgZ45
5iaZGmsBwnJwI9GcgMGoWSDkSaL/1PrI03WtUczFAidTPvIY08FA8CTdX8Bo/j1vK5yj8spVzrNq
2YNw08dzyQOA6p4yaEO8Raki3qlKk9oCGUe72zvHFj8EIo6DPYz7MTOBMZh7qLr1JDqBA+iyQCSU
UO9dElHR49OYArhLqejxnXEbJqi2McLLRKhJoiH7B/feWKz5mjNEjtWpHgiwx6VhyEKkL6UZ1Rib
ZtiEI9gtUbhZ6XzaYm3TiIRoYgTzxH0j8bAv7Zy61YnOi5ds35hrlF48AdxPXK/eT9RxLQ9JC4D+
xhLyqoQdstrt5DgaM3NxG2mKEJVH9uc9wj8j/rmn9YrBedhVek2F8Uvojvb9UP2S80Gz13xgD5DT
uHlDBG0pjratONtNE06BnMLwZRtD8fOAmitaJqr+uurpGUSmFSP1C9+FHTWgzBTdRwxLO8vYdEOz
WFiLspZhFCxJpRdUt6N09XI21qtC+0+ZgVoJcuL102pig2HCGw+mVSkibp2ZzBHApj3TyyQWeR0T
soE6qVGrU0cCA6w+mgSp/LpLjFALA+nFAG3lXPvfyzy3nWkgcWbCXiItZJY+SdblaE3tEF0j7zRy
QEv4a8Rg+L6tHbS4IhpoHW2u/3VbDszbEYb4sRKfYUA0hAwJaM8jOAxyu4YRtJsjn94Jek1Taiie
hp0Ndlnhy5vlx4q5I6i8Nc99UyR9uhRu8iqRtT7nCYuJSAzDby3Uxqh6srwmKPrb31KF5pRhTgEE
hoDR5pRAhvr+p6GEHRm1IAJTB/vA3Cmck+beIM8DaYRIdaZnzC9N04oH+sWVHExAUc9WW2ZHotPC
yowKFvokfu+7look6EHxqKtkI6qUIsFrQgy755fSnh7+GR8EVZFKqkRCDv0zQz3m3MIaUQ9GzxNA
nVZg02l+SgGZHXvy8wOZE4ONpWcUccgX9k8Mqf2VrJEhn7FTdwr/L68VLWlWyJ51gTID4qsEbmQR
eUcVhXwZ8J6/Jr+tfQkihSE/r9/FrMS9DtCeXZFSTXFkRXX3jwy08FYzVkX1AU3nfi5uob/pWe44
jJ4c+H4TgTK/YFd0U9+b9+hcQ/PKCmyuUWlZMD2jh2m6YaM0tRHT7pTE3k+5NorK0KIzBPhuhR0P
kwadh+BfDa9Ed/g8FI4r9aO+bzUYkbubz1m2BkiyrHNUN4b/jhDQyeuJYsvVZmik7vXZ6GcS1rnC
ZJpUE1bWR8FcYhqQoncmXGI126qn791BoIP3g9UyBSGDJ/hK/eFW6lylhaaJjjVsKepmxGzcVN1B
mCwVpKVdTSGBmK72htH5om7KKA2S1rC5U1UUj3MbiW7ZNwfDd0USkl8imBDLwgYFtoEE1ko8C7Jc
eUprl5A05bpIwcNw4M1zuvcSJzD1rtWdZQl2vo3uekE+ox++ptfYE1O4Xj/2TqSRnKWmvElAWcGk
d1P93oZ45PNjviXZ8GjPM3O0qWdvlgjvAq0xdzA6x0TysB9PpseLW+g8nB6svNvi0GhK/LLkeLYg
V+VOQradYifDOr8PNb0cqid1ncvsR8+c0tlZfcJr23pLfcE3Vqz5wPmHYoK484/vAUmQUEHiXjLv
MiKyjk8ywnYHQ/TOYWuO5OiF3b4XtDucLmEyRzxNB7rY1i7qaj6wGs15PP5RLOMaDOI9Kg6163IT
YHmjt12E1isvBtgqS4df/zN19hcUsAr+Hd+fpoCiaRD8qfZT7eD2F7aDUpS5tVOH7gVSyJWqzQ5q
Obv9Yhw7rja/O45RtfCLUeQNveIdOxbYJdxtkbtNUL4THMOaUooUKNDHf2XRJ/IU29P3yYsch8DL
w6GDueFKcmhtTaLLsoIw5tztfz1OnR/Ji8//265ufazAczEkWZEuwDJ820UjB8sYf6rqgnsGaFMq
k4/RqF2vivZ5ejxFZq4j5HxYIkrT0dvfR14iHiz1gFBjRkaPy0KB92AudlRi5GguJSj9i9apnV0C
9Q8mNjw2IhqKOYuyV9e6QbBpKJ96If+glayPM19wkoNu3wYrQpc35Fto6fYKFdY6dhE8nKPhcitV
/uItKlA/SbBd82Zd2+R5YPNcmQq0sWFXHgntGjncAGogKw7gdfoVMOM8623k3ZSxgx+hl1hERb55
2VAlad1Z2TVWotbB4SU6fYbYbkgvMzH5sJuCqbAAKfcoPFz1nWbbyWa08tpLEd7dFgSfxRMD6emG
vbRwvFQQjTUHayp8X4YhTp75/cn7s7BNav/nMANVwbzv+7PlcCBDE/FAkBmre/mWCARVoeNQi9yk
Lmy+/QFbBCSDmgH9dT+J0qyptUReayys26DpOx3zpnRbUVqoevpDLpdsoEIttEWQIhHlgFCwxqwE
aRk/jq630RhYJrspYYhMKJx7vBModJIEGer5px3GFiyOMr4+4I2Loz4N0yOCB4NxzVtMSM+DMFzb
Yqmp3TY7W03MSy4BUlptWvy4cfrCDCrea8duJ43frMTKFTfbW+IerIgRfu6o1EW2xXm1cTpBK1C5
GDw5N3ENOo9k6+Og7Rv6BqrZrvmt4KofAZpoRQwtrvIUEswUfZzexMH0dWDua0IDEUztjkju9U3k
MYVajimuyW6IXCYU0qQCvsz9sBM2LLZ1x1Vup7fB1Ec5aPwU/UHatOkTm3aX0ZLYdmaCrVM88w9G
XHeo1x2sSQwb3bclHeYGqJ5KFtGY8NkrjA2kOqD+X2jo651hd0o8X/ii6dRA1MaQa3XRL48KOtEM
HH0PUmnhNz19o5YiXS60R4NMyF8DBJ2arUQqgtrBdHpYd+zsNwOO4FJe/HVkB0g9fp75mEMH5PiJ
iCp8PJo1jsqW1yWtRGUFGwq3z88uUmySC3W8F4jZcCA/IVM3H1z/nL/Xi6GkPU3ho614p2M5bRq2
14TEYUDIUMMz5OS3VFeKp3NLgKmCpVj7tbmiZi9T8Yde5BbWfETD2YjKPY4NPYiw4TNz+908oHc2
yTbewFueWvL/NaEUrh1xMwQw0DRkd8xsxovrukJPMeMMIOpJVuHAqxeQFIhjwyO05shLRO+8ICOY
lVC8RDu4KIeHaBIdj78ETsgHAau5157cMpNdCv1z6u/eAEhsPNaTpoYf5z4Ulz5+vbrw+Ig6ywPW
AC3chkAwdqF9uooKaqUaS0uaMYKHDaK2y5UfVCBUcfko4mCk+jjZbqPR4oE/RY4mRKF+S5KVRb51
goeafsPpARmOwOZcbpLNMXGonqOUJEFV7nFBn0sn+mMycGAzE+JXd2B03sI8g6vqICD4805s8/Q7
Q9RvYQCBXt2A6pU5gu9eZBujlJ5yteDEmqSPNTNLHzUtnYMoAcOjjRN+mnEfti3CP2YaqZYc7AEK
EmGhccCK28g3Iq3fyEIwqSG5ZMQqTqoqd2RXD5hdEa8/QoSw8h+tBDysQ5iCskiecYnVoVm2sJ9g
EiFptSQHJIy0hyW5bqu4IBzo173gYuxltoA/x0vJsCyFYs77QhbyJAFsJLmGHqO3cT9lndY5RmIe
G2IsYZVzwYIn/hCH0vy7GSobNYDvEMIvGBaU5p1UTsf1zLoaBwNW5il64Rmt8mWVqr6Q4Cv07zk7
YKXZHTXhEeAgsPcWekKsDPhosTQ1OG/Lbmqe6Xtt932gr1mKpZC9HDG0zXIrXY+2oSE8WilO1BRy
J88nrrr7Yu0oYnF4wZWHuAWIyjgLKyWWX4IP/WRaze8T+DWjRzYC+x719Lw3Own8W4ws2iTfKhys
/AoSQctmniBEUleebvUzkP/54oUfgrmlSFnT+LQI1wpo2T+VfQtutqXZD+Q9onWKVVV4HeEbkZlD
NiZEFqgI7BCHMNKvyQsr+gN3d1+ljxpDWwjLTifh1kNDK1FTX628L7Esv/ze15vf2ojo/9c1/gl/
t1SV+B85OJEVM2ghrmoVc/L4ECZPJK0ZQo5F/4K6TFqIGKCvu6JvWCTXCXXQuvIJWVCf3yQ+xB28
CnIRjnpjYhPYNojhQfb5Zv+GZ7LFqZZ1/o78veE9yuWl0lUlNLkf7AciAMp2qc67QqLSzbmp+IIZ
GRPGcMLDzgqZMu5UoNLRtDcIK4IdO68RfVU+DfGj7azU8UasdLC7EXFxENSmQ/djh/0I4Ci41R+q
wsa+kmx3eYs+rFXPF/gpMof9+m7gcNIlaKRiKrmGwaefZwbiLS2b5ZrIZ6dIXfBst6s3VP1CYaaa
+z49NTCU0GqV80EBrXnRQ63CMSRECEHoQlN/WGzyaldjxjHPYO9Hmx4A4l37hy0X4CBEgwcgcLmn
2IaYATXcAYJj2x+86KLB5ybH7SyK4Ew14BYjahhIhbE/HpiaKw6srEVCnQJsybU/L8kpmLrJFJJB
A7L0H6rsyqypQ0Gw1vYRNT/Iq1SfeeCbJucKyPaC8FIIMxhLscoBs871BAGV6PnoCQwWlPdh7wt/
cV+rFe76p7fOp7y/iWBGEIZ3hi+nWA/1wg/Gwy2n5z+TL5zSsOLvSN/UaFnaFFlJfzsshhbbzRjm
u8HmR4iISYlZfg+PuCGg4qWDzTm+W3rHe0IKKFdTl4GXGM1/EpTtOAqbIDIWKEIZkJ5l8b15nkSy
kXA7m+xG+B2kCr6obeLcnH/Kll+3TvkRO20Bb17nVNUb9o9OAtuAZf0dsN0dkMWVbDBmARX5RrB8
Xaso0jhmy2GD0839FOGPRmjq0itlZIHy9gyGxFuelbdXGBP7YJlreCebt5nS69xLW/ntBMeaobHB
+fuRF9ZeLz6NIAjircenBW7v07uWGziq8CV4rmH/bVbBQVpgNLXkN8+irSvzIih6+uQU+4qnhkGf
6DPM1CIN42m9ynyzhboG0MwLmsmxfHNu6W7pdDbuQK0nD+bziOLzzqrXLBnyPXGnwpO2QuvUEpHz
JbvGAC0fH3+ZHVgO2K75xWmD0ckLOS8k2Z5yXiDsc+mex5g46t0h1hrH4Yyvs+xHhn22sZ5vmAd9
z+TAxX31wRoiRQvb/b9h8k+DfNRbYFTRb2ARM5f0wglZ2CBCHU3UDca46UnCcX0s2i8dCJiik+U8
1YIMvzM1YeyL3p4mMj0N+JIFkUtiWw2Iimbj4Zp6ofh5N27FA2Lw2SNpuIQppGII0um+Cd8fl8LJ
wmvWzSxiUir0Ax11Yq2EPE4jm3nKtv2sY0E6lx8WJYJydjXzqOwe7I/q8cblI4Vw7LJj+vuX/Vac
5mEUxAfQSPmHwmPnz7dWxElLo7zN511DK5ZEC8GBtiK9/m3RoIfI1+3Csl/GLaL5uWLV5jg3nmav
Y0x1hldBRI4gGM/8vCOKB1q8BY8TbeB6wETtrgJDpKK2w6lzrgVWA5wHTPjCuFeJZQKurXZeL80g
JJpIX8UxxYd+U6Gg7ji8gqW9cjciYoznCFRSJAcwiV6/RLQ7TMkMWTU2UPbgRRUhP5AJaTlsHLBG
kDpRv5sUys85ONbc5+pksLhtG+6Vd/mWvnomEBms1/e+jX8+Af6n98WPo67PSdCntlBBB0GpSw77
A58uptTtJh3ZnWGQRMSuQLMvad/WJZKosSXA1e4gAi8brVgIYmbIc2kzpFVAw8CT8ZJVQt0dh7lh
8tVc9ifnMjHMk7eBB/kSfTmYqiH66g/FPPIMThz2zJc8uB+JcA65L3cTruK5TAIZfFjQsRhDD+jo
+IQSPEMe5sSQGn6lLvuEYseLQbSEswNwE1xM0mWOmQTgipmdzDR1ApQU7CJ3glXHI7CVSZ+Ptc0x
tMhQKU+3nMUBMdbrbWczDZr8+LtuVq79gy6RjWSEvDiU8k/C2jfU7gvAAhYeQmEWA2ZDfrBZGMUe
ctwS4RKrBsgrdotouRos6i7rnUYet3BfSROrkb0kSdMZRGxAyAEEU/HXaAAC8PBph61GdBPOjY2o
ucgy4/5j59ePvr2AHV13YPvzcUThetgzbOE/iQtfdAyChyoVx/t7MUXlzDXK9YyFeO5akcWlv5cV
/tZmdn+0Ip2LqVVRXFEBSoKdQdXJdPtlxjfAelCI04ov4YoJ58o+t0nhwgO7bkbIx87oHNgrzQ2M
F9Nx7WUW7kGIwr83dm82aDD3MxmSYxoppKine4XFBSQuB5OgrdtAHhsoSTFIgdLrqVtjPempXbGk
sAGCyeTTFU5G+XjRzr/5F6bDtFizNprxJBKDaht1ZHz7ETvgFDqUE1wXMVV/4EQdWo3mWO3IzFHy
MHtIRlXUch3GQNXGHB3VG9FfABO63ISUv+i8letcphRuJGaIqd6D140yb1j9b65V/pllsmcXjxZI
Ah43oD+OViZ853FMzqnn1m6QUPSsMZIRyqrAz1NPtluN+CJrw1FCZVpiTakwpdxU24wYPLdzkJVt
MpfNjTp4CfPgAm7JSZ8uNwQriV6W+lMhO/nOlWDmWdpkvsTuaEmfMCDUgnSLOZS+lGvmuwQqc4c7
zpaP6+TmfafMbg199BGBGKHnAzZYORNMzqGduqQH2rfIjXYsYhgEvrviZ02MrjLaQZP6+Ut5Alf8
E/kL+HVFFRph1szoSkmJ7EBXybrGUR5qMCQirKzjN+9O+mZGlpjLRjEm9OvwEI2YBAdnbEy2PUIS
EppQU9iHilUApIhfes6nYf+wBw90smvQ+ggytyPZpyUuHI4qtFg7oOfeQJsHmMUTERb3j27kJedP
2tYr9qiiRWvUkdwJ4KJwqWf4pQgGognpwYEamf+1nPv2wTMMQK8Xx/yjdn10Y0/KWTAYXLQMmYjz
1frZ7sNr9m2G1bncTeAGzAAYatbj5nvolqrKxgG3z0xhGVUVc40Ki2Nepm+7jD8G0IY0ml5LLddn
YbZpN/8M3Qhx3Xq5oGiH/2TnC8sMX0iYn2UCyLxrWczitSRdquyZOivyQrbiaox+Q14RjH2RZNd5
aQF0j+++AlFnkxA005oCTlPjkpfMTIc4RxeeLQJ/tOK503oFkgsrCogo+yF12lnKy6igucSzbMPn
3Wor45sypUNSbvvkuBCYT1dqOqZXmmu2OwrJxxib2arzDMD+Od3/2YCFIL50cnXvoIjhEB0DXR9K
/K7a88aV7qbJ4DHBzJ3f0XIdiFQ8SQgz7J1rbVBgheu6FymoZephdjJLqZb90iDDQWVJmojtbzXg
gFOUIz5M7rwsn1szvg6OQvvyk2BO7F4pzU/gosxylIy+ZgksSmVFg/qaV20rZ1k+aSKwrFaoQyeZ
RFL+1rHpj+IbGKJ0T6azxeZPrSBdULXO4GIJdvr3Qb7m1uZp95FUpJBDu9qVsBeW+e88fCT6V8gX
VS6NTuR49358rzHdu4P84iHiJvQ86U9hTj3lb3jjwQAZN8p0kHLIhJ/OK3HNXw+RTjLj3vFhUR/i
IRh025GWPgCvLKW/Fcjs6l17Yf4iBubssKiYf8wlCs3fcp9iubVKMP7pRHwefSdGrCymu6kYmLgw
mqeCa1xHRtdyJWo9Qe40/RZF/z5wrG4kAL6/QY4JsNK5IuaqdL11AZL2SCSWi+If9d6xMChOcgdO
Kz8rL/ul1zVN4v9usZdnQoWuT37LkO/XTV67Fotcg6wt/2SklpnESLjZ8scuc4uMPNBaKqJxjusu
l1vSBAc0RfX+94qdKAB1kZkl5L/0wR4MeVpy7u7MCHssLTOzpzCO9upNisBXiFFPDC00CfVouYZN
XXF0RkU9ILKEeChv27SW6Gi7Qy+jku7OC4OkwVTtOeSe3uN21fa0MxUAVDqDcSYih33eUdQ2UgQt
L6AkF4QraqjCQmkNLaNY6/FADaaIph2sC0y2v4R6EliBhBDUC/ueMaaLEicWDYdky6CenbfyuZOC
Uvu3Y/IwIV5G1ioj22TVv+/LM2NMXlM3efeBXVFLlpk0glMoySXNMXgPIwpcUbWKr9MvEuUqvHfU
Ua+EPFCKPWY+MPtNhxODgEaf5SD42ilmAXixVxbfQgZT8KDy5ESHSevUnG4beDCiUOx2OxSZYEd2
WecJ3ZL6564z/G4fc7Om0ZIOU9ng5EgK5ufct/8wDhJxhrKfWKF8oGMAz/NIeDg+KDpnnOd9TWC8
m1C/nAlPRFVJESuKzp85N/iFta4ERlbMXC3KbBhJx19efD9AzC6BaiST96FqCaEQ0gbAZg+5M0vd
sd4uARkYKVZ+saEmK10NttpOf8+fMTy+o11z0fGYxK7evc99er/Gbpf39qG9yEfmAEVRfphmZPIn
SQf7u15eABhrE65ulYC9cW/1kD9cckhW3Ca6Fmggjt0dr5f0xyY9FGPQPcKlXF41lN5BHyQxsQIA
iGo9RSECpzORa/a8M6ZNFsEFb1RNk7PIJWUUTwA3yGJ86kp56QxDSwHJ3pphqBtvncSbkJA4qxYe
VYFrqoPM2y9CnuLtBx77VYq0P4lNlDZj2jk3mHJrjUoyGQJcNWMrbXeusyvrDBumKKKJuoCp8Ji0
/RMJ+8HFg8+R4uKqYvpIJg8NyYQ8vYA5vtYccRW0jvZP/i0U6PWDFr9Jttd7mvkTVOZWVQzQwIa1
CX0sZXUqWjeUdWRk0PgpbprIfHUzRGF/71Zzu1yRW2GCnx767EQ5qKMpDIk0GPjYaqO4xoSoi9aM
1yz/MP17scsZFRtDTEX3mlGXuzvOXzoZuF1pv+cx/HZyvxTWVigsZvXDBZjLh/wgy0creA+fBV1k
8fkV6zAuCk5dk5WqKFfYd+1UeCPMcZKIBp4CT4CSOy97C7PdZOfTtjBE2N1HOoaQ2ZxOQQfwlT7T
fBNkY0FZvjuckL0I+G/gCuS39PwVULFYbFIzpXBM1Nbej2d5BRC9Qd2AZu9sxMPtcZKUu95Tnwhz
RLTAtWmI3jpVmutYnGnpM5mKwhhOdMO3VOC5v3YpF592DzT+6/6Acs5ks+nnzpA1Us36PVKcWGkE
M1WjUqhQAuy5AFtL3rF2Roudc62UHxBXUcrRUznmTU0m6HWy5ij6umKW8aSGQEAuTFkgHG+/QK3t
lkny9IyYFmqLI8pYvOJTBRa/mUHj/dj/6NbKzslOo2YhiygO1nVPUAcgCQY4cgBaV1HZAFPnSrue
xDDcyoDCQ9XAq7HtK2PK5zi3RkeZ2APBYNWexQi62G+cTV00wfk/mJEXllv7M1McZl6EYNB7w7Wy
NSFsKlLu8YEu9N+Kz6RKVjxTNxRK8PL4e5PF+lnFbOzA7pjA2WZ8s4rN/GBsDQxj+iRTW9eFFwkI
55pwh0HyA5SIW3FjpJUf7cIrlGZ4oEXT7+1t1T2BK+cZECsvU3yQPWI0wujjI3BHqX2Avcr6Gfjj
Zt/BOCeLm3WPYbVnr5JtETvK2x7GxSyH+9LMO852zV25Cd+48P/c6S2Kw0ca728Ny1Y6KGbL3qlP
4EvN/TZ7etw5UKea706IUXwIQVwpP5jQ938y0oHDYwffAWQlBszHIVreDFPDhRH7grduFfXwkAZq
Xg1+sBIztw+hxqlMs53QCz42G+g9RWycycylepEsvcSk9fVNm6VmgeZfgi6X66giRnNJpU2PIBAF
TmbPAcrMrGqiw6Igp/NT9dLv+HdaubjRbMktYivcwKhtfvRJxOMuhYot4wWlUUavaDQbJmW24VmJ
ZwCVPPi6rQ4Nhst/OnX8HNiq2U/gTHWXorogGqfyr8Y6nwQ1i/rMdmxoA7b/GE1m9P5/B6xamFQg
EwXo+CxJrOCPsGlEdrtI/EomayDvxVj5CfvkkF3AfbS1sQsfyGGG1tUvsuzyG6HbCWTS0DgHLYKw
mLw/kac2HudY+pRGugwjN7CsZhMmmjhzcrMq0IOLuASVzEQ07NRtu7qYo3gXq8qnNgGi3DQKDYrw
SYfT6Pwt/XDOLV/1Nwm7lrkBfprfCHgW0qbPVabJczWZCD+LcxtBQw3gU2094NvU7pb7yPhlgrq0
cS5wrnWHRgkSVTP2nTdECUOf2uvdv6UAYuKZB+WHxfuNgMuJy+NNx5KfDuofgKn+lYGw6REYH3Ka
ZOfYztF8bAdIPEvwSawpzhGQAiNBWeC79fEj8BBPy695w6r/wK/tqaFZeWkyTtf0I3GsKFAFjoZf
KzKY+NxdAAJi0qPk4lVk75CJ8kptfpPfFywJQmfyBb975TcM5vpsuS0OLQ7PPrjlQ3gHCKvA+H4n
QPQpKtQRoRv3axSt2d5bX+nHX7sDe0XLK+YohWnf6W2r8ED9onbhdOXu/KX2OHKoCbv/dCpO3JIs
yPgJIlcsES6Z7VNPf7AG2iCOhM8IJc2rkfWNF05kCosrhh9zj72ovE8RIohjbE6NHLiuUlA8oede
e6MJsIbj7L6BcoK50YtZJ47mkqQ53XN8aAc4J/rI7owAq6S9g50tYefm3L0nPbuCGWHERzd2gjBj
eixz+xrcNM7tnJIQKf3BHG5GEXQzMr8loXRSFArDmZxS3+X0oRJlIt5ZBx6wPaJLw/47C403FaVO
IQ7rKIj1J78aFfPu3+RUWyAxXdSUla9IOrNugivXxl+/pixnEdfqFhdGh7sINrMDr3Gva7MydLld
aT6Xxy2ZXoCIrn3QUJYKAx8iSWuYEwP4DqSnDEcIzqyptarJmsEalMCp9GrYMqhCwNqKhm7QFRVH
EJZYkgW+8UMhys0ogbrtFGbOrQzAPtBJbeUFIniW3mJQMXc79i1yiE21ixQ8ixak+mrYSNslA3e6
hUZFTZJoh5xpuHQYY1nBk5twjasanafpLNUSwBeNbZ44LL0/WMXxVmEI+OffB5P3t3OhAtcLuUmq
dmfqUu5wfet7GcTzjZMame10OMV+omk6zhW4JKpGLlaOc5wx6/zoGhGWuaT+cWFv7j06y/IK1Ge5
VwYmkjNekZd73ikRPgWbiiTGW9uE4WwlB6bawr+FtFUk26pt7kv3iGZfcaexkYk3gFuoCjMatcxm
5iJBYNcSz8AWR2X2L+XKSxtSf0hQgxgqoTL2UfsFHmKChrS4gCUThdVlzTQXUx4eyHaIJJH9DnFE
M5L/7tl89MeROUUOeAtes3QIlHeFFHBL/Ji3cfap8ryGMN1/gtgWdRFkXnoX+G6hQhXwma8qXikA
LWFDlKPRFEnz45o+6OCrGzLwe/otDBFLGfQ+GWVpN0kV/uZQ75Sf0e/PsUXpFnaLewiSKank6gwi
8yF+WH1FQE9YQ18xUl4fwH8mizCAxcpFYsA0t+RbSUT3n/4OMU5Qp9o7PN7lBGRIO5p6cMtXRnXC
JfW5MAwmEbuYLebmtXFTuJDEJn0GyquYWPiwpRZnv1ziMZpHifvHl8+OztIxJd2mYoB0qILovXrv
p+sSoT6d+Qt2nOaFyPi/m6CB3U6EZTDb/lY9CEtizEw/HAA/6VwkE8uIX7K7vI/hr2H0tduoiiNC
Z7Qlv61NGDw+Zsk5lf/EB3d4KiMTGGR+U3OwHtOnm6VYC8rcu1iaHeniGKq68Pd4RNabdW0SEWBG
SCsEB5twlwDDXXKD7ZjGPdrzFL4xeUQOh7FvLbwmC9sr/yhddMvrFkA2V9wW905QTisuA8OW3JSB
AUh4iRU5p3eIXnK4bV5DGLg5qrBMXKp7ITgTUsrz1GkN0djgyFC0XYoOcjI7B/yHlOip+3I0y4mv
lvXPbxrefN6gyKaXEaeKqc8lkTrapgWmcul9IqE2dc62oipP4yfF9dyU9mxlW10geK1g24KEyzGo
BeRphtKG4Qmo+nfR7liloRHvowONq++DWCDl7U64lFtPGM8DVJ8L3f2O4dZ63W280QNqOHfM+D3v
oYV1BCKRuIDzGPh+aSQpVALS7SpCpa9vz5n7NadTJvhdFlHr4KfuJX3Dh2oImi+n71N0Qn84euc1
fOD4vRyV2dyrbvpf8ZyzqYuhxBpx4gleNeoUIVPfagb2FoQQ+bskrJ9Fzaop3uYeyYjVHHz9Hn/v
kD96iS4c3YZAm2tkHGVHg07+rB7CjCZASOlDUuBZBYy/Vf49Oo6ZIbyPX6zKW1HIZX6TCXgL2RMD
Z18i6bS4dVWdamjHoVM2FEWy0zWmP48ZzqIofGQ35eZ/S/W7DX9ElshVXWSoz2DnttgcYeQP85Uy
g9m+ziCUZIcadRW964AoRUA3+eqQFMd4s3bDuqBW3XcuFpHSRPXh6t0Fs16Zxakn48FFt53gPuPn
kWccmrUbXLvLcqhA8NtpSsiryUclKgessi+7wqGZwaOZ/56iVBpZqOJwABqb37gDS4naRX5Lhm3s
m3HaTaYcXMsCHqn0auTQIir/uX4q5UPZFQ8Bz8UC3UKxfj5ULvWsnpZTirNjNzizmAgQT8RVbgzU
2G5ppcdSvbuZsNpQGRd4Pb6lyI9TgsK+1nbLlHGhemrdiL/34MiuObwmSLc73QRRBxNgFET6e1Lv
o6xWN/l6TErNc+6EiEwrxgHsEDYFHeG6qnW1ueS9Lpmo4/z7e+6wy6Tl/b5WouFHRr5e9BLEbuxz
42BX4dBB1w/PfHqyvQ9VWKQ2jLS19zH4agGu55yMenuP9MgLtErIMJT+Bl4ELPGwB6MlUUqTZB3t
VQC2OppjbtSjETZroDDv09xkwKjiHqEFViOwEy3sF9EdAetnX005D6kuc/K3fTbQi+m6fMRiKN2Z
BiUYhf8XENvED3ZMQxboABD11DmJ1e9Fs74DiyxWCij5drQwOkqqstt1vqKAB5y7Yfz7BEDaiFt4
N/hwftM3GyDIag16EDHX9KUEehn7+WAQVjm8M9q3X05bEsi+YJzDYvQ1YUMmCywjgkrU+we6Zlfj
jwHfaDlARpdR7SkNfEHejmsi+v6oKmporsGFi/PV6Zto0tsGqVmsM4rG7ACZ9Rr67LZv2ZBYmau9
YMgEVa7MgE7o+XRH98+6g76U+vPo8sDSXBzjLxrUWj7LbaLAwHwCiaHAk2NE6S11a38XlxU9q4Rc
V/ZeXX8H7FNqwpWafLtSUSFGjVEl2UPuR+LqiFTtg5pDbXTI3RUZ/1FTQXdKgs8mgkiZobQpzFE/
rrjhpfu5U2VFgUt175KUgZwXZkH/mSNkaexiOIwbfcsZBAy/tKw0ZMHpRgmxVxs6aDNEnWMppYML
mirp99KtxeiB4YkVvhoCIgRH9rd9f8SjF4hpmqeG33F+I/8aGa/B9TDn9mIOB0MkA9G27OhNWHti
BhiDpachcuiKHNRXtROW2tZ6QSKltulLhEE2tKS5ySwwxUggM23fjcafEriJsOg/75JPoP0f7KSD
GKya9azUZuLQNLPDToOlCvYyOgxC7DwAJSzAineFxmxudrjNaala4ME5f7ber08k0H7a98KpnWhr
7Wj2/ZJ+vEdRg5LF5JobYzKvmpaM7hGgOO0Y0TDtIOO7HUt3HbEwZQnXW67gaNwbS1SMvRGswaYx
K6wkNU8q8NKtgBuc+BLolYfLBZRJcyR4yNDpU2ZjHuWIT4ts/OFFXInD84SDkSXjHApALHfZxsnt
cTfPbSH8fDmCJm8Vuoqw1xgU6RGcrAVPTlI/Bq6t7tCPO+YaS7Zc7owdZvEsNMbqoZsmDCFe8doV
8cVthfoNVR0f3SFwHIhWyLqcudCO3w5Kbmclzjof/qugz7XI3W4up1D76MJKqi3dcnruoFlabFxm
tSwx3GSlL+5B2O2YixhTq2xSfw1sszftRCihJ0NMSoRqkcjUCZWV/isTBo0MmbQfNmdasTOjZ7ew
2BGPXSHQT6V3s6XY14QEqIGMHPF5erZNNQZhY8yMaHagYfd2U+nuwBd7aS4EyGQFpNTw3QcKE37V
hGX17EZiG8Wq6MY/44BXOfTCtCeKo/byhuif/pVMsu+ca4R5zGuY3CiVWYEsPvzxF/qKifpxZi51
XRmtFk0dvxCb9LZijwdOxnyH8ZiWDHs7mJnDVpcWUMPZU8IvqumksK95mbWFPl5LqmMFM0jEs8PD
mTfV2GTjPFDNIyUlS5wgr5mAkFV9aGhFTJyxgym8HJTFTPnH5yHrrcc8JJLtN4hU1di3Xn1fE3uT
opoRvS0bdUapON9OlwVhd26jM7wCZBYB6trMJ8Mp76myBkkv39NINwvcNz0C9PjTC2KxxPuukWtR
w/yhSCjv3HZENtmeUszZgrIUGEER9oAiD+owYoWYlewK0ILXabNAqrhmEBqBHrr9oqgbcYRDzuYy
tXp0TFqhsCtk673OJdQGB6Oio70EYcvfK2+/+lQbm8RY3MMrGTIdFT56B/KY7jNhS0GK2TQxwqhs
TRZFKV/ZJk4siqHTytH15d/JDe5gR0ZT6YLiWctRZ0o7rDFAuWGOts2T5plZkYkKlicuij/brRUE
VoPwjXc21Asul2nGZ4oqWITvNNvqsSj3pZcib/NkEb/ywxjqeutPrWHdY2z9bYYV0afl6iN+OJPF
mRYM7kLjlkifzhHkjMHeNI/3PFm0mygSZsjtHDrFRcYjNY27pFqwHt2ydv+Y8I0N1SDHvn9BLNJu
oFVKeuo90KYeeut8r9DrRTYqFOonG2OEQDDLAFRufZ3qQCoZzCVAz2808ZTxpmyZlUrqqRB5eNoR
fjg1JW2zKpsRpYXTmNQeMRdldk+Feri5oq9cGD5YRVbI8qXrgCFVgnHaSb6bgNKjoxu7ljGDhDlA
fyljqWnwjpwLnJrnLEEPxCA0T5/et2QButOgW3nnwmS1l46RTyIuJvDC37QKPJAoZiXW3NONxQ4S
VMkIxUni4WFNp61+I8ALmhKWYBMnSF2olRUJgjx/5EoFbnaRnuG71h4SLeOPIDGWQZc0jBwrQoy/
p39/L/g1wLZ3FqNDV7qggQZ0GMY0PqS78funhvJ8e59DeuguR3c8Qw2C0tcThu571K4wpX/OFbnY
beeizjT0zdkHhRSex+8gBUGhTbaSXFA+qwXR9xCY+C7zYRTKO8Nx+cPPqtw9pP9PxBswmjqhEKt6
3Ck/ADyCLZdGREp/A68XVGVvHb/JvfOg35vhDTnY5YS2yaSxtOlTrfweIjcpHNm/KYIfyfc8tE37
vQgFgsHKTN1WfK5wTNKf7aRiY0HC8102JHI+A45viX2RWjDbdLJq2Y7F5ppx0BUGXajkekHFHtTP
zGH4mWnc+ZM9cxpDbZHg9CWY03g1SIePCaPv+IQWravG0Y5/FjoT60o3H5FyFBudgMVZ3cp8VzJe
LvD1NXLx34aC55OogymYf2wimfHqDswutWmnj+tuNMEDOInqQNq9UcHM/OyxxtX8wTTT/NRUFeVm
VeKtfofxOPU4GgEr7q/dgpmmyUwpJdTmUIWgEo/EFBgHOpfX6wnVmKNZLK/35u6h5zONTzL/dQna
H6zFQ6I+cQKT5ug+al7l3k03OO7iBB2zXBSdPjOWpTtDodnsbHMw86WcpUsjoqFkiDJh0K9pAiTs
yu0YtLXYhpLRc8vLx+nlNPLnBlewheD6Rsel2vUITR+Y0R+LTIVcFizL3RkCWpgT8Mv7GFBus0bs
tXa7x74NoVvDOv16dK5Bp6co4kem5MjsBMqulNnb5qAiSRSAHjJVEcbgiN/ejphUzKhhnQ2rLlmR
J0srKz5SDkt9GoLIIQYs5LiQz7IybWCgpgj6AsAgzJv8o1wGzGOJFcuutKhU3byY8gX4mvT1mcoL
+oV0fltqMUZ5+7fYGYXRzx+IoKYTulFlekV7KaIy6pn9anlT85vVRhfq3tNZZRGuUALVSiHKp1Bv
hSH5jlo6taMLCDODPF39Tqvftq6OemOjXklUiPQyYpE3hA7qrG4TTmxYZzDSMPUrCpTcgg6vjYA+
icfYFMU1pgr4fLmYJ0fROfPHuGJh8j+aeRnjdDL1S9T5mRS4VQFv2nBpMet9lpa4++KbevKGFfwJ
BO0QF4h8xYmLMoxmJE4LfilYtw9dGxV5baelDnfq58HheZD2ds1QdE7sNtEpXV6y/daqe+F0IrwO
EggItvtulBViDAFHzzEs4Ors+9e3U7TiRkh+FQouUA4zwFshY6xGA6Dbnol3ZBzdaBUiUM72DESu
4f8i55WEiA1ksZPV3YoWd/4fFxoy40yp+YAThVsC3PUgYwIJd+HeGGy4QmzfwbeK+mDAR9fhkgPx
nzDL3LV2Gv3HmCCLPBRF3HWk89YHpBOvD6r+uOVfqkM48561HfV7l3A6apzVHxEOEh1IyTyiN4f6
3KVzCDqCvavPKeaSnkFs20XLbL+sYELy1lix4/B4BOvvSBa6muSI5EwkO9IYHRp4SldDU/BoT6Cf
qRS1nv1bScZ42MttKPlYo5C+D45g6wpNReoA61TtaIEPBZNYtLw4TsZyYTF8v5ZzdClRynhRzcCS
TDxMcqXxYDSNoJqUrB7zcYe4AU3uO+Tj6wXoA39LLbsKtK1EY16dK5eicLPwSoFRhW+yHzcF2R0r
WPJGyuHI7ddZdu81doAYgdtje29f2PoQ7UdSTUx5TaBtDIJ3Rj9hzUirGokvUqbl7/aQny41+3XL
F7yI+f+1hfB0KztcysNAoH/Ef6mEeMnfNIZ1MWfgKXi2mHySkygQ6NWZ6vvA1E4qyMJXH6Ff48/K
gOLCxf9q2hiWqZQnp6Xn75CfUcw3BVuhzDPyLdr0RuUnInmBo6zzYXmuhUgWD3UZOwbOLMbQde1E
4+ppigWbA6D8yjjDH5d///Ez3Ge5UANdGKtn5+zwt6sVz/UnNbLaIxHavGC/XYYHjVzK8UBa1goj
rRjxZYq+/vP9jTUVM/We05Tuu6Vhr8Xqgqbs4LxdLvSY5ZRtfkiZ4ZCcUX6PAd4EH3/mr2iiXXwk
MaHxtETB5c92jL0MYVhAngHcoQp4PXcVgMM53uyhUPz7f2ILQV2YDlsJucEYfDq13cpM0FlEQd0h
5mhrSC7d1cT9pzwN/S9h7Qh/HzA8ELwUmuPuJDo2/TpqVz3rFrdQd6zrjucPEC8bNXyMJ4KKbI8D
jSOb8qPFWrNmF54vmxSvOh/OuuWoD9f3nVoFgkV+u9aHOriGCvKVf9fo+9RKQjPtDXcFXUfhU3Cv
MzmWBqGndqHMPSFCJwZft7uzO4LOPPH0VfFoxWhRynQwCPBocMx6x0YUJV+M3EFU6Vu7E3kJrFsl
y1fn4yO53dC25b8g4zcCCiBPZyfjr/dEPpI56AfsYVso/JiXvsCGk4Q44hgxk7E2o05UqQCMycBS
ygQjxTdflOik9YO+XOKbMzwwOKB9IrJf7iEl2lQF2K+TkGRUH4+zgS1JhcVqHPMQR+DJxVpWfM0M
H47wPKt6giCxmkkimy+FeHTdZ6hz+24lzsFu3UbXHAwWbAtim+kz7tWoUwDCuWtRez90LMVibV03
s9OTE0S01WDnqkPCfv23N97xtDZeKpUclYjzfg8WN4IphB+xKA760It6EE+vAg6sslhPeEtILCY4
Uo32QdRhD4sEjjub54P8JzSNxRxNbgJXU+8ynehszPSEyuxl5dDi1AscV5lkhXQ99VE3kbMI8ilh
QVUy1qYXE9K5fiRAV0MgOjL6GGRYoTf4n43A3FTs90xm2IHT/tG6dfy45aY7VCkDyOLAsNg6qbjb
S+am1g2mbZSI1nM9RhmFc/sBTe78Kgm7HWfCi6EV9WsWjqKGa5AaRsASsm7bd1npnUKXCxM53zTI
77Gkmb968Gfj1eaXjJQdf892eoN9RwJPsCC18O81xXkHoHW9rpUzV/NkTfGJToNKY6n8O/U/gp3y
AG4NmQb+ohRjIbQrMorHExbrqsFGL4eC3yc69mOV+v1CTYsqda7U3Kustm/djGTSpFqDUaNUmNv7
s59H+WB4s7H0P4v0ac2cjyGb2JiekKYXjqytCQsMiVJwOtyNM7tOjPKEr5DFyVazHv2pRLOhaGVG
87WLyoRqDpuHLeZLjrkoa33bl1FYrCa3J6+jJ7/V3xNnIZQChJxZvKwYAjZaE4fMV2ZZJnThqFaV
jzThXMsUKhts7V+pxPK+9zyGMAfbJb+gqTodEbZFGJ3uAmuFe4/D7u5r4ULee1EtBh9bcw2j+Ola
cNtHZu9ufBxtKXSETdazieWpvDhS+w9bsCl/1kwyTaNvigZTEXWAX7zN8t/Lv3wG6d57wx/BxB+E
F8OAUdaEA/l/kXOG0XbxRG2wQEbzuLgDFSmrE62VEjJinXmf1q7lMpmlsJOGH0t6Vpx6OC8xz8e0
9F6q/ODk0dxRYn1TlLWz5oHLnk5CLNiWA8DqRrYx16q9uzU6zk/7a2dB6MGsTzhiIU00omSXkLY3
uhJSd6oKTQspc9w3uPCrB095lhsz+vGhD4iM4/CS2HsS0zXvKKDnVX6r6sYwhAYS1txJn8cHejTS
33a3FzrLh/Lr8tihbnmzdHQJtk+sq7tZb72rWrEbk48sbF9yJahsTCRqNmxxIiHoM81CkKoI+Lxh
cfc0D5Yp/MomiNvkLGAQL9gJNP3W0OyucO7MynZvbq3xjQW7UGuTkM+U7elqqbUSHoc+YvoRMbS0
Wra3OUa9vgiPvfWOPUXkCzQ+GZz5oh+zUdgV9KFSEg78gDsnyyeW/ilBD6TtAk9pe6QKH83lGlA/
2bWItSalCQk+8HJxYzEowKqYFGa6IaIc9tMb8mXj8fSJrYpmGSaaPDJJbiFsHkgzUgKFO56A6/eF
ldbJbZmhU48DLTEq3y10q679uNFxpRjMbj1VLTSaUJ5hhfLgA9jgL7ku8ypfmsyML/AFtmtYlAYS
x/hfNfqd/HxrFDj4suOVtrsEgFli/p8rQFuk8bUKKi+qMACYCmucfH6KPKuWAuxGCuqam7J+SLhy
F6DV5jjns6q2TiCqwQ/SFDGGwNWkiXwsljkpcugaJxrggWO350nMbF0QYxh1wDeVmRmPTvIktQeN
C2vym6ToRxoNYTF2Tp4Y99bkBeDapsuHhs2C3sEBcQs8X6JL4hEvCnkrhPhAFYDvUWiWd97v1xEF
JXyVXUJkVG9BXgkFfhxRC6VBtIUPWaRXjsqkEhgA4GfNh9Ato1kt2NsNy0Yk0TuxhhyZVCo9JfjN
xOUbhJqEzzlTH8+IdmNPKx43EGDT0Lrsk/UOaUPBvFWdb3GqIMg4TchPjXgWpuyR85DLNpqWKB3K
K2K8dzks0hfLCIP0o1ZrJyaV6vTRLX6GDJX6JZRDQIcYVYCtM38a642Um1FZz9czprkChHqQfL3B
NzQrdtyK7LIW3fUDo5pKTkFMk/BrlxVPsmRbDFKf4rxCbgZA+dTNUmlpBauC7VYTM5YFkM6wgAQf
kvhXW9lkApSLz8wKN03C6wRC66r8yh/YqKG+OjTUsFovJrTDokQK8MgWGIzpNPRCNORK91DK5GNY
HEXIaZzdLIwnRbeaVleFh1M2/3aFZkINsBeVqebQim1r/XodkwvYfRJymSowdoWJn6/gXjWYYZGh
nHpo+U87TYAoe/0bNSftOYIRvEYmlBQPHk/YuQ7Jdb5hXqiv8iaBtaRv3kWfgGc6JF0PyuLIJmQz
sePGBoxGEAi/gTPFAp5q7bYdVvVh+ebZ1KPCkgVP67PIAZMIBdM7ytHOVT5vyhBUSnzHGj7tsaK/
AqD6UoWrkSts4FsZnh9O4M8pkE8Vm26V8YWdgHnDnz87zqQ/CBdX9Nf6pLsk7Gm/k4IQqgnaYV3Q
djGKNtk3QKG8x7u/AfFVjfC3uxos9Lej1HjxSt7yMGU5UStm3a89d3ADmdllSmHXG8oaJwgC5yD+
6ZyoV+S6O/inHAAITWTqNss+CZq3wQ2fSPRm3iMIYujSFh49ZWF6Y5hhATGZ7puV05IkX1gc8Ela
qcxST2cD5iqJ2QwgOpu3pXIdq8sop2UlJ2ii2/Ct6PF84r15S+LX3gLwJ/KnCGF+GUwOWmRkx3Hu
v4EWljx5OFiNNQjpL6/VF8J8mZgV0Yatyn1p4Zb53UROPaTcM7aRopMguRKwhgpbxYt/+eTJW6XO
DU2onCq+kdiW47TN2oEGrRxvPPPOq8/oSOfJtP28+4j2QIWKpNEEkyM1waSHRIK9ySAFcsxROSmZ
y5VUaZHpge4mjt4o3wek/wS6MwWVPMsAu3hEPxAU1KQr/u9URt3MMa2fLlo4iYegrEEYe2yLrrAN
jfOlfFl2WAfnBn0q9dqaZPhtJGkjLcv87aMFcrI8E5sRxgPWXNHe5E3yM7fFaxtQ9czAwy5HBQ7T
gJgBJSPfEfU8e3x0JPGyrdeTDJ3A7ttFutTZr1mNDvkDS1bKipmWU7JPSOW9iMIXgy8z3KaMV17o
y3aq0spIkFtfHwEMlx5tdEz8T/iwPwSqX7cnQdq/VsqDUNNb4SVzr+cYcHaGI1VbX/0HzDuMomQP
8bBDfD6NPr3YWlufkhrsbQfYW7WwfFtn5mraBA8+uYpAnFvNL1nN6ushsbMR1N+vSXjcYN5NACl/
H2124SzQrgKMKsLqQRU44LOU1vbHbBKDecnaquvebNH7p2feemLLqYcfbhQerM8RTzfGlW92BjUa
pGu7s0UvPCSvVvGLI6kKWChXl/Ug0dnDJutwDJbPGIIKIcK+2NPBDWx7NvZcgk1vLArNWzWWN5i0
Z8dDhZ6CzgsX9JZYvHPLyXwjLrgSDXp6EkJ3xaVltlxsSPjIWuSJ5UR2t3a5j70+y53DA5hawRIJ
BflpJHyKmzPzoIY+XozhC5geLbq+MLSTkXTA+Md2N7j1po0WdpbtlNFxKyHKeOmAG5tXoFNxuonX
NfKY106GmQh1ErXt/sv1FnwsfMlB1zi1P2UI7BNRKZFKqOrCBbJHJCnZXGXx5HE1jHd9qZY8pcf/
raU+1iunjRWFwqi0m4Q/8gbHQTiFqXI0Vta3iD7PfOvOLzc9cuejpa4JY/ddtS3kX2TIpZRySbii
XgeFxsoRZG/o05PSNLi9egYTmlUgVS8d+uK+3hIvzh7l7GM7KBHA/q9Nsn2MXkbuM26NH3qxiAea
Dn32PsY77N/kRaam/N0h1Zw1y+Yze0k6Xo7SvXAa3PeIHINvxYjsqA0DUbJAr2qJQ9ez9vPSqTOB
Dhbd/08MfHVAhXHpF3fM+00YOk9kcYkG9Ri/eeixt2oEDZaKzJLnnoqvFxeWkGjVuZfdk5dOu9v7
ExEKEHZo+ZvJiEXLjjzmDtZFould5AIW+q3ME1xdRFAo48yScl3GdhltW7oIIwCbxONHp6pPH1DB
UKn3Dh2Z6TWDBMdTMe2/L9TS7lojLF/dKkQy/l5IxcOXSsyxUWAVpL5ZrB9DtijZUUpLiHlAFei9
Y9Z+k80OmqZhY2yO5s8R0ALs1Ft48o5GjKhCgHF72iPb/y0d1jf95FfmUoxwezzrhskMaOCfFgg8
AphxbFX/k+52qiLuQkjtJScwGnNfZDEzWfMjSThKXVI/arwQ7Tn55JqubDkyP18b3uYJ3czC/KiX
yv+ED9+8d35HV+DzUtygwZY7rrisICcU3NFk7cc8i1jdolvkOva04x34YiSWT+zjbKj39iDgMJfP
nq1M1Ah0h3m9u3TgvvOjbzfU5dUNe5/RyIdK0LTLLKGFZO1jZL2P6ntEgfg507gCdVHVavN3mTHX
IPwxe6Y6aJ52LnrwSvqTlTplUK3PXqyywVm3ukSQ8najZI5ITtibqu8sJzJxPESP1h/CGEy2irf0
tKuFjzq4iUmlE08KwGR6AdQ90uUyDZ7BInDpap0TUFE2yqj+Cmg/RLdONz44miMbIJ+DAxSUi2MS
CVoaEGRDgZX7L+1GCwlSyMt9OauSexn2E56pMGI/A/PNjcGrIdxkutQoK2YRlg7i6f+wNb9Y2gcM
YzNWLYz5uyo3rNjHRcKm7HEbiWcCdoOlOc1k1c55wLySin4bgMGuA9UXa2pj15QXYNFMeJbtfhwm
ar4+eZn5WyZ6Q7DhbN8CKPpHO9TyDPvVgQmrAQcWSBAx1hC6wirnvf7ATJlrz+DmfHI9E026mId6
KH40lG9jMqfrWu7g7s8wz6nIBiamEhcd5objUHUEmMKbsASQjGVhZA6QbCbgAukMJWUtjQs3kGXc
FgiOMoJpGeYNPE8MJgGTMl4eB3OVuQh36cD5wqXzYC8GP17NZ/0WINIk6TBXOsOpv1WCDSwhzshP
zuOsK8lBIWHJFZMEZp1ygQP/cGs0RyCqkD8ulUBTV+K+EZcy6DXjw67oee/ALKZrhgkjW/cAGZxd
eGZowjoQwZjMCPMMu4WX0cMnUwzIo4hU1IQi+ktIpNRZkliY3/li31LBpNye1mMA1I1p7/jq9Rb+
No3LbhHCont+fMEy734+6OiLsjBXts+/ro+qRqYFtjyT+k0RFo619T77Yp2untdxkjuR6be0s93j
vPwKi2VrjYaTCJbKSM0oj0YtWmM4nSWlNLkS2h2rjbGdujgcDPlU8I44Bo2G1oMGiCui9FodkZtG
kOBqtjbv1R/z+321jpGACzq25FPJUSd1xst7U+0GLp/EzuEpptq4ISk5nnvG8OpY7afVlV5aPFsj
MBQKt8uSzd/dHgxVjmPeqp1cV0WABPcaLzC/ehxbi04Q
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IVxyk7XRM4VsQcD0QPYws4xsTeDPKdwWYfreQJ7l1z8C+G+JAKZ2psrNI+b5ecZ2ziPH9MBGr/oY
8XtzCKmjJw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VO3Jpo4aYF9TyVwyAUb3a/oDy8Yhm9ea/9mAjNtuOBRL0qoy0/CWzL7D+bc1SnZvEP4BG903Ildl
dM2y4TNyVTBUaU7Cz+LzZfu9kCPWnmttlx92LcMKLNuvGUMPXmV5jr3PzSFEvoDuCinMqNc8uKFO
Ux/aX6fmBD8AbQfpK30=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qOkimDe0rSU5f1zKvoE8a4lZw1WOOUxh8wtTIN0ys09AXuQuNNCdfu6VL2Xuj0Xus09sBU1FazgW
XpQHuw7XcozHRlnUFKPJg2P12yPJsLRkOqUWtHTUXmH/8s2RglOoEcmFeX9FVh1IRMdnp+D/F4GX
/80OwH0Jtm4eUDa5EFkNoIfhlOG4JOG/JCsYRnsAoZAbyHMEk6qPxdOGDrYzkbA3CMCikTuE6wOm
0j69ZgENzpWR5aludQDu44oKZqgkdMKNm6Mvk//s2aUOTBYWabbSKe/I/+cEp1tWS7+9AAmaVwO+
KwmsZsNR4Ztb6OH4hCq0936o+bycwR0b+Wr1VA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4df1QYXbx3PmA5i1scwSy/ZAJgZ0wNtl21eeCeUI5h4IQD2UalJOUkc5a5UR/j7lX9ToyF2yFHzK
L4EoH+xXm54bGihfoaTvocQQsWhCDObbmBOtqB6WS1/bog7FNgoEObi/E19vJsjPSd6nCCdhglZ1
j33mJRkZed+lVziTR/s=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Rtu5N6w0tnewss9ZQUyM3gMzu1D5Ba/+qJO2rdGgk0QN5Nm+4TaVyiEXzVM5DP8z3mycaRD+z4HG
QXarW6RH4GHKahoLlSY8cryjSJRWS6D7/Z1joY2fgJb8apydMguGWjRZ/uW6R7BEimGxB3Xuon63
ZdpcvKZmoyvfg0kjAjor/DxtP3SP6DKxH3BeegGQKpP/+5EmCrAhhPu+NA21340wcbghotvyYusJ
ErSZhtj+1FLwV2sO7TUt1etBG8nf/yETDQPE7Q+zX+BzOktmY3tIKds/9qdyDt6Qb5WIxLMyaMa3
eyi0SGAuZdeDtK8Os3w2ajEZI+VjufruVqtCCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17760)
`protect data_block
yvvRtu+tA91Rtyv3I35O4K6BiUlBjs7LTFLRc9twWgYZkATXrSpXZut2NlvE8mcC7mB31ueT2vlU
P9hzhGYaJ5GcmScpsC1FKNndMfl3Ug9Pqiw49YT0Xp/AQWIr+q38Pu2DmkLm87YVBi0HN6JMSu6G
rwJt5qvXJYVA5oSnqcy27I93z0KCdBaCW4BhEaXbMLEY+qzcYsWxGhgjRzVfC2OhOSpdpDr2MKHw
1YDri1cTZAVy/b3L8VUTlyQx4YRG+qS3u0Cz3dOLm9nglzh9Pa9XJC4+Lnpli7w7vpvakaXaH9W9
I9Xs/9ShuVul4UrHUMsoz9V5jcPh1iHPT9m0ZTeLUdfod7NEEFDW47vWU8XjL6iEqBvA/DrJKrri
hjJ//n7fbl9gjxGZT+IKqHleRVz+dRiS/uTuRo22UsAcWrLoCdroE0x4MAJ9vC0vScZa86PQBj0m
ixJFhU15XHesAUmaWmkIVFZdUdZL6n63C2nZpQmpBX8G1td46ib/xrjcP1HPzbr1hPb30S/GA95D
4e3ICss1yPb8NZCwvzZHNKYRJlVJ6EOWwDxLeBOjWmUySMUcywo+toi8FWztPmB/Fzs/gyRSBxsb
FBe82kj2NTjDK0dD4XCcU8bGjVOKNJ3KoJmC+0UD0jihX5N1CdPg7+/bvmP+MCdk3ondXZKJzYI3
9YFYkr0RM2BhF57jZwHcHHmFJrakmG38Lap7lsdonuIO5mfOOuicr4JGW8Qijs1+c7VMc6LUwGDt
YKznnHTq75vwwVLxmtGYpW4RTIuqlZmOJwC34kp9oVx0+wFtUxMvQgXry9FwUwb2gSWRseSfbmMB
auDz+22lW+enEoOu3PzG3plNq4oQP2K2H++ZU7HNTNGSA6VpJWDQ1c8o+i7+XEkyIqt9DZHUxb+3
HlbwgxRkMYX88B7lb3GnNDLF2YzkJMgQjpyPi+t3N2MtquCFuqNuaKv0LoD6+mwRceg/hAylp3x1
m9DKQ0DcKuhctFlcx3aOGMXc0mzgjh9Umxn2Ng7JEliL6/L086w36Jar0AAtsKsXZ1NsDDBpiIeT
c9pWEQj9ud2144CtZKOT9/hr1wy8/jpi1lQaHanlWWtc/eb1aDpSY58hPbltVjUTyizUFFWsqQAC
PGoqDXF3N036pR2Ipsz0lKGQE6qHOZ9IQByoJkJfVJQFD7arWnGsW4G4I9tdTj8LBH1I0/XQKvur
lSNx9C6iPx8J8GemXPHqEIipG+GgoeMURYc7ft3GzrBdwbTFPm/qrxT/0vdju3tRDBl4JSzWO+do
z/s/CD6wNYNcDBCSDKcprRdML0+tkUYr6Jexl5rxIe2GBG2XGRgBDqc+wBSNJY7VVfutmSr3NjPK
RJK5NldZFn8fT/rjewbLV4flhMn1tgsE6HhNm8GuRS52PpzP+BK3fCtYvb1mnkFy+e3mwc3RgZ45
5iaZGmsBwnJwI9GcgMGoWSDkSaL/1PrI03WtUczFAidTPvIY08FA8CTdX8Bo/j1vK5yj8spVzrNq
2YNw08dzyQOA6p4yaEO8Raki3qlKk9oCGUe72zvHFj8EIo6DPYz7MTOBMZh7qLr1JDqBA+iyQCSU
UO9dElHR49OYArhLqejxnXEbJqi2McLLRKhJoiH7B/feWKz5mjNEjtWpHgiwx6VhyEKkL6UZ1Rib
ZtiEI9gtUbhZ6XzaYm3TiIRoYgTzxH0j8bAv7Zy61YnOi5ds35hrlF48AdxPXK/eT9RxLQ9JC4D+
xhLyqoQdstrt5DgaM3NxG2mKEJVH9uc9wj8j/rmn9YrBedhVek2F8Uvojvb9UP2S80Gz13xgD5DT
uHlDBG0pjratONtNE06BnMLwZRtD8fOAmitaJqr+uurpGUSmFSP1C9+FHTWgzBTdRwxLO8vYdEOz
WFiLspZhFCxJpRdUt6N09XI21qtC+0+ZgVoJcuL102pig2HCGw+mVSkibp2ZzBHApj3TyyQWeR0T
soE6qVGrU0cCA6w+mgSp/LpLjFALA+nFAG3lXPvfyzy3nWkgcWbCXiItZJY+SdblaE3tEF0j7zRy
QEv4a8Rg+L6tHbS4IhpoHW2u/3VbDszbEYb4sRKfYUA0hAwJaM8jOAxyu4YRtJsjn94Jek1Taiie
hp0Ndlnhy5vlx4q5I6i8Nc99UyR9uhRu8iqRtT7nCYuJSAzDby3Uxqh6srwmKPrb31KF5pRhTgEE
hoDR5pRAhvr+p6GEHRm1IAJTB/vA3Cmck+beIM8DaYRIdaZnzC9N04oH+sWVHExAUc9WW2ZHotPC
yowKFvokfu+7look6EHxqKtkI6qUIsFrQgy755fSnh7+GR8EVZFKqkRCDv0zQz3m3MIaUQ9GzxNA
nVZg02l+SgGZHXvy8wOZE4ONpWcUccgX9k8Mqf2VrJEhn7FTdwr/L68VLWlWyJ51gTID4qsEbmQR
eUcVhXwZ8J6/Jr+tfQkihSE/r9/FrMS9DtCeXZFSTXFkRXX3jwy08FYzVkX1AU3nfi5uob/pWe44
jJ4c+H4TgTK/YFd0U9+b9+hcQ/PKCmyuUWlZMD2jh2m6YaM0tRHT7pTE3k+5NorK0KIzBPhuhR0P
kwadh+BfDa9Ed/g8FI4r9aO+bzUYkbubz1m2BkiyrHNUN4b/jhDQyeuJYsvVZmik7vXZ6GcS1rnC
ZJpUE1bWR8FcYhqQoncmXGI126qn791BoIP3g9UyBSGDJ/hK/eFW6lylhaaJjjVsKepmxGzcVN1B
mCwVpKVdTSGBmK72htH5om7KKA2S1rC5U1UUj3MbiW7ZNwfDd0USkl8imBDLwgYFtoEE1ko8C7Jc
eUprl5A05bpIwcNw4M1zuvcSJzD1rtWdZQl2vo3uekE+ox++ptfYE1O4Xj/2TqSRnKWmvElAWcGk
d1P93oZ45PNjviXZ8GjPM3O0qWdvlgjvAq0xdzA6x0TysB9PpseLW+g8nB6svNvi0GhK/LLkeLYg
V+VOQradYifDOr8PNb0cqid1ncvsR8+c0tlZfcJr23pLfcE3Vqz5wPmHYoK484/vAUmQUEHiXjLv
MiKyjk8ywnYHQ/TOYWuO5OiF3b4XtDucLmEyRzxNB7rY1i7qaj6wGs15PP5RLOMaDOI9Kg6163IT
YHmjt12E1isvBtgqS4df/zN19hcUsAr+Hd+fpoCiaRD8qfZT7eD2F7aDUpS5tVOH7gVSyJWqzQ5q
Obv9Yhw7rja/O45RtfCLUeQNveIdOxbYJdxtkbtNUL4THMOaUooUKNDHf2XRJ/IU29P3yYsch8DL
w6GDueFKcmhtTaLLsoIw5tztfz1OnR/Ji8//265ufazAczEkWZEuwDJ820UjB8sYf6rqgnsGaFMq
k4/RqF2vivZ5ejxFZq4j5HxYIkrT0dvfR14iHiz1gFBjRkaPy0KB92AudlRi5GguJSj9i9apnV0C
9Q8mNjw2IhqKOYuyV9e6QbBpKJ96If+glayPM19wkoNu3wYrQpc35Fto6fYKFdY6dhE8nKPhcitV
/uItKlA/SbBd82Zd2+R5YPNcmQq0sWFXHgntGjncAGogKw7gdfoVMOM8623k3ZSxgx+hl1hERb55
2VAlad1Z2TVWotbB4SU6fYbYbkgvMzH5sJuCqbAAKfcoPFz1nWbbyWa08tpLEd7dFgSfxRMD6emG
vbRwvFQQjTUHayp8X4YhTp75/cn7s7BNav/nMANVwbzv+7PlcCBDE/FAkBmre/mWCARVoeNQi9yk
Lmy+/QFbBCSDmgH9dT+J0qyptUReayys26DpOx3zpnRbUVqoevpDLpdsoEIttEWQIhHlgFCwxqwE
aRk/jq630RhYJrspYYhMKJx7vBModJIEGer5px3GFiyOMr4+4I2Loz4N0yOCB4NxzVtMSM+DMFzb
Yqmp3TY7W03MSy4BUlptWvy4cfrCDCrea8duJ43frMTKFTfbW+IerIgRfu6o1EW2xXm1cTpBK1C5
GDw5N3ENOo9k6+Og7Rv6BqrZrvmt4KofAZpoRQwtrvIUEswUfZzexMH0dWDua0IDEUztjkju9U3k
MYVajimuyW6IXCYU0qQCvsz9sBM2LLZ1x1Vup7fB1Ec5aPwU/UHatOkTm3aX0ZLYdmaCrVM88w9G
XHeo1x2sSQwb3bclHeYGqJ5KFtGY8NkrjA2kOqD+X2jo651hd0o8X/ii6dRA1MaQa3XRL48KOtEM
HH0PUmnhNz19o5YiXS60R4NMyF8DBJ2arUQqgtrBdHpYd+zsNwOO4FJe/HVkB0g9fp75mEMH5PiJ
iCp8PJo1jsqW1yWtRGUFGwq3z88uUmySC3W8F4jZcCA/IVM3H1z/nL/Xi6GkPU3ho614p2M5bRq2
14TEYUDIUMMz5OS3VFeKp3NLgKmCpVj7tbmiZi9T8Yde5BbWfETD2YjKPY4NPYiw4TNz+908oHc2
yTbewFueWvL/NaEUrh1xMwQw0DRkd8xsxovrukJPMeMMIOpJVuHAqxeQFIhjwyO05shLRO+8ICOY
lVC8RDu4KIeHaBIdj78ETsgHAau5157cMpNdCv1z6u/eAEhsPNaTpoYf5z4Ulz5+vbrw+Ig6ywPW
AC3chkAwdqF9uooKaqUaS0uaMYKHDaK2y5UfVCBUcfko4mCk+jjZbqPR4oE/RY4mRKF+S5KVRb51
goeafsPpARmOwOZcbpLNMXGonqOUJEFV7nFBn0sn+mMycGAzE+JXd2B03sI8g6vqICD4805s8/Q7
Q9RvYQCBXt2A6pU5gu9eZBujlJ5yteDEmqSPNTNLHzUtnYMoAcOjjRN+mnEfti3CP2YaqZYc7AEK
EmGhccCK28g3Iq3fyEIwqSG5ZMQqTqoqd2RXD5hdEa8/QoSw8h+tBDysQ5iCskiecYnVoVm2sJ9g
EiFptSQHJIy0hyW5bqu4IBzo173gYuxltoA/x0vJsCyFYs77QhbyJAFsJLmGHqO3cT9lndY5RmIe
G2IsYZVzwYIn/hCH0vy7GSobNYDvEMIvGBaU5p1UTsf1zLoaBwNW5il64Rmt8mWVqr6Q4Cv07zk7
YKXZHTXhEeAgsPcWekKsDPhosTQ1OG/Lbmqe6Xtt932gr1mKpZC9HDG0zXIrXY+2oSE8WilO1BRy
J88nrrr7Yu0oYnF4wZWHuAWIyjgLKyWWX4IP/WRaze8T+DWjRzYC+x719Lw3Own8W4ws2iTfKhys
/AoSQctmniBEUleebvUzkP/54oUfgrmlSFnT+LQI1wpo2T+VfQtutqXZD+Q9onWKVVV4HeEbkZlD
NiZEFqgI7BCHMNKvyQsr+gN3d1+ljxpDWwjLTifh1kNDK1FTX628L7Esv/ze15vf2ojo/9c1/gl/
t1SV+B85OJEVM2ghrmoVc/L4ECZPJK0ZQo5F/4K6TFqIGKCvu6JvWCTXCXXQuvIJWVCf3yQ+xB28
CnIRjnpjYhPYNojhQfb5Zv+GZ7LFqZZ1/o78veE9yuWl0lUlNLkf7AciAMp2qc67QqLSzbmp+IIZ
GRPGcMLDzgqZMu5UoNLRtDcIK4IdO68RfVU+DfGj7azU8UasdLC7EXFxENSmQ/djh/0I4Ci41R+q
wsa+kmx3eYs+rFXPF/gpMof9+m7gcNIlaKRiKrmGwaefZwbiLS2b5ZrIZ6dIXfBst6s3VP1CYaaa
+z49NTCU0GqV80EBrXnRQ63CMSRECEHoQlN/WGzyaldjxjHPYO9Hmx4A4l37hy0X4CBEgwcgcLmn
2IaYATXcAYJj2x+86KLB5ybH7SyK4Ew14BYjahhIhbE/HpiaKw6srEVCnQJsybU/L8kpmLrJFJJB
A7L0H6rsyqypQ0Gw1vYRNT/Iq1SfeeCbJucKyPaC8FIIMxhLscoBs871BAGV6PnoCQwWlPdh7wt/
cV+rFe76p7fOp7y/iWBGEIZ3hi+nWA/1wg/Gwy2n5z+TL5zSsOLvSN/UaFnaFFlJfzsshhbbzRjm
u8HmR4iISYlZfg+PuCGg4qWDzTm+W3rHe0IKKFdTl4GXGM1/EpTtOAqbIDIWKEIZkJ5l8b15nkSy
kXA7m+xG+B2kCr6obeLcnH/Kll+3TvkRO20Bb17nVNUb9o9OAtuAZf0dsN0dkMWVbDBmARX5RrB8
Xaso0jhmy2GD0839FOGPRmjq0itlZIHy9gyGxFuelbdXGBP7YJlreCebt5nS69xLW/ntBMeaobHB
+fuRF9ZeLz6NIAjircenBW7v07uWGziq8CV4rmH/bVbBQVpgNLXkN8+irSvzIih6+uQU+4qnhkGf
6DPM1CIN42m9ynyzhboG0MwLmsmxfHNu6W7pdDbuQK0nD+bziOLzzqrXLBnyPXGnwpO2QuvUEpHz
JbvGAC0fH3+ZHVgO2K75xWmD0ckLOS8k2Z5yXiDsc+mex5g46t0h1hrH4Yyvs+xHhn22sZ5vmAd9
z+TAxX31wRoiRQvb/b9h8k+DfNRbYFTRb2ARM5f0wglZ2CBCHU3UDca46UnCcX0s2i8dCJiik+U8
1YIMvzM1YeyL3p4mMj0N+JIFkUtiWw2Iimbj4Zp6ofh5N27FA2Lw2SNpuIQppGII0um+Cd8fl8LJ
wmvWzSxiUir0Ax11Yq2EPE4jm3nKtv2sY0E6lx8WJYJydjXzqOwe7I/q8cblI4Vw7LJj+vuX/Vac
5mEUxAfQSPmHwmPnz7dWxElLo7zN511DK5ZEC8GBtiK9/m3RoIfI1+3Csl/GLaL5uWLV5jg3nmav
Y0x1hldBRI4gGM/8vCOKB1q8BY8TbeB6wETtrgJDpKK2w6lzrgVWA5wHTPjCuFeJZQKurXZeL80g
JJpIX8UxxYd+U6Gg7ji8gqW9cjciYoznCFRSJAcwiV6/RLQ7TMkMWTU2UPbgRRUhP5AJaTlsHLBG
kDpRv5sUys85ONbc5+pksLhtG+6Vd/mWvnomEBms1/e+jX8+Af6n98WPo67PSdCntlBBB0GpSw77
A58uptTtJh3ZnWGQRMSuQLMvad/WJZKosSXA1e4gAi8brVgIYmbIc2kzpFVAw8CT8ZJVQt0dh7lh
8tVc9ifnMjHMk7eBB/kSfTmYqiH66g/FPPIMThz2zJc8uB+JcA65L3cTruK5TAIZfFjQsRhDD+jo
+IQSPEMe5sSQGn6lLvuEYseLQbSEswNwE1xM0mWOmQTgipmdzDR1ApQU7CJ3glXHI7CVSZ+Ptc0x
tMhQKU+3nMUBMdbrbWczDZr8+LtuVq79gy6RjWSEvDiU8k/C2jfU7gvAAhYeQmEWA2ZDfrBZGMUe
ctwS4RKrBsgrdotouRos6i7rnUYet3BfSROrkb0kSdMZRGxAyAEEU/HXaAAC8PBph61GdBPOjY2o
ucgy4/5j59ePvr2AHV13YPvzcUThetgzbOE/iQtfdAyChyoVx/t7MUXlzDXK9YyFeO5akcWlv5cV
/tZmdn+0Ip2LqVVRXFEBSoKdQdXJdPtlxjfAelCI04ov4YoJ58o+t0nhwgO7bkbIx87oHNgrzQ2M
F9Nx7WUW7kGIwr83dm82aDD3MxmSYxoppKine4XFBSQuB5OgrdtAHhsoSTFIgdLrqVtjPempXbGk
sAGCyeTTFU5G+XjRzr/5F6bDtFizNprxJBKDaht1ZHz7ETvgFDqUE1wXMVV/4EQdWo3mWO3IzFHy
MHtIRlXUch3GQNXGHB3VG9FfABO63ISUv+i8letcphRuJGaIqd6D140yb1j9b65V/pllsmcXjxZI
Ah43oD+OViZ853FMzqnn1m6QUPSsMZIRyqrAz1NPtluN+CJrw1FCZVpiTakwpdxU24wYPLdzkJVt
MpfNjTp4CfPgAm7JSZ8uNwQriV6W+lMhO/nOlWDmWdpkvsTuaEmfMCDUgnSLOZS+lGvmuwQqc4c7
zpaP6+TmfafMbg199BGBGKHnAzZYORNMzqGduqQH2rfIjXYsYhgEvrviZ02MrjLaQZP6+Ut5Alf8
E/kL+HVFFRph1szoSkmJ7EBXybrGUR5qMCQirKzjN+9O+mZGlpjLRjEm9OvwEI2YBAdnbEy2PUIS
EppQU9iHilUApIhfes6nYf+wBw90smvQ+ggytyPZpyUuHI4qtFg7oOfeQJsHmMUTERb3j27kJedP
2tYr9qiiRWvUkdwJ4KJwqWf4pQgGognpwYEamf+1nPv2wTMMQK8Xx/yjdn10Y0/KWTAYXLQMmYjz
1frZ7sNr9m2G1bncTeAGzAAYatbj5nvolqrKxgG3z0xhGVUVc40Ki2Nepm+7jD8G0IY0ml5LLddn
YbZpN/8M3Qhx3Xq5oGiH/2TnC8sMX0iYn2UCyLxrWczitSRdquyZOivyQrbiaox+Q14RjH2RZNd5
aQF0j+++AlFnkxA005oCTlPjkpfMTIc4RxeeLQJ/tOK503oFkgsrCogo+yF12lnKy6igucSzbMPn
3Wor45sypUNSbvvkuBCYT1dqOqZXmmu2OwrJxxib2arzDMD+Od3/2YCFIL50cnXvoIjhEB0DXR9K
/K7a88aV7qbJ4DHBzJ3f0XIdiFQ8SQgz7J1rbVBgheu6FymoZephdjJLqZb90iDDQWVJmojtbzXg
gFOUIz5M7rwsn1szvg6OQvvyk2BO7F4pzU/gosxylIy+ZgksSmVFg/qaV20rZ1k+aSKwrFaoQyeZ
RFL+1rHpj+IbGKJ0T6azxeZPrSBdULXO4GIJdvr3Qb7m1uZp95FUpJBDu9qVsBeW+e88fCT6V8gX
VS6NTuR49358rzHdu4P84iHiJvQ86U9hTj3lb3jjwQAZN8p0kHLIhJ/OK3HNXw+RTjLj3vFhUR/i
IRh025GWPgCvLKW/Fcjs6l17Yf4iBubssKiYf8wlCs3fcp9iubVKMP7pRHwefSdGrCymu6kYmLgw
mqeCa1xHRtdyJWo9Qe40/RZF/z5wrG4kAL6/QY4JsNK5IuaqdL11AZL2SCSWi+If9d6xMChOcgdO
Kz8rL/ul1zVN4v9usZdnQoWuT37LkO/XTV67Fotcg6wt/2SklpnESLjZ8scuc4uMPNBaKqJxjusu
l1vSBAc0RfX+94qdKAB1kZkl5L/0wR4MeVpy7u7MCHssLTOzpzCO9upNisBXiFFPDC00CfVouYZN
XXF0RkU9ILKEeChv27SW6Gi7Qy+jku7OC4OkwVTtOeSe3uN21fa0MxUAVDqDcSYih33eUdQ2UgQt
L6AkF4QraqjCQmkNLaNY6/FADaaIph2sC0y2v4R6EliBhBDUC/ueMaaLEicWDYdky6CenbfyuZOC
Uvu3Y/IwIV5G1ioj22TVv+/LM2NMXlM3efeBXVFLlpk0glMoySXNMXgPIwpcUbWKr9MvEuUqvHfU
Ua+EPFCKPWY+MPtNhxODgEaf5SD42ilmAXixVxbfQgZT8KDy5ESHSevUnG4beDCiUOx2OxSZYEd2
WecJ3ZL6564z/G4fc7Om0ZIOU9ng5EgK5ufct/8wDhJxhrKfWKF8oGMAz/NIeDg+KDpnnOd9TWC8
m1C/nAlPRFVJESuKzp85N/iFta4ERlbMXC3KbBhJx19efD9AzC6BaiST96FqCaEQ0gbAZg+5M0vd
sd4uARkYKVZ+saEmK10NttpOf8+fMTy+o11z0fGYxK7evc99er/Gbpf39qG9yEfmAEVRfphmZPIn
SQf7u15eABhrE65ulYC9cW/1kD9cckhW3Ca6Fmggjt0dr5f0xyY9FGPQPcKlXF41lN5BHyQxsQIA
iGo9RSECpzORa/a8M6ZNFsEFb1RNk7PIJWUUTwA3yGJ86kp56QxDSwHJ3pphqBtvncSbkJA4qxYe
VYFrqoPM2y9CnuLtBx77VYq0P4lNlDZj2jk3mHJrjUoyGQJcNWMrbXeusyvrDBumKKKJuoCp8Ji0
/RMJ+8HFg8+R4uKqYvpIJg8NyYQ8vYA5vtYccRW0jvZP/i0U6PWDFr9Jttd7mvkTVOZWVQzQwIa1
CX0sZXUqWjeUdWRk0PgpbprIfHUzRGF/71Zzu1yRW2GCnx767EQ5qKMpDIk0GPjYaqO4xoSoi9aM
1yz/MP17scsZFRtDTEX3mlGXuzvOXzoZuF1pv+cx/HZyvxTWVigsZvXDBZjLh/wgy0creA+fBV1k
8fkV6zAuCk5dk5WqKFfYd+1UeCPMcZKIBp4CT4CSOy97C7PdZOfTtjBE2N1HOoaQ2ZxOQQfwlT7T
fBNkY0FZvjuckL0I+G/gCuS39PwVULFYbFIzpXBM1Nbej2d5BRC9Qd2AZu9sxMPtcZKUu95Tnwhz
RLTAtWmI3jpVmutYnGnpM5mKwhhOdMO3VOC5v3YpF592DzT+6/6Acs5ks+nnzpA1Us36PVKcWGkE
M1WjUqhQAuy5AFtL3rF2Roudc62UHxBXUcrRUznmTU0m6HWy5ij6umKW8aSGQEAuTFkgHG+/QK3t
lkny9IyYFmqLI8pYvOJTBRa/mUHj/dj/6NbKzslOo2YhiygO1nVPUAcgCQY4cgBaV1HZAFPnSrue
xDDcyoDCQ9XAq7HtK2PK5zi3RkeZ2APBYNWexQi62G+cTV00wfk/mJEXllv7M1McZl6EYNB7w7Wy
NSFsKlLu8YEu9N+Kz6RKVjxTNxRK8PL4e5PF+lnFbOzA7pjA2WZ8s4rN/GBsDQxj+iRTW9eFFwkI
55pwh0HyA5SIW3FjpJUf7cIrlGZ4oEXT7+1t1T2BK+cZECsvU3yQPWI0wujjI3BHqX2Avcr6Gfjj
Zt/BOCeLm3WPYbVnr5JtETvK2x7GxSyH+9LMO852zV25Cd+48P/c6S2Kw0ca728Ny1Y6KGbL3qlP
4EvN/TZ7etw5UKea706IUXwIQVwpP5jQ938y0oHDYwffAWQlBszHIVreDFPDhRH7grduFfXwkAZq
Xg1+sBIztw+hxqlMs53QCz42G+g9RWycycylepEsvcSk9fVNm6VmgeZfgi6X66giRnNJpU2PIBAF
TmbPAcrMrGqiw6Igp/NT9dLv+HdaubjRbMktYivcwKhtfvRJxOMuhYot4wWlUUavaDQbJmW24VmJ
ZwCVPPi6rQ4Nhst/OnX8HNiq2U/gTHWXorogGqfyr8Y6nwQ1i/rMdmxoA7b/GE1m9P5/B6xamFQg
EwXo+CxJrOCPsGlEdrtI/EomayDvxVj5CfvkkF3AfbS1sQsfyGGG1tUvsuzyG6HbCWTS0DgHLYKw
mLw/kac2HudY+pRGugwjN7CsZhMmmjhzcrMq0IOLuASVzEQ07NRtu7qYo3gXq8qnNgGi3DQKDYrw
SYfT6Pwt/XDOLV/1Nwm7lrkBfprfCHgW0qbPVabJczWZCD+LcxtBQw3gU2094NvU7pb7yPhlgrq0
cS5wrnWHRgkSVTP2nTdECUOf2uvdv6UAYuKZB+WHxfuNgMuJy+NNx5KfDuofgKn+lYGw6REYH3Ka
ZOfYztF8bAdIPEvwSawpzhGQAiNBWeC79fEj8BBPy695w6r/wK/tqaFZeWkyTtf0I3GsKFAFjoZf
KzKY+NxdAAJi0qPk4lVk75CJ8kptfpPfFywJQmfyBb975TcM5vpsuS0OLQ7PPrjlQ3gHCKvA+H4n
QPQpKtQRoRv3axSt2d5bX+nHX7sDe0XLK+YohWnf6W2r8ED9onbhdOXu/KX2OHKoCbv/dCpO3JIs
yPgJIlcsES6Z7VNPf7AG2iCOhM8IJc2rkfWNF05kCosrhh9zj72ovE8RIohjbE6NHLiuUlA8oede
e6MJsIbj7L6BcoK50YtZJ47mkqQ53XN8aAc4J/rI7owAq6S9g50tYefm3L0nPbuCGWHERzd2gjBj
eixz+xrcNM7tnJIQKf3BHG5GEXQzMr8loXRSFArDmZxS3+X0oRJlIt5ZBx6wPaJLw/47C403FaVO
IQ7rKIj1J78aFfPu3+RUWyAxXdSUla9IOrNugivXxl+/pixnEdfqFhdGh7sINrMDr3Gva7MydLld
aT6Xxy2ZXoCIrn3QUJYKAx8iSWuYEwP4DqSnDEcIzqyptarJmsEalMCp9GrYMqhCwNqKhm7QFRVH
EJZYkgW+8UMhys0ogbrtFGbOrQzAPtBJbeUFIniW3mJQMXc79i1yiE21ixQ8ixak+mrYSNslA3e6
hUZFTZJoh5xpuHQYY1nBk5twjasanafpLNUSwBeNbZ44LL0/WMXxVmEI+OffB5P3t3OhAtcLuUmq
dmfqUu5wfet7GcTzjZMame10OMV+omk6zhW4JKpGLlaOc5wx6/zoGhGWuaT+cWFv7j06y/IK1Ge5
VwYmkjNekZd73ikRPgWbiiTGW9uE4WwlB6bawr+FtFUk26pt7kv3iGZfcaexkYk3gFuoCjMatcxm
5iJBYNcSz8AWR2X2L+XKSxtSf0hQgxgqoTL2UfsFHmKChrS4gCUThdVlzTQXUx4eyHaIJJH9DnFE
M5L/7tl89MeROUUOeAtes3QIlHeFFHBL/Ji3cfap8ryGMN1/gtgWdRFkXnoX+G6hQhXwma8qXikA
LWFDlKPRFEnz45o+6OCrGzLwe/otDBFLGfQ+GWVpN0kV/uZQ75Sf0e/PsUXpFnaLewiSKank6gwi
8yF+WH1FQE9YQ18xUl4fwH8mizCAxcpFYsA0t+RbSUT3n/4OMU5Qp9o7PN7lBGRIO5p6cMtXRnXC
JfW5MAwmEbuYLebmtXFTuJDEJn0GyquYWPiwpRZnv1ziMZpHifvHl8+OztIxJd2mYoB0qILovXrv
p+sSoT6d+Qt2nOaFyPi/m6CB3U6EZTDb/lY9CEtizEw/HAA/6VwkE8uIX7K7vI/hr2H0tduoiiNC
Z7Qlv61NGDw+Zsk5lf/EB3d4KiMTGGR+U3OwHtOnm6VYC8rcu1iaHeniGKq68Pd4RNabdW0SEWBG
SCsEB5twlwDDXXKD7ZjGPdrzFL4xeUQOh7FvLbwmC9sr/yhddMvrFkA2V9wW905QTisuA8OW3JSB
AUh4iRU5p3eIXnK4bV5DGLg5qrBMXKp7ITgTUsrz1GkN0djgyFC0XYoOcjI7B/yHlOip+3I0y4mv
lvXPbxrefN6gyKaXEaeKqc8lkTrapgWmcul9IqE2dc62oipP4yfF9dyU9mxlW10geK1g24KEyzGo
BeRphtKG4Qmo+nfR7liloRHvowONq++DWCDl7U64lFtPGM8DVJ8L3f2O4dZ63W280QNqOHfM+D3v
oYV1BCKRuIDzGPh+aSQpVALS7SpCpa9vz5n7NadTJvhdFlHr4KfuJX3Dh2oImi+n71N0Qn84euc1
fOD4vRyV2dyrbvpf8ZyzqYuhxBpx4gleNeoUIVPfagb2FoQQ+bskrJ9Fzaop3uYeyYjVHHz9Hn/v
kD96iS4c3YZAm2tkHGVHg07+rB7CjCZASOlDUuBZBYy/Vf49Oo6ZIbyPX6zKW1HIZX6TCXgL2RMD
Z18i6bS4dVWdamjHoVM2FEWy0zWmP48ZzqIofGQ35eZ/S/W7DX9ElshVXWSoz2DnttgcYeQP85Uy
g9m+ziCUZIcadRW964AoRUA3+eqQFMd4s3bDuqBW3XcuFpHSRPXh6t0Fs16Zxakn48FFt53gPuPn
kWccmrUbXLvLcqhA8NtpSsiryUclKgessi+7wqGZwaOZ/56iVBpZqOJwABqb37gDS4naRX5Lhm3s
m3HaTaYcXMsCHqn0auTQIir/uX4q5UPZFQ8Bz8UC3UKxfj5ULvWsnpZTirNjNzizmAgQT8RVbgzU
2G5ppcdSvbuZsNpQGRd4Pb6lyI9TgsK+1nbLlHGhemrdiL/34MiuObwmSLc73QRRBxNgFET6e1Lv
o6xWN/l6TErNc+6EiEwrxgHsEDYFHeG6qnW1ueS9Lpmo4/z7e+6wy6Tl/b5WouFHRr5e9BLEbuxz
42BX4dBB1w/PfHqyvQ9VWKQ2jLS19zH4agGu55yMenuP9MgLtErIMJT+Bl4ELPGwB6MlUUqTZB3t
VQC2OppjbtSjETZroDDv09xkwKjiHqEFViOwEy3sF9EdAetnX005D6kuc/K3fTbQi+m6fMRiKN2Z
BiUYhf8XENvED3ZMQxboABD11DmJ1e9Fs74DiyxWCij5drQwOkqqstt1vqKAB5y7Yfz7BEDaiFt4
N/hwftM3GyDIag16EDHX9KUEehn7+WAQVjm8M9q3X05bEsi+YJzDYvQ1YUMmCywjgkrU+we6Zlfj
jwHfaDlARpdR7SkNfEHejmsi+v6oKmporsGFi/PV6Zto0tsGqVmsM4rG7ACZ9Rr67LZv2ZBYmau9
YMgEVa7MgE7o+XRH98+6g76U+vPo8sDSXBzjLxrUWj7LbaLAwHwCiaHAk2NE6S11a38XlxU9q4Rc
V/ZeXX8H7FNqwpWafLtSUSFGjVEl2UPuR+LqiFTtg5pDbXTI3RUZ/1FTQXdKgs8mgkiZobQpzFE/
rrjhpfu5U2VFgUt175KUgZwXZkH/mSNkaexiOIwbfcsZBAy/tKw0ZMHpRgmxVxs6aDNEnWMppYML
mirp99KtxeiB4YkVvhoCIgRH9rd9f8SjF4hpmqeG33F+I/8aGa/B9TDn9mIOB0MkA9G27OhNWHti
BhiDpachcuiKHNRXtROW2tZ6QSKltulLhEE2tKS5ySwwxUggM23fjcafEriJsOg/75JPoP0f7KSD
GKya9azUZuLQNLPDToOlCvYyOgxC7DwAJSzAineFxmxudrjNaala4ME5f7ber08k0H7a98KpnWhr
7Wj2/ZJ+vEdRg5LF5JobYzKvmpaM7hGgOO0Y0TDtIOO7HUt3HbEwZQnXW67gaNwbS1SMvRGswaYx
K6wkNU8q8NKtgBuc+BLolYfLBZRJcyR4yNDpU2ZjHuWIT4ts/OFFXInD84SDkSXjHApALHfZxsnt
cTfPbSH8fDmCJm8Vuoqw1xgU6RGcrAVPTlI/Bq6t7tCPO+YaS7Zc7owdZvEsNMbqoZsmDCFe8doV
8cVthfoNVR0f3SFwHIhWyLqcudCO3w5Kbmclzjof/qugz7XI3W4up1D76MJKqi3dcnruoFlabFxm
tSwx3GSlL+5B2O2YixhTq2xSfw1sszftRCihJ0NMSoRqkcjUCZWV/isTBo0MmbQfNmdasTOjZ7ew
2BGPXSHQT6V3s6XY14QEqIGMHPF5erZNNQZhY8yMaHagYfd2U+nuwBd7aS4EyGQFpNTw3QcKE37V
hGX17EZiG8Wq6MY/44BXOfTCtCeKo/byhuif/pVMsu+ca4R5zGuY3CiVWYEsPvzxF/qKifpxZi51
XRmtFk0dvxCb9LZijwdOxnyH8ZiWDHs7mJnDVpcWUMPZU8IvqumksK95mbWFPl5LqmMFM0jEs8PD
mTfV2GTjPFDNIyUlS5wgr5mAkFV9aGhFTJyxgym8HJTFTPnH5yHrrcc8JJLtN4hU1di3Xn1fE3uT
opoRvS0bdUapON9OlwVhd26jM7wCZBYB6trMJ8Mp76myBkkv39NINwvcNz0C9PjTC2KxxPuukWtR
w/yhSCjv3HZENtmeUszZgrIUGEER9oAiD+owYoWYlewK0ILXabNAqrhmEBqBHrr9oqgbcYRDzuYy
tXp0TFqhsCtk673OJdQGB6Oio70EYcvfK2+/+lQbm8RY3MMrGTIdFT56B/KY7jNhS0GK2TQxwqhs
TRZFKV/ZJk4siqHTytH15d/JDe5gR0ZT6YLiWctRZ0o7rDFAuWGOts2T5plZkYkKlicuij/brRUE
VoPwjXc21Asul2nGZ4oqWITvNNvqsSj3pZcib/NkEb/ywxjqeutPrWHdY2z9bYYV0afl6iN+OJPF
mRYM7kLjlkifzhHkjMHeNI/3PFm0mygSZsjtHDrFRcYjNY27pFqwHt2ydv+Y8I0N1SDHvn9BLNJu
oFVKeuo90KYeeut8r9DrRTYqFOonG2OEQDDLAFRufZ3qQCoZzCVAz2808ZTxpmyZlUrqqRB5eNoR
fjg1JW2zKpsRpYXTmNQeMRdldk+Feri5oq9cGD5YRVbI8qXrgCFVgnHaSb6bgNKjoxu7ljGDhDlA
fyljqWnwjpwLnJrnLEEPxCA0T5/et2QButOgW3nnwmS1l46RTyIuJvDC37QKPJAoZiXW3NONxQ4S
VMkIxUni4WFNp61+I8ALmhKWYBMnSF2olRUJgjx/5EoFbnaRnuG71h4SLeOPIDGWQZc0jBwrQoy/
p39/L/g1wLZ3FqNDV7qggQZ0GMY0PqS78funhvJ8e59DeuguR3c8Qw2C0tcThu571K4wpX/OFbnY
beeizjT0zdkHhRSex+8gBUGhTbaSXFA+qwXR9xCY+C7zYRTKO8Nx+cPPqtw9pP9PxBswmjqhEKt6
3Ck/ADyCLZdGREp/A68XVGVvHb/JvfOg35vhDTnY5YS2yaSxtOlTrfweIjcpHNm/KYIfyfc8tE37
vQgFgsHKTN1WfK5wTNKf7aRiY0HC8102JHI+A45viX2RWjDbdLJq2Y7F5ppx0BUGXajkekHFHtTP
zGH4mWnc+ZM9cxpDbZHg9CWY03g1SIePCaPv+IQWravG0Y5/FjoT60o3H5FyFBudgMVZ3cp8VzJe
LvD1NXLx34aC55OogymYf2wimfHqDswutWmnj+tuNMEDOInqQNq9UcHM/OyxxtX8wTTT/NRUFeVm
VeKtfofxOPU4GgEr7q/dgpmmyUwpJdTmUIWgEo/EFBgHOpfX6wnVmKNZLK/35u6h5zONTzL/dQna
H6zFQ6I+cQKT5ug+al7l3k03OO7iBB2zXBSdPjOWpTtDodnsbHMw86WcpUsjoqFkiDJh0K9pAiTs
yu0YtLXYhpLRc8vLx+nlNPLnBlewheD6Rsel2vUITR+Y0R+LTIVcFizL3RkCWpgT8Mv7GFBus0bs
tXa7x74NoVvDOv16dK5Bp6co4kem5MjsBMqulNnb5qAiSRSAHjJVEcbgiN/ejphUzKhhnQ2rLlmR
J0srKz5SDkt9GoLIIQYs5LiQz7IybWCgpgj6AsAgzJv8o1wGzGOJFcuutKhU3byY8gX4mvT1mcoL
+oV0fltqMUZ5+7fYGYXRzx+IoKYTulFlekV7KaIy6pn9anlT85vVRhfq3tNZZRGuUALVSiHKp1Bv
hSH5jlo6taMLCDODPF39Tqvftq6OemOjXklUiPQyYpE3hA7qrG4TTmxYZzDSMPUrCpTcgg6vjYA+
icfYFMU1pgr4fLmYJ0fROfPHuGJh8j+aeRnjdDL1S9T5mRS4VQFv2nBpMet9lpa4++KbevKGFfwJ
BO0QF4h8xYmLMoxmJE4LfilYtw9dGxV5baelDnfq58HheZD2ds1QdE7sNtEpXV6y/daqe+F0IrwO
EggItvtulBViDAFHzzEs4Ors+9e3U7TiRkh+FQouUA4zwFshY6xGA6Dbnol3ZBzdaBUiUM72DESu
4f8i55WEiA1ksZPV3YoWd/4fFxoy40yp+YAThVsC3PUgYwIJd+HeGGy4QmzfwbeK+mDAR9fhkgPx
nzDL3LV2Gv3HmCCLPBRF3HWk89YHpBOvD6r+uOVfqkM48561HfV7l3A6apzVHxEOEh1IyTyiN4f6
3KVzCDqCvavPKeaSnkFs20XLbL+sYELy1lix4/B4BOvvSBa6muSI5EwkO9IYHRp4SldDU/BoT6Cf
qRS1nv1bScZ42MttKPlYo5C+D45g6wpNReoA61TtaIEPBZNYtLw4TsZyYTF8v5ZzdClRynhRzcCS
TDxMcqXxYDSNoJqUrB7zcYe4AU3uO+Tj6wXoA39LLbsKtK1EY16dK5eicLPwSoFRhW+yHzcF2R0r
WPJGyuHI7ddZdu81doAYgdtje29f2PoQ7UdSTUx5TaBtDIJ3Rj9hzUirGokvUqbl7/aQny41+3XL
F7yI+f+1hfB0KztcysNAoH/Ef6mEeMnfNIZ1MWfgKXi2mHySkygQ6NWZ6vvA1E4qyMJXH6Ff48/K
gOLCxf9q2hiWqZQnp6Xn75CfUcw3BVuhzDPyLdr0RuUnInmBo6zzYXmuhUgWD3UZOwbOLMbQde1E
4+ppigWbA6D8yjjDH5d///Ez3Ge5UANdGKtn5+zwt6sVz/UnNbLaIxHavGC/XYYHjVzK8UBa1goj
rRjxZYq+/vP9jTUVM/We05Tuu6Vhr8Xqgqbs4LxdLvSY5ZRtfkiZ4ZCcUX6PAd4EH3/mr2iiXXwk
MaHxtETB5c92jL0MYVhAngHcoQp4PXcVgMM53uyhUPz7f2ILQV2YDlsJucEYfDq13cpM0FlEQd0h
5mhrSC7d1cT9pzwN/S9h7Qh/HzA8ELwUmuPuJDo2/TpqVz3rFrdQd6zrjucPEC8bNXyMJ4KKbI8D
jSOb8qPFWrNmF54vmxSvOh/OuuWoD9f3nVoFgkV+u9aHOriGCvKVf9fo+9RKQjPtDXcFXUfhU3Cv
MzmWBqGndqHMPSFCJwZft7uzO4LOPPH0VfFoxWhRynQwCPBocMx6x0YUJV+M3EFU6Vu7E3kJrFsl
y1fn4yO53dC25b8g4zcCCiBPZyfjr/dEPpI56AfsYVso/JiXvsCGk4Q44hgxk7E2o05UqQCMycBS
ygQjxTdflOik9YO+XOKbMzwwOKB9IrJf7iEl2lQF2K+TkGRUH4+zgS1JhcVqHPMQR+DJxVpWfM0M
H47wPKt6giCxmkkimy+FeHTdZ6hz+24lzsFu3UbXHAwWbAtim+kz7tWoUwDCuWtRez90LMVibV03
s9OTE0S01WDnqkPCfv23N97xtDZeKpUclYjzfg8WN4IphB+xKA760It6EE+vAg6sslhPeEtILCY4
Uo32QdRhD4sEjjub54P8JzSNxRxNbgJXU+8ynehszPSEyuxl5dDi1AscV5lkhXQ99VE3kbMI8ilh
QVUy1qYXE9K5fiRAV0MgOjL6GGRYoTf4n43A3FTs90xm2IHT/tG6dfy45aY7VCkDyOLAsNg6qbjb
S+am1g2mbZSI1nM9RhmFc/sBTe78Kgm7HWfCi6EV9WsWjqKGa5AaRsASsm7bd1npnUKXCxM53zTI
77Gkmb968Gfj1eaXjJQdf892eoN9RwJPsCC18O81xXkHoHW9rpUzV/NkTfGJToNKY6n8O/U/gp3y
AG4NmQb+ohRjIbQrMorHExbrqsFGL4eC3yc69mOV+v1CTYsqda7U3Kustm/djGTSpFqDUaNUmNv7
s59H+WB4s7H0P4v0ac2cjyGb2JiekKYXjqytCQsMiVJwOtyNM7tOjPKEr5DFyVazHv2pRLOhaGVG
87WLyoRqDpuHLeZLjrkoa33bl1FYrCa3J6+jJ7/V3xNnIZQChJxZvKwYAjZaE4fMV2ZZJnThqFaV
jzThXMsUKhts7V+pxPK+9zyGMAfbJb+gqTodEbZFGJ3uAmuFe4/D7u5r4ULee1EtBh9bcw2j+Ola
cNtHZu9ufBxtKXSETdazieWpvDhS+w9bsCl/1kwyTaNvigZTEXWAX7zN8t/Lv3wG6d57wx/BxB+E
F8OAUdaEA/l/kXOG0XbxRG2wQEbzuLgDFSmrE62VEjJinXmf1q7lMpmlsJOGH0t6Vpx6OC8xz8e0
9F6q/ODk0dxRYn1TlLWz5oHLnk5CLNiWA8DqRrYx16q9uzU6zk/7a2dB6MGsTzhiIU00omSXkLY3
uhJSd6oKTQspc9w3uPCrB095lhsz+vGhD4iM4/CS2HsS0zXvKKDnVX6r6sYwhAYS1txJn8cHejTS
33a3FzrLh/Lr8tihbnmzdHQJtk+sq7tZb72rWrEbk48sbF9yJahsTCRqNmxxIiHoM81CkKoI+Lxh
cfc0D5Yp/MomiNvkLGAQL9gJNP3W0OyucO7MynZvbq3xjQW7UGuTkM+U7elqqbUSHoc+YvoRMbS0
Wra3OUa9vgiPvfWOPUXkCzQ+GZz5oh+zUdgV9KFSEg78gDsnyyeW/ilBD6TtAk9pe6QKH83lGlA/
2bWItSalCQk+8HJxYzEowKqYFGa6IaIc9tMb8mXj8fSJrYpmGSaaPDJJbiFsHkgzUgKFO56A6/eF
ldbJbZmhU48DLTEq3y10q679uNFxpRjMbj1VLTSaUJ5hhfLgA9jgL7ku8ypfmsyML/AFtmtYlAYS
x/hfNfqd/HxrFDj4suOVtrsEgFli/p8rQFuk8bUKKi+qMACYCmucfH6KPKuWAuxGCuqam7J+SLhy
F6DV5jjns6q2TiCqwQ/SFDGGwNWkiXwsljkpcugaJxrggWO350nMbF0QYxh1wDeVmRmPTvIktQeN
C2vym6ToRxoNYTF2Tp4Y99bkBeDapsuHhs2C3sEBcQs8X6JL4hEvCnkrhPhAFYDvUWiWd97v1xEF
JXyVXUJkVG9BXgkFfhxRC6VBtIUPWaRXjsqkEhgA4GfNh9Ato1kt2NsNy0Yk0TuxhhyZVCo9JfjN
xOUbhJqEzzlTH8+IdmNPKx43EGDT0Lrsk/UOaUPBvFWdb3GqIMg4TchPjXgWpuyR85DLNpqWKB3K
K2K8dzks0hfLCIP0o1ZrJyaV6vTRLX6GDJX6JZRDQIcYVYCtM38a642Um1FZz9czprkChHqQfL3B
NzQrdtyK7LIW3fUDo5pKTkFMk/BrlxVPsmRbDFKf4rxCbgZA+dTNUmlpBauC7VYTM5YFkM6wgAQf
kvhXW9lkApSLz8wKN03C6wRC66r8yh/YqKG+OjTUsFovJrTDokQK8MgWGIzpNPRCNORK91DK5GNY
HEXIaZzdLIwnRbeaVleFh1M2/3aFZkINsBeVqebQim1r/XodkwvYfRJymSowdoWJn6/gXjWYYZGh
nHpo+U87TYAoe/0bNSftOYIRvEYmlBQPHk/YuQ7Jdb5hXqiv8iaBtaRv3kWfgGc6JF0PyuLIJmQz
sePGBoxGEAi/gTPFAp5q7bYdVvVh+ebZ1KPCkgVP67PIAZMIBdM7ytHOVT5vyhBUSnzHGj7tsaK/
AqD6UoWrkSts4FsZnh9O4M8pkE8Vm26V8YWdgHnDnz87zqQ/CBdX9Nf6pLsk7Gm/k4IQqgnaYV3Q
djGKNtk3QKG8x7u/AfFVjfC3uxos9Lej1HjxSt7yMGU5UStm3a89d3ADmdllSmHXG8oaJwgC5yD+
6ZyoV+S6O/inHAAITWTqNss+CZq3wQ2fSPRm3iMIYujSFh49ZWF6Y5hhATGZ7puV05IkX1gc8Ela
qcxST2cD5iqJ2QwgOpu3pXIdq8sop2UlJ2ii2/Ct6PF84r15S+LX3gLwJ/KnCGF+GUwOWmRkx3Hu
v4EWljx5OFiNNQjpL6/VF8J8mZgV0Yatyn1p4Zb53UROPaTcM7aRopMguRKwhgpbxYt/+eTJW6XO
DU2onCq+kdiW47TN2oEGrRxvPPPOq8/oSOfJtP28+4j2QIWKpNEEkyM1waSHRIK9ySAFcsxROSmZ
y5VUaZHpge4mjt4o3wek/wS6MwWVPMsAu3hEPxAU1KQr/u9URt3MMa2fLlo4iYegrEEYe2yLrrAN
jfOlfFl2WAfnBn0q9dqaZPhtJGkjLcv87aMFcrI8E5sRxgPWXNHe5E3yM7fFaxtQ9czAwy5HBQ7T
gJgBJSPfEfU8e3x0JPGyrdeTDJ3A7ttFutTZr1mNDvkDS1bKipmWU7JPSOW9iMIXgy8z3KaMV17o
y3aq0spIkFtfHwEMlx5tdEz8T/iwPwSqX7cnQdq/VsqDUNNb4SVzr+cYcHaGI1VbX/0HzDuMomQP
8bBDfD6NPr3YWlufkhrsbQfYW7WwfFtn5mraBA8+uYpAnFvNL1nN6ushsbMR1N+vSXjcYN5NACl/
H2124SzQrgKMKsLqQRU44LOU1vbHbBKDecnaquvebNH7p2feemLLqYcfbhQerM8RTzfGlW92BjUa
pGu7s0UvPCSvVvGLI6kKWChXl/Ug0dnDJutwDJbPGIIKIcK+2NPBDWx7NvZcgk1vLArNWzWWN5i0
Z8dDhZ6CzgsX9JZYvHPLyXwjLrgSDXp6EkJ3xaVltlxsSPjIWuSJ5UR2t3a5j70+y53DA5hawRIJ
BflpJHyKmzPzoIY+XozhC5geLbq+MLSTkXTA+Md2N7j1po0WdpbtlNFxKyHKeOmAG5tXoFNxuonX
NfKY106GmQh1ErXt/sv1FnwsfMlB1zi1P2UI7BNRKZFKqOrCBbJHJCnZXGXx5HE1jHd9qZY8pcf/
raU+1iunjRWFwqi0m4Q/8gbHQTiFqXI0Vta3iD7PfOvOLzc9cuejpa4JY/ddtS3kX2TIpZRySbii
XgeFxsoRZG/o05PSNLi9egYTmlUgVS8d+uK+3hIvzh7l7GM7KBHA/q9Nsn2MXkbuM26NH3qxiAea
Dn32PsY77N/kRaam/N0h1Zw1y+Yze0k6Xo7SvXAa3PeIHINvxYjsqA0DUbJAr2qJQ9ez9vPSqTOB
Dhbd/08MfHVAhXHpF3fM+00YOk9kcYkG9Ri/eeixt2oEDZaKzJLnnoqvFxeWkGjVuZfdk5dOu9v7
ExEKEHZo+ZvJiEXLjjzmDtZFould5AIW+q3ME1xdRFAo48yScl3GdhltW7oIIwCbxONHp6pPH1DB
UKn3Dh2Z6TWDBMdTMe2/L9TS7lojLF/dKkQy/l5IxcOXSsyxUWAVpL5ZrB9DtijZUUpLiHlAFei9
Y9Z+k80OmqZhY2yO5s8R0ALs1Ft48o5GjKhCgHF72iPb/y0d1jf95FfmUoxwezzrhskMaOCfFgg8
AphxbFX/k+52qiLuQkjtJScwGnNfZDEzWfMjSThKXVI/arwQ7Tn55JqubDkyP18b3uYJ3czC/KiX
yv+ED9+8d35HV+DzUtygwZY7rrisICcU3NFk7cc8i1jdolvkOva04x34YiSWT+zjbKj39iDgMJfP
nq1M1Ah0h3m9u3TgvvOjbzfU5dUNe5/RyIdK0LTLLKGFZO1jZL2P6ntEgfg507gCdVHVavN3mTHX
IPwxe6Y6aJ52LnrwSvqTlTplUK3PXqyywVm3ukSQ8najZI5ITtibqu8sJzJxPESP1h/CGEy2irf0
tKuFjzq4iUmlE08KwGR6AdQ90uUyDZ7BInDpap0TUFE2yqj+Cmg/RLdONz44miMbIJ+DAxSUi2MS
CVoaEGRDgZX7L+1GCwlSyMt9OauSexn2E56pMGI/A/PNjcGrIdxkutQoK2YRlg7i6f+wNb9Y2gcM
YzNWLYz5uyo3rNjHRcKm7HEbiWcCdoOlOc1k1c55wLySin4bgMGuA9UXa2pj15QXYNFMeJbtfhwm
ar4+eZn5WyZ6Q7DhbN8CKPpHO9TyDPvVgQmrAQcWSBAx1hC6wirnvf7ATJlrz+DmfHI9E026mId6
KH40lG9jMqfrWu7g7s8wz6nIBiamEhcd5objUHUEmMKbsASQjGVhZA6QbCbgAukMJWUtjQs3kGXc
FgiOMoJpGeYNPE8MJgGTMl4eB3OVuQh36cD5wqXzYC8GP17NZ/0WINIk6TBXOsOpv1WCDSwhzshP
zuOsK8lBIWHJFZMEZp1ygQP/cGs0RyCqkD8ulUBTV+K+EZcy6DXjw67oee/ALKZrhgkjW/cAGZxd
eGZowjoQwZjMCPMMu4WX0cMnUwzIo4hU1IQi+ktIpNRZkliY3/li31LBpNye1mMA1I1p7/jq9Rb+
No3LbhHCont+fMEy734+6OiLsjBXts+/ro+qRqYFtjyT+k0RFo619T77Yp2untdxkjuR6be0s93j
vPwKi2VrjYaTCJbKSM0oj0YtWmM4nSWlNLkS2h2rjbGdujgcDPlU8I44Bo2G1oMGiCui9FodkZtG
kOBqtjbv1R/z+321jpGACzq25FPJUSd1xst7U+0GLp/EzuEpptq4ISk5nnvG8OpY7afVlV5aPFsj
MBQKt8uSzd/dHgxVjmPeqp1cV0WABPcaLzC/ehxbi04Q
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IVxyk7XRM4VsQcD0QPYws4xsTeDPKdwWYfreQJ7l1z8C+G+JAKZ2psrNI+b5ecZ2ziPH9MBGr/oY
8XtzCKmjJw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VO3Jpo4aYF9TyVwyAUb3a/oDy8Yhm9ea/9mAjNtuOBRL0qoy0/CWzL7D+bc1SnZvEP4BG903Ildl
dM2y4TNyVTBUaU7Cz+LzZfu9kCPWnmttlx92LcMKLNuvGUMPXmV5jr3PzSFEvoDuCinMqNc8uKFO
Ux/aX6fmBD8AbQfpK30=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qOkimDe0rSU5f1zKvoE8a4lZw1WOOUxh8wtTIN0ys09AXuQuNNCdfu6VL2Xuj0Xus09sBU1FazgW
XpQHuw7XcozHRlnUFKPJg2P12yPJsLRkOqUWtHTUXmH/8s2RglOoEcmFeX9FVh1IRMdnp+D/F4GX
/80OwH0Jtm4eUDa5EFkNoIfhlOG4JOG/JCsYRnsAoZAbyHMEk6qPxdOGDrYzkbA3CMCikTuE6wOm
0j69ZgENzpWR5aludQDu44oKZqgkdMKNm6Mvk//s2aUOTBYWabbSKe/I/+cEp1tWS7+9AAmaVwO+
KwmsZsNR4Ztb6OH4hCq0936o+bycwR0b+Wr1VA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4df1QYXbx3PmA5i1scwSy/ZAJgZ0wNtl21eeCeUI5h4IQD2UalJOUkc5a5UR/j7lX9ToyF2yFHzK
L4EoH+xXm54bGihfoaTvocQQsWhCDObbmBOtqB6WS1/bog7FNgoEObi/E19vJsjPSd6nCCdhglZ1
j33mJRkZed+lVziTR/s=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Rtu5N6w0tnewss9ZQUyM3gMzu1D5Ba/+qJO2rdGgk0QN5Nm+4TaVyiEXzVM5DP8z3mycaRD+z4HG
QXarW6RH4GHKahoLlSY8cryjSJRWS6D7/Z1joY2fgJb8apydMguGWjRZ/uW6R7BEimGxB3Xuon63
ZdpcvKZmoyvfg0kjAjor/DxtP3SP6DKxH3BeegGQKpP/+5EmCrAhhPu+NA21340wcbghotvyYusJ
ErSZhtj+1FLwV2sO7TUt1etBG8nf/yETDQPE7Q+zX+BzOktmY3tIKds/9qdyDt6Qb5WIxLMyaMa3
eyi0SGAuZdeDtK8Os3w2ajEZI+VjufruVqtCCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17760)
`protect data_block
yvvRtu+tA91Rtyv3I35O4K6BiUlBjs7LTFLRc9twWgYZkATXrSpXZut2NlvE8mcC7mB31ueT2vlU
P9hzhGYaJ5GcmScpsC1FKNndMfl3Ug9Pqiw49YT0Xp/AQWIr+q38Pu2DmkLm87YVBi0HN6JMSu6G
rwJt5qvXJYVA5oSnqcy27I93z0KCdBaCW4BhEaXbMLEY+qzcYsWxGhgjRzVfC2OhOSpdpDr2MKHw
1YDri1cTZAVy/b3L8VUTlyQx4YRG+qS3u0Cz3dOLm9nglzh9Pa9XJC4+Lnpli7w7vpvakaXaH9W9
I9Xs/9ShuVul4UrHUMsoz9V5jcPh1iHPT9m0ZTeLUdfod7NEEFDW47vWU8XjL6iEqBvA/DrJKrri
hjJ//n7fbl9gjxGZT+IKqHleRVz+dRiS/uTuRo22UsAcWrLoCdroE0x4MAJ9vC0vScZa86PQBj0m
ixJFhU15XHesAUmaWmkIVFZdUdZL6n63C2nZpQmpBX8G1td46ib/xrjcP1HPzbr1hPb30S/GA95D
4e3ICss1yPb8NZCwvzZHNKYRJlVJ6EOWwDxLeBOjWmUySMUcywo+toi8FWztPmB/Fzs/gyRSBxsb
FBe82kj2NTjDK0dD4XCcU8bGjVOKNJ3KoJmC+0UD0jihX5N1CdPg7+/bvmP+MCdk3ondXZKJzYI3
9YFYkr0RM2BhF57jZwHcHHmFJrakmG38Lap7lsdonuIO5mfOOuicr4JGW8Qijs1+c7VMc6LUwGDt
YKznnHTq75vwwVLxmtGYpW4RTIuqlZmOJwC34kp9oVx0+wFtUxMvQgXry9FwUwb2gSWRseSfbmMB
auDz+22lW+enEoOu3PzG3plNq4oQP2K2H++ZU7HNTNGSA6VpJWDQ1c8o+i7+XEkyIqt9DZHUxb+3
HlbwgxRkMYX88B7lb3GnNDLF2YzkJMgQjpyPi+t3N2MtquCFuqNuaKv0LoD6+mwRceg/hAylp3x1
m9DKQ0DcKuhctFlcx3aOGMXc0mzgjh9Umxn2Ng7JEliL6/L086w36Jar0AAtsKsXZ1NsDDBpiIeT
c9pWEQj9ud2144CtZKOT9/hr1wy8/jpi1lQaHanlWWtc/eb1aDpSY58hPbltVjUTyizUFFWsqQAC
PGoqDXF3N036pR2Ipsz0lKGQE6qHOZ9IQByoJkJfVJQFD7arWnGsW4G4I9tdTj8LBH1I0/XQKvur
lSNx9C6iPx8J8GemXPHqEIipG+GgoeMURYc7ft3GzrBdwbTFPm/qrxT/0vdju3tRDBl4JSzWO+do
z/s/CD6wNYNcDBCSDKcprRdML0+tkUYr6Jexl5rxIe2GBG2XGRgBDqc+wBSNJY7VVfutmSr3NjPK
RJK5NldZFn8fT/rjewbLV4flhMn1tgsE6HhNm8GuRS52PpzP+BK3fCtYvb1mnkFy+e3mwc3RgZ45
5iaZGmsBwnJwI9GcgMGoWSDkSaL/1PrI03WtUczFAidTPvIY08FA8CTdX8Bo/j1vK5yj8spVzrNq
2YNw08dzyQOA6p4yaEO8Raki3qlKk9oCGUe72zvHFj8EIo6DPYz7MTOBMZh7qLr1JDqBA+iyQCSU
UO9dElHR49OYArhLqejxnXEbJqi2McLLRKhJoiH7B/feWKz5mjNEjtWpHgiwx6VhyEKkL6UZ1Rib
ZtiEI9gtUbhZ6XzaYm3TiIRoYgTzxH0j8bAv7Zy61YnOi5ds35hrlF48AdxPXK/eT9RxLQ9JC4D+
xhLyqoQdstrt5DgaM3NxG2mKEJVH9uc9wj8j/rmn9YrBedhVek2F8Uvojvb9UP2S80Gz13xgD5DT
uHlDBG0pjratONtNE06BnMLwZRtD8fOAmitaJqr+uurpGUSmFSP1C9+FHTWgzBTdRwxLO8vYdEOz
WFiLspZhFCxJpRdUt6N09XI21qtC+0+ZgVoJcuL102pig2HCGw+mVSkibp2ZzBHApj3TyyQWeR0T
soE6qVGrU0cCA6w+mgSp/LpLjFALA+nFAG3lXPvfyzy3nWkgcWbCXiItZJY+SdblaE3tEF0j7zRy
QEv4a8Rg+L6tHbS4IhpoHW2u/3VbDszbEYb4sRKfYUA0hAwJaM8jOAxyu4YRtJsjn94Jek1Taiie
hp0Ndlnhy5vlx4q5I6i8Nc99UyR9uhRu8iqRtT7nCYuJSAzDby3Uxqh6srwmKPrb31KF5pRhTgEE
hoDR5pRAhvr+p6GEHRm1IAJTB/vA3Cmck+beIM8DaYRIdaZnzC9N04oH+sWVHExAUc9WW2ZHotPC
yowKFvokfu+7look6EHxqKtkI6qUIsFrQgy755fSnh7+GR8EVZFKqkRCDv0zQz3m3MIaUQ9GzxNA
nVZg02l+SgGZHXvy8wOZE4ONpWcUccgX9k8Mqf2VrJEhn7FTdwr/L68VLWlWyJ51gTID4qsEbmQR
eUcVhXwZ8J6/Jr+tfQkihSE/r9/FrMS9DtCeXZFSTXFkRXX3jwy08FYzVkX1AU3nfi5uob/pWe44
jJ4c+H4TgTK/YFd0U9+b9+hcQ/PKCmyuUWlZMD2jh2m6YaM0tRHT7pTE3k+5NorK0KIzBPhuhR0P
kwadh+BfDa9Ed/g8FI4r9aO+bzUYkbubz1m2BkiyrHNUN4b/jhDQyeuJYsvVZmik7vXZ6GcS1rnC
ZJpUE1bWR8FcYhqQoncmXGI126qn791BoIP3g9UyBSGDJ/hK/eFW6lylhaaJjjVsKepmxGzcVN1B
mCwVpKVdTSGBmK72htH5om7KKA2S1rC5U1UUj3MbiW7ZNwfDd0USkl8imBDLwgYFtoEE1ko8C7Jc
eUprl5A05bpIwcNw4M1zuvcSJzD1rtWdZQl2vo3uekE+ox++ptfYE1O4Xj/2TqSRnKWmvElAWcGk
d1P93oZ45PNjviXZ8GjPM3O0qWdvlgjvAq0xdzA6x0TysB9PpseLW+g8nB6svNvi0GhK/LLkeLYg
V+VOQradYifDOr8PNb0cqid1ncvsR8+c0tlZfcJr23pLfcE3Vqz5wPmHYoK484/vAUmQUEHiXjLv
MiKyjk8ywnYHQ/TOYWuO5OiF3b4XtDucLmEyRzxNB7rY1i7qaj6wGs15PP5RLOMaDOI9Kg6163IT
YHmjt12E1isvBtgqS4df/zN19hcUsAr+Hd+fpoCiaRD8qfZT7eD2F7aDUpS5tVOH7gVSyJWqzQ5q
Obv9Yhw7rja/O45RtfCLUeQNveIdOxbYJdxtkbtNUL4THMOaUooUKNDHf2XRJ/IU29P3yYsch8DL
w6GDueFKcmhtTaLLsoIw5tztfz1OnR/Ji8//265ufazAczEkWZEuwDJ820UjB8sYf6rqgnsGaFMq
k4/RqF2vivZ5ejxFZq4j5HxYIkrT0dvfR14iHiz1gFBjRkaPy0KB92AudlRi5GguJSj9i9apnV0C
9Q8mNjw2IhqKOYuyV9e6QbBpKJ96If+glayPM19wkoNu3wYrQpc35Fto6fYKFdY6dhE8nKPhcitV
/uItKlA/SbBd82Zd2+R5YPNcmQq0sWFXHgntGjncAGogKw7gdfoVMOM8623k3ZSxgx+hl1hERb55
2VAlad1Z2TVWotbB4SU6fYbYbkgvMzH5sJuCqbAAKfcoPFz1nWbbyWa08tpLEd7dFgSfxRMD6emG
vbRwvFQQjTUHayp8X4YhTp75/cn7s7BNav/nMANVwbzv+7PlcCBDE/FAkBmre/mWCARVoeNQi9yk
Lmy+/QFbBCSDmgH9dT+J0qyptUReayys26DpOx3zpnRbUVqoevpDLpdsoEIttEWQIhHlgFCwxqwE
aRk/jq630RhYJrspYYhMKJx7vBModJIEGer5px3GFiyOMr4+4I2Loz4N0yOCB4NxzVtMSM+DMFzb
Yqmp3TY7W03MSy4BUlptWvy4cfrCDCrea8duJ43frMTKFTfbW+IerIgRfu6o1EW2xXm1cTpBK1C5
GDw5N3ENOo9k6+Og7Rv6BqrZrvmt4KofAZpoRQwtrvIUEswUfZzexMH0dWDua0IDEUztjkju9U3k
MYVajimuyW6IXCYU0qQCvsz9sBM2LLZ1x1Vup7fB1Ec5aPwU/UHatOkTm3aX0ZLYdmaCrVM88w9G
XHeo1x2sSQwb3bclHeYGqJ5KFtGY8NkrjA2kOqD+X2jo651hd0o8X/ii6dRA1MaQa3XRL48KOtEM
HH0PUmnhNz19o5YiXS60R4NMyF8DBJ2arUQqgtrBdHpYd+zsNwOO4FJe/HVkB0g9fp75mEMH5PiJ
iCp8PJo1jsqW1yWtRGUFGwq3z88uUmySC3W8F4jZcCA/IVM3H1z/nL/Xi6GkPU3ho614p2M5bRq2
14TEYUDIUMMz5OS3VFeKp3NLgKmCpVj7tbmiZi9T8Yde5BbWfETD2YjKPY4NPYiw4TNz+908oHc2
yTbewFueWvL/NaEUrh1xMwQw0DRkd8xsxovrukJPMeMMIOpJVuHAqxeQFIhjwyO05shLRO+8ICOY
lVC8RDu4KIeHaBIdj78ETsgHAau5157cMpNdCv1z6u/eAEhsPNaTpoYf5z4Ulz5+vbrw+Ig6ywPW
AC3chkAwdqF9uooKaqUaS0uaMYKHDaK2y5UfVCBUcfko4mCk+jjZbqPR4oE/RY4mRKF+S5KVRb51
goeafsPpARmOwOZcbpLNMXGonqOUJEFV7nFBn0sn+mMycGAzE+JXd2B03sI8g6vqICD4805s8/Q7
Q9RvYQCBXt2A6pU5gu9eZBujlJ5yteDEmqSPNTNLHzUtnYMoAcOjjRN+mnEfti3CP2YaqZYc7AEK
EmGhccCK28g3Iq3fyEIwqSG5ZMQqTqoqd2RXD5hdEa8/QoSw8h+tBDysQ5iCskiecYnVoVm2sJ9g
EiFptSQHJIy0hyW5bqu4IBzo173gYuxltoA/x0vJsCyFYs77QhbyJAFsJLmGHqO3cT9lndY5RmIe
G2IsYZVzwYIn/hCH0vy7GSobNYDvEMIvGBaU5p1UTsf1zLoaBwNW5il64Rmt8mWVqr6Q4Cv07zk7
YKXZHTXhEeAgsPcWekKsDPhosTQ1OG/Lbmqe6Xtt932gr1mKpZC9HDG0zXIrXY+2oSE8WilO1BRy
J88nrrr7Yu0oYnF4wZWHuAWIyjgLKyWWX4IP/WRaze8T+DWjRzYC+x719Lw3Own8W4ws2iTfKhys
/AoSQctmniBEUleebvUzkP/54oUfgrmlSFnT+LQI1wpo2T+VfQtutqXZD+Q9onWKVVV4HeEbkZlD
NiZEFqgI7BCHMNKvyQsr+gN3d1+ljxpDWwjLTifh1kNDK1FTX628L7Esv/ze15vf2ojo/9c1/gl/
t1SV+B85OJEVM2ghrmoVc/L4ECZPJK0ZQo5F/4K6TFqIGKCvu6JvWCTXCXXQuvIJWVCf3yQ+xB28
CnIRjnpjYhPYNojhQfb5Zv+GZ7LFqZZ1/o78veE9yuWl0lUlNLkf7AciAMp2qc67QqLSzbmp+IIZ
GRPGcMLDzgqZMu5UoNLRtDcIK4IdO68RfVU+DfGj7azU8UasdLC7EXFxENSmQ/djh/0I4Ci41R+q
wsa+kmx3eYs+rFXPF/gpMof9+m7gcNIlaKRiKrmGwaefZwbiLS2b5ZrIZ6dIXfBst6s3VP1CYaaa
+z49NTCU0GqV80EBrXnRQ63CMSRECEHoQlN/WGzyaldjxjHPYO9Hmx4A4l37hy0X4CBEgwcgcLmn
2IaYATXcAYJj2x+86KLB5ybH7SyK4Ew14BYjahhIhbE/HpiaKw6srEVCnQJsybU/L8kpmLrJFJJB
A7L0H6rsyqypQ0Gw1vYRNT/Iq1SfeeCbJucKyPaC8FIIMxhLscoBs871BAGV6PnoCQwWlPdh7wt/
cV+rFe76p7fOp7y/iWBGEIZ3hi+nWA/1wg/Gwy2n5z+TL5zSsOLvSN/UaFnaFFlJfzsshhbbzRjm
u8HmR4iISYlZfg+PuCGg4qWDzTm+W3rHe0IKKFdTl4GXGM1/EpTtOAqbIDIWKEIZkJ5l8b15nkSy
kXA7m+xG+B2kCr6obeLcnH/Kll+3TvkRO20Bb17nVNUb9o9OAtuAZf0dsN0dkMWVbDBmARX5RrB8
Xaso0jhmy2GD0839FOGPRmjq0itlZIHy9gyGxFuelbdXGBP7YJlreCebt5nS69xLW/ntBMeaobHB
+fuRF9ZeLz6NIAjircenBW7v07uWGziq8CV4rmH/bVbBQVpgNLXkN8+irSvzIih6+uQU+4qnhkGf
6DPM1CIN42m9ynyzhboG0MwLmsmxfHNu6W7pdDbuQK0nD+bziOLzzqrXLBnyPXGnwpO2QuvUEpHz
JbvGAC0fH3+ZHVgO2K75xWmD0ckLOS8k2Z5yXiDsc+mex5g46t0h1hrH4Yyvs+xHhn22sZ5vmAd9
z+TAxX31wRoiRQvb/b9h8k+DfNRbYFTRb2ARM5f0wglZ2CBCHU3UDca46UnCcX0s2i8dCJiik+U8
1YIMvzM1YeyL3p4mMj0N+JIFkUtiWw2Iimbj4Zp6ofh5N27FA2Lw2SNpuIQppGII0um+Cd8fl8LJ
wmvWzSxiUir0Ax11Yq2EPE4jm3nKtv2sY0E6lx8WJYJydjXzqOwe7I/q8cblI4Vw7LJj+vuX/Vac
5mEUxAfQSPmHwmPnz7dWxElLo7zN511DK5ZEC8GBtiK9/m3RoIfI1+3Csl/GLaL5uWLV5jg3nmav
Y0x1hldBRI4gGM/8vCOKB1q8BY8TbeB6wETtrgJDpKK2w6lzrgVWA5wHTPjCuFeJZQKurXZeL80g
JJpIX8UxxYd+U6Gg7ji8gqW9cjciYoznCFRSJAcwiV6/RLQ7TMkMWTU2UPbgRRUhP5AJaTlsHLBG
kDpRv5sUys85ONbc5+pksLhtG+6Vd/mWvnomEBms1/e+jX8+Af6n98WPo67PSdCntlBBB0GpSw77
A58uptTtJh3ZnWGQRMSuQLMvad/WJZKosSXA1e4gAi8brVgIYmbIc2kzpFVAw8CT8ZJVQt0dh7lh
8tVc9ifnMjHMk7eBB/kSfTmYqiH66g/FPPIMThz2zJc8uB+JcA65L3cTruK5TAIZfFjQsRhDD+jo
+IQSPEMe5sSQGn6lLvuEYseLQbSEswNwE1xM0mWOmQTgipmdzDR1ApQU7CJ3glXHI7CVSZ+Ptc0x
tMhQKU+3nMUBMdbrbWczDZr8+LtuVq79gy6RjWSEvDiU8k/C2jfU7gvAAhYeQmEWA2ZDfrBZGMUe
ctwS4RKrBsgrdotouRos6i7rnUYet3BfSROrkb0kSdMZRGxAyAEEU/HXaAAC8PBph61GdBPOjY2o
ucgy4/5j59ePvr2AHV13YPvzcUThetgzbOE/iQtfdAyChyoVx/t7MUXlzDXK9YyFeO5akcWlv5cV
/tZmdn+0Ip2LqVVRXFEBSoKdQdXJdPtlxjfAelCI04ov4YoJ58o+t0nhwgO7bkbIx87oHNgrzQ2M
F9Nx7WUW7kGIwr83dm82aDD3MxmSYxoppKine4XFBSQuB5OgrdtAHhsoSTFIgdLrqVtjPempXbGk
sAGCyeTTFU5G+XjRzr/5F6bDtFizNprxJBKDaht1ZHz7ETvgFDqUE1wXMVV/4EQdWo3mWO3IzFHy
MHtIRlXUch3GQNXGHB3VG9FfABO63ISUv+i8letcphRuJGaIqd6D140yb1j9b65V/pllsmcXjxZI
Ah43oD+OViZ853FMzqnn1m6QUPSsMZIRyqrAz1NPtluN+CJrw1FCZVpiTakwpdxU24wYPLdzkJVt
MpfNjTp4CfPgAm7JSZ8uNwQriV6W+lMhO/nOlWDmWdpkvsTuaEmfMCDUgnSLOZS+lGvmuwQqc4c7
zpaP6+TmfafMbg199BGBGKHnAzZYORNMzqGduqQH2rfIjXYsYhgEvrviZ02MrjLaQZP6+Ut5Alf8
E/kL+HVFFRph1szoSkmJ7EBXybrGUR5qMCQirKzjN+9O+mZGlpjLRjEm9OvwEI2YBAdnbEy2PUIS
EppQU9iHilUApIhfes6nYf+wBw90smvQ+ggytyPZpyUuHI4qtFg7oOfeQJsHmMUTERb3j27kJedP
2tYr9qiiRWvUkdwJ4KJwqWf4pQgGognpwYEamf+1nPv2wTMMQK8Xx/yjdn10Y0/KWTAYXLQMmYjz
1frZ7sNr9m2G1bncTeAGzAAYatbj5nvolqrKxgG3z0xhGVUVc40Ki2Nepm+7jD8G0IY0ml5LLddn
YbZpN/8M3Qhx3Xq5oGiH/2TnC8sMX0iYn2UCyLxrWczitSRdquyZOivyQrbiaox+Q14RjH2RZNd5
aQF0j+++AlFnkxA005oCTlPjkpfMTIc4RxeeLQJ/tOK503oFkgsrCogo+yF12lnKy6igucSzbMPn
3Wor45sypUNSbvvkuBCYT1dqOqZXmmu2OwrJxxib2arzDMD+Od3/2YCFIL50cnXvoIjhEB0DXR9K
/K7a88aV7qbJ4DHBzJ3f0XIdiFQ8SQgz7J1rbVBgheu6FymoZephdjJLqZb90iDDQWVJmojtbzXg
gFOUIz5M7rwsn1szvg6OQvvyk2BO7F4pzU/gosxylIy+ZgksSmVFg/qaV20rZ1k+aSKwrFaoQyeZ
RFL+1rHpj+IbGKJ0T6azxeZPrSBdULXO4GIJdvr3Qb7m1uZp95FUpJBDu9qVsBeW+e88fCT6V8gX
VS6NTuR49358rzHdu4P84iHiJvQ86U9hTj3lb3jjwQAZN8p0kHLIhJ/OK3HNXw+RTjLj3vFhUR/i
IRh025GWPgCvLKW/Fcjs6l17Yf4iBubssKiYf8wlCs3fcp9iubVKMP7pRHwefSdGrCymu6kYmLgw
mqeCa1xHRtdyJWo9Qe40/RZF/z5wrG4kAL6/QY4JsNK5IuaqdL11AZL2SCSWi+If9d6xMChOcgdO
Kz8rL/ul1zVN4v9usZdnQoWuT37LkO/XTV67Fotcg6wt/2SklpnESLjZ8scuc4uMPNBaKqJxjusu
l1vSBAc0RfX+94qdKAB1kZkl5L/0wR4MeVpy7u7MCHssLTOzpzCO9upNisBXiFFPDC00CfVouYZN
XXF0RkU9ILKEeChv27SW6Gi7Qy+jku7OC4OkwVTtOeSe3uN21fa0MxUAVDqDcSYih33eUdQ2UgQt
L6AkF4QraqjCQmkNLaNY6/FADaaIph2sC0y2v4R6EliBhBDUC/ueMaaLEicWDYdky6CenbfyuZOC
Uvu3Y/IwIV5G1ioj22TVv+/LM2NMXlM3efeBXVFLlpk0glMoySXNMXgPIwpcUbWKr9MvEuUqvHfU
Ua+EPFCKPWY+MPtNhxODgEaf5SD42ilmAXixVxbfQgZT8KDy5ESHSevUnG4beDCiUOx2OxSZYEd2
WecJ3ZL6564z/G4fc7Om0ZIOU9ng5EgK5ufct/8wDhJxhrKfWKF8oGMAz/NIeDg+KDpnnOd9TWC8
m1C/nAlPRFVJESuKzp85N/iFta4ERlbMXC3KbBhJx19efD9AzC6BaiST96FqCaEQ0gbAZg+5M0vd
sd4uARkYKVZ+saEmK10NttpOf8+fMTy+o11z0fGYxK7evc99er/Gbpf39qG9yEfmAEVRfphmZPIn
SQf7u15eABhrE65ulYC9cW/1kD9cckhW3Ca6Fmggjt0dr5f0xyY9FGPQPcKlXF41lN5BHyQxsQIA
iGo9RSECpzORa/a8M6ZNFsEFb1RNk7PIJWUUTwA3yGJ86kp56QxDSwHJ3pphqBtvncSbkJA4qxYe
VYFrqoPM2y9CnuLtBx77VYq0P4lNlDZj2jk3mHJrjUoyGQJcNWMrbXeusyvrDBumKKKJuoCp8Ji0
/RMJ+8HFg8+R4uKqYvpIJg8NyYQ8vYA5vtYccRW0jvZP/i0U6PWDFr9Jttd7mvkTVOZWVQzQwIa1
CX0sZXUqWjeUdWRk0PgpbprIfHUzRGF/71Zzu1yRW2GCnx767EQ5qKMpDIk0GPjYaqO4xoSoi9aM
1yz/MP17scsZFRtDTEX3mlGXuzvOXzoZuF1pv+cx/HZyvxTWVigsZvXDBZjLh/wgy0creA+fBV1k
8fkV6zAuCk5dk5WqKFfYd+1UeCPMcZKIBp4CT4CSOy97C7PdZOfTtjBE2N1HOoaQ2ZxOQQfwlT7T
fBNkY0FZvjuckL0I+G/gCuS39PwVULFYbFIzpXBM1Nbej2d5BRC9Qd2AZu9sxMPtcZKUu95Tnwhz
RLTAtWmI3jpVmutYnGnpM5mKwhhOdMO3VOC5v3YpF592DzT+6/6Acs5ks+nnzpA1Us36PVKcWGkE
M1WjUqhQAuy5AFtL3rF2Roudc62UHxBXUcrRUznmTU0m6HWy5ij6umKW8aSGQEAuTFkgHG+/QK3t
lkny9IyYFmqLI8pYvOJTBRa/mUHj/dj/6NbKzslOo2YhiygO1nVPUAcgCQY4cgBaV1HZAFPnSrue
xDDcyoDCQ9XAq7HtK2PK5zi3RkeZ2APBYNWexQi62G+cTV00wfk/mJEXllv7M1McZl6EYNB7w7Wy
NSFsKlLu8YEu9N+Kz6RKVjxTNxRK8PL4e5PF+lnFbOzA7pjA2WZ8s4rN/GBsDQxj+iRTW9eFFwkI
55pwh0HyA5SIW3FjpJUf7cIrlGZ4oEXT7+1t1T2BK+cZECsvU3yQPWI0wujjI3BHqX2Avcr6Gfjj
Zt/BOCeLm3WPYbVnr5JtETvK2x7GxSyH+9LMO852zV25Cd+48P/c6S2Kw0ca728Ny1Y6KGbL3qlP
4EvN/TZ7etw5UKea706IUXwIQVwpP5jQ938y0oHDYwffAWQlBszHIVreDFPDhRH7grduFfXwkAZq
Xg1+sBIztw+hxqlMs53QCz42G+g9RWycycylepEsvcSk9fVNm6VmgeZfgi6X66giRnNJpU2PIBAF
TmbPAcrMrGqiw6Igp/NT9dLv+HdaubjRbMktYivcwKhtfvRJxOMuhYot4wWlUUavaDQbJmW24VmJ
ZwCVPPi6rQ4Nhst/OnX8HNiq2U/gTHWXorogGqfyr8Y6nwQ1i/rMdmxoA7b/GE1m9P5/B6xamFQg
EwXo+CxJrOCPsGlEdrtI/EomayDvxVj5CfvkkF3AfbS1sQsfyGGG1tUvsuzyG6HbCWTS0DgHLYKw
mLw/kac2HudY+pRGugwjN7CsZhMmmjhzcrMq0IOLuASVzEQ07NRtu7qYo3gXq8qnNgGi3DQKDYrw
SYfT6Pwt/XDOLV/1Nwm7lrkBfprfCHgW0qbPVabJczWZCD+LcxtBQw3gU2094NvU7pb7yPhlgrq0
cS5wrnWHRgkSVTP2nTdECUOf2uvdv6UAYuKZB+WHxfuNgMuJy+NNx5KfDuofgKn+lYGw6REYH3Ka
ZOfYztF8bAdIPEvwSawpzhGQAiNBWeC79fEj8BBPy695w6r/wK/tqaFZeWkyTtf0I3GsKFAFjoZf
KzKY+NxdAAJi0qPk4lVk75CJ8kptfpPfFywJQmfyBb975TcM5vpsuS0OLQ7PPrjlQ3gHCKvA+H4n
QPQpKtQRoRv3axSt2d5bX+nHX7sDe0XLK+YohWnf6W2r8ED9onbhdOXu/KX2OHKoCbv/dCpO3JIs
yPgJIlcsES6Z7VNPf7AG2iCOhM8IJc2rkfWNF05kCosrhh9zj72ovE8RIohjbE6NHLiuUlA8oede
e6MJsIbj7L6BcoK50YtZJ47mkqQ53XN8aAc4J/rI7owAq6S9g50tYefm3L0nPbuCGWHERzd2gjBj
eixz+xrcNM7tnJIQKf3BHG5GEXQzMr8loXRSFArDmZxS3+X0oRJlIt5ZBx6wPaJLw/47C403FaVO
IQ7rKIj1J78aFfPu3+RUWyAxXdSUla9IOrNugivXxl+/pixnEdfqFhdGh7sINrMDr3Gva7MydLld
aT6Xxy2ZXoCIrn3QUJYKAx8iSWuYEwP4DqSnDEcIzqyptarJmsEalMCp9GrYMqhCwNqKhm7QFRVH
EJZYkgW+8UMhys0ogbrtFGbOrQzAPtBJbeUFIniW3mJQMXc79i1yiE21ixQ8ixak+mrYSNslA3e6
hUZFTZJoh5xpuHQYY1nBk5twjasanafpLNUSwBeNbZ44LL0/WMXxVmEI+OffB5P3t3OhAtcLuUmq
dmfqUu5wfet7GcTzjZMame10OMV+omk6zhW4JKpGLlaOc5wx6/zoGhGWuaT+cWFv7j06y/IK1Ge5
VwYmkjNekZd73ikRPgWbiiTGW9uE4WwlB6bawr+FtFUk26pt7kv3iGZfcaexkYk3gFuoCjMatcxm
5iJBYNcSz8AWR2X2L+XKSxtSf0hQgxgqoTL2UfsFHmKChrS4gCUThdVlzTQXUx4eyHaIJJH9DnFE
M5L/7tl89MeROUUOeAtes3QIlHeFFHBL/Ji3cfap8ryGMN1/gtgWdRFkXnoX+G6hQhXwma8qXikA
LWFDlKPRFEnz45o+6OCrGzLwe/otDBFLGfQ+GWVpN0kV/uZQ75Sf0e/PsUXpFnaLewiSKank6gwi
8yF+WH1FQE9YQ18xUl4fwH8mizCAxcpFYsA0t+RbSUT3n/4OMU5Qp9o7PN7lBGRIO5p6cMtXRnXC
JfW5MAwmEbuYLebmtXFTuJDEJn0GyquYWPiwpRZnv1ziMZpHifvHl8+OztIxJd2mYoB0qILovXrv
p+sSoT6d+Qt2nOaFyPi/m6CB3U6EZTDb/lY9CEtizEw/HAA/6VwkE8uIX7K7vI/hr2H0tduoiiNC
Z7Qlv61NGDw+Zsk5lf/EB3d4KiMTGGR+U3OwHtOnm6VYC8rcu1iaHeniGKq68Pd4RNabdW0SEWBG
SCsEB5twlwDDXXKD7ZjGPdrzFL4xeUQOh7FvLbwmC9sr/yhddMvrFkA2V9wW905QTisuA8OW3JSB
AUh4iRU5p3eIXnK4bV5DGLg5qrBMXKp7ITgTUsrz1GkN0djgyFC0XYoOcjI7B/yHlOip+3I0y4mv
lvXPbxrefN6gyKaXEaeKqc8lkTrapgWmcul9IqE2dc62oipP4yfF9dyU9mxlW10geK1g24KEyzGo
BeRphtKG4Qmo+nfR7liloRHvowONq++DWCDl7U64lFtPGM8DVJ8L3f2O4dZ63W280QNqOHfM+D3v
oYV1BCKRuIDzGPh+aSQpVALS7SpCpa9vz5n7NadTJvhdFlHr4KfuJX3Dh2oImi+n71N0Qn84euc1
fOD4vRyV2dyrbvpf8ZyzqYuhxBpx4gleNeoUIVPfagb2FoQQ+bskrJ9Fzaop3uYeyYjVHHz9Hn/v
kD96iS4c3YZAm2tkHGVHg07+rB7CjCZASOlDUuBZBYy/Vf49Oo6ZIbyPX6zKW1HIZX6TCXgL2RMD
Z18i6bS4dVWdamjHoVM2FEWy0zWmP48ZzqIofGQ35eZ/S/W7DX9ElshVXWSoz2DnttgcYeQP85Uy
g9m+ziCUZIcadRW964AoRUA3+eqQFMd4s3bDuqBW3XcuFpHSRPXh6t0Fs16Zxakn48FFt53gPuPn
kWccmrUbXLvLcqhA8NtpSsiryUclKgessi+7wqGZwaOZ/56iVBpZqOJwABqb37gDS4naRX5Lhm3s
m3HaTaYcXMsCHqn0auTQIir/uX4q5UPZFQ8Bz8UC3UKxfj5ULvWsnpZTirNjNzizmAgQT8RVbgzU
2G5ppcdSvbuZsNpQGRd4Pb6lyI9TgsK+1nbLlHGhemrdiL/34MiuObwmSLc73QRRBxNgFET6e1Lv
o6xWN/l6TErNc+6EiEwrxgHsEDYFHeG6qnW1ueS9Lpmo4/z7e+6wy6Tl/b5WouFHRr5e9BLEbuxz
42BX4dBB1w/PfHqyvQ9VWKQ2jLS19zH4agGu55yMenuP9MgLtErIMJT+Bl4ELPGwB6MlUUqTZB3t
VQC2OppjbtSjETZroDDv09xkwKjiHqEFViOwEy3sF9EdAetnX005D6kuc/K3fTbQi+m6fMRiKN2Z
BiUYhf8XENvED3ZMQxboABD11DmJ1e9Fs74DiyxWCij5drQwOkqqstt1vqKAB5y7Yfz7BEDaiFt4
N/hwftM3GyDIag16EDHX9KUEehn7+WAQVjm8M9q3X05bEsi+YJzDYvQ1YUMmCywjgkrU+we6Zlfj
jwHfaDlARpdR7SkNfEHejmsi+v6oKmporsGFi/PV6Zto0tsGqVmsM4rG7ACZ9Rr67LZv2ZBYmau9
YMgEVa7MgE7o+XRH98+6g76U+vPo8sDSXBzjLxrUWj7LbaLAwHwCiaHAk2NE6S11a38XlxU9q4Rc
V/ZeXX8H7FNqwpWafLtSUSFGjVEl2UPuR+LqiFTtg5pDbXTI3RUZ/1FTQXdKgs8mgkiZobQpzFE/
rrjhpfu5U2VFgUt175KUgZwXZkH/mSNkaexiOIwbfcsZBAy/tKw0ZMHpRgmxVxs6aDNEnWMppYML
mirp99KtxeiB4YkVvhoCIgRH9rd9f8SjF4hpmqeG33F+I/8aGa/B9TDn9mIOB0MkA9G27OhNWHti
BhiDpachcuiKHNRXtROW2tZ6QSKltulLhEE2tKS5ySwwxUggM23fjcafEriJsOg/75JPoP0f7KSD
GKya9azUZuLQNLPDToOlCvYyOgxC7DwAJSzAineFxmxudrjNaala4ME5f7ber08k0H7a98KpnWhr
7Wj2/ZJ+vEdRg5LF5JobYzKvmpaM7hGgOO0Y0TDtIOO7HUt3HbEwZQnXW67gaNwbS1SMvRGswaYx
K6wkNU8q8NKtgBuc+BLolYfLBZRJcyR4yNDpU2ZjHuWIT4ts/OFFXInD84SDkSXjHApALHfZxsnt
cTfPbSH8fDmCJm8Vuoqw1xgU6RGcrAVPTlI/Bq6t7tCPO+YaS7Zc7owdZvEsNMbqoZsmDCFe8doV
8cVthfoNVR0f3SFwHIhWyLqcudCO3w5Kbmclzjof/qugz7XI3W4up1D76MJKqi3dcnruoFlabFxm
tSwx3GSlL+5B2O2YixhTq2xSfw1sszftRCihJ0NMSoRqkcjUCZWV/isTBo0MmbQfNmdasTOjZ7ew
2BGPXSHQT6V3s6XY14QEqIGMHPF5erZNNQZhY8yMaHagYfd2U+nuwBd7aS4EyGQFpNTw3QcKE37V
hGX17EZiG8Wq6MY/44BXOfTCtCeKo/byhuif/pVMsu+ca4R5zGuY3CiVWYEsPvzxF/qKifpxZi51
XRmtFk0dvxCb9LZijwdOxnyH8ZiWDHs7mJnDVpcWUMPZU8IvqumksK95mbWFPl5LqmMFM0jEs8PD
mTfV2GTjPFDNIyUlS5wgr5mAkFV9aGhFTJyxgym8HJTFTPnH5yHrrcc8JJLtN4hU1di3Xn1fE3uT
opoRvS0bdUapON9OlwVhd26jM7wCZBYB6trMJ8Mp76myBkkv39NINwvcNz0C9PjTC2KxxPuukWtR
w/yhSCjv3HZENtmeUszZgrIUGEER9oAiD+owYoWYlewK0ILXabNAqrhmEBqBHrr9oqgbcYRDzuYy
tXp0TFqhsCtk673OJdQGB6Oio70EYcvfK2+/+lQbm8RY3MMrGTIdFT56B/KY7jNhS0GK2TQxwqhs
TRZFKV/ZJk4siqHTytH15d/JDe5gR0ZT6YLiWctRZ0o7rDFAuWGOts2T5plZkYkKlicuij/brRUE
VoPwjXc21Asul2nGZ4oqWITvNNvqsSj3pZcib/NkEb/ywxjqeutPrWHdY2z9bYYV0afl6iN+OJPF
mRYM7kLjlkifzhHkjMHeNI/3PFm0mygSZsjtHDrFRcYjNY27pFqwHt2ydv+Y8I0N1SDHvn9BLNJu
oFVKeuo90KYeeut8r9DrRTYqFOonG2OEQDDLAFRufZ3qQCoZzCVAz2808ZTxpmyZlUrqqRB5eNoR
fjg1JW2zKpsRpYXTmNQeMRdldk+Feri5oq9cGD5YRVbI8qXrgCFVgnHaSb6bgNKjoxu7ljGDhDlA
fyljqWnwjpwLnJrnLEEPxCA0T5/et2QButOgW3nnwmS1l46RTyIuJvDC37QKPJAoZiXW3NONxQ4S
VMkIxUni4WFNp61+I8ALmhKWYBMnSF2olRUJgjx/5EoFbnaRnuG71h4SLeOPIDGWQZc0jBwrQoy/
p39/L/g1wLZ3FqNDV7qggQZ0GMY0PqS78funhvJ8e59DeuguR3c8Qw2C0tcThu571K4wpX/OFbnY
beeizjT0zdkHhRSex+8gBUGhTbaSXFA+qwXR9xCY+C7zYRTKO8Nx+cPPqtw9pP9PxBswmjqhEKt6
3Ck/ADyCLZdGREp/A68XVGVvHb/JvfOg35vhDTnY5YS2yaSxtOlTrfweIjcpHNm/KYIfyfc8tE37
vQgFgsHKTN1WfK5wTNKf7aRiY0HC8102JHI+A45viX2RWjDbdLJq2Y7F5ppx0BUGXajkekHFHtTP
zGH4mWnc+ZM9cxpDbZHg9CWY03g1SIePCaPv+IQWravG0Y5/FjoT60o3H5FyFBudgMVZ3cp8VzJe
LvD1NXLx34aC55OogymYf2wimfHqDswutWmnj+tuNMEDOInqQNq9UcHM/OyxxtX8wTTT/NRUFeVm
VeKtfofxOPU4GgEr7q/dgpmmyUwpJdTmUIWgEo/EFBgHOpfX6wnVmKNZLK/35u6h5zONTzL/dQna
H6zFQ6I+cQKT5ug+al7l3k03OO7iBB2zXBSdPjOWpTtDodnsbHMw86WcpUsjoqFkiDJh0K9pAiTs
yu0YtLXYhpLRc8vLx+nlNPLnBlewheD6Rsel2vUITR+Y0R+LTIVcFizL3RkCWpgT8Mv7GFBus0bs
tXa7x74NoVvDOv16dK5Bp6co4kem5MjsBMqulNnb5qAiSRSAHjJVEcbgiN/ejphUzKhhnQ2rLlmR
J0srKz5SDkt9GoLIIQYs5LiQz7IybWCgpgj6AsAgzJv8o1wGzGOJFcuutKhU3byY8gX4mvT1mcoL
+oV0fltqMUZ5+7fYGYXRzx+IoKYTulFlekV7KaIy6pn9anlT85vVRhfq3tNZZRGuUALVSiHKp1Bv
hSH5jlo6taMLCDODPF39Tqvftq6OemOjXklUiPQyYpE3hA7qrG4TTmxYZzDSMPUrCpTcgg6vjYA+
icfYFMU1pgr4fLmYJ0fROfPHuGJh8j+aeRnjdDL1S9T5mRS4VQFv2nBpMet9lpa4++KbevKGFfwJ
BO0QF4h8xYmLMoxmJE4LfilYtw9dGxV5baelDnfq58HheZD2ds1QdE7sNtEpXV6y/daqe+F0IrwO
EggItvtulBViDAFHzzEs4Ors+9e3U7TiRkh+FQouUA4zwFshY6xGA6Dbnol3ZBzdaBUiUM72DESu
4f8i55WEiA1ksZPV3YoWd/4fFxoy40yp+YAThVsC3PUgYwIJd+HeGGy4QmzfwbeK+mDAR9fhkgPx
nzDL3LV2Gv3HmCCLPBRF3HWk89YHpBOvD6r+uOVfqkM48561HfV7l3A6apzVHxEOEh1IyTyiN4f6
3KVzCDqCvavPKeaSnkFs20XLbL+sYELy1lix4/B4BOvvSBa6muSI5EwkO9IYHRp4SldDU/BoT6Cf
qRS1nv1bScZ42MttKPlYo5C+D45g6wpNReoA61TtaIEPBZNYtLw4TsZyYTF8v5ZzdClRynhRzcCS
TDxMcqXxYDSNoJqUrB7zcYe4AU3uO+Tj6wXoA39LLbsKtK1EY16dK5eicLPwSoFRhW+yHzcF2R0r
WPJGyuHI7ddZdu81doAYgdtje29f2PoQ7UdSTUx5TaBtDIJ3Rj9hzUirGokvUqbl7/aQny41+3XL
F7yI+f+1hfB0KztcysNAoH/Ef6mEeMnfNIZ1MWfgKXi2mHySkygQ6NWZ6vvA1E4qyMJXH6Ff48/K
gOLCxf9q2hiWqZQnp6Xn75CfUcw3BVuhzDPyLdr0RuUnInmBo6zzYXmuhUgWD3UZOwbOLMbQde1E
4+ppigWbA6D8yjjDH5d///Ez3Ge5UANdGKtn5+zwt6sVz/UnNbLaIxHavGC/XYYHjVzK8UBa1goj
rRjxZYq+/vP9jTUVM/We05Tuu6Vhr8Xqgqbs4LxdLvSY5ZRtfkiZ4ZCcUX6PAd4EH3/mr2iiXXwk
MaHxtETB5c92jL0MYVhAngHcoQp4PXcVgMM53uyhUPz7f2ILQV2YDlsJucEYfDq13cpM0FlEQd0h
5mhrSC7d1cT9pzwN/S9h7Qh/HzA8ELwUmuPuJDo2/TpqVz3rFrdQd6zrjucPEC8bNXyMJ4KKbI8D
jSOb8qPFWrNmF54vmxSvOh/OuuWoD9f3nVoFgkV+u9aHOriGCvKVf9fo+9RKQjPtDXcFXUfhU3Cv
MzmWBqGndqHMPSFCJwZft7uzO4LOPPH0VfFoxWhRynQwCPBocMx6x0YUJV+M3EFU6Vu7E3kJrFsl
y1fn4yO53dC25b8g4zcCCiBPZyfjr/dEPpI56AfsYVso/JiXvsCGk4Q44hgxk7E2o05UqQCMycBS
ygQjxTdflOik9YO+XOKbMzwwOKB9IrJf7iEl2lQF2K+TkGRUH4+zgS1JhcVqHPMQR+DJxVpWfM0M
H47wPKt6giCxmkkimy+FeHTdZ6hz+24lzsFu3UbXHAwWbAtim+kz7tWoUwDCuWtRez90LMVibV03
s9OTE0S01WDnqkPCfv23N97xtDZeKpUclYjzfg8WN4IphB+xKA760It6EE+vAg6sslhPeEtILCY4
Uo32QdRhD4sEjjub54P8JzSNxRxNbgJXU+8ynehszPSEyuxl5dDi1AscV5lkhXQ99VE3kbMI8ilh
QVUy1qYXE9K5fiRAV0MgOjL6GGRYoTf4n43A3FTs90xm2IHT/tG6dfy45aY7VCkDyOLAsNg6qbjb
S+am1g2mbZSI1nM9RhmFc/sBTe78Kgm7HWfCi6EV9WsWjqKGa5AaRsASsm7bd1npnUKXCxM53zTI
77Gkmb968Gfj1eaXjJQdf892eoN9RwJPsCC18O81xXkHoHW9rpUzV/NkTfGJToNKY6n8O/U/gp3y
AG4NmQb+ohRjIbQrMorHExbrqsFGL4eC3yc69mOV+v1CTYsqda7U3Kustm/djGTSpFqDUaNUmNv7
s59H+WB4s7H0P4v0ac2cjyGb2JiekKYXjqytCQsMiVJwOtyNM7tOjPKEr5DFyVazHv2pRLOhaGVG
87WLyoRqDpuHLeZLjrkoa33bl1FYrCa3J6+jJ7/V3xNnIZQChJxZvKwYAjZaE4fMV2ZZJnThqFaV
jzThXMsUKhts7V+pxPK+9zyGMAfbJb+gqTodEbZFGJ3uAmuFe4/D7u5r4ULee1EtBh9bcw2j+Ola
cNtHZu9ufBxtKXSETdazieWpvDhS+w9bsCl/1kwyTaNvigZTEXWAX7zN8t/Lv3wG6d57wx/BxB+E
F8OAUdaEA/l/kXOG0XbxRG2wQEbzuLgDFSmrE62VEjJinXmf1q7lMpmlsJOGH0t6Vpx6OC8xz8e0
9F6q/ODk0dxRYn1TlLWz5oHLnk5CLNiWA8DqRrYx16q9uzU6zk/7a2dB6MGsTzhiIU00omSXkLY3
uhJSd6oKTQspc9w3uPCrB095lhsz+vGhD4iM4/CS2HsS0zXvKKDnVX6r6sYwhAYS1txJn8cHejTS
33a3FzrLh/Lr8tihbnmzdHQJtk+sq7tZb72rWrEbk48sbF9yJahsTCRqNmxxIiHoM81CkKoI+Lxh
cfc0D5Yp/MomiNvkLGAQL9gJNP3W0OyucO7MynZvbq3xjQW7UGuTkM+U7elqqbUSHoc+YvoRMbS0
Wra3OUa9vgiPvfWOPUXkCzQ+GZz5oh+zUdgV9KFSEg78gDsnyyeW/ilBD6TtAk9pe6QKH83lGlA/
2bWItSalCQk+8HJxYzEowKqYFGa6IaIc9tMb8mXj8fSJrYpmGSaaPDJJbiFsHkgzUgKFO56A6/eF
ldbJbZmhU48DLTEq3y10q679uNFxpRjMbj1VLTSaUJ5hhfLgA9jgL7ku8ypfmsyML/AFtmtYlAYS
x/hfNfqd/HxrFDj4suOVtrsEgFli/p8rQFuk8bUKKi+qMACYCmucfH6KPKuWAuxGCuqam7J+SLhy
F6DV5jjns6q2TiCqwQ/SFDGGwNWkiXwsljkpcugaJxrggWO350nMbF0QYxh1wDeVmRmPTvIktQeN
C2vym6ToRxoNYTF2Tp4Y99bkBeDapsuHhs2C3sEBcQs8X6JL4hEvCnkrhPhAFYDvUWiWd97v1xEF
JXyVXUJkVG9BXgkFfhxRC6VBtIUPWaRXjsqkEhgA4GfNh9Ato1kt2NsNy0Yk0TuxhhyZVCo9JfjN
xOUbhJqEzzlTH8+IdmNPKx43EGDT0Lrsk/UOaUPBvFWdb3GqIMg4TchPjXgWpuyR85DLNpqWKB3K
K2K8dzks0hfLCIP0o1ZrJyaV6vTRLX6GDJX6JZRDQIcYVYCtM38a642Um1FZz9czprkChHqQfL3B
NzQrdtyK7LIW3fUDo5pKTkFMk/BrlxVPsmRbDFKf4rxCbgZA+dTNUmlpBauC7VYTM5YFkM6wgAQf
kvhXW9lkApSLz8wKN03C6wRC66r8yh/YqKG+OjTUsFovJrTDokQK8MgWGIzpNPRCNORK91DK5GNY
HEXIaZzdLIwnRbeaVleFh1M2/3aFZkINsBeVqebQim1r/XodkwvYfRJymSowdoWJn6/gXjWYYZGh
nHpo+U87TYAoe/0bNSftOYIRvEYmlBQPHk/YuQ7Jdb5hXqiv8iaBtaRv3kWfgGc6JF0PyuLIJmQz
sePGBoxGEAi/gTPFAp5q7bYdVvVh+ebZ1KPCkgVP67PIAZMIBdM7ytHOVT5vyhBUSnzHGj7tsaK/
AqD6UoWrkSts4FsZnh9O4M8pkE8Vm26V8YWdgHnDnz87zqQ/CBdX9Nf6pLsk7Gm/k4IQqgnaYV3Q
djGKNtk3QKG8x7u/AfFVjfC3uxos9Lej1HjxSt7yMGU5UStm3a89d3ADmdllSmHXG8oaJwgC5yD+
6ZyoV+S6O/inHAAITWTqNss+CZq3wQ2fSPRm3iMIYujSFh49ZWF6Y5hhATGZ7puV05IkX1gc8Ela
qcxST2cD5iqJ2QwgOpu3pXIdq8sop2UlJ2ii2/Ct6PF84r15S+LX3gLwJ/KnCGF+GUwOWmRkx3Hu
v4EWljx5OFiNNQjpL6/VF8J8mZgV0Yatyn1p4Zb53UROPaTcM7aRopMguRKwhgpbxYt/+eTJW6XO
DU2onCq+kdiW47TN2oEGrRxvPPPOq8/oSOfJtP28+4j2QIWKpNEEkyM1waSHRIK9ySAFcsxROSmZ
y5VUaZHpge4mjt4o3wek/wS6MwWVPMsAu3hEPxAU1KQr/u9URt3MMa2fLlo4iYegrEEYe2yLrrAN
jfOlfFl2WAfnBn0q9dqaZPhtJGkjLcv87aMFcrI8E5sRxgPWXNHe5E3yM7fFaxtQ9czAwy5HBQ7T
gJgBJSPfEfU8e3x0JPGyrdeTDJ3A7ttFutTZr1mNDvkDS1bKipmWU7JPSOW9iMIXgy8z3KaMV17o
y3aq0spIkFtfHwEMlx5tdEz8T/iwPwSqX7cnQdq/VsqDUNNb4SVzr+cYcHaGI1VbX/0HzDuMomQP
8bBDfD6NPr3YWlufkhrsbQfYW7WwfFtn5mraBA8+uYpAnFvNL1nN6ushsbMR1N+vSXjcYN5NACl/
H2124SzQrgKMKsLqQRU44LOU1vbHbBKDecnaquvebNH7p2feemLLqYcfbhQerM8RTzfGlW92BjUa
pGu7s0UvPCSvVvGLI6kKWChXl/Ug0dnDJutwDJbPGIIKIcK+2NPBDWx7NvZcgk1vLArNWzWWN5i0
Z8dDhZ6CzgsX9JZYvHPLyXwjLrgSDXp6EkJ3xaVltlxsSPjIWuSJ5UR2t3a5j70+y53DA5hawRIJ
BflpJHyKmzPzoIY+XozhC5geLbq+MLSTkXTA+Md2N7j1po0WdpbtlNFxKyHKeOmAG5tXoFNxuonX
NfKY106GmQh1ErXt/sv1FnwsfMlB1zi1P2UI7BNRKZFKqOrCBbJHJCnZXGXx5HE1jHd9qZY8pcf/
raU+1iunjRWFwqi0m4Q/8gbHQTiFqXI0Vta3iD7PfOvOLzc9cuejpa4JY/ddtS3kX2TIpZRySbii
XgeFxsoRZG/o05PSNLi9egYTmlUgVS8d+uK+3hIvzh7l7GM7KBHA/q9Nsn2MXkbuM26NH3qxiAea
Dn32PsY77N/kRaam/N0h1Zw1y+Yze0k6Xo7SvXAa3PeIHINvxYjsqA0DUbJAr2qJQ9ez9vPSqTOB
Dhbd/08MfHVAhXHpF3fM+00YOk9kcYkG9Ri/eeixt2oEDZaKzJLnnoqvFxeWkGjVuZfdk5dOu9v7
ExEKEHZo+ZvJiEXLjjzmDtZFould5AIW+q3ME1xdRFAo48yScl3GdhltW7oIIwCbxONHp6pPH1DB
UKn3Dh2Z6TWDBMdTMe2/L9TS7lojLF/dKkQy/l5IxcOXSsyxUWAVpL5ZrB9DtijZUUpLiHlAFei9
Y9Z+k80OmqZhY2yO5s8R0ALs1Ft48o5GjKhCgHF72iPb/y0d1jf95FfmUoxwezzrhskMaOCfFgg8
AphxbFX/k+52qiLuQkjtJScwGnNfZDEzWfMjSThKXVI/arwQ7Tn55JqubDkyP18b3uYJ3czC/KiX
yv+ED9+8d35HV+DzUtygwZY7rrisICcU3NFk7cc8i1jdolvkOva04x34YiSWT+zjbKj39iDgMJfP
nq1M1Ah0h3m9u3TgvvOjbzfU5dUNe5/RyIdK0LTLLKGFZO1jZL2P6ntEgfg507gCdVHVavN3mTHX
IPwxe6Y6aJ52LnrwSvqTlTplUK3PXqyywVm3ukSQ8najZI5ITtibqu8sJzJxPESP1h/CGEy2irf0
tKuFjzq4iUmlE08KwGR6AdQ90uUyDZ7BInDpap0TUFE2yqj+Cmg/RLdONz44miMbIJ+DAxSUi2MS
CVoaEGRDgZX7L+1GCwlSyMt9OauSexn2E56pMGI/A/PNjcGrIdxkutQoK2YRlg7i6f+wNb9Y2gcM
YzNWLYz5uyo3rNjHRcKm7HEbiWcCdoOlOc1k1c55wLySin4bgMGuA9UXa2pj15QXYNFMeJbtfhwm
ar4+eZn5WyZ6Q7DhbN8CKPpHO9TyDPvVgQmrAQcWSBAx1hC6wirnvf7ATJlrz+DmfHI9E026mId6
KH40lG9jMqfrWu7g7s8wz6nIBiamEhcd5objUHUEmMKbsASQjGVhZA6QbCbgAukMJWUtjQs3kGXc
FgiOMoJpGeYNPE8MJgGTMl4eB3OVuQh36cD5wqXzYC8GP17NZ/0WINIk6TBXOsOpv1WCDSwhzshP
zuOsK8lBIWHJFZMEZp1ygQP/cGs0RyCqkD8ulUBTV+K+EZcy6DXjw67oee/ALKZrhgkjW/cAGZxd
eGZowjoQwZjMCPMMu4WX0cMnUwzIo4hU1IQi+ktIpNRZkliY3/li31LBpNye1mMA1I1p7/jq9Rb+
No3LbhHCont+fMEy734+6OiLsjBXts+/ro+qRqYFtjyT+k0RFo619T77Yp2untdxkjuR6be0s93j
vPwKi2VrjYaTCJbKSM0oj0YtWmM4nSWlNLkS2h2rjbGdujgcDPlU8I44Bo2G1oMGiCui9FodkZtG
kOBqtjbv1R/z+321jpGACzq25FPJUSd1xst7U+0GLp/EzuEpptq4ISk5nnvG8OpY7afVlV5aPFsj
MBQKt8uSzd/dHgxVjmPeqp1cV0WABPcaLzC/ehxbi04Q
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IVxyk7XRM4VsQcD0QPYws4xsTeDPKdwWYfreQJ7l1z8C+G+JAKZ2psrNI+b5ecZ2ziPH9MBGr/oY
8XtzCKmjJw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VO3Jpo4aYF9TyVwyAUb3a/oDy8Yhm9ea/9mAjNtuOBRL0qoy0/CWzL7D+bc1SnZvEP4BG903Ildl
dM2y4TNyVTBUaU7Cz+LzZfu9kCPWnmttlx92LcMKLNuvGUMPXmV5jr3PzSFEvoDuCinMqNc8uKFO
Ux/aX6fmBD8AbQfpK30=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qOkimDe0rSU5f1zKvoE8a4lZw1WOOUxh8wtTIN0ys09AXuQuNNCdfu6VL2Xuj0Xus09sBU1FazgW
XpQHuw7XcozHRlnUFKPJg2P12yPJsLRkOqUWtHTUXmH/8s2RglOoEcmFeX9FVh1IRMdnp+D/F4GX
/80OwH0Jtm4eUDa5EFkNoIfhlOG4JOG/JCsYRnsAoZAbyHMEk6qPxdOGDrYzkbA3CMCikTuE6wOm
0j69ZgENzpWR5aludQDu44oKZqgkdMKNm6Mvk//s2aUOTBYWabbSKe/I/+cEp1tWS7+9AAmaVwO+
KwmsZsNR4Ztb6OH4hCq0936o+bycwR0b+Wr1VA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4df1QYXbx3PmA5i1scwSy/ZAJgZ0wNtl21eeCeUI5h4IQD2UalJOUkc5a5UR/j7lX9ToyF2yFHzK
L4EoH+xXm54bGihfoaTvocQQsWhCDObbmBOtqB6WS1/bog7FNgoEObi/E19vJsjPSd6nCCdhglZ1
j33mJRkZed+lVziTR/s=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Rtu5N6w0tnewss9ZQUyM3gMzu1D5Ba/+qJO2rdGgk0QN5Nm+4TaVyiEXzVM5DP8z3mycaRD+z4HG
QXarW6RH4GHKahoLlSY8cryjSJRWS6D7/Z1joY2fgJb8apydMguGWjRZ/uW6R7BEimGxB3Xuon63
ZdpcvKZmoyvfg0kjAjor/DxtP3SP6DKxH3BeegGQKpP/+5EmCrAhhPu+NA21340wcbghotvyYusJ
ErSZhtj+1FLwV2sO7TUt1etBG8nf/yETDQPE7Q+zX+BzOktmY3tIKds/9qdyDt6Qb5WIxLMyaMa3
eyi0SGAuZdeDtK8Os3w2ajEZI+VjufruVqtCCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17760)
`protect data_block
yvvRtu+tA91Rtyv3I35O4K6BiUlBjs7LTFLRc9twWgYZkATXrSpXZut2NlvE8mcC7mB31ueT2vlU
P9hzhGYaJ5GcmScpsC1FKNndMfl3Ug9Pqiw49YT0Xp/AQWIr+q38Pu2DmkLm87YVBi0HN6JMSu6G
rwJt5qvXJYVA5oSnqcy27I93z0KCdBaCW4BhEaXbMLEY+qzcYsWxGhgjRzVfC2OhOSpdpDr2MKHw
1YDri1cTZAVy/b3L8VUTlyQx4YRG+qS3u0Cz3dOLm9nglzh9Pa9XJC4+Lnpli7w7vpvakaXaH9W9
I9Xs/9ShuVul4UrHUMsoz9V5jcPh1iHPT9m0ZTeLUdfod7NEEFDW47vWU8XjL6iEqBvA/DrJKrri
hjJ//n7fbl9gjxGZT+IKqHleRVz+dRiS/uTuRo22UsAcWrLoCdroE0x4MAJ9vC0vScZa86PQBj0m
ixJFhU15XHesAUmaWmkIVFZdUdZL6n63C2nZpQmpBX8G1td46ib/xrjcP1HPzbr1hPb30S/GA95D
4e3ICss1yPb8NZCwvzZHNKYRJlVJ6EOWwDxLeBOjWmUySMUcywo+toi8FWztPmB/Fzs/gyRSBxsb
FBe82kj2NTjDK0dD4XCcU8bGjVOKNJ3KoJmC+0UD0jihX5N1CdPg7+/bvmP+MCdk3ondXZKJzYI3
9YFYkr0RM2BhF57jZwHcHHmFJrakmG38Lap7lsdonuIO5mfOOuicr4JGW8Qijs1+c7VMc6LUwGDt
YKznnHTq75vwwVLxmtGYpW4RTIuqlZmOJwC34kp9oVx0+wFtUxMvQgXry9FwUwb2gSWRseSfbmMB
auDz+22lW+enEoOu3PzG3plNq4oQP2K2H++ZU7HNTNGSA6VpJWDQ1c8o+i7+XEkyIqt9DZHUxb+3
HlbwgxRkMYX88B7lb3GnNDLF2YzkJMgQjpyPi+t3N2MtquCFuqNuaKv0LoD6+mwRceg/hAylp3x1
m9DKQ0DcKuhctFlcx3aOGMXc0mzgjh9Umxn2Ng7JEliL6/L086w36Jar0AAtsKsXZ1NsDDBpiIeT
c9pWEQj9ud2144CtZKOT9/hr1wy8/jpi1lQaHanlWWtc/eb1aDpSY58hPbltVjUTyizUFFWsqQAC
PGoqDXF3N036pR2Ipsz0lKGQE6qHOZ9IQByoJkJfVJQFD7arWnGsW4G4I9tdTj8LBH1I0/XQKvur
lSNx9C6iPx8J8GemXPHqEIipG+GgoeMURYc7ft3GzrBdwbTFPm/qrxT/0vdju3tRDBl4JSzWO+do
z/s/CD6wNYNcDBCSDKcprRdML0+tkUYr6Jexl5rxIe2GBG2XGRgBDqc+wBSNJY7VVfutmSr3NjPK
RJK5NldZFn8fT/rjewbLV4flhMn1tgsE6HhNm8GuRS52PpzP+BK3fCtYvb1mnkFy+e3mwc3RgZ45
5iaZGmsBwnJwI9GcgMGoWSDkSaL/1PrI03WtUczFAidTPvIY08FA8CTdX8Bo/j1vK5yj8spVzrNq
2YNw08dzyQOA6p4yaEO8Raki3qlKk9oCGUe72zvHFj8EIo6DPYz7MTOBMZh7qLr1JDqBA+iyQCSU
UO9dElHR49OYArhLqejxnXEbJqi2McLLRKhJoiH7B/feWKz5mjNEjtWpHgiwx6VhyEKkL6UZ1Rib
ZtiEI9gtUbhZ6XzaYm3TiIRoYgTzxH0j8bAv7Zy61YnOi5ds35hrlF48AdxPXK/eT9RxLQ9JC4D+
xhLyqoQdstrt5DgaM3NxG2mKEJVH9uc9wj8j/rmn9YrBedhVek2F8Uvojvb9UP2S80Gz13xgD5DT
uHlDBG0pjratONtNE06BnMLwZRtD8fOAmitaJqr+uurpGUSmFSP1C9+FHTWgzBTdRwxLO8vYdEOz
WFiLspZhFCxJpRdUt6N09XI21qtC+0+ZgVoJcuL102pig2HCGw+mVSkibp2ZzBHApj3TyyQWeR0T
soE6qVGrU0cCA6w+mgSp/LpLjFALA+nFAG3lXPvfyzy3nWkgcWbCXiItZJY+SdblaE3tEF0j7zRy
QEv4a8Rg+L6tHbS4IhpoHW2u/3VbDszbEYb4sRKfYUA0hAwJaM8jOAxyu4YRtJsjn94Jek1Taiie
hp0Ndlnhy5vlx4q5I6i8Nc99UyR9uhRu8iqRtT7nCYuJSAzDby3Uxqh6srwmKPrb31KF5pRhTgEE
hoDR5pRAhvr+p6GEHRm1IAJTB/vA3Cmck+beIM8DaYRIdaZnzC9N04oH+sWVHExAUc9WW2ZHotPC
yowKFvokfu+7look6EHxqKtkI6qUIsFrQgy755fSnh7+GR8EVZFKqkRCDv0zQz3m3MIaUQ9GzxNA
nVZg02l+SgGZHXvy8wOZE4ONpWcUccgX9k8Mqf2VrJEhn7FTdwr/L68VLWlWyJ51gTID4qsEbmQR
eUcVhXwZ8J6/Jr+tfQkihSE/r9/FrMS9DtCeXZFSTXFkRXX3jwy08FYzVkX1AU3nfi5uob/pWe44
jJ4c+H4TgTK/YFd0U9+b9+hcQ/PKCmyuUWlZMD2jh2m6YaM0tRHT7pTE3k+5NorK0KIzBPhuhR0P
kwadh+BfDa9Ed/g8FI4r9aO+bzUYkbubz1m2BkiyrHNUN4b/jhDQyeuJYsvVZmik7vXZ6GcS1rnC
ZJpUE1bWR8FcYhqQoncmXGI126qn791BoIP3g9UyBSGDJ/hK/eFW6lylhaaJjjVsKepmxGzcVN1B
mCwVpKVdTSGBmK72htH5om7KKA2S1rC5U1UUj3MbiW7ZNwfDd0USkl8imBDLwgYFtoEE1ko8C7Jc
eUprl5A05bpIwcNw4M1zuvcSJzD1rtWdZQl2vo3uekE+ox++ptfYE1O4Xj/2TqSRnKWmvElAWcGk
d1P93oZ45PNjviXZ8GjPM3O0qWdvlgjvAq0xdzA6x0TysB9PpseLW+g8nB6svNvi0GhK/LLkeLYg
V+VOQradYifDOr8PNb0cqid1ncvsR8+c0tlZfcJr23pLfcE3Vqz5wPmHYoK484/vAUmQUEHiXjLv
MiKyjk8ywnYHQ/TOYWuO5OiF3b4XtDucLmEyRzxNB7rY1i7qaj6wGs15PP5RLOMaDOI9Kg6163IT
YHmjt12E1isvBtgqS4df/zN19hcUsAr+Hd+fpoCiaRD8qfZT7eD2F7aDUpS5tVOH7gVSyJWqzQ5q
Obv9Yhw7rja/O45RtfCLUeQNveIdOxbYJdxtkbtNUL4THMOaUooUKNDHf2XRJ/IU29P3yYsch8DL
w6GDueFKcmhtTaLLsoIw5tztfz1OnR/Ji8//265ufazAczEkWZEuwDJ820UjB8sYf6rqgnsGaFMq
k4/RqF2vivZ5ejxFZq4j5HxYIkrT0dvfR14iHiz1gFBjRkaPy0KB92AudlRi5GguJSj9i9apnV0C
9Q8mNjw2IhqKOYuyV9e6QbBpKJ96If+glayPM19wkoNu3wYrQpc35Fto6fYKFdY6dhE8nKPhcitV
/uItKlA/SbBd82Zd2+R5YPNcmQq0sWFXHgntGjncAGogKw7gdfoVMOM8623k3ZSxgx+hl1hERb55
2VAlad1Z2TVWotbB4SU6fYbYbkgvMzH5sJuCqbAAKfcoPFz1nWbbyWa08tpLEd7dFgSfxRMD6emG
vbRwvFQQjTUHayp8X4YhTp75/cn7s7BNav/nMANVwbzv+7PlcCBDE/FAkBmre/mWCARVoeNQi9yk
Lmy+/QFbBCSDmgH9dT+J0qyptUReayys26DpOx3zpnRbUVqoevpDLpdsoEIttEWQIhHlgFCwxqwE
aRk/jq630RhYJrspYYhMKJx7vBModJIEGer5px3GFiyOMr4+4I2Loz4N0yOCB4NxzVtMSM+DMFzb
Yqmp3TY7W03MSy4BUlptWvy4cfrCDCrea8duJ43frMTKFTfbW+IerIgRfu6o1EW2xXm1cTpBK1C5
GDw5N3ENOo9k6+Og7Rv6BqrZrvmt4KofAZpoRQwtrvIUEswUfZzexMH0dWDua0IDEUztjkju9U3k
MYVajimuyW6IXCYU0qQCvsz9sBM2LLZ1x1Vup7fB1Ec5aPwU/UHatOkTm3aX0ZLYdmaCrVM88w9G
XHeo1x2sSQwb3bclHeYGqJ5KFtGY8NkrjA2kOqD+X2jo651hd0o8X/ii6dRA1MaQa3XRL48KOtEM
HH0PUmnhNz19o5YiXS60R4NMyF8DBJ2arUQqgtrBdHpYd+zsNwOO4FJe/HVkB0g9fp75mEMH5PiJ
iCp8PJo1jsqW1yWtRGUFGwq3z88uUmySC3W8F4jZcCA/IVM3H1z/nL/Xi6GkPU3ho614p2M5bRq2
14TEYUDIUMMz5OS3VFeKp3NLgKmCpVj7tbmiZi9T8Yde5BbWfETD2YjKPY4NPYiw4TNz+908oHc2
yTbewFueWvL/NaEUrh1xMwQw0DRkd8xsxovrukJPMeMMIOpJVuHAqxeQFIhjwyO05shLRO+8ICOY
lVC8RDu4KIeHaBIdj78ETsgHAau5157cMpNdCv1z6u/eAEhsPNaTpoYf5z4Ulz5+vbrw+Ig6ywPW
AC3chkAwdqF9uooKaqUaS0uaMYKHDaK2y5UfVCBUcfko4mCk+jjZbqPR4oE/RY4mRKF+S5KVRb51
goeafsPpARmOwOZcbpLNMXGonqOUJEFV7nFBn0sn+mMycGAzE+JXd2B03sI8g6vqICD4805s8/Q7
Q9RvYQCBXt2A6pU5gu9eZBujlJ5yteDEmqSPNTNLHzUtnYMoAcOjjRN+mnEfti3CP2YaqZYc7AEK
EmGhccCK28g3Iq3fyEIwqSG5ZMQqTqoqd2RXD5hdEa8/QoSw8h+tBDysQ5iCskiecYnVoVm2sJ9g
EiFptSQHJIy0hyW5bqu4IBzo173gYuxltoA/x0vJsCyFYs77QhbyJAFsJLmGHqO3cT9lndY5RmIe
G2IsYZVzwYIn/hCH0vy7GSobNYDvEMIvGBaU5p1UTsf1zLoaBwNW5il64Rmt8mWVqr6Q4Cv07zk7
YKXZHTXhEeAgsPcWekKsDPhosTQ1OG/Lbmqe6Xtt932gr1mKpZC9HDG0zXIrXY+2oSE8WilO1BRy
J88nrrr7Yu0oYnF4wZWHuAWIyjgLKyWWX4IP/WRaze8T+DWjRzYC+x719Lw3Own8W4ws2iTfKhys
/AoSQctmniBEUleebvUzkP/54oUfgrmlSFnT+LQI1wpo2T+VfQtutqXZD+Q9onWKVVV4HeEbkZlD
NiZEFqgI7BCHMNKvyQsr+gN3d1+ljxpDWwjLTifh1kNDK1FTX628L7Esv/ze15vf2ojo/9c1/gl/
t1SV+B85OJEVM2ghrmoVc/L4ECZPJK0ZQo5F/4K6TFqIGKCvu6JvWCTXCXXQuvIJWVCf3yQ+xB28
CnIRjnpjYhPYNojhQfb5Zv+GZ7LFqZZ1/o78veE9yuWl0lUlNLkf7AciAMp2qc67QqLSzbmp+IIZ
GRPGcMLDzgqZMu5UoNLRtDcIK4IdO68RfVU+DfGj7azU8UasdLC7EXFxENSmQ/djh/0I4Ci41R+q
wsa+kmx3eYs+rFXPF/gpMof9+m7gcNIlaKRiKrmGwaefZwbiLS2b5ZrIZ6dIXfBst6s3VP1CYaaa
+z49NTCU0GqV80EBrXnRQ63CMSRECEHoQlN/WGzyaldjxjHPYO9Hmx4A4l37hy0X4CBEgwcgcLmn
2IaYATXcAYJj2x+86KLB5ybH7SyK4Ew14BYjahhIhbE/HpiaKw6srEVCnQJsybU/L8kpmLrJFJJB
A7L0H6rsyqypQ0Gw1vYRNT/Iq1SfeeCbJucKyPaC8FIIMxhLscoBs871BAGV6PnoCQwWlPdh7wt/
cV+rFe76p7fOp7y/iWBGEIZ3hi+nWA/1wg/Gwy2n5z+TL5zSsOLvSN/UaFnaFFlJfzsshhbbzRjm
u8HmR4iISYlZfg+PuCGg4qWDzTm+W3rHe0IKKFdTl4GXGM1/EpTtOAqbIDIWKEIZkJ5l8b15nkSy
kXA7m+xG+B2kCr6obeLcnH/Kll+3TvkRO20Bb17nVNUb9o9OAtuAZf0dsN0dkMWVbDBmARX5RrB8
Xaso0jhmy2GD0839FOGPRmjq0itlZIHy9gyGxFuelbdXGBP7YJlreCebt5nS69xLW/ntBMeaobHB
+fuRF9ZeLz6NIAjircenBW7v07uWGziq8CV4rmH/bVbBQVpgNLXkN8+irSvzIih6+uQU+4qnhkGf
6DPM1CIN42m9ynyzhboG0MwLmsmxfHNu6W7pdDbuQK0nD+bziOLzzqrXLBnyPXGnwpO2QuvUEpHz
JbvGAC0fH3+ZHVgO2K75xWmD0ckLOS8k2Z5yXiDsc+mex5g46t0h1hrH4Yyvs+xHhn22sZ5vmAd9
z+TAxX31wRoiRQvb/b9h8k+DfNRbYFTRb2ARM5f0wglZ2CBCHU3UDca46UnCcX0s2i8dCJiik+U8
1YIMvzM1YeyL3p4mMj0N+JIFkUtiWw2Iimbj4Zp6ofh5N27FA2Lw2SNpuIQppGII0um+Cd8fl8LJ
wmvWzSxiUir0Ax11Yq2EPE4jm3nKtv2sY0E6lx8WJYJydjXzqOwe7I/q8cblI4Vw7LJj+vuX/Vac
5mEUxAfQSPmHwmPnz7dWxElLo7zN511DK5ZEC8GBtiK9/m3RoIfI1+3Csl/GLaL5uWLV5jg3nmav
Y0x1hldBRI4gGM/8vCOKB1q8BY8TbeB6wETtrgJDpKK2w6lzrgVWA5wHTPjCuFeJZQKurXZeL80g
JJpIX8UxxYd+U6Gg7ji8gqW9cjciYoznCFRSJAcwiV6/RLQ7TMkMWTU2UPbgRRUhP5AJaTlsHLBG
kDpRv5sUys85ONbc5+pksLhtG+6Vd/mWvnomEBms1/e+jX8+Af6n98WPo67PSdCntlBBB0GpSw77
A58uptTtJh3ZnWGQRMSuQLMvad/WJZKosSXA1e4gAi8brVgIYmbIc2kzpFVAw8CT8ZJVQt0dh7lh
8tVc9ifnMjHMk7eBB/kSfTmYqiH66g/FPPIMThz2zJc8uB+JcA65L3cTruK5TAIZfFjQsRhDD+jo
+IQSPEMe5sSQGn6lLvuEYseLQbSEswNwE1xM0mWOmQTgipmdzDR1ApQU7CJ3glXHI7CVSZ+Ptc0x
tMhQKU+3nMUBMdbrbWczDZr8+LtuVq79gy6RjWSEvDiU8k/C2jfU7gvAAhYeQmEWA2ZDfrBZGMUe
ctwS4RKrBsgrdotouRos6i7rnUYet3BfSROrkb0kSdMZRGxAyAEEU/HXaAAC8PBph61GdBPOjY2o
ucgy4/5j59ePvr2AHV13YPvzcUThetgzbOE/iQtfdAyChyoVx/t7MUXlzDXK9YyFeO5akcWlv5cV
/tZmdn+0Ip2LqVVRXFEBSoKdQdXJdPtlxjfAelCI04ov4YoJ58o+t0nhwgO7bkbIx87oHNgrzQ2M
F9Nx7WUW7kGIwr83dm82aDD3MxmSYxoppKine4XFBSQuB5OgrdtAHhsoSTFIgdLrqVtjPempXbGk
sAGCyeTTFU5G+XjRzr/5F6bDtFizNprxJBKDaht1ZHz7ETvgFDqUE1wXMVV/4EQdWo3mWO3IzFHy
MHtIRlXUch3GQNXGHB3VG9FfABO63ISUv+i8letcphRuJGaIqd6D140yb1j9b65V/pllsmcXjxZI
Ah43oD+OViZ853FMzqnn1m6QUPSsMZIRyqrAz1NPtluN+CJrw1FCZVpiTakwpdxU24wYPLdzkJVt
MpfNjTp4CfPgAm7JSZ8uNwQriV6W+lMhO/nOlWDmWdpkvsTuaEmfMCDUgnSLOZS+lGvmuwQqc4c7
zpaP6+TmfafMbg199BGBGKHnAzZYORNMzqGduqQH2rfIjXYsYhgEvrviZ02MrjLaQZP6+Ut5Alf8
E/kL+HVFFRph1szoSkmJ7EBXybrGUR5qMCQirKzjN+9O+mZGlpjLRjEm9OvwEI2YBAdnbEy2PUIS
EppQU9iHilUApIhfes6nYf+wBw90smvQ+ggytyPZpyUuHI4qtFg7oOfeQJsHmMUTERb3j27kJedP
2tYr9qiiRWvUkdwJ4KJwqWf4pQgGognpwYEamf+1nPv2wTMMQK8Xx/yjdn10Y0/KWTAYXLQMmYjz
1frZ7sNr9m2G1bncTeAGzAAYatbj5nvolqrKxgG3z0xhGVUVc40Ki2Nepm+7jD8G0IY0ml5LLddn
YbZpN/8M3Qhx3Xq5oGiH/2TnC8sMX0iYn2UCyLxrWczitSRdquyZOivyQrbiaox+Q14RjH2RZNd5
aQF0j+++AlFnkxA005oCTlPjkpfMTIc4RxeeLQJ/tOK503oFkgsrCogo+yF12lnKy6igucSzbMPn
3Wor45sypUNSbvvkuBCYT1dqOqZXmmu2OwrJxxib2arzDMD+Od3/2YCFIL50cnXvoIjhEB0DXR9K
/K7a88aV7qbJ4DHBzJ3f0XIdiFQ8SQgz7J1rbVBgheu6FymoZephdjJLqZb90iDDQWVJmojtbzXg
gFOUIz5M7rwsn1szvg6OQvvyk2BO7F4pzU/gosxylIy+ZgksSmVFg/qaV20rZ1k+aSKwrFaoQyeZ
RFL+1rHpj+IbGKJ0T6azxeZPrSBdULXO4GIJdvr3Qb7m1uZp95FUpJBDu9qVsBeW+e88fCT6V8gX
VS6NTuR49358rzHdu4P84iHiJvQ86U9hTj3lb3jjwQAZN8p0kHLIhJ/OK3HNXw+RTjLj3vFhUR/i
IRh025GWPgCvLKW/Fcjs6l17Yf4iBubssKiYf8wlCs3fcp9iubVKMP7pRHwefSdGrCymu6kYmLgw
mqeCa1xHRtdyJWo9Qe40/RZF/z5wrG4kAL6/QY4JsNK5IuaqdL11AZL2SCSWi+If9d6xMChOcgdO
Kz8rL/ul1zVN4v9usZdnQoWuT37LkO/XTV67Fotcg6wt/2SklpnESLjZ8scuc4uMPNBaKqJxjusu
l1vSBAc0RfX+94qdKAB1kZkl5L/0wR4MeVpy7u7MCHssLTOzpzCO9upNisBXiFFPDC00CfVouYZN
XXF0RkU9ILKEeChv27SW6Gi7Qy+jku7OC4OkwVTtOeSe3uN21fa0MxUAVDqDcSYih33eUdQ2UgQt
L6AkF4QraqjCQmkNLaNY6/FADaaIph2sC0y2v4R6EliBhBDUC/ueMaaLEicWDYdky6CenbfyuZOC
Uvu3Y/IwIV5G1ioj22TVv+/LM2NMXlM3efeBXVFLlpk0glMoySXNMXgPIwpcUbWKr9MvEuUqvHfU
Ua+EPFCKPWY+MPtNhxODgEaf5SD42ilmAXixVxbfQgZT8KDy5ESHSevUnG4beDCiUOx2OxSZYEd2
WecJ3ZL6564z/G4fc7Om0ZIOU9ng5EgK5ufct/8wDhJxhrKfWKF8oGMAz/NIeDg+KDpnnOd9TWC8
m1C/nAlPRFVJESuKzp85N/iFta4ERlbMXC3KbBhJx19efD9AzC6BaiST96FqCaEQ0gbAZg+5M0vd
sd4uARkYKVZ+saEmK10NttpOf8+fMTy+o11z0fGYxK7evc99er/Gbpf39qG9yEfmAEVRfphmZPIn
SQf7u15eABhrE65ulYC9cW/1kD9cckhW3Ca6Fmggjt0dr5f0xyY9FGPQPcKlXF41lN5BHyQxsQIA
iGo9RSECpzORa/a8M6ZNFsEFb1RNk7PIJWUUTwA3yGJ86kp56QxDSwHJ3pphqBtvncSbkJA4qxYe
VYFrqoPM2y9CnuLtBx77VYq0P4lNlDZj2jk3mHJrjUoyGQJcNWMrbXeusyvrDBumKKKJuoCp8Ji0
/RMJ+8HFg8+R4uKqYvpIJg8NyYQ8vYA5vtYccRW0jvZP/i0U6PWDFr9Jttd7mvkTVOZWVQzQwIa1
CX0sZXUqWjeUdWRk0PgpbprIfHUzRGF/71Zzu1yRW2GCnx767EQ5qKMpDIk0GPjYaqO4xoSoi9aM
1yz/MP17scsZFRtDTEX3mlGXuzvOXzoZuF1pv+cx/HZyvxTWVigsZvXDBZjLh/wgy0creA+fBV1k
8fkV6zAuCk5dk5WqKFfYd+1UeCPMcZKIBp4CT4CSOy97C7PdZOfTtjBE2N1HOoaQ2ZxOQQfwlT7T
fBNkY0FZvjuckL0I+G/gCuS39PwVULFYbFIzpXBM1Nbej2d5BRC9Qd2AZu9sxMPtcZKUu95Tnwhz
RLTAtWmI3jpVmutYnGnpM5mKwhhOdMO3VOC5v3YpF592DzT+6/6Acs5ks+nnzpA1Us36PVKcWGkE
M1WjUqhQAuy5AFtL3rF2Roudc62UHxBXUcrRUznmTU0m6HWy5ij6umKW8aSGQEAuTFkgHG+/QK3t
lkny9IyYFmqLI8pYvOJTBRa/mUHj/dj/6NbKzslOo2YhiygO1nVPUAcgCQY4cgBaV1HZAFPnSrue
xDDcyoDCQ9XAq7HtK2PK5zi3RkeZ2APBYNWexQi62G+cTV00wfk/mJEXllv7M1McZl6EYNB7w7Wy
NSFsKlLu8YEu9N+Kz6RKVjxTNxRK8PL4e5PF+lnFbOzA7pjA2WZ8s4rN/GBsDQxj+iRTW9eFFwkI
55pwh0HyA5SIW3FjpJUf7cIrlGZ4oEXT7+1t1T2BK+cZECsvU3yQPWI0wujjI3BHqX2Avcr6Gfjj
Zt/BOCeLm3WPYbVnr5JtETvK2x7GxSyH+9LMO852zV25Cd+48P/c6S2Kw0ca728Ny1Y6KGbL3qlP
4EvN/TZ7etw5UKea706IUXwIQVwpP5jQ938y0oHDYwffAWQlBszHIVreDFPDhRH7grduFfXwkAZq
Xg1+sBIztw+hxqlMs53QCz42G+g9RWycycylepEsvcSk9fVNm6VmgeZfgi6X66giRnNJpU2PIBAF
TmbPAcrMrGqiw6Igp/NT9dLv+HdaubjRbMktYivcwKhtfvRJxOMuhYot4wWlUUavaDQbJmW24VmJ
ZwCVPPi6rQ4Nhst/OnX8HNiq2U/gTHWXorogGqfyr8Y6nwQ1i/rMdmxoA7b/GE1m9P5/B6xamFQg
EwXo+CxJrOCPsGlEdrtI/EomayDvxVj5CfvkkF3AfbS1sQsfyGGG1tUvsuzyG6HbCWTS0DgHLYKw
mLw/kac2HudY+pRGugwjN7CsZhMmmjhzcrMq0IOLuASVzEQ07NRtu7qYo3gXq8qnNgGi3DQKDYrw
SYfT6Pwt/XDOLV/1Nwm7lrkBfprfCHgW0qbPVabJczWZCD+LcxtBQw3gU2094NvU7pb7yPhlgrq0
cS5wrnWHRgkSVTP2nTdECUOf2uvdv6UAYuKZB+WHxfuNgMuJy+NNx5KfDuofgKn+lYGw6REYH3Ka
ZOfYztF8bAdIPEvwSawpzhGQAiNBWeC79fEj8BBPy695w6r/wK/tqaFZeWkyTtf0I3GsKFAFjoZf
KzKY+NxdAAJi0qPk4lVk75CJ8kptfpPfFywJQmfyBb975TcM5vpsuS0OLQ7PPrjlQ3gHCKvA+H4n
QPQpKtQRoRv3axSt2d5bX+nHX7sDe0XLK+YohWnf6W2r8ED9onbhdOXu/KX2OHKoCbv/dCpO3JIs
yPgJIlcsES6Z7VNPf7AG2iCOhM8IJc2rkfWNF05kCosrhh9zj72ovE8RIohjbE6NHLiuUlA8oede
e6MJsIbj7L6BcoK50YtZJ47mkqQ53XN8aAc4J/rI7owAq6S9g50tYefm3L0nPbuCGWHERzd2gjBj
eixz+xrcNM7tnJIQKf3BHG5GEXQzMr8loXRSFArDmZxS3+X0oRJlIt5ZBx6wPaJLw/47C403FaVO
IQ7rKIj1J78aFfPu3+RUWyAxXdSUla9IOrNugivXxl+/pixnEdfqFhdGh7sINrMDr3Gva7MydLld
aT6Xxy2ZXoCIrn3QUJYKAx8iSWuYEwP4DqSnDEcIzqyptarJmsEalMCp9GrYMqhCwNqKhm7QFRVH
EJZYkgW+8UMhys0ogbrtFGbOrQzAPtBJbeUFIniW3mJQMXc79i1yiE21ixQ8ixak+mrYSNslA3e6
hUZFTZJoh5xpuHQYY1nBk5twjasanafpLNUSwBeNbZ44LL0/WMXxVmEI+OffB5P3t3OhAtcLuUmq
dmfqUu5wfet7GcTzjZMame10OMV+omk6zhW4JKpGLlaOc5wx6/zoGhGWuaT+cWFv7j06y/IK1Ge5
VwYmkjNekZd73ikRPgWbiiTGW9uE4WwlB6bawr+FtFUk26pt7kv3iGZfcaexkYk3gFuoCjMatcxm
5iJBYNcSz8AWR2X2L+XKSxtSf0hQgxgqoTL2UfsFHmKChrS4gCUThdVlzTQXUx4eyHaIJJH9DnFE
M5L/7tl89MeROUUOeAtes3QIlHeFFHBL/Ji3cfap8ryGMN1/gtgWdRFkXnoX+G6hQhXwma8qXikA
LWFDlKPRFEnz45o+6OCrGzLwe/otDBFLGfQ+GWVpN0kV/uZQ75Sf0e/PsUXpFnaLewiSKank6gwi
8yF+WH1FQE9YQ18xUl4fwH8mizCAxcpFYsA0t+RbSUT3n/4OMU5Qp9o7PN7lBGRIO5p6cMtXRnXC
JfW5MAwmEbuYLebmtXFTuJDEJn0GyquYWPiwpRZnv1ziMZpHifvHl8+OztIxJd2mYoB0qILovXrv
p+sSoT6d+Qt2nOaFyPi/m6CB3U6EZTDb/lY9CEtizEw/HAA/6VwkE8uIX7K7vI/hr2H0tduoiiNC
Z7Qlv61NGDw+Zsk5lf/EB3d4KiMTGGR+U3OwHtOnm6VYC8rcu1iaHeniGKq68Pd4RNabdW0SEWBG
SCsEB5twlwDDXXKD7ZjGPdrzFL4xeUQOh7FvLbwmC9sr/yhddMvrFkA2V9wW905QTisuA8OW3JSB
AUh4iRU5p3eIXnK4bV5DGLg5qrBMXKp7ITgTUsrz1GkN0djgyFC0XYoOcjI7B/yHlOip+3I0y4mv
lvXPbxrefN6gyKaXEaeKqc8lkTrapgWmcul9IqE2dc62oipP4yfF9dyU9mxlW10geK1g24KEyzGo
BeRphtKG4Qmo+nfR7liloRHvowONq++DWCDl7U64lFtPGM8DVJ8L3f2O4dZ63W280QNqOHfM+D3v
oYV1BCKRuIDzGPh+aSQpVALS7SpCpa9vz5n7NadTJvhdFlHr4KfuJX3Dh2oImi+n71N0Qn84euc1
fOD4vRyV2dyrbvpf8ZyzqYuhxBpx4gleNeoUIVPfagb2FoQQ+bskrJ9Fzaop3uYeyYjVHHz9Hn/v
kD96iS4c3YZAm2tkHGVHg07+rB7CjCZASOlDUuBZBYy/Vf49Oo6ZIbyPX6zKW1HIZX6TCXgL2RMD
Z18i6bS4dVWdamjHoVM2FEWy0zWmP48ZzqIofGQ35eZ/S/W7DX9ElshVXWSoz2DnttgcYeQP85Uy
g9m+ziCUZIcadRW964AoRUA3+eqQFMd4s3bDuqBW3XcuFpHSRPXh6t0Fs16Zxakn48FFt53gPuPn
kWccmrUbXLvLcqhA8NtpSsiryUclKgessi+7wqGZwaOZ/56iVBpZqOJwABqb37gDS4naRX5Lhm3s
m3HaTaYcXMsCHqn0auTQIir/uX4q5UPZFQ8Bz8UC3UKxfj5ULvWsnpZTirNjNzizmAgQT8RVbgzU
2G5ppcdSvbuZsNpQGRd4Pb6lyI9TgsK+1nbLlHGhemrdiL/34MiuObwmSLc73QRRBxNgFET6e1Lv
o6xWN/l6TErNc+6EiEwrxgHsEDYFHeG6qnW1ueS9Lpmo4/z7e+6wy6Tl/b5WouFHRr5e9BLEbuxz
42BX4dBB1w/PfHqyvQ9VWKQ2jLS19zH4agGu55yMenuP9MgLtErIMJT+Bl4ELPGwB6MlUUqTZB3t
VQC2OppjbtSjETZroDDv09xkwKjiHqEFViOwEy3sF9EdAetnX005D6kuc/K3fTbQi+m6fMRiKN2Z
BiUYhf8XENvED3ZMQxboABD11DmJ1e9Fs74DiyxWCij5drQwOkqqstt1vqKAB5y7Yfz7BEDaiFt4
N/hwftM3GyDIag16EDHX9KUEehn7+WAQVjm8M9q3X05bEsi+YJzDYvQ1YUMmCywjgkrU+we6Zlfj
jwHfaDlARpdR7SkNfEHejmsi+v6oKmporsGFi/PV6Zto0tsGqVmsM4rG7ACZ9Rr67LZv2ZBYmau9
YMgEVa7MgE7o+XRH98+6g76U+vPo8sDSXBzjLxrUWj7LbaLAwHwCiaHAk2NE6S11a38XlxU9q4Rc
V/ZeXX8H7FNqwpWafLtSUSFGjVEl2UPuR+LqiFTtg5pDbXTI3RUZ/1FTQXdKgs8mgkiZobQpzFE/
rrjhpfu5U2VFgUt175KUgZwXZkH/mSNkaexiOIwbfcsZBAy/tKw0ZMHpRgmxVxs6aDNEnWMppYML
mirp99KtxeiB4YkVvhoCIgRH9rd9f8SjF4hpmqeG33F+I/8aGa/B9TDn9mIOB0MkA9G27OhNWHti
BhiDpachcuiKHNRXtROW2tZ6QSKltulLhEE2tKS5ySwwxUggM23fjcafEriJsOg/75JPoP0f7KSD
GKya9azUZuLQNLPDToOlCvYyOgxC7DwAJSzAineFxmxudrjNaala4ME5f7ber08k0H7a98KpnWhr
7Wj2/ZJ+vEdRg5LF5JobYzKvmpaM7hGgOO0Y0TDtIOO7HUt3HbEwZQnXW67gaNwbS1SMvRGswaYx
K6wkNU8q8NKtgBuc+BLolYfLBZRJcyR4yNDpU2ZjHuWIT4ts/OFFXInD84SDkSXjHApALHfZxsnt
cTfPbSH8fDmCJm8Vuoqw1xgU6RGcrAVPTlI/Bq6t7tCPO+YaS7Zc7owdZvEsNMbqoZsmDCFe8doV
8cVthfoNVR0f3SFwHIhWyLqcudCO3w5Kbmclzjof/qugz7XI3W4up1D76MJKqi3dcnruoFlabFxm
tSwx3GSlL+5B2O2YixhTq2xSfw1sszftRCihJ0NMSoRqkcjUCZWV/isTBo0MmbQfNmdasTOjZ7ew
2BGPXSHQT6V3s6XY14QEqIGMHPF5erZNNQZhY8yMaHagYfd2U+nuwBd7aS4EyGQFpNTw3QcKE37V
hGX17EZiG8Wq6MY/44BXOfTCtCeKo/byhuif/pVMsu+ca4R5zGuY3CiVWYEsPvzxF/qKifpxZi51
XRmtFk0dvxCb9LZijwdOxnyH8ZiWDHs7mJnDVpcWUMPZU8IvqumksK95mbWFPl5LqmMFM0jEs8PD
mTfV2GTjPFDNIyUlS5wgr5mAkFV9aGhFTJyxgym8HJTFTPnH5yHrrcc8JJLtN4hU1di3Xn1fE3uT
opoRvS0bdUapON9OlwVhd26jM7wCZBYB6trMJ8Mp76myBkkv39NINwvcNz0C9PjTC2KxxPuukWtR
w/yhSCjv3HZENtmeUszZgrIUGEER9oAiD+owYoWYlewK0ILXabNAqrhmEBqBHrr9oqgbcYRDzuYy
tXp0TFqhsCtk673OJdQGB6Oio70EYcvfK2+/+lQbm8RY3MMrGTIdFT56B/KY7jNhS0GK2TQxwqhs
TRZFKV/ZJk4siqHTytH15d/JDe5gR0ZT6YLiWctRZ0o7rDFAuWGOts2T5plZkYkKlicuij/brRUE
VoPwjXc21Asul2nGZ4oqWITvNNvqsSj3pZcib/NkEb/ywxjqeutPrWHdY2z9bYYV0afl6iN+OJPF
mRYM7kLjlkifzhHkjMHeNI/3PFm0mygSZsjtHDrFRcYjNY27pFqwHt2ydv+Y8I0N1SDHvn9BLNJu
oFVKeuo90KYeeut8r9DrRTYqFOonG2OEQDDLAFRufZ3qQCoZzCVAz2808ZTxpmyZlUrqqRB5eNoR
fjg1JW2zKpsRpYXTmNQeMRdldk+Feri5oq9cGD5YRVbI8qXrgCFVgnHaSb6bgNKjoxu7ljGDhDlA
fyljqWnwjpwLnJrnLEEPxCA0T5/et2QButOgW3nnwmS1l46RTyIuJvDC37QKPJAoZiXW3NONxQ4S
VMkIxUni4WFNp61+I8ALmhKWYBMnSF2olRUJgjx/5EoFbnaRnuG71h4SLeOPIDGWQZc0jBwrQoy/
p39/L/g1wLZ3FqNDV7qggQZ0GMY0PqS78funhvJ8e59DeuguR3c8Qw2C0tcThu571K4wpX/OFbnY
beeizjT0zdkHhRSex+8gBUGhTbaSXFA+qwXR9xCY+C7zYRTKO8Nx+cPPqtw9pP9PxBswmjqhEKt6
3Ck/ADyCLZdGREp/A68XVGVvHb/JvfOg35vhDTnY5YS2yaSxtOlTrfweIjcpHNm/KYIfyfc8tE37
vQgFgsHKTN1WfK5wTNKf7aRiY0HC8102JHI+A45viX2RWjDbdLJq2Y7F5ppx0BUGXajkekHFHtTP
zGH4mWnc+ZM9cxpDbZHg9CWY03g1SIePCaPv+IQWravG0Y5/FjoT60o3H5FyFBudgMVZ3cp8VzJe
LvD1NXLx34aC55OogymYf2wimfHqDswutWmnj+tuNMEDOInqQNq9UcHM/OyxxtX8wTTT/NRUFeVm
VeKtfofxOPU4GgEr7q/dgpmmyUwpJdTmUIWgEo/EFBgHOpfX6wnVmKNZLK/35u6h5zONTzL/dQna
H6zFQ6I+cQKT5ug+al7l3k03OO7iBB2zXBSdPjOWpTtDodnsbHMw86WcpUsjoqFkiDJh0K9pAiTs
yu0YtLXYhpLRc8vLx+nlNPLnBlewheD6Rsel2vUITR+Y0R+LTIVcFizL3RkCWpgT8Mv7GFBus0bs
tXa7x74NoVvDOv16dK5Bp6co4kem5MjsBMqulNnb5qAiSRSAHjJVEcbgiN/ejphUzKhhnQ2rLlmR
J0srKz5SDkt9GoLIIQYs5LiQz7IybWCgpgj6AsAgzJv8o1wGzGOJFcuutKhU3byY8gX4mvT1mcoL
+oV0fltqMUZ5+7fYGYXRzx+IoKYTulFlekV7KaIy6pn9anlT85vVRhfq3tNZZRGuUALVSiHKp1Bv
hSH5jlo6taMLCDODPF39Tqvftq6OemOjXklUiPQyYpE3hA7qrG4TTmxYZzDSMPUrCpTcgg6vjYA+
icfYFMU1pgr4fLmYJ0fROfPHuGJh8j+aeRnjdDL1S9T5mRS4VQFv2nBpMet9lpa4++KbevKGFfwJ
BO0QF4h8xYmLMoxmJE4LfilYtw9dGxV5baelDnfq58HheZD2ds1QdE7sNtEpXV6y/daqe+F0IrwO
EggItvtulBViDAFHzzEs4Ors+9e3U7TiRkh+FQouUA4zwFshY6xGA6Dbnol3ZBzdaBUiUM72DESu
4f8i55WEiA1ksZPV3YoWd/4fFxoy40yp+YAThVsC3PUgYwIJd+HeGGy4QmzfwbeK+mDAR9fhkgPx
nzDL3LV2Gv3HmCCLPBRF3HWk89YHpBOvD6r+uOVfqkM48561HfV7l3A6apzVHxEOEh1IyTyiN4f6
3KVzCDqCvavPKeaSnkFs20XLbL+sYELy1lix4/B4BOvvSBa6muSI5EwkO9IYHRp4SldDU/BoT6Cf
qRS1nv1bScZ42MttKPlYo5C+D45g6wpNReoA61TtaIEPBZNYtLw4TsZyYTF8v5ZzdClRynhRzcCS
TDxMcqXxYDSNoJqUrB7zcYe4AU3uO+Tj6wXoA39LLbsKtK1EY16dK5eicLPwSoFRhW+yHzcF2R0r
WPJGyuHI7ddZdu81doAYgdtje29f2PoQ7UdSTUx5TaBtDIJ3Rj9hzUirGokvUqbl7/aQny41+3XL
F7yI+f+1hfB0KztcysNAoH/Ef6mEeMnfNIZ1MWfgKXi2mHySkygQ6NWZ6vvA1E4qyMJXH6Ff48/K
gOLCxf9q2hiWqZQnp6Xn75CfUcw3BVuhzDPyLdr0RuUnInmBo6zzYXmuhUgWD3UZOwbOLMbQde1E
4+ppigWbA6D8yjjDH5d///Ez3Ge5UANdGKtn5+zwt6sVz/UnNbLaIxHavGC/XYYHjVzK8UBa1goj
rRjxZYq+/vP9jTUVM/We05Tuu6Vhr8Xqgqbs4LxdLvSY5ZRtfkiZ4ZCcUX6PAd4EH3/mr2iiXXwk
MaHxtETB5c92jL0MYVhAngHcoQp4PXcVgMM53uyhUPz7f2ILQV2YDlsJucEYfDq13cpM0FlEQd0h
5mhrSC7d1cT9pzwN/S9h7Qh/HzA8ELwUmuPuJDo2/TpqVz3rFrdQd6zrjucPEC8bNXyMJ4KKbI8D
jSOb8qPFWrNmF54vmxSvOh/OuuWoD9f3nVoFgkV+u9aHOriGCvKVf9fo+9RKQjPtDXcFXUfhU3Cv
MzmWBqGndqHMPSFCJwZft7uzO4LOPPH0VfFoxWhRynQwCPBocMx6x0YUJV+M3EFU6Vu7E3kJrFsl
y1fn4yO53dC25b8g4zcCCiBPZyfjr/dEPpI56AfsYVso/JiXvsCGk4Q44hgxk7E2o05UqQCMycBS
ygQjxTdflOik9YO+XOKbMzwwOKB9IrJf7iEl2lQF2K+TkGRUH4+zgS1JhcVqHPMQR+DJxVpWfM0M
H47wPKt6giCxmkkimy+FeHTdZ6hz+24lzsFu3UbXHAwWbAtim+kz7tWoUwDCuWtRez90LMVibV03
s9OTE0S01WDnqkPCfv23N97xtDZeKpUclYjzfg8WN4IphB+xKA760It6EE+vAg6sslhPeEtILCY4
Uo32QdRhD4sEjjub54P8JzSNxRxNbgJXU+8ynehszPSEyuxl5dDi1AscV5lkhXQ99VE3kbMI8ilh
QVUy1qYXE9K5fiRAV0MgOjL6GGRYoTf4n43A3FTs90xm2IHT/tG6dfy45aY7VCkDyOLAsNg6qbjb
S+am1g2mbZSI1nM9RhmFc/sBTe78Kgm7HWfCi6EV9WsWjqKGa5AaRsASsm7bd1npnUKXCxM53zTI
77Gkmb968Gfj1eaXjJQdf892eoN9RwJPsCC18O81xXkHoHW9rpUzV/NkTfGJToNKY6n8O/U/gp3y
AG4NmQb+ohRjIbQrMorHExbrqsFGL4eC3yc69mOV+v1CTYsqda7U3Kustm/djGTSpFqDUaNUmNv7
s59H+WB4s7H0P4v0ac2cjyGb2JiekKYXjqytCQsMiVJwOtyNM7tOjPKEr5DFyVazHv2pRLOhaGVG
87WLyoRqDpuHLeZLjrkoa33bl1FYrCa3J6+jJ7/V3xNnIZQChJxZvKwYAjZaE4fMV2ZZJnThqFaV
jzThXMsUKhts7V+pxPK+9zyGMAfbJb+gqTodEbZFGJ3uAmuFe4/D7u5r4ULee1EtBh9bcw2j+Ola
cNtHZu9ufBxtKXSETdazieWpvDhS+w9bsCl/1kwyTaNvigZTEXWAX7zN8t/Lv3wG6d57wx/BxB+E
F8OAUdaEA/l/kXOG0XbxRG2wQEbzuLgDFSmrE62VEjJinXmf1q7lMpmlsJOGH0t6Vpx6OC8xz8e0
9F6q/ODk0dxRYn1TlLWz5oHLnk5CLNiWA8DqRrYx16q9uzU6zk/7a2dB6MGsTzhiIU00omSXkLY3
uhJSd6oKTQspc9w3uPCrB095lhsz+vGhD4iM4/CS2HsS0zXvKKDnVX6r6sYwhAYS1txJn8cHejTS
33a3FzrLh/Lr8tihbnmzdHQJtk+sq7tZb72rWrEbk48sbF9yJahsTCRqNmxxIiHoM81CkKoI+Lxh
cfc0D5Yp/MomiNvkLGAQL9gJNP3W0OyucO7MynZvbq3xjQW7UGuTkM+U7elqqbUSHoc+YvoRMbS0
Wra3OUa9vgiPvfWOPUXkCzQ+GZz5oh+zUdgV9KFSEg78gDsnyyeW/ilBD6TtAk9pe6QKH83lGlA/
2bWItSalCQk+8HJxYzEowKqYFGa6IaIc9tMb8mXj8fSJrYpmGSaaPDJJbiFsHkgzUgKFO56A6/eF
ldbJbZmhU48DLTEq3y10q679uNFxpRjMbj1VLTSaUJ5hhfLgA9jgL7ku8ypfmsyML/AFtmtYlAYS
x/hfNfqd/HxrFDj4suOVtrsEgFli/p8rQFuk8bUKKi+qMACYCmucfH6KPKuWAuxGCuqam7J+SLhy
F6DV5jjns6q2TiCqwQ/SFDGGwNWkiXwsljkpcugaJxrggWO350nMbF0QYxh1wDeVmRmPTvIktQeN
C2vym6ToRxoNYTF2Tp4Y99bkBeDapsuHhs2C3sEBcQs8X6JL4hEvCnkrhPhAFYDvUWiWd97v1xEF
JXyVXUJkVG9BXgkFfhxRC6VBtIUPWaRXjsqkEhgA4GfNh9Ato1kt2NsNy0Yk0TuxhhyZVCo9JfjN
xOUbhJqEzzlTH8+IdmNPKx43EGDT0Lrsk/UOaUPBvFWdb3GqIMg4TchPjXgWpuyR85DLNpqWKB3K
K2K8dzks0hfLCIP0o1ZrJyaV6vTRLX6GDJX6JZRDQIcYVYCtM38a642Um1FZz9czprkChHqQfL3B
NzQrdtyK7LIW3fUDo5pKTkFMk/BrlxVPsmRbDFKf4rxCbgZA+dTNUmlpBauC7VYTM5YFkM6wgAQf
kvhXW9lkApSLz8wKN03C6wRC66r8yh/YqKG+OjTUsFovJrTDokQK8MgWGIzpNPRCNORK91DK5GNY
HEXIaZzdLIwnRbeaVleFh1M2/3aFZkINsBeVqebQim1r/XodkwvYfRJymSowdoWJn6/gXjWYYZGh
nHpo+U87TYAoe/0bNSftOYIRvEYmlBQPHk/YuQ7Jdb5hXqiv8iaBtaRv3kWfgGc6JF0PyuLIJmQz
sePGBoxGEAi/gTPFAp5q7bYdVvVh+ebZ1KPCkgVP67PIAZMIBdM7ytHOVT5vyhBUSnzHGj7tsaK/
AqD6UoWrkSts4FsZnh9O4M8pkE8Vm26V8YWdgHnDnz87zqQ/CBdX9Nf6pLsk7Gm/k4IQqgnaYV3Q
djGKNtk3QKG8x7u/AfFVjfC3uxos9Lej1HjxSt7yMGU5UStm3a89d3ADmdllSmHXG8oaJwgC5yD+
6ZyoV+S6O/inHAAITWTqNss+CZq3wQ2fSPRm3iMIYujSFh49ZWF6Y5hhATGZ7puV05IkX1gc8Ela
qcxST2cD5iqJ2QwgOpu3pXIdq8sop2UlJ2ii2/Ct6PF84r15S+LX3gLwJ/KnCGF+GUwOWmRkx3Hu
v4EWljx5OFiNNQjpL6/VF8J8mZgV0Yatyn1p4Zb53UROPaTcM7aRopMguRKwhgpbxYt/+eTJW6XO
DU2onCq+kdiW47TN2oEGrRxvPPPOq8/oSOfJtP28+4j2QIWKpNEEkyM1waSHRIK9ySAFcsxROSmZ
y5VUaZHpge4mjt4o3wek/wS6MwWVPMsAu3hEPxAU1KQr/u9URt3MMa2fLlo4iYegrEEYe2yLrrAN
jfOlfFl2WAfnBn0q9dqaZPhtJGkjLcv87aMFcrI8E5sRxgPWXNHe5E3yM7fFaxtQ9czAwy5HBQ7T
gJgBJSPfEfU8e3x0JPGyrdeTDJ3A7ttFutTZr1mNDvkDS1bKipmWU7JPSOW9iMIXgy8z3KaMV17o
y3aq0spIkFtfHwEMlx5tdEz8T/iwPwSqX7cnQdq/VsqDUNNb4SVzr+cYcHaGI1VbX/0HzDuMomQP
8bBDfD6NPr3YWlufkhrsbQfYW7WwfFtn5mraBA8+uYpAnFvNL1nN6ushsbMR1N+vSXjcYN5NACl/
H2124SzQrgKMKsLqQRU44LOU1vbHbBKDecnaquvebNH7p2feemLLqYcfbhQerM8RTzfGlW92BjUa
pGu7s0UvPCSvVvGLI6kKWChXl/Ug0dnDJutwDJbPGIIKIcK+2NPBDWx7NvZcgk1vLArNWzWWN5i0
Z8dDhZ6CzgsX9JZYvHPLyXwjLrgSDXp6EkJ3xaVltlxsSPjIWuSJ5UR2t3a5j70+y53DA5hawRIJ
BflpJHyKmzPzoIY+XozhC5geLbq+MLSTkXTA+Md2N7j1po0WdpbtlNFxKyHKeOmAG5tXoFNxuonX
NfKY106GmQh1ErXt/sv1FnwsfMlB1zi1P2UI7BNRKZFKqOrCBbJHJCnZXGXx5HE1jHd9qZY8pcf/
raU+1iunjRWFwqi0m4Q/8gbHQTiFqXI0Vta3iD7PfOvOLzc9cuejpa4JY/ddtS3kX2TIpZRySbii
XgeFxsoRZG/o05PSNLi9egYTmlUgVS8d+uK+3hIvzh7l7GM7KBHA/q9Nsn2MXkbuM26NH3qxiAea
Dn32PsY77N/kRaam/N0h1Zw1y+Yze0k6Xo7SvXAa3PeIHINvxYjsqA0DUbJAr2qJQ9ez9vPSqTOB
Dhbd/08MfHVAhXHpF3fM+00YOk9kcYkG9Ri/eeixt2oEDZaKzJLnnoqvFxeWkGjVuZfdk5dOu9v7
ExEKEHZo+ZvJiEXLjjzmDtZFould5AIW+q3ME1xdRFAo48yScl3GdhltW7oIIwCbxONHp6pPH1DB
UKn3Dh2Z6TWDBMdTMe2/L9TS7lojLF/dKkQy/l5IxcOXSsyxUWAVpL5ZrB9DtijZUUpLiHlAFei9
Y9Z+k80OmqZhY2yO5s8R0ALs1Ft48o5GjKhCgHF72iPb/y0d1jf95FfmUoxwezzrhskMaOCfFgg8
AphxbFX/k+52qiLuQkjtJScwGnNfZDEzWfMjSThKXVI/arwQ7Tn55JqubDkyP18b3uYJ3czC/KiX
yv+ED9+8d35HV+DzUtygwZY7rrisICcU3NFk7cc8i1jdolvkOva04x34YiSWT+zjbKj39iDgMJfP
nq1M1Ah0h3m9u3TgvvOjbzfU5dUNe5/RyIdK0LTLLKGFZO1jZL2P6ntEgfg507gCdVHVavN3mTHX
IPwxe6Y6aJ52LnrwSvqTlTplUK3PXqyywVm3ukSQ8najZI5ITtibqu8sJzJxPESP1h/CGEy2irf0
tKuFjzq4iUmlE08KwGR6AdQ90uUyDZ7BInDpap0TUFE2yqj+Cmg/RLdONz44miMbIJ+DAxSUi2MS
CVoaEGRDgZX7L+1GCwlSyMt9OauSexn2E56pMGI/A/PNjcGrIdxkutQoK2YRlg7i6f+wNb9Y2gcM
YzNWLYz5uyo3rNjHRcKm7HEbiWcCdoOlOc1k1c55wLySin4bgMGuA9UXa2pj15QXYNFMeJbtfhwm
ar4+eZn5WyZ6Q7DhbN8CKPpHO9TyDPvVgQmrAQcWSBAx1hC6wirnvf7ATJlrz+DmfHI9E026mId6
KH40lG9jMqfrWu7g7s8wz6nIBiamEhcd5objUHUEmMKbsASQjGVhZA6QbCbgAukMJWUtjQs3kGXc
FgiOMoJpGeYNPE8MJgGTMl4eB3OVuQh36cD5wqXzYC8GP17NZ/0WINIk6TBXOsOpv1WCDSwhzshP
zuOsK8lBIWHJFZMEZp1ygQP/cGs0RyCqkD8ulUBTV+K+EZcy6DXjw67oee/ALKZrhgkjW/cAGZxd
eGZowjoQwZjMCPMMu4WX0cMnUwzIo4hU1IQi+ktIpNRZkliY3/li31LBpNye1mMA1I1p7/jq9Rb+
No3LbhHCont+fMEy734+6OiLsjBXts+/ro+qRqYFtjyT+k0RFo619T77Yp2untdxkjuR6be0s93j
vPwKi2VrjYaTCJbKSM0oj0YtWmM4nSWlNLkS2h2rjbGdujgcDPlU8I44Bo2G1oMGiCui9FodkZtG
kOBqtjbv1R/z+321jpGACzq25FPJUSd1xst7U+0GLp/EzuEpptq4ISk5nnvG8OpY7afVlV5aPFsj
MBQKt8uSzd/dHgxVjmPeqp1cV0WABPcaLzC/ehxbi04Q
`protect end_protected
|
----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 14:48:55 05/24/2011
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reader is
port (
nrst : in std_logic;
clk108 : in std_logic;
input_red : in std_logic;
input_green : in std_logic;
input_blue : in std_logic;
is_reading_active : in std_logic;
time_resolution : in integer range 0 to 15;
-- This is an asynchronous output. It indicates that during next
-- clock cycle entity will generate flush_and_return_to_zero.
overflow_indicator : out std_logic;
screen_segment : out natural range 0 to 13;
screen_column : out natural range 0 to 1279;
flush_and_return_to_zero : out std_logic;
write_enable : out std_logic;
red_value : out std_logic;
green_value : out std_logic;
blue_value : out std_logic
);
constant max_time_resolution : natural := 432000;
type res_array is array (0 to 15) of natural range 2 to max_time_resolution;
-- Real time resolution will be given by equation:
-- time_between_probes = time_resolutions (time_resolution) / (108 Mhz)
-- No 1 (ones) here please!
constant time_resolutions : res_array := (
2, 5, 10, 20, 108, 216, 432, 1080, 2160, 4320,
10800, 21600, 43200, 108000, 216000, 432000
);
end reader;
architecture behavioral of reader is
signal time_position : natural range 0 to max_time_resolution + 1 := 0;
signal next_time_position : natural range 0 to max_time_resolution + 1;
signal time_overflow : std_logic;
signal memory_position : natural range 0 to (14 * 1280) := 0;
signal next_memory_position : natural range 0 to (14 * 1280);
signal internal_screen_segment : natural range 0 to 13:= 0;
signal internal_screen_column : natural range 0 to 1279 := 0;
signal next_screen_segment : natural range 0 to 14;
signal next_screen_column : natural range 0 to 1280;
signal internal_overflow_indicator : std_logic;
begin
overflow_indicator <= internal_overflow_indicator;
screen_segment <= internal_screen_segment;
screen_column <= internal_screen_column;
-- Process computes next_time_position and time_overflow
process (time_position) is
begin
if time_position + 1 >= time_resolutions (time_resolution) then
next_time_position <= 0;
time_overflow <= '1';
else
next_time_position <= time_position + 1;
time_overflow <= '0';
end if;
end process;
-- Process computes next_memory_position and internal_overflow_indicator
process (memory_position, internal_screen_segment, internal_screen_column, time_overflow) is
begin
if time_overflow = '1' then
if memory_position + 1 >= (14 * 1280) then
next_memory_position <= 0;
next_screen_segment <= 0;
next_screen_column <= 0;
internal_overflow_indicator <= '1';
else
next_memory_position <= memory_position + 1;
if internal_screen_column + 1 >= 1280 then
next_screen_column <= 0;
next_screen_segment <= internal_screen_segment + 1;
else
next_screen_column <= internal_screen_column + 1;
next_screen_segment <= internal_screen_segment;
end if;
internal_overflow_indicator <= '0';
end if;
else
next_memory_position <= memory_position;
next_screen_column <= internal_screen_column;
next_screen_segment <= internal_screen_segment;
internal_overflow_indicator <= '0';
end if;
end process;
process (nrst, clk108) is
begin
if nrst = '0' then
time_position <= 0;
memory_position <= 0;
flush_and_return_to_zero <= '0';
write_enable <= '0';
red_value <= '0';
green_value <= '0';
blue_value <= '0';
elsif rising_edge (clk108) then
memory_position <= next_memory_position;
internal_screen_column <= next_screen_column;
internal_screen_segment <= next_screen_segment;
if is_reading_active = '1' or time_position /= 0 then
time_position <= next_time_position;
if time_overflow = '1' then
red_value <= input_red;
green_value <= input_green;
blue_value <= input_blue;
write_enable <= '1';
flush_and_return_to_zero <= internal_overflow_indicator;
else
red_value <= '0';
green_value <= '0';
blue_value <= '0';
write_enable <= '0';
flush_and_return_to_zero <= '0';
end if;
else
red_value <= '0';
green_value <= '0';
blue_value <= '0';
write_enable <= '0';
flush_and_return_to_zero <= '0';
end if;
end if;
end process;
end behavioral;
|
component Computer_System is
port (
adc_sclk : out std_logic; -- sclk
adc_cs_n : out std_logic; -- cs_n
adc_dout : in std_logic := 'X'; -- dout
adc_din : out std_logic; -- din
audio_ADCDAT : in std_logic := 'X'; -- ADCDAT
audio_ADCLRCK : in std_logic := 'X'; -- ADCLRCK
audio_BCLK : in std_logic := 'X'; -- BCLK
audio_DACDAT : out std_logic; -- DACDAT
audio_DACLRCK : in std_logic := 'X'; -- DACLRCK
audio_clk_clk : out std_logic; -- clk
audio_pll_ref_clk_clk : in std_logic := 'X'; -- clk
audio_pll_ref_reset_reset : in std_logic := 'X'; -- reset
av_config_SDAT : inout std_logic := 'X'; -- SDAT
av_config_SCLK : out std_logic; -- SCLK
expansion_jp1_export : inout std_logic_vector(31 downto 0) := (others => 'X'); -- export
expansion_jp2_export : inout std_logic_vector(31 downto 0) := (others => 'X'); -- export
hex3_hex0_export : out std_logic_vector(31 downto 0); -- export
hex5_hex4_export : out std_logic_vector(15 downto 0); -- export
hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_io_hps_io_qspi_inst_IO0 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO0
hps_io_hps_io_qspi_inst_IO1 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO1
hps_io_hps_io_qspi_inst_IO2 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO2
hps_io_hps_io_qspi_inst_IO3 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO3
hps_io_hps_io_qspi_inst_SS0 : out std_logic; -- hps_io_qspi_inst_SS0
hps_io_hps_io_qspi_inst_CLK : out std_logic; -- hps_io_qspi_inst_CLK
hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK
hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI
hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO
hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0
hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA
hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL
hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09
hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35
hps_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO40
hps_io_hps_io_gpio_inst_GPIO41 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO41
hps_io_hps_io_gpio_inst_GPIO48 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO48
hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54
hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61
irda_TXD : out std_logic; -- TXD
irda_RXD : in std_logic := 'X'; -- RXD
leds_export : out std_logic_vector(9 downto 0); -- export
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
ps2_port_CLK : inout std_logic := 'X'; -- CLK
ps2_port_DAT : inout std_logic := 'X'; -- DAT
ps2_port_dual_CLK : inout std_logic := 'X'; -- CLK
ps2_port_dual_DAT : inout std_logic := 'X'; -- DAT
pushbuttons_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
sdram_addr : out std_logic_vector(12 downto 0); -- addr
sdram_ba : out std_logic_vector(1 downto 0); -- ba
sdram_cas_n : out std_logic; -- cas_n
sdram_cke : out std_logic; -- cke
sdram_cs_n : out std_logic; -- cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
sdram_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_ras_n : out std_logic; -- ras_n
sdram_we_n : out std_logic; -- we_n
sdram_clk_clk : out std_logic; -- clk
slider_switches_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export
system_pll_ref_clk_clk : in std_logic := 'X'; -- clk
system_pll_ref_reset_reset : in std_logic := 'X'; -- reset
vga_CLK : out std_logic; -- CLK
vga_HS : out std_logic; -- HS
vga_VS : out std_logic; -- VS
vga_BLANK : out std_logic; -- BLANK
vga_SYNC : out std_logic; -- SYNC
vga_R : out std_logic_vector(7 downto 0); -- R
vga_G : out std_logic_vector(7 downto 0); -- G
vga_B : out std_logic_vector(7 downto 0); -- B
vga_pll_ref_clk_clk : in std_logic := 'X'; -- clk
vga_pll_ref_reset_reset : in std_logic := 'X'; -- reset
video_in_TD_CLK27 : in std_logic := 'X'; -- TD_CLK27
video_in_TD_DATA : in std_logic_vector(7 downto 0) := (others => 'X'); -- TD_DATA
video_in_TD_HS : in std_logic := 'X'; -- TD_HS
video_in_TD_VS : in std_logic := 'X'; -- TD_VS
video_in_clk27_reset : in std_logic := 'X'; -- clk27_reset
video_in_TD_RESET : out std_logic; -- TD_RESET
video_in_overflow_flag : out std_logic -- overflow_flag
);
end component Computer_System;
u0 : component Computer_System
port map (
adc_sclk => CONNECTED_TO_adc_sclk, -- adc.sclk
adc_cs_n => CONNECTED_TO_adc_cs_n, -- .cs_n
adc_dout => CONNECTED_TO_adc_dout, -- .dout
adc_din => CONNECTED_TO_adc_din, -- .din
audio_ADCDAT => CONNECTED_TO_audio_ADCDAT, -- audio.ADCDAT
audio_ADCLRCK => CONNECTED_TO_audio_ADCLRCK, -- .ADCLRCK
audio_BCLK => CONNECTED_TO_audio_BCLK, -- .BCLK
audio_DACDAT => CONNECTED_TO_audio_DACDAT, -- .DACDAT
audio_DACLRCK => CONNECTED_TO_audio_DACLRCK, -- .DACLRCK
audio_clk_clk => CONNECTED_TO_audio_clk_clk, -- audio_clk.clk
audio_pll_ref_clk_clk => CONNECTED_TO_audio_pll_ref_clk_clk, -- audio_pll_ref_clk.clk
audio_pll_ref_reset_reset => CONNECTED_TO_audio_pll_ref_reset_reset, -- audio_pll_ref_reset.reset
av_config_SDAT => CONNECTED_TO_av_config_SDAT, -- av_config.SDAT
av_config_SCLK => CONNECTED_TO_av_config_SCLK, -- .SCLK
expansion_jp1_export => CONNECTED_TO_expansion_jp1_export, -- expansion_jp1.export
expansion_jp2_export => CONNECTED_TO_expansion_jp2_export, -- expansion_jp2.export
hex3_hex0_export => CONNECTED_TO_hex3_hex0_export, -- hex3_hex0.export
hex5_hex4_export => CONNECTED_TO_hex5_hex4_export, -- hex5_hex4.export
hps_io_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CLK, -- hps_io.hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
hps_io_hps_io_qspi_inst_IO0 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO0, -- .hps_io_qspi_inst_IO0
hps_io_hps_io_qspi_inst_IO1 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO1, -- .hps_io_qspi_inst_IO1
hps_io_hps_io_qspi_inst_IO2 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO2, -- .hps_io_qspi_inst_IO2
hps_io_hps_io_qspi_inst_IO3 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO3, -- .hps_io_qspi_inst_IO3
hps_io_hps_io_qspi_inst_SS0 => CONNECTED_TO_hps_io_hps_io_qspi_inst_SS0, -- .hps_io_qspi_inst_SS0
hps_io_hps_io_qspi_inst_CLK => CONNECTED_TO_hps_io_hps_io_qspi_inst_CLK, -- .hps_io_qspi_inst_CLK
hps_io_hps_io_sdio_inst_CMD => CONNECTED_TO_hps_io_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK => CONNECTED_TO_hps_io_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK => CONNECTED_TO_hps_io_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP => CONNECTED_TO_hps_io_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR => CONNECTED_TO_hps_io_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT => CONNECTED_TO_hps_io_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
hps_io_hps_io_spim1_inst_CLK => CONNECTED_TO_hps_io_hps_io_spim1_inst_CLK, -- .hps_io_spim1_inst_CLK
hps_io_hps_io_spim1_inst_MOSI => CONNECTED_TO_hps_io_hps_io_spim1_inst_MOSI, -- .hps_io_spim1_inst_MOSI
hps_io_hps_io_spim1_inst_MISO => CONNECTED_TO_hps_io_hps_io_spim1_inst_MISO, -- .hps_io_spim1_inst_MISO
hps_io_hps_io_spim1_inst_SS0 => CONNECTED_TO_hps_io_hps_io_spim1_inst_SS0, -- .hps_io_spim1_inst_SS0
hps_io_hps_io_uart0_inst_RX => CONNECTED_TO_hps_io_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX => CONNECTED_TO_hps_io_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
hps_io_hps_io_i2c0_inst_SDA => CONNECTED_TO_hps_io_hps_io_i2c0_inst_SDA, -- .hps_io_i2c0_inst_SDA
hps_io_hps_io_i2c0_inst_SCL => CONNECTED_TO_hps_io_hps_io_i2c0_inst_SCL, -- .hps_io_i2c0_inst_SCL
hps_io_hps_io_i2c1_inst_SDA => CONNECTED_TO_hps_io_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
hps_io_hps_io_i2c1_inst_SCL => CONNECTED_TO_hps_io_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
hps_io_hps_io_gpio_inst_GPIO09 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO09, -- .hps_io_gpio_inst_GPIO09
hps_io_hps_io_gpio_inst_GPIO35 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO35, -- .hps_io_gpio_inst_GPIO35
hps_io_hps_io_gpio_inst_GPIO40 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO40, -- .hps_io_gpio_inst_GPIO40
hps_io_hps_io_gpio_inst_GPIO41 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO41, -- .hps_io_gpio_inst_GPIO41
hps_io_hps_io_gpio_inst_GPIO48 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO48, -- .hps_io_gpio_inst_GPIO48
hps_io_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO53, -- .hps_io_gpio_inst_GPIO53
hps_io_hps_io_gpio_inst_GPIO54 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO54, -- .hps_io_gpio_inst_GPIO54
hps_io_hps_io_gpio_inst_GPIO61 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO61, -- .hps_io_gpio_inst_GPIO61
irda_TXD => CONNECTED_TO_irda_TXD, -- irda.TXD
irda_RXD => CONNECTED_TO_irda_RXD, -- .RXD
leds_export => CONNECTED_TO_leds_export, -- leds.export
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
ps2_port_CLK => CONNECTED_TO_ps2_port_CLK, -- ps2_port.CLK
ps2_port_DAT => CONNECTED_TO_ps2_port_DAT, -- .DAT
ps2_port_dual_CLK => CONNECTED_TO_ps2_port_dual_CLK, -- ps2_port_dual.CLK
ps2_port_dual_DAT => CONNECTED_TO_ps2_port_dual_DAT, -- .DAT
pushbuttons_export => CONNECTED_TO_pushbuttons_export, -- pushbuttons.export
sdram_addr => CONNECTED_TO_sdram_addr, -- sdram.addr
sdram_ba => CONNECTED_TO_sdram_ba, -- .ba
sdram_cas_n => CONNECTED_TO_sdram_cas_n, -- .cas_n
sdram_cke => CONNECTED_TO_sdram_cke, -- .cke
sdram_cs_n => CONNECTED_TO_sdram_cs_n, -- .cs_n
sdram_dq => CONNECTED_TO_sdram_dq, -- .dq
sdram_dqm => CONNECTED_TO_sdram_dqm, -- .dqm
sdram_ras_n => CONNECTED_TO_sdram_ras_n, -- .ras_n
sdram_we_n => CONNECTED_TO_sdram_we_n, -- .we_n
sdram_clk_clk => CONNECTED_TO_sdram_clk_clk, -- sdram_clk.clk
slider_switches_export => CONNECTED_TO_slider_switches_export, -- slider_switches.export
system_pll_ref_clk_clk => CONNECTED_TO_system_pll_ref_clk_clk, -- system_pll_ref_clk.clk
system_pll_ref_reset_reset => CONNECTED_TO_system_pll_ref_reset_reset, -- system_pll_ref_reset.reset
vga_CLK => CONNECTED_TO_vga_CLK, -- vga.CLK
vga_HS => CONNECTED_TO_vga_HS, -- .HS
vga_VS => CONNECTED_TO_vga_VS, -- .VS
vga_BLANK => CONNECTED_TO_vga_BLANK, -- .BLANK
vga_SYNC => CONNECTED_TO_vga_SYNC, -- .SYNC
vga_R => CONNECTED_TO_vga_R, -- .R
vga_G => CONNECTED_TO_vga_G, -- .G
vga_B => CONNECTED_TO_vga_B, -- .B
vga_pll_ref_clk_clk => CONNECTED_TO_vga_pll_ref_clk_clk, -- vga_pll_ref_clk.clk
vga_pll_ref_reset_reset => CONNECTED_TO_vga_pll_ref_reset_reset, -- vga_pll_ref_reset.reset
video_in_TD_CLK27 => CONNECTED_TO_video_in_TD_CLK27, -- video_in.TD_CLK27
video_in_TD_DATA => CONNECTED_TO_video_in_TD_DATA, -- .TD_DATA
video_in_TD_HS => CONNECTED_TO_video_in_TD_HS, -- .TD_HS
video_in_TD_VS => CONNECTED_TO_video_in_TD_VS, -- .TD_VS
video_in_clk27_reset => CONNECTED_TO_video_in_clk27_reset, -- .clk27_reset
video_in_TD_RESET => CONNECTED_TO_video_in_TD_RESET, -- .TD_RESET
video_in_overflow_flag => CONNECTED_TO_video_in_overflow_flag -- .overflow_flag
);
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Tue Mar 29 14:16:28 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/SKL/Desktop/ECE532/quadencoder/encoder_ip_prj2/encoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_16kb/dcfifo_32in_32out_16kb_stub.vhdl
-- Design : dcfifo_32in_32out_16kb
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dcfifo_32in_32out_16kb is
Port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
wr_data_count : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end dcfifo_32in_32out_16kb;
architecture stub of dcfifo_32in_32out_16kb is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty,wr_data_count[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v12_0,Vivado 2015.1";
begin
end;
|
-------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Sbox_registers is
port(
Clk : in std_logic; -- Clock
Shift0In : in std_logic_vector(15 downto 0);
Shift1In : in std_logic_vector(15 downto 0);
Shift2In : in std_logic_vector(15 downto 0);
Shift3In : in std_logic_vector(15 downto 0);
Shift4In : in std_logic_vector(15 downto 0);
Shift0Out : out std_logic_vector(15 downto 0);
Shift1Out : out std_logic_vector(15 downto 0);
Shift2Out : out std_logic_vector(15 downto 0);
Shift3Out : out std_logic_vector(15 downto 0);
Shift4Out : out std_logic_vector(15 downto 0);
load0in : in std_logic_vector(63 downto 0);
load1in : in std_logic_vector(63 downto 0);
load2in : in std_logic_vector(63 downto 0);
load3in : in std_logic_vector(63 downto 0);
load4in : in std_logic_vector(63 downto 0);
load0out : out std_logic_vector(63 downto 0);
load1out : out std_logic_vector(63 downto 0);
load2out : out std_logic_vector(63 downto 0);
load3out : out std_logic_vector(63 downto 0);
load4out : out std_logic_vector(63 downto 0);
Sel : in std_logic_vector(1 downto 0);
ShiftEnable : in std_logic;
Reg0En : in std_logic;
Reg1En : in std_logic;
Reg2En : in std_logic;
Reg3En : in std_logic;
Reg4En : in std_logic
);
end entity Sbox_registers;
architecture structural of Sbox_registers is
signal Part0_0, Part0_1, Part0_2, Part0_3 : std_logic_vector(15 downto 0);
signal Part1_0, Part1_1, Part1_2, Part1_3 : std_logic_vector(15 downto 0);
signal Part2_0, Part2_1, Part2_2, Part2_3 : std_logic_vector(15 downto 0);
signal Part3_0, Part3_1, Part3_2, Part3_3 : std_logic_vector(15 downto 0);
signal Part4_0, Part4_1, Part4_2, Part4_3 : std_logic_vector(15 downto 0);
begin
----------------------------------
------ Combinatorial logic ------
----------------------------------
datapath: process(Part0_0, Part0_1, Part0_2, Part0_3, Part1_0, Part1_1, Part1_2, Part1_3, Part2_0, Part2_1, Part2_2, Part2_3,
Part3_0, Part3_1, Part3_2, Part3_3, Part4_0, Part4_1, Part4_2, Part4_3, Sel) is
begin
load0out <= Part0_0 & Part0_1 & Part0_2 & Part0_3;
load1out <= Part1_0 & Part1_1 & Part1_2 & Part1_3;
load2out <= Part2_0 & Part2_1 & Part2_2 & Part2_3;
load3out <= Part3_0 & Part3_1 & Part3_2 & Part3_3;
load4out <= Part4_0 & Part4_1 & Part4_2 & Part4_3;
if Sel = "00" then
Shift0Out <= Part0_0;
Shift1Out <= Part1_0;
Shift2Out <= Part2_0;
Shift3Out <= Part3_0;
Shift4Out <= Part4_0;
elsif Sel = "01" then
Shift0Out <= Part0_1;
Shift1Out <= Part1_1;
Shift2Out <= Part2_1;
Shift3Out <= Part3_1;
Shift4Out <= Part4_1;
elsif Sel = "10" then
Shift0Out <= Part0_2;
Shift1Out <= Part1_2;
Shift2Out <= Part2_2;
Shift3Out <= Part3_2;
Shift4Out <= Part4_2;
else
Shift0Out <= Part0_3;
Shift1Out <= Part1_3;
Shift2Out <= Part2_3;
Shift3Out <= Part3_3;
Shift4Out <= Part4_3;
end if;
end process datapath;
---------------------------------------------
------ The registers in the datapath --------
---------------------------------------------
registerdatapath : process(Clk) is
begin
if(Clk = '1' and Clk'event) then
if ShiftEnable = '1' then
if Sel = "00" then
Part0_0 <= Shift0In;
Part1_0 <= Shift1In;
Part2_0 <= Shift2In;
Part3_0 <= Shift3In;
Part4_0 <= Shift4In;
elsif Sel = "01" then
Part0_1 <= Shift0In;
Part1_1 <= Shift1In;
Part2_1 <= Shift2In;
Part3_1 <= Shift3In;
Part4_1 <= Shift4In;
elsif Sel = "10" then
Part0_2 <= Shift0In;
Part1_2 <= Shift1In;
Part2_2 <= Shift2In;
Part3_2 <= Shift3In;
Part4_2 <= Shift4In;
elsif Sel = "11" then
Part0_3 <= Shift0In;
Part1_3 <= Shift1In;
Part2_3 <= Shift2In;
Part3_3 <= Shift3In;
Part4_3 <= Shift4In;
end if;
else
if Reg0En = '1' then
Part0_0 <= load0in(63 downto 48);
Part0_1 <= load0in(47 downto 32);
Part0_2 <= load0in(31 downto 16);
Part0_3 <= load0in(15 downto 0);
end if;
if Reg1En = '1' then
Part1_0 <= load1in(63 downto 48);
Part1_1 <= load1in(47 downto 32);
Part1_2 <= load1in(31 downto 16);
Part1_3 <= load1in(15 downto 0);
end if;
if Reg2En = '1' then
Part2_0 <= load2in(63 downto 48);
Part2_1 <= load2in(47 downto 32);
Part2_2 <= load2in(31 downto 16);
Part2_3 <= load2in(15 downto 0);
end if;
if Reg3En = '1' then
Part3_0 <= load3in(63 downto 48);
Part3_1 <= load3in(47 downto 32);
Part3_2 <= load3in(31 downto 16);
Part3_3 <= load3in(15 downto 0);
end if;
if Reg4En = '1' then
Part4_0 <= load4in(63 downto 48);
Part4_1 <= load4in(47 downto 32);
Part4_2 <= load4in(31 downto 16);
Part4_3 <= load4in(15 downto 0);
end if;
end if;
end if;
end process registerdatapath;
end architecture structural;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 27 19:26:50 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_stub.vhdl
-- Design : system_inverter_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_inverter_0_0 is
Port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end system_inverter_0_0;
architecture stub of system_inverter_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "x,x_not";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "inverter,Vivado 2016.4";
begin
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2087.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02087ent IS
END c07s02b04x00p20n01i02087ent;
ARCHITECTURE c07s02b04x00p20n01i02087arch OF c07s02b04x00p20n01i02087ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_4 is boolean_v (1 to 4);
SUBTYPE boolean_8 is boolean_v (1 to 8);
BEGIN
TESTING: PROCESS
variable result : boolean_8;
variable l_operand : boolean_4 := (true,false,true,false);
variable r_operand : boolean_4 := (false,false,true,true);
BEGIN
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = (true,false,true,false,false,false,true,true)) and (result(1) = true))
report "***PASSED TEST: c07s02b04x00p20n01i02087"
severity NOTE;
assert ((result = (true,false,true,false,false,false,true,true)) and (result(1) = true))
report "***FAILED TEST: c07s02b04x00p20n01i02087 - Concatenation of two BOOLEAN arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02087arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2087.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02087ent IS
END c07s02b04x00p20n01i02087ent;
ARCHITECTURE c07s02b04x00p20n01i02087arch OF c07s02b04x00p20n01i02087ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_4 is boolean_v (1 to 4);
SUBTYPE boolean_8 is boolean_v (1 to 8);
BEGIN
TESTING: PROCESS
variable result : boolean_8;
variable l_operand : boolean_4 := (true,false,true,false);
variable r_operand : boolean_4 := (false,false,true,true);
BEGIN
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = (true,false,true,false,false,false,true,true)) and (result(1) = true))
report "***PASSED TEST: c07s02b04x00p20n01i02087"
severity NOTE;
assert ((result = (true,false,true,false,false,false,true,true)) and (result(1) = true))
report "***FAILED TEST: c07s02b04x00p20n01i02087 - Concatenation of two BOOLEAN arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02087arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2087.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02087ent IS
END c07s02b04x00p20n01i02087ent;
ARCHITECTURE c07s02b04x00p20n01i02087arch OF c07s02b04x00p20n01i02087ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_4 is boolean_v (1 to 4);
SUBTYPE boolean_8 is boolean_v (1 to 8);
BEGIN
TESTING: PROCESS
variable result : boolean_8;
variable l_operand : boolean_4 := (true,false,true,false);
variable r_operand : boolean_4 := (false,false,true,true);
BEGIN
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = (true,false,true,false,false,false,true,true)) and (result(1) = true))
report "***PASSED TEST: c07s02b04x00p20n01i02087"
severity NOTE;
assert ((result = (true,false,true,false,false,false,true,true)) and (result(1) = true))
report "***FAILED TEST: c07s02b04x00p20n01i02087 - Concatenation of two BOOLEAN arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02087arch;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 02:35:48 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zybo_zynq_design_auto_pc_0_stub.vhdl
-- Design : zybo_zynq_design_auto_pc_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2";
begin
end;
|
-- fast_Oscillator.vhd
--************************************
-- Program to simulate fast oscillator
--************************************
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
entity fast_oscillator is
port (
stop : in std_logic;
fast_clk : out std_logic:='0'
);
end entity;
architecture behave of fast_oscillator is
signal clk: std_logic:='0';
begin
process(clk,Stop)
begin
if Stop = '1' then
clk <= not clk after 99 pS;
elsif stop = '0' then
clk <= '0';
end if;
end process;
fast_clk <= clk;
end behave; |
------------------------------------------------------------------------------
-- File name: ee560_debounce_DPB_SCEN_CCEN_MCEN.vhd
-- Date: 6/10/2009
-- (C) Copyright 2009 Gandhi Puvvada
-- Description:
-- A vhdl design for debouncing a Push Button (PB) and produce the following:
-- (1) a debounced pulse DPB (DPB = debounced PB)
-- (2) a single clock-enable pulse, SCEN, after 0.084 sec, for single-stepping user design using a push button,
-- (3) a contunuous clock-enable pulse, CCEN, after another 0.16 sec., for running at full-speed
-- (4) a sequence of (multiple of) clock-enable pulses, MCEN, after every 0.084 sec after the 0.16 sec, for multi-stepping
--
-- Once 'PB' is pressed, after the initial bouncing finishes in the WQ (wait quarter second (actaully 0.084 sec)) state, the DPB is activated,
-- and all three pulses (SCEN, CCEN, and MCEN) are produced just for *one clock* in SCEN_state.
-- Then, after waiting another half second in the WH (wait half second) (actaully 0.168 sec)) state, the MCEN goes active for 1 clock every
-- quarter second and the CCEN goes active continuously. in MCEN_state. Finally, if the PB is released, we wait in WFCR
-- (Wait for a complete release) state for a quarter second and return to the INI state. Please see the state diagram or
-- read the code to understand the exact behavior.
-- The additional half-second (actually 0.168 sec) waiting after producing the first single-clock wide pulse allows the user
-- to release the button in time to avoid multi-stepping or running at full-speed even if he/she has used MCEN or CCEN
-- in his/her design.
-- To achieve the above and generate the outputs without asny glitches (though this is not necessary), let us use output coding.
-- In output coding the state memory bits are thoughtfully chosen in order to form the needed outputs.
-- In this case DPB, SCEN, MCEN, and CCEN are thos outputs. However, the output combinations may repeat in different states.
-- So we need here two tie-breakers.
-- State State DPB SCEN MCEN CCEN Tie-Breaker1 Tie-Breaker0
-- initial INI 0 0 0 0 0 0
-- wait quarter WQ 0 0 0 0 0 1
-- SCEN_state SCEN_st 1 1 1 1 - -
-- wait half WH 1 0 0 0 0 0
-- MCEN_state MCEN_st 1 0 1 1 - -
-- CCEN_state CCEN_st 1 0 0 1 - -
-- Counter Clear CCR 1 0 0 0 0 1
-- WFCR_state WFCR 1 0 0 0 1 -
-- Timers (Counters to keep time): 2**19 clocks of 20ns = 2**20 of 10ns = approximately 10 milliseconds = accurately 10.48576 ms
-- So, instead of quarter second, let us wait for 2**22 clocks ( 0.084 sec.) and instead of half second,
-- let us wait for 2**23 clocks (0.168 seconds).
-- If we use a 24-bit counter, count(23 downto 0), and start it with 0, then the first time, count(22) goes high,
-- we know that the lower 22 bits (21:0) have gone through their 2**22 combinations. So count(22) is used as
-- the 0.084 sec timer and the count(23) is used as the 0.168 sec timer.
-- We will use a generic parameter called N_dc (dc for debounce count) in place of 23 (and N_dc-1 in place of 22),
-- so that N_dc can be made 4 during behavioral simulation to test this debouncing module.
-- As the names say, the SCEN, MCEN, and the CCEN are clock enables and are not clocks by themselves. If you use
-- SCEN (or MCEN) as a "clock" by itself, then you would be creating a lot of sckew as these outputs of the internal
-- state machine take ordinary routes and do not get to go on the special routes used for clock distribution.
-- However, when they are used as clock enables, the static timing analyzer checks timing of these signals with respect
-- to the main clock signal (50 MHz clock) properly. This results in a good timing design. Moreover, you can use different
-- clock enables in different parts of the control unit so that the system is single stepped in some critical areas and
-- multi-stepped or made to run at full speed. This will not be possible if you try to use both SCEN and MCEN as clocks
-- as you should not be using multiple clocks in a supposedly single-clock system.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ee560_debounce is
generic (N_dc: positive := 23);
port (CLK, RESETB_DEBOUNCE :in std_logic; -- CLK = 50 MHz
PB :in std_logic; -- push button
DPB, SCEN, MCEN, CCEN :out std_logic -- debounced PB, single_CEN, multi_CEN, continuous CEN
);
end ee560_debounce ;
-------------------------------------------------------------------------------
architecture debounce_RTL of ee560_debounce is
-- Note: The most common RTL coding in VHDL is to use symbolic names for states
-- and leave it to the synthesis tool to tie these symbolic names to encoded bit combinations.
-- Designers define a suitable enumerated state type as shown below.
-- type debounce_state_type is (INI, WQ, SCEN_St, WH, MCEN_St, CCEN_St, CCR, WFCR);
-- signal debounce_state: debounce_state_type;
-- However, in this design, we would like to use output coding and we want enforce state assignments.
-- Hence, we define constants bearing the symbolic state names and initialize them to the bit
-- combinations of our choice.
-- By default, the synthesis tool (with default XST option "auto" for FSM encoding) will extract the state machine and will perform
attribute fsm_encoding: string; -- Refer to XST user guide -- FSM encoding
signal debounce_state: std_logic_vector(5 downto 0); -- 6-bit combination
-- DPB SCEN MCEN CCEN TieB1 TieB0
constant INI: std_logic_vector(5 downto 0) := ('0' & '0' & '0' & '0' & '0' & '0');
constant WQ: std_logic_vector(5 downto 0) := ('0' & '0' & '0' & '0' & '0' & '1');
constant SCEN_st: std_logic_vector(5 downto 0) := ('1' & '1' & '1' & '1' & '0' & '0');
constant WH: std_logic_vector(5 downto 0) := ('1' & '0' & '0' & '0' & '0' & '0');
constant MCEN_St: std_logic_vector(5 downto 0) := ('1' & '0' & '1' & '1' & '0' & '0');
constant CCEN_St: std_logic_vector(5 downto 0) := ('1' & '0' & '0' & '1' & '0' & '0');
constant CCR: std_logic_vector(5 downto 0) := ('1' & '0' & '0' & '0' & '0' & '1');
constant WFCR: std_logic_vector(5 downto 0) := ('1' & '0' & '0' & '0' & '1' & '0');
attribute fsm_encoding of debounce_state: signal is "user";
-- The enumerated state type allows the display of state name in symbolic form (ASCII form) in the waveform which is easy to read.
-- So, to provide this convenience, let us define an enumerated state signal called d_state here, and later assign values to it.
type debounce_state_type is (INI_s, WQ_s, SCEN_St_s, WH_s, MCEN_St_s, CCEN_St_s, CCR_s, WFCR_s);
signal d_state: debounce_state_type;
signal debounce_count: std_logic_vector(N_dc downto 0);
-- signal DPB_int, SCEN_int, MCEN_int, CCEN_int: std_logic; -- internal signals
-- signal tie-breaker1, tie-breaker0: std_logic; -- internal signals
begin
-- concurrent signal assignment statements
(DPB, SCEN, MCEN, CCEN) <= debounce_state(5 downto 2); -- this is because of output coding
-- for the purpose of displaying in the waveform
d_state <= INI_s when (debounce_state = INI) else
WQ_s when (debounce_state = WQ) else
SCEN_St_s when (debounce_state = SCEN_St) else
WH_s when (debounce_state = WH) else
MCEN_St_s when (debounce_state = MCEN_St) else
CCEN_St_s when (debounce_state = CCEN_St) else
CCR_s when (debounce_state = CCR) else
WFCR_s; -- when (debounce_state = WFCR);
debounce: process (CLK, RESETB_DEBOUNCE)
begin
if (RESETB_DEBOUNCE = '0') then
debounce_count <= (others => 'X');
debounce_state <= INI;
elsif (CLK'event and CLK = '1') then
case debounce_state is
when INI =>
debounce_count <= (others => '0');
if (PB = '1') then
debounce_state <= WQ;
end if;
when WQ =>
debounce_count <= debounce_count + 1;
if (PB = '0') then
debounce_state <= INI;
elsif (debounce_count(N_dc-1) = '1') then
debounce_state <= SCEN_St;
end if;
when SCEN_St =>
debounce_count <= (others => '0');
debounce_state <= WH;
when WH =>
debounce_count <= debounce_count + 1;
if (PB = '0') then
debounce_state <= CCR;
elsif (debounce_count(N_dc) = '1') then
debounce_state <= MCEN_St;
end if;
when MCEN_St =>
debounce_count <= (others => '0');
debounce_state <= CCEN_St;
when CCEN_St =>
debounce_count <= debounce_count + 1;
if (PB = '0') then
debounce_state <= CCR;
elsif (debounce_count(N_dc-1) = '1') then
debounce_state <= MCEN_St;
end if;
when CCR =>
debounce_count <= (others => '0');
debounce_state <= WFCR;
when others => -- when WFCR =>
debounce_count <= debounce_count + 1;
if (PB = '1') then
debounce_state <= WH;
elsif (debounce_count(N_dc-1) = '1') then
debounce_state <= INI;
end if;
end case;
end if;
end process debounce;
----------------------------
end debounce_RTL ;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:34:29 12/23/2015
-- Design Name:
-- Module Name: multiplexer_4_to_1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity multiplexer_4_to_1 is
Port ( in1 : IN std_logic_vector(15 downto 0);
in2 : IN std_logic_vector(15 downto 0);
in3 : IN std_logic_vector(15 downto 0);
in4 : IN std_logic_vector(15 downto 0);
S : in STD_LOGIC_VECTOR(1 downto 0);
O : out std_logic_vector(15 downto 0));
end multiplexer_4_to_1;
architecture Behavioral of multiplexer_4_to_1 is
begin
process (in1, in2, in3, in4, S)
begin
case S is
when "00" => O <= in1;
when "01" => O <= in2;
when "10" => O <= in3;
when "11" => O <= in4;
when others => O <= "0000000000000000";
end case;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:34:29 12/23/2015
-- Design Name:
-- Module Name: multiplexer_4_to_1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity multiplexer_4_to_1 is
Port ( in1 : IN std_logic_vector(15 downto 0);
in2 : IN std_logic_vector(15 downto 0);
in3 : IN std_logic_vector(15 downto 0);
in4 : IN std_logic_vector(15 downto 0);
S : in STD_LOGIC_VECTOR(1 downto 0);
O : out std_logic_vector(15 downto 0));
end multiplexer_4_to_1;
architecture Behavioral of multiplexer_4_to_1 is
begin
process (in1, in2, in3, in4, S)
begin
case S is
when "00" => O <= in1;
when "01" => O <= in2;
when "10" => O <= in3;
when "11" => O <= in4;
when others => O <= "0000000000000000";
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- File Name : HostBFM.vhd
--
-- Project : JPEG_ENC
--
-- Module : HostBFM
--
-- Content : Host BFM (Xilinx OPB v2.1)
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
library work;
use work.GPL_V2_Image_Pkg.ALL;
use WORK.MDCT_PKG.all;
use WORK.MDCTTB_PKG.all;
use work.JPEG_PKG.all;
entity HostBFM is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : out std_logic_vector(31 downto 0);
OPB_BE : out std_logic_vector(3 downto 0);
OPB_DBus_in : out std_logic_vector(31 downto 0);
OPB_RNW : out std_logic;
OPB_select : out std_logic;
OPB_DBus_out : in std_logic_vector(31 downto 0);
OPB_XferAck : in std_logic;
OPB_retry : in std_logic;
OPB_toutSup : in std_logic;
OPB_errAck : in std_logic;
-- HOST DATA
iram_wdata : out std_logic_vector(C_PIXEL_BITS-1 downto 0);
iram_wren : out std_logic;
fifo_almost_full : in std_logic;
sim_done : out std_logic
);
end entity HostBFM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of HostBFM is
signal num_comps : integer;
signal addr_inc : integer := 0;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- code
-------------------------------------------------------------------
p_code : process
-----------------------------------------------------------------
-- HOST WRITE
-----------------------------------------------------------------
procedure host_write
(
signal clk : in std_logic;
constant C_ADDR : in unsigned(31 downto 0);
constant C_WDATA : in unsigned(31 downto 0);
signal OPB_ABus : out std_logic_vector(31 downto 0);
signal OPB_BE : out std_logic_vector(3 downto 0);
signal OPB_DBus_in : out std_logic_vector(31 downto 0);
signal OPB_RNW : out std_logic;
signal OPB_select : out std_logic;
signal OPB_XferAck : in std_logic
) is
begin
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
wait until rising_edge(clk);
OPB_select <= '1';
OPB_ABus <= std_logic_vector(C_ADDR);
OPB_RNW <= '0';
OPB_BE <= X"F";
OPB_DBus_in <= std_logic_vector(C_WDATA);
wait until rising_edge(clk);
while OPB_XferAck /= '1' loop
wait until rising_edge(clk);
end loop;
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
assert false
report CR&"Host write access, address = " & HexImage(C_ADDR) & ",data written = " & HexImage(C_WDATA) &CR
severity note;
wait until rising_edge(clk);
end procedure host_write;
-----------------------------------------------------------------
-- HOST READ
-----------------------------------------------------------------
procedure host_read
(
signal clk : in std_logic;
constant C_ADDR : in unsigned(31 downto 0);
variable RDATA : out unsigned(31 downto 0);
signal OPB_ABus : out std_logic_vector(31 downto 0);
signal OPB_BE : out std_logic_vector(3 downto 0);
signal OPB_DBus_out : in std_logic_vector(31 downto 0);
signal OPB_RNW : out std_logic;
signal OPB_select : out std_logic;
signal OPB_XferAck : in std_logic
)
is
variable data_r : std_logic_vector(31 downto 0);
begin
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
wait until rising_edge(clk);
OPB_select <= '1';
OPB_ABus <= std_logic_vector(C_ADDR);
OPB_RNW <= '1';
OPB_BE <= X"F";
wait until rising_edge(clk);
while OPB_XferAck /= '1' loop
wait until rising_edge(clk);
end loop;
RDATA := unsigned(OPB_DBus_out);
data_r := OPB_DBus_out;
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
assert false
report CR&"Host read access, address = " & HexImage(C_ADDR) & ",data read = " & HexImage(data_r) &CR
severity note;
wait until rising_edge(clk);
end procedure host_read;
--------------------------------------
-- read text image data
--------------------------------------
procedure read_image is
file infile : TEXT open read_mode is "test.txt";
constant N : integer := 8;
constant MAX_COMPS : integer := 3;
variable inline : LINE;
variable tmp_int : INTEGER := 0;
variable y_size : INTEGER := 0;
variable x_size : INTEGER := 0;
variable matrix : I_MATRIX_TYPE;
variable x_blk_cnt : INTEGER := 0;
variable y_blk_cnt : INTEGER := 0;
variable n_lines_arr : N_LINES_TYPE;
variable line_n : INTEGER := 0;
variable pix_n : INTEGER := 0;
variable x_n : INTEGER := 0;
variable y_n : INTEGER := 0;
variable data_word : unsigned(31 downto 0);
variable image_line : STD_LOGIC_VECTOR(0 to MAX_COMPS*MAX_IMAGE_SIZE_X*IP_W-1);
constant C_IMAGE_RAM_BASE : unsigned(31 downto 0) := X"0010_0000";
variable x_cnt : integer;
variable data_word2 : unsigned(31 downto 0);
variable num_comps_v : integer;
begin
READLINE(infile,inline);
READ(inline,num_comps_v);
READLINE(infile,inline);
READ(inline,y_size);
READLINE(infile,inline);
READ(inline,x_size);
num_comps <= num_comps_v;
if y_size rem N > 0 then
assert false
report "ERROR: Image height dimension is not multiply of 8!"
severity Failure;
end if;
if x_size rem N > 0 then
assert false
report "ERROR: Image width dimension is not multiply of 8!"
severity Failure;
end if;
if x_size > C_MAX_LINE_WIDTH then
assert false
report "ERROR: Image width bigger than C_MAX_LINE_WIDTH in JPEG_PKG.VHD! " &
"Increase C_MAX_LINE_WIDTH accordingly"
severity Failure;
end if;
addr_inc <= 0;
-- image size
host_write(CLK, X"0000_0004", to_unsigned(x_size,16) & to_unsigned(y_size,16),
OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
iram_wren <= '0';
for y_n in 0 to y_size-1 loop
READLINE(infile,inline);
HREAD(inline,image_line(0 to num_comps*x_size*IP_W-1));
x_cnt := 0;
for x_n in 0 to x_size-1 loop
data_word := X"00" & UNSIGNED(image_line(x_cnt to x_cnt+num_comps*IP_W-1));
if C_PIXEL_BITS = 24 then
data_word2(7 downto 0) := data_word(23 downto 16);
data_word2(15 downto 8) := data_word(15 downto 8);
data_word2(23 downto 16) := data_word(7 downto 0);
else
data_word2(4 downto 0) := data_word(23 downto 19);
data_word2(10 downto 5) := data_word(15 downto 10);
data_word2(15 downto 11) := data_word(7 downto 3);
end if;
iram_wren <= '0';
iram_wdata <= (others => 'X');
while(fifo_almost_full = '1') loop
wait until rising_edge(clk);
end loop;
--for i in 0 to 9 loop
-- wait until rising_edge(clk);
--end loop;
iram_wren <= '1';
iram_wdata <= std_logic_vector(data_word2(C_PIXEL_BITS-1 downto 0));
wait until rising_edge(clk);
x_cnt := x_cnt + num_comps*IP_W;
addr_inc <= addr_inc + 1;
end loop;
end loop;
iram_wren <= '0';
end read_image;
------------------
type ROMQ_TYPE is array (0 to 64-1)
of unsigned(7 downto 0);
constant qrom_lum : ROMQ_TYPE :=
(
-- 100%
--others => X"01"
-- 85%
--X"05", X"03", X"04", X"04",
--X"04", X"03", X"05", X"04",
--X"04", X"04", X"05", X"05",
--X"05", X"06", X"07", X"0C",
--X"08", X"07", X"07", X"07",
--X"07", X"0F", X"0B", X"0B",
--X"09", X"0C", X"11", X"0F",
--X"12", X"12", X"11", X"0F",
--X"11", X"11", X"13", X"16",
--X"1C", X"17", X"13", X"14",
--X"1A", X"15", X"11", X"11",
--X"18", X"21", X"18", X"1A",
--X"1D", X"1D", X"1F", X"1F",
--X"1F", X"13", X"17", X"22",
--X"24", X"22", X"1E", X"24",
--X"1C", X"1E", X"1F", X"1E"
-- 100%
--others => X"01"
-- 75%
--X"08", X"06", X"06", X"07", X"06", X"05", X"08", X"07", X"07", X"07", X"09", X"09", X"08", X"0A", X"0C", X"14",
--X"0D", X"0C", X"0B", X"0B", X"0C", X"19", X"12", X"13", X"0F", X"14", X"1D", X"1A", X"1F", X"1E", X"1D", X"1A",
--X"1C", X"1C", X"20", X"24", X"2E", X"27", X"20", X"22", X"2C", X"23", X"1C", X"1C", X"28", X"37", X"29", X"2C",
--X"30", X"31", X"34", X"34", X"34", X"1F", X"27", X"39", X"3D", X"38", X"32", X"3C", X"2E", X"33", X"34", X"32"
-- 15 %
--X"35", X"25", X"28", X"2F",
--X"28", X"21", X"35", X"2F",
--X"2B", X"2F", X"3C", X"39",
--X"35", X"3F", X"50", X"85",
--X"57", X"50", X"49", X"49",
--X"50", X"A3", X"75", X"7B",
--X"61", X"85", X"C1", X"AA",
--X"CB", X"C8", X"BE", X"AA",
--X"BA", X"B7", X"D5", X"F0",
--X"FF", X"FF", X"D5", X"E2",
--X"FF", X"E6", X"B7", X"BA",
--X"FF", X"FF", X"FF", X"FF",
--X"FF", X"FF", X"FF", X"FF",
--X"FF", X"CE", X"FF", X"FF",
--X"FF", X"FF", X"FF", X"FF",
--X"FF", X"FF", X"FF", X"FF"
-- 50%
X"10", X"0B", X"0C", X"0E", X"0C", X"0A", X"10", X"0E",
X"0D", X"0E", X"12", X"11", X"10", X"13", X"18", X"28",
X"1A", X"18", X"16", X"16", X"18", X"31", X"23", X"25",
X"1D", X"28", X"3A", X"33", X"3D", X"3C", X"39", X"33",
X"38", X"37", X"40", X"48", X"5C", X"4E", X"40", X"44",
X"57", X"45", X"37", X"38", X"50", X"6D", X"51", X"57",
X"5F", X"62", X"67", X"68", X"67", X"3E", X"4D", X"71",
X"79", X"70", X"64", X"78", X"5C", X"65", X"67", X"63"
);
constant qrom_chr : ROMQ_TYPE :=
(
-- 50% for chrominance
X"11", X"12", X"12", X"18", X"15", X"18", X"2F", X"1A",
X"1A", X"2F", X"63", X"42", X"38", X"42", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63"
-- 75% chrominance
--X"09", X"09", X"09", X"0C", X"0B", X"0C", X"18", X"0D",
--X"0D", X"18", X"32", X"21", X"1C", X"21", X"32", X"32",
--X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
--X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
--X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
--X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
--X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
--X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32"
--X"08", X"06", X"06", X"07", X"06", X"05", X"08", X"07", X"07", X"07", X"09", X"09", X"08", X"0A", X"0C", X"14",
--X"0D", X"0C", X"0B", X"0B", X"0C", X"19", X"12", X"13", X"0F", X"14", X"1D", X"1A", X"1F", X"1E", X"1D", X"1A",
--X"1C", X"1C", X"20", X"24", X"2E", X"27", X"20", X"22", X"2C", X"23", X"1C", X"1C", X"28", X"37", X"29", X"2C",
--X"30", X"31", X"34", X"34", X"34", X"1F", X"27", X"39", X"3D", X"38", X"32", X"3C", X"2E", X"33", X"34", X"32"
--others => X"01"
);
variable data_read : unsigned(31 downto 0);
variable data_write : unsigned(31 downto 0);
variable addr : unsigned(31 downto 0);
------------------------------------------------------------------------------
-- BEGIN
------------------------------------------------------------------------------
begin
sim_done <= '0';
iram_wren <= '0';
while RST /= '0' loop
wait until rising_edge(clk);
end loop;
for i in 0 to 100 loop
wait until rising_edge(clk);
end loop;
host_read(CLK, X"0000_0000", data_read,
OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
host_read(CLK, X"0000_0004", data_read,
OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
-- write luminance quantization table
for i in 0 to 64-1 loop
data_write := X"0000_00" & qrom_lum(i);
addr := X"0000_0100" + to_unsigned(4*i,32);
host_write(CLK, addr, data_write,
OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
end loop;
-- write chrominance quantization table
for i in 0 to 64-1 loop
data_write := X"0000_00" & qrom_chr(i);
addr := X"0000_0200" + to_unsigned(4*i,32);
host_write(CLK, addr, data_write,
OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
end loop;
data_write := to_unsigned(1,32) + shift_left(to_unsigned(3,32),1);
-- SOF & num_comps
host_write(CLK, X"0000_0000", data_write,
OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
-- write BUF_FIFO with bitmap
read_image;
-- wait until JPEG encoding is done
host_read(CLK, X"0000_000C", data_read,
OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
while data_read /= 2 loop
host_read(CLK, X"0000_000C", data_read,
OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
end loop;
sim_done <= '1';
wait;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.