content
stringlengths 1
1.04M
⌀ |
|---|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(0 downto 0) := (others => '0');
begin
stackram: for i in 0 to 3 generate
stackmem: RAMB16_S9_S9
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SIM_COLLISION_CHECK => "NONE"
)
port map (
DOA => stack_a_read( ((i+1)*8)-1 downto (i*8)),
DOB => stack_b_read( ((i+1)*8)-1 downto (i*8)),
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr(stackSize_bits-1 downto 2),
ADDRB => stack_b_addr(stackSize_bits-1 downto 2),
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write( ((i+1)*8)-1 downto (i*8)),
DIB => stack_b_write( ((i+1)*8)-1 downto (i*8)),
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable(i),
WEB => stack_b_writeenable(i)
);
end generate;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(0 downto 0) := (others => '0');
begin
stackram: for i in 0 to 3 generate
stackmem: RAMB16_S9_S9
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SIM_COLLISION_CHECK => "NONE"
)
port map (
DOA => stack_a_read( ((i+1)*8)-1 downto (i*8)),
DOB => stack_b_read( ((i+1)*8)-1 downto (i*8)),
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr(stackSize_bits-1 downto 2),
ADDRB => stack_b_addr(stackSize_bits-1 downto 2),
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write( ((i+1)*8)-1 downto (i*8)),
DIB => stack_b_write( ((i+1)*8)-1 downto (i*8)),
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable(i),
WEB => stack_b_writeenable(i)
);
end generate;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(0 downto 0) := (others => '0');
begin
stackram: for i in 0 to 3 generate
stackmem: RAMB16_S9_S9
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SIM_COLLISION_CHECK => "NONE"
)
port map (
DOA => stack_a_read( ((i+1)*8)-1 downto (i*8)),
DOB => stack_b_read( ((i+1)*8)-1 downto (i*8)),
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr(stackSize_bits-1 downto 2),
ADDRB => stack_b_addr(stackSize_bits-1 downto 2),
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write( ((i+1)*8)-1 downto (i*8)),
DIB => stack_b_write( ((i+1)*8)-1 downto (i*8)),
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable(i),
WEB => stack_b_writeenable(i)
);
end generate;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(0 downto 0) := (others => '0');
begin
stackram: for i in 0 to 3 generate
stackmem: RAMB16_S9_S9
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SIM_COLLISION_CHECK => "NONE"
)
port map (
DOA => stack_a_read( ((i+1)*8)-1 downto (i*8)),
DOB => stack_b_read( ((i+1)*8)-1 downto (i*8)),
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr(stackSize_bits-1 downto 2),
ADDRB => stack_b_addr(stackSize_bits-1 downto 2),
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write( ((i+1)*8)-1 downto (i*8)),
DIB => stack_b_write( ((i+1)*8)-1 downto (i*8)),
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable(i),
WEB => stack_b_writeenable(i)
);
end generate;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(0 downto 0) := (others => '0');
begin
stackram: for i in 0 to 3 generate
stackmem: RAMB16_S9_S9
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SIM_COLLISION_CHECK => "NONE"
)
port map (
DOA => stack_a_read( ((i+1)*8)-1 downto (i*8)),
DOB => stack_b_read( ((i+1)*8)-1 downto (i*8)),
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr(stackSize_bits-1 downto 2),
ADDRB => stack_b_addr(stackSize_bits-1 downto 2),
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write( ((i+1)*8)-1 downto (i*8)),
DIB => stack_b_write( ((i+1)*8)-1 downto (i*8)),
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable(i),
WEB => stack_b_writeenable(i)
);
end generate;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(0 downto 0) := (others => '0');
begin
stackram: for i in 0 to 3 generate
stackmem: RAMB16_S9_S9
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SIM_COLLISION_CHECK => "NONE"
)
port map (
DOA => stack_a_read( ((i+1)*8)-1 downto (i*8)),
DOB => stack_b_read( ((i+1)*8)-1 downto (i*8)),
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr(stackSize_bits-1 downto 2),
ADDRB => stack_b_addr(stackSize_bits-1 downto 2),
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write( ((i+1)*8)-1 downto (i*8)),
DIB => stack_b_write( ((i+1)*8)-1 downto (i*8)),
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable(i),
WEB => stack_b_writeenable(i)
);
end generate;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(0 downto 0) := (others => '0');
begin
stackram: for i in 0 to 3 generate
stackmem: RAMB16_S9_S9
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SIM_COLLISION_CHECK => "NONE"
)
port map (
DOA => stack_a_read( ((i+1)*8)-1 downto (i*8)),
DOB => stack_b_read( ((i+1)*8)-1 downto (i*8)),
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr(stackSize_bits-1 downto 2),
ADDRB => stack_b_addr(stackSize_bits-1 downto 2),
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write( ((i+1)*8)-1 downto (i*8)),
DIB => stack_b_write( ((i+1)*8)-1 downto (i*8)),
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable(i),
WEB => stack_b_writeenable(i)
);
end generate;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(0 downto 0) := (others => '0');
begin
stackram: for i in 0 to 3 generate
stackmem: RAMB16_S9_S9
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SIM_COLLISION_CHECK => "NONE"
)
port map (
DOA => stack_a_read( ((i+1)*8)-1 downto (i*8)),
DOB => stack_b_read( ((i+1)*8)-1 downto (i*8)),
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr(stackSize_bits-1 downto 2),
ADDRB => stack_b_addr(stackSize_bits-1 downto 2),
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write( ((i+1)*8)-1 downto (i*8)),
DIB => stack_b_write( ((i+1)*8)-1 downto (i*8)),
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable(i),
WEB => stack_b_writeenable(i)
);
end generate;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(0 downto 0) := (others => '0');
begin
stackram: for i in 0 to 3 generate
stackmem: RAMB16_S9_S9
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SIM_COLLISION_CHECK => "NONE"
)
port map (
DOA => stack_a_read( ((i+1)*8)-1 downto (i*8)),
DOB => stack_b_read( ((i+1)*8)-1 downto (i*8)),
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr(stackSize_bits-1 downto 2),
ADDRB => stack_b_addr(stackSize_bits-1 downto 2),
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write( ((i+1)*8)-1 downto (i*8)),
DIB => stack_b_write( ((i+1)*8)-1 downto (i*8)),
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable(i),
WEB => stack_b_writeenable(i)
);
end generate;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(0 downto 0) := (others => '0');
begin
stackram: for i in 0 to 3 generate
stackmem: RAMB16_S9_S9
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SIM_COLLISION_CHECK => "NONE"
)
port map (
DOA => stack_a_read( ((i+1)*8)-1 downto (i*8)),
DOB => stack_b_read( ((i+1)*8)-1 downto (i*8)),
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr(stackSize_bits-1 downto 2),
ADDRB => stack_b_addr(stackSize_bits-1 downto 2),
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write( ((i+1)*8)-1 downto (i*8)),
DIB => stack_b_write( ((i+1)*8)-1 downto (i*8)),
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable(i),
WEB => stack_b_writeenable(i)
);
end generate;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(0 downto 0) := (others => '0');
begin
stackram: for i in 0 to 3 generate
stackmem: RAMB16_S9_S9
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SIM_COLLISION_CHECK => "NONE"
)
port map (
DOA => stack_a_read( ((i+1)*8)-1 downto (i*8)),
DOB => stack_b_read( ((i+1)*8)-1 downto (i*8)),
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr(stackSize_bits-1 downto 2),
ADDRB => stack_b_addr(stackSize_bits-1 downto 2),
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write( ((i+1)*8)-1 downto (i*8)),
DIB => stack_b_write( ((i+1)*8)-1 downto (i*8)),
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable(i),
WEB => stack_b_writeenable(i)
);
end generate;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(0 downto 0) := (others => '0');
begin
stackram: for i in 0 to 3 generate
stackmem: RAMB16_S9_S9
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SIM_COLLISION_CHECK => "NONE"
)
port map (
DOA => stack_a_read( ((i+1)*8)-1 downto (i*8)),
DOB => stack_b_read( ((i+1)*8)-1 downto (i*8)),
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr(stackSize_bits-1 downto 2),
ADDRB => stack_b_addr(stackSize_bits-1 downto 2),
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write( ((i+1)*8)-1 downto (i*8)),
DIB => stack_b_write( ((i+1)*8)-1 downto (i*8)),
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable(i),
WEB => stack_b_writeenable(i)
);
end generate;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(0 downto 0) := (others => '0');
begin
stackram: for i in 0 to 3 generate
stackmem: RAMB16_S9_S9
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SIM_COLLISION_CHECK => "NONE"
)
port map (
DOA => stack_a_read( ((i+1)*8)-1 downto (i*8)),
DOB => stack_b_read( ((i+1)*8)-1 downto (i*8)),
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr(stackSize_bits-1 downto 2),
ADDRB => stack_b_addr(stackSize_bits-1 downto 2),
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write( ((i+1)*8)-1 downto (i*8)),
DIB => stack_b_write( ((i+1)*8)-1 downto (i*8)),
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable(i),
WEB => stack_b_writeenable(i)
);
end generate;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(0 downto 0) := (others => '0');
begin
stackram: for i in 0 to 3 generate
stackmem: RAMB16_S9_S9
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SIM_COLLISION_CHECK => "NONE"
)
port map (
DOA => stack_a_read( ((i+1)*8)-1 downto (i*8)),
DOB => stack_b_read( ((i+1)*8)-1 downto (i*8)),
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr(stackSize_bits-1 downto 2),
ADDRB => stack_b_addr(stackSize_bits-1 downto 2),
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write( ((i+1)*8)-1 downto (i*8)),
DIB => stack_b_write( ((i+1)*8)-1 downto (i*8)),
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable(i),
WEB => stack_b_writeenable(i)
);
end generate;
end behave;
|
-------------------------------------------------------------------------------------
-- FILE NAME :
--
-- AUTHOR : Luis F Munoz
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity -
-- architecture -
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- Conversion between a standard StellarIP wormhole output to an AXI-Stream Master. Use
-- with StellarIP Block that has a WH_OUT interface but we really want AXI-Stream Master.
-- For example an ADC.
--
-- AXI-Stream Slave <- AXI-Stream Master to WH_IN (this entity) <- WH_OUT
-------------------------------------------------------------------------------------
-- Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
-- provided to you as is. 4DSP specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4DSP does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the Designs
-- will be corrected. Furthermore, 4DSP does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- LIMITATION OF LIABILITY. In no event will 4DSP or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. This limitation will apply even if 4DSP
-- has been advised of the possibility of such damage. This
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
--library declaration
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
-------------------------------------------------------------------------------------
--Entity Declaration
-------------------------------------------------------------------------------------
entity whout_to_axistream is
port (
-- global
clk : in std_logic;
rst : in std_logic;
--Wormhole 'data_in' of type 'wh_in':
data_in_in_stop : out std_logic;
data_in_in_dval : in std_logic;
data_in_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'data_out' of type 'axis_32b_out':
data_out_tdata : out std_logic_vector(63 downto 0);
data_out_tkeep : in std_logic_vector(3 downto 0);
data_out_tlast : out std_logic;
data_out_tready : in std_logic;
data_out_tstrb : in std_logic;
data_out_tuser : out std_logic_vector(31 downto 0);
data_out_tvalid : out std_logic
);
end entity whout_to_axistream;
-------------------------------------------------------------------------------------
--Architecture declaration
-------------------------------------------------------------------------------------
architecture behavioural of whout_to_axistream is
--***********************************************************************************
begin
--***********************************************************************************
inst0_fifo:
entity work.axis2wh_fifo
port map (
rst => rst,
wr_clk => clk,
rd_clk => clk,
din => data_in_in_data,
wr_en => data_in_in_dval,
rd_en => data_out_tready,
dout => data_out_tdata,
full => open,
almost_full => data_in_in_stop,
empty => open,
valid => data_out_tvalid
);
--process(clk, rst)
--begin
-- if rising_edge(clk) then
-- data_out_tdata <= data_in_in_data;
-- data_out_tvalid <= data_in_in_dval;
-- data_in_in_stop <= not data_out_tready;
-- end if;
--end process;
data_out_tuser <= (others=>'0');
data_out_tlast <= '1'; -- This indicates that all transfers are individual packets
--**********************************************************************************
end architecture behavioural;
--**********************************************************************************
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
--
-- Title : Fixed-point package (Instantiated package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary fixed point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library IEEE;
package fixed_pkg is new IEEE.fixed_generic_pkg
generic map (
fixed_round_style => IEEE.fixed_float_types.fixed_round,
fixed_overflow_style => IEEE.fixed_float_types.fixed_saturate,
fixed_guard_bits => 3,
no_warning => false
);
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
--
-- Title : Fixed-point package (Instantiated package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary fixed point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library IEEE;
package fixed_pkg is new IEEE.fixed_generic_pkg
generic map (
fixed_round_style => IEEE.fixed_float_types.fixed_round,
fixed_overflow_style => IEEE.fixed_float_types.fixed_saturate,
fixed_guard_bits => 3,
no_warning => false
);
|
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity neuron_model is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
step_once_complete : out STD_LOGIC; --signals to the core that a time step has finished
eventport_in_spike_aggregate : in STD_LOGIC_VECTOR(511 downto 0);
current_regime_in_stdlv : in STD_LOGIC_VECTOR(1 downto 0);
current_regime_out_stdlv : out STD_LOGIC_VECTOR(1 downto 0);
eventport_out_spike : out STD_LOGIC;
param_time_refract : in sfixed (6 downto -18);
param_conductance_leakConductance : in sfixed (-22 downto -53);
param_voltage_leakReversal : in sfixed (2 downto -22);
param_voltage_thresh : in sfixed (2 downto -22);
param_voltage_reset : in sfixed (2 downto -22);
param_capacitance_C : in sfixed (-33 downto -47);
param_capacitance_inv_C_inv : in sfixed (47 downto 33);
exposure_voltage_v : out sfixed (2 downto -22);
statevariable_voltage_v_out : out sfixed (2 downto -22);
statevariable_voltage_v_in : in sfixed (2 downto -22);
statevariable_time_lastSpikeTime_out : out sfixed (6 downto -18);
statevariable_time_lastSpikeTime_in : in sfixed (6 downto -18);
param_time_SynapseModel_tauDecay : in sfixed (6 downto -18);
param_conductance_SynapseModel_gbase : in sfixed (-22 downto -53);
param_voltage_SynapseModel_erev : in sfixed (2 downto -22);
param_time_inv_SynapseModel_tauDecay_inv : in sfixed (18 downto -6);
exposure_current_SynapseModel_i : out sfixed (-28 downto -53);
exposure_conductance_SynapseModel_g : out sfixed (-22 downto -53);
statevariable_conductance_SynapseModel_g_out : out sfixed (-22 downto -53);
statevariable_conductance_SynapseModel_g_in : in sfixed (-22 downto -53);
derivedvariable_current_SynapseModel_i_out : out sfixed (-28 downto -53);
derivedvariable_current_SynapseModel_i_in : in sfixed (-28 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end neuron_model;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of neuron_model is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal SynapseModel_step_once_complete_fired : STD_LOGIC := '1';
signal step_once_complete_fired : STD_LOGIC := '1';
signal Component_done : STD_LOGIC := '0';
constant cNSpikeSources : integer := 512; -- The number of spike sources.
constant cNOutputs : integer := 512; -- The number of Synapses in the neuron model.
constant cNSelectBits : integer := 9; -- Log2(NOutputs), rounded up.
signal SpikeOut : Std_logic_vector((cNOutputs-1) downto 0);
signal statevariable_voltage_integrating_v_temp_1 : sfixed (2 downto -22);
signal statevariable_voltage_integrating_v_temp_1_next : sfixed (2 downto -22);
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_current_iSyn : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iSyn_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iMemb : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iMemb_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
signal statevariable_voltage_v_next : sfixed (2 downto -22);
signal statevariable_time_lastSpikeTime_next : sfixed (6 downto -18);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
signal EventPort_out_spike_internal : std_logic := '0';
---------------------------------------------------------------------
type regime_type is (refractory,integrating);
signal current_regime_in_int: regime_type;
signal next_regime: regime_type;
function CONV_STDLV_TO_REGIME (DATA :std_logic_vector) return regime_type is
begin
return regime_type'val(to_integer(unsigned(DATA)));
end CONV_STDLV_TO_REGIME;
function CONV_REGIME_TO_STDLV (regime :regime_type) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(regime_type'pos(regime),2));
end CONV_REGIME_TO_STDLV;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
component SynapseModel
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
eventport_in_in : in STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_time_tauDecay : in sfixed (6 downto -18);
param_conductance_gbase : in sfixed (-22 downto -53);
param_voltage_erev : in sfixed (2 downto -22);
param_time_inv_tauDecay_inv : in sfixed (18 downto -6);
exposure_current_i : out sfixed (-28 downto -53);
exposure_conductance_g : out sfixed (-22 downto -53);
statevariable_conductance_g_out : out sfixed (-22 downto -53);
statevariable_conductance_g_in : in sfixed (-22 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal SynapseModel_Component_done : STD_LOGIC ; signal Exposure_current_SynapseModel_i_internal : sfixed (-28 downto -53);
signal Exposure_conductance_SynapseModel_g_internal : sfixed (-22 downto -53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
SynapseModel_uut : SynapseModel
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => SynapseModel_Component_done,
eventport_in_in => EventPort_in_spike_aggregate(0),
param_time_tauDecay => param_time_SynapseModel_tauDecay,
param_conductance_gbase => param_conductance_SynapseModel_gbase,
param_voltage_erev => param_voltage_SynapseModel_erev,
param_time_inv_tauDecay_inv => param_time_inv_SynapseModel_tauDecay_inv,
requirement_voltage_v => statevariable_voltage_v_in,
Exposure_current_i => Exposure_current_SynapseModel_i_internal,
Exposure_conductance_g => Exposure_conductance_SynapseModel_g_internal,
statevariable_conductance_g_out => statevariable_conductance_SynapseModel_g_out,
statevariable_conductance_g_in => statevariable_conductance_SynapseModel_g_in,
derivedvariable_current_i_out => derivedvariable_current_SynapseModel_i_out,
derivedvariable_current_i_in => derivedvariable_current_SynapseModel_i_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_current_SynapseModel_i <= Exposure_current_SynapseModel_i_internal;
Exposure_conductance_SynapseModel_g <= Exposure_conductance_SynapseModel_g_internal;
derived_variable_pre_process_comb :process ( sysparam_time_timestep,exposure_current_SynapseModel_i_internal, param_conductance_leakConductance, param_voltage_leakReversal, statevariable_voltage_v_in , derivedvariable_current_iSyn_next )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep,exposure_current_SynapseModel_i_internal, param_conductance_leakConductance, param_voltage_leakReversal, statevariable_voltage_v_in , derivedvariable_current_iSyn_next )
begin
derivedvariable_current_iSyn_next <= resize(( exposure_current_SynapseModel_i_internal ),-28,-53);
derivedvariable_current_iMemb_next <= resize(( param_conductance_leakConductance * ( param_voltage_leakReversal - statevariable_voltage_v_in ) + derivedvariable_current_iSyn_next ),-28,-53);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_current_iSyn <= derivedvariable_current_iSyn_next;
derivedvariable_current_iMemb <= derivedvariable_current_iMemb_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDRegime EDState Machine Process
---------------------------------------------------------------------
regime_state_process_comb :process (sysparam_time_simtime,current_regime_in_int,init_model,statevariable_voltage_v_in, statevariable_time_lastSpikeTime_in , param_time_refract, sysparam_time_simtime, param_voltage_thresh, statevariable_voltage_v_in )
begin
next_regime <= current_regime_in_int;
if init_model = '1' then
next_regime <= integrating;
else
if ( current_regime_in_int = refractory ) and To_slv ( resize (sysparam_time_simtime- ( statevariable_time_lastSpikeTime_in + param_time_refract ) ,2,-18))(20) = '0' then
next_regime <= integrating;
end if;
if ( current_regime_in_int = integrating ) and To_slv ( resize ( statevariable_voltage_v_in - ( param_voltage_thresh ) ,2,-18))(20) = '0' then
next_regime <= refractory;
end if;
end if;
end process;
current_regime_out_stdlv <= CONV_REGIME_TO_STDLV(next_regime);
current_regime_in_int <= CONV_STDLV_TO_REGIME(current_regime_in_stdlv);
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep, derivedvariable_current_iMemb , param_capacitance_C,param_capacitance_inv_C_inv )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep, derivedvariable_current_iMemb , param_capacitance_C,param_capacitance_inv_C_inv ,statevariable_voltage_v_in)
begin
statevariable_voltage_integrating_v_temp_1_next <= resize(statevariable_voltage_v_in + ( derivedvariable_current_iMemb * param_capacitance_inv_C_inv ) * sysparam_time_timestep,2,-22);
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
statevariable_voltage_integrating_v_temp_1 <= statevariable_voltage_integrating_v_temp_1_next;
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_0 :process (sysparam_time_timestep,init_model,param_voltage_reset,current_regime_in_int,next_regime,statevariable_voltage_integrating_v_temp_1,derivedvariable_current_iMemb,param_capacitance_C,param_capacitance_inv_C_inv)
variable statevariable_voltage_v_temp_1 : sfixed (2 downto -22);
variable statevariable_voltage_v_temp_2 : sfixed (2 downto -22);
begin
if ( current_regime_in_int = refractory ) then
statevariable_voltage_v_temp_1 := resize(statevariable_voltage_v_in ,2,-22);
end if;
if ( current_regime_in_int = integrating ) then
statevariable_voltage_v_temp_1 := statevariable_voltage_integrating_v_temp_1;
end if;
if (not ( current_regime_in_int = next_regime )) and ( next_regime = refractory ) then
statevariable_voltage_v_temp_2 := resize( param_voltage_reset ,2,-22);
else
statevariable_voltage_v_temp_2 := statevariable_voltage_v_temp_1;
end if;
if (not ( current_regime_in_int = next_regime )) and ( next_regime = integrating ) then
end if;
statevariable_voltage_v_next <= statevariable_voltage_v_temp_2;
end process;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_1 :process (sysparam_time_timestep,init_model,current_regime_in_int,next_regime)
variable statevariable_time_lastSpikeTime_temp_1 : sfixed (6 downto -18);
begin
if ( current_regime_in_int = refractory ) then
statevariable_time_lastSpikeTime_temp_1 := resize(statevariable_time_lastSpikeTime_in ,6,-18);
end if;
if ( current_regime_in_int = integrating ) then
statevariable_time_lastSpikeTime_temp_1 := resize(statevariable_time_lastSpikeTime_in ,6,-18);
end if;
if (not ( current_regime_in_int = next_regime )) and ( next_regime = refractory ) then
statevariable_time_lastSpikeTime_temp_1 := resize(sysparam_time_simtime,6,-18);
else
statevariable_time_lastSpikeTime_temp_1 := statevariable_time_lastSpikeTime_in;
end if;
if (not ( current_regime_in_int = next_regime )) and ( next_regime = integrating ) then
end if;
statevariable_time_lastSpikeTime_next <= statevariable_time_lastSpikeTime_temp_1;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
eventport_driver0 :process ( clk,sysparam_time_timestep,init_model, param_voltage_thresh, statevariable_voltage_v_in )
variable eventport_out_spike_temp_1 : std_logic;
variable eventport_out_spike_temp_2 : std_logic;
begin
if rising_edge(clk) and subprocess_all_ready_shot = '1' then
if ( current_regime_in_int = integrating) and To_slv ( resize ( statevariable_voltage_v_in - ( param_voltage_thresh ) ,2,-18))(20) = '0' then
eventport_out_spike_temp_1 := '1';
else
eventport_out_spike_temp_1 := '0';
end if;eventport_out_spike_internal <= eventport_out_spike_temp_1;
end if;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
exposure_voltage_v <= statevariable_voltage_v_in;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
statevariable_voltage_v_out <= statevariable_voltage_v_next;statevariable_time_lastSpikeTime_out <= statevariable_time_lastSpikeTime_next;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
childrenCombined_component_done_process:process(SynapseModel_component_done,CLK)
begin
if (SynapseModel_component_done = '1') then
childrenCombined_component_done <= '1';
else
childrenCombined_component_done <= '0';
end if;
end process childrenCombined_component_done_process;
component_done <= component_done_int and childrenCombined_component_done;
---------------------------------------------------------------------
-- Control the done signal
---------------------------------------------------------------------
step_once_complete_synch:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then step_once_complete <= '0';
step_once_complete_fired <= '1';
else if component_done = '1' and step_once_complete_fired = '0' then
step_once_complete <= '1';
step_once_complete_fired <= '1';
---------------------------------------------------------------------
-- Assign event ports to exposures
---------------------------------------------------------------------
eventport_out_spike <= eventport_out_spike_internal ;
---------------------------------------------------------------------
elsif component_done = '0' then
step_once_complete <= '0';
step_once_complete_fired <= '0';
---------------------------------------------------------------------
-- Assign event ports to exposures
---------------------------------------------------------------------
eventport_out_spike <= '0';
---------------------------------------------------------------------
else
step_once_complete <= '0';
---------------------------------------------------------------------
-- Assign event ports to exposures
---------------------------------------------------------------------
eventport_out_spike <= '0';
---------------------------------------------------------------------
end if;
end if;
end if;
end process step_once_complete_synch;
---------------------------------------------------------------------
end RTL;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fdiv_32ns_32ns_32_16 is
generic (
ID : integer := 2;
NUM_STAGE : integer := 16;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fdiv_32ns_32ns_32_16 is
--------------------- Component ---------------------
component ANN_ap_fdiv_14_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fdiv_14_no_dsp_32_u : component ANN_ap_fdiv_14_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fdiv_32ns_32ns_32_16 is
generic (
ID : integer := 2;
NUM_STAGE : integer := 16;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fdiv_32ns_32ns_32_16 is
--------------------- Component ---------------------
component ANN_ap_fdiv_14_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fdiv_14_no_dsp_32_u : component ANN_ap_fdiv_14_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fdiv_32ns_32ns_32_16 is
generic (
ID : integer := 2;
NUM_STAGE : integer := 16;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fdiv_32ns_32ns_32_16 is
--------------------- Component ---------------------
component ANN_ap_fdiv_14_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fdiv_14_no_dsp_32_u : component ANN_ap_fdiv_14_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fdiv_32ns_32ns_32_16 is
generic (
ID : integer := 2;
NUM_STAGE : integer := 16;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fdiv_32ns_32ns_32_16 is
--------------------- Component ---------------------
component ANN_ap_fdiv_14_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fdiv_14_no_dsp_32_u : component ANN_ap_fdiv_14_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fdiv_32ns_32ns_32_16 is
generic (
ID : integer := 2;
NUM_STAGE : integer := 16;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fdiv_32ns_32ns_32_16 is
--------------------- Component ---------------------
component ANN_ap_fdiv_14_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fdiv_14_no_dsp_32_u : component ANN_ap_fdiv_14_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fdiv_32ns_32ns_32_16 is
generic (
ID : integer := 2;
NUM_STAGE : integer := 16;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fdiv_32ns_32ns_32_16 is
--------------------- Component ---------------------
component ANN_ap_fdiv_14_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fdiv_14_no_dsp_32_u : component ANN_ap_fdiv_14_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fdiv_32ns_32ns_32_16 is
generic (
ID : integer := 2;
NUM_STAGE : integer := 16;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fdiv_32ns_32ns_32_16 is
--------------------- Component ---------------------
component ANN_ap_fdiv_14_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fdiv_14_no_dsp_32_u : component ANN_ap_fdiv_14_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(
opcode : in std_logic_vector (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector (3 downto 0);
wrtrigval : out std_logic_vector (3 downto 0);
wrtrigcfg : out std_logic_vector (3 downto 0);
wrspeed : out std_logic;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic;
abort : out std_logic;
ident : out std_logic;
meta : out std_logic
);
end decoder;
architecture behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
abort <= '0'; ident <= '0'; meta <= '0';
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
when x"02" => ident <= '1';
when x"04" => meta <= '1';
when x"05" => abort <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(
opcode : in std_logic_vector (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector (3 downto 0);
wrtrigval : out std_logic_vector (3 downto 0);
wrtrigcfg : out std_logic_vector (3 downto 0);
wrspeed : out std_logic;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic;
abort : out std_logic;
ident : out std_logic;
meta : out std_logic
);
end decoder;
architecture behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
abort <= '0'; ident <= '0'; meta <= '0';
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
when x"02" => ident <= '1';
when x"04" => meta <= '1';
when x"05" => abort <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(
opcode : in std_logic_vector (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector (3 downto 0);
wrtrigval : out std_logic_vector (3 downto 0);
wrtrigcfg : out std_logic_vector (3 downto 0);
wrspeed : out std_logic;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic;
abort : out std_logic;
ident : out std_logic;
meta : out std_logic
);
end decoder;
architecture behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
abort <= '0'; ident <= '0'; meta <= '0';
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
when x"02" => ident <= '1';
when x"04" => meta <= '1';
when x"05" => abort <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(
opcode : in std_logic_vector (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector (3 downto 0);
wrtrigval : out std_logic_vector (3 downto 0);
wrtrigcfg : out std_logic_vector (3 downto 0);
wrspeed : out std_logic;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic;
abort : out std_logic;
ident : out std_logic;
meta : out std_logic
);
end decoder;
architecture behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
abort <= '0'; ident <= '0'; meta <= '0';
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
when x"02" => ident <= '1';
when x"04" => meta <= '1';
when x"05" => abort <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(
opcode : in std_logic_vector (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector (3 downto 0);
wrtrigval : out std_logic_vector (3 downto 0);
wrtrigcfg : out std_logic_vector (3 downto 0);
wrspeed : out std_logic;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic;
abort : out std_logic;
ident : out std_logic;
meta : out std_logic
);
end decoder;
architecture behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
abort <= '0'; ident <= '0'; meta <= '0';
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
when x"02" => ident <= '1';
when x"04" => meta <= '1';
when x"05" => abort <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(
opcode : in std_logic_vector (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector (3 downto 0);
wrtrigval : out std_logic_vector (3 downto 0);
wrtrigcfg : out std_logic_vector (3 downto 0);
wrspeed : out std_logic;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic;
abort : out std_logic;
ident : out std_logic;
meta : out std_logic
);
end decoder;
architecture behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
abort <= '0'; ident <= '0'; meta <= '0';
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
when x"02" => ident <= '1';
when x"04" => meta <= '1';
when x"05" => abort <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(
opcode : in std_logic_vector (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector (3 downto 0);
wrtrigval : out std_logic_vector (3 downto 0);
wrtrigcfg : out std_logic_vector (3 downto 0);
wrspeed : out std_logic;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic;
abort : out std_logic;
ident : out std_logic;
meta : out std_logic
);
end decoder;
architecture behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
abort <= '0'; ident <= '0'; meta <= '0';
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
when x"02" => ident <= '1';
when x"04" => meta <= '1';
when x"05" => abort <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(
opcode : in std_logic_vector (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector (3 downto 0);
wrtrigval : out std_logic_vector (3 downto 0);
wrtrigcfg : out std_logic_vector (3 downto 0);
wrspeed : out std_logic;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic;
abort : out std_logic;
ident : out std_logic;
meta : out std_logic
);
end decoder;
architecture behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
abort <= '0'; ident <= '0'; meta <= '0';
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
when x"02" => ident <= '1';
when x"04" => meta <= '1';
when x"05" => abort <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(
opcode : in std_logic_vector (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector (3 downto 0);
wrtrigval : out std_logic_vector (3 downto 0);
wrtrigcfg : out std_logic_vector (3 downto 0);
wrspeed : out std_logic;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic;
abort : out std_logic;
ident : out std_logic;
meta : out std_logic
);
end decoder;
architecture behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
abort <= '0'; ident <= '0'; meta <= '0';
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
when x"02" => ident <= '1';
when x"04" => meta <= '1';
when x"05" => abort <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(
opcode : in std_logic_vector (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector (3 downto 0);
wrtrigval : out std_logic_vector (3 downto 0);
wrtrigcfg : out std_logic_vector (3 downto 0);
wrspeed : out std_logic;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic;
abort : out std_logic;
ident : out std_logic;
meta : out std_logic
);
end decoder;
architecture behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
abort <= '0'; ident <= '0'; meta <= '0';
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
when x"02" => ident <= '1';
when x"04" => meta <= '1';
when x"05" => abort <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(
opcode : in std_logic_vector (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector (3 downto 0);
wrtrigval : out std_logic_vector (3 downto 0);
wrtrigcfg : out std_logic_vector (3 downto 0);
wrspeed : out std_logic;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic;
abort : out std_logic;
ident : out std_logic;
meta : out std_logic
);
end decoder;
architecture behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
abort <= '0'; ident <= '0'; meta <= '0';
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
when x"02" => ident <= '1';
when x"04" => meta <= '1';
when x"05" => abort <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(
opcode : in std_logic_vector (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector (3 downto 0);
wrtrigval : out std_logic_vector (3 downto 0);
wrtrigcfg : out std_logic_vector (3 downto 0);
wrspeed : out std_logic;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic;
abort : out std_logic;
ident : out std_logic;
meta : out std_logic
);
end decoder;
architecture behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
abort <= '0'; ident <= '0'; meta <= '0';
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
when x"02" => ident <= '1';
when x"04" => meta <= '1';
when x"05" => abort <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(
opcode : in std_logic_vector (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector (3 downto 0);
wrtrigval : out std_logic_vector (3 downto 0);
wrtrigcfg : out std_logic_vector (3 downto 0);
wrspeed : out std_logic;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic;
abort : out std_logic;
ident : out std_logic;
meta : out std_logic
);
end decoder;
architecture behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
abort <= '0'; ident <= '0'; meta <= '0';
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
when x"02" => ident <= '1';
when x"04" => meta <= '1';
when x"05" => abort <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- Company: Digilent RO
-- Engineer: Mircea Dabacan
--
-- Create Date: 12:57:12 03/01/2008
-- Design Name:
-- Module Name: MouseRefComp - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This is the structural VHDL code of the
-- Digilent Mouse Reference Component.
-- It instantiates three components:
-- - ps2interface
-- - mouse_controller
-- - resolution_mouse_informer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
entity MouseRefComp is
generic (
MainClockSpeed : integer
);
port (
CLK : in std_logic;
RESOLUTION : in std_logic;
RST : in std_logic;
SWITCH : in std_logic;
LEFT : out std_logic;
MIDDLE : out std_logic;
NEW_EVENT : out std_logic;
RIGHT : out std_logic;
XPOS : out std_logic_vector (9 downto 0);
YPOS : out std_logic_vector (9 downto 0);
ZPOS : out std_logic_vector (3 downto 0);
PS2_CLK : inout std_logic;
PS2_DATA : inout std_logic);
end MouseRefComp;
architecture Structural of MouseRefComp is
signal TX_DATA : std_logic_vector (7 downto 0);
signal bitSetMaxX : std_logic;
signal vecValue : std_logic_vector (9 downto 0);
signal bitRead : std_logic;
signal bitWrite : std_logic;
signal bitErr : std_logic;
signal bitSetX : std_logic;
signal bitSetY : std_logic;
signal bitSetMaxY : std_logic;
signal vecRxData : std_logic_vector (7 downto 0);
component mouse_controller
port ( clk : in std_logic;
rst : in std_logic;
read : in std_logic;
write : out std_logic;
err : in std_logic;
setx : in std_logic;
sety : in std_logic;
setmax_x : in std_logic;
setmax_y : in std_logic;
value : in std_logic_vector (9 downto 0);
rx_data : in std_logic_vector (7 downto 0);
tx_data : out std_logic_vector (7 downto 0);
left : out std_logic;
middle : out std_logic;
right : out std_logic;
xpos : out std_logic_vector (9 downto 0);
ypos : out std_logic_vector (9 downto 0);
zpos : out std_logic_vector (3 downto 0);
new_event : out std_logic);
end component;
component resolution_mouse_informer
port ( clk : in std_logic;
rst : in std_logic;
resolution : in std_logic;
switch : in std_logic;
setx : out std_logic;
sety : out std_logic;
setmax_x : out std_logic;
setmax_y : out std_logic;
value : out std_logic_vector (9 downto 0));
end component;
component ps2interface
generic (
MainClockSpeed : integer
);
port ( clk : in std_logic;
rst : in std_logic;
read : out std_logic;
write : in std_logic;
rx_data : out std_logic_vector (7 downto 0);
tx_data : in std_logic_vector (7 downto 0);
busy : out std_logic;
err : out std_logic;
ps2_clk : inout std_logic;
ps2_data : inout std_logic);
end component;
begin
MouseCtrlInst : mouse_controller
port map (clk=>CLK,
rst=>RST,
read=>bitRead,
write=>bitWrite,
err=>bitErr,
setmax_x=>bitSetMaxX,
setmax_y=>bitSetMaxY,
setx=>bitSetX,
sety=>bitSetY,
value(9 downto 0)=>vecValue(9 downto 0),
rx_data(7 downto 0)=>vecRxData(7 downto 0),
tx_data(7 downto 0)=>TX_DATA(7 downto 0),
left=>LEFT,
middle=>MIDDLE,
right=>RIGHT,
xpos(9 downto 0)=>XPOS(9 downto 0),
ypos(9 downto 0)=>YPOS(9 downto 0),
zpos(3 downto 0)=>ZPOS(3 downto 0),
new_event=>NEW_EVENT);
ResMouseInfInst : resolution_mouse_informer
port map (clk=>CLK,
resolution=>RESOLUTION,
rst=>RST,
switch=>SWITCH,
setmax_x=>bitSetMaxX,
setmax_y=>bitSetMaxY,
setx=>bitSetX,
sety=>bitSetY,
value(9 downto 0)=>vecValue(9 downto 0));
Pss2Inst : ps2interface
generic map (MainClockSpeed => MainClockSpeed)
port map (clk=>CLK,
rst=>RST,
tx_data(7 downto 0)=>TX_DATA(7 downto 0),
read=>bitRead,
write=>bitWrite,
busy=>open,
err=>bitErr,
rx_data(7 downto 0)=>vecRxData(7 downto 0),
ps2_clk=>PS2_CLK,
ps2_data=>PS2_DATA);
end Structural;
|
package pack is
function "=" (L: bit; R: bit) return bit;
end package;
package body pack is
function "=" (L: bit; R: bit) return bit is
begin
if L = R then
return '1';
else
return '0';
end if;
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity issue570 is
end entity;
architecture test of issue570 is
signal x : bit := '1';
begin
p1: process is
begin
assert (bit'( '1' ) = bit'( '1' )) = '1';
if x = '0' then
assert false;
end if;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity RS_FF is
PORT ( S: in std_logic;
R: in std_logic;
CLOCK: in std_logic;
CLR: in std_logic;
PRESET: in std_logic;
Q: out std_logic;
QN: out std_logic);
end RS_FF;
Architecture Arch_RS_FF of RS_FF is
begin
FF:process(CLOCK,CLR,PRESET)
begin
if (CLR='0') then
x:='0';
elsif(PRESET='0') then
x:='1';
elsif(CLOCK='1' and CLOCK'EVENT) then
if (S='0' and R='0') then
x:=x;
elsif(S='1' and R='1') then
x:='Z';
elsif(S='0' and R='1') then
x:='0';
else
x:='1';
end if;
end if;
Q<=x;
QN<=not x;
end process FF;
end Arch_RS_FF;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use ieee.numeric_std.all;
entity tb is
generic(
address_width: integer := 13;
memory_file : string := "code.txt";
log_file: string := "out.txt";
uart_support : string := "no"
);
end tb;
architecture tb of tb is
signal clock_in, reset, data, stall, stall_sig: std_logic := '0';
signal uart_read, uart_write: std_logic;
signal boot_enable_n, ram_enable_n, ram_dly: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0);
signal gpio_sig: std_logic := '0';
signal data_read_sram: std_logic_vector(31 downto 0);
signal data_mode: std_logic_vector(2 downto 0);
signal burst, wr, rd, stall_dly, stall_dly2, stall_sram, spi_cs, spi_clk, spi_mosi, spi_miso, hold_n: std_logic := '0';
begin
process --25Mhz system clock
begin
clock_in <= not clock_in;
wait for 20 ns;
clock_in <= not clock_in;
wait for 20 ns;
end process;
process
begin
wait for 4 ms;
gpio_sig <= not gpio_sig;
wait for 100 us;
gpio_sig <= not gpio_sig;
end process;
gpioa_in <= "0000" & gpio_sig & "000";
process
begin
stall <= not stall;
wait for 123 ns;
stall <= not stall;
wait for 123 ns;
end process;
reset <= '0', '1' after 5 ns, '0' after 500 ns;
ext_irq <= "0000000" & periph_irq;
boot_enable_n <= '0' when (address(31 downto 28) = "0000" and stall_sig = '0') or reset = '1' else '1';
ram_enable_n <= '0' when (address(31 downto 28) = "0100" and stall_sig = '0') or reset = '1' else '1';
rd <= '1' when (address(31 downto 28) = "0110" and data_we = "0000" and stall_dly2 = '0') else '0';
wr <= '1' when (address(31 downto 28) = "0110" and data_we /= "0000" and stall_dly2 = '0') else '0';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else
data_read_sram when address(31 downto 28) = "0110" or stall_dly2 = '1' else data_read_ram;
data_w_n_ram <= not data_we;
hold_n <= '1';
burst <= '0';
stall_sig <= stall_sram;
process(clock_in, reset, stall_sram)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
stall_dly <= '0';
stall_dly2 <= '0';
elsif clock_in'event and clock_in = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
stall_dly <= stall_sram;
stall_dly2 <= stall_dly;
end if;
end process;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock_in,
rst_i => reset,
stall_i => stall_sig,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => data_mode,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock_in,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr
);
sram_ctrl_core: entity work.spi_sram_ctrl
port map( clk_i => clock_in,
rst_i => reset,
addr_i => address(23 downto 0),
data_i => data_write,
data_o => data_read_sram,
burst_i => burst,
bmode_i => data_mode(2),
hmode_i => data_mode(1),
wr_i => wr,
rd_i => rd,
data_ack_o => open,
cpu_stall_o => stall_sram,
spi_cs_n_o => spi_cs,
spi_clk_o => spi_clk,
spi_mosi_o => spi_mosi,
spi_miso_i => spi_miso
);
spi_sram: entity work.M23LC1024
port map( SI_SIO0 => spi_mosi,
SO_SIO1 => spi_miso,
SCK => spi_clk,
CS_N => spi_cs,
SIO2 => open,
HOLD_N_SIO3 => hold_n,
RESET => reset
);
-- boot ROM
boot0lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 0)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(7 downto 0)
);
boot0ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 1)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(15 downto 8)
);
boot1lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 2)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(23 downto 16)
);
boot1ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 3)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(31 downto 24)
);
-- RAM
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
-- debug process
debug:
if uart_support = "no" generate
process(clock_in, address)
file store_file : text open write_mode is "debug.txt";
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if clock_in'event and clock_in = '1' then
if address = x"f00000d0" and data = '0' then
data <= '1';
index := conv_integer(data_write(30 downto 24));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
writeline(store_file, hex_file_line);
line_length := 0;
end if;
else
data <= '0';
end if;
end if;
end process;
end generate;
process(clock_in, reset, address)
begin
if reset = '1' then
elsif clock_in'event and clock_in = '0' then
assert address /= x"e0000000" report "end of simulation" severity failure;
assert (address < x"70000000") or (address >= x"e0000000") report "out of memory region" severity failure;
assert address /= x"40000104" report "handling IRQ" severity warning;
end if;
end process;
end tb;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity contact_discoverycud_ram is
generic(
mem_type : string := "block";
dwidth : integer := 8;
awidth : integer := 15;
mem_size : integer := 19200
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of contact_discoverycud_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity contact_discoverycud is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 19200;
AddressWidth : INTEGER := 15);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of contact_discoverycud is
component contact_discoverycud_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
contact_discoverycud_ram_U : component contact_discoverycud_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity contact_discoverycud_ram is
generic(
mem_type : string := "block";
dwidth : integer := 8;
awidth : integer := 15;
mem_size : integer := 19200
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of contact_discoverycud_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity contact_discoverycud is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 19200;
AddressWidth : INTEGER := 15);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of contact_discoverycud is
component contact_discoverycud_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
contact_discoverycud_ram_U : component contact_discoverycud_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity contact_discoverycud_ram is
generic(
mem_type : string := "block";
dwidth : integer := 8;
awidth : integer := 15;
mem_size : integer := 19200
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of contact_discoverycud_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity contact_discoverycud is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 19200;
AddressWidth : INTEGER := 15);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of contact_discoverycud is
component contact_discoverycud_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
contact_discoverycud_ram_U : component contact_discoverycud_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1);
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk100 : in std_ulogic;
clk125 : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
clkvga : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, vgaclk, clk40, clk65, clk50, clk25 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
signal clkval40 : std_logic_vector(1 downto 0);
signal clkval65 : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
clkvga <= vgaclk;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk)
begin -- process
if rising_edge(vgaclk) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk, c2 => gnd, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk, c2 => gnd, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
-- Clock selection
bufg00 : BUFG port map (I => lvgaclk, O => vgaclk);
lvgaclk <= clk25 when clksel = "00" else clk40 when clksel = "01"
else clk50 when clksel = "10" else clk65;
-- Generate clocks
clkdiv : process(clk100, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk100) then
clkval <= clkval + 1;
end if;
end process;
clkdiv65 : process(clk125, rstn)
begin
if rstn = '0' then clkval65 <= "00"; clkval40 <= "00";
elsif rising_edge(clk125) then
clkval65 <= clkval65 + 1;
if clkval40 = "10" then clkval40 <= "00";
else clkval40 <= clkval40 + 1; end if;
end if;
end process;
clk25 <= clkval(1);
clk50 <= clkval(0);
clk40 <= clkval40(1);
clk65 <= clkval65(0);
end rtl;
|
------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_multiplier.vhd
--!
--! @brief fpgaMSP430 16x16 Hardware multiplier.
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use work.fmsp_misc_package.all;
use work.fmsp_per_package.all;
use work.fmsp_functions.all;
entity fmsp_multiplier is
port (
mclk : in std_logic; --! Main system clock
mrst : in std_logic; --! Main system reset
--! INPUTs
per_addr : in std_logic_vector(13 downto 0); --! Peripheral address
per_din : in std_logic_vector(15 downto 0); --! Peripheral data input
per_en : in std_logic; --! Peripheral enable (high active)
per_we : in std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
--! OUTPUTs
per_dout : out std_logic_vector(15 downto 0) --! Peripheral data output
);
end entity fmsp_multiplier;
architecture RTL of fmsp_multiplier is
--=============================================================================
--! 1) PARAMETER/REGISTERS & WIRE DECLARATION
--=============================================================================
--! Register base address (must be aligned to decoder bit width)
constant BASE_ADDR : std_logic_vector(14 downto 0) := "000000100110000";
--! Decoder bit width (defines how many bits are considered for address decoding)
constant DEC_WD : integer := 4;
--! Register addresses offset
constant OP1_MPY : integer := 0;
constant OP1_MPYS : integer := 2;
constant OP1_MAC : integer := 4;
constant OP1_MACS : integer := 6;
constant OP2 : integer := 8;
constant RESLO : integer := 10;
constant RESHI : integer := 12;
constant SUMEXT : integer := 14;
--! Register one-hot decoder utilities
constant DEC_SZ : integer := 2**DEC_WD;
constant BASE_REG : std_logic_vector(DEC_SZ-1 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(1, DEC_SZ));
constant OP1_MPY_D : std_logic_vector(DEC_SZ-1 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(OP1_MPY, DEC_SZ));
constant OP1_MPYS_D : std_logic_vector(DEC_SZ-1 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(OP1_MPYS, DEC_SZ));
constant OP1_MAC_D : std_logic_vector(DEC_SZ-1 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(OP1_MAC, DEC_SZ));
constant OP1_MACS_D : std_logic_vector(DEC_SZ-1 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(OP1_MACS, DEC_SZ));
constant OP2_D : std_logic_vector(DEC_SZ-1 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(OP2, DEC_SZ));
constant RESLO_D : std_logic_vector(DEC_SZ-1 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(RESLO, DEC_SZ));
constant RESHI_D : std_logic_vector(DEC_SZ-1 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(RESHI, DEC_SZ));
constant SUMEXT_D : std_logic_vector(DEC_SZ-1 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(SUMEXT, DEC_SZ));
type fmsp_multiplier_in_type is record
mrst : std_logic; --! Main system reset
per_addr : std_logic_vector(13 downto 0); --! Peripheral address
per_din : std_logic_vector(15 downto 0); --! Peripheral data input
per_en : std_logic; --! Peripheral enable (high active)
per_we : std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
end record;
type reg_type is record
op1 : std_logic_vector(15 downto 0);
op2 : std_logic_vector(15 downto 0);
reslo : std_logic_vector(15 downto 0);
reshi : std_logic_vector(15 downto 0);
sumext_s : std_logic_vector(1 downto 0);
sign_sel : std_logic; --! Detect signed mode
acc_sel : std_logic; --! Detect accumulate mode
cycle : std_logic;--! Detect start of a multiplication
--! To outside of module
nmie : std_logic; --! Non-maskable interrupt enable
wdtie : std_logic; --! Watchdog-timer interrupt enable
nmiifg : std_logic;
wdtifg : std_logic;
wdt_reset : std_logic; --! Watchdog-timer reset
end record;
signal d : fmsp_multiplier_in_type;
signal r : reg_type := ( op1 => x"0000",
op2 => x"0000",
reslo => x"0000",
reshi => x"0000",
sumext_s => "00",
sign_sel => '0', --! Detect signed mode
acc_sel => '0', --! Detect accumulate mode
cycle => '0', --! Detect start of a multiplication
nmie => '0',
wdtie => '0',
nmiifg => '0',
wdtifg => '0',
wdt_reset => '0'
);
signal rin : reg_type;
begin
d.per_addr <= per_addr;
d.per_din <= per_din;
d.per_en <= per_en;
d.per_we <= per_we;
COMB : process (d, r)
variable v : reg_type;
--! Wire pre-declarations
variable v_result_wr : std_logic;
variable v_result_clr : std_logic;
-- variable v_early_read : std_logic;
--! Local register selection
variable v_reg_sel : std_logic;
--! Register local address
variable v_reg_addr : std_logic_vector(DEC_WD-2 downto 0);
--! Register address decode
variable v_reg_dec : std_logic_vector((DEC_SZ/2)-1 downto 0);
--! Read/Write probes
variable v_reg_write : std_logic;
variable v_reg_read : std_logic;
--! Read/Write vectors
variable v_reg_wr : std_logic_vector(DEC_SZ-1 downto 0);
variable v_reg_rd : std_logic_vector(DEC_SZ-1 downto 0);
--! OP1 Register
-------------------!
variable v_op1_wr : std_logic;
variable v_op1_rd : std_logic_vector(15 downto 0);
--! OP2 Register
-------------------!
variable v_op2_wr : std_logic;
variable v_op2_rd : std_logic_vector(15 downto 0);
--! RESLO Register
-------------------!
variable v_reslo_nxt : std_logic_vector(15 downto 0);
variable v_reslo_wr : std_logic;
variable v_reslo_rd : std_logic_vector(15 downto 0);
--! RESHI Register
-------------------!
variable v_reshi_nxt : std_logic_vector(15 downto 0);
variable v_reshi_wr : std_logic;
variable v_reshi_rd : std_logic_vector(15 downto 0);
--! SUMEXT Register
-------------------!
variable v_sumext_s_nxt : std_logic_vector(1 downto 0);
variable v_sumext_nxt : std_logic_vector(15 downto 0);
variable v_sumext : std_logic_vector(15 downto 0);
variable v_sumext_rd : std_logic_vector(15 downto 0);
variable v_op1_mux : std_logic_vector(15 downto 0);
variable v_op2_mux : std_logic_vector(15 downto 0);
variable v_reslo_mux : std_logic_vector(15 downto 0);
variable v_reshi_mux : std_logic_vector(15 downto 0);
variable v_sumext_mux : std_logic_vector(15 downto 0);
--! Combine RESHI & RESLO
variable v_result : std_logic_vector(31 downto 0);
-- variable v_op1_xp : std_logic_vector(16 downto 0);
-- variable v_op2_xp : std_logic_vector(16 downto 0);
--! 17x17 signed multiplication
variable v_product : signed(33 downto 0);
--! Accumulate
variable v_result_nxt : signed(32 downto 0);
--! Next register values
-- variable v_reslo_nxt : std_logic_vector(15 downto 0);
-- variable v_reshi_nxt : std_logic_vector(15 downto 0);
-- variable v_sumext_s_nxt : std_logic_vector(1 downto 0);
--! Expand the operands to support signed & unsigned operations
variable v_op1_xp : std_logic_vector(16 downto 0);
variable v_op2_xp : std_logic_vector(16 downto 0);
--! 17x9 signed multiplication
-- variable v_product : std_logic_vector(25 downto 0);
variable v_product_xp : std_logic_vector(31 downto 0);
--! Accumulate
-- variable v_result_nxt : std_logic_vector(32 downto 0);
--! Next register values
variable v_per_dout : std_logic_vector(15 downto 0);
-- variable v_reshi_nxt : std_logic_vector(15 downto 0);
-- variable v_sumext_s_nxt : std_logic_vector(1 downto 0);
begin
--! default assignment
v := r;
--! overriding assignments
--============================================================================
--! 2) REGISTER DECODER
--============================================================================
--! Local register selection
if (d.per_addr(13 downto DEC_WD-1) = BASE_ADDR(14 downto DEC_WD)) then
v_reg_sel := d.per_en;
else
v_reg_sel := '0';
end if;
--! Register local address
v_reg_addr := d.per_addr(DEC_WD-2 downto 0);
--! Register address decode
v_reg_dec := onehot(v_reg_addr);
--! Read/Write probes
v_reg_write := (d.per_we(1) or d.per_we(0)) and v_reg_sel;
v_reg_read := not(d.per_we(1) or d.per_we(0)) and v_reg_sel;
--! Read/Write vectors
for i in 0 to (DEC_SZ/2)-1 loop
v_reg_wr((i*2)+0) := v_reg_dec(i) and v_reg_write;
v_reg_wr((i*2)+1) := v_reg_dec(i) and v_reg_write;
v_reg_rd((i*2)+0) := v_reg_dec(i) and v_reg_read;
v_reg_rd((i*2)+1) := v_reg_dec(i) and v_reg_read;
end loop;
--============================================================================
--! 3) REGISTERS
--============================================================================
--! OP1 Register
-------------------!
v_op1_wr := v_reg_wr(OP1_MPY) or
v_reg_wr(OP1_MPYS) or
v_reg_wr(OP1_MAC) or
v_reg_wr(OP1_MACS);
if (v_op1_wr = '1') then
v.op1 := d.per_din;
end if;
v_op1_rd := r.op1;
--! OP2 Register
-------------------!
v_op2_wr := v_reg_wr(OP2);
if (v_op2_wr = '1') then
v.op2 := d.per_din;
end if;
v_op2_rd := r.op2;
--! RESLO Register
-------------------!
v_reslo_wr := v_reg_wr(RESLO);
if (v_reslo_wr = '1') then
v.reslo := d.per_din;
elsif (v_result_clr = '1') then
v.reslo := x"0000";
elsif (v_result_wr = '1') then
v.reslo := v_reslo_nxt;
end if;
-- if (v_early_read = '1') then
-- v_reslo_rd := v_reslo_nxt;
-- else
v_reslo_rd := r.reslo;
-- end if;
--! RESHI Register
-------------------!
v_reshi_wr := v_reg_wr(RESLO);
if (v_reshi_wr = '1') then
v.reshi := d.per_din;
elsif (v_result_clr = '1') then
v.reshi := x"0000";
elsif (v_result_wr = '1') then
v.reshi := v_reshi_nxt;
end if;
-- if (v_early_read = '1') then
-- v_reshi_rd := v_reshi_nxt;
-- else
v_reshi_rd := r.reshi;
-- end if;
--! SUMEXT Register
-------------------!
-- v_sumext_nxt := (0 => v_sumext_s_nxt(0), others => v_sumext_s_nxt(1));
v_sumext := (0 => r.sumext_s(0), others => r.sumext_s(1));
v_sumext_rd := v_sumext;
if (v_op2_wr = '1') then
v.sumext_s := (Others => '0');
elsif (v_result_wr = '1') then
v.sumext_s := v_sumext_s_nxt;
end if;
--============================================================================
--! 4) DATA OUTPUT GENERATION
--============================================================================
--! Data output mux
v_op1_mux := word_per_select_dout( OP1_MPY, v_reg_rd, v_op2_rd );
-- if ( (v_reg_rd(OP1_MPY) = '1') or (v_reg_rd(OP1_MPYS) = '1') or (v_reg_rd(OP1_MAC) = '1') or (v_reg_rd(OP1_MACS) = '1') ) then
if ( (v_reg_rd(OP1_MPYS) = '1') or (v_reg_rd(OP1_MAC) = '1') or (v_reg_rd(OP1_MACS) = '1') ) then
v_op1_mux := v_op1_rd;
end if;
v_op2_mux := word_per_select_dout( OP2, v_reg_rd, v_op2_rd );
v_reslo_mux := word_per_select_dout( RESLO, v_reg_rd, v_reslo_rd );
v_reshi_mux := word_per_select_dout( RESHI, v_reg_rd, v_reshi_rd );
v_sumext_mux := word_per_select_dout( SUMEXT, v_reg_rd, v_sumext_rd );
v_per_dout := v_op1_mux or
v_op2_mux or
v_reslo_mux or
v_reshi_mux or
v_sumext_mux;
--============================================================================
--! 5) HARDWARE MULTIPLIER FUNCTIONAL LOGIC
--============================================================================
--! Multiplier configuration
----------------------------
--! Detect signed mode
if (v_op1_wr = '1') then
v.sign_sel := v_reg_wr(OP1_MPYS) or v_reg_wr(OP1_MACS);
end if;
--! Detect accumulate mode
if (v_op1_wr = '1') then
v.acc_sel := v_reg_wr(OP1_MAC) or v_reg_wr(OP1_MACS);
end if;
--! Detect whenever the RESHI and RESLO registers should be cleared
v_result_clr := v_op2_wr and not(r.acc_sel);
--! Combine RESHI & RESLO
v_result := r.reshi & r.reslo;
--! 16x16 Multiplier (result computed in 1 clock cycle)
-------------------------------------------------------
--! Detect start of a multiplication
v.cycle := v_op2_wr;
v_result_wr := r.cycle;
--! Expand the operands to support signed & unsigned operations
v_op1_xp := (r.sign_sel and r.op1(15)) & r.op1;
v_op2_xp := (r.sign_sel and r.op2(15)) & r.op2;
--! 17x17 signed multiplication
v_product := SIGNED(v_op1_xp) * SIGNED(v_op2_xp);
--! Accumulate
v_result_nxt := SIGNED('0' & v_result) + SIGNED('0' & v_product(31 downto 0));
--! Next register values
v_reslo_nxt := STD_LOGIC_VECTOR(v_result_nxt(15 downto 0));
v_reshi_nxt := STD_LOGIC_VECTOR(v_result_nxt(31 downto 16));
if (r.sign_sel = '1') then
v_sumext_s_nxt := v_result_nxt(31) & v_result_nxt(31);
else
v_sumext_s_nxt := '0' & v_result_nxt(31);
end if;
--! Since the MAC is completed within 1 clock cycle,
--! an early read can't happen.
-- v_early_read := '0';
--! drive register inputs
rin <= v;
--! drive module outputs
per_dout <= v_per_dout; --! Peripheral data output
end process COMB;
REGS : process (mclk,mrst)
begin
if (mrst = '1') then
r <= ( op1 => x"0000",
op2 => x"0000",
reslo => x"0000",
reshi => x"0000",
sumext_s => "00",
sign_sel => '0', --! Detect signed mode
acc_sel => '0', --! Detect accumulate mode
cycle => '0', --! Detect start of a multiplication
nmie => '0',
wdtie => '0',
nmiifg => '0',
wdtifg => '0',
wdt_reset => '0'
);
elsif rising_edge(mclk) then
r <= rin;
end if;
end process REGS;
end RTL; |
----------------------------------------------------------------------------------
-- TUM
-- Engineer: Martin Strasser, Ning Chen
--
-- Create Date: 16:34:40 06/16/2008
-- Design Name:
-- Module Name: idea_com - Behavioral
-- Project Name: idea lab
-- Target Devices: Spartan 3E
-- Tool versions: > 9.2
-- Description: This file is intended to be the top
-- level module. It brings the clock generator
-- and the clocked idea module together.
--
-- Revision 1.00 - File created and tested
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Make this the top module:
entity idea_com is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
RxD : in STD_LOGIC;
TxD : out STD_LOGIC;
LEDs : out STD_LOGIC_VECTOR (7 downto 0));
end idea_com;
architecture Behavioral of idea_com is
-- Mapping the inner idea part.
-- The outer part is only to syntesize
-- the clock generator properly.
component idea_com_inner
port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
RxD : in STD_LOGIC;
TxD : out STD_LOGIC;
LEDs : out STD_LOGIC_VECTOR (7 downto 0));
end component;
-- The clock generator for the UART.
-- This block generates a clock of approx. 16*9600 Hz
-- from the 50 MHz system clock.
component clk_div
port ( CLK : in STD_LOGIC;
CLK_OUT : out STD_LOGIC );
end component;
signal clk_out : STD_LOGIC;
begin
clk_div_1 : clk_div port map( clk, clk_out );
idea_1 : idea_com_inner port map( clk_out, Reset, RxD, TxD, LEDs ); --here original: idea_1 : idea_com_inner port map( clk_out, Reset, RxD, TxD, LEDs );
end Behavioral;
|
----------------------------------------------------------------------------------
-- TUM
-- Engineer: Martin Strasser, Ning Chen
--
-- Create Date: 16:34:40 06/16/2008
-- Design Name:
-- Module Name: idea_com - Behavioral
-- Project Name: idea lab
-- Target Devices: Spartan 3E
-- Tool versions: > 9.2
-- Description: This file is intended to be the top
-- level module. It brings the clock generator
-- and the clocked idea module together.
--
-- Revision 1.00 - File created and tested
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Make this the top module:
entity idea_com is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
RxD : in STD_LOGIC;
TxD : out STD_LOGIC;
LEDs : out STD_LOGIC_VECTOR (7 downto 0));
end idea_com;
architecture Behavioral of idea_com is
-- Mapping the inner idea part.
-- The outer part is only to syntesize
-- the clock generator properly.
component idea_com_inner
port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
RxD : in STD_LOGIC;
TxD : out STD_LOGIC;
LEDs : out STD_LOGIC_VECTOR (7 downto 0));
end component;
-- The clock generator for the UART.
-- This block generates a clock of approx. 16*9600 Hz
-- from the 50 MHz system clock.
component clk_div
port ( CLK : in STD_LOGIC;
CLK_OUT : out STD_LOGIC );
end component;
signal clk_out : STD_LOGIC;
begin
clk_div_1 : clk_div port map( clk, clk_out );
idea_1 : idea_com_inner port map( clk_out, Reset, RxD, TxD, LEDs ); --here original: idea_1 : idea_com_inner port map( clk_out, Reset, RxD, TxD, LEDs );
end Behavioral;
|
----------------------------------------------------------------------------------
-- TUM
-- Engineer: Martin Strasser, Ning Chen
--
-- Create Date: 16:34:40 06/16/2008
-- Design Name:
-- Module Name: idea_com - Behavioral
-- Project Name: idea lab
-- Target Devices: Spartan 3E
-- Tool versions: > 9.2
-- Description: This file is intended to be the top
-- level module. It brings the clock generator
-- and the clocked idea module together.
--
-- Revision 1.00 - File created and tested
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Make this the top module:
entity idea_com is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
RxD : in STD_LOGIC;
TxD : out STD_LOGIC;
LEDs : out STD_LOGIC_VECTOR (7 downto 0));
end idea_com;
architecture Behavioral of idea_com is
-- Mapping the inner idea part.
-- The outer part is only to syntesize
-- the clock generator properly.
component idea_com_inner
port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
RxD : in STD_LOGIC;
TxD : out STD_LOGIC;
LEDs : out STD_LOGIC_VECTOR (7 downto 0));
end component;
-- The clock generator for the UART.
-- This block generates a clock of approx. 16*9600 Hz
-- from the 50 MHz system clock.
component clk_div
port ( CLK : in STD_LOGIC;
CLK_OUT : out STD_LOGIC );
end component;
signal clk_out : STD_LOGIC;
begin
clk_div_1 : clk_div port map( clk, clk_out );
idea_1 : idea_com_inner port map( clk_out, Reset, RxD, TxD, LEDs ); --here original: idea_1 : idea_com_inner port map( clk_out, Reset, RxD, TxD, LEDs );
end Behavioral;
|
----------------------------------------------------------------------------------
-- TUM
-- Engineer: Martin Strasser, Ning Chen
--
-- Create Date: 16:34:40 06/16/2008
-- Design Name:
-- Module Name: idea_com - Behavioral
-- Project Name: idea lab
-- Target Devices: Spartan 3E
-- Tool versions: > 9.2
-- Description: This file is intended to be the top
-- level module. It brings the clock generator
-- and the clocked idea module together.
--
-- Revision 1.00 - File created and tested
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Make this the top module:
entity idea_com is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
RxD : in STD_LOGIC;
TxD : out STD_LOGIC;
LEDs : out STD_LOGIC_VECTOR (7 downto 0));
end idea_com;
architecture Behavioral of idea_com is
-- Mapping the inner idea part.
-- The outer part is only to syntesize
-- the clock generator properly.
component idea_com_inner
port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
RxD : in STD_LOGIC;
TxD : out STD_LOGIC;
LEDs : out STD_LOGIC_VECTOR (7 downto 0));
end component;
-- The clock generator for the UART.
-- This block generates a clock of approx. 16*9600 Hz
-- from the 50 MHz system clock.
component clk_div
port ( CLK : in STD_LOGIC;
CLK_OUT : out STD_LOGIC );
end component;
signal clk_out : STD_LOGIC;
begin
clk_div_1 : clk_div port map( clk, clk_out );
idea_1 : idea_com_inner port map( clk_out, Reset, RxD, TxD, LEDs ); --here original: idea_1 : idea_com_inner port map( clk_out, Reset, RxD, TxD, LEDs );
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RAM_Controller is
Port ( clk_200,clk_100 : in STD_LOGIC;
rst : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(15 DOWNTO 0);
data_out : out STD_LOGIC_VECTOR(15 DOWNTO 0);
mask_lb, mask_ub: in std_logic;
done: out STD_LOGIC;
write, read: in STD_LOGIC;
contr_addr_in : in STD_LOGIC_VECTOR(26 DOWNTO 0);
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0));
end RAM_Controller;
architecture Behavioral of RAM_Controller is
component ram2ddrxadc
port(
clk_200MHz_i : in std_logic; -- 200 MHz system clock
rst_i : in std_logic; -- active high system reset
device_temp_i : in std_logic_vector(11 downto 0);
-- RAM interface
-- The RAM is accessing 2 bytes per access
ram_a : in std_logic_vector(26 downto 0); -- input address
ram_dq_i : in std_logic_vector(15 downto 0); -- input data
ram_dq_o : out std_logic_vector(15 downto 0); -- output data
ram_cen : in std_logic; -- chip enable
ram_oen : in std_logic; -- output enable
ram_wen : in std_logic; -- write enable
ram_ub : in std_logic; -- upper byte
ram_lb : in std_logic; -- lower byte
-- DDR2 interface
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0)
);
end component;
-- Physical RAM Pin Signals
signal ram_cen, ram_oen, ram_wen, ram_ub, ram_lb: std_logic;
signal ram_dq_o, ram_dq_i: std_logic_vector (15 downto 0);
type memory_states IS (IDLE_STATE, PREPARE_STATE, READ_STATE, WRITE_STATE, INTERMITENT_STATE);
-- Where current state and next_state are pretty self-forward, last state will check
signal current_state, next_state, last_state: memory_states := IDLE_STATE;
signal temp_data_write, temp_data_read: std_logic_vector(63 downto 0);
signal ram_a: std_logic_vector(26 downto 0);
-- Result
signal read_out: std_logic_vector(15 downto 0) := (others => '0');
-- Counters
signal hundred_nano_seconds_elapsed, wait_counter : integer range 0 to 150 := 0;
signal s_read : std_logic := '0';
signal writeOnce, readOnce : std_logic := '0';
begin
ram2ddr: ram2ddrxadc
port map(
clk_200MHz_i=>clk_200,
rst_i=>rst,
device_temp_i=>"000000000000",
ram_a=>ram_a,
ram_dq_i=>ram_dq_o,
ram_dq_o=>ram_dq_i,
ram_cen=>ram_cen,
ram_oen=>ram_oen,
ram_wen=>ram_wen,
ram_ub=>ram_ub,
ram_lb=>ram_lb,
ddr2_addr=>ddr2_addr,
ddr2_ba=>ddr2_ba,
ddr2_ras_n=>ddr2_ras_n,
ddr2_cas_n=>ddr2_cas_n,
ddr2_we_n=>ddr2_we_n,
ddr2_ck_p=>ddr2_ck_p,
ddr2_ck_n=>ddr2_ck_n,
ddr2_cke=>ddr2_cke,
ddr2_cs_n=>ddr2_cs_n,
ddr2_dm=>ddr2_dm,
ddr2_odt=>ddr2_odt,
ddr2_dq=>ddr2_dq,
ddr2_dqs_p=>ddr2_dqs_p,
ddr2_dqs_n=>ddr2_dqs_n
);
process(clk_100,rst) begin
if(rst = '1') then
current_state <= IDLE_STATE;
elsif(rising_edge(clk_100)) then
current_state <= next_state;
end if;
end process;
process(current_state, rst, clk_100) begin
if(rst = '1') then
read_out <= (others => '0');
readOnce <= '0';
writeOnce <= '0';
elsif(rising_edge(clk_100)) then
next_state <= current_state;
case current_state is
-- State IDLE_STATE: Disable chip enable, write and read
when IDLE_STATE =>
ram_cen <= '1';
ram_oen <= '1';
ram_wen <= '1';
if(read = '1') then
s_read <= '1';
next_state <= PREPARE_STATE;
elsif(write = '1') then
s_read <= '0';
next_state <= PREPARE_STATE;
end if;
-- State PREPARE_STATE: Assert whatever needs to be asserted
when PREPARE_STATE =>
-- Reset the counters
hundred_nano_seconds_elapsed <= 0;
wait_counter <= 0;
-- Read
if(s_read = '1') then
readOnce <= '1';
ram_oen <= '0';
ram_cen <= '0';
ram_lb <= '0';
ram_ub <= '0';
ram_wen <= '1';
next_state <= READ_STATE;
-- Write
else
writeOnce <= '1';
ram_oen <= '1';
ram_cen <= '0';
ram_lb <= '0';
ram_ub <= '0';
ram_wen <= '0';
next_state <= WRITE_STATE;
end if;
-- State READ_STATE: Waits until the delta time indicated by the
-- data sheet has elapsed to finish reading
when READ_STATE =>
hundred_nano_seconds_elapsed <= hundred_nano_seconds_elapsed + 1;
-- Wait till the necessary clock cycles elapsed while it's recording the data
if(hundred_nano_seconds_elapsed > 22) then
read_out <= ram_dq_i;
next_state <= INTERMITENT_STATE;
end if;
-- Once we're at the write state, the upper and lower byte masks had been asserted
-- to start writing, after which we are free to select the mask combination we need.
when WRITE_STATE =>
ram_lb <= mask_lb;
ram_ub <= mask_ub;
hundred_nano_seconds_elapsed <= hundred_nano_seconds_elapsed + 1;
if(hundred_nano_seconds_elapsed > 27) then
next_state <= INTERMITENT_STATE;
-- Dummy read_out to signal we are done writing
read_out <= (5 => '1', others => '0');
end if;
-- State INTERMITENT_STATE: The done flag will be raised to allow the MMU
-- to continue onto the next byte
when INTERMITENT_STATE =>
read_out <= ram_dq_i;
next_state <= IDLE_STATE;
when others =>
next_state <= IDLE_STATE;
end case;
end if;
end process;
ram_dq_o <= data_in;
ram_a <= contr_addr_in;
data_out <= read_out;
done <= '1' when current_state = INTERMITENT_STATE else '0';
end Behavioral;
|
-- altera_asmi_parallel.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity altera_asmi_parallel is
port (
clkin : in std_logic := '0'; -- clkin.clk
fast_read : in std_logic := '0'; -- fast_read.fast_read
rden : in std_logic := '0'; -- rden.rden
addr : in std_logic_vector(23 downto 0) := (others => '0'); -- addr.addr
read_sid : in std_logic := '0'; -- read_sid.read_sid
read_status : in std_logic := '0'; -- read_status.read_status
write : in std_logic := '0'; -- write.write
datain : in std_logic_vector(7 downto 0) := (others => '0'); -- datain.datain
shift_bytes : in std_logic := '0'; -- shift_bytes.shift_bytes
sector_protect : in std_logic := '0'; -- sector_protect.sector_protect
sector_erase : in std_logic := '0'; -- sector_erase.sector_erase
bulk_erase : in std_logic := '0'; -- bulk_erase.bulk_erase
wren : in std_logic := '0'; -- wren.wren
read_rdid : in std_logic := '0'; -- read_rdid.read_rdid
reset : in std_logic := '0'; -- reset.reset
read_dummyclk : in std_logic := '0'; -- read_dummyclk.read_dummyclk
dataout : out std_logic_vector(7 downto 0); -- dataout.dataout
busy : out std_logic; -- busy.busy
data_valid : out std_logic; -- data_valid.data_valid
epcs_id : out std_logic_vector(7 downto 0); -- epcs_id.epcs_id
status_out : out std_logic_vector(7 downto 0); -- status_out.status_out
illegal_write : out std_logic; -- illegal_write.illegal_write
illegal_erase : out std_logic; -- illegal_erase.illegal_erase
rdid_out : out std_logic_vector(7 downto 0) -- rdid_out.rdid_out
);
end entity altera_asmi_parallel;
architecture rtl of altera_asmi_parallel is
component niosii_epcq_controller_0_altera_asmi_parallel_altera_asmi_parallel is
port (
clkin : in std_logic := 'X'; -- clk
fast_read : in std_logic := 'X'; -- fast_read
rden : in std_logic := 'X'; -- rden
addr : in std_logic_vector(23 downto 0) := (others => 'X'); -- addr
read_sid : in std_logic := 'X'; -- read_sid
read_status : in std_logic := 'X'; -- read_status
write : in std_logic := 'X'; -- write
datain : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain
shift_bytes : in std_logic := 'X'; -- shift_bytes
sector_protect : in std_logic := 'X'; -- sector_protect
sector_erase : in std_logic := 'X'; -- sector_erase
bulk_erase : in std_logic := 'X'; -- bulk_erase
wren : in std_logic := 'X'; -- wren
read_rdid : in std_logic := 'X'; -- read_rdid
reset : in std_logic := 'X'; -- reset
read_dummyclk : in std_logic := 'X'; -- read_dummyclk
dataout : out std_logic_vector(7 downto 0); -- dataout
busy : out std_logic; -- busy
data_valid : out std_logic; -- data_valid
epcs_id : out std_logic_vector(7 downto 0); -- epcs_id
status_out : out std_logic_vector(7 downto 0); -- status_out
illegal_write : out std_logic; -- illegal_write
illegal_erase : out std_logic; -- illegal_erase
rdid_out : out std_logic_vector(7 downto 0) -- rdid_out
);
end component niosii_epcq_controller_0_altera_asmi_parallel_altera_asmi_parallel;
begin
altera_asmi_parallel : component niosii_epcq_controller_0_altera_asmi_parallel_altera_asmi_parallel
port map (
clkin => clkin, -- clkin.clk
fast_read => fast_read, -- fast_read.fast_read
rden => rden, -- rden.rden
addr => addr, -- addr.addr
read_sid => read_sid, -- read_sid.read_sid
read_status => read_status, -- read_status.read_status
write => write, -- write.write
datain => datain, -- datain.datain
shift_bytes => shift_bytes, -- shift_bytes.shift_bytes
sector_protect => sector_protect, -- sector_protect.sector_protect
sector_erase => sector_erase, -- sector_erase.sector_erase
bulk_erase => bulk_erase, -- bulk_erase.bulk_erase
wren => wren, -- wren.wren
read_rdid => read_rdid, -- read_rdid.read_rdid
reset => reset, -- reset.reset
read_dummyclk => read_dummyclk, -- read_dummyclk.read_dummyclk
dataout => dataout, -- dataout.dataout
busy => busy, -- busy.busy
data_valid => data_valid, -- data_valid.data_valid
epcs_id => epcs_id, -- epcs_id.epcs_id
status_out => status_out, -- status_out.status_out
illegal_write => illegal_write, -- illegal_write.illegal_write
illegal_erase => illegal_erase, -- illegal_erase.illegal_erase
rdid_out => rdid_out -- rdid_out.rdid_out
);
end architecture rtl; -- of altera_asmi_parallel
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package stream is
subtype valid_t is std_logic;
subtype ready_t is std_logic;
type array_ready_t is array (natural range <>) of ready_t;
type array_valid_t is array (natural range <>) of valid_t;
-- dummy functionality which needs to be shared
procedure split_stream (
signal outcomb : out array_valid_t;
signal outalone : out ready_t;
signal incomb : in array_ready_t;
signal inalone : in valid_t);
end package;
package body stream is
procedure split_stream (
signal outcomb : out array_valid_t;
signal outalone : out ready_t;
signal incomb : in array_ready_t;
signal inalone : in valid_t)
is
begin
outcomb <= (outcomb'range => '1');
outalone <= '1';
end procedure split_stream;
end stream;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.stream.all;
entity BFPD is
port (
reset : in std_logic; -- asynchronous eset
clock : in std_logic; -- clock
clock_en : in std_logic; -- clock enable
in_valid : in valid_t;
in_ready : out ready_t;
out_valid : out valid_t;
out_ready : in ready_t
);
end BFPD;
architecture rtl of BFPD is
type ctrl_t is (MANT_RET_IN, EXP_RET_IN, DIV_RET_IN,
MANT_RET_OUT, EXP_RET_OUT, DIV_RET_OUT,
MULT);
subtype ctrl_range_t is integer range ctrl_t'pos(ctrl_t'left) to ctrl_t'pos(ctrl_t'right);
subtype ret_split_t is integer range ctrl_t'pos(MANT_RET_IN) to ctrl_t'pos(DIV_RET_IN);
signal ready: array_ready_t(ctrl_range_t);
signal valid: array_valid_t(ctrl_range_t);
begin
split_stream (outcomb => valid(ret_split_t), outalone => in_ready,
incomb => ready(ret_split_t), inalone => in_valid);
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package stream is
subtype valid_t is std_logic;
subtype ready_t is std_logic;
type array_ready_t is array (natural range <>) of ready_t;
type array_valid_t is array (natural range <>) of valid_t;
-- dummy functionality which needs to be shared
procedure split_stream (
signal outcomb : out array_valid_t;
signal outalone : out ready_t;
signal incomb : in array_ready_t;
signal inalone : in valid_t);
end package;
package body stream is
procedure split_stream (
signal outcomb : out array_valid_t;
signal outalone : out ready_t;
signal incomb : in array_ready_t;
signal inalone : in valid_t)
is
begin
outcomb <= (outcomb'range => '1');
outalone <= '1';
end procedure split_stream;
end stream;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.stream.all;
entity BFPD is
port (
reset : in std_logic; -- asynchronous eset
clock : in std_logic; -- clock
clock_en : in std_logic; -- clock enable
in_valid : in valid_t;
in_ready : out ready_t;
out_valid : out valid_t;
out_ready : in ready_t
);
end BFPD;
architecture rtl of BFPD is
type ctrl_t is (MANT_RET_IN, EXP_RET_IN, DIV_RET_IN,
MANT_RET_OUT, EXP_RET_OUT, DIV_RET_OUT,
MULT);
subtype ctrl_range_t is integer range ctrl_t'pos(ctrl_t'left) to ctrl_t'pos(ctrl_t'right);
subtype ret_split_t is integer range ctrl_t'pos(MANT_RET_IN) to ctrl_t'pos(DIV_RET_IN);
signal ready: array_ready_t(ctrl_range_t);
signal valid: array_valid_t(ctrl_range_t);
begin
split_stream (outcomb => valid(ret_split_t), outalone => in_ready,
incomb => ready(ret_split_t), inalone => in_valid);
end rtl;
|
entity test is
package a is new b generic map(inertial foo);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.sampler_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity sampler_tb is
end entity;
architecture tb of sampler_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal sample_L : signed(17 downto 0);
signal sample_R : signed(17 downto 0);
signal new_sample : std_logic;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_dut: entity work.sampler
generic map (
g_clock_freq => 62_500_000,
g_num_voices => 8 )
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
mem_req => mem_req,
mem_resp => mem_resp,
sample_L => sample_L,
sample_R => sample_R,
new_sample => new_sample );
i_io_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => io_req,
resp => io_resp );
i_mem_bfm: entity work.mem_bus_slave_bfm
generic map (
g_name => "mem_bfm",
g_latency => 2 )
port map (
clock => clock,
req => mem_req,
resp => mem_resp );
test: process
variable io : p_io_bus_bfm_object;
variable mem : h_mem_object;
variable d : std_logic_vector(7 downto 0);
begin
wait until reset='0';
bind_io_bus_bfm("io_bfm", io);
bind_mem_model("mem_bfm", mem);
for i in 0 to 255 loop
d := std_logic_vector(to_signed(integer(127.0*sin(real(i) / 40.58451048843)), 8));
write_memory_8(mem, std_logic_vector(to_unsigned(16#1234500#+i, 32)), d);
end loop;
io_write(io, X"00" + c_sample_volume , X"3F");
io_write(io, X"00" + c_sample_pan , X"07");
io_write(io, X"00" + c_sample_start_addr_h , X"01");
io_write(io, X"00" + c_sample_start_addr_mh , X"23");
io_write(io, X"00" + c_sample_start_addr_ml , X"45");
io_write(io, X"00" + c_sample_start_addr_l , X"00");
io_write(io, X"00" + c_sample_length_h , X"00");
io_write(io, X"00" + c_sample_length_m , X"01");
io_write(io, X"00" + c_sample_length_l , X"00");
io_write(io, X"00" + c_sample_rate_h , X"00");
io_write(io, X"00" + c_sample_rate_l , X"18");
io_write(io, X"00" + c_sample_control , X"01");
io_write(io, X"20" + c_sample_volume , X"28");
io_write(io, X"20" + c_sample_pan , X"0F");
io_write(io, X"20" + c_sample_start_addr_h , X"01");
io_write(io, X"20" + c_sample_start_addr_mh , X"23");
io_write(io, X"20" + c_sample_start_addr_ml , X"45");
io_write(io, X"20" + c_sample_start_addr_l , X"00");
io_write(io, X"20" + c_sample_length_h , X"00");
io_write(io, X"20" + c_sample_length_m , X"01");
io_write(io, X"20" + c_sample_length_l , X"00");
io_write(io, X"20" + c_sample_rate_h , X"00");
io_write(io, X"20" + c_sample_rate_l , X"05");
io_write(io, X"20" + c_sample_rep_b_pos_l , X"CC");
io_write(io, X"20" + c_sample_control , X"03"); -- repeat on
io_write(io, X"E0" + c_sample_volume , X"38");
io_write(io, X"E0" + c_sample_pan , X"04");
io_write(io, X"E0" + c_sample_start_addr_h , X"01");
io_write(io, X"E0" + c_sample_start_addr_mh , X"23");
io_write(io, X"E0" + c_sample_start_addr_ml , X"45");
io_write(io, X"E0" + c_sample_start_addr_l , X"00");
io_write(io, X"E0" + c_sample_length_h , X"00");
io_write(io, X"E0" + c_sample_length_m , X"00");
io_write(io, X"E0" + c_sample_length_l , X"80");
io_write(io, X"E0" + c_sample_rate_h , X"00");
io_write(io, X"E0" + c_sample_rate_l , X"09");
io_write(io, X"E0" + c_sample_rep_b_pos_l , X"80");
io_write(io, X"E0" + c_sample_control , X"13"); -- repeat on, 16 bit
wait;
end process;
end architecture;
|
entity tb_dff05 is
end tb_dff05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff05 is
signal clk : std_logic;
signal en1 : std_logic;
signal en2 : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff05
port map (
q => dout,
d => din,
en1 => en1,
en2 => en2,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
en1 <= '1';
en2 <= '1';
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
en1 <= '0';
din <= '0';
pulse;
assert dout = '1' severity failure;
en1 <= '1';
din <= '0';
pulse;
assert dout = '0' severity failure;
en2 <= '0';
din <= '1';
pulse;
assert dout = '0' severity failure;
en2 <= '1';
din <= '1';
pulse;
assert dout = '1' severity failure;
wait;
end process;
end behav;
|
-- Company: Fachhochschule Dortmund
-- Engineer: Mysara Ibrahim
--
-- Create Date: 06/16/2017 03:07:27 PM
-- Design Name: TraceBack testbench for Convolutional Codes example project
-- Module Name: TraceBack_tb - Behavioral
-- Project Name: Convolutional Codes example project
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.conf_pkg.all;
entity TraceBack_tb is
-- Port ( );
end TraceBack_tb;
architecture Behavioral of TraceBack_tb is
component MyTraceBack
port (index : in integer;
surv_path : in integer;
selectionIndex1, selectionIndex2, selectionIndex3, selectionIndex4 : in bit;
selectionIndex5, selectionIndex6, selectionIndex7, selectionIndex8 : in bit;
Decoded_out : out std_logic_vector(seq downto 0):=(others => '0'));
end component MyTraceBack;
signal selectx1, selectx2, selectx3, selectx4, selectx5, selectx6, selectx7, selectx8 : bit;
signal surv_sig, index1 : integer range 0 to 8;
signal trac_out : std_logic_vector(seq downto 0):="00000000";
begin
resbts : MyTraceBack port map(index => index1, surv_path => surv_sig,
selectionIndex1 => selectx1, selectionIndex2 => selectx2,
selectionIndex3 => selectx3, selectionIndex4 => selectx4,
selectionIndex5 => selectx5, selectionIndex6 => selectx6,
selectionIndex7 => selectx7, selectionIndex8 => selectx8,
Decoded_out => trac_out);
stim_proc : process
begin
wait for clk_period/2;
index1 <= 0;
selectx1 <= '1';selectx2 <= '1';selectx3 <= '1';selectx4 <= '1';selectx5 <= '1';selectx6 <= '1';selectx7 <= '1';selectx8 <= '1';
wait for clk_period;
index1 <= index1+1;
selectx1 <= '1';selectx2 <= '1';selectx3 <= '1';selectx4 <= '1';selectx5 <= '0';selectx6 <= '1';selectx7 <= '1';selectx8 <= '1';
wait for clk_period;
index1 <= index1+1;
selectx1 <= '1';selectx2 <= '1';selectx3 <= '0';selectx4 <= '1';selectx5 <= '1';selectx6 <= '1';selectx7 <= '1';selectx8 <= '1';
wait for clk_period;
index1 <= index1+1;
selectx1 <= '1';selectx2 <= '1';selectx3 <= '1';selectx4 <= '1';selectx5 <= '1';selectx6 <= '0';selectx7 <= '1';selectx8 <= '1';
wait for clk_period;
index1 <= index1+1;
selectx1 <= '1';selectx2 <= '1';selectx3 <= '1';selectx4 <= '1';selectx5 <= '1';selectx6 <= '1';selectx7 <= '1';selectx8 <= '1';
wait for clk_period;
index1 <= index1+1;
selectx1 <= '1';selectx2 <= '1';selectx3 <= '1';selectx4 <= '0';selectx5 <= '1';selectx6 <= '1';selectx7 <= '1';selectx8 <= '1';
wait for clk_period;
index1 <= index1+1;
selectx1 <= '1';selectx2 <= '1';selectx3 <= '1';selectx4 <= '1';selectx5 <= '1';selectx6 <= '1';selectx7 <= '1';selectx8 <= '1';
wait for clk_period;
index1 <= index1+1; surv_sig <= 1;
selectx1 <= '1';selectx2 <= '1';selectx3 <= '1';selectx4 <= '1';selectx5 <= '1';selectx6 <= '1';selectx7 <= '1';selectx8 <= '1';
wait for 3*clk_period/2;
end process;
end Behavioral;
|
-- ROM package
library ieee;
use ieee.std_logic_1164.all;
package p1_rom is
constant w:integer:= 32; --width of ROM
constant l:integer:= 25; --lenght of ROM
subtype rom_word is std_logic_vector(w-1 downto 0);
type rom_table is array (0 to l-1) of rom_word;
constant rom_image:rom_table:=rom_table'(
"00000000000000000000000000000000",
"01111111110000000000000000001110",
"00000100001000000000000000001100",
"00000000100000000000000000000000",
"10001100010000010000000100000000",
"10001100011000010000000100000100",
"00100000101000100001100000000000",
"00000100001000011111111111111100",
"00000000100001000010100000000000",
"01100000101000000000100000000000",
"01011100101000001111111111111010",
"00000000000000000000000000000000",
"10011100100000000000000100001000",
"01001100000000000000000000000000",
"00000000000000000000000000000000",
"00000100001000000000000000100000",
"10011100001000010000000011111111",
"00000100001000011111111111111100",
"01011100001000001111111111111110",
"00000000000000000000000000000000",
"01111100000111100000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000");
end; |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_8;
USE axi_dma_v7_1_8.axi_dma;
ENTITY design_SWandHW_standalone_axi_dma_1_1 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_SWandHW_standalone_axi_dma_1_1;
ARCHITECTURE design_SWandHW_standalone_axi_dma_1_1_arch OF design_SWandHW_standalone_axi_dma_1_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SWandHW_standalone_axi_dma_1_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SWandHW_standalone_axi_dma_1_1_arch: ARCHITECTURE IS "axi_dma,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SWandHW_standalone_axi_dma_1_1_arch : ARCHITECTURE IS "design_SWandHW_standalone_axi_dma_1_1,axi_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SWandHW_standalone_axi_dma_1_1_arch: ARCHITECTURE IS "design_SWandHW_standalone_axi_dma_1_1,axi_dma,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=14,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=0,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=256,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_INCLUDE_S2MM_DRE=1,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 14,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 0,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 256,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 1,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => '0',
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_bvalid => '0',
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_arready => '0',
m_axi_mm2s_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_mm2s_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_mm2s_rlast => '0',
m_axi_mm2s_rvalid => '0',
m_axis_mm2s_tready => '0',
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END design_SWandHW_standalone_axi_dma_1_1_arch;
|
architecture RTL of FIFO is
signal fifo_wr : std_logic;
signal fifo_wr : std_logic_vector(3 downto 0);
signal fifo_wr : std_logic_vector(3 downto 0) := "000";
signal fifo_wr, fifo_rd, fifo_empty : std_logic := '1';
signal fifo_rd : fifo_wr'subtype;
begin
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
entity reg_a is
generic
(
LW : integer := 8
);
port
(
clk, ie, oe, reset : in std_logic;
data_in : in std_logic_vector(LW-1 downto 0);
data_out : out std_logic_vector(LW-1 downto 0)
);
end reg_a;
architecture behav of reg_a is
--signal reg: std_logic_vector(LW-1 downto 0);
begin
process(reset, clk, ie, oe)
variable reg : std_logic_vector(LW-1 downto 0);
begin
if falling_edge(clk) then
if(reset = '1') then
reg := "00000000";
elsif(ie = '1') then
reg := data_in;
elsif(oe = '1') then
data_out <= reg;
elsif (oe = '0') then
data_out <= (others => 'Z');
-- if(reset = '1') then
-- reg <= (others => '0');
-- elsif(ie = '1') then
-- reg <= data_in;
-- elsif(oe = '1') then
-- data_out <= reg;
-- elsif (oe = '0') then
-- data_out <= (others => 'Z');
end if;
end if;
end process;
end behav;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2061.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02061ent IS
END c07s02b04x00p01n02i02061ent;
ARCHITECTURE c07s02b04x00p01n02i02061arch OF c07s02b04x00p01n02i02061ent IS
signal S1 : Integer;
signal S2 : Integer;
signal S3 : BIT_VECTOR(0 to 7);
BEGIN
TESTING: PROCESS
variable V1,V2 : Integer := 10;
variable V3,V4 : BIT_VECTOR(0 to 3) := "0101" ;
BEGIN
S1 <= V1 + V2;
wait for 1 ns;
assert NOT(S1 = 20)
report "***PASSED TEST: c07s02b04x00p01n02i02061"
severity NOTE;
assert (S1 = 20)
report "***FAILED TEST: c07s02b04x00p01n02i02061 - Operands must be of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02061arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2061.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02061ent IS
END c07s02b04x00p01n02i02061ent;
ARCHITECTURE c07s02b04x00p01n02i02061arch OF c07s02b04x00p01n02i02061ent IS
signal S1 : Integer;
signal S2 : Integer;
signal S3 : BIT_VECTOR(0 to 7);
BEGIN
TESTING: PROCESS
variable V1,V2 : Integer := 10;
variable V3,V4 : BIT_VECTOR(0 to 3) := "0101" ;
BEGIN
S1 <= V1 + V2;
wait for 1 ns;
assert NOT(S1 = 20)
report "***PASSED TEST: c07s02b04x00p01n02i02061"
severity NOTE;
assert (S1 = 20)
report "***FAILED TEST: c07s02b04x00p01n02i02061 - Operands must be of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02061arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2061.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02061ent IS
END c07s02b04x00p01n02i02061ent;
ARCHITECTURE c07s02b04x00p01n02i02061arch OF c07s02b04x00p01n02i02061ent IS
signal S1 : Integer;
signal S2 : Integer;
signal S3 : BIT_VECTOR(0 to 7);
BEGIN
TESTING: PROCESS
variable V1,V2 : Integer := 10;
variable V3,V4 : BIT_VECTOR(0 to 3) := "0101" ;
BEGIN
S1 <= V1 + V2;
wait for 1 ns;
assert NOT(S1 = 20)
report "***PASSED TEST: c07s02b04x00p01n02i02061"
severity NOTE;
assert (S1 = 20)
report "***FAILED TEST: c07s02b04x00p01n02i02061 - Operands must be of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02061arch;
|
-- #################################################################################################
-- # << NEO430 - Processor Test Implementation (neo430_test.vhd) >> #
-- # ********************************************************************************************* #
-- # If you do not have an own design (yet), you can use this unit as top entity to play with #
-- # the NEO430 processor. Take a look at the project's documentary (chapter "Let's Get It #
-- # Started!") to get more information. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_test is
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rst_i : in std_ulogic; -- global reset, async, LOW-active
-- parallel io --
gpio_o : out std_ulogic_vector(07 downto 0); -- parallel output
-- serial com --
uart_txd_o : out std_ulogic; -- UART send data
uart_rxd_i : in std_ulogic -- UART receive data
);
end neo430_test;
architecture neo430_test_rtl of neo430_test is
-- local signals --
signal gpio_out : std_ulogic_vector(15 downto 0);
signal rst_int : std_ulogic;
begin
-- The Core of the Problem --------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_top_test_inst: neo430_top
generic map (
-- general configuration --
CLOCK_SPEED => 100000000, -- main clock in Hz
IMEM_SIZE => 4*1024, -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE => 2*1024, -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE => x"CAFE", -- custom user code
-- module configuration --
MULDIV_USE => true, -- implement multiplier/divider unit? (default=true)
WB32_USE => true, -- implement WB32 unit? (default=true)
WDT_USE => true, -- implement WDT? (default=true)
GPIO_USE => true, -- implement GPIO unit? (default=true)
TIMER_USE => true, -- implement timer? (default=true)
UART_USE => true, -- implement UART? (default=true)
CRC_USE => true, -- implement CRC unit? (default=true)
CFU_USE => false, -- implement custom functions unit? (default=false)
PWM_USE => true, -- implement PWM controller? (default=true)
TWI_USE => true, -- implement two wire serial interface? (default=true)
SPI_USE => true, -- implement SPI? (default=true)
TRNG_USE => false, -- implement TRNG? (default=false)
EXIRQ_USE => true, -- implement EXIRQ? (default=true)
FREQ_GEN_USE => true, -- implement FREQ_GEN? (default=true)
-- boot configuration --
BOOTLD_USE => true, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => false -- implement IMEM as read-only memory? (default=false)
)
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
rst_i => rst_int, -- global reset, async, low-active
-- gpio --
gpio_o => gpio_out, -- parallel output
gpio_i => x"0000", -- parallel input
-- pwm channels --
pwm_o => open, -- pwm channels
-- arbitrary frequency generator --
freq_gen_o => open, -- programmable frequency output
-- serial com --
uart_txd_o => uart_txd_o, -- UART send data
uart_rxd_i => uart_rxd_i, -- UART receive data
spi_sclk_o => open, -- serial clock line
spi_mosi_o => open, -- serial data line out
spi_miso_i => '0', -- serial data line in
spi_cs_o => open, -- SPI CS
twi_sda_io => open, -- twi serial data line
twi_scl_io => open, -- twi serial clock line
-- 32-bit wishbone interface --
wb_adr_o => open, -- address
wb_dat_i => x"00000000", -- read data
wb_dat_o => open, -- write data
wb_we_o => open, -- read/write
wb_sel_o => open, -- byte enable
wb_stb_o => open, -- strobe
wb_cyc_o => open, -- valid cycle
wb_ack_i => '0', -- transfer acknowledge
-- external interrupts --
ext_irq_i => "00000000", -- external interrupt request lines
ext_ack_o => open -- external interrupt request acknowledges
);
-- constrain output signals --
gpio_o <= gpio_out(7 downto 0);
-- internal reset (must be low-active!) --
rst_int <= rst_i; -- invert me?!
end neo430_test_rtl;
|
-- file: dcm_TFT9_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity dcm_TFT9_tb is
end dcm_TFT9_tb;
architecture test of dcm_TFT9_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.000 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
-- Status and control signals
signal RESET : std_logic := '0';
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
component dcm_TFT9_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
begin
report "Timing checks are not valid" severity note;
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
wait until LOCKED = '1';
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
report "Simulation Stopped." severity failure;
wait;
end process;
process (CLK_IN1)
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
begin
if (CLK_IN1'event and CLK_IN1='1') then
timeout_counter <= timeout_counter + '1';
if (timeout_counter = "10000000000000") then
if (LOCKED /= '1') then
simtimeprint;
report "NO LOCK signal" severity failure;
end if;
end if;
end if;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : dcm_TFT9_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET,
LOCKED => LOCKED);
end test;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_3 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_3;
architecture xilinx of blk_mem_gen_v8_3_3 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_3 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_3;
architecture xilinx of blk_mem_gen_v8_3_3 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_3 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_3;
architecture xilinx of blk_mem_gen_v8_3_3 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_3 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_3;
architecture xilinx of blk_mem_gen_v8_3_3 is
begin
end
architecture xilinx;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc501.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p02n01i00501ent IS
END c03s02b02x00p02n01i00501ent;
ARCHITECTURE c03s02b02x00p02n01i00501arch OF c03s02b02x00p02n01i00501ent IS
type rec_type is
record
x : integer;
y : integer;
end record;
BEGIN
TESTING: PROCESS
variable v1 : rec_type;
BEGIN
v1.x := 12;
v1.y := v1.x * 111;
assert NOT(v1.x=12 and v1.y=1332)
report "***PASSED TEST: c03s02b02x00p02n01i00501"
severity NOTE;
assert (v1.x=12 and v1.y=1332)
report "***FAILED TEST: c03s02b02x00p02n01i00501 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p02n01i00501arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc501.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p02n01i00501ent IS
END c03s02b02x00p02n01i00501ent;
ARCHITECTURE c03s02b02x00p02n01i00501arch OF c03s02b02x00p02n01i00501ent IS
type rec_type is
record
x : integer;
y : integer;
end record;
BEGIN
TESTING: PROCESS
variable v1 : rec_type;
BEGIN
v1.x := 12;
v1.y := v1.x * 111;
assert NOT(v1.x=12 and v1.y=1332)
report "***PASSED TEST: c03s02b02x00p02n01i00501"
severity NOTE;
assert (v1.x=12 and v1.y=1332)
report "***FAILED TEST: c03s02b02x00p02n01i00501 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p02n01i00501arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc501.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p02n01i00501ent IS
END c03s02b02x00p02n01i00501ent;
ARCHITECTURE c03s02b02x00p02n01i00501arch OF c03s02b02x00p02n01i00501ent IS
type rec_type is
record
x : integer;
y : integer;
end record;
BEGIN
TESTING: PROCESS
variable v1 : rec_type;
BEGIN
v1.x := 12;
v1.y := v1.x * 111;
assert NOT(v1.x=12 and v1.y=1332)
report "***PASSED TEST: c03s02b02x00p02n01i00501"
severity NOTE;
assert (v1.x=12 and v1.y=1332)
report "***FAILED TEST: c03s02b02x00p02n01i00501 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p02n01i00501arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nodeController is
port(clk: in std_logic;
grant: in std_logic;
start: in std_logic;
count_in : in unsigned(1 downto 0);
nodeid : in std_logic_vector(1 downto 0);
req:out std_logic;
count_en : out std_logic;
data_out: out std_logic_vector(15 downto 0));
end entity nodeController;
-------------------------------------------------------------------------------
architecture arch of nodeController is
type node_states is (ready,requested,granted,update);
signal state, next_state: node_states;
signal output_enable: std_logic;
begin -- architecture arch
data_out <= (nodeid & '1' & std_logic_vector(count_in) & "000000" & nodeid & '0' & std_logic_vector(count_in)) when (output_enable='1') else (others => 'Z');
process (clk)
begin
if (clk='1' and clk'Event) then
state <= next_state;
end if;
end process;
process (state, start, grant)
begin
case state is
when ready => if start='1' then
next_state <= requested;
else
next_state <= ready;
end if;
when requested => if(grant='1') then
next_state <= granted;
else
next_state <= requested;
end if;
when granted => next_state <= update;
when update => next_state <= ready;
end case;
end process;
process (state)
begin
case state is
when ready => req<='0';output_enable<='0';count_en<='0';
when requested => req<='1';output_enable<='0';count_en<='0';
when granted => req<='0';output_enable<='1';count_en<='0';
when update => req<='0';output_enable<='0';count_en<='1';
end case;
end process;
end architecture arch;
-------------------------------------------------------------------------------
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
uLjt23yh/MM0c4ovvWg4RlBFzakDlTvbZQRcr3o93uu7Vzlu0/BjRNFja8HfCgn6GTpHrmCreVpw
yUYMKEM/LIApThzM5JQyyoy9kJW3KYYqH+ZtvrvZsjEDSeXO8rlRl9tVJ22fIByOYeYIQ8YCn1/u
MOCv3RUnISNAXZzNs6r67f4Hg5x1nMjuPFglQvaBk/+Asva1U30GoKHMbVo4m4sH3wCBdi54ltUb
v+8W5K6DIS2LcMhkRZCb2ylDcNdsUrJCrU6xFzlEGecgNXQEfzKWDKdZoijBg3WQ4ml9HM/RMrjm
8wwDnnn1fKKFtJXf03Z5xujcf6/yPYib6J7Vyq27bM/XFASF6Q/nLgjdPAn3EYSWRQzfAymREWDx
CDntwQ4G7xwraB60rK9IkcY5RzeMVVeJSawaLe8VODZQWJq3/B5KVtU36H8LQfpTAOrcqQsAgb9S
5XmEVqyO67rGA/s/pN49FvF8V97CtvbS7ZX/dXuw6KyySIxYhtgnieZM2G9Dq9XMQbtr02LeHw2r
FmrX7dkK8olOvV5gUR9dWlOCcvDC88tTdn7fz8hScvEonGd9IU4WrQ60mK/266gI6v9VUl+D7k/h
t1GdYvKFX+sQ26/li+GgHzH89vuNR+nFAdXLi5Uc6oh6z0KzHK+ckQPogY2BGI4NvCJCrduowh2b
uzdSgMOXkfvBOdLA1perQQ92P0X/7Xn8t7Wrb00knPD9Q+wuUGxYt9OimZ29j5uQCLr2FdgOgZbF
pCIaQNJxz8/oYcE5sr1l1/QqxWbejOVF/+aR0QTevGP4ZAxrckyf5qtlCi+KEpjhxjQAMlrB1aP8
xiqmqUNQ1lVvNxFlPfIKwoTOHfSPB+TJoy90ELTTLJQa8g3pXGAH+L81wRk4cnEzn2iB6y+7Q85F
ejUb8LuhgRLFS1GqkAf4K53UgW3eLgvjAtP+F+FVi4m18+B5duavc+0QS2UIxFJh3BfxRJjUqnoq
52EYuwA+GqdtFiUOI8qy01Wyztj0779ekxrv8+jRsr1iXSAHrhi4CzyJIolwExQppQAOKsiIilZM
z7BDBCyUjwLfZzU7wiDNtNQ8zb0leBhunyLdH08bS/WcNglvyKiqBRoHZVyVO1RgjGUxnqw3DeYl
XwmLb7taNGEGOT4X7ZIUGPmgXaeBEUYrRRg+aqiwNZq7TV5DnGBGWWnthtPxJwRidjRI0/l42DCN
CyJBGiBL4Ke9ly26CuPa6qxXUerBQZatg4ngID5krWuPghxFnInRMyV6bG+azk6i0KDSyZ9Hoerw
hLjd8AA86+yO1YKoHcaLDmIJgIYH9vL2mYyXsyfBrHkrfHJdlZu5tOOofo6h8wEEUTbRhctMxZln
7pJcPg1iCh8QO43aW/FM2kI+m5vvq04GwMjzGUNZchJam3QlPXsY1Jo3eVRTZUte2TwQoqJMRdm1
8AisoRG3FNkFd6pnuyK27+qLLeFDMUj2w96rIYXn9jruqe1H8+Lg2JoG5fEGx0cX+STB2V7WmIfB
J/E9ph8aprzIxG7Hr6shYXGLWc/twFpGs1jna/KHfCRIh+BwNcOJRBF6JlD0crrpMMb5+ZKB7LTF
+l5IAfQhk3WrWWgejNy2Fd7E/leQAF8XPJ7strq8E7g+CpYW3p+O/uQciSabe06zhu9Ox7bwd7as
KVpISQer8WaTEIAATkSA6GYT6gJj1j6CP0kFDTCDoQwvDzONXUbuhcAk023htn3Ij3ik99KNwBkp
hecNsZjYq2A4DgWldbzADg5sD7zUCogxXPaioS9iH/KrsidUGB9tJTExJCRGFpB/CZGxYdX6izHt
DwvKvWBCWnWdZmESAr9IwaGV/3y0+xW3dgKC60/fiS3usdkscvGhyDKm+HrTKvy42ax/dsB8TjMV
utMPB1oWRPF8QCu2TOITa45Ij377JfjYKEbgMJwZvXulKhmqJNHnrTTfgazSLS/xGw5Zey+hCq+6
5+kU4yuBGSDMTq3FhBKj4QuhigM1/E+c+fLkYoU+bb5Ytg+SrwDoPq8AQ240Jj27MVnJjSgH8bK6
T/RnR11kDk5k9TkQgi6vSYGYaS/h1MedR56c96p4JZD/A569+fGrdz982v5MjEAPMNs501ceDPeA
XtvXRo8JNQeNWoMFd3xAEBXycDm+AW3XjmzvLLeq+wE5fuHsboV+8F4tJ9C69ueralNBrwNDL18m
O9cn11Ap8fGxlCU8z7etj6NaUHj7Ed7Ju3EuFeX9z/YwOgBcRO6Tbbvy8QX+U1GmITfrEjeJhjgr
CdsLG1woZO7mVfygjUjstPuAftEgXH2KlnOeMnOegIk17XlT6PnE4HbCvlGEssjCet4R/is0Ez8q
6V4Gx1dZY3WJXbLuT8iBXFGYghYfhYj/KL7M30qwWh/HnLREOfah6nOT4rIocHKaw4Oy6cdEYWsI
yd3gWhFIsGEafZE+/V/WQlIZQs1oEBBH69N/pPqnSouk0z8bdjquPkkCu/DyOLqesMaDSno4C+Xd
vG+MlcVGTn+3M/3RVVvnJ3e/Zs3I2m1Yxm+KqVIN4DYEvX4Og2mCFOqsZZZNFF5Bb1FJU1iuO1S4
t5GcjPIid/f6ocq3uqka0QnK+zTm4QsnDLyO1DHr/FtIRXQkPiXmqlghWO2ERrD3iDo1BpQDY3Q2
cK2XvrFjw0dSEGBzw+nMiIwKPOwXgPJZG2CGDWuD/1JjUry3K4z+hjdbACmbAziuS3pzbIXx3chZ
jHFj2ZFTn/c7LZregJ0iiG8HxblbmwaBYXBOsjNNUL2IzYoeUlG0ToOveeHWVzSKQFG+BHHY92rD
RWUD+cJ0M9gethSy3xPZt/DLkpe/HmioJZ1IZ6G1W25f6aMjLLZAyjWDqstufZiI0EnWDOm3l3VJ
GgxOR13QA0NUsZvh4pGyI3TbRdvWdWvJrJ8eYM+YWL9p3Z1WTX9tBO6u5olFYDG5OSJeM9MNpGJV
0KrJKQFqTsoyGFl+w9eh3ThUYGmJEbXjGmPURg6ZZGQ9x+Gpf06Q86IiTYZUcAy802THIVGXzOEn
5VXLDvgb7zmd7csdDhidCphgEcH6P8PjZfGyXBqtR61MTWpyMa5Mj47Ngi7jzzXasl8cfw6Q+KDK
g1Qv16i2Ghg0aSLCob+/6K2/lUjx3gdFsBjjKDkrkATpy16vm4iB45BEK3+gGovRlMb9KQK6qAHS
Z2l2R+n8w5pVMXl6Oni062C8wTC5n+pMtygAwZEETcJTB2zdA5p+gSSrQWiOJ/4s2lZ/fCBZl5AK
zUISAI9GHr2boNyrJ9zhb2hWHARK+xPuOGVs9M/OX/joggcTRd5szf+P4Fxf8c6cRo+4Ukb/hnwn
uP8b7a0Y27pGyaCqwQ287+YdMLJL6hLX/7Pq5vnfAuXIX24nCkoNaEMY6DgEt6V7lIdpSmtFuy8R
9BjpV4y0hJbHtnR5BR0Mff2rQhCO1TwRUpG53ah5CjG6vF5DZpy4eCeUKAYLKcrjHE8tC6froqYy
KDPoFrNZJHsZpFdfLIuPlk2Fn6cZpvclopCnJQ54AkNsr4jqhl5ig3qHIKZfbQiT0J79/wMc4jZE
zG7x8xPiOeKYvvYoIrkoG16Gl5bevXIBKnpQGrCWlsWzICe+Xp7y4hkFs51hq4hMd1CWV9gGFLYO
kV9NOH9y0Y2LUK5RZtzsozFiA9YB0fanUOlV5NvJ2z1qan8UL+6mrtKFYqJzA/4ryxKpkOqRPM7x
L4P/5NWvsCXGs43Nl6e83kjpHm3767pzAGZzNgCru9IMBPvGYLVXeWQDifn4kLoe1Vj1gBsUw39s
IH3pHHVgQg9ybQKVo9dcgh4/XUkbnoXH5Q061yygh0fg9OtfVSacGsR+QxfXu9ay5BuNnVioT2vX
Clvo5418AJ+SRnSgjV6IU6Wv/4ksLLRmPb6RytwoPdcYugXP32ng6wK2A9UEANK3hm1bMkR1uU1L
QMj7c2eOd0HHrJ2G52/lYsWn6SnGXSiQ6GVkDwUIFDfckmFDFb+aKaa/SmueprjIc2ATPLW7KUQe
jmjonXdZXGFExOvFG+RRwbK21JZ+oiSfrQ+IpTDTYzmQUjFq01rzOOobrGSwn0xmW2tW0A0zIHVJ
B5AwxNbW67WccVhZrCDgO14y9B2mFnIGRAEKcBb4grR9X1LHfLE+6N109gYSq7WCqHtmbm8ROCwC
ed3xzN4taeLq90CkUWDjxxl+TNaAKC3Vr2CBk7/eajE+zKu6U18Csq14gulTWOkY5xyJwg05ss5X
2sYTYA2eEjYPFa+nMQ6C28QjQBAfIo2SpARjwlaxsnEGTOw7sW2pUMRfP3gycIGN6KPcYF5z/GnT
X6mngjtfTAJjoouHQOvP8Byj2B9xiz2Go3n4+3UZkZsSVwxNp4XW3Q4brDGxLlzgK9KNBnROtITs
PY97tllFNMXJei+GlFnxuK7mWvwPZVjJd+nXeeJM1p1ZuXlirs37Ysa2a7RpC7hZ3iBdgzQQi+6a
bZgNqTjDMkQG9y/Ioe5RdFogwlXGgaErgldlPO7O2g6oSm1ovzc0nVUzFq/xxg0VZ6K20Z0a9KUO
0+6hRdoyfTX8BQ3zcof6k08lrk23wLTp2hK+8f9ZtvDdCF8TY83z62PrkkSjKLFRHr31tFkhazOa
MI8zH5HaXriEyyvKHh4Jj2D65G/e769HWKvx4aFRU/sdPtxoY1OjniSr3Vp/HrygI8dgiek7FWeZ
fH6wYKgrUwt01MM3tlkLJTKAb3xg5pUNvFQTPWz/2ApYvOGTE1s4xMge/reMX8eFazZZ9NLYIbbn
cQHKTeRI44YI2If7JC6qJd3ITQ6YYZRm3xWtQF9actqmyRcnzlErnw2pxrLdTUAKA0W2AN+MQMTb
muY4UUNjXBriyXsZp24uNkIDtWKz7bq3mAh45XGXIsus2Wzl1w9Cbzby+DKtypwxVRft934zhWgP
iY7dMyrMFGMLyw1PtCR+c9bNrXNeoJQR9vR9ro4Eo6GtgqQm5FMiDYwEEnHbzb8+b/8ho6Bg/Ook
zV5ALZOxU2Uk9krB3fT4RX7d1fqQyJOxO333TCxnDZHXt2vQTfXGFJ5JAqReufIigdVnzvoiHlDZ
HYUIM8EmW4b14UNy7UVzg3oO6of1JziPSAgmUv3B2uQofPl3CjVdBLMcdYrrvSOGcXrLxZgFf8IO
73Nrk0Cz2BOrI9Y3syQr/R2cjGO3e9BFAXESVbvMZHPI7vHnsmeqwuwn/sni3f1w2EQ6ej+dmCKn
M5D6jt92WjhQXAdMuvAEBBmWKP4Jk7j96B1uJTleDzfP/ac2cN5m1Dlp0/JUfwPll21Rpnuqc63J
VFYu5VCGDaLWwxXmGM0epxU6cTwp2C8Rf3uf6SeQr7vdXlC8YtgyjKrrR+YXU0uE5b1s057WSbtE
o9v0kjDJLwkGodiKPygdjBu1I2jL2IGZfrHPWSbKovfn0igbfrSQic2zsybqWlVP5ojPuzR7geGU
F5v9e3t//BIdwCgKFApn9dx0E0ESA6l4uLXJ5+98KukIY4EeLT8vZah4fnTzaDqrCrgcUAnvuonB
gx/9oic74HSSlMYsvei/kTtXUCwBROMyFCLceaMpCokZhXx2iUNP5LiL80BCIZY8Nc88MoYodzCK
HJDbAFUVu1REEh+/EMwR9En4OhLsr6WEDLMuZ14O2iLLprC7suqIl6VVJAv9IUmM53ZaF4LvfKau
XKeee7fNzwYfzskRXF8c9KouZMkjZywNb4r2dKVeQb2zU27s13rjZTgx/5eTcUjFMV4S6bPGJ2ZQ
IVxxiFzwsWcY4Cbx7Fu4DotN/oqL8RVh5lT+XodsJCM1AoZPkJYklw8uVR2GR7l0wG3F/BwImvur
ENhBR4qb8UAZB85BshufvXTCAPtYlB4chT4IPnEZVpjWiK84nFeKKeCAzAfqh7AAjeGPWw/WMVA7
F645AfSLARNkvSDn7zmul9emsfL8BOEXlpOF/L1nUTczV199qCwfo3jNquvVWDPFqvTmqPB8sTnW
uNU9fzCp50HM2Ui+IzvdQBxv48sLDj541XFVcfnw8dOiY0arafTtnWKG41EjGSsEUO5HXrsPeMcz
anMLC350HUMkPBtvQVUF/qMgjGfsfMU4FxURBhD+ojTvIZSHUONilGH8THM3rzXHx9a5exugANjS
0YxI8zqLWB6rS9vg4xFipTAcg228zDIN8Y/IjRWkyWl5XWPEuVVDVkduRDzJVxlr7fmR879nKs9S
k9qyHXHNIdpWUY2dopQQlhGahmppm//8em0Z0J3KY9YPHuOMP+r3iA/9A4sJZs0ZPHIpxQ/4tz05
M+Ja23Q5b9JYD3ZBr5xWJAWVlWhFaGCjYA13gPJPc2qiu0bngBTsUchzE1rchp1c0gScpxs=
`protect end_protected
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.