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------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
faultify_clk_slow_out : out std_logic;
s_axis_aresetn : in std_logic;
-- AXI IFACE
resultvector_o : out std_logic_vector(numOut-1 downto 0);
resultvector_f : out std_logic_vector(numOut-1 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component faultify_top is
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
aclk : in std_logic;
arst_n : in std_logic;
clk : in std_logic;
clk_x32 : in std_logic;
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0);
resultvector_o_p : out std_logic_vector(numOut-1 downto 0);
resultvector_f_p : out std_logic_vector(numOut-1 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
s_axis_aresetn : in std_logic
);
end component faultify_top;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal register_write_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_read_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_write_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal register_read_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal faultify_read_valid : std_logic;
signal faultify_read_address_valid : std_logic;
signal faultify_read_address : std_logic_vector(31 downto 0);
signal faultify_write_valid : std_logic;
signal counter, divide : integer := 0;
signal faultify_clk_slow_i : std_logic;
begin
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= faultify_read_valid;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
register_write_data <= (others => '0');
register_write_address <= (others => '0');
faultify_write_valid <= '0';
else
faultify_write_valid <= slv_write_ack;
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(0, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(1, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(2, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(3, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(4, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(5, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(6, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(7, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(8, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(9, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(10, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(11, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(12, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(13, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(14, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(15, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(16, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(17, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(18, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(19, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(20, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(21, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(22, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(23, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(24, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(25, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(26, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(27, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(28, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(29, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(30, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(31, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process(slv_reg_read_sel, faultify_read_valid) is
begin
faultify_read_address_valid <= '1';
case slv_reg_read_sel is
when "10000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(0, 32));
when "01000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(1, 32));
when "00100000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(2, 32));
when "00010000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(3, 32));
when "00001000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(4, 32));
when "00000100000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(5, 32));
when "00000010000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(6, 32));
when "00000001000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(7, 32));
when "00000000100000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(8, 32));
when "00000000010000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(9, 32));
when "00000000001000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(10, 32));
when "00000000000100000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(11, 32));
when "00000000000010000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(12, 32));
when "00000000000001000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(13, 32));
when "00000000000000100000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(14, 32));
when "00000000000000010000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(15, 32));
when "00000000000000001000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(16, 32));
when "00000000000000000100000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(17, 32));
when "00000000000000000010000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(18, 32));
when "00000000000000000001000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(19, 32));
when "00000000000000000000100000000000" => faultify_read_address <= std_logic_vector(to_unsigned(20, 32));
when "00000000000000000000010000000000" => faultify_read_address <= std_logic_vector(to_unsigned(21, 32));
when "00000000000000000000001000000000" => faultify_read_address <= std_logic_vector(to_unsigned(22, 32));
when "00000000000000000000000100000000" => faultify_read_address <= std_logic_vector(to_unsigned(23, 32));
when "00000000000000000000000010000000" => faultify_read_address <= std_logic_vector(to_unsigned(24, 32));
when "00000000000000000000000001000000" => faultify_read_address <= std_logic_vector(to_unsigned(25, 32));
when "00000000000000000000000000100000" => faultify_read_address <= std_logic_vector(to_unsigned(26, 32));
when "00000000000000000000000000010000" => faultify_read_address <= std_logic_vector(to_unsigned(27, 32));
when "00000000000000000000000000001000" => faultify_read_address <= std_logic_vector(to_unsigned(28, 32));
when "00000000000000000000000000000100" => faultify_read_address <= std_logic_vector(to_unsigned(29, 32));
when "00000000000000000000000000000010" => faultify_read_address <= std_logic_vector(to_unsigned(30, 32));
when "00000000000000000000000000000001" => faultify_read_address <= std_logic_vector(to_unsigned(31, 32));
when others => faultify_read_address <= (others => '0');
faultify_read_address_valid <= '0';
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= register_read_data when faultify_read_valid = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-----------------------------------------------------------------------------
-- clock divider 32 -> 1
-----------------------------------------------------------------------------
divide <= 32;
process(Bus2IP_Clk, Bus2IP_Resetn)
begin
if Bus2IP_Resetn = '0' then
counter <= 0;
faultify_clk_slow_i <= '0';
elsif(rising_edge(Bus2IP_Clk)) then
if(counter < divide/2-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '1';
else
faultify_clk_slow_i <= '0';
counter <= 0;
end if;
end if;
end process;
faultify_clk_slow_out <= faultify_clk_slow_i;
faultify_top_1 : faultify_top
generic map (
numInj => numInj,
numIn => numIn,
numOut => numOut)
port map (
aclk => Bus2IP_Clk,
arst_n => Bus2IP_Resetn,
clk => faultify_clk_slow_i,
clk_x32 => Bus2IP_Clk,
awvalid => faultify_write_valid,
awaddr => register_write_address,
wvalid => faultify_write_valid,
wdata => register_write_data,
arvalid => faultify_read_address_valid,
araddr => faultify_read_address,
rvalid => faultify_read_valid,
rdata => register_read_data,
resultvector_o_p => resultvector_o,
resultvector_f_p => resultvector_f,
testvector => testvector,
s_axis_aresetn => s_axis_aresetn
);
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
faultify_clk_slow_out : out std_logic;
s_axis_aresetn : in std_logic;
-- AXI IFACE
resultvector_o : out std_logic_vector(numOut-1 downto 0);
resultvector_f : out std_logic_vector(numOut-1 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component faultify_top is
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
aclk : in std_logic;
arst_n : in std_logic;
clk : in std_logic;
clk_x32 : in std_logic;
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0);
resultvector_o_p : out std_logic_vector(numOut-1 downto 0);
resultvector_f_p : out std_logic_vector(numOut-1 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
s_axis_aresetn : in std_logic
);
end component faultify_top;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal register_write_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_read_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_write_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal register_read_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal faultify_read_valid : std_logic;
signal faultify_read_address_valid : std_logic;
signal faultify_read_address : std_logic_vector(31 downto 0);
signal faultify_write_valid : std_logic;
signal counter, divide : integer := 0;
signal faultify_clk_slow_i : std_logic;
begin
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= faultify_read_valid;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
register_write_data <= (others => '0');
register_write_address <= (others => '0');
faultify_write_valid <= '0';
else
faultify_write_valid <= slv_write_ack;
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(0, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(1, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(2, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(3, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(4, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(5, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(6, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(7, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(8, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(9, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(10, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(11, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(12, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(13, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(14, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(15, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(16, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(17, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(18, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(19, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(20, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(21, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(22, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(23, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(24, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(25, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(26, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(27, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(28, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(29, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(30, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(31, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process(slv_reg_read_sel, faultify_read_valid) is
begin
faultify_read_address_valid <= '1';
case slv_reg_read_sel is
when "10000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(0, 32));
when "01000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(1, 32));
when "00100000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(2, 32));
when "00010000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(3, 32));
when "00001000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(4, 32));
when "00000100000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(5, 32));
when "00000010000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(6, 32));
when "00000001000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(7, 32));
when "00000000100000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(8, 32));
when "00000000010000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(9, 32));
when "00000000001000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(10, 32));
when "00000000000100000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(11, 32));
when "00000000000010000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(12, 32));
when "00000000000001000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(13, 32));
when "00000000000000100000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(14, 32));
when "00000000000000010000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(15, 32));
when "00000000000000001000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(16, 32));
when "00000000000000000100000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(17, 32));
when "00000000000000000010000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(18, 32));
when "00000000000000000001000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(19, 32));
when "00000000000000000000100000000000" => faultify_read_address <= std_logic_vector(to_unsigned(20, 32));
when "00000000000000000000010000000000" => faultify_read_address <= std_logic_vector(to_unsigned(21, 32));
when "00000000000000000000001000000000" => faultify_read_address <= std_logic_vector(to_unsigned(22, 32));
when "00000000000000000000000100000000" => faultify_read_address <= std_logic_vector(to_unsigned(23, 32));
when "00000000000000000000000010000000" => faultify_read_address <= std_logic_vector(to_unsigned(24, 32));
when "00000000000000000000000001000000" => faultify_read_address <= std_logic_vector(to_unsigned(25, 32));
when "00000000000000000000000000100000" => faultify_read_address <= std_logic_vector(to_unsigned(26, 32));
when "00000000000000000000000000010000" => faultify_read_address <= std_logic_vector(to_unsigned(27, 32));
when "00000000000000000000000000001000" => faultify_read_address <= std_logic_vector(to_unsigned(28, 32));
when "00000000000000000000000000000100" => faultify_read_address <= std_logic_vector(to_unsigned(29, 32));
when "00000000000000000000000000000010" => faultify_read_address <= std_logic_vector(to_unsigned(30, 32));
when "00000000000000000000000000000001" => faultify_read_address <= std_logic_vector(to_unsigned(31, 32));
when others => faultify_read_address <= (others => '0');
faultify_read_address_valid <= '0';
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= register_read_data when faultify_read_valid = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-----------------------------------------------------------------------------
-- clock divider 32 -> 1
-----------------------------------------------------------------------------
divide <= 32;
process(Bus2IP_Clk, Bus2IP_Resetn)
begin
if Bus2IP_Resetn = '0' then
counter <= 0;
faultify_clk_slow_i <= '0';
elsif(rising_edge(Bus2IP_Clk)) then
if(counter < divide/2-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '1';
else
faultify_clk_slow_i <= '0';
counter <= 0;
end if;
end if;
end process;
faultify_clk_slow_out <= faultify_clk_slow_i;
faultify_top_1 : faultify_top
generic map (
numInj => numInj,
numIn => numIn,
numOut => numOut)
port map (
aclk => Bus2IP_Clk,
arst_n => Bus2IP_Resetn,
clk => faultify_clk_slow_i,
clk_x32 => Bus2IP_Clk,
awvalid => faultify_write_valid,
awaddr => register_write_address,
wvalid => faultify_write_valid,
wdata => register_write_data,
arvalid => faultify_read_address_valid,
araddr => faultify_read_address,
rvalid => faultify_read_valid,
rdata => register_read_data,
resultvector_o_p => resultvector_o,
resultvector_f_p => resultvector_f,
testvector => testvector,
s_axis_aresetn => s_axis_aresetn
);
end IMP;
|
library ieee;
use ieee.numeric_bit.all;
entity smul23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (45 downto 0)
);
end entity smul23;
architecture rtl of smul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity smul23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (45 downto 0)
);
end entity smul23;
architecture rtl of smul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity smul23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (45 downto 0)
);
end entity smul23;
architecture rtl of smul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity smul23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (45 downto 0)
);
end entity smul23;
architecture rtl of smul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
uart_0_rxd : in std_logic := 'X'; -- rxd
uart_0_txd : out std_logic; -- txd
ip_pwm_dir : out std_logic_vector(1 downto 0); -- dir
ip_pwm_out : out std_logic_vector(1 downto 0) -- out
);
end component niosii;
u0 : component niosii
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
pio_0_external_connection_export => CONNECTED_TO_pio_0_external_connection_export, -- pio_0_external_connection.export
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
uart_0_rxd => CONNECTED_TO_uart_0_rxd, -- uart_0.rxd
uart_0_txd => CONNECTED_TO_uart_0_txd, -- .txd
ip_pwm_dir => CONNECTED_TO_ip_pwm_dir, -- ip_pwm.dir
ip_pwm_out => CONNECTED_TO_ip_pwm_out -- .out
);
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(13-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 256,
C_DOUT_WIDTH => 32,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 256,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 256,
C_WR_PNTR_WIDTH => 10,
C_RD_PNTR_WIDTH => 13,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : write_data_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(13-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 256,
C_DOUT_WIDTH => 32,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 256,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 256,
C_WR_PNTR_WIDTH => 10,
C_RD_PNTR_WIDTH => 13,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : write_data_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
------------------------------------------------------------------------------------------------------------------------
-- SPI Slave IP-Core
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-09-06 V0.01 First Implementation
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi is
generic (
frameSize_g : integer := 8;
cpol_g : boolean := false;
cpha_g : boolean := false
);
port (
-- Control Interface
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(frameSize_g-1 downto 0);
load : in std_logic; --load din
dout : out std_logic_vector(frameSize_g-1 downto 0);
valid : out std_logic; --dout is valid
-- SPI
sck : in std_logic;
ss : in std_logic;
miso : out std_logic;
mosi : in std_logic
);
end spi;
architecture rtl of spi is
--pulse generation out of spi clock (sck)
signal sckL : std_logic;
signal sckRising : std_logic;
signal sckFalling : std_logic;
signal capPulse : std_logic; --pulse to capture data
signal setPulse : std_logic; --pulse to change data
--capture data
signal capMosi : std_logic;
signal capDout : std_logic_vector(frameSize_g-1 downto 0);
--frame counter
signal cnt : integer range 0 to frameSize_g;
signal tc : std_logic;
signal miso_s : std_logic;
signal din_s : std_logic_vector(frameSize_g-1 downto 0);
begin
miso <= miso_s when ss = '1' else 'Z'; --set miso to high if slave isn't selected!
spiClkShiftReg : process(clk, rst)
begin
if rst = '1' then
if cpol_g = false then
sckL <= '0';
else
sckL <= '1';
end if;
elsif clk = '1' and clk'event then
sckL <= sck;
end if;
end process;
--generate sck rising falling edge pulse
sckRising <= '1' when sckL = '0' and sck = '1' else '0';
sckFalling <= '1' when sckL = '1' and sck = '0' else '0';
capPulse <= '0' when (ss /= '1') else
sckRising when (cpha_g = false and cpol_g = false) else
sckFalling when (cpha_g = false and cpol_g = true) else
sckFalling when (cpha_g = true and cpol_g = false) else
sckRising when (cpha_g = true and cpol_g = true) else
'0';
setPulse <= '0' when (ss /= '1') else
sckFalling when (cpha_g = false and cpol_g = false) else
sckRising when (cpha_g = false and cpol_g = true) else
sckRising when (cpha_g = true and cpol_g = false) else
sckFalling when (cpha_g = true and cpol_g = true) else
'0';
theCapLatch : process(clk, rst)
begin
if rst = '1' then
capMosi <= '0';
elsif clk = '1' and clk'event then
if capPulse = '1' then
--capture mosi data
capMosi <= mosi;
elsif load = '1' and cpha_g = true then
capMosi <= din(0);
end if;
end if;
end process;
theFrameCnt : process(clk, rst)
begin
if rst = '1' then
cnt <= 0;
elsif clk = '1' and clk'event then
if tc = '1' then
cnt <= 0;
elsif capPulse = '1' and cpha_g = true then
cnt <= cnt + 1;
elsif setPulse = '1' and cpha_g = false then
cnt <= cnt + 1;
end if;
end if;
end process;
tc <= '1' when cnt = frameSize_g else '0';
theDoutLatch : process(clk, rst)
begin
if rst = '1' then
dout <= (others => '0');
elsif clk = '1' and clk'event then
valid <= '0';
if tc = '1' then
if cpha_g = false then
dout <= capDout;
else
dout <= capDout(capDout'left-1 downto 0) & capMosi;
end if;
valid <= '1';
end if;
end if;
end process;
dinGenPhaF : if cpha_g = false generate
din_s <= din;
end generate;
dinGenPhaT : if cpha_g = true generate
din_s <= '0' & din(din'left downto 1);
end generate;
theShiftRegister : entity work.spi_sreg
generic map (
size_g => frameSize_g
)
port map (
clk => clk,
rst => rst,
shift => setPulse,
load => load,
din => din_s,
dout => capDout,
sin => capMosi,
sout => miso_s
);
end rtl;
|
------------------------------------------------------------------------------------------------------------------------
-- SPI Slave IP-Core
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-09-06 V0.01 First Implementation
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi is
generic (
frameSize_g : integer := 8;
cpol_g : boolean := false;
cpha_g : boolean := false
);
port (
-- Control Interface
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(frameSize_g-1 downto 0);
load : in std_logic; --load din
dout : out std_logic_vector(frameSize_g-1 downto 0);
valid : out std_logic; --dout is valid
-- SPI
sck : in std_logic;
ss : in std_logic;
miso : out std_logic;
mosi : in std_logic
);
end spi;
architecture rtl of spi is
--pulse generation out of spi clock (sck)
signal sckL : std_logic;
signal sckRising : std_logic;
signal sckFalling : std_logic;
signal capPulse : std_logic; --pulse to capture data
signal setPulse : std_logic; --pulse to change data
--capture data
signal capMosi : std_logic;
signal capDout : std_logic_vector(frameSize_g-1 downto 0);
--frame counter
signal cnt : integer range 0 to frameSize_g;
signal tc : std_logic;
signal miso_s : std_logic;
signal din_s : std_logic_vector(frameSize_g-1 downto 0);
begin
miso <= miso_s when ss = '1' else 'Z'; --set miso to high if slave isn't selected!
spiClkShiftReg : process(clk, rst)
begin
if rst = '1' then
if cpol_g = false then
sckL <= '0';
else
sckL <= '1';
end if;
elsif clk = '1' and clk'event then
sckL <= sck;
end if;
end process;
--generate sck rising falling edge pulse
sckRising <= '1' when sckL = '0' and sck = '1' else '0';
sckFalling <= '1' when sckL = '1' and sck = '0' else '0';
capPulse <= '0' when (ss /= '1') else
sckRising when (cpha_g = false and cpol_g = false) else
sckFalling when (cpha_g = false and cpol_g = true) else
sckFalling when (cpha_g = true and cpol_g = false) else
sckRising when (cpha_g = true and cpol_g = true) else
'0';
setPulse <= '0' when (ss /= '1') else
sckFalling when (cpha_g = false and cpol_g = false) else
sckRising when (cpha_g = false and cpol_g = true) else
sckRising when (cpha_g = true and cpol_g = false) else
sckFalling when (cpha_g = true and cpol_g = true) else
'0';
theCapLatch : process(clk, rst)
begin
if rst = '1' then
capMosi <= '0';
elsif clk = '1' and clk'event then
if capPulse = '1' then
--capture mosi data
capMosi <= mosi;
elsif load = '1' and cpha_g = true then
capMosi <= din(0);
end if;
end if;
end process;
theFrameCnt : process(clk, rst)
begin
if rst = '1' then
cnt <= 0;
elsif clk = '1' and clk'event then
if tc = '1' then
cnt <= 0;
elsif capPulse = '1' and cpha_g = true then
cnt <= cnt + 1;
elsif setPulse = '1' and cpha_g = false then
cnt <= cnt + 1;
end if;
end if;
end process;
tc <= '1' when cnt = frameSize_g else '0';
theDoutLatch : process(clk, rst)
begin
if rst = '1' then
dout <= (others => '0');
elsif clk = '1' and clk'event then
valid <= '0';
if tc = '1' then
if cpha_g = false then
dout <= capDout;
else
dout <= capDout(capDout'left-1 downto 0) & capMosi;
end if;
valid <= '1';
end if;
end if;
end process;
dinGenPhaF : if cpha_g = false generate
din_s <= din;
end generate;
dinGenPhaT : if cpha_g = true generate
din_s <= '0' & din(din'left downto 1);
end generate;
theShiftRegister : entity work.spi_sreg
generic map (
size_g => frameSize_g
)
port map (
clk => clk,
rst => rst,
shift => setPulse,
load => load,
din => din_s,
dout => capDout,
sin => capMosi,
sout => miso_s
);
end rtl;
|
------------------------------------------------------------------------------------------------------------------------
-- SPI Slave IP-Core
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-09-06 V0.01 First Implementation
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi is
generic (
frameSize_g : integer := 8;
cpol_g : boolean := false;
cpha_g : boolean := false
);
port (
-- Control Interface
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(frameSize_g-1 downto 0);
load : in std_logic; --load din
dout : out std_logic_vector(frameSize_g-1 downto 0);
valid : out std_logic; --dout is valid
-- SPI
sck : in std_logic;
ss : in std_logic;
miso : out std_logic;
mosi : in std_logic
);
end spi;
architecture rtl of spi is
--pulse generation out of spi clock (sck)
signal sckL : std_logic;
signal sckRising : std_logic;
signal sckFalling : std_logic;
signal capPulse : std_logic; --pulse to capture data
signal setPulse : std_logic; --pulse to change data
--capture data
signal capMosi : std_logic;
signal capDout : std_logic_vector(frameSize_g-1 downto 0);
--frame counter
signal cnt : integer range 0 to frameSize_g;
signal tc : std_logic;
signal miso_s : std_logic;
signal din_s : std_logic_vector(frameSize_g-1 downto 0);
begin
miso <= miso_s when ss = '1' else 'Z'; --set miso to high if slave isn't selected!
spiClkShiftReg : process(clk, rst)
begin
if rst = '1' then
if cpol_g = false then
sckL <= '0';
else
sckL <= '1';
end if;
elsif clk = '1' and clk'event then
sckL <= sck;
end if;
end process;
--generate sck rising falling edge pulse
sckRising <= '1' when sckL = '0' and sck = '1' else '0';
sckFalling <= '1' when sckL = '1' and sck = '0' else '0';
capPulse <= '0' when (ss /= '1') else
sckRising when (cpha_g = false and cpol_g = false) else
sckFalling when (cpha_g = false and cpol_g = true) else
sckFalling when (cpha_g = true and cpol_g = false) else
sckRising when (cpha_g = true and cpol_g = true) else
'0';
setPulse <= '0' when (ss /= '1') else
sckFalling when (cpha_g = false and cpol_g = false) else
sckRising when (cpha_g = false and cpol_g = true) else
sckRising when (cpha_g = true and cpol_g = false) else
sckFalling when (cpha_g = true and cpol_g = true) else
'0';
theCapLatch : process(clk, rst)
begin
if rst = '1' then
capMosi <= '0';
elsif clk = '1' and clk'event then
if capPulse = '1' then
--capture mosi data
capMosi <= mosi;
elsif load = '1' and cpha_g = true then
capMosi <= din(0);
end if;
end if;
end process;
theFrameCnt : process(clk, rst)
begin
if rst = '1' then
cnt <= 0;
elsif clk = '1' and clk'event then
if tc = '1' then
cnt <= 0;
elsif capPulse = '1' and cpha_g = true then
cnt <= cnt + 1;
elsif setPulse = '1' and cpha_g = false then
cnt <= cnt + 1;
end if;
end if;
end process;
tc <= '1' when cnt = frameSize_g else '0';
theDoutLatch : process(clk, rst)
begin
if rst = '1' then
dout <= (others => '0');
elsif clk = '1' and clk'event then
valid <= '0';
if tc = '1' then
if cpha_g = false then
dout <= capDout;
else
dout <= capDout(capDout'left-1 downto 0) & capMosi;
end if;
valid <= '1';
end if;
end if;
end process;
dinGenPhaF : if cpha_g = false generate
din_s <= din;
end generate;
dinGenPhaT : if cpha_g = true generate
din_s <= '0' & din(din'left downto 1);
end generate;
theShiftRegister : entity work.spi_sreg
generic map (
size_g => frameSize_g
)
port map (
clk => clk,
rst => rst,
shift => setPulse,
load => load,
din => din_s,
dout => capDout,
sin => capMosi,
sout => miso_s
);
end rtl;
|
-- *********************************************************************
-- Copyright 2011, ON Semiconductor Corporation.
--
-- This software is owned by ON Semiconductor Corporation (ON)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of ON.
--
-- Disclaimer: ON makes no warranty of any kind, express or
-- implied, with regard to this material, including, but not limited to,
-- the implied warranties of merchantability and fitness for a particular
-- purpose. ON reserves the right to make changes without further
-- notice to the materials described herein. ON does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. ON's products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the ON Software License Agreement.
--
-- *********************************************************************
-- File : $URL: http://whatever.euro.cypress.com/repos/ff_te/VHDL/LIB/modules/Iserdes/trunk/iserdes_compare.vhd $
-- Author : $Author: bert.dewil $
-- Department : CISP
-- Date : $Date: 2011-04-18 15:49:57 +0200 (ma, 18 apr 2011) $
-- Revision : $Revision: 903 $
-- *********************************************************************
-- Description
--
-- *********************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
library unisim;
use unisim.vcomponents.all;
entity iserdes_compare is
generic(
NROF_CONN : integer
);
port(
CLOCK : in std_logic;
CLKDIV : in std_logic;
RESET : in std_logic;
FIFO_EN : in std_logic;
SAMPLEINFIRSTBIT : in std_logic_vector(NROF_CONN-1 downto 0);
SAMPLEINLASTBIT : in std_logic_vector(NROF_CONN-1 downto 0);
SAMPLEINOTHERBIT : in std_logic_vector(NROF_CONN-1 downto 0);
SKEW_ERROR : out std_logic;
FIFO_WREN : out std_logic;
DELAY_WREN : out std_logic
);
end iserdes_compare;
architecture rtl of iserdes_compare is
signal FIRSTBIT_OR : std_logic;
signal LASTBIT_OR : std_logic;
signal OTHERBIT_OR : std_logic;
signal DELAY_WREN_r : std_logic;
signal DELAY_WREN_r2 : std_logic;
signal FIFO_WREN_r2 : std_logic;
begin
-- OR'ed status
process (SAMPLEINFIRSTBIT)
variable TMP : std_logic;
begin
TMP := '0';
for I in SAMPLEINFIRSTBIT'low to SAMPLEINFIRSTBIT'high loop
TMP := TMP or SAMPLEINFIRSTBIT(I);
end loop;
FIRSTBIT_OR <= TMP;
end process;
process (SAMPLEINLASTBIT)
variable TMP : std_logic;
begin
TMP := '0';
for I in SAMPLEINLASTBIT'low to SAMPLEINLASTBIT'high loop
TMP := TMP or SAMPLEINLASTBIT(I);
end loop;
LASTBIT_OR <= TMP;
end process;
process (SAMPLEINOTHERBIT)
variable TMP : std_logic;
begin
TMP := '0';
for I in SAMPLEINOTHERBIT'low to SAMPLEINOTHERBIT'high loop
TMP := TMP or SAMPLEINOTHERBIT(I);
end loop;
OTHERBIT_OR <= TMP;
end process;
delayselector: process(RESET, CLOCK)
variable orstatus : std_logic_vector(2 downto 0);
begin
if (RESET = '1') then
SKEW_ERROR <= '0';
DELAY_WREN_r <= '0';
elsif (CLOCK'event and CLOCK = '1') then
orstatus := OTHERBIT_OR & LASTBIT_OR & FIRSTBIT_OR;
case orstatus is
when "000" => --not yet trained 0
SKEW_ERROR <= '0';
DELAY_WREN_r <= '0';
when "001" => --all samples in first bit 1
SKEW_ERROR <= '0';
DELAY_WREN_r <= '0';
when "010" => --all samples in last bit 2
SKEW_ERROR <= '0';
DELAY_WREN_r <= '0';
when "100" => --all samples in other bit 4
SKEW_ERROR <= '0';
DELAY_WREN_r <= '0';
when "101" => --samples in first & other 5
SKEW_ERROR <= '0';
DELAY_WREN_r <= '0';
when "110" => --samples in lastt & other 6
SKEW_ERROR <= '0';
DELAY_WREN_r <= '0';
when "011" => --samples in first & last 3
-- use special fifo enable to compensate word skew
SKEW_ERROR <= '0';
DELAY_WREN_r <= '1';
when "111" => --unsupported, too much skew 7
SKEW_ERROR <= '1';
DELAY_WREN_r <= '0';
when others =>
SKEW_ERROR <= '0';
DELAY_WREN_r <= '0';
end case;
end if;
end process delayselector;
clockdomaincrossing: process(RESET, CLKDIV)
begin
if (RESET = '1') then
DELAY_WREN_r2 <= '0';
DELAY_WREN <= '0';
FIFO_WREN <= '0';
FIFO_WREN_r2 <= '0';
elsif (CLKDIV'event and CLKDIV = '1') then
DELAY_WREN_r2 <= DELAY_WREN_r;
DELAY_WREN <= DELAY_WREN_r2;
FIFO_WREN_r2 <= FIFO_EN;
FIFO_WREN <= FIFO_WREN_r2;
end if;
end process clockdomaincrossing;
end rtl; |
library ieee;
use ieee.std_logic_1164.all;
entity system_timing is
generic (
TIMESTAMP_COUNTER_MAX: integer := 1000
);
port (
clock_50MHz : in std_logic;
reset : in std_logic;
time_base_50_ms_out: out std_logic;
elapsed_time_out: out integer range 0 to TIMESTAMP_COUNTER_MAX
);
end;
architecture rtl of system_timing is
constant COUNTER_50_MS_MAX: integer := 50_000_000 / 20; -- 100 ms / 20 ns
signal counter_50_ms: integer range 0 to COUNTER_50_MS_MAX;
signal time_base_50_ms: std_logic;
signal elapsed_time: integer range 0 to TIMESTAMP_COUNTER_MAX;
begin
elapsed_time_out <= elapsed_time;
time_base_50_ms_out <= time_base_50_ms;
process (clock_50MHz, reset) begin
if reset then
time_base_50_ms <= '0';
counter_50_ms <= 0;
elsif rising_edge(clock_50MHz) then
if counter_50_ms < COUNTER_50_MS_MAX then
counter_50_ms <= counter_50_ms + 1;
time_base_50_ms <= '0';
else
counter_50_ms <= 0;
time_base_50_ms <= '1';
end if;
end if;
end process;
process (clock_50MHz, reset) begin
if reset then
elapsed_time <= 0;
elsif rising_edge(clock_50MHz) then
if time_base_50_ms then
elapsed_time <= elapsed_time + 1;
end if;
end if;
end process;
end;
|
package pack is
type rec is record
x : integer;
y : bit_vector;
end record;
type rec_array is array (natural range <>) of rec;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
i : in rec_array;
o1 : out integer_vector;
o2 : out bit_vector );
end entity;
architecture test of sub is
begin
g: for n in i'range generate
constant stride : natural := i(n).y'length;
begin
o1(n) <= i(n).x;
o2(1 + (n-1)*stride to n*stride) <= i(n).y;
end generate;
end architecture;
-------------------------------------------------------------------------------
use work.pack.all;
entity elab33 is
end entity;
architecture test of elab33 is
signal a : rec_array(1 to 2)(y(1 to 3));
signal b : integer_vector(1 to 2);
signal c : bit_vector(1 to 6);
begin
u : entity work.sub
port map ( a, b, c );
check: process is
begin
a(1) <= (y => "101", x => 2);
wait for 1 ns;
assert b = (2, integer'left);
assert c = "101000";
a(2).x <= 5;
a(2).y <= "110";
wait for 1 ns;
assert b = (2, 5);
assert c = "101110";
wait;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahb_apb
-- File: spi2ahb_apb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- This entity provides an APB interface for setting defining the
-- AHB address window that can be accessed from SPI.
-- See spi2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.spi.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.conv_std_logic;
use grlib.stdlib.conv_std_logic_vector;
entity spi2ahb_apb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end entity spi2ahb_apb;
architecture rtl of spi2ahb_apb is
-- Register offsets
constant CTRL_OFF : std_logic_vector(4 downto 2) := "000";
constant STS_OFF : std_logic_vector(4 downto 2) := "001";
constant ADDR_OFF : std_logic_vector(4 downto 2) := "010";
constant MASK_OFF : std_logic_vector(4 downto 2) := "011";
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SPI2AHB, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type apb_reg_type is record
spi2ahbi : spi2ahb_in_type;
irq : std_ulogic;
irqen : std_ulogic;
prot : std_ulogic;
protx : std_ulogic;
wr : std_ulogic;
dma : std_ulogic;
dmax : std_ulogic;
end record;
signal r, rin : apb_reg_type;
signal spi2ahbo : spi2ahb_out_type;
begin
bridge : spi2ahbx
generic map (hindex => hindex, oepol => oepol, filter => filter,
cpol => cpol, cpha => cpha)
port map (rstn => rstn, clk => clk, ahbi => ahbi, ahbo => ahbo,
spii => spii, spio => spio, spi2ahbi => r.spi2ahbi,
spi2ahbo => spi2ahbo);
comb: process (r, rstn, apbi, spi2ahbo)
variable v : apb_reg_type;
variable apbaddr : std_logic_vector(4 downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable irqout : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; apbaddr := apbi.paddr(apbaddr'range); apbout := (others => '0');
v.irq := '0'; irqout := (others => '0'); irqout(pirq) := r.irq;
v.protx := spi2ahbo.prot; v.dmax := spi2ahbo.dma;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable) = '1' then
case apbaddr is
when CTRL_OFF => apbout(1 downto 0) := r.irqen & r.spi2ahbi.en;
when STS_OFF => apbout(2 downto 0) := r.prot & r.wr & r.dma;
when ADDR_OFF => apbout := r.spi2ahbi.haddr;
when MASK_OFF => apbout := r.spi2ahbi.hmask;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when CTRL_OFF => v.irqen := apbi.pwdata(1); v.spi2ahbi.en := apbi.pwdata(0);
when STS_OFF => v.dma := r.dma and not apbi.pwdata(0);
v.prot := r.prot and not apbi.pwdata(2);
when ADDR_OFF => v.spi2ahbi.haddr := apbi.pwdata;
when MASK_OFF => v.spi2ahbi.hmask := apbi.pwdata;
when others => null;
end case;
end if;
-- interrupt and status register handling
if ((spi2ahbo.dma and not r.dmax) or
(spi2ahbo.prot and not r.protx)) = '1' then
v.dma := '1'; v.prot := r.prot or spi2ahbo.prot; v.wr := spi2ahbo.wr;
if (r.irqen and not r.dma) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- reset
---------------------------------------------------------------------------
if rstn = '0' then
v.spi2ahbi.en := conv_std_logic(resen = 1);
v.spi2ahbi.haddr := conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
v.spi2ahbi.hmask := conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
v.irqen := '0'; v.prot := '0'; v.wr := '0'; v.dma := '0';
end if;
---------------------------------------------------------------------------
-- signal assignments
---------------------------------------------------------------------------
-- update registers
rin <= v;
-- update outputs
apbo.prdata <= apbout;
apbo.pirq <= irqout;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
end process comb;
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message provided in spi2ahbx...
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_662 is
port (
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
eq : out std_logic
);
end cmp_662;
architecture augh of cmp_662 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_662 is
port (
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
eq : out std_logic
);
end cmp_662;
architecture augh of cmp_662 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_662 is
port (
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
eq : out std_logic
);
end cmp_662;
architecture augh of cmp_662 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : DRAM model
-------------------------------------------------------------------------------
-- File : dram_model_8.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple DRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.tl_string_util_pkg.all;
entity dram_model_8 is
generic (
g_given_name : string;
g_cas_latency : positive := 2;
g_burst_len_r : positive := 1;
g_burst_len_w : positive := 1;
g_column_bits : positive := 10;
g_row_bits : positive := 13;
g_bank_bits : positive := 2 );
port (
CLK : in std_logic;
CKE : in std_logic;
A : in std_logic_vector(g_row_bits-1 downto 0);
BA : in std_logic_vector(g_bank_bits-1 downto 0);
CSn : in std_logic;
RASn : in std_logic;
CASn : in std_logic;
WEn : in std_logic;
DQM : in std_logic;
DQ : inout std_logic_vector(7 downto 0) );
end dram_model_8;
architecture bfm of dram_model_8 is
shared variable this : h_mem_object;
signal bound : boolean := false;
signal command : std_logic_vector(2 downto 0);
constant c_banks : integer := 2 ** g_bank_bits;
type t_row_array is array(0 to c_banks-1) of std_logic_vector(g_row_bits-1 downto 0);
signal bank_rows : t_row_array;
signal bank : integer;
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
signal r_queue : t_byte_array(0 to g_cas_latency + g_burst_len_r) := (others => (others => 'Z'));
-- constant c_col : integer := 0;
-- constant c_bank : integer := g_column_bits;
-- constant c_row : integer := g_column_bits + g_bank_bits;
begin
bind: process
begin
register_mem_model(dram_model_8'path_name, g_given_name, this);
bound <= true;
wait;
end process;
command <= WEn & CASn & RASn;
bank <= to_integer(unsigned(BA));
DQ <= transport r_queue(0) after 6 ns;
process(CLK)
variable raddr : std_logic_vector(31 downto 0) := (others => '0');
variable waddr : std_logic_vector(31 downto 0) := (others => '0');
variable more_writes : integer := 0;
function map_address(bank_bits : std_logic_vector(g_bank_bits-1 downto 0);
row_bits : std_logic_vector(g_row_bits-1 downto 0);
col_bits : std_logic_vector(g_column_bits-1 downto 0) ) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0) := (others => '0');
begin
-- mapping used in v5_sdr
--addr_bank <= address_fifo(3 downto 2);
--addr_row <= address_fifo(24 downto 12);
--addr_column <= address_fifo(11 downto 4) & address_fifo(1 downto 0);
ret(g_bank_bits+1 downto 2) := bank_bits;
ret(1 downto 0) := col_bits(1 downto 0);
ret(g_column_bits+g_bank_bits-1 downto g_bank_bits+2) := col_bits(g_column_bits-1 downto 2);
ret(g_bank_bits+g_column_bits+g_row_bits-1 downto g_bank_bits+g_column_bits) := row_bits;
return ret;
end function;
begin
if rising_edge(CLK) then
if bound and CKE='1' then
r_queue <= r_queue(1 to r_queue'high) & ("ZZZZZZZZ");
if more_writes > 0 then
waddr := std_logic_vector(unsigned(waddr) + 1);
if to_integer(unsigned(waddr)) mod g_burst_len_w = 0 then
waddr := std_logic_vector(unsigned(waddr) - g_burst_len_w);
end if;
if DQM='0' then
write_memory_8(this, waddr, DQ);
end if;
more_writes := more_writes - 1;
end if;
if CSn='0' then
case command is
when "110" => -- RAS, register bank address
bank_rows(bank) <= A(g_row_bits-1 downto 0);
when "101" => -- CAS, start read burst
raddr := map_address(BA, bank_rows(bank), A(g_column_bits-1 downto 0));
--raddr(c_bank+g_bank_bits-1 downto c_bank) := BA;
--raddr(c_row+g_row_bits-1 downto c_row) := bank_rows(bank);
--raddr(c_col+g_column_bits-1 downto c_col) := A(g_column_bits-1 downto 0);
--report hstr(BA) & " " & hstr(bank_rows(bank)) & " " & hstr(A) & ": " & hstr(raddr);
for i in 0 to g_burst_len_r-1 loop
r_queue(g_cas_latency-1 + i) <= read_memory_8(this, raddr);
raddr := std_logic_vector(unsigned(raddr) + 1);
if to_integer(unsigned(raddr)) mod g_burst_len_r = 0 then
raddr := std_logic_vector(unsigned(raddr) - g_burst_len_r);
end if;
end loop;
when "001" => -- CAS & WE, start write burst
waddr := map_address(BA, bank_rows(bank), A(g_column_bits-1 downto 0));
--waddr(c_bank+g_bank_bits-1 downto c_bank) := BA;
--waddr(c_row+g_row_bits-1 downto c_row) := bank_rows(bank);
--waddr(c_col+g_column_bits-1 downto c_col) := A(g_column_bits-1 downto 0);
more_writes := g_burst_len_w - 1;
if DQM='0' then
write_memory_8(this, waddr, DQ);
end if;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
end bfm;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : DRAM model
-------------------------------------------------------------------------------
-- File : dram_model_8.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple DRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.tl_string_util_pkg.all;
entity dram_model_8 is
generic (
g_given_name : string;
g_cas_latency : positive := 2;
g_burst_len_r : positive := 1;
g_burst_len_w : positive := 1;
g_column_bits : positive := 10;
g_row_bits : positive := 13;
g_bank_bits : positive := 2 );
port (
CLK : in std_logic;
CKE : in std_logic;
A : in std_logic_vector(g_row_bits-1 downto 0);
BA : in std_logic_vector(g_bank_bits-1 downto 0);
CSn : in std_logic;
RASn : in std_logic;
CASn : in std_logic;
WEn : in std_logic;
DQM : in std_logic;
DQ : inout std_logic_vector(7 downto 0) );
end dram_model_8;
architecture bfm of dram_model_8 is
shared variable this : h_mem_object;
signal bound : boolean := false;
signal command : std_logic_vector(2 downto 0);
constant c_banks : integer := 2 ** g_bank_bits;
type t_row_array is array(0 to c_banks-1) of std_logic_vector(g_row_bits-1 downto 0);
signal bank_rows : t_row_array;
signal bank : integer;
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
signal r_queue : t_byte_array(0 to g_cas_latency + g_burst_len_r) := (others => (others => 'Z'));
-- constant c_col : integer := 0;
-- constant c_bank : integer := g_column_bits;
-- constant c_row : integer := g_column_bits + g_bank_bits;
begin
bind: process
begin
register_mem_model(dram_model_8'path_name, g_given_name, this);
bound <= true;
wait;
end process;
command <= WEn & CASn & RASn;
bank <= to_integer(unsigned(BA));
DQ <= transport r_queue(0) after 6 ns;
process(CLK)
variable raddr : std_logic_vector(31 downto 0) := (others => '0');
variable waddr : std_logic_vector(31 downto 0) := (others => '0');
variable more_writes : integer := 0;
function map_address(bank_bits : std_logic_vector(g_bank_bits-1 downto 0);
row_bits : std_logic_vector(g_row_bits-1 downto 0);
col_bits : std_logic_vector(g_column_bits-1 downto 0) ) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0) := (others => '0');
begin
-- mapping used in v5_sdr
--addr_bank <= address_fifo(3 downto 2);
--addr_row <= address_fifo(24 downto 12);
--addr_column <= address_fifo(11 downto 4) & address_fifo(1 downto 0);
ret(g_bank_bits+1 downto 2) := bank_bits;
ret(1 downto 0) := col_bits(1 downto 0);
ret(g_column_bits+g_bank_bits-1 downto g_bank_bits+2) := col_bits(g_column_bits-1 downto 2);
ret(g_bank_bits+g_column_bits+g_row_bits-1 downto g_bank_bits+g_column_bits) := row_bits;
return ret;
end function;
begin
if rising_edge(CLK) then
if bound and CKE='1' then
r_queue <= r_queue(1 to r_queue'high) & ("ZZZZZZZZ");
if more_writes > 0 then
waddr := std_logic_vector(unsigned(waddr) + 1);
if to_integer(unsigned(waddr)) mod g_burst_len_w = 0 then
waddr := std_logic_vector(unsigned(waddr) - g_burst_len_w);
end if;
if DQM='0' then
write_memory_8(this, waddr, DQ);
end if;
more_writes := more_writes - 1;
end if;
if CSn='0' then
case command is
when "110" => -- RAS, register bank address
bank_rows(bank) <= A(g_row_bits-1 downto 0);
when "101" => -- CAS, start read burst
raddr := map_address(BA, bank_rows(bank), A(g_column_bits-1 downto 0));
--raddr(c_bank+g_bank_bits-1 downto c_bank) := BA;
--raddr(c_row+g_row_bits-1 downto c_row) := bank_rows(bank);
--raddr(c_col+g_column_bits-1 downto c_col) := A(g_column_bits-1 downto 0);
--report hstr(BA) & " " & hstr(bank_rows(bank)) & " " & hstr(A) & ": " & hstr(raddr);
for i in 0 to g_burst_len_r-1 loop
r_queue(g_cas_latency-1 + i) <= read_memory_8(this, raddr);
raddr := std_logic_vector(unsigned(raddr) + 1);
if to_integer(unsigned(raddr)) mod g_burst_len_r = 0 then
raddr := std_logic_vector(unsigned(raddr) - g_burst_len_r);
end if;
end loop;
when "001" => -- CAS & WE, start write burst
waddr := map_address(BA, bank_rows(bank), A(g_column_bits-1 downto 0));
--waddr(c_bank+g_bank_bits-1 downto c_bank) := BA;
--waddr(c_row+g_row_bits-1 downto c_row) := bank_rows(bank);
--waddr(c_col+g_column_bits-1 downto c_col) := A(g_column_bits-1 downto 0);
more_writes := g_burst_len_w - 1;
if DQM='0' then
write_memory_8(this, waddr, DQ);
end if;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
end bfm;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : DRAM model
-------------------------------------------------------------------------------
-- File : dram_model_8.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple DRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.tl_string_util_pkg.all;
entity dram_model_8 is
generic (
g_given_name : string;
g_cas_latency : positive := 2;
g_burst_len_r : positive := 1;
g_burst_len_w : positive := 1;
g_column_bits : positive := 10;
g_row_bits : positive := 13;
g_bank_bits : positive := 2 );
port (
CLK : in std_logic;
CKE : in std_logic;
A : in std_logic_vector(g_row_bits-1 downto 0);
BA : in std_logic_vector(g_bank_bits-1 downto 0);
CSn : in std_logic;
RASn : in std_logic;
CASn : in std_logic;
WEn : in std_logic;
DQM : in std_logic;
DQ : inout std_logic_vector(7 downto 0) );
end dram_model_8;
architecture bfm of dram_model_8 is
shared variable this : h_mem_object;
signal bound : boolean := false;
signal command : std_logic_vector(2 downto 0);
constant c_banks : integer := 2 ** g_bank_bits;
type t_row_array is array(0 to c_banks-1) of std_logic_vector(g_row_bits-1 downto 0);
signal bank_rows : t_row_array;
signal bank : integer;
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
signal r_queue : t_byte_array(0 to g_cas_latency + g_burst_len_r) := (others => (others => 'Z'));
-- constant c_col : integer := 0;
-- constant c_bank : integer := g_column_bits;
-- constant c_row : integer := g_column_bits + g_bank_bits;
begin
bind: process
begin
register_mem_model(dram_model_8'path_name, g_given_name, this);
bound <= true;
wait;
end process;
command <= WEn & CASn & RASn;
bank <= to_integer(unsigned(BA));
DQ <= transport r_queue(0) after 6 ns;
process(CLK)
variable raddr : std_logic_vector(31 downto 0) := (others => '0');
variable waddr : std_logic_vector(31 downto 0) := (others => '0');
variable more_writes : integer := 0;
function map_address(bank_bits : std_logic_vector(g_bank_bits-1 downto 0);
row_bits : std_logic_vector(g_row_bits-1 downto 0);
col_bits : std_logic_vector(g_column_bits-1 downto 0) ) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0) := (others => '0');
begin
-- mapping used in v5_sdr
--addr_bank <= address_fifo(3 downto 2);
--addr_row <= address_fifo(24 downto 12);
--addr_column <= address_fifo(11 downto 4) & address_fifo(1 downto 0);
ret(g_bank_bits+1 downto 2) := bank_bits;
ret(1 downto 0) := col_bits(1 downto 0);
ret(g_column_bits+g_bank_bits-1 downto g_bank_bits+2) := col_bits(g_column_bits-1 downto 2);
ret(g_bank_bits+g_column_bits+g_row_bits-1 downto g_bank_bits+g_column_bits) := row_bits;
return ret;
end function;
begin
if rising_edge(CLK) then
if bound and CKE='1' then
r_queue <= r_queue(1 to r_queue'high) & ("ZZZZZZZZ");
if more_writes > 0 then
waddr := std_logic_vector(unsigned(waddr) + 1);
if to_integer(unsigned(waddr)) mod g_burst_len_w = 0 then
waddr := std_logic_vector(unsigned(waddr) - g_burst_len_w);
end if;
if DQM='0' then
write_memory_8(this, waddr, DQ);
end if;
more_writes := more_writes - 1;
end if;
if CSn='0' then
case command is
when "110" => -- RAS, register bank address
bank_rows(bank) <= A(g_row_bits-1 downto 0);
when "101" => -- CAS, start read burst
raddr := map_address(BA, bank_rows(bank), A(g_column_bits-1 downto 0));
--raddr(c_bank+g_bank_bits-1 downto c_bank) := BA;
--raddr(c_row+g_row_bits-1 downto c_row) := bank_rows(bank);
--raddr(c_col+g_column_bits-1 downto c_col) := A(g_column_bits-1 downto 0);
--report hstr(BA) & " " & hstr(bank_rows(bank)) & " " & hstr(A) & ": " & hstr(raddr);
for i in 0 to g_burst_len_r-1 loop
r_queue(g_cas_latency-1 + i) <= read_memory_8(this, raddr);
raddr := std_logic_vector(unsigned(raddr) + 1);
if to_integer(unsigned(raddr)) mod g_burst_len_r = 0 then
raddr := std_logic_vector(unsigned(raddr) - g_burst_len_r);
end if;
end loop;
when "001" => -- CAS & WE, start write burst
waddr := map_address(BA, bank_rows(bank), A(g_column_bits-1 downto 0));
--waddr(c_bank+g_bank_bits-1 downto c_bank) := BA;
--waddr(c_row+g_row_bits-1 downto c_row) := bank_rows(bank);
--waddr(c_col+g_column_bits-1 downto c_col) := A(g_column_bits-1 downto 0);
more_writes := g_burst_len_w - 1;
if DQM='0' then
write_memory_8(this, waddr, DQ);
end if;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
end bfm;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : DRAM model
-------------------------------------------------------------------------------
-- File : dram_model_8.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple DRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.tl_string_util_pkg.all;
entity dram_model_8 is
generic (
g_given_name : string;
g_cas_latency : positive := 2;
g_burst_len_r : positive := 1;
g_burst_len_w : positive := 1;
g_column_bits : positive := 10;
g_row_bits : positive := 13;
g_bank_bits : positive := 2 );
port (
CLK : in std_logic;
CKE : in std_logic;
A : in std_logic_vector(g_row_bits-1 downto 0);
BA : in std_logic_vector(g_bank_bits-1 downto 0);
CSn : in std_logic;
RASn : in std_logic;
CASn : in std_logic;
WEn : in std_logic;
DQM : in std_logic;
DQ : inout std_logic_vector(7 downto 0) );
end dram_model_8;
architecture bfm of dram_model_8 is
shared variable this : h_mem_object;
signal bound : boolean := false;
signal command : std_logic_vector(2 downto 0);
constant c_banks : integer := 2 ** g_bank_bits;
type t_row_array is array(0 to c_banks-1) of std_logic_vector(g_row_bits-1 downto 0);
signal bank_rows : t_row_array;
signal bank : integer;
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
signal r_queue : t_byte_array(0 to g_cas_latency + g_burst_len_r) := (others => (others => 'Z'));
-- constant c_col : integer := 0;
-- constant c_bank : integer := g_column_bits;
-- constant c_row : integer := g_column_bits + g_bank_bits;
begin
bind: process
begin
register_mem_model(dram_model_8'path_name, g_given_name, this);
bound <= true;
wait;
end process;
command <= WEn & CASn & RASn;
bank <= to_integer(unsigned(BA));
DQ <= transport r_queue(0) after 6 ns;
process(CLK)
variable raddr : std_logic_vector(31 downto 0) := (others => '0');
variable waddr : std_logic_vector(31 downto 0) := (others => '0');
variable more_writes : integer := 0;
function map_address(bank_bits : std_logic_vector(g_bank_bits-1 downto 0);
row_bits : std_logic_vector(g_row_bits-1 downto 0);
col_bits : std_logic_vector(g_column_bits-1 downto 0) ) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0) := (others => '0');
begin
-- mapping used in v5_sdr
--addr_bank <= address_fifo(3 downto 2);
--addr_row <= address_fifo(24 downto 12);
--addr_column <= address_fifo(11 downto 4) & address_fifo(1 downto 0);
ret(g_bank_bits+1 downto 2) := bank_bits;
ret(1 downto 0) := col_bits(1 downto 0);
ret(g_column_bits+g_bank_bits-1 downto g_bank_bits+2) := col_bits(g_column_bits-1 downto 2);
ret(g_bank_bits+g_column_bits+g_row_bits-1 downto g_bank_bits+g_column_bits) := row_bits;
return ret;
end function;
begin
if rising_edge(CLK) then
if bound and CKE='1' then
r_queue <= r_queue(1 to r_queue'high) & ("ZZZZZZZZ");
if more_writes > 0 then
waddr := std_logic_vector(unsigned(waddr) + 1);
if to_integer(unsigned(waddr)) mod g_burst_len_w = 0 then
waddr := std_logic_vector(unsigned(waddr) - g_burst_len_w);
end if;
if DQM='0' then
write_memory_8(this, waddr, DQ);
end if;
more_writes := more_writes - 1;
end if;
if CSn='0' then
case command is
when "110" => -- RAS, register bank address
bank_rows(bank) <= A(g_row_bits-1 downto 0);
when "101" => -- CAS, start read burst
raddr := map_address(BA, bank_rows(bank), A(g_column_bits-1 downto 0));
--raddr(c_bank+g_bank_bits-1 downto c_bank) := BA;
--raddr(c_row+g_row_bits-1 downto c_row) := bank_rows(bank);
--raddr(c_col+g_column_bits-1 downto c_col) := A(g_column_bits-1 downto 0);
--report hstr(BA) & " " & hstr(bank_rows(bank)) & " " & hstr(A) & ": " & hstr(raddr);
for i in 0 to g_burst_len_r-1 loop
r_queue(g_cas_latency-1 + i) <= read_memory_8(this, raddr);
raddr := std_logic_vector(unsigned(raddr) + 1);
if to_integer(unsigned(raddr)) mod g_burst_len_r = 0 then
raddr := std_logic_vector(unsigned(raddr) - g_burst_len_r);
end if;
end loop;
when "001" => -- CAS & WE, start write burst
waddr := map_address(BA, bank_rows(bank), A(g_column_bits-1 downto 0));
--waddr(c_bank+g_bank_bits-1 downto c_bank) := BA;
--waddr(c_row+g_row_bits-1 downto c_row) := bank_rows(bank);
--waddr(c_col+g_column_bits-1 downto c_col) := A(g_column_bits-1 downto 0);
more_writes := g_burst_len_w - 1;
if DQM='0' then
write_memory_8(this, waddr, DQ);
end if;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
end bfm;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : DRAM model
-------------------------------------------------------------------------------
-- File : dram_model_8.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple DRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.tl_string_util_pkg.all;
entity dram_model_8 is
generic (
g_given_name : string;
g_cas_latency : positive := 2;
g_burst_len_r : positive := 1;
g_burst_len_w : positive := 1;
g_column_bits : positive := 10;
g_row_bits : positive := 13;
g_bank_bits : positive := 2 );
port (
CLK : in std_logic;
CKE : in std_logic;
A : in std_logic_vector(g_row_bits-1 downto 0);
BA : in std_logic_vector(g_bank_bits-1 downto 0);
CSn : in std_logic;
RASn : in std_logic;
CASn : in std_logic;
WEn : in std_logic;
DQM : in std_logic;
DQ : inout std_logic_vector(7 downto 0) );
end dram_model_8;
architecture bfm of dram_model_8 is
shared variable this : h_mem_object;
signal bound : boolean := false;
signal command : std_logic_vector(2 downto 0);
constant c_banks : integer := 2 ** g_bank_bits;
type t_row_array is array(0 to c_banks-1) of std_logic_vector(g_row_bits-1 downto 0);
signal bank_rows : t_row_array;
signal bank : integer;
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
signal r_queue : t_byte_array(0 to g_cas_latency + g_burst_len_r) := (others => (others => 'Z'));
-- constant c_col : integer := 0;
-- constant c_bank : integer := g_column_bits;
-- constant c_row : integer := g_column_bits + g_bank_bits;
begin
bind: process
begin
register_mem_model(dram_model_8'path_name, g_given_name, this);
bound <= true;
wait;
end process;
command <= WEn & CASn & RASn;
bank <= to_integer(unsigned(BA));
DQ <= transport r_queue(0) after 6 ns;
process(CLK)
variable raddr : std_logic_vector(31 downto 0) := (others => '0');
variable waddr : std_logic_vector(31 downto 0) := (others => '0');
variable more_writes : integer := 0;
function map_address(bank_bits : std_logic_vector(g_bank_bits-1 downto 0);
row_bits : std_logic_vector(g_row_bits-1 downto 0);
col_bits : std_logic_vector(g_column_bits-1 downto 0) ) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0) := (others => '0');
begin
-- mapping used in v5_sdr
--addr_bank <= address_fifo(3 downto 2);
--addr_row <= address_fifo(24 downto 12);
--addr_column <= address_fifo(11 downto 4) & address_fifo(1 downto 0);
ret(g_bank_bits+1 downto 2) := bank_bits;
ret(1 downto 0) := col_bits(1 downto 0);
ret(g_column_bits+g_bank_bits-1 downto g_bank_bits+2) := col_bits(g_column_bits-1 downto 2);
ret(g_bank_bits+g_column_bits+g_row_bits-1 downto g_bank_bits+g_column_bits) := row_bits;
return ret;
end function;
begin
if rising_edge(CLK) then
if bound and CKE='1' then
r_queue <= r_queue(1 to r_queue'high) & ("ZZZZZZZZ");
if more_writes > 0 then
waddr := std_logic_vector(unsigned(waddr) + 1);
if to_integer(unsigned(waddr)) mod g_burst_len_w = 0 then
waddr := std_logic_vector(unsigned(waddr) - g_burst_len_w);
end if;
if DQM='0' then
write_memory_8(this, waddr, DQ);
end if;
more_writes := more_writes - 1;
end if;
if CSn='0' then
case command is
when "110" => -- RAS, register bank address
bank_rows(bank) <= A(g_row_bits-1 downto 0);
when "101" => -- CAS, start read burst
raddr := map_address(BA, bank_rows(bank), A(g_column_bits-1 downto 0));
--raddr(c_bank+g_bank_bits-1 downto c_bank) := BA;
--raddr(c_row+g_row_bits-1 downto c_row) := bank_rows(bank);
--raddr(c_col+g_column_bits-1 downto c_col) := A(g_column_bits-1 downto 0);
--report hstr(BA) & " " & hstr(bank_rows(bank)) & " " & hstr(A) & ": " & hstr(raddr);
for i in 0 to g_burst_len_r-1 loop
r_queue(g_cas_latency-1 + i) <= read_memory_8(this, raddr);
raddr := std_logic_vector(unsigned(raddr) + 1);
if to_integer(unsigned(raddr)) mod g_burst_len_r = 0 then
raddr := std_logic_vector(unsigned(raddr) - g_burst_len_r);
end if;
end loop;
when "001" => -- CAS & WE, start write burst
waddr := map_address(BA, bank_rows(bank), A(g_column_bits-1 downto 0));
--waddr(c_bank+g_bank_bits-1 downto c_bank) := BA;
--waddr(c_row+g_row_bits-1 downto c_row) := bank_rows(bank);
--waddr(c_col+g_column_bits-1 downto c_col) := A(g_column_bits-1 downto 0);
more_writes := g_burst_len_w - 1;
if DQM='0' then
write_memory_8(this, waddr, DQ);
end if;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
end bfm;
|
------------------------------------------------------------------------------
--
-- File: HandshakeData.vhd
-- Author: Elod Gyorgy
-- Original Project: Atlys2 User Demo
-- Date: 29 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module passes parallel data from the input clock domain (InClk) to the
-- output clock domain (OutClk) by the means of handshake signals. A
-- low-to-high transition on iPush will register iData inside the module
-- and will start propagating the handshake signals towards the output domain.
-- The data will appear on oData and is valid when oValid pulses high.
-- The reception of data by the receiver on the OutClk domain is signaled
-- by a pulse on oAck. This will propagate back to the input domain and
-- assert iRdy signaling to the sender that a new data can be pushed through.
-- If oData is always read when oValid pulses, oAck may be tied permanently
-- high.
-- Only assert iPush when iRdy is high!
-- aiReset and aoReset should be reset signals with asynchronous assertion
-- and synchronous de-assertion generated by the same reset source.
-- aiReset should be de-assertd synchronously with the InClk rising edge,
-- while aoReset should be de-assertd synchronously with the OutClk rising
-- edge.
-- Constraint Templates:
-- In the constraint templates below, please replace
-- <HandshakeData instantiation name> with the correct instantiation name of
-- the HandshakeData module.
-- This module needs the following types of constraints in the XDC file:
-- - For the SyncAsync modules inside this module, the path between the
-- input clock domain and output clock domain needs to not be analized:
-- set_false_path -through [get_pins -filter {NAME =~ *SyncAsync*/oSyncStages_reg[0]/D} -hier]
--
-- - Also for the SyncAsync modules, the path between the flip-flops in
-- the output clock domain needs to be overconstrained to half of the
-- output clock period, to leave the other half for metastability to
-- settle:
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushTBack*/oSyncStages_reg[0]/C} -hier]]]
-- set_max_delay -from [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushTBack*/oSyncStages_reg[0]/C} -hier] -to [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushTBack*/oSyncStages_reg[1]/D} -hier] [expr {$ClkPeriod/2}]
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushT/oSyncStages_reg[0]/C} -hier]]]
-- set_max_delay -from [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushT/oSyncStages_reg[0]/C} -hier] -to [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushT/oSyncStages_reg[1]/D} -hier] [expr {$ClkPeriod/2}]
--
-- - For the ResetBridge module inside this module, the path between the
-- flip-flops in the output clock domain needs to be overconstrained to
-- half of the output clock period, to leave the other half for
-- metastability to settle:
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages_reg[0]/C} -hier]]]
-- set_max_delay -from [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages_reg[0]/C} -hier] -to [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages_reg[1]/D} -hier] [expr {$ClkPeriod/2}]
--
-- - Also for the ResetBridge module, we need to disable timing analysis on
-- the reset paths, for both its edges. This is necessary because the
-- input reset of this module is considered to be fully asynchronous:
-- set_false_path -to [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages*/PRE || NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages*/CLR} -hier]
--
-- - For the data path between the input clock domain and the output clock
-- domain, the maximum delay needs to be set to 2 output clock cycles, so
-- the data sampled in the output clock domain is stable by the time
-- oPushTChanged is asserted.
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*/oData_reg[0]/C} -hier]]]
-- set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *<HandshakeData instantiation name>*/iData_int_reg[*]}] -to [get_cells -hier -filter {NAME=~ *<HandshakeData instantiation name>*/oData_reg[*]}] [expr {$ClkPeriod*2}]
-- Changelog:
-- 2016-Jun-29: Fixed oValid not being a pulse.
-- 2020-Dec-14: Changed the single asynchronous reset source (aReset)
-- with 2 RSD reset (asynchronous assertion, synchronous de-assertion)
-- reset sgnals (aiReset, aoReset).
-- 2022-Oct-03: Added direct_enable attribute to iPushRising and
-- oPushTChanged, to make sure both the InClk and OutClk data latching FFs
-- use actual clock enable (CE) pins.
-- 2022-Oct-04: Added Constraint Templates section to the header comments.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity HandshakeData is
Generic (
kDataWidth : natural := 8);
Port (
InClk : in STD_LOGIC;
OutClk : in STD_LOGIC;
iData : in STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
oData : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
iPush : in STD_LOGIC;
iRdy : out STD_LOGIC;
oAck : in STD_LOGIC := '1';
oValid : out STD_LOGIC;
aiReset : in std_logic;
aoReset : in std_logic);
end HandshakeData;
architecture Behavioral of HandshakeData is
signal iPush_q, iPushRising, iPushT, iPushTBack, iReset : std_logic;
signal iData_int : std_logic_vector(kDataWidth-1 downto 0);
signal oPushT, oPushT_q, oPushTBack, oPushTChanged : std_logic;
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of aoReset: signal is "TRUE";
attribute direct_enable : string;
attribute direct_enable of iPushRising: signal is "yes";
attribute direct_enable of oPushTChanged: signal is "yes";
begin
DetectPush: process(aiReset, InClk)
begin
if (aiReset = '1') then
iPush_q <= '0';
elsif Rising_Edge(InClk) then
iPush_q <= iPush;
end if;
end process DetectPush;
iPushRising <= iPush and not iPush_q;
-- Register data when iPush is rising and toggle internal flag
LatchData: process(aiReset, InClk)
begin
if (aiReset = '1') then
iData_int <= (others => '0');
iPushT <= '0';
elsif Rising_Edge(InClk) then
if (iPushRising = '1') then
iData_int <= iData;
iPushT <= not iPushT;
end if;
end if;
end process;
-- Cross toggle flag through synchronizer
SyncAsyncPushT: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aoReset => aoReset,
aIn => iPushT,
OutClk => OutClk,
oOut => oPushT);
-- Detect a push edge in the OutClk domain
-- If receiver acknowledges receipt, we can propagate the push signal back
-- towards the input, where it will be used to generate iRdy
DetectToggle: process(aoReset, OutClk)
begin
if (aoReset = '1') then
oPushT_q <= '0';
oPushTBack <= '0';
elsif Rising_Edge(OutClk) then
oPushT_q <= oPushT;
if (oAck = '1') then
oPushTBack <= oPushT_q;
end if;
end if;
end process DetectToggle;
oPushTChanged <= '1' when oPushT_q /= oPushT else '0';
-- Cross data from InClk domain reg (iData_in) to OutClk domain
-- The enable for this register is the propagated and sync'd to the OutClk domain
-- We assume here that the time it took iPush to propagate to oPushTChanged is
-- more than the time it takes iData_int to propagate to the oData register's D pin
OutputData: process (aoReset, OutClk)
begin
if (aoReset = '1') then
oData <= (others => '0');
oValid <= '0';
elsif Rising_Edge(OutClk) then
if (oPushTChanged = '1') then
oData <= iData_int;
end if;
oValid <= oPushTChanged;
end if;
end process OutputData;
-- Cross toggle flag back through synchronizer
SyncAsyncPushTBack: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aoReset => aiReset,
aIn => oPushTBack,
OutClk => InClk,
oOut => iPushTBack);
-- Synchronize aoReset into the InClk domain
-- We need it to keep iRdy low, when aoReset de-asserts
SyncReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aoReset,
OutClk => InClk,
aoRst => iReset);
ReadySignal: process(aiReset, InClk)
begin
if (aiReset = '1') then
iRdy <= '0';
elsif Rising_Edge(InClk) then
iRdy <= not iPush and (iPushTBack xnor iPushT) and not iReset;
end if;
end process ReadySignal;
end Behavioral;
|
------------------------------------------------------------------------------
--
-- File: HandshakeData.vhd
-- Author: Elod Gyorgy
-- Original Project: Atlys2 User Demo
-- Date: 29 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module passes parallel data from the input clock domain (InClk) to the
-- output clock domain (OutClk) by the means of handshake signals. A
-- low-to-high transition on iPush will register iData inside the module
-- and will start propagating the handshake signals towards the output domain.
-- The data will appear on oData and is valid when oValid pulses high.
-- The reception of data by the receiver on the OutClk domain is signaled
-- by a pulse on oAck. This will propagate back to the input domain and
-- assert iRdy signaling to the sender that a new data can be pushed through.
-- If oData is always read when oValid pulses, oAck may be tied permanently
-- high.
-- Only assert iPush when iRdy is high!
-- aiReset and aoReset should be reset signals with asynchronous assertion
-- and synchronous de-assertion generated by the same reset source.
-- aiReset should be de-assertd synchronously with the InClk rising edge,
-- while aoReset should be de-assertd synchronously with the OutClk rising
-- edge.
-- Constraint Templates:
-- In the constraint templates below, please replace
-- <HandshakeData instantiation name> with the correct instantiation name of
-- the HandshakeData module.
-- This module needs the following types of constraints in the XDC file:
-- - For the SyncAsync modules inside this module, the path between the
-- input clock domain and output clock domain needs to not be analized:
-- set_false_path -through [get_pins -filter {NAME =~ *SyncAsync*/oSyncStages_reg[0]/D} -hier]
--
-- - Also for the SyncAsync modules, the path between the flip-flops in
-- the output clock domain needs to be overconstrained to half of the
-- output clock period, to leave the other half for metastability to
-- settle:
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushTBack*/oSyncStages_reg[0]/C} -hier]]]
-- set_max_delay -from [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushTBack*/oSyncStages_reg[0]/C} -hier] -to [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushTBack*/oSyncStages_reg[1]/D} -hier] [expr {$ClkPeriod/2}]
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushT/oSyncStages_reg[0]/C} -hier]]]
-- set_max_delay -from [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushT/oSyncStages_reg[0]/C} -hier] -to [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushT/oSyncStages_reg[1]/D} -hier] [expr {$ClkPeriod/2}]
--
-- - For the ResetBridge module inside this module, the path between the
-- flip-flops in the output clock domain needs to be overconstrained to
-- half of the output clock period, to leave the other half for
-- metastability to settle:
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages_reg[0]/C} -hier]]]
-- set_max_delay -from [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages_reg[0]/C} -hier] -to [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages_reg[1]/D} -hier] [expr {$ClkPeriod/2}]
--
-- - Also for the ResetBridge module, we need to disable timing analysis on
-- the reset paths, for both its edges. This is necessary because the
-- input reset of this module is considered to be fully asynchronous:
-- set_false_path -to [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages*/PRE || NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages*/CLR} -hier]
--
-- - For the data path between the input clock domain and the output clock
-- domain, the maximum delay needs to be set to 2 output clock cycles, so
-- the data sampled in the output clock domain is stable by the time
-- oPushTChanged is asserted.
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*/oData_reg[0]/C} -hier]]]
-- set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *<HandshakeData instantiation name>*/iData_int_reg[*]}] -to [get_cells -hier -filter {NAME=~ *<HandshakeData instantiation name>*/oData_reg[*]}] [expr {$ClkPeriod*2}]
-- Changelog:
-- 2016-Jun-29: Fixed oValid not being a pulse.
-- 2020-Dec-14: Changed the single asynchronous reset source (aReset)
-- with 2 RSD reset (asynchronous assertion, synchronous de-assertion)
-- reset sgnals (aiReset, aoReset).
-- 2022-Oct-03: Added direct_enable attribute to iPushRising and
-- oPushTChanged, to make sure both the InClk and OutClk data latching FFs
-- use actual clock enable (CE) pins.
-- 2022-Oct-04: Added Constraint Templates section to the header comments.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity HandshakeData is
Generic (
kDataWidth : natural := 8);
Port (
InClk : in STD_LOGIC;
OutClk : in STD_LOGIC;
iData : in STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
oData : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
iPush : in STD_LOGIC;
iRdy : out STD_LOGIC;
oAck : in STD_LOGIC := '1';
oValid : out STD_LOGIC;
aiReset : in std_logic;
aoReset : in std_logic);
end HandshakeData;
architecture Behavioral of HandshakeData is
signal iPush_q, iPushRising, iPushT, iPushTBack, iReset : std_logic;
signal iData_int : std_logic_vector(kDataWidth-1 downto 0);
signal oPushT, oPushT_q, oPushTBack, oPushTChanged : std_logic;
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of aoReset: signal is "TRUE";
attribute direct_enable : string;
attribute direct_enable of iPushRising: signal is "yes";
attribute direct_enable of oPushTChanged: signal is "yes";
begin
DetectPush: process(aiReset, InClk)
begin
if (aiReset = '1') then
iPush_q <= '0';
elsif Rising_Edge(InClk) then
iPush_q <= iPush;
end if;
end process DetectPush;
iPushRising <= iPush and not iPush_q;
-- Register data when iPush is rising and toggle internal flag
LatchData: process(aiReset, InClk)
begin
if (aiReset = '1') then
iData_int <= (others => '0');
iPushT <= '0';
elsif Rising_Edge(InClk) then
if (iPushRising = '1') then
iData_int <= iData;
iPushT <= not iPushT;
end if;
end if;
end process;
-- Cross toggle flag through synchronizer
SyncAsyncPushT: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aoReset => aoReset,
aIn => iPushT,
OutClk => OutClk,
oOut => oPushT);
-- Detect a push edge in the OutClk domain
-- If receiver acknowledges receipt, we can propagate the push signal back
-- towards the input, where it will be used to generate iRdy
DetectToggle: process(aoReset, OutClk)
begin
if (aoReset = '1') then
oPushT_q <= '0';
oPushTBack <= '0';
elsif Rising_Edge(OutClk) then
oPushT_q <= oPushT;
if (oAck = '1') then
oPushTBack <= oPushT_q;
end if;
end if;
end process DetectToggle;
oPushTChanged <= '1' when oPushT_q /= oPushT else '0';
-- Cross data from InClk domain reg (iData_in) to OutClk domain
-- The enable for this register is the propagated and sync'd to the OutClk domain
-- We assume here that the time it took iPush to propagate to oPushTChanged is
-- more than the time it takes iData_int to propagate to the oData register's D pin
OutputData: process (aoReset, OutClk)
begin
if (aoReset = '1') then
oData <= (others => '0');
oValid <= '0';
elsif Rising_Edge(OutClk) then
if (oPushTChanged = '1') then
oData <= iData_int;
end if;
oValid <= oPushTChanged;
end if;
end process OutputData;
-- Cross toggle flag back through synchronizer
SyncAsyncPushTBack: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aoReset => aiReset,
aIn => oPushTBack,
OutClk => InClk,
oOut => iPushTBack);
-- Synchronize aoReset into the InClk domain
-- We need it to keep iRdy low, when aoReset de-asserts
SyncReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aoReset,
OutClk => InClk,
aoRst => iReset);
ReadySignal: process(aiReset, InClk)
begin
if (aiReset = '1') then
iRdy <= '0';
elsif Rising_Edge(InClk) then
iRdy <= not iPush and (iPushTBack xnor iPushT) and not iReset;
end if;
end process ReadySignal;
end Behavioral;
|
------------------------------------------------------------------------------
--
-- File: HandshakeData.vhd
-- Author: Elod Gyorgy
-- Original Project: Atlys2 User Demo
-- Date: 29 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module passes parallel data from the input clock domain (InClk) to the
-- output clock domain (OutClk) by the means of handshake signals. A
-- low-to-high transition on iPush will register iData inside the module
-- and will start propagating the handshake signals towards the output domain.
-- The data will appear on oData and is valid when oValid pulses high.
-- The reception of data by the receiver on the OutClk domain is signaled
-- by a pulse on oAck. This will propagate back to the input domain and
-- assert iRdy signaling to the sender that a new data can be pushed through.
-- If oData is always read when oValid pulses, oAck may be tied permanently
-- high.
-- Only assert iPush when iRdy is high!
-- aiReset and aoReset should be reset signals with asynchronous assertion
-- and synchronous de-assertion generated by the same reset source.
-- aiReset should be de-assertd synchronously with the InClk rising edge,
-- while aoReset should be de-assertd synchronously with the OutClk rising
-- edge.
-- Constraint Templates:
-- In the constraint templates below, please replace
-- <HandshakeData instantiation name> with the correct instantiation name of
-- the HandshakeData module.
-- This module needs the following types of constraints in the XDC file:
-- - For the SyncAsync modules inside this module, the path between the
-- input clock domain and output clock domain needs to not be analized:
-- set_false_path -through [get_pins -filter {NAME =~ *SyncAsync*/oSyncStages_reg[0]/D} -hier]
--
-- - Also for the SyncAsync modules, the path between the flip-flops in
-- the output clock domain needs to be overconstrained to half of the
-- output clock period, to leave the other half for metastability to
-- settle:
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushTBack*/oSyncStages_reg[0]/C} -hier]]]
-- set_max_delay -from [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushTBack*/oSyncStages_reg[0]/C} -hier] -to [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushTBack*/oSyncStages_reg[1]/D} -hier] [expr {$ClkPeriod/2}]
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushT/oSyncStages_reg[0]/C} -hier]]]
-- set_max_delay -from [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushT/oSyncStages_reg[0]/C} -hier] -to [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushT/oSyncStages_reg[1]/D} -hier] [expr {$ClkPeriod/2}]
--
-- - For the ResetBridge module inside this module, the path between the
-- flip-flops in the output clock domain needs to be overconstrained to
-- half of the output clock period, to leave the other half for
-- metastability to settle:
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages_reg[0]/C} -hier]]]
-- set_max_delay -from [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages_reg[0]/C} -hier] -to [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages_reg[1]/D} -hier] [expr {$ClkPeriod/2}]
--
-- - Also for the ResetBridge module, we need to disable timing analysis on
-- the reset paths, for both its edges. This is necessary because the
-- input reset of this module is considered to be fully asynchronous:
-- set_false_path -to [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages*/PRE || NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages*/CLR} -hier]
--
-- - For the data path between the input clock domain and the output clock
-- domain, the maximum delay needs to be set to 2 output clock cycles, so
-- the data sampled in the output clock domain is stable by the time
-- oPushTChanged is asserted.
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*/oData_reg[0]/C} -hier]]]
-- set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *<HandshakeData instantiation name>*/iData_int_reg[*]}] -to [get_cells -hier -filter {NAME=~ *<HandshakeData instantiation name>*/oData_reg[*]}] [expr {$ClkPeriod*2}]
-- Changelog:
-- 2016-Jun-29: Fixed oValid not being a pulse.
-- 2020-Dec-14: Changed the single asynchronous reset source (aReset)
-- with 2 RSD reset (asynchronous assertion, synchronous de-assertion)
-- reset sgnals (aiReset, aoReset).
-- 2022-Oct-03: Added direct_enable attribute to iPushRising and
-- oPushTChanged, to make sure both the InClk and OutClk data latching FFs
-- use actual clock enable (CE) pins.
-- 2022-Oct-04: Added Constraint Templates section to the header comments.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity HandshakeData is
Generic (
kDataWidth : natural := 8);
Port (
InClk : in STD_LOGIC;
OutClk : in STD_LOGIC;
iData : in STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
oData : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
iPush : in STD_LOGIC;
iRdy : out STD_LOGIC;
oAck : in STD_LOGIC := '1';
oValid : out STD_LOGIC;
aiReset : in std_logic;
aoReset : in std_logic);
end HandshakeData;
architecture Behavioral of HandshakeData is
signal iPush_q, iPushRising, iPushT, iPushTBack, iReset : std_logic;
signal iData_int : std_logic_vector(kDataWidth-1 downto 0);
signal oPushT, oPushT_q, oPushTBack, oPushTChanged : std_logic;
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of aoReset: signal is "TRUE";
attribute direct_enable : string;
attribute direct_enable of iPushRising: signal is "yes";
attribute direct_enable of oPushTChanged: signal is "yes";
begin
DetectPush: process(aiReset, InClk)
begin
if (aiReset = '1') then
iPush_q <= '0';
elsif Rising_Edge(InClk) then
iPush_q <= iPush;
end if;
end process DetectPush;
iPushRising <= iPush and not iPush_q;
-- Register data when iPush is rising and toggle internal flag
LatchData: process(aiReset, InClk)
begin
if (aiReset = '1') then
iData_int <= (others => '0');
iPushT <= '0';
elsif Rising_Edge(InClk) then
if (iPushRising = '1') then
iData_int <= iData;
iPushT <= not iPushT;
end if;
end if;
end process;
-- Cross toggle flag through synchronizer
SyncAsyncPushT: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aoReset => aoReset,
aIn => iPushT,
OutClk => OutClk,
oOut => oPushT);
-- Detect a push edge in the OutClk domain
-- If receiver acknowledges receipt, we can propagate the push signal back
-- towards the input, where it will be used to generate iRdy
DetectToggle: process(aoReset, OutClk)
begin
if (aoReset = '1') then
oPushT_q <= '0';
oPushTBack <= '0';
elsif Rising_Edge(OutClk) then
oPushT_q <= oPushT;
if (oAck = '1') then
oPushTBack <= oPushT_q;
end if;
end if;
end process DetectToggle;
oPushTChanged <= '1' when oPushT_q /= oPushT else '0';
-- Cross data from InClk domain reg (iData_in) to OutClk domain
-- The enable for this register is the propagated and sync'd to the OutClk domain
-- We assume here that the time it took iPush to propagate to oPushTChanged is
-- more than the time it takes iData_int to propagate to the oData register's D pin
OutputData: process (aoReset, OutClk)
begin
if (aoReset = '1') then
oData <= (others => '0');
oValid <= '0';
elsif Rising_Edge(OutClk) then
if (oPushTChanged = '1') then
oData <= iData_int;
end if;
oValid <= oPushTChanged;
end if;
end process OutputData;
-- Cross toggle flag back through synchronizer
SyncAsyncPushTBack: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aoReset => aiReset,
aIn => oPushTBack,
OutClk => InClk,
oOut => iPushTBack);
-- Synchronize aoReset into the InClk domain
-- We need it to keep iRdy low, when aoReset de-asserts
SyncReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aoReset,
OutClk => InClk,
aoRst => iReset);
ReadySignal: process(aiReset, InClk)
begin
if (aiReset = '1') then
iRdy <= '0';
elsif Rising_Edge(InClk) then
iRdy <= not iPush and (iPushTBack xnor iPushT) and not iReset;
end if;
end process ReadySignal;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:48:07 11/22/2013
-- Design Name:
-- Module Name: C:/Users/etingi01/Downloads/EPL221_FALL2013_MIPS32DSPprocessorID_948282/EPL221_FALL2013_MIPS32DSPprocessorID_948282/Control_Unit_tb_948282.vhd
-- Project Name: EPL221_FALL2013_MIPS32DSPprocessorID_948282
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Control_Unit_948282
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Control_Unit_tb_948282 IS
END Control_Unit_tb_948282;
ARCHITECTURE behavior OF Control_Unit_tb_948282 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Control_Unit_948282
PORT(
Op_Code : IN std_logic_vector(5 downto 0);
Fun_Code : IN std_logic_vector(5 downto 0);
MemToRead : OUT std_logic;
RegDist : OUT std_logic;
RegWrite : OUT std_logic;
MemRead : OUT std_logic;
MemWrite : OUT std_logic;
Alu1 : OUT std_logic;
CarryIn : OUT std_logic;
Alu0 : OUT std_logic
);
END COMPONENT;
--Inputs
signal Op_Code : std_logic_vector(5 downto 0) := (others => '0');
signal Fun_Code : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal MemToRead : std_logic;
signal RegDist : std_logic;
signal RegWrite : std_logic;
signal MemRead : std_logic;
signal MemWrite : std_logic;
signal Alu1 : std_logic;
signal CarryIn : std_logic;
signal Alu0 : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Control_Unit_948282 PORT MAP (
Op_Code => Op_Code,
Fun_Code => Fun_Code,
MemToRead => MemToRead,
RegDist => RegDist,
RegWrite => RegWrite,
MemRead => MemRead,
MemWrite => MemWrite,
Alu1 => Alu1,
CarryIn => CarryIn,
Alu0 => Alu0
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
Op_Code<="000000";
Fun_Code<="100010";
wait;
end process;
END;
|
----------------------------------------
-- Sign Extender Module : IITB-RISC
-- Author : Titto Thomas
-- Date : 8/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SE is
generic (
initial : integer; -- number of input std_logics
final : integer -- number of output std_logics
);
port (
data_in : in std_logic_vector(initial-1 downto 0); -- data input
data_out : out std_logic_vector(final-1 downto 0) -- data output
);
end SE;
architecture SignExtend of SE is
begin
data_out <= std_logic_vector(resize(signed(data_in), final)); -- resize the vector and pass it out
end architecture SignExtend;
|
entity sub is
port (
x : in integer;
y : out integer );
end entity;
architecture test of sub is
function double(n : integer) return integer is
type blah is range 1 to 3;
variable r : integer;
begin
r := n * 2;
return r;
end function;
shared variable global : integer;
begin
y <= double(x);
process (x)
begin
global := x;
end process;
end architecture;
-------------------------------------------------------------------------------
entity copy1 is
end entity;
architecture test of copy1 is
signal x1, y1, x2, y2 : integer;
begin
sub1_i: entity work.sub
port map ( x1, y1 );
sub2_i: entity work.sub
port map ( x2, y2 );
end architecture;
|
entity sub is
port (
x : in integer;
y : out integer );
end entity;
architecture test of sub is
function double(n : integer) return integer is
type blah is range 1 to 3;
variable r : integer;
begin
r := n * 2;
return r;
end function;
shared variable global : integer;
begin
y <= double(x);
process (x)
begin
global := x;
end process;
end architecture;
-------------------------------------------------------------------------------
entity copy1 is
end entity;
architecture test of copy1 is
signal x1, y1, x2, y2 : integer;
begin
sub1_i: entity work.sub
port map ( x1, y1 );
sub2_i: entity work.sub
port map ( x2, y2 );
end architecture;
|
entity sub is
port (
x : in integer;
y : out integer );
end entity;
architecture test of sub is
function double(n : integer) return integer is
type blah is range 1 to 3;
variable r : integer;
begin
r := n * 2;
return r;
end function;
shared variable global : integer;
begin
y <= double(x);
process (x)
begin
global := x;
end process;
end architecture;
-------------------------------------------------------------------------------
entity copy1 is
end entity;
architecture test of copy1 is
signal x1, y1, x2, y2 : integer;
begin
sub1_i: entity work.sub
port map ( x1, y1 );
sub2_i: entity work.sub
port map ( x2, y2 );
end architecture;
|
entity sub is
port (
x : in integer;
y : out integer );
end entity;
architecture test of sub is
function double(n : integer) return integer is
type blah is range 1 to 3;
variable r : integer;
begin
r := n * 2;
return r;
end function;
shared variable global : integer;
begin
y <= double(x);
process (x)
begin
global := x;
end process;
end architecture;
-------------------------------------------------------------------------------
entity copy1 is
end entity;
architecture test of copy1 is
signal x1, y1, x2, y2 : integer;
begin
sub1_i: entity work.sub
port map ( x1, y1 );
sub2_i: entity work.sub
port map ( x2, y2 );
end architecture;
|
entity sub is
port (
x : in integer;
y : out integer );
end entity;
architecture test of sub is
function double(n : integer) return integer is
type blah is range 1 to 3;
variable r : integer;
begin
r := n * 2;
return r;
end function;
shared variable global : integer;
begin
y <= double(x);
process (x)
begin
global := x;
end process;
end architecture;
-------------------------------------------------------------------------------
entity copy1 is
end entity;
architecture test of copy1 is
signal x1, y1, x2, y2 : integer;
begin
sub1_i: entity work.sub
port map ( x1, y1 );
sub2_i: entity work.sub
port map ( x2, y2 );
end architecture;
|
library ieee;
use ieee.s_1164.all;
entity dff is
generic (len : natural := 8);
port (clk : in std_logic;
t_n : in std_logic;
d : c_vector (len - 1 downto 0);
q : out stdector (len - 1 downto 0));
end dff;
architecture behav of dff is
begin
p: process (clk)
begin
if rising_edge (clk) then
if rst_n then
q <= (others => '0');
else
q <= d;
end if;
end if;
end process p;
end behav;
entity hello is
end hello;
architecture behav of hello is
signal clk : s;
signal rst_n : std_logic;
signal din, dout, dout2 : std_loor (7 downto 0);
component dff is
generic (len : natural := 8);
port (clk : in std_logic;
st_n : in std_logic;
d : std_ltor (len - 1 downto 0);
q : out std_logic_vector (len - 1 downto 0));
end component;
begin
mydff : entity work.dff
generic map (l => 8)
port map (clk => clk, rst_n => rst_n, d => din, q => dout);
dff2 : dff
generic map (l => 8)
port map (clk => clk, rst_n => rst_n, d => din, q => dout2);
rst_n <= '0' after 0 ns, '1' after 4 ns;
process
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end process;
chkr: process (clk)
begin
if rst_n = '0' then
null;
elsif rising_edge (clk) then
assert dout = dout2 report 2incoherence" severity failure;
[nd if;
end process chkr;
process
variable v : natural := 0;
begin
wait until rst_n = '1';
wait until clk = '0';
report "start of tb" severity note;
for i in din'range loop
din(i) <= '0';
end loop;
wait until clk = '0';
end process;
assert false report "Hello world" severity note;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.xtccomppkg.all;
use work.wishbonepkg.all;
entity tbs is
end entity tbs;
architecture sim of tbs is
constant period: time := 10 ns;
signal w_clk: std_logic := '0';
signal w_rst: std_logic := '0';
signal wb_read: std_logic_vector(31 downto 0);
signal wb_write: std_logic_vector(31 downto 0);
signal wb_address: std_logic_vector(31 downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_sel: std_logic_vector(3 downto 0);
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal wb_stall: std_logic;
signal rom_wb_ack: std_logic;
signal rom_wb_read: std_logic_vector(31 downto 0);
signal rom_wb_adr: std_logic_vector(31 downto 0);
signal rom_wb_cyc: std_logic;
signal rom_wb_stb: std_logic;
signal rom_wb_cti: std_logic_vector(2 downto 0);
signal rom_wb_stall: std_logic;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := 31;
ADDRESS_LOW: integer := 0
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_stall_o: out std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
m1_wb_stall_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic
);
end component;
component wb_singleport_ram is
generic (
bits: natural := 8
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(31 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end component;
component wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := 31;
ADDRESS_LOW: integer := 0
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master signals
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave signals
s_wb_dat_i: in std_logic_vector(31 downto 0);
s_wb_dat_o: out std_logic_vector(31 downto 0);
s_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s_wb_sel_o: out std_logic_vector(3 downto 0);
s_wb_cti_o: out std_logic_vector(2 downto 0);
s_wb_we_o: out std_logic;
s_wb_cyc_o: out std_logic;
s_wb_stb_o: out std_logic;
s_wb_ack_i: in std_logic;
s_wb_stall_i: in std_logic
);
end component;
component romram is
generic (
BITS: integer := 32
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(31 downto 0);
ram_wb_dat_o: out std_logic_vector(31 downto 0);
ram_wb_adr_i: in std_logic_vector(BITS-1 downto 2);
ram_wb_sel_i: in std_logic_vector(3 downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(31 downto 0);
rom_wb_adr_i: in std_logic_vector(BITS-1 downto 2);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end component;
begin
w_clk <= not w_clk after period/2;
cpu: xtc
port map (
wb_clk_i => w_clk,
wb_rst_i => w_rst,
-- Master wishbone interface
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_sel_o => wb_sel,
wb_we_o => wb_we,
wb_stall_i => wb_stall,
-- ROM wb interface
rom_wb_ack_i => rom_wb_ack,
rom_wb_dat_i => rom_wb_read,
rom_wb_adr_o => rom_wb_adr,
rom_wb_cyc_o => rom_wb_cyc,
rom_wb_stb_o => rom_wb_stb,
rom_wb_stall_i => rom_wb_stall,
wb_inta_i => '0',
isnmi => '0'
);
myram: romram
generic map (
BITS => 15
)
port map (
ram_wb_clk_i => w_clk,
ram_wb_rst_i => w_rst,
ram_wb_ack_o => wb_ack,
ram_wb_dat_i => wb_write,
ram_wb_dat_o => wb_read,
ram_wb_adr_i => wb_address(14 downto 2),
ram_wb_cyc_i => wb_cyc,
ram_wb_stb_i => wb_stb,
ram_wb_sel_i => wb_sel,
ram_wb_we_i => wb_we,
ram_wb_stall_o => wb_stall,
rom_wb_clk_i => w_clk,
rom_wb_rst_i => w_rst,
rom_wb_ack_o => rom_wb_ack,
rom_wb_dat_o => rom_wb_read,
rom_wb_adr_i => rom_wb_adr(14 downto 2),
rom_wb_cyc_i => rom_wb_cyc,
rom_wb_stb_i => rom_wb_stb,
rom_wb_stall_o => rom_wb_stall
);
-- Reset procedure
process
begin
w_rst<='0';
wait for period;
w_rst<='1';
wait for period;
w_rst<='0';
wait;
end process;
end sim;
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- cond_init_2.c
-- arg = * data
-- reg1 = * cond
-- reg2 = * cond_attr
-- The return value should be the condattr->num set by either the
-- software main thread, or the bfl in case of simulation.
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_condattr_t * condattr = (hthread_condattr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the value of cond
thrd2intrfc_address <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_LOAD;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg1_next <= intrfc2thrd_value;
-- Read the value of cond_attr
thrd2intrfc_address <= arg + 4;
thrd2intrfc_opcode <= OPCODE_LOAD;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
-- hthread_condattr_init( data->attr );
when STATE_3 =>
reg2_next <= intrfc2thrd_value;
-- Push data->attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- Call hthread_condattr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CONDATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_5;
next_state <= WAIT_STATE;
-- hthread_cond_init( data->cond, data->attr );
when STATE_5 =>
-- Push data->attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- Push data->attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg1;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- Call hthread_condattr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- data->attr->num = 4;
when STATE_8 =>
-- Store '4' for the value of attr->num
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_value <= x"00000004";
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
--retVal = data->cond->num
when STATE_9 =>
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg1;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
package fifo_pkg is
end package;
package fifo_pkg is
END package;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory_matrix_tb is
end entity;
architecture memory_matrix_tb_arq of memory_matrix_tb is
signal finished : boolean := false;
signal x_write: std_logic_vector(9 downto 0) := (others => '0');
signal y_write: std_logic_vector(9 downto 0) := (others => '0');
signal write_data: std_logic_vector(0 downto 0) := (others => '0');
signal write_enable: std_logic := '0';
signal clk: std_logic := '0';
signal enable: std_logic := '0';
signal reset: std_logic := '0';
signal x_read: std_logic_vector(9 downto 0) := (others => '0');
signal y_read: std_logic_vector(9 downto 0) := (others => '0');
signal read_data : std_logic_vector(0 downto 0) := (others => '0');
component memory_matrix is
generic(ROWS: integer := 350; COLUMNS: integer := 350; CLK_DELAY_COUNT: integer := 9);
port(
x_write: in std_logic_vector(9 downto 0) := (others => '0');
y_write: in std_logic_vector(9 downto 0) := (others => '0');
write_data: in std_logic_vector(0 downto 0) := (others => '0');
write_enable: in std_logic := '0';
clk: in std_logic := '0';
enable: in std_logic := '0';
reset: in std_logic := '0';
x_read: in std_logic_vector(9 downto 0) := (others => '0');
y_read: in std_logic_vector(9 downto 0) := (others => '0');
read_data : out std_logic_vector(0 downto 0) := (others => '0')
);
end component;
begin
memory_matrix_0 : memory_matrix
generic map(CLK_DELAY_COUNT => 9)
port map(
x_write => x_write,
y_write => y_write,
write_data => write_data,
write_enable => write_enable,
clk => clk,
enable => enable,
reset => reset,
x_read => x_read,
y_read => y_read,
read_data => read_data
);
process(clk)
begin
if(not finished) then
clk <= not(clk) after 1 ns;
end if;
end process;
process
type pattern_type is record
xin : std_logic_vector(9 downto 0);
yin : std_logic_vector(9 downto 0);
wd : std_logic_vector(0 downto 0);
wen : std_logic;
xo : std_logic_vector(9 downto 0);
yo : std_logic_vector(9 downto 0);
dot : std_logic_vector(0 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("0000000100",
"0000000100",
"1",
'1',
"0000000000",
"0000000000",
"0"),
("0000000011",
"0000000011",
"1",
'1',
"0000000000",
"0000000000",
"0"),
("0000000000",
"0000000000",
"0",
'0',
"0000000100",
"0000000100",
"1"),
("0000000000",
"0000000000",
"0",
'0',
"0000000011",
"0000000011",
"1"),
("0000000000",
"0000000000",
"0",
'0',
"0000000011",
"0000000011",
"1"),
("0000000000",
"0000000000",
"0",
'0',
"0000000011",
"0000000011",
"1")
);
begin
reset <= '0';
enable <= '1';
for i in patterns'range loop
-- Set the inputs.
x_write <= patterns(i).xin;
y_write <= patterns(i).yin;
write_data <= patterns(i).wd;
write_enable <= patterns(i).wen;
x_read <= patterns(i).xo;
y_read <= patterns(i).yo;
enable <= '1';
wait for 20 ns;
assert patterns(i).dot = read_data report "BAD SAVED VALUE, EXPECTED: " & std_logic'image(patterns(i).dot(0)) & " GOT: " & std_logic'image(read_data(0));
-- Check the outputs.
end loop;
reset <= '1';
wait for 20 ns;
assert read_data = "0" report "BAD SAVED VALUE, EXPECTED: " & std_logic'image('0') & " GOT: " & std_logic'image(read_data(0));
finished <= true;
assert false report "end of test" severity note;
wait;
end process;
end;
|
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`protect begin_protected
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8000)
`protect data_block
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|
library verilog;
use verilog.vl_types.all;
entity AddrReg is
port(
AddrReg_in : in vl_logic_vector(31 downto 0);
AddrReg_write_en: in vl_logic;
Clk : in vl_logic;
AddrReg_out : out vl_logic_vector(31 downto 0)
);
end AddrReg;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DIO_MOD is
generic (
-- IO-REQ: 2 DWORD
WB_CONF_OFFSET: std_logic_vector(15 downto 2) := "00000000000000";
WB_CONF_DATA: std_logic_vector(15 downto 0) := "0000000000000010";
WB_ADDR_OFFSET: std_logic_vector(15 downto 2) := "00000000000000"
);
port (
OUT_EN: in std_logic;
SCLK_EDGE: in std_logic;
SCLK_STATE: in std_logic;
WB_CLK: in std_logic;
WB_RST: in std_logic;
WB_ADDR: in std_logic_vector(15 downto 2);
WB_DATA_OUT: out std_logic_vector(31 downto 0);
WB_DATA_IN: in std_logic_vector(31 downto 0);
WB_STB_RD: in std_logic;
WB_STB_WR: in std_logic;
SV : inout std_logic_vector(10 downto 3)
);
end;
architecture rtl of DIO_MOD is
constant OUT_TEST_PATTERN: std_logic_vector(7 downto 0) := "10110010";
constant IN_TEST_PATTERN: std_logic_vector(7 downto 0) := "10101100";
signal wb_data_mux : std_logic_vector(31 downto 0);
signal shift_cnt: std_logic_vector(5 downto 0);
signal bitcnt_sync: std_logic;
signal bitcnt_top: std_logic;
signal ssync: std_logic;
signal sclk: std_logic;
signal output_fault: std_logic;
signal output_fault_in: std_logic;
signal output_fault_sync: std_logic_vector(1 downto 0);
signal output_fault_dly: std_logic_vector(9 downto 0) := (others => '1');
signal si_out: std_logic;
signal so_out: std_logic;
signal so_out_data: std_logic_vector(39 downto 0);
signal so_out_shift: std_logic_vector(47 downto 0);
signal si_out_shift: std_logic_vector(7 downto 0);
signal out_data_error: std_logic;
signal si_in: std_logic;
signal so_in: std_logic;
signal so_in_shift: std_logic_vector(7 downto 0);
signal si_in_shift: std_logic_vector(47 downto 0);
signal si_in_data: std_logic_vector(39 downto 0);
signal in_data_error: std_logic;
signal output_fault_reg: std_logic;
signal out_data_error_reg: std_logic;
signal in_data_error_reg: std_logic;
begin
----------------------------------------------------------
--- bus logic
----------------------------------------------------------
P_WB_RD : process(WB_ADDR)
begin
case WB_ADDR is
when WB_CONF_OFFSET =>
wb_data_mux(15 downto 0) <= WB_CONF_DATA;
wb_data_mux(31 downto 16) <= WB_ADDR_OFFSET & "00";
when WB_ADDR_OFFSET =>
wb_data_mux <= si_in_data(31 downto 0);
when WB_ADDR_OFFSET + 1 =>
wb_data_mux <= (others => '0');
wb_data_mux(7 downto 0) <= si_in_data(39 downto 32);
wb_data_mux(16) <= output_fault_reg;
wb_data_mux(17) <= out_data_error_reg;
wb_data_mux(18) <= in_data_error_reg;
when others =>
wb_data_mux <= (others => '0');
end case;
end process;
P_WB_RD_REG : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
WB_DATA_OUT <= (others => '0');
elsif rising_edge(WB_CLK) then
if WB_STB_RD = '1' then
WB_DATA_OUT <= wb_data_mux;
end if;
end if;
end process;
P_PE_REG_WR : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
so_out_data <= (others => '0');
output_fault_reg <= '0';
out_data_error_reg <= '0';
in_data_error_reg <= '0';
elsif rising_edge(WB_CLK) then
-- reset error flags when output is disabled
if OUT_EN = '0' then
so_out_data <= (others => '0');
output_fault_reg <= '0';
out_data_error_reg <= '0';
in_data_error_reg <= '0';
end if;
-- set error flags on error
if output_fault = '1' then
output_fault_reg <= '1';
end if;
if out_data_error = '1' then
out_data_error_reg <= '1';
end if;
if in_data_error = '1' then
in_data_error_reg <= '1';
end if;
if WB_STB_WR = '1' then
case WB_ADDR is
when WB_ADDR_OFFSET =>
so_out_data(31 downto 0) <= WB_DATA_IN;
when WB_ADDR_OFFSET + 1 =>
so_out_data(39 downto 32) <= WB_DATA_IN(7 downto 0);
if WB_DATA_IN(16) = '1' then
output_fault_reg <= '0';
end if;
if WB_DATA_IN(17) = '1' then
out_data_error_reg <= '0';
end if;
if WB_DATA_IN(18) = '1' then
in_data_error_reg <= '0';
end if;
when others =>
end case;
end if;
end if;
end process;
----------------------------------------------------------
--- serial clock
----------------------------------------------------------
p_sclk: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
ssync <= '0';
sclk <= '1';
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' then
ssync <= '0';
sclk <= '1';
if SCLK_STATE = '1' then
if bitcnt_sync = '1' then
ssync <= '1';
else
sclk <= '0';
end if;
end if;
end if;
end if;
end process;
----------------------------------------------------------
--- shift counter
----------------------------------------------------------
p_bitcnt_cnt: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
shift_cnt <= (others => '0');
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' and SCLK_STATE = '1' then
if bitcnt_top = '1' then
shift_cnt <= (others => '0');
else
shift_cnt <= shift_cnt + 1;
end if;
end if;
end if;
end process;
bitcnt_sync <= '1' when shift_cnt = 47 else '0';
bitcnt_top <= '1' when shift_cnt = 48 else '0';
----------------------------------------------------------
--- output shift registers
----------------------------------------------------------
p_so_out_shift: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
so_out_shift <= (others => '0');
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' and SCLK_STATE = '0' then
if bitcnt_top = '1' then
so_out_shift <= OUT_TEST_PATTERN & so_out_data;
else
so_out_shift <= so_out_shift(46 downto 0) & "1";
end if;
end if;
end if;
end process;
so_out <= so_out_shift(47);
p_si_out_shift: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
si_out_shift <= (others => '0');
out_data_error <= '0';
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' and SCLK_STATE = '0' then
if bitcnt_sync = '1' then
if si_out_shift /= OUT_TEST_PATTERN then
out_data_error <= '1';
else
out_data_error <= '0';
end if;
si_out_shift <= (others => '0');
else
si_out_shift <= si_out_shift(6 downto 0) & si_out;
end if;
end if;
end if;
end process;
----------------------------------------------------------
--- input shift registers
----------------------------------------------------------
p_so_in_shift: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
so_in_shift <= (others => '0');
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' and SCLK_STATE = '0' then
if bitcnt_top = '1' then
so_in_shift <= IN_TEST_PATTERN;
else
so_in_shift <= so_in_shift(6 downto 0) & "0";
end if;
end if;
end if;
end process;
so_in <= so_in_shift(7);
p_si_in_shift: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
si_in_data <= (others => '0');
si_in_shift <= (others => '0');
in_data_error <= '0';
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' and SCLK_STATE = '0' then
if bitcnt_sync = '1' then
if si_in_shift(7 downto 0) /= IN_TEST_PATTERN then
in_data_error <= '1';
else
in_data_error <= '0';
si_in_data <= si_in_shift(47 downto 8);
end if;
si_in_shift <= (others => '0');
else
si_in_shift <= si_in_shift(46 downto 0) & si_in;
end if;
end if;
end if;
end process;
----------------------------------------------------------
--- output fault delay
----------------------------------------------------------
p_output_fault_sync: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
output_fault_sync <= (others => '0');
elsif rising_edge(WB_CLK) then
output_fault_sync <= output_fault_in & output_fault_sync(1);
end if;
end process;
p_output_fault_dly: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
output_fault_dly <= (others => '1');
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' and SCLK_STATE = '0' then
if output_fault_sync(0) = '1' then
if output_fault = '0' then
output_fault_dly <= output_fault_dly - 1;
end if;
else
output_fault_dly <= (others => '1');
end if;
end if;
end if;
end process;
output_fault <= '1' when output_fault_dly = 0 else '0';
----------------------------------------------------------
--- output mapping
----------------------------------------------------------
output_fault_in <= not SV(3);
si_in <= SV(5);
si_out <= not SV(6);
SV(4) <= OUT_EN;
SV(7) <= ssync;
SV(8) <= sclk;
SV(9) <= so_in;
SV(10) <= not so_out;
end;
|
--------------------------------------------------------------------------------
-- Baud Rate Counter --
--------------------------------------------------------------------------------
-- Copyright (C)2011 Mathias Hörtnagl <[email protected]> --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
generic(
FREQ : positive := 50; -- Clock frequency in MHz.
RATE : positive := 19200 -- Baud rate (times sampling rate).
);
port(
clk : in std_logic;
rst : in std_logic;
tick : out std_logic
);
end counter;
architecture rtl of counter is
constant MAX : positive := (FREQ*1000000)/(RATE*16);
signal c, cin : natural range 0 to MAX;
begin
tick <= '1' when c = MAX else '0';
cin <= 0 when c = MAX else c + 1;
reg : process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
c <= 0;
else
c <= cin;
end if;
end if;
end process;
end rtl; |
package body fifo_pkg is
end package body;
package body fifo_pkg is
end package body;
package body fifo_pkg is
end package body;
package body fifo_pkg is
end package body;
|
-------------------------------------------------------------------------------
--
-- Title : q
-- Design : lab1
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\lab1\lab1\compile\q1.vhd
-- Generated : Tue Sep 23 20:38:45 2014
-- From : c:\My_Designs\lab1\lab1\src\q1.bde
-- By : Bde2Vhdl ver. 2.6
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
-- Design unit header --
library IEEE;
use IEEE.std_logic_1164.all;
entity q is
port(
in1 : in STD_LOGIC;
in2 : in STD_LOGIC;
in3 : in STD_LOGIC;
Q : out STD_LOGIC
);
end q;
architecture q of q is
---- Signal declarations used on the diagram ----
signal NET251 : STD_LOGIC;
signal NET265 : STD_LOGIC;
signal NET274 : STD_LOGIC;
begin
---- Component instantiations ----
NET274 <= in2 and in1;
NET265 <= in3 and NET251;
NET251 <= not(in2);
Q <= NET265 or NET274;
end q;
|
-------------------------------------------------------------------------------
--
-- Title : q
-- Design : lab1
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\lab1\lab1\compile\q1.vhd
-- Generated : Tue Sep 23 20:38:45 2014
-- From : c:\My_Designs\lab1\lab1\src\q1.bde
-- By : Bde2Vhdl ver. 2.6
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
-- Design unit header --
library IEEE;
use IEEE.std_logic_1164.all;
entity q is
port(
in1 : in STD_LOGIC;
in2 : in STD_LOGIC;
in3 : in STD_LOGIC;
Q : out STD_LOGIC
);
end q;
architecture q of q is
---- Signal declarations used on the diagram ----
signal NET251 : STD_LOGIC;
signal NET265 : STD_LOGIC;
signal NET274 : STD_LOGIC;
begin
---- Component instantiations ----
NET274 <= in2 and in1;
NET265 <= in3 and NET251;
NET251 <= not(in2);
Q <= NET265 or NET274;
end q;
|
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
package mypack is
type MEM_CTL is record
act: std_ulogic;
write: std_ulogic;
addr: u8;
wdata: u8;
end record;
type MEM_RES is record
valid: std_ulogic;
busy: std_ulogic;
rdata: u8;
end record;
type MyEnum is (
MyEnum_one,
MyEnum_two,
MyEnum_three);
subtype myVec55 is unsigned(54 downto 0);
type myArr256_u8 is array(0 to 255) of u8;
function DoXorAnd (aa : u8; bb : u8; isXor : std_ulogic) return u8;
end package;
package body mypack is
function DoXorAnd (aa : u8; bb : u8; isXor : std_ulogic) return u8 is
variable result: u8;
begin
result := X"00"; -- local-var zero-init
if (isXor = '1') then
result := (aa xor bb);
else
result := (aa and bb);
end if;
end;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1625.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s12b00x00p03n01i01625pkg is
end c08s12b00x00p03n01i01625pkg;
package body c08s12b00x00p03n01i01625pkg is
return true; -- illegal in package
body
end c08s12b00x00p03n01i01625pkg;
ENTITY c08s12b00x00p03n01i01625ent IS
END c08s12b00x00p03n01i01625ent;
ARCHITECTURE c08s12b00x00p03n01i01625arch OF c08s12b00x00p03n01i01625ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01625 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01625arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1625.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s12b00x00p03n01i01625pkg is
end c08s12b00x00p03n01i01625pkg;
package body c08s12b00x00p03n01i01625pkg is
return true; -- illegal in package
body
end c08s12b00x00p03n01i01625pkg;
ENTITY c08s12b00x00p03n01i01625ent IS
END c08s12b00x00p03n01i01625ent;
ARCHITECTURE c08s12b00x00p03n01i01625arch OF c08s12b00x00p03n01i01625ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01625 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01625arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1625.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s12b00x00p03n01i01625pkg is
end c08s12b00x00p03n01i01625pkg;
package body c08s12b00x00p03n01i01625pkg is
return true; -- illegal in package
body
end c08s12b00x00p03n01i01625pkg;
ENTITY c08s12b00x00p03n01i01625ent IS
END c08s12b00x00p03n01i01625ent;
ARCHITECTURE c08s12b00x00p03n01i01625arch OF c08s12b00x00p03n01i01625ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01625 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01625arch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Feb 08 00:47:23 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Zybo-Open-Source-Video-IP-Toolbox/video_processing_examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_sim_netlist.vhdl
-- Design : system_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "system_processing_system7_0_0.hwdef";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7";
attribute POWER : string;
attribute POWER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
end system_processing_system7_0_0_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_processing_system7_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_processing_system7_0_0 : entity is "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_processing_system7_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_processing_system7_0_0 : entity is "processing_system7_v5_5_processing_system7,Vivado 2016.4";
end system_processing_system7_0_0;
architecture STRUCTURE of system_processing_system7_0_0 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "system_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
pullup_MIO_0inst: unisim.vcomponents.PULLUP
port map (
O => MIO(0)
);
pullup_MIO_9inst: unisim.vcomponents.PULLUP
port map (
O => MIO(9)
);
pullup_MIO_10inst: unisim.vcomponents.PULLUP
port map (
O => MIO(10)
);
pullup_MIO_11inst: unisim.vcomponents.PULLUP
port map (
O => MIO(11)
);
pullup_MIO_12inst: unisim.vcomponents.PULLUP
port map (
O => MIO(12)
);
pullup_MIO_13inst: unisim.vcomponents.PULLUP
port map (
O => MIO(13)
);
pullup_MIO_14inst: unisim.vcomponents.PULLUP
port map (
O => MIO(14)
);
pullup_MIO_15inst: unisim.vcomponents.PULLUP
port map (
O => MIO(15)
);
pullup_MIO_46inst: unisim.vcomponents.PULLUP
port map (
O => MIO(46)
);
inst: entity work.system_processing_system7_0_0_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => SDIO0_WP,
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
|
entity test is
package a is new b generic map(c => ((bar baz, qux zzz)) foo);
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2mig
-- File: ahb2mig.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: AHB wrapper for Xilinx Virtex6 DDR2/3 MIG
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package ml605 is
constant nCS_PER_RANK : integer := 1;
constant BANK_WIDTH : integer := 3;
constant CK_WIDTH : integer := 1;
constant CKE_WIDTH : integer := 1;
constant COL_WIDTH : integer := 10;
constant CS_WIDTH : integer := 1;
constant DM_WIDTH : integer := 8;
constant DQ_WIDTH : integer := 64;
constant DQS_WIDTH : integer := 8;
constant ROW_WIDTH : integer := 13;
constant PAYLOAD_WIDTH : integer := 64;
constant ADDR_WIDTH : integer := 27;
type mig_app_in_type is record
app_wdf_wren : std_logic;
app_wdf_data : std_logic_vector((4*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_mask : std_logic_vector((4*PAYLOAD_WIDTH)/8-1 downto 0);
app_wdf_end : std_logic;
app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : std_logic_vector(2 downto 0);
app_en : std_logic;
end record;
type mig_app_out_type is record
app_rdy : std_logic;
app_wdf_rdy : std_logic;
app_rd_data : std_logic_vector((4*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_valid : std_logic;
end record;
component ahb2mig_ml605
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#e00#;
MHz : integer := 100;
Mbyte : integer := 512;
nosync : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
migi : out mig_app_in_type;
migo : in mig_app_out_type
);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use work.ml605.all;
entity ahb2mig_ml605 is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#e00#;
MHz : integer := 100;
Mbyte : integer := 512;
nosync : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
migi : out mig_app_in_type;
migo : in mig_app_out_type
);
end;
architecture rtl of ahb2mig_ml605 is
constant REVISION : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type ddr_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
constant abuf : integer := 6;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
end record;
-- local registers
type mem is array(0 to 15) of std_logic_vector(31 downto 0);
type wrm is array(0 to 15) of std_logic_vector(3 downto 0);
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
startsd : std_ulogic;
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(127 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(2 downto 0);
acc : access_param;
sync : std_ulogic;
hwdata : mem;
write : wrm;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
hrdata : std_logic_vector(511 downto 0);
sync : std_ulogic;
dstate : ahb_state_type;
end record;
signal vcc, clk_ahb1, clk_ahb2 : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal hwdata, hwdatab : std_logic_vector(127 downto 0);
begin
vcc <= '1';
ahb_ctrl : process(rst, ahbsi, r, ra, migo, hwdata)
variable va : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable ready : std_logic;
variable tmp : std_logic_vector(3 downto 0);
variable waddr : integer;
variable rdata : std_logic_vector(127 downto 0);
begin
va := ra; va.hresp := HRESP_OKAY;
tmp := (others => '0');
case ra.raddr(3 downto 2) is
when "00" => rdata := r.hrdata(127 downto 0);
when "01" => rdata := r.hrdata(255 downto 128);
when "10" => rdata := r.hrdata(383 downto 256);
when others => rdata := r.hrdata(511 downto 384);
end case;
if AHBDW > 64 and ra.size = HSIZE_4WORD then
va.hrdata := rdata(31 downto 0) & rdata(63 downto 32) & rdata(95 downto 64) & rdata(127 downto 96);
elsif AHBDW > 32 and ra.size = HSIZE_DWORD then
if ra.raddr(1) = '1' then va.hrdata(63 downto 0) := rdata(95 downto 64) & rdata(127 downto 96);
else va.hrdata(63 downto 0) := rdata(31 downto 0) & rdata(63 downto 32); end if;
va.hrdata(127 downto 64) := va.hrdata(63 downto 0);
else
case ra.raddr(1 downto 0) is
when "00" => va.hrdata(31 downto 0) := rdata(31 downto 0);
when "01" => va.hrdata(31 downto 0) := rdata(63 downto 32);
when "10" => va.hrdata(31 downto 0) := rdata(95 downto 64);
when others => va.hrdata(31 downto 0) := rdata(127 downto 96);
end case;
va.hrdata(127 downto 32) := va.hrdata(31 downto 0) &
va.hrdata(31 downto 0) &
va.hrdata(31 downto 0);
end if;
if nosync = 0 then
va.sync := r.startsd;
if ra.startsd = ra.sync then ready := '1';
else ready := '0'; end if;
else
if ra.startsd = r.startsd then ready := '1';
else ready := '0'; end if;
end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.htrans := ahbsi.htrans; va.haddr := ahbsi.haddr;
va.size := ahbsi.hsize(2 downto 0); va.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
va.hsel := '1'; va.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then va.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
va.write := (others => "0000");
if ((va.hsel and va.htrans(1)) = '1') then
if va.hwrite = '0' then
va.state := rhold; va.startsd := not ra.startsd;
else
va.state := dwrite; va.hready := '1';
end if;
end if;
va.raddr := ra.haddr(7 downto 2);
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.acc := (va.haddr, va.size, va.hwrite);
end if;
when rhold =>
va.raddr := ra.haddr(7 downto 2);
if ready = '1' then
va.state := dread; va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
end if;
when dread =>
va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
if ((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.raddr(3 downto 0) = "0000") then
va.state := midle; va.hready := '0';
end if;
va.acc := (va.haddr, va.size, va.hwrite);
when dwrite =>
va.raddr := ra.haddr(7 downto 2); va.hready := '1';
if (((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.haddr(5 downto 2) = "1111")
or (AHBDW > 32 and ra.haddr(5 downto 2) = "1110" and andv(ra.size(1 downto 0)) = '1')
or (AHBDW > 64 and ra.haddr(5 downto 2) = "1100" and ra.size(2) = '1')) then
va.startsd := not ra.startsd; va.state := whold1;
va.hready := '0';
end if;
tmp := decode(ra.haddr(1 downto 0));
waddr := conv_integer(ra.haddr(5 downto 2));
va.hwdata(waddr) := hwdata(31 downto 0);
case ra.size is
when "000" => va.write(waddr) := tmp(0) & tmp(1) & tmp(2) & tmp(3);
when "001" => va.write(waddr) := tmp(0) & tmp(0) & tmp(2) & tmp(2);
when "010" => va.write(waddr) := "1111";
when "011" => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
when others => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.write(waddr+2) := "1111"; va.write(waddr+3) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
va.hwdata(waddr+2) := hwdata((95 mod AHBDW) downto (64 mod AHBDW));
va.hwdata(waddr+3) := hwdata((127 mod AHBDW) downto (96 mod AHBDW));
end case;
when whold1 =>
va.state := whold2;
when whold2 =>
if ready = '1' then
va.state := midle; va.acc := (va.haddr, va.size, va.hwrite);
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then va.hready := '1'; end if;
end if;
if rst = '0' then
va.hsel := '0';
va.hready := '1';
va.state := midle;
va.startsd := '0';
va.acc.hwrite := '0';
va.acc.haddr := (others => '0');
end if;
rai <= va;
end process;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= ahbdrivedata(ra.hrdata);
migi.app_addr <= '0' & ra.acc.haddr(28 downto 6) & "000";
ddr_ctrl : process(rst, r, ra, migo)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable app_en : std_ulogic;
variable app_cmd : std_logic_vector(2 downto 0);
variable app_wdf_mask : std_logic_vector(31 downto 0);
variable app_wdf_wren : std_ulogic;
variable app_wdf_end : std_ulogic;
variable app_wdf_data : std_logic_vector(255 downto 0);
begin
-- Variable default settings to avoid latches
v := r; app_en := '0'; app_cmd := "000";
app_wdf_wren := '0'; app_wdf_mask := ra.write(7) & ra.write(6) & ra.write(5) &
ra.write(4) & ra.write(3) & ra.write(2) & ra.write(1) & ra.write(0);
app_wdf_data := ra.hwdata(7) & ra.hwdata(6) & ra.hwdata(5) & ra.hwdata(4) &
ra.hwdata(3) & ra.hwdata(2) & ra.hwdata(1) & ra.hwdata(0);
if ra.acc.hwrite = '0' then app_cmd(0) := '1'; else app_cmd(0) := '0'; end if;
app_wdf_end := '0'; v.sync := ra.startsd;
if nosync = 0 then
if r.startsd /= r.sync then startsd := '1';
else startsd := '0'; end if;
else
if ra.startsd /= r.startsd then startsd := '1';
else startsd := '0'; end if;
end if;
case r.dstate is
when midle =>
if startsd = '1' then app_en := '1'; end if;
if (migo.app_rdy and app_en) = '1' then
if ra.acc.hwrite = '0' then v.dstate := dread;
else v.dstate := dwrite; end if;
end if;
when dread =>
if migo.app_rd_data_valid = '1' then
v.hrdata(255 downto 0) := migo.app_rd_data;
v.dstate := rhold;
end if;
when rhold =>
v.hrdata(511 downto 256) := migo.app_rd_data;
v.dstate := midle;
v.startsd := not r.startsd;
when dwrite =>
app_wdf_wren := '1';
if migo.app_wdf_rdy = '1' then
v.dstate := whold1;
end if;
when whold1 =>
app_wdf_wren := '1'; app_wdf_end := '1';
app_wdf_mask := ra.write(15) & ra.write(14) & ra.write(13) &
ra.write(12) & ra.write(11) & ra.write(10) & ra.write(9) & ra.write(8);
app_wdf_data := ra.hwdata(15) & ra.hwdata(14) & ra.hwdata(13) & ra.hwdata(12) &
ra.hwdata(11) & ra.hwdata(10) & ra.hwdata(9) & ra.hwdata(8);
if migo.app_wdf_rdy = '1' then
v.startsd := not r.startsd;
v.dstate := midle;
end if;
when others =>
end case;
-- reset
if rst = '0' then
v.startsd := '0';
end if;
ri <= v;
migi.app_cmd <= app_cmd;
migi.app_en <= app_en;
migi.app_wdf_wren <= app_wdf_wren;
migi.app_wdf_end <= app_wdf_end;
migi.app_wdf_mask <= not app_wdf_mask;
migi.app_wdf_data <= app_wdf_data;
end process;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
clk_ahb1 <= clk_ahb; clk_ahb2 <= clk_ahb1; -- sync clock deltas
ahbregs : process(clk_ahb2) begin
if rising_edge(clk_ahb2) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst) begin
if rising_edge(clk_ddr) then
r <= ri;
end if;
end process;
-- Write data selection.
AHB32: if AHBDW = 32 generate
hwdata <= ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0) &
ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0);
end generate AHB32;
AHB64: if AHBDW = 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(63 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab(63 downto 0) <= ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(1 downto 0) = "11") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(31 downto 0) & hwdatab(63 downto 32);
end generate AHB64;
AHBWIDE: if AHBDW > 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(127 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab <= ahbread4word(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(2) = '1') else
(ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2))) when (ra.size = "011") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(95 downto 64) & hwdatab(127 downto 96);
end generate AHBWIDE;
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "mig2ahb" & tost(hindex) & ": 64-bit DDR2/3 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2111.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02111ent IS
END c07s02b04x00p20n01i02111ent;
ARCHITECTURE c07s02b04x00p20n01i02111arch OF c07s02b04x00p20n01i02111ent IS
TYPE time_v is array (integer range <>) of time;
SUBTYPE time_null is time_v (1 to 0);
SUBTYPE time_4 is time_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : time_4;
variable l_operand : time_4 := ( 78 ns , 23 ns , 78 ns , 23 ns );
variable r_operand : time_null;
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT((result = ( 78 ns, 23 ns, 78 ns, 23 ns )) and (result(1) = 78 ns))
report "***PASSED TEST: c07s02b04x00p20n01i02111"
severity NOTE;
assert ((result = ( 78 ns, 23 ns, 78 ns, 23 ns )) and (result(1) = 78 ns))
report "***FAILED TEST: c07s02b04x00p20n01i02111 - Concatenation of null and TIME array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02111arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2111.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02111ent IS
END c07s02b04x00p20n01i02111ent;
ARCHITECTURE c07s02b04x00p20n01i02111arch OF c07s02b04x00p20n01i02111ent IS
TYPE time_v is array (integer range <>) of time;
SUBTYPE time_null is time_v (1 to 0);
SUBTYPE time_4 is time_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : time_4;
variable l_operand : time_4 := ( 78 ns , 23 ns , 78 ns , 23 ns );
variable r_operand : time_null;
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT((result = ( 78 ns, 23 ns, 78 ns, 23 ns )) and (result(1) = 78 ns))
report "***PASSED TEST: c07s02b04x00p20n01i02111"
severity NOTE;
assert ((result = ( 78 ns, 23 ns, 78 ns, 23 ns )) and (result(1) = 78 ns))
report "***FAILED TEST: c07s02b04x00p20n01i02111 - Concatenation of null and TIME array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02111arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2111.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02111ent IS
END c07s02b04x00p20n01i02111ent;
ARCHITECTURE c07s02b04x00p20n01i02111arch OF c07s02b04x00p20n01i02111ent IS
TYPE time_v is array (integer range <>) of time;
SUBTYPE time_null is time_v (1 to 0);
SUBTYPE time_4 is time_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : time_4;
variable l_operand : time_4 := ( 78 ns , 23 ns , 78 ns , 23 ns );
variable r_operand : time_null;
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT((result = ( 78 ns, 23 ns, 78 ns, 23 ns )) and (result(1) = 78 ns))
report "***PASSED TEST: c07s02b04x00p20n01i02111"
severity NOTE;
assert ((result = ( 78 ns, 23 ns, 78 ns, 23 ns )) and (result(1) = 78 ns))
report "***FAILED TEST: c07s02b04x00p20n01i02111 - Concatenation of null and TIME array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02111arch;
|
--translates the input Score Digits into SSD compatible format
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BCD2SSD is
Port ( Data_In1 : in STD_LOGIC_VECTOR (3 downto 0);
Data_In2 : in STD_LOGIC_VECTOR (3 downto 0);
Player_in : in STD_LOGIC_VECTOR (15 downto 0);
SSDisplay : out STD_LOGIC_VECTOR (31 downto 0)
);
end BCD2SSD;
architecture Behavioral of BCD2SSD is
signal SSD1: STD_LOGIC_VECTOR (7 downto 0);
signal SSD2: STD_LOGIC_VECTOR (7 downto 0);
begin
process (Data_In1,Data_In2)
begin
if (Data_In1 = "0000") then
SSD1<= "00000011";-----0
elsif Data_In1 = "0001" then
SSD1 <= "10011111";-----1
elsif Data_In1 = "0010" then
SSD1 <= "00100101";-----2
elsif Data_In1 = "0011" then
SSD1 <= "00001101";-----3
elsif Data_In1 = "0100" then
SSD1 <= "10011001";-----4
elsif Data_In1 = "0101" then
SSD1 <= "01001001";-----5
elsif Data_In1 = "0110" then
SSD1 <= "01000001";-----6
elsif Data_In1 = "0111" then
SSD1 <= "00011111";-----7
elsif Data_In1 = "1000" then
SSD1 <= "00000001";-----8
elsif Data_In1 = "1001" then
SSD1 <= "00001001";-----9
else
SSD1 <= "11111110";-----decimal point
end if;
if (Data_In2 = "0000") then
SSD2 <= "00000011";-----0
elsif Data_In2 = "0001" then
SSD2 <= "10011111";-----1
elsif Data_In2 = "0010" then
SSD2 <= "00100101";-----2
elsif Data_In2 = "0011" then
SSD2 <= "00001101";-----3
elsif Data_In2 = "0100" then
SSD2 <= "10011001";-----4
elsif Data_In2 = "0101" then
SSD2 <= "01001001";-----5
elsif Data_In2 = "0110" then
SSD2 <= "01000001";-----6
elsif Data_In2 = "0111" then
SSD2 <= "00011111";-----7
elsif Data_In2 = "1000" then
SSD2 <= "00000001";-----8
elsif Data_In2 = "1001" then
SSD2 <= "00001001";-----9
else
SSD2 <= "11111110";-----decimal point
end if;
end process;
SSDisplay<=Player_in & SSD1 & SSD2;
end Behavioral; |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:54 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/title2_1/title2_stub.vhdl
-- Design : title2
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity title2 is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end title2;
architecture stub of title2 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[13:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:54 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/title2_1/title2_stub.vhdl
-- Design : title2
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity title2 is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end title2;
architecture stub of title2 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[13:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
--###############################
--# Project Name :
--# File :
--# Author :
--# Description :
--# Modification History
--#
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_MPU6050_1 is
end tb_MPU6050_1;
architecture stimulus of tb_MPU6050_1 is
-- COMPONENTS --
component MPU6050
port(
MCLK : in std_logic;
nRST : in std_logic;
TIC : in std_logic;
SRST : out std_logic;
DOUT : out std_logic_vector(7 downto 0);
RD : out std_logic;
WE : out std_logic;
QUEUED : in std_logic;
NACK : in std_logic;
STOP : in std_logic;
DATA_VALID : in std_logic;
DIN : in std_logic_vector(7 downto 0);
ADR : out std_logic_vector(3 downto 0);
DATA : out std_logic_vector(7 downto 0);
LOAD : out std_logic;
COMPLETED : out std_logic;
RESCAN : in std_logic
);
end component;
component I2CMASTER
generic(
DEVICE : std_logic_vector(7 downto 0)
);
port(
MCLK : in std_logic;
nRST : in std_logic;
SRST : in std_logic;
TIC : in std_logic;
DIN : in std_logic_vector(7 downto 0);
DOUT : out std_logic_vector(7 downto 0);
RD : in std_logic;
WE : in std_logic;
NACK : out std_logic;
QUEUED : out std_logic;
DATA_VALID : out std_logic;
STATUS : out std_logic_vector(2 downto 0);
STOP : out std_logic;
SCL_IN : in std_logic;
SCL_OUT : out std_logic;
SDA_IN : in std_logic;
SDA_OUT : out std_logic
);
end component;
--
-- SIGNALS --
signal MCLK : std_logic;
signal nRST : std_logic;
signal TIC : std_logic;
signal SRST : std_logic;
signal DOUT : std_logic_vector(7 downto 0);
signal RD : std_logic;
signal WE : std_logic;
signal QUEUED : std_logic;
signal NACK : std_logic;
signal STOP : std_logic;
signal DATA_VALID : std_logic;
signal DIN : std_logic_vector(7 downto 0);
signal ADR : std_logic_vector(3 downto 0);
signal DATA : std_logic_vector(7 downto 0);
signal LOAD : std_logic;
signal COMPLETED : std_logic;
signal RESCAN : std_logic;
signal STATUS : std_logic_vector(2 downto 0);
signal SCL_IN : std_logic;
signal SCL_OUT : std_logic;
signal SDA_IN : std_logic;
signal SDA_OUT : std_logic;
--
signal RUNNING : std_logic := '1';
signal counter : std_logic_vector(7 downto 0);
begin
-- PORT MAP --
I_MPU6050_0 : MPU6050
port map (
MCLK => MCLK,
nRST => nRST,
TIC => TIC,
SRST => SRST,
DOUT => DIN,
RD => RD,
WE => WE,
QUEUED => QUEUED,
NACK => NACK,
STOP => STOP,
DATA_VALID => DATA_VALID,
DIN => DOUT,
ADR => ADR,
DATA => DATA,
LOAD => LOAD,
COMPLETED => COMPLETED,
RESCAN => RESCAN
);
-- PORT MAP --
I_I2CMASTER_0 : I2CMASTER
generic map (
DEVICE => x"68"
)
port map (
MCLK => MCLK,
nRST => nRST,
SRST => SRST,
TIC => TIC,
DIN => DIN,
DOUT => DOUT,
RD => RD,
WE => WE,
NACK => NACK,
QUEUED => QUEUED,
DATA_VALID => DATA_VALID,
STOP => STOP,
STATUS => STATUS,
SCL_IN => SCL_IN,
SCL_OUT => SCL_OUT,
SDA_IN => SDA_IN,
SDA_OUT => SDA_OUT
);
--
TIC <= counter(7) and counter(5); -- 2.56 + 0.64 uS (~300 khz ) for ~100 kbit
GEN: process(MCLK, nRST)
begin
if (nRST = '0') then
counter <= (others=>'0');
elsif (MCLK'event and MCLK='1') then
if (TIC = '1') then
counter <= (others=>'0');
else
counter <= std_logic_vector(to_unsigned(to_integer(unsigned( counter )) + 1, 8));
end if;
end if;
end process GEN;
--
CLOCK: process
begin
while (RUNNING = '1') loop
MCLK <= '1';
wait for 10 ns;
MCLK <= '0';
wait for 10 ns;
end loop;
wait;
end process CLOCK;
GO: process
begin
nRST <= '0';
RESCAN <= '0';
SDA_IN <= '1';
SCL_IN <= '0';
wait for 1000 ns;
nRST <= '1';
wait until NACK='1';
wait until NACK='1';
wait until NACK='1';
RUNNING <= '0';
wait;
end process GO;
end stimulus;
|
entity test is
subtype t is foo(open);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY framer is
generic(N : integer := 16);
port(clk : in std_ulogic;
sin : in std_ulogic;
resetb : in std_ulogic;
SOUT : out std_ulogic;
clk_div_8 : out std_ulogic;
decode_F628_out : out std_ulogic);
end framer;
architecture behavior of framer is
signal shiftreg_16 : std_ulogic_vector(15 downto 0);
constant F628 : std_ulogic_vector (15 downto 0) := x"F628";
signal decode_F628 : std_ulogic;
signal parallel_reg : std_ulogic_vector (7 downto 0);
signal parallel_clk : std_ulogic;
signal count_4bit : std_ulogic_vector (3 downto 0);
signal count_4bit_int : natural;
signal bit_counter : integer;
begin
shiftin: process (clk, resetb)
begin
if (resetb = '0') then
SOUT <= '0';
shiftreg_16 <= (others => '0');
elsif rising_edge(CLK) then
shiftreg_16 <= shiftreg_16(14 downto 0) & SIN;
SOUT <= shiftreg_16(N-1);
end if;
end process shiftin;
decode_A1A2: process (shiftreg_16)
begin
if (shiftreg_16 = F628) then
decode_F628 <= '1';
else
decode_F628 <= '0';
end if;
end process;
decode_F628_out <= decode_F628;
par_load: process (clk, resetb)
begin
if (resetb = '0') then
bit_counter <= 0;
elsif rising_edge (clk) then
if (decode_F628 = '1') then
bit_counter <= 0;
elsif (bit_counter = 7)then
bit_counter <= 0;
else
bit_counter <= bit_counter + 1 mod 8;
end if;
end if;
end process;
count_4bit <= std_ulogic_vector(to_unsigned (count_4bit_int,4));
clk_div_8 <= count_4bit(2);
process (clk, resetb)
begin
if (resetb = '0') then
count_4bit_int <= 0;
elsif rising_edge (clk) then
if (decode_F628 = '1') then
count_4bit_int <= 0;
elsif (count_4bit_int = 15) then
count_4bit_int <= 0;
else
count_4bit_int <= count_4bit_int + 1;
end if;
end if;
end process;
process (clk, resetb)
begin
if (resetb = '0') then
parallel_reg <= (others => '0');
elsif rising_edge (clk) then
if (decode_F628= '1') then
parallel_reg <= (shiftreg_16 (15 downto 8));
elsif (bit_counter = 7) then
parallel_reg <= (shiftreg_16 (15 downto 8));
end if;
end if;
end process;
end behavior;
|
entity sub2 is
port (
x0, x1 : in bit;
y0, y1 : out bit );
end entity;
architecture test of sub2 is
begin
y0 <= x0 after 0 ns;
y1 <= not x1 after 0 ns;
end architecture;
-------------------------------------------------------------------------------
entity sub is
port (
x : in bit_vector(1 downto 0);
y : out bit_vector(1 downto 0) );
end entity;
architecture test1 of sub is
begin
y(0) <= x(0) after 0 ns;
y(1) <= not x(1) after 0 ns;
end architecture;
architecture test2 of sub is
begin
sub2_i: entity work.sub2
port map (
x0 => x(0),
x1 => x(1),
y0 => y(0),
y1 => y(1) );
end architecture;
-------------------------------------------------------------------------------
entity elab24 is
end entity;
architecture test of elab24 is
begin
test_a: block is
signal x0, x1, y0, y1 : bit;
begin
sub_i: entity work.sub(test1)
port map (
x(0) => x0,
x(1) => x1,
y(0) => y0,
y(1) => y1 );
process is
begin
x0 <= '1';
wait for 2 ns;
assert y0 = '1';
wait;
end process;
end block;
test_b: block is
signal x0, x1, y0, y1 : bit;
begin
sub_i: entity work.sub(test2)
port map (
x(0) => x0,
x(1) => x1,
y(0) => y0,
y(1) => y1 );
process is
begin
x0 <= '1';
wait for 2 ns;
assert y0 = '1';
wait;
end process;
end block;
end architecture;
|
entity sub2 is
port (
x0, x1 : in bit;
y0, y1 : out bit );
end entity;
architecture test of sub2 is
begin
y0 <= x0 after 0 ns;
y1 <= not x1 after 0 ns;
end architecture;
-------------------------------------------------------------------------------
entity sub is
port (
x : in bit_vector(1 downto 0);
y : out bit_vector(1 downto 0) );
end entity;
architecture test1 of sub is
begin
y(0) <= x(0) after 0 ns;
y(1) <= not x(1) after 0 ns;
end architecture;
architecture test2 of sub is
begin
sub2_i: entity work.sub2
port map (
x0 => x(0),
x1 => x(1),
y0 => y(0),
y1 => y(1) );
end architecture;
-------------------------------------------------------------------------------
entity elab24 is
end entity;
architecture test of elab24 is
begin
test_a: block is
signal x0, x1, y0, y1 : bit;
begin
sub_i: entity work.sub(test1)
port map (
x(0) => x0,
x(1) => x1,
y(0) => y0,
y(1) => y1 );
process is
begin
x0 <= '1';
wait for 2 ns;
assert y0 = '1';
wait;
end process;
end block;
test_b: block is
signal x0, x1, y0, y1 : bit;
begin
sub_i: entity work.sub(test2)
port map (
x(0) => x0,
x(1) => x1,
y(0) => y0,
y(1) => y1 );
process is
begin
x0 <= '1';
wait for 2 ns;
assert y0 = '1';
wait;
end process;
end block;
end architecture;
|
entity sub2 is
port (
x0, x1 : in bit;
y0, y1 : out bit );
end entity;
architecture test of sub2 is
begin
y0 <= x0 after 0 ns;
y1 <= not x1 after 0 ns;
end architecture;
-------------------------------------------------------------------------------
entity sub is
port (
x : in bit_vector(1 downto 0);
y : out bit_vector(1 downto 0) );
end entity;
architecture test1 of sub is
begin
y(0) <= x(0) after 0 ns;
y(1) <= not x(1) after 0 ns;
end architecture;
architecture test2 of sub is
begin
sub2_i: entity work.sub2
port map (
x0 => x(0),
x1 => x(1),
y0 => y(0),
y1 => y(1) );
end architecture;
-------------------------------------------------------------------------------
entity elab24 is
end entity;
architecture test of elab24 is
begin
test_a: block is
signal x0, x1, y0, y1 : bit;
begin
sub_i: entity work.sub(test1)
port map (
x(0) => x0,
x(1) => x1,
y(0) => y0,
y(1) => y1 );
process is
begin
x0 <= '1';
wait for 2 ns;
assert y0 = '1';
wait;
end process;
end block;
test_b: block is
signal x0, x1, y0, y1 : bit;
begin
sub_i: entity work.sub(test2)
port map (
x(0) => x0,
x(1) => x1,
y(0) => y0,
y(1) => y1 );
process is
begin
x0 <= '1';
wait for 2 ns;
assert y0 = '1';
wait;
end process;
end block;
end architecture;
|
entity sub2 is
port (
x0, x1 : in bit;
y0, y1 : out bit );
end entity;
architecture test of sub2 is
begin
y0 <= x0 after 0 ns;
y1 <= not x1 after 0 ns;
end architecture;
-------------------------------------------------------------------------------
entity sub is
port (
x : in bit_vector(1 downto 0);
y : out bit_vector(1 downto 0) );
end entity;
architecture test1 of sub is
begin
y(0) <= x(0) after 0 ns;
y(1) <= not x(1) after 0 ns;
end architecture;
architecture test2 of sub is
begin
sub2_i: entity work.sub2
port map (
x0 => x(0),
x1 => x(1),
y0 => y(0),
y1 => y(1) );
end architecture;
-------------------------------------------------------------------------------
entity elab24 is
end entity;
architecture test of elab24 is
begin
test_a: block is
signal x0, x1, y0, y1 : bit;
begin
sub_i: entity work.sub(test1)
port map (
x(0) => x0,
x(1) => x1,
y(0) => y0,
y(1) => y1 );
process is
begin
x0 <= '1';
wait for 2 ns;
assert y0 = '1';
wait;
end process;
end block;
test_b: block is
signal x0, x1, y0, y1 : bit;
begin
sub_i: entity work.sub(test2)
port map (
x(0) => x0,
x(1) => x1,
y(0) => y0,
y(1) => y1 );
process is
begin
x0 <= '1';
wait for 2 ns;
assert y0 = '1';
wait;
end process;
end block;
end architecture;
|
entity sub2 is
port (
x0, x1 : in bit;
y0, y1 : out bit );
end entity;
architecture test of sub2 is
begin
y0 <= x0 after 0 ns;
y1 <= not x1 after 0 ns;
end architecture;
-------------------------------------------------------------------------------
entity sub is
port (
x : in bit_vector(1 downto 0);
y : out bit_vector(1 downto 0) );
end entity;
architecture test1 of sub is
begin
y(0) <= x(0) after 0 ns;
y(1) <= not x(1) after 0 ns;
end architecture;
architecture test2 of sub is
begin
sub2_i: entity work.sub2
port map (
x0 => x(0),
x1 => x(1),
y0 => y(0),
y1 => y(1) );
end architecture;
-------------------------------------------------------------------------------
entity elab24 is
end entity;
architecture test of elab24 is
begin
test_a: block is
signal x0, x1, y0, y1 : bit;
begin
sub_i: entity work.sub(test1)
port map (
x(0) => x0,
x(1) => x1,
y(0) => y0,
y(1) => y1 );
process is
begin
x0 <= '1';
wait for 2 ns;
assert y0 = '1';
wait;
end process;
end block;
test_b: block is
signal x0, x1, y0, y1 : bit;
begin
sub_i: entity work.sub(test2)
port map (
x(0) => x0,
x(1) => x1,
y(0) => y0,
y(1) => y1 );
process is
begin
x0 <= '1';
wait for 2 ns;
assert y0 = '1';
wait;
end process;
end block;
end architecture;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
-- Note: This package will be compiled into every single VVC library.
-- As the type t_vvc_target_record is already compiled into every single VVC library,
-- the type definition will be unique for every library, and thus result in a unique
-- procedure signature for every VVC. Hence the shared variable shared_vvc_cmd will
-- refer to only the shared variable defined in the given library.
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.vvc_cmd_pkg.all; -- shared_vvc_response, t_vvc_result
use work.td_target_support_pkg.all;
package td_vvc_framework_common_methods_pkg is
--======================================================================
-- Common Methods
--======================================================================
-------------------------------------------
-- await_completion
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Awaits completion of all commands in the queue for the specified VVC, or
-- until timeout.
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant timeout : in time;
constant msg : in string := ""
);
-------------------------------------------
-- await_completion
-------------------------------------------
-- See description above
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant timeout : in time;
constant msg : in string := ""
);
-------------------------------------------
-- await_completion
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Awaits completion of the specified command 'wanted_idx' in the queue for the specified VVC, or
-- until timeout.
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in natural;
constant timeout : in time;
constant msg : in string := ""
);
-------------------------------------------
-- await_completion
-------------------------------------------
-- See description above
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in natural;
constant timeout : in time;
constant msg : in string := ""
);
-------------------------------------------
-- await_any_completion
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Waits for the first of multiple VVCs to finish :
-- - Awaits completion of all commands in the queue for the specified VVC, or
-- - until global_awaiting_completion /= '1' (any of the other involved VVCs completed).
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0
);
-- Overload without vvc_channel
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0
);
-- Overload with wanted_idx
-- - Awaits completion of the specified command 'wanted_idx' in the queue for the specified VVC, or
-- - until global_awaiting_completion /= '1' (any of the other involved VVCs completed).
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in natural;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0
);
-- Overload without vvc_channel
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in natural;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0
);
-------------------------------------------
-- disable_log_msg
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Disables the specified msg_id for the VVC
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
);
-------------------------------------------
-- disable_log_msg
-------------------------------------------
-- See description above
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
);
-------------------------------------------
-- enable_log_msg
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Enables the specified msg_id for the VVC
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
);
-------------------------------------------
-- enable_log_msg
-------------------------------------------
-- See description above
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
);
-------------------------------------------
-- flush_command_queue
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Flushes the command queue of the specified VVC
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg : in string := ""
);
-------------------------------------------
-- flush_command_queue
-------------------------------------------
-- See description above
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := ""
);
-------------------------------------------
-- fetch_result
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Fetches result from a VVC
-- - Requires that result is available (i.e. already executed in respective VVC)
-- - Logs with ID ID_UVVM_CMD_RESULT
-- The 'result' parameter is of type t_vvc_result to
-- support that the BFM returns something other than a std_logic_vector.
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant caller_name : in string := "base_procedure"
);
-- -- Same as above but without fetch_is_accepted.
-- -- Will trigger alert with alert_level if not OK.
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR
);
-- -- - This version does not use vvc_channel.
-- -- - Fetches result from a VVC
-- -- - Requires that result is available (i.e. already executed in respective VVC)
-- -- - Logs with ID ID_UVVM_CMD_RESULT
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR
);
-- -- Same as above but without fetch_is_accepted.
-- -- Will trigger alert with alert_level if not OK.
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- VVC executor QUEUED command
-- - Inserts delay for 'delay' clock cycles
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in natural; -- in clock cycles
constant msg : in string := ""
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- See description above
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in natural; -- in clock cycles
constant msg : in string := ""
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- VVC executor QUEUED command
-- - Inserts delay for a given time
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in time;
constant msg : in string := ""
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- See description above
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in time;
constant msg : in string := ""
);
-------------------------------------------
-- terminate_current_command
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Terminates the current command being processed in the VVC executor
procedure terminate_current_command(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := ""
);
-- Overload without VVC channel
procedure terminate_current_command(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := ""
);
-------------------------------------------
-- terminate_all_commands
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Terminates the current command being processed in the VVC executor, and
-- flushes the command queue
procedure terminate_all_commands(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := ""
);
-- Overload without VVC channel
procedure terminate_all_commands(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := ""
);
-- Returns the index of the last queued command
impure function get_last_received_cmd_idx(
signal vvc_target : in t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := ""
) return natural;
end package td_vvc_framework_common_methods_pkg;
package body td_vvc_framework_common_methods_pkg is
--=========================================================================================
-- Methods
--=========================================================================================
-- NOTE: ALL VVCs using this td_vvc_framework_common_methods_pkg package MUST have the following declared in their local vvc_cmd_pkg.
-- - The enumerated t_operation (e.g. AWAIT_COMPLETION, ENABLE_LOG_MSG, etc.)
-- Any VVC based on an older version of td_vvc_framework_common_methods_pkg must - if new operators have been introduced in td_vvc_framework_common_methods_pkg either
-- a) include the new operator(s) in its t_operation, or
-- b) change the use-reference to an older common_methods package.
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant timeout : in time;
constant msg : in string := ""
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(timeout, ns) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_COMPLETION);
shared_vvc_cmd.gen_integer_array(0) := -1; -- All commands must be completed (i.e. not just a selected command index)
shared_vvc_cmd.timeout := timeout;
send_command_to_vvc(vvc_target, timeout);
end procedure;
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant timeout : in time;
constant msg : in string := ""
) is
begin
await_completion(vvc_target, vvc_instance_idx, NA, timeout, msg);
end procedure;
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in natural;
constant timeout : in time;
constant msg : in string := ""
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ", " & to_string(timeout, ns) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_COMPLETION);
shared_vvc_cmd.gen_integer_array(0) := wanted_idx;
shared_vvc_cmd.timeout := timeout;
send_command_to_vvc(vvc_target, timeout);
end procedure;
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in natural;
constant timeout : in time;
constant msg : in string := ""
) is
begin
await_completion(vvc_target, vvc_instance_idx, NA, wanted_idx, timeout, msg);
end procedure;
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0 -- Useful when being called by multiple sequencers
) is
constant proc_name : string := "await_any_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(timeout, ns) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_ANY_COMPLETION);
shared_vvc_cmd.gen_integer_array(0) := -1; -- All commands must be completed (i.e. not just a selected command index)
shared_vvc_cmd.gen_integer_array(1) := awaiting_completion_idx;
shared_vvc_cmd.timeout := timeout;
if lastness = LAST then
shared_vvc_cmd.gen_boolean := true; -- LAST
else
shared_vvc_cmd.gen_boolean := false; -- NOT_LAST
end if;
send_command_to_vvc(vvc_target, timeout); -- sets vvc_target.trigger, then waits until global_vvc_ack = '1' for timeout
end procedure;
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0
) is
begin
await_any_completion(vvc_target, vvc_instance_idx, NA, lastness, timeout, msg, awaiting_completion_idx);
end procedure;
-- The two below are as the two above, except with wanted_idx as parameter
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in natural;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0 -- Useful when being called by multiple sequencers
) is
constant proc_name : string := "await_any_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ", " & to_string(timeout, ns) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_ANY_COMPLETION);
shared_vvc_cmd.gen_integer_array(0) := wanted_idx;
shared_vvc_cmd.gen_integer_array(1) := awaiting_completion_idx;
shared_vvc_cmd.timeout := timeout;
if lastness = LAST then
-- LAST
shared_vvc_cmd.gen_boolean := true;
else
-- NOT_LAST : Timeout must be handled in interpreter_await_any_completion
-- becuase the command is always acknowledged immediately by the VVC to allow the sequencer to continue
shared_vvc_cmd.gen_boolean := false;
end if;
send_command_to_vvc(vvc_target, timeout);
end procedure;
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in natural;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0 -- Useful when being called by multiple sequencers
) is
begin
await_any_completion(vvc_target, vvc_instance_idx, NA, wanted_idx, lastness, timeout, msg, awaiting_completion_idx);
end procedure;
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
) is
constant proc_name : string := "disable_log_msg";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_upper(to_string(msg_id)) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, DISABLE_LOG_MSG);
shared_vvc_cmd.msg_id := msg_id;
shared_vvc_cmd.quietness := quietness;
send_command_to_vvc(vvc_target);
end procedure;
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
) is
begin
disable_log_msg(vvc_target, vvc_instance_idx, NA, msg_id, msg, quietness);
end procedure;
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
) is
constant proc_name : string := "enable_log_msg";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_upper(to_string(msg_id)) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, ENABLE_LOG_MSG);
shared_vvc_cmd.msg_id := msg_id;
shared_vvc_cmd.quietness := quietness;
send_command_to_vvc(vvc_target);
end procedure;
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
) is
begin
enable_log_msg(vvc_target, vvc_instance_idx, NA, msg_id, msg, quietness);
end procedure;
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg : in string := ""
) is
constant proc_name : string := "flush_command_queue";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, FLUSH_COMMAND_QUEUE);
send_command_to_vvc(vvc_target);
end procedure;
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := ""
) is
begin
flush_command_queue(vvc_target, vvc_instance_idx, NA, msg);
end procedure;
-- Requires that result is available (i.e. already executed in respective VVC)
-- The four next procedures are overloads for when 'result' is of type work.vvc_cmd_pkg.t_vvc_result
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant caller_name : in string := "base_procedure"
) is
constant proc_name : string := "fetch_result";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ")";
begin
await_semaphore_in_delta_cycles(protected_response_semaphore);
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, FETCH_RESULT);
shared_vvc_cmd.gen_integer_array(0) := wanted_idx;
send_command_to_vvc(vvc_target);
-- Post process
result := shared_vvc_response.result;
fetch_is_accepted := shared_vvc_response.fetch_is_accepted;
if caller_name = "base_procedure" then
log(ID_UVVM_CMD_RESULT, proc_call & ": Legal=>" & to_string(shared_vvc_response.fetch_is_accepted) & ", Result=>" & to_string(result) & format_command_idx(shared_cmd_idx), C_SCOPE); -- Get and ack the new command
end if;
release_semaphore(protected_response_semaphore);
end procedure;
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR
) is
variable v_fetch_is_accepted : boolean;
constant proc_name : string := "fetch_result";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ")";
begin
fetch_result(vvc_target, vvc_instance_idx, vvc_channel, wanted_idx, result, v_fetch_is_accepted, msg, alert_level, proc_name & "_with_check_of_ok");
if v_fetch_is_accepted then
log(ID_UVVM_CMD_RESULT, proc_call & ": Legal=>" & to_string(v_fetch_is_accepted) & ", Result=>" & format_command_idx(shared_cmd_idx), C_SCOPE); -- Get and ack the new command
else
alert(alert_level, "fetch_result(" & to_string(wanted_idx) & "): " & add_msg_delimiter(msg) & "." &
" Failed. Trying to fetch result from not yet executed command or from command with no result stored. " & format_command_idx(shared_cmd_idx), C_SCOPE);
end if;
end procedure;
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR
) is
begin
fetch_result(vvc_target, vvc_instance_idx, NA, wanted_idx, result, fetch_is_accepted, msg, alert_level);
end procedure;
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR
) is
begin
fetch_result(vvc_target, vvc_instance_idx, NA, wanted_idx, result, msg, alert_level);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in natural; -- in clock cycles
constant msg : in string := ""
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(delay) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, QUEUED, INSERT_DELAY);
shared_vvc_cmd.gen_integer_array(0) := delay;
send_command_to_vvc(vvc_target);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in natural; -- in clock cycles
constant msg : in string := ""
) is
begin
insert_delay(vvc_target, vvc_instance_idx, NA, delay, msg);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in time;
constant msg : in string := ""
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(delay) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, QUEUED, INSERT_DELAY);
shared_vvc_cmd.delay := delay;
send_command_to_vvc(vvc_target);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in time;
constant msg : in string := ""
) is
begin
insert_delay(vvc_target, vvc_instance_idx, NA, delay, msg);
end procedure;
procedure terminate_current_command(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := ""
) is
constant proc_name : string := "terminate_current_command";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, TERMINATE_CURRENT_COMMAND);
send_command_to_vvc(vvc_target);
end procedure;
-- Overload without VVC channel
procedure terminate_current_command(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := ""
) is
constant vvc_channel : t_channel := NA;
constant proc_name : string := "terminate_current_command";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx) -- First part common for all
& ")";
begin
terminate_current_command(vvc_target, vvc_instance_idx, vvc_channel, msg);
end procedure;
procedure terminate_all_commands(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := ""
) is
begin
flush_command_queue(vvc_target, vvc_instance_idx, vvc_channel,msg);
terminate_current_command(vvc_target, vvc_instance_idx, vvc_channel, msg);
end procedure;
-- Overload without VVC channel
procedure terminate_all_commands(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := ""
) is
constant vvc_channel : t_channel := NA;
begin
terminate_all_commands(vvc_target, vvc_instance_idx, vvc_channel, msg);
end procedure;
-- Returns the index of the last queued command
impure function get_last_received_cmd_idx(
signal vvc_target : in t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := ""
) return natural is
variable v_cmd_idx : integer := -1;
begin
v_cmd_idx := shared_vvc_last_received_cmd_idx(vvc_channel, vvc_instance_idx);
check_value(v_cmd_idx /= -1, tb_error, "Channel " & to_string(vvc_channel) & " not supported on VVC " & vvc_target.vvc_name, C_SCOPE, ID_NEVER);
if v_cmd_idx /= -1 then
return v_cmd_idx;
else
-- return 0 in case of failure
return 0;
end if;
end function;
end package body td_vvc_framework_common_methods_pkg;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtbp
-- File: ahbtbp.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: AHB Testbench package
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
package ahbtbp is
type ahbtbm_ctrl_type is record
delay : std_logic_vector(7 downto 0);
dbgl : integer;
reset : std_logic;
use128 : integer;
end record;
type ahbtbm_access_type is record
haddr : std_logic_vector(31 downto 0);
hdata : std_logic_vector(31 downto 0);
hdata128 : std_logic_vector(127 downto 0);
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hprot : std_logic_vector(3 downto 0);
hwrite : std_logic;
ctrl : ahbtbm_ctrl_type;
end record;
type ahbtbm_status_type is record
err : std_logic;
ecount : std_logic_vector(15 downto 0);
eaddr : std_logic_vector(31 downto 0);
edatac : std_logic_vector(31 downto 0);
edatar : std_logic_vector(31 downto 0);
hresp : std_logic_vector(1 downto 0);
end record;
type ahbtbm_access_array_type is array (0 to 1) of ahbtbm_access_type;
type ahbtbm_ctrl_in_type is record
ac : ahbtbm_access_type;
end record;
type ahbtbm_ctrl_out_type is record
rst : std_logic;
clk : std_logic;
update : std_logic;
dvalid : std_logic;
hrdata : std_logic_vector(31 downto 0);
hrdata128 : std_logic_vector(127 downto 0);
status : ahbtbm_status_type;
end record;
type ahbtb_ctrl_type is record
i : ahbtbm_ctrl_in_type;
o : ahbtbm_ctrl_out_type;
end record;
constant ac_idle : ahbtbm_access_type :=
(haddr => x"00000000", hdata => x"00000000",
hdata128 => x"00000000000000000000000000000000",
htrans => "00", hburst =>"000", hsize => "000", hprot => "0000", hwrite => '0',
ctrl => (delay => x"00", dbgl => 100, reset =>'0', use128 => 0));
constant ctrli_idle : ahbtbm_ctrl_in_type :=(ac => ac_idle);
constant ctrlo_nodrive : ahbtbm_ctrl_out_type :=(rst => 'H', clk => 'H',
update => 'H', dvalid => 'H', hrdata => (others => 'H'), hrdata128 => (others => 'H'),
status => (err => 'H', ecount => (others => 'H'), eaddr => (others => 'H'),
edatac => (others => 'H'), edatar => (others => 'H'),
hresp => (others => 'H')));
impure function ptime return string;
-- pragma translate_off
-----------------------------------------------------------------------------
-- AHB testbench Master
-----------------------------------------------------------------------------
component ahbtbm is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := 0;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ctrli : in ahbtbm_ctrl_in_type;
ctrlo : out ahbtbm_ctrl_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- AHB testbench Slave
-----------------------------------------------------------------------------
component ahbtbs is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
-----------------------------------------------------------------------------
-- dprint (Debug print)
-----------------------------------------------------------------------------
procedure dprint(
constant doprint : in boolean := true;
constant s : in string);
procedure dprint(
constant s : in string);
-----------------------------------------------------------------------------
-- AMBATB Init
-----------------------------------------------------------------------------
procedure ahbtbminit(
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBATB DONE
-----------------------------------------------------------------------------
procedure ahbtbmdone(
constant stop: in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBATB Idle
-----------------------------------------------------------------------------
procedure ahbtbmidle(
constant sync: in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Start address
constant data : in std_logic_vector(31 downto 0); -- Start data
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(127 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(127 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(63 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(63 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
end ahbtbp;
package body ahbtbp is
impure function ptime return string is
variable s : string(1 to 20);
variable length : integer := tost(NOW / 1 ns)'length;
begin
s(1 to length + 9) :="Time: " & tost(NOW / 1 ns) & "ns ";
return s(1 to length + 9);
end function ptime;
-----------------------------------------------------------------------------
-- dprint (Debug print)
-----------------------------------------------------------------------------
procedure dprint(
constant doprint : in boolean := true;
constant s : in string) is
begin
if doprint = true then
print(s);
end if;
end procedure dprint;
procedure dprint(
constant s : in string) is
begin
print(s);
end procedure dprint;
-----------------------------------------------------------------------------
-- AHBTB init
-----------------------------------------------------------------------------
procedure ahbtbminit(
signal ctrl : inout ahbtb_ctrl_type) is
begin
ctrl.o <= ctrlo_nodrive;
ctrl.i <= ctrli_idle;
--ctrli.ac.hburst <= "000"; ctrli.ac.hsize <= "010";
--ctrli.ac.haddr <= x"00000000"; ctrli.ac.hdata <= x"00000000";
--ctrli.ac.htrans <= "00"; ctrli.ac.hwrite <= '0';
wait until ctrl.o.rst = '1';
print("**********************************************************");
print(" AHBTBM Testbench Init");
print("**********************************************************");
end procedure ahbtbminit;
-----------------------------------------------------------------------------
-- AMBTB DONE
-----------------------------------------------------------------------------
procedure ahbtbmdone(
constant stop: in integer;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
print("**********************************************************");
print(" AHBTBM Testbench Done");
print("**********************************************************");
wait for 100 ns;
assert stop = 0
report "ahbtb testbench done!"
severity FAILURE;
end procedure ahbtbmdone;
-----------------------------------------------------------------------------
-- AMBTB Idle
-----------------------------------------------------------------------------
procedure ahbtbmidle(
constant sync: in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
if sync = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
end if;
end procedure ahbtbmidle;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "000";
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type) is
variable vaddr : std_logic_vector(31 downto 0);
variable vdata : std_logic_vector(31 downto 0);
variable vhtrans : std_logic_vector(1 downto 0);
begin
--ctrl.o <= ctrlo_nodrive;
vaddr := address; vdata := data; vhtrans := "10";
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "001";
ctrl.i.ac.hprot <= "1110";
for i in 0 to count - 1 loop
ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata;
ctrl.i.ac.htrans <= vhtrans;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
vaddr := vaddr + x"4"; vdata := vdata + 1;
vhtrans := "11";
end loop;
ctrl.i <= ctrli_idle;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "000";
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type) is
variable vaddr : std_logic_vector(31 downto 0);
variable vdata : std_logic_vector(31 downto 0);
variable vhtrans : std_logic_vector(1 downto 0);
begin
--ctrl.o <= ctrlo_nodrive;
vaddr := address; vdata := data; vhtrans := "10";
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "001";
ctrl.i.ac.hprot <= "1110";
for i in 0 to count - 1 loop
ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata;
ctrl.i.ac.htrans <= vhtrans;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
vaddr := vaddr + x"4"; vdata := vdata + 1;
vhtrans := "11";
end loop;
ctrl.i <= ctrli_idle;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128write;
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128write;
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128read;
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128read;
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64write;
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64write;
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64read;
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64read;
-- pragma translate_on
end ahbtbp;
|
LIBRARY ieee;
library std;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.math_real.ALL;
USE std.textio.ALL;
PACKAGE my_package IS
function to_bstring(sl : std_logic) return string;
function to_bstring(slv : std_logic_vector) return string;
END PACKAGE;
PACKAGE BODY my_package IS
function to_bstring(sl : std_logic) return string is
variable sl_str_v : string(1 to 3); -- std_logic image with quotes around
begin
sl_str_v := std_logic'image(sl);
return "" & sl_str_v(2); -- "" & character to get string
end function;
function to_bstring(slv : std_logic_vector) return string is
alias slv_norm : std_logic_vector(1 to slv'length) is slv;
variable sl_str_v : string(1 to 1); -- String of std_logic
variable res_v : string(1 to slv'length);
begin
for idx in slv_norm'range loop
sl_str_v := to_bstring(slv_norm(idx));
res_v(idx) := sl_str_v(1);
end loop;
return res_v;
end function;
END PACKAGE BODY; |
LIBRARY ieee;
library std;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.math_real.ALL;
USE std.textio.ALL;
PACKAGE my_package IS
function to_bstring(sl : std_logic) return string;
function to_bstring(slv : std_logic_vector) return string;
END PACKAGE;
PACKAGE BODY my_package IS
function to_bstring(sl : std_logic) return string is
variable sl_str_v : string(1 to 3); -- std_logic image with quotes around
begin
sl_str_v := std_logic'image(sl);
return "" & sl_str_v(2); -- "" & character to get string
end function;
function to_bstring(slv : std_logic_vector) return string is
alias slv_norm : std_logic_vector(1 to slv'length) is slv;
variable sl_str_v : string(1 to 1); -- String of std_logic
variable res_v : string(1 to slv'length);
begin
for idx in slv_norm'range loop
sl_str_v := to_bstring(slv_norm(idx));
res_v(idx) := sl_str_v(1);
end loop;
return res_v;
end function;
END PACKAGE BODY; |
--------------------------------------------------------------------------------
--
-- register.vhd
--
-- This file contains the logic for a single register. The contents of the
-- register will always be output. The register will change its value to the
-- input on every rising edge of the clock, whenever the 'nLd' input is
-- asserted. The design is parametrized on 'N', the size of the register.
--
-- The size of this cell is O(N).
--
-- Dependencies:
-- None.
--
-- Revision History:
-- 07 May 2015 Brian Kubisiak Initial revision.
--
--------------------------------------------------------------------------------
-- bring in the necessary packages
library ieee;
use ieee.std_logic_1164.all;
-- Reg
--
-- parameters:
-- N (integer) Number of bits in the register.
--
-- inputs:
-- Clk (std_logic) System clock for latching the input.
-- DataIn (std_logic_vector) Data input for loading into the register.
-- nLd (std_logic) Active-low signal indicating the input
-- should be latched on the next rising clock
-- edge.
--
-- outputs:
-- DataOut (std_logic_vector) Value currently stored in the register.
--
entity Reg is
generic ( N : integer := 8 ); -- Number of bits.
port (
Clk : in std_logic; -- System clock.
DataIn : in std_logic_vector(N-1 downto 0); -- Data input.
nLd : in std_logic; -- Latch the input.
DataOut : out std_logic_vector(N-1 downto 0) -- Value in register.
);
end Reg;
architecture procedural of Reg is
-- Current value in the register. It will always be output, and will be
-- loaded on the rising edge of the clock whenever 'nLd' is asserted.
signal value : std_logic_vector(N-1 downto 0);
begin
-- Always output the current value of the register.
DataOut <= value;
--
-- LoadReg
--
-- This process will latch the register value on every clock, unless the
-- 'nLd' signal is asserted. If this is asserted, then the new value is
-- taken from the data input.
--
LoadReg: process(clk)
begin
-- Latch the data using the given clock.
if rising_edge(clk) then
-- When loading, store the new value.
if (nLd = '0') then
value <= DataIn;
-- Else, when not loading, latch the current value.
elsif (nLd = '1') then
value <= value;
-- For simulation, latch unknown value when input is unknown.
else
value <= (others => 'X');
end if;
end if;
end process;
end procedural;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: util
-- File: util.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Misc utilities
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity report_version is
generic (msg1, msg2, msg3, msg4 : string := ""; mdel : integer := 4);
end;
architecture beh of report_version is
begin
x : process
begin
wait for mdel * 1 ns;
if (msg1 /= "") then print(msg1); end if;
if (msg2 /= "") then print(msg2); end if;
if (msg3 /= "") then print(msg3); end if;
if (msg4 /= "") then print(msg4); end if;
wait;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity report_design is
generic (msg1, fabtech, memtech : string := ""; mdel : integer := 4);
end;
architecture beh of report_design is
begin
x : report_version
generic map (
msg1 => msg1,
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & fabtech & ", memory library: " & memtech,
mdel => mdel);
end;
-- pragma translate_on
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use work.RWCACHE_PKG.all;
entity RWCACHE is
generic (
regaddrsize : integer
);
port (
CLK : in std_logic;
RST : in std_logic; -- active high
ENABLE_EX : in std_logic;
READNOTWRITE_EX : in std_logic;
ALU_OUT_REAL : in std_logic_vector(DATA_SIZE - 1 downto 0);
RS2_DATA_EX : in std_logic_vector(DATA_SIZE - 1 downto 0);
RS2_EX : in std_logic_vector(regaddrsize-1 downto 0);
RD_MEM : in std_logic_vector(regaddrsize-1 downto 0);
MEM_STALL : in std_logic;
LATCHER : in std_logic;
MEM_DATA : out std_logic_vector(DATA_SIZE - 1 downto 0);
STALL : out std_logic;
RAM_ISSUE : out std_logic;
RAM_READNOTWRITE : out std_logic;
RAM_ADDRESS : out std_logic_vector(DATA_SIZE - 1 downto 0);
RAM_DATA : inout std_logic_vector(2*DATA_SIZE - 1 downto 0);
RAM_READY : in std_logic
);
end RWCACHE;
architecture Behavioral of RWCACHE is
signal CACHE,CACHE_REG : RWCACHE_TYPE;
signal STATE_CURRENT : state_type;
signal STATE_NEXT : state_type;
signal INT_ISSUE_RAM_READ : std_logic;
signal ENABLE : std_logic;
signal READNOTWRITE : std_logic;
signal INT_INOUT_DATA,int_address_data,address_to_mem : std_logic_vector(DATA_SIZE -1 downto 0);
signal ADDRESS : std_logic_vector(DATA_SIZE -1 downto 0);
signal IN_DATA : std_logic_vector(DATA_SIZE -1 downto 0);
signal INT_MEM_DATA : std_logic_vector(DATA_SIZE -1 downto 0);
signal INT_RAM_DATA : std_logic_vector(2*DATA_SIZE -1 downto 0) := (others => 'Z');
signal NOP_OUT : std_logic;
signal INT_STALL : std_logic;
signal rewrite : std_logic:='0';
signal INT_RAM_READNOTWRITE: std_logic;
begin
--
-- FSM Management
--
state_update: process(CLK, RST, STATE_NEXT, LATCHER)
variable RS2_MEM_EQ_RD_WB : std_logic;
variable LATCHED_RS2_DATA_EX : std_logic_vector(DATA_SIZE-1 downto 0);
variable LATCHED_ALU_OUT_REAL : std_logic_vector(DATA_SIZE-1 downto 0);
begin
if RST = '1' then
STATE_CURRENT <= STATE_FLUSH_MEM;
elsif clk'event and clk = '1' then
CACHE_REG <= CACHE;
STATE_CURRENT <= STATE_NEXT;
if INT_STALL = '0' then
ENABLE <= ENABLE_EX;
READNOTWRITE <= READNOTWRITE_EX;
else
ENABLE <= '1';
end if;
if LATCHER = '1' then
LATCHED_RS2_DATA_EX := RS2_DATA_EX;
LATCHED_ALU_OUT_REAL := ALU_OUT_REAL;
end if;
ADDRESS <= LATCHED_ALU_OUT_REAL;
RS2_MEM_EQ_RD_WB := (not or_reduce( RS2_EX xor RD_MEM ) and ( not MEM_STALL ));
if RS2_MEM_EQ_RD_WB = '1' then
IN_DATA <= INT_MEM_DATA;
else
IN_DATA <= LATCHED_RS2_DATA_EX;
end if;
end if;
end process;
--
-- The MONSTER
main: process(STATE_CURRENT, ADDRESS, IN_DATA, READNOTWRITE, RAM_READY, int_address_data, ENABLE, CACHE_REG)
variable HIT : std_logic:='0';
variable int_mem : std_logic_vector(2*DATA_SIZE - 1 downto 0);
variable currentLine : natural range 0 to 2**RWCACHE_COUNTERSIZE;
variable count_miss : natural range 0 to RWCACHE_NUMLINES;
variable index : natural range 0 to 2**RWCACHE_INDEXOFFSET - 1;
variable lineIndex : natural range 0 to RWCACHE_NUMLINES;
variable address_stall : std_logic_vector(DATA_SIZE - 1 downto 0);
variable data_stall : std_logic_vector(DATA_SIZE - 1 downto 0);
variable readnotwrite_stall : std_logic := '0';
variable test : integer;
begin
report "addr" & integer'image(conv_integer(unsigned(ADDRESS))) & " rnw " & std_logic'image(READNOTWRITE) & "inout" & integer'image(conv_integer(unsigned(IN_DATA))) & " indata " & integer'image(conv_integer(unsigned(IN_DATA))) & " enable " & std_logic'image(ENABLE) & " state " & integer'image(conv_integer(unsigned(STATE_CURRENT))) & " ram ready " & std_logic'image(RAM_READY);
count_miss := 0;
CACHE <= CACHE_REG;
INT_INOUT_DATA <= (others => '0');
case (STATE_CURRENT) is
when STATE_FLUSH_MEM =>
-- ADDRESS <= (others => '0');
INT_INOUT_DATA <= (others =>'0');
for i in 0 to RWCACHE_NUMSETS - 1 loop
for j in 0 to RWCACHE_NUMLINES - 1 loop
CACHE(i)(j).tag( RWCACHE_TAGSIZE - 1 downto 0 ) <= (others => '0');
CACHE(i)(j).valid <= '0'; -- dirty bit
CACHE(i)(j).counter <= 0;
for k in 0 to RWCACHE_WORDS - 1 loop
CACHE(i)(j).words(k) <= (others => '1');
end loop;
end loop;
end loop;
NOP_OUT <= '1';
HIT := '0';
INT_ISSUE_RAM_READ <= '0';
STATE_NEXT <= STATE_IDLE;
when STATE_IDLE => STATE_NEXT <= STATE_COMPARE_TAGS;
when STATE_WRITE_MISS =>
if(RAM_READY = '1') then
STATE_NEXT <= STATE_MISS;
INT_ISSUE_RAM_READ <= '1';
else
STATE_NEXT <= STATE_WRITE_MISS;
end if;
-- MISS STATE
-- Probe the RAM and wait until RAM_READY
when STATE_MISS =>
-- I gots the data
rewrite <= '0';
INT_ISSUE_RAM_READ <= '1';
INT_RAM_READNOTWRITE <= '1';
if (RAM_READY = '1' and rewrite='0') then
-- Identify line to hold the new data
currentLine := GET_REPLACEMENT_LINE(int_address_data, CACHE_REG);
-- Identify word index inside the line
-- report "----------------- Instr " & integer'image(conv_integer(unsigned(int_address_data))) & "-> Writing TAG " & integer'image(conv_integer(unsigned(int_address_data(DATA_SIZE-1 downto RWCACHE_TAGOFFSET)))) & " in set " & integer'image(GET_SET(int_address_data)) & " line " & integer'image(currentLine);
-- Store TAG
CACHE(GET_SET(int_address_data))(currentLine).tag <= int_address_data(DATA_SIZE - 1 downto RWCACHE_TAGOFFSET);
-- Reset LFU counter
CACHE(GET_SET(int_address_data))(currentLine).counter <= 0;
-- Set valid bit
CACHE(GET_SET(int_address_data))(currentLine).valid <= '1';
-- Fetch the line from memory data bus and write it into the cache data
for i in 0 to RWCACHE_WORDS - 1 loop
if( readnotwrite_stall = '0' and i = conv_integer(unsigned(int_address_data(RWCACHE_INDEXOFFSET - 1 downto 0)))) then
CACHE(GET_SET(int_address_data))(currentLine).words(i) <= data_stall;
else
CACHE(GET_SET(int_address_data))(currentLine).words(i)
<= RAM_DATA(((i+1)*DATA_SIZE - 1) downto i*DATA_SIZE);
end if;
end loop;
-- Write the DATA_OUT
if(readnotwrite_stall = '1' ) then
if((conv_integer(unsigned(int_address_data(RWCACHE_INDEXOFFSET - 1 downto 0)))) = 0) then
INT_INOUT_DATA <= RAM_DATA(DATA_SIZE - 1 downto 0);
else
INT_INOUT_DATA <= RAM_DATA(2*DATA_SIZE - 1 downto DATA_SIZE);
end if;
end if;
STATE_NEXT <= STATE_COMPARE_TAGS;
NOP_OUT <= '0';
end if;
-- Fetch instruction and print it if HIT
when STATE_COMPARE_TAGS =>
if(ENABLE = '1') then
NOP_OUT <= '1';
INT_ISSUE_RAM_READ <= '0';
if(READNOTWRITE = '0') then
INT_INOUT_DATA <= RS2_DATA_EX;
report "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ Writing " & integer'image(conv_integer(unsigned(IN_DATA))) & " into " & integer'image(conv_integer(unsigned(ADDRESS)));
end if;
-- Look in the CACHE
for i in 0 to RWCACHE_NUMLINES - 1 loop
-- Is it a HIT ?
HIT := COMPARE_TAGS(
ADDRESS(DATA_SIZE - 1 downto RWCACHE_TAGOFFSET),
CACHE_REG(GET_SET(ADDRESS))(i).tag(RWCACHE_TAGSIZE - 1 downto 0)
);
-- HIT!
if (HIT = '1') then
-- Is the entry valid?
if(CACHE_REG(GET_SET(ADDRESS))(i).valid = '1') then
lineIndex:= i;
-- report string'("STATE: ") & integer'image(conv_integer(unsigned(STATE_CURRENT))) & string'(" || ADDRESS: ") & integer'image(conv_integer(unsigned(ADDRESS))) & string'(" || HIT: ") & integer'image(conv_integer(conv_integer(HIT))) & string'(" || i: ") & integer'image(i) & string'(" || offset: ") & integer'image(GET_SET(ADDRESS)) & string'(" || count_miss = ") & integer'image(count_miss);
HIT := '0'; -- Reset HIT
CACHE(GET_SET(ADDRESS))(lineIndex).counter <= CACHE_REG(GET_SET(ADDRESS))(lineIndex).counter + 1;
if(READNOTWRITE = '1') then
-- Print out the instruction
INT_INOUT_DATA <= CACHE_REG(
GET_SET(ADDRESS))(lineIndex).words(
conv_integer(unsigned(ADDRESS(RWCACHE_INDEXOFFSET - 1 downto 0))
)
);
test := conv_integer(unsigned(CACHE_REG(
GET_SET(ADDRESS))(lineIndex).words(
conv_integer(unsigned(ADDRESS(RWCACHE_INDEXOFFSET - 1 downto 0))
)
)));
report "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ Reading " & integer'image(test) & " into " & integer'image(conv_integer(unsigned(ADDRESS)));
else
CACHE(
GET_SET(ADDRESS))(lineIndex).words(
conv_integer(unsigned(ADDRESS(RWCACHE_INDEXOFFSET - 1 downto 0))
)
) <= IN_DATA;
end if;
NOP_OUT <= '0';
-- Next state: the same
STATE_NEXT <= STATE_COMPARE_TAGS;
count_miss := 0;
exit;
-- The entry is not valid. Count as miss, save its index
else
count_miss := count_miss + 1;
end if;
-- Miss :(
else
count_miss := count_miss + 1;
end if;
end loop;
-- Miss?
if(count_miss = RWCACHE_NUMLINES) then
int_address_data <= ADDRESS;
readnotwrite_stall := READNOTWRITE;
data_stall := IN_DATA;
currentLine := GET_REPLACEMENT_LINE(ADDRESS, CACHE_REG);
if(CACHE_REG(GET_SET(ADDRESS))(currentLine).valid = '1') then
address_stall := CACHE_REG(GET_SET(ADDRESS))(currentLine).tag & ADDRESS(RWCACHE_TAGOFFSET-1 downto RWCACHE_SETOFFSET) & '0';
rewrite <= '1';
address_to_mem <= address_stall;
-- report "ADDRESS TO MEM: "& integer'image(conv_integer(unsigned(address_stall)));
INT_RAM_DATA <= CACHE_REG(GET_SET(address_stall))(currentLine).words(0) & CACHE_REG(GET_SET(address_stall))(currentLine).words(1);
CACHE(GET_SET(ADDRESS))(currentLine).valid <= '0';
INT_RAM_READNOTWRITE <= '0';
STATE_NEXT <= STATE_WRITE_MISS;
else
STATE_NEXT <= STATE_MISS;
end if;
end if;
-- Reset the counter
count_miss := 0;
else
INT_ISSUE_RAM_READ <= '0';
INT_INOUT_DATA <= ALU_OUT_REAL;
STATE_NEXT <= STATE_COMPARE_TAGS;
end if;
count_miss := 0;
when OTHERS => null;
end case;
end process;
INT_STALL <= NOP_OUT when ENABLE = '1' else '0';
STALL <= INT_STALL;
RAM_ISSUE <= INT_ISSUE_RAM_READ or rewrite;
RAM_READNOTWRITE <= INT_RAM_READNOTWRITE;
RAM_ADDRESS <= address_to_mem when (rewrite = '1') else
int_address_data when (INT_ISSUE_RAM_READ='1') else (others=> 'Z') ;
RAM_DATA <= INT_RAM_DATA when rewrite = '1' else (others =>'Z');
INT_MEM_DATA <= INT_INOUT_DATA;
MEM_DATA <= INT_MEM_DATA;
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCCZ56SYK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNCCZ56SYK is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 ,
width_inr=> 0,
width_outl=> 25,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCCZ56SYK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNCCZ56SYK is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 ,
width_inr=> 0,
width_outl=> 25,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCCZ56SYK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNCCZ56SYK is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 ,
width_inr=> 0,
width_outl=> 25,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCCZ56SYK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNCCZ56SYK is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 ,
width_inr=> 0,
width_outl=> 25,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
yout => output
);
end architecture; |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY blk_mem_gen_1 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END blk_mem_gen_1;
ARCHITECTURE blk_mem_gen_1_arch OF blk_mem_gen_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_1_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_1_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_1_arch : ARCHITECTURE IS "blk_mem_gen_1,blk_mem_gen_v8_3_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_1_arch: ARCHITECTURE IS "blk_mem_gen_1,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=kintex7,C_XDEVICEFAMILY=kintex7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_1.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=4096,C_READ_DEPTH_B=4096,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.53475 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "kintex7",
C_XDEVICEFAMILY => "kintex7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_1.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 4096,
C_READ_DEPTH_A => 4096,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 4096,
C_READ_DEPTH_B => 4096,
C_ADDRB_WIDTH => 12,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.53475 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_1_arch;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Loop_loop_height_pro is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_rows_assign_cast_loc_dout : IN STD_LOGIC_VECTOR (11 downto 0);
p_rows_assign_cast_loc_empty_n : IN STD_LOGIC;
p_rows_assign_cast_loc_read : OUT STD_LOGIC;
p_cols_assign_cast_loc_dout : IN STD_LOGIC_VECTOR (11 downto 0);
p_cols_assign_cast_loc_empty_n : IN STD_LOGIC;
p_cols_assign_cast_loc_read : OUT STD_LOGIC;
img3_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img3_data_stream_0_V_full_n : IN STD_LOGIC;
img3_data_stream_0_V_write : OUT STD_LOGIC;
img3_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img3_data_stream_1_V_full_n : IN STD_LOGIC;
img3_data_stream_1_V_write : OUT STD_LOGIC;
img3_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img3_data_stream_2_V_full_n : IN STD_LOGIC;
img3_data_stream_2_V_write : OUT STD_LOGIC;
gamma_dout : IN STD_LOGIC_VECTOR (7 downto 0);
gamma_empty_n : IN STD_LOGIC;
gamma_read : OUT STD_LOGIC;
img0_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img0_data_stream_0_V_empty_n : IN STD_LOGIC;
img0_data_stream_0_V_read : OUT STD_LOGIC;
img0_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img0_data_stream_1_V_empty_n : IN STD_LOGIC;
img0_data_stream_1_V_read : OUT STD_LOGIC;
img0_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img0_data_stream_2_V_empty_n : IN STD_LOGIC;
img0_data_stream_2_V_read : OUT STD_LOGIC );
end;
architecture behav of Loop_loop_height_pro is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv8_8 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_const_lv8_7 : STD_LOGIC_VECTOR (7 downto 0) := "00000111";
constant ap_const_lv8_6 : STD_LOGIC_VECTOR (7 downto 0) := "00000110";
constant ap_const_lv8_5 : STD_LOGIC_VECTOR (7 downto 0) := "00000101";
constant ap_const_lv8_4 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_const_lv8_3 : STD_LOGIC_VECTOR (7 downto 0) := "00000011";
constant ap_const_lv8_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal lut2_2_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_2_ce0 : STD_LOGIC;
signal lut2_2_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_2_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_2_ce1 : STD_LOGIC;
signal lut2_2_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_2_address2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_2_ce2 : STD_LOGIC;
signal lut2_2_q2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_4_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_4_ce0 : STD_LOGIC;
signal lut0_4_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_4_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_4_ce1 : STD_LOGIC;
signal lut0_4_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_4_address2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_4_ce2 : STD_LOGIC;
signal lut0_4_q2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_2_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_2_ce0 : STD_LOGIC;
signal lut0_2_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_2_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_2_ce1 : STD_LOGIC;
signal lut0_2_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_2_address2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_2_ce2 : STD_LOGIC;
signal lut0_2_q2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_2_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_2_ce0 : STD_LOGIC;
signal lut1_2_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_2_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_2_ce1 : STD_LOGIC;
signal lut1_2_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_2_address2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_2_ce2 : STD_LOGIC;
signal lut1_2_q2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_4_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_4_ce0 : STD_LOGIC;
signal lut1_4_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_4_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_4_ce1 : STD_LOGIC;
signal lut1_4_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_4_address2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_4_ce2 : STD_LOGIC;
signal lut1_4_q2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_6_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_6_ce0 : STD_LOGIC;
signal lut1_6_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_6_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_6_ce1 : STD_LOGIC;
signal lut1_6_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_6_address2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_6_ce2 : STD_LOGIC;
signal lut1_6_q2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_8_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_8_ce0 : STD_LOGIC;
signal lut1_8_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_8_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_8_ce1 : STD_LOGIC;
signal lut1_8_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_8_address2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_8_ce2 : STD_LOGIC;
signal lut1_8_q2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_0_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_0_ce0 : STD_LOGIC;
signal lut2_0_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_0_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_0_ce1 : STD_LOGIC;
signal lut2_0_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_0_address2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_0_ce2 : STD_LOGIC;
signal lut2_0_q2 : STD_LOGIC_VECTOR (7 downto 0);
signal p_rows_assign_cast_loc_blk_n : STD_LOGIC;
signal p_cols_assign_cast_loc_blk_n : STD_LOGIC;
signal img3_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal ap_block_pp0_stage0 : BOOLEAN;
signal exitcond_i_i_i_reg_837 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 : STD_LOGIC_VECTOR (0 downto 0);
signal img3_data_stream_1_V_blk_n : STD_LOGIC;
signal img3_data_stream_2_V_blk_n : STD_LOGIC;
signal gamma_blk_n : STD_LOGIC;
signal img0_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal img0_data_stream_1_V_blk_n : STD_LOGIC;
signal img0_data_stream_2_V_blk_n : STD_LOGIC;
signal t_V_2_reg_444 : STD_LOGIC_VECTOR (10 downto 0);
signal gamma_read_reg_750 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_state1 : BOOLEAN;
signal p_rows_assign_cast_lo_reg_762 : STD_LOGIC_VECTOR (11 downto 0);
signal p_cols_assign_cast_lo_reg_767 : STD_LOGIC_VECTOR (11 downto 0);
signal sel_tmp2_fu_460_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_reg_772 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal sel_tmp6_fu_470_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp6_reg_779 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp1_fu_480_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp1_reg_786 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp5_fu_490_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp5_reg_793 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_fu_495_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_reg_800 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond2_fu_507_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond2_reg_807 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond4_fu_519_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond4_reg_814 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond6_fu_531_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond6_reg_821 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond161_i_i_i_fu_541_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal i_V_fu_546_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_V_reg_832 : STD_LOGIC_VECTOR (10 downto 0);
signal exitcond_i_i_i_fu_556_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state4_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state6_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state7_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_pp0_stage0_11001 : BOOLEAN;
signal ap_reg_pp0_iter1_exitcond_i_i_i_reg_837 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 : STD_LOGIC_VECTOR (0 downto 0);
signal j_V_fu_561_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal tmp_9_reg_846 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_9_reg_846 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_9_reg_846 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_reg_852 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_10_reg_852 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_10_reg_852 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_11_reg_858 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_11_reg_858 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_11_reg_858 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_0_2_reg_984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal d_val_0_3_reg_989 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_0_6_reg_994 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_0_7_reg_999 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel1_fu_600_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel1_reg_1004 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel3_fu_607_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel3_reg_1009 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_1_2_reg_1014 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_1_3_reg_1019 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_1_6_reg_1024 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_1_7_reg_1029 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel9_fu_614_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel9_reg_1034 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel10_fu_621_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel10_reg_1039 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_2_2_reg_1044 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_2_3_reg_1049 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_2_6_reg_1054 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_2_7_reg_1059 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel15_fu_628_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel15_reg_1064 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel17_fu_635_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel17_reg_1069 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_pp0_stage0_subdone : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state4 : STD_LOGIC;
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal t_V_reg_433 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal tmp_26_i_i_fu_567_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_26_1_i_i_fu_578_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_26_2_i_i_fu_589_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage0_01001 : BOOLEAN;
signal sel_tmp3_fu_485_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp8_fu_475_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp4_fu_465_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp_fu_455_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond1_fu_501_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond3_fu_513_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond5_fu_525_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal t_V_cast_i_i_fu_537_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal t_V_1_cast_i_i_fu_552_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal newSel_fu_642_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel2_fu_647_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel4_fu_652_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel5_fu_658_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel6_fu_664_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel8_fu_678_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel7_fu_683_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel11_fu_688_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel12_fu_694_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel13_fu_700_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel14_fu_714_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel16_fu_719_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel18_fu_724_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel19_fu_730_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel20_fu_736_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component Loop_loop_height_bkb IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0);
address2 : IN STD_LOGIC_VECTOR (7 downto 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_cud IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0);
address2 : IN STD_LOGIC_VECTOR (7 downto 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_dEe IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0);
address2 : IN STD_LOGIC_VECTOR (7 downto 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_eOg IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0);
address2 : IN STD_LOGIC_VECTOR (7 downto 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_fYi IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0);
address2 : IN STD_LOGIC_VECTOR (7 downto 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_g8j IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0);
address2 : IN STD_LOGIC_VECTOR (7 downto 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_hbi IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0);
address2 : IN STD_LOGIC_VECTOR (7 downto 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_ibs IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0);
address2 : IN STD_LOGIC_VECTOR (7 downto 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
lut2_2_U : component Loop_loop_height_bkb
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut2_2_address0,
ce0 => lut2_2_ce0,
q0 => lut2_2_q0,
address1 => lut2_2_address1,
ce1 => lut2_2_ce1,
q1 => lut2_2_q1,
address2 => lut2_2_address2,
ce2 => lut2_2_ce2,
q2 => lut2_2_q2);
lut0_4_U : component Loop_loop_height_cud
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut0_4_address0,
ce0 => lut0_4_ce0,
q0 => lut0_4_q0,
address1 => lut0_4_address1,
ce1 => lut0_4_ce1,
q1 => lut0_4_q1,
address2 => lut0_4_address2,
ce2 => lut0_4_ce2,
q2 => lut0_4_q2);
lut0_2_U : component Loop_loop_height_dEe
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut0_2_address0,
ce0 => lut0_2_ce0,
q0 => lut0_2_q0,
address1 => lut0_2_address1,
ce1 => lut0_2_ce1,
q1 => lut0_2_q1,
address2 => lut0_2_address2,
ce2 => lut0_2_ce2,
q2 => lut0_2_q2);
lut1_2_U : component Loop_loop_height_eOg
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut1_2_address0,
ce0 => lut1_2_ce0,
q0 => lut1_2_q0,
address1 => lut1_2_address1,
ce1 => lut1_2_ce1,
q1 => lut1_2_q1,
address2 => lut1_2_address2,
ce2 => lut1_2_ce2,
q2 => lut1_2_q2);
lut1_4_U : component Loop_loop_height_fYi
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut1_4_address0,
ce0 => lut1_4_ce0,
q0 => lut1_4_q0,
address1 => lut1_4_address1,
ce1 => lut1_4_ce1,
q1 => lut1_4_q1,
address2 => lut1_4_address2,
ce2 => lut1_4_ce2,
q2 => lut1_4_q2);
lut1_6_U : component Loop_loop_height_g8j
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut1_6_address0,
ce0 => lut1_6_ce0,
q0 => lut1_6_q0,
address1 => lut1_6_address1,
ce1 => lut1_6_ce1,
q1 => lut1_6_q1,
address2 => lut1_6_address2,
ce2 => lut1_6_ce2,
q2 => lut1_6_q2);
lut1_8_U : component Loop_loop_height_hbi
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut1_8_address0,
ce0 => lut1_8_ce0,
q0 => lut1_8_q0,
address1 => lut1_8_address1,
ce1 => lut1_8_ce1,
q1 => lut1_8_q1,
address2 => lut1_8_address2,
ce2 => lut1_8_ce2,
q2 => lut1_8_q2);
lut2_0_U : component Loop_loop_height_ibs
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut2_0_address0,
ce0 => lut2_0_ce0,
q0 => lut2_0_q0,
address1 => lut2_0_address1,
ce1 => lut2_0_ce1,
q1 => lut2_0_q1,
address2 => lut2_0_address2,
ce2 => lut2_0_ce2,
q2 => lut2_0_q2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif (((exitcond161_i_i_i_fu_541_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state4) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond161_i_i_i_fu_541_p2 = ap_const_lv1_0))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state4)) then
ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state4);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond161_i_i_i_fu_541_p2 = ap_const_lv1_0))) then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
t_V_2_reg_444_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_fu_556_p2 = ap_const_lv1_0))) then
t_V_2_reg_444 <= j_V_fu_561_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond161_i_i_i_fu_541_p2 = ap_const_lv1_0))) then
t_V_2_reg_444 <= ap_const_lv11_0;
end if;
end if;
end process;
t_V_reg_433_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
t_V_reg_433 <= i_V_reg_832;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
t_V_reg_433 <= ap_const_lv11_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_reg_pp0_iter1_exitcond_i_i_i_reg_837 <= exitcond_i_i_i_reg_837;
exitcond_i_i_i_reg_837 <= exitcond_i_i_i_fu_556_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 <= ap_reg_pp0_iter1_exitcond_i_i_i_reg_837;
ap_reg_pp0_iter2_tmp_10_reg_852 <= tmp_10_reg_852;
ap_reg_pp0_iter2_tmp_11_reg_858 <= tmp_11_reg_858;
ap_reg_pp0_iter2_tmp_9_reg_846 <= tmp_9_reg_846;
ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 <= ap_reg_pp0_iter2_exitcond_i_i_i_reg_837;
ap_reg_pp0_iter3_tmp_10_reg_852 <= ap_reg_pp0_iter2_tmp_10_reg_852;
ap_reg_pp0_iter3_tmp_11_reg_858 <= ap_reg_pp0_iter2_tmp_11_reg_858;
ap_reg_pp0_iter3_tmp_9_reg_846 <= ap_reg_pp0_iter2_tmp_9_reg_846;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_cond6_reg_821 = ap_const_lv1_1) and (or_cond4_reg_814 = ap_const_lv1_1) and (or_cond_reg_800 = ap_const_lv1_1) and (sel_tmp5_reg_793 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 = ap_const_lv1_0))) then
d_val_0_2_reg_984 <= lut0_4_q0;
d_val_1_2_reg_1014 <= lut0_4_q1;
d_val_2_2_reg_1044 <= lut0_4_q2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_cond6_reg_821 = ap_const_lv1_1) and (or_cond4_reg_814 = ap_const_lv1_1) and (or_cond_reg_800 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (sel_tmp5_reg_793 = ap_const_lv1_0))) then
d_val_0_3_reg_989 <= lut0_2_q0;
d_val_1_3_reg_1019 <= lut0_2_q1;
d_val_2_3_reg_1049 <= lut0_2_q2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_cond6_reg_821 = ap_const_lv1_1) and (or_cond2_reg_807 = ap_const_lv1_1) and (sel_tmp6_reg_779 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (or_cond4_reg_814 = ap_const_lv1_0))) then
d_val_0_6_reg_994 <= lut1_6_q0;
d_val_1_6_reg_1024 <= lut1_6_q1;
d_val_2_6_reg_1054 <= lut1_6_q2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_cond6_reg_821 = ap_const_lv1_1) and (or_cond2_reg_807 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (or_cond4_reg_814 = ap_const_lv1_0) and (sel_tmp6_reg_779 = ap_const_lv1_0))) then
d_val_0_7_reg_999 <= lut1_8_q0;
d_val_1_7_reg_1029 <= lut1_8_q1;
d_val_2_7_reg_1059 <= lut1_8_q2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((gamma_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
gamma_read_reg_750 <= gamma_dout;
p_cols_assign_cast_lo_reg_767 <= p_cols_assign_cast_loc_dout;
p_rows_assign_cast_lo_reg_762 <= p_rows_assign_cast_loc_dout;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
i_V_reg_832 <= i_V_fu_546_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_cond6_reg_821 = ap_const_lv1_1) and (ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (or_cond4_reg_814 = ap_const_lv1_0) and (or_cond2_reg_807 = ap_const_lv1_0))) then
newSel10_reg_1039 <= newSel10_fu_621_p3;
newSel17_reg_1069 <= newSel17_fu_635_p3;
newSel3_reg_1009 <= newSel3_fu_607_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_cond6_reg_821 = ap_const_lv1_1) and (or_cond4_reg_814 = ap_const_lv1_1) and (ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (or_cond_reg_800 = ap_const_lv1_0))) then
newSel15_reg_1064 <= newSel15_fu_628_p3;
newSel1_reg_1004 <= newSel1_fu_600_p3;
newSel9_reg_1034 <= newSel9_fu_614_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
or_cond2_reg_807 <= or_cond2_fu_507_p2;
or_cond4_reg_814 <= or_cond4_fu_519_p2;
or_cond6_reg_821 <= or_cond6_fu_531_p2;
or_cond_reg_800 <= or_cond_fu_495_p2;
sel_tmp1_reg_786 <= sel_tmp1_fu_480_p2;
sel_tmp2_reg_772 <= sel_tmp2_fu_460_p2;
sel_tmp5_reg_793 <= sel_tmp5_fu_490_p2;
sel_tmp6_reg_779 <= sel_tmp6_fu_470_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0))) then
tmp_10_reg_852 <= img0_data_stream_1_V_dout;
tmp_11_reg_858 <= img0_data_stream_2_V_dout;
tmp_9_reg_846 <= img0_data_stream_0_V_dout;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, gamma_empty_n, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, exitcond161_i_i_i_fu_541_p2, ap_CS_fsm_state3, exitcond_i_i_i_fu_556_p2, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_subdone)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((gamma_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
if (((exitcond161_i_i_i_fu_541_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (exitcond_i_i_i_fu_556_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1))) and not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif ((((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (exitcond_i_i_i_fu_556_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1)))) then
ap_NS_fsm <= ap_ST_fsm_state9;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(3);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state9 <= ap_CS_fsm(4);
ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_01001_assign_proc : process(img3_data_stream_0_V_full_n, img3_data_stream_1_V_full_n, img3_data_stream_2_V_full_n, img0_data_stream_0_V_empty_n, img0_data_stream_1_V_empty_n, img0_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter4, exitcond_i_i_i_reg_837, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837, ap_enable_reg_pp0_iter1)
begin
ap_block_pp0_stage0_01001 <= (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((img0_data_stream_2_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img0_data_stream_1_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img0_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)))) or ((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (((img3_data_stream_2_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img3_data_stream_1_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img3_data_stream_0_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)))));
end process;
ap_block_pp0_stage0_11001_assign_proc : process(img3_data_stream_0_V_full_n, img3_data_stream_1_V_full_n, img3_data_stream_2_V_full_n, img0_data_stream_0_V_empty_n, img0_data_stream_1_V_empty_n, img0_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter4, exitcond_i_i_i_reg_837, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837, ap_enable_reg_pp0_iter1)
begin
ap_block_pp0_stage0_11001 <= (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((img0_data_stream_2_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img0_data_stream_1_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img0_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)))) or ((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (((img3_data_stream_2_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img3_data_stream_1_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img3_data_stream_0_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)))));
end process;
ap_block_pp0_stage0_subdone_assign_proc : process(img3_data_stream_0_V_full_n, img3_data_stream_1_V_full_n, img3_data_stream_2_V_full_n, img0_data_stream_0_V_empty_n, img0_data_stream_1_V_empty_n, img0_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter4, exitcond_i_i_i_reg_837, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837, ap_enable_reg_pp0_iter1)
begin
ap_block_pp0_stage0_subdone <= (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((img0_data_stream_2_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img0_data_stream_1_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img0_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)))) or ((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (((img3_data_stream_2_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img3_data_stream_1_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img3_data_stream_0_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)))));
end process;
ap_block_state1_assign_proc : process(ap_start, ap_done_reg, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, gamma_empty_n)
begin
ap_block_state1 <= ((gamma_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state4_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage0_iter1_assign_proc : process(img0_data_stream_0_V_empty_n, img0_data_stream_1_V_empty_n, img0_data_stream_2_V_empty_n, exitcond_i_i_i_reg_837)
begin
ap_block_state5_pp0_stage0_iter1 <= (((img0_data_stream_2_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img0_data_stream_1_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img0_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)));
end process;
ap_block_state6_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter4_assign_proc : process(img3_data_stream_0_V_full_n, img3_data_stream_1_V_full_n, img3_data_stream_2_V_full_n, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837)
begin
ap_block_state8_pp0_stage0_iter4 <= (((img3_data_stream_2_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img3_data_stream_1_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img3_data_stream_0_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)));
end process;
ap_condition_pp0_exit_iter0_state4_assign_proc : process(exitcond_i_i_i_fu_556_p2)
begin
if ((exitcond_i_i_i_fu_556_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state4 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state4 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_done_reg, exitcond161_i_i_i_fu_541_p2, ap_CS_fsm_state3)
begin
if (((exitcond161_i_i_i_fu_541_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter2)
begin
if (((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_0))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(exitcond161_i_i_i_fu_541_p2, ap_CS_fsm_state3)
begin
if (((exitcond161_i_i_i_fu_541_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
exitcond161_i_i_i_fu_541_p2 <= "1" when (t_V_cast_i_i_fu_537_p1 = p_rows_assign_cast_lo_reg_762) else "0";
exitcond_i_i_i_fu_556_p2 <= "1" when (t_V_1_cast_i_i_fu_552_p1 = p_cols_assign_cast_lo_reg_767) else "0";
gamma_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, gamma_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
gamma_blk_n <= gamma_empty_n;
else
gamma_blk_n <= ap_const_logic_1;
end if;
end process;
gamma_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, gamma_empty_n)
begin
if ((not(((gamma_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
gamma_read <= ap_const_logic_1;
else
gamma_read <= ap_const_logic_0;
end if;
end process;
i_V_fu_546_p2 <= std_logic_vector(unsigned(t_V_reg_433) + unsigned(ap_const_lv11_1));
img0_data_stream_0_V_blk_n_assign_proc : process(img0_data_stream_0_V_empty_n, ap_block_pp0_stage0, exitcond_i_i_i_reg_837, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
begin
if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
img0_data_stream_0_V_blk_n <= img0_data_stream_0_V_empty_n;
else
img0_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
img0_data_stream_0_V_read_assign_proc : process(exitcond_i_i_i_reg_837, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0))) then
img0_data_stream_0_V_read <= ap_const_logic_1;
else
img0_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
img0_data_stream_1_V_blk_n_assign_proc : process(img0_data_stream_1_V_empty_n, ap_block_pp0_stage0, exitcond_i_i_i_reg_837, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
begin
if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
img0_data_stream_1_V_blk_n <= img0_data_stream_1_V_empty_n;
else
img0_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
img0_data_stream_1_V_read_assign_proc : process(exitcond_i_i_i_reg_837, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0))) then
img0_data_stream_1_V_read <= ap_const_logic_1;
else
img0_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
img0_data_stream_2_V_blk_n_assign_proc : process(img0_data_stream_2_V_empty_n, ap_block_pp0_stage0, exitcond_i_i_i_reg_837, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
begin
if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
img0_data_stream_2_V_blk_n <= img0_data_stream_2_V_empty_n;
else
img0_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
img0_data_stream_2_V_read_assign_proc : process(exitcond_i_i_i_reg_837, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0))) then
img0_data_stream_2_V_read <= ap_const_logic_1;
else
img0_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
img3_data_stream_0_V_blk_n_assign_proc : process(img3_data_stream_0_V_full_n, ap_enable_reg_pp0_iter4, ap_block_pp0_stage0, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837)
begin
if (((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
img3_data_stream_0_V_blk_n <= img3_data_stream_0_V_full_n;
else
img3_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
img3_data_stream_0_V_din <=
newSel6_fu_664_p3 when (or_cond6_reg_821(0) = '1') else
ap_reg_pp0_iter3_tmp_9_reg_846;
img3_data_stream_0_V_write_assign_proc : process(ap_enable_reg_pp0_iter4, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0))) then
img3_data_stream_0_V_write <= ap_const_logic_1;
else
img3_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
img3_data_stream_1_V_blk_n_assign_proc : process(img3_data_stream_1_V_full_n, ap_enable_reg_pp0_iter4, ap_block_pp0_stage0, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837)
begin
if (((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
img3_data_stream_1_V_blk_n <= img3_data_stream_1_V_full_n;
else
img3_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
img3_data_stream_1_V_din <=
newSel13_fu_700_p3 when (or_cond6_reg_821(0) = '1') else
ap_reg_pp0_iter3_tmp_10_reg_852;
img3_data_stream_1_V_write_assign_proc : process(ap_enable_reg_pp0_iter4, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0))) then
img3_data_stream_1_V_write <= ap_const_logic_1;
else
img3_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
img3_data_stream_2_V_blk_n_assign_proc : process(img3_data_stream_2_V_full_n, ap_enable_reg_pp0_iter4, ap_block_pp0_stage0, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837)
begin
if (((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
img3_data_stream_2_V_blk_n <= img3_data_stream_2_V_full_n;
else
img3_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
img3_data_stream_2_V_din <=
newSel20_fu_736_p3 when (or_cond6_reg_821(0) = '1') else
ap_reg_pp0_iter3_tmp_11_reg_858;
img3_data_stream_2_V_write_assign_proc : process(ap_enable_reg_pp0_iter4, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0))) then
img3_data_stream_2_V_write <= ap_const_logic_1;
else
img3_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
j_V_fu_561_p2 <= std_logic_vector(unsigned(t_V_2_reg_444) + unsigned(ap_const_lv11_1));
lut0_2_address0 <= tmp_26_i_i_fu_567_p1(8 - 1 downto 0);
lut0_2_address1 <= tmp_26_1_i_i_fu_578_p1(8 - 1 downto 0);
lut0_2_address2 <= tmp_26_2_i_i_fu_589_p1(8 - 1 downto 0);
lut0_2_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut0_2_ce0 <= ap_const_logic_1;
else
lut0_2_ce0 <= ap_const_logic_0;
end if;
end process;
lut0_2_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut0_2_ce1 <= ap_const_logic_1;
else
lut0_2_ce1 <= ap_const_logic_0;
end if;
end process;
lut0_2_ce2_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut0_2_ce2 <= ap_const_logic_1;
else
lut0_2_ce2 <= ap_const_logic_0;
end if;
end process;
lut0_4_address0 <= tmp_26_i_i_fu_567_p1(8 - 1 downto 0);
lut0_4_address1 <= tmp_26_1_i_i_fu_578_p1(8 - 1 downto 0);
lut0_4_address2 <= tmp_26_2_i_i_fu_589_p1(8 - 1 downto 0);
lut0_4_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut0_4_ce0 <= ap_const_logic_1;
else
lut0_4_ce0 <= ap_const_logic_0;
end if;
end process;
lut0_4_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut0_4_ce1 <= ap_const_logic_1;
else
lut0_4_ce1 <= ap_const_logic_0;
end if;
end process;
lut0_4_ce2_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut0_4_ce2 <= ap_const_logic_1;
else
lut0_4_ce2 <= ap_const_logic_0;
end if;
end process;
lut1_2_address0 <= tmp_26_i_i_fu_567_p1(8 - 1 downto 0);
lut1_2_address1 <= tmp_26_1_i_i_fu_578_p1(8 - 1 downto 0);
lut1_2_address2 <= tmp_26_2_i_i_fu_589_p1(8 - 1 downto 0);
lut1_2_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_2_ce0 <= ap_const_logic_1;
else
lut1_2_ce0 <= ap_const_logic_0;
end if;
end process;
lut1_2_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_2_ce1 <= ap_const_logic_1;
else
lut1_2_ce1 <= ap_const_logic_0;
end if;
end process;
lut1_2_ce2_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_2_ce2 <= ap_const_logic_1;
else
lut1_2_ce2 <= ap_const_logic_0;
end if;
end process;
lut1_4_address0 <= tmp_26_i_i_fu_567_p1(8 - 1 downto 0);
lut1_4_address1 <= tmp_26_1_i_i_fu_578_p1(8 - 1 downto 0);
lut1_4_address2 <= tmp_26_2_i_i_fu_589_p1(8 - 1 downto 0);
lut1_4_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_4_ce0 <= ap_const_logic_1;
else
lut1_4_ce0 <= ap_const_logic_0;
end if;
end process;
lut1_4_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_4_ce1 <= ap_const_logic_1;
else
lut1_4_ce1 <= ap_const_logic_0;
end if;
end process;
lut1_4_ce2_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_4_ce2 <= ap_const_logic_1;
else
lut1_4_ce2 <= ap_const_logic_0;
end if;
end process;
lut1_6_address0 <= tmp_26_i_i_fu_567_p1(8 - 1 downto 0);
lut1_6_address1 <= tmp_26_1_i_i_fu_578_p1(8 - 1 downto 0);
lut1_6_address2 <= tmp_26_2_i_i_fu_589_p1(8 - 1 downto 0);
lut1_6_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_6_ce0 <= ap_const_logic_1;
else
lut1_6_ce0 <= ap_const_logic_0;
end if;
end process;
lut1_6_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_6_ce1 <= ap_const_logic_1;
else
lut1_6_ce1 <= ap_const_logic_0;
end if;
end process;
lut1_6_ce2_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_6_ce2 <= ap_const_logic_1;
else
lut1_6_ce2 <= ap_const_logic_0;
end if;
end process;
lut1_8_address0 <= tmp_26_i_i_fu_567_p1(8 - 1 downto 0);
lut1_8_address1 <= tmp_26_1_i_i_fu_578_p1(8 - 1 downto 0);
lut1_8_address2 <= tmp_26_2_i_i_fu_589_p1(8 - 1 downto 0);
lut1_8_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_8_ce0 <= ap_const_logic_1;
else
lut1_8_ce0 <= ap_const_logic_0;
end if;
end process;
lut1_8_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_8_ce1 <= ap_const_logic_1;
else
lut1_8_ce1 <= ap_const_logic_0;
end if;
end process;
lut1_8_ce2_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_8_ce2 <= ap_const_logic_1;
else
lut1_8_ce2 <= ap_const_logic_0;
end if;
end process;
lut2_0_address0 <= tmp_26_i_i_fu_567_p1(8 - 1 downto 0);
lut2_0_address1 <= tmp_26_1_i_i_fu_578_p1(8 - 1 downto 0);
lut2_0_address2 <= tmp_26_2_i_i_fu_589_p1(8 - 1 downto 0);
lut2_0_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut2_0_ce0 <= ap_const_logic_1;
else
lut2_0_ce0 <= ap_const_logic_0;
end if;
end process;
lut2_0_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut2_0_ce1 <= ap_const_logic_1;
else
lut2_0_ce1 <= ap_const_logic_0;
end if;
end process;
lut2_0_ce2_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut2_0_ce2 <= ap_const_logic_1;
else
lut2_0_ce2 <= ap_const_logic_0;
end if;
end process;
lut2_2_address0 <= tmp_26_i_i_fu_567_p1(8 - 1 downto 0);
lut2_2_address1 <= tmp_26_1_i_i_fu_578_p1(8 - 1 downto 0);
lut2_2_address2 <= tmp_26_2_i_i_fu_589_p1(8 - 1 downto 0);
lut2_2_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut2_2_ce0 <= ap_const_logic_1;
else
lut2_2_ce0 <= ap_const_logic_0;
end if;
end process;
lut2_2_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut2_2_ce1 <= ap_const_logic_1;
else
lut2_2_ce1 <= ap_const_logic_0;
end if;
end process;
lut2_2_ce2_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut2_2_ce2 <= ap_const_logic_1;
else
lut2_2_ce2 <= ap_const_logic_0;
end if;
end process;
newSel10_fu_621_p3 <=
lut2_0_q1 when (sel_tmp2_reg_772(0) = '1') else
lut2_2_q1;
newSel11_fu_688_p3 <=
newSel8_fu_678_p3 when (or_cond_reg_800(0) = '1') else
newSel9_reg_1034;
newSel12_fu_694_p3 <=
newSel7_fu_683_p3 when (or_cond2_reg_807(0) = '1') else
newSel10_reg_1039;
newSel13_fu_700_p3 <=
newSel11_fu_688_p3 when (or_cond4_reg_814(0) = '1') else
newSel12_fu_694_p3;
newSel14_fu_714_p3 <=
d_val_2_2_reg_1044 when (sel_tmp5_reg_793(0) = '1') else
d_val_2_3_reg_1049;
newSel15_fu_628_p3 <=
lut1_2_q2 when (sel_tmp1_reg_786(0) = '1') else
lut1_4_q2;
newSel16_fu_719_p3 <=
d_val_2_6_reg_1054 when (sel_tmp6_reg_779(0) = '1') else
d_val_2_7_reg_1059;
newSel17_fu_635_p3 <=
lut2_0_q2 when (sel_tmp2_reg_772(0) = '1') else
lut2_2_q2;
newSel18_fu_724_p3 <=
newSel14_fu_714_p3 when (or_cond_reg_800(0) = '1') else
newSel15_reg_1064;
newSel19_fu_730_p3 <=
newSel16_fu_719_p3 when (or_cond2_reg_807(0) = '1') else
newSel17_reg_1069;
newSel1_fu_600_p3 <=
lut1_2_q0 when (sel_tmp1_reg_786(0) = '1') else
lut1_4_q0;
newSel20_fu_736_p3 <=
newSel18_fu_724_p3 when (or_cond4_reg_814(0) = '1') else
newSel19_fu_730_p3;
newSel2_fu_647_p3 <=
d_val_0_6_reg_994 when (sel_tmp6_reg_779(0) = '1') else
d_val_0_7_reg_999;
newSel3_fu_607_p3 <=
lut2_0_q0 when (sel_tmp2_reg_772(0) = '1') else
lut2_2_q0;
newSel4_fu_652_p3 <=
newSel_fu_642_p3 when (or_cond_reg_800(0) = '1') else
newSel1_reg_1004;
newSel5_fu_658_p3 <=
newSel2_fu_647_p3 when (or_cond2_reg_807(0) = '1') else
newSel3_reg_1009;
newSel6_fu_664_p3 <=
newSel4_fu_652_p3 when (or_cond4_reg_814(0) = '1') else
newSel5_fu_658_p3;
newSel7_fu_683_p3 <=
d_val_1_6_reg_1024 when (sel_tmp6_reg_779(0) = '1') else
d_val_1_7_reg_1029;
newSel8_fu_678_p3 <=
d_val_1_2_reg_1014 when (sel_tmp5_reg_793(0) = '1') else
d_val_1_3_reg_1019;
newSel9_fu_614_p3 <=
lut1_2_q1 when (sel_tmp1_reg_786(0) = '1') else
lut1_4_q1;
newSel_fu_642_p3 <=
d_val_0_2_reg_984 when (sel_tmp5_reg_793(0) = '1') else
d_val_0_3_reg_989;
or_cond1_fu_501_p2 <= (sel_tmp8_fu_475_p2 or sel_tmp1_fu_480_p2);
or_cond2_fu_507_p2 <= (sel_tmp6_fu_470_p2 or sel_tmp4_fu_465_p2);
or_cond3_fu_513_p2 <= (sel_tmp_fu_455_p2 or sel_tmp2_fu_460_p2);
or_cond4_fu_519_p2 <= (or_cond_fu_495_p2 or or_cond1_fu_501_p2);
or_cond5_fu_525_p2 <= (or_cond3_fu_513_p2 or or_cond2_fu_507_p2);
or_cond6_fu_531_p2 <= (or_cond5_fu_525_p2 or or_cond4_fu_519_p2);
or_cond_fu_495_p2 <= (sel_tmp5_fu_490_p2 or sel_tmp3_fu_485_p2);
p_cols_assign_cast_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_cols_assign_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_cols_assign_cast_loc_blk_n <= p_cols_assign_cast_loc_empty_n;
else
p_cols_assign_cast_loc_blk_n <= ap_const_logic_1;
end if;
end process;
p_cols_assign_cast_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, gamma_empty_n)
begin
if ((not(((gamma_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_cols_assign_cast_loc_read <= ap_const_logic_1;
else
p_cols_assign_cast_loc_read <= ap_const_logic_0;
end if;
end process;
p_rows_assign_cast_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_rows_assign_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_rows_assign_cast_loc_blk_n <= p_rows_assign_cast_loc_empty_n;
else
p_rows_assign_cast_loc_blk_n <= ap_const_logic_1;
end if;
end process;
p_rows_assign_cast_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, gamma_empty_n)
begin
if ((not(((gamma_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_rows_assign_cast_loc_read <= ap_const_logic_1;
else
p_rows_assign_cast_loc_read <= ap_const_logic_0;
end if;
end process;
sel_tmp1_fu_480_p2 <= "1" when (gamma_read_reg_750 = ap_const_lv8_3) else "0";
sel_tmp2_fu_460_p2 <= "1" when (gamma_read_reg_750 = ap_const_lv8_7) else "0";
sel_tmp3_fu_485_p2 <= "1" when (gamma_read_reg_750 = ap_const_lv8_2) else "0";
sel_tmp4_fu_465_p2 <= "1" when (gamma_read_reg_750 = ap_const_lv8_6) else "0";
sel_tmp5_fu_490_p2 <= "1" when (gamma_read_reg_750 = ap_const_lv8_1) else "0";
sel_tmp6_fu_470_p2 <= "1" when (gamma_read_reg_750 = ap_const_lv8_5) else "0";
sel_tmp8_fu_475_p2 <= "1" when (gamma_read_reg_750 = ap_const_lv8_4) else "0";
sel_tmp_fu_455_p2 <= "1" when (gamma_read_reg_750 = ap_const_lv8_8) else "0";
t_V_1_cast_i_i_fu_552_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_2_reg_444),12));
t_V_cast_i_i_fu_537_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_reg_433),12));
tmp_26_1_i_i_fu_578_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_reg_852),64));
tmp_26_2_i_i_fu_589_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_reg_858),64));
tmp_26_i_i_fu_567_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_reg_846),64));
end behav;
|
-- Vhdl test bench created from schematic /home/emmanuel/current_projects/Xilinx/Workspace/cpu_v2/ALU.sch - Fri Jun 8 12:08:08 2012
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY ALU_ALU_sch_tb IS
END ALU_ALU_sch_tb;
ARCHITECTURE behavioral OF ALU_ALU_sch_tb IS
COMPONENT ALU
PORT( Reg2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
Reg1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
Result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ALUControl : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
Zero : OUT STD_LOGIC);
END COMPONENT;
SIGNAL Reg2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL Reg1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL Result : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL ALUControl : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL Zero : STD_LOGIC;
BEGIN
UUT: ALU PORT MAP(
Reg2 => Reg2,
Reg1 => Reg1,
Result => Result,
ALUControl => ALUControl,
Zero => Zero
);
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
-- Test add : 2 + 3 = 5
Reg1 <= "00000000000000000000000000000010";
Reg2 <= "00000000000000000000000000000011";
ALUControl <= "0010";
wait for 1ms;
-- Test sub : 3 - 3 = 0
Reg1 <= "00000000000000000000000000000011";
Reg2 <= "00000000000000000000000000000011";
ALUControl <= "0110";
wait for 1ms;
-- Test and 15 & 6 = 6
Reg1 <= "00000000000000000000000000001111";
Reg2 <= "00000000000000000000000000000110";
ALUControl <= "0000";
wait for 1ms;
-- Test or : 15 | 6 = 15
Reg1 <= "00000000000000000000000000001111";
Reg2 <= "00000000000000000000000000000110";
ALUControl <= "0001";
wait for 1ms;
-- Test xor : 7 xor 5 = 2
Reg1 <= "00000000000000000000000000000111";
Reg2 <= "00000000000000000000000000000101";
ALUControl <= "0011";
wait for 1ms;
-- Test slt : 1 slt 4 = 1
Reg1 <= "00000000000000000000000000000001";
Reg2 <= "00000000000000000000000000000100";
ALUControl <= "0111";
wait for 1ms;
WAIT; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
|
package pack is
constant C : integer;
type rec is record
x : integer;
y : bit_vector(1 to C);
end record;
end package;
package body pack is
constant C : integer := 4;
end package body;
-------------------------------------------------------------------------------
entity issue549 is
end entity;
use work.pack.all;
architecture test of issue549 is
constant def : rec := (x => 0, y => "0000");
procedure modify (variable arg : inout rec) is
begin
arg.y(1) := '1';
end procedure;
procedure test (arg : in rec) is
variable copy : rec := def;
begin
copy.y := arg.y;
modify(copy);
assert def.y = "0000";
assert copy.y = "1110";
end procedure;
begin
p1: test((x => 1, y => "0110"));
end architecture;
|
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- fLink definitions --
-- --
-- THIS FILE WAS CREATED AUTOMATICALLY - do not change --
-- --
-- Created with: flinkinterface/func_id/ --
-- create_flink_definitions.vhd_flinkVHDL.sh --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE fLink_definitions IS
-- Global
CONSTANT c_fLink_avs_data_width : INTEGER := 32;
CONSTANT c_fLink_avs_data_width_in_byte : INTEGER := c_fLink_avs_data_width/8;
-- Header registers
CONSTANT c_fLink_number_of_std_registers : INTEGER := 8;
CONSTANT c_fLink_typdef_address : INTEGER := 0;
CONSTANT c_fLink_mem_size_address : INTEGER := 1;
CONSTANT c_fLink_number_of_channels_address : INTEGER := 2;
CONSTANT c_fLink_unique_id_address : INTEGER := 3;
CONSTANT c_fLink_status_address : INTEGER := 4;
CONSTANT c_fLink_configuration_address : INTEGER := 5;
CONSTANT c_fLink_id_length : INTEGER := 16;
CONSTANT c_fLink_subtype_length : INTEGER := 8;
CONSTANT c_fLink_interface_version_length : INTEGER := 8;
CONSTANT c_fLink_reset_bit_num : INTEGER := 0;
-- Interface IDs:
CONSTANT c_fLink_info_id : INTEGER RANGE 0 TO 65535 := 0;
CONSTANT c_fLink_analog_input_id : INTEGER RANGE 0 TO 65535 := 1;
CONSTANT c_fLink_analog_output_id : INTEGER RANGE 0 TO 65535 := 2;
CONSTANT c_fLink_digital_io_id : INTEGER RANGE 0 TO 65535 := 5;
CONSTANT c_fLink_counter_id : INTEGER RANGE 0 TO 65535 := 6;
CONSTANT c_fLink_timer_id : INTEGER RANGE 0 TO 65535 := 7;
CONSTANT c_fLink_memory_id : INTEGER RANGE 0 TO 65535 := 8;
CONSTANT c_fLink_pwm_out_id : INTEGER RANGE 0 TO 65535 := 12;
CONSTANT c_fLink_ppwa_id : INTEGER RANGE 0 TO 65535 := 13;
CONSTANT c_fLink_uart_id : INTEGER RANGE 0 TO 65535 := 15;
CONSTANT c_fLink_watchdog_id : INTEGER RANGE 0 TO 65535 := 16;
CONSTANT c_fLink_sensor_id : INTEGER RANGE 0 TO 65535 := 17;
END PACKAGE fLink_definitions;
|
-- ----------------------------------------------------------------------------
-- Entity for conversion from binary state encoding to one hot encoding
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity DECODER%$% is
generic(
INPUT_DATA_WIDTH : integer := %$%;
OUTPUT_DATA_WIDTH : integer := %$%
);
port(
-- input data interface
INPUT : in std_logic_vector(INPUT_DATA_WIDTH - 1 downto 0);
-- output data interface
OUTPUT : out std_logic_vector(OUTPUT_DATA_WIDTH - 1 downto 0)
);
end entity DECODER%$%;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of DECODER%$% is
signal bin : std_logic_vector(OUTPUT_DATA_WIDTH - 1 downto 0);
%$%
begin
%$%
end architecture full; |
--4选1数据选择器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUXB41 IS
PORT(DATA0,DATA1,DATA2,DATA3:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
A,B:IN STD_LOGIC;
Y:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY;
ARCHITECTURE ART OF MUXB41 IS
SIGNAL SEL:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
SEL<=B&A;
PROCESS(SEL)
BEGIN
CASE SEL IS
WHEN "00"=>Y<=DATA0;
WHEN "01"=>Y<=DATA1;
WHEN "10"=>Y<=DATA2;
WHEN "11"=>Y<=DATA3;
WHEN OTHERS=>Y<=NULL;
END CASE;
END PROCESS;
END ARCHITECTURE ART; |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ethernet_control is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
cnt_23 : in STD_LOGIC;
cnt_22 : in STD_LOGIC;
PhyRstn : out STD_LOGIC);
end ethernet_control;
architecture Behavioral of ethernet_control is
begin
-- PHY requires reset to be asserted for 100 uS
phy_reset: process (clk)
variable done : STD_LOGIC := '0';
begin
if RISING_EDGE(clk) then
if done = '0' then
PhyRstn <= not cnt_22;
end if;
done := done or cnt_23;
if rst = '1' then
done := '0';
PhyRstn <= '0';
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: udp_add_udp_header - Behavioral
--
-- Description: Add the UDP header to a data stream
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity udp_add_udp_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ip_src_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
ip_dst_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
udp_src_port : in std_logic_vector(15 downto 0);
udp_dst_port : in std_logic_vector(15 downto 0);
data_length : in std_logic_vector(15 downto 0);
data_checksum : in std_logic_vector(15 downto 0));
end udp_add_udp_header;
architecture Behavioral of udp_add_udp_header is
type a_data_delay is array(0 to 8) of std_logic_vector(8 downto 0);
signal data_delay : a_data_delay := (others => (others => '0'));
----------------------------------------------------------------
-- Note: Set the initial state to pass the data striaght through
----------------------------------------------------------------
signal count : unsigned(3 downto 0) := (others => '1');
signal data_valid_in_last : std_logic := '0';
signal udp_length : std_logic_vector(15 downto 0);
signal udp_checksum_u1a : unsigned(19 downto 0);
signal udp_checksum_u1b : unsigned(19 downto 0);
signal udp_checksum_u2 : unsigned(16 downto 0);
signal udp_checksum_u3 : unsigned(15 downto 0);
signal udp_checksum : std_logic_vector(15 downto 0);
--------------------------------------------------------------------
-- UDP checksum is calculated based on a pseudo header that includes
-- the source and destination IP addresses
--------------------------------------------------------------------
signal pseudohdr_0 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_2 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_3 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_4 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_5 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_6 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_7 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_8 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_9 : std_logic_vector(15 downto 0) := (others => '0');
begin
udp_length <= std_logic_vector(unsigned(data_length)+8);
pseudohdr_0 <= ip_src_ip( 7 downto 0) & ip_src_ip(15 downto 8);
pseudohdr_1 <= ip_src_ip(23 downto 16) & ip_src_ip(31 downto 24);
pseudohdr_2 <= ip_dst_ip( 7 downto 0) & ip_dst_ip(15 downto 8);
pseudohdr_3 <= ip_dst_ip(23 downto 16) & ip_dst_ip(31 downto 24);
pseudohdr_4 <= x"0011"; -- UDP Protocol
pseudohdr_5 <= udp_length;
pseudohdr_6 <= udp_src_port;
pseudohdr_7 <= udp_dst_port;
pseudohdr_8 <= udp_length;
pseudohdr_9 <= udp_checksum;
process(clk)
begin
if rising_edge(clk) then
case count is
when "0000" => data_out <= udp_src_port(15 downto 8); data_valid_out <= '1';
when "0001" => data_out <= udp_src_port( 7 downto 0); data_valid_out <= '1';
when "0010" => data_out <= udp_dst_port(15 downto 8); data_valid_out <= '1';
when "0011" => data_out <= udp_dst_port( 7 downto 0); data_valid_out <= '1';
when "0100" => data_out <= udp_length(15 downto 8); data_valid_out <= '1';
when "0101" => data_out <= udp_length( 7 downto 0); data_valid_out <= '1';
when "0110" => data_out <= udp_checksum(15 downto 8); data_valid_out <= '1';
when "0111" => data_out <= udp_checksum( 7 downto 0); data_valid_out <= '1';
when others => data_out <= data_delay(0)(7 downto 0); data_valid_out <= data_delay(0)(8);
end case;
data_delay(0 to data_delay'high-1) <= data_delay(1 to data_delay'high);
if data_valid_in = '1' then
data_delay(data_delay'high) <= '1' & data_in;
if data_valid_in_last = '0' then
count <= (others => '0');
elsif count /= "1111" then
count <= count + 1;
end if;
else
data_delay(data_delay'high) <= (others => '0');
if count /= "1111" then
count <= count + 1;
end if;
end if;
data_valid_in_last <= data_valid_in;
-- Pipelined checksum calculation
udp_checksum_u1a <= to_unsigned(0,20) + unsigned(pseudohdr_0) + unsigned(pseudohdr_1)
+ unsigned(pseudohdr_2) + unsigned(pseudohdr_3)
+ unsigned(pseudohdr_4);
udp_checksum_u1b <= to_unsigned(0,20) + unsigned(pseudohdr_5)
+ unsigned(pseudohdr_6) + unsigned(pseudohdr_7)
+ unsigned(pseudohdr_8) + unsigned(data_checksum);
udp_checksum_u2 <= to_unsigned(0,17) + udp_checksum_u1a(15 downto 0) + udp_checksum_u1a(19 downto 16)
+ udp_checksum_u1b(15 downto 0) + udp_checksum_u1b(19 downto 16);
udp_checksum_u3 <= udp_checksum_u2(15 downto 0) + udp_checksum_u2(16 downto 16);
udp_checksum <= not std_logic_vector(udp_checksum_u3);
end if;
end process;
end Behavioral; |
# For complete documentation of this file, please see Geany's main documentation
[styling]
# foreground;background;bold;italic
default=0x000000;0xffffff;false;false
comment=0xd00000;0xffffff;false;false
comment_line_bang=0x3f5fbf;0xffffff;false;false;
number=0x007f00;0xffffff;false;false
string=0xff901e;0xffffff;false;false
operator=0x301010;0xffffff;false;false
identifier=0x000000;0xffffff;false;false
stringeol=0x000000;0xe0c0e0;false;false
keyword=0x001a7f;0xffffff;true;false
stdoperator=0x007f7f;0xffffff;false;false
attribute=0x804020;0xffffff;false;false
stdfunction=0x808020;0xffffff;true;false
stdpackage=0x208020;0xffffff;false;false
stdtype=0x208080;0xffffff;false;false
userword=0x804020;0xffffff;true;false
[keywords]
# all items must be in one line
keywords=access after alias all architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map new next null of on open others out package port postponed procedure process pure range record register reject report return select severity shared signal subtype then to transport type unaffected units until use variable wait when while with
operators=abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
attributes=left right low high ascending image value pos val succ pred leftof rightof base range reverse_range length delayed stable quiet transaction event active last_event last_active last_value driving driving_value simple_name path_name instance_name
std_functions=now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left rotate_right resize to_integer to_unsigned to_signed std_match to_01
std_packages=std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives vital_timing
std_types=boolean bit character severity_level integer real time delay_length natural positive string bit_vector file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic std_logic_vector X01 X01Z UX01 UX01Z unsigned signed
userwords=
[settings]
# default extension used when saving files
extension=vhd
# the following characters are these which a "word" can contains, see documentation
#wordchars=_abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789
# single comments, like # in this file
comment_single=--
# multiline comments
#comment_open=
#comment_close=
# set to false if a comment character/string should start at column 0 of a line, true uses any
# indentation of the line, e.g. setting to true causes the following on pressing CTRL+d
#command_example();
# setting to false would generate this
# command_example();
# This setting works only for single line comments
comment_use_indent=true
# context action command (please see Geany's main documentation for details)
context_action_cmd=
[indentation]
#width=4
# 0 is spaces, 1 is tabs, 2 is tab & spaces
#type=1
|
--
-- This entity converts button states to the SNES communication protocol
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.snes_lib.all;
entity snes_btn_ctrl is
port (
clk_i : in std_logic;
pause_o : out std_logic;
snes_js_btn_i : in snes_js_btn_r;
snes_js_bus_i : in snes_js_bus_i_r;
snes_js_bus_o : out snes_js_bus_o_r;
clock_indicator_o : out std_logic;
latch_indicator_o : out std_logic
);
end entity snes_btn_ctrl;
architecture behavioral of snes_btn_ctrl is
-- latches the state of the buttons
signal btn_r : std_logic_vector(15 downto 0);
signal btn_next_r : std_logic_vector(15 downto 0);
signal latch_r : std_logic;
signal ext_clock_r : std_logic;
signal prev_latch_r : std_logic;
signal prev_ext_clock_r : std_logic;
signal latch_rising_s : std_logic;
signal ext_clock_rising_s : std_logic;
signal clk_counter_s : unsigned(15 downto 0);
signal clk_counter_next_s : unsigned(15 downto 0);
signal latch_counter_s : unsigned(15 downto 0);
signal latch_counter_next_s : unsigned(15 downto 0);
begin
clock_proc: process (clk_i)
begin
if rising_edge(clk_i) then
prev_latch_r <= latch_r;
prev_ext_clock_r <= ext_clock_r;
ext_clock_r <= snes_js_bus_i.clock;
latch_r <= snes_js_bus_i.latch;
btn_r <= btn_next_r;
clk_counter_s <= clk_counter_next_s;
latch_counter_s <= latch_counter_next_s;
end if;
end process;
latch_rising_s <= not(prev_latch_r) and latch_r;
ext_clock_rising_s <= not(prev_ext_clock_r) and ext_clock_r;
clock_indicator_o <= clk_counter_s(3);
latch_indicator_o <= latch_counter_s(6);
pause_o <= '0' when clk_counter_s > 15 else '1';
snes_js_bus_o.data <= not(btn_r(0));
comb_proc : process (ext_clock_rising_s, latch_r, btn_r, btn_next_r, clk_counter_s, latch_counter_s, latch_rising_s,
snes_js_btn_i.up, snes_js_btn_i.left, snes_js_btn_i.right, snes_js_btn_i.down,
snes_js_btn_i.a, snes_js_btn_i.b, snes_js_btn_i.x, snes_js_btn_i.y, snes_js_btn_i.start,
snes_js_btn_i.sel, snes_js_btn_i.l, snes_js_btn_i.r)
begin
btn_next_r <= btn_r;
latch_counter_next_s <= latch_counter_s;
clk_counter_next_s <= clk_counter_s;
-- latch button state
if latch_rising_s = '1' then
latch_counter_next_s <= latch_counter_s + 1;
elsif latch_r = '1' then
btn_next_r(0) <= snes_js_btn_i.b;
btn_next_r(1) <= snes_js_btn_i.y;
btn_next_r(2) <= snes_js_btn_i.sel;
btn_next_r(3) <= snes_js_btn_i.start;
btn_next_r(4) <= snes_js_btn_i.up;
btn_next_r(5) <= snes_js_btn_i.down;
btn_next_r(6) <= snes_js_btn_i.left;
btn_next_r(7) <= snes_js_btn_i.right;
btn_next_r(8) <= snes_js_btn_i.a;
btn_next_r(9) <= snes_js_btn_i.x;
btn_next_r(10) <= snes_js_btn_i.l;
btn_next_r(11) <= snes_js_btn_i.r;
btn_next_r(15 downto 12) <= "0000"; -- unused bits
clk_counter_next_s <= x"0000";
-- shift out our values
elsif ext_clock_rising_s = '1' then
for i in 0 to 14 loop
btn_next_r(i) <= btn_r(i+1);
end loop;
btn_next_r(15) <= '0';
clk_counter_next_s <= clk_counter_s + 1;
end if;
end process;
end;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- TestBench --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.STD_LOGIC_UNSIGNED.all;
LIBRARY std;
USE std.TEXTIO.all;
USE work.utils.all;
entity papilio1_tb is
end papilio1_tb ;
ARCHITECTURE struct OF papilio1_tb IS
-- Architecture declarations
signal dind1_s : std_logic;
signal dind2_s : std_logic;
-- Internal signal declarations
SIGNAL CLOCK_40MHZ : std_logic := '0';
SIGNAL CLOCK_32MHZ : std_logic := '0';
SIGNAL CTS : std_logic;
SIGNAL resetn : std_logic;
SIGNAL TXD : std_logic;
SIGNAL cpuerror : std_logic;
SIGNAL rdn_s : std_logic; -- Active Low Read Pulse (CLK)
SIGNAL rdrf : std_logic;
SIGNAL rxenable : std_logic;
SIGNAL txcmd : std_logic;
SIGNAL txenable : std_logic;
SIGNAL udbus : Std_Logic_Vector(7 DOWNTO 0);
CONSTANT DIVIDER_c : std_logic_vector(7 downto 0):="01000001"; -- 65, baudrate divider 40MHz
SIGNAL divtx_s : std_logic_vector(3 downto 0);
SIGNAL divcnt_s : std_logic_vector(7 downto 0);
SIGNAL rxclk16_s : std_logic;
SIGNAL tdre_s : std_logic;
SIGNAL wrn_s : std_logic;
SIGNAL char_s : std_logic_vector(7 downto 0);
signal rx : STD_LOGIC;
signal tx : STD_LOGIC;
signal W1A : STD_LOGIC_VECTOR (15 downto 0);
signal W1B : STD_LOGIC_VECTOR (15 downto 0);
signal W2C : STD_LOGIC_VECTOR (15 downto 0);
signal clk : STD_LOGIC;
-- Component Declarations
COMPONENT papilio1_top
Port ( rx : in STD_LOGIC;
tx : out STD_LOGIC;
W1A : inout STD_LOGIC_VECTOR (15 downto 0);
W1B : inout STD_LOGIC_VECTOR (15 downto 0);
W2C : inout STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC);
END COMPONENT;
component Aaatop
Port (
CLK : in STD_LOGIC;
txd : inout std_logic;
rxd : in std_logic;
ARD_RESET : out STD_LOGIC;
DUO_SW1 : in STD_LOGIC;
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
Arduino : inout STD_LOGIC_VECTOR (53 downto 0)
);
end component;
COMPONENT uartrx
PORT (
clk : IN std_logic;
enable : IN std_logic;
rdn : IN std_logic;
resetn : IN std_logic;
rx : IN std_logic;
dbus : OUT std_logic_vector (7 DOWNTO 0);
ferror : OUT std_logic;
rdrf : OUT std_logic
);
END COMPONENT;
COMPONENT uarttx
PORT (
clk : in std_logic ;
enable : in std_logic ; -- 1 x bit_rate transmit clock enable
resetn : in std_logic ;
dbus : in std_logic_vector (7 downto 0); -- input to txshift register
tdre : out std_logic ;
wrn : in std_logic ;
tx : out std_logic);
END COMPONENT;
BEGIN
CLOCK_40MHZ <= not CLOCK_40MHZ after 12.5 ns; -- 40MHz
-- CLOCK_40MHZ <= not CLOCK_40MHZ after 25 ns; -- 20MHz
CLOCK_32MHZ <= not CLOCK_32MHZ after 15.625 ns; -- 32MHz
process
variable L : line;
procedure write_to_uart (char_in : IN character) is
begin
char_s <=to_std_logic_vector(char_in);
wait until rising_edge(CLOCK_40MHZ);
wrn_s <= '0';
wait until rising_edge(CLOCK_40MHZ);
wrn_s <= '1';
wait until rising_edge(CLOCK_40MHZ);
wait until rising_edge(tdre_s);
end;
begin
CTS <= '1';
resetn <= '0'; -- PIN3 on Drigmorn1 connected to PIN2
wait for 100 ns;
resetn <= '1';
wrn_s <= '1'; -- Active low write strobe to TX UART
char_s <= (others => '1');
wait for 25.1 ms; -- wait for > prompt before issuing commands
-- write_to_uart('R');
write_to_uart('H');
wait for 47 ms; -- wait for > prompt before issuing commands
write_to_uart('D'); -- Issue Fill Memory command
write_to_uart('M');
write_to_uart('0');
write_to_uart('1');
write_to_uart('0');
write_to_uart('0');
wait for 1 ms;
write_to_uart('0');
write_to_uart('1');
write_to_uart('2');
write_to_uart('4');
wait for 50 ms; -- wait for > prompt before issuing commands
wait;
end process;
------------------------------------------------------------------------------
-- 8 bits divider
-- Generate rxenable clock (16 x baudrate)
------------------------------------------------------------------------------
process (CLOCK_40MHZ,resetn) -- First divider
begin
if (resetn='0') then
divcnt_s <= (others => '0');
rxclk16_s <= '0'; -- Receive clock (x16, pulse)
elsif (rising_edge(CLOCK_40MHZ)) then
if divcnt_s=DIVIDER_c then
divcnt_s <= (others => '0');
rxclk16_s <= '1';
else
rxclk16_s <= '0';
divcnt_s <= divcnt_s + '1';
end if;
end if;
end process;
rxenable <= rxclk16_s;
------------------------------------------------------------------------------
-- divider by 16
-- rxclk16/16=txclk
------------------------------------------------------------------------------
process (CLOCK_40MHZ,resetn)
begin
if (resetn='0') then
divtx_s <= (others => '0');
elsif (rising_edge(CLOCK_40MHZ)) then
if rxclk16_s='1' then
divtx_s <= divtx_s + '1';
if divtx_s="0000" then
txenable <= '1';
end if;
else
txenable <= '0';
end if;
end if;
end process;
assert not ((NOW > 0 ns) and cpuerror='1') report "**** CPU Error flag asserted ****" severity error;
------------------------------------------------------------------------------
-- UART Monitor
-- Display string on console after 80 characters or when CR character is received
------------------------------------------------------------------------------
process (rdrf,resetn)
variable L : line;
variable i_v : integer;
begin
if resetn='0' then
i_v := 0; -- clear character counter
elsif (rising_edge(rdrf)) then -- possible, pulse is wide!
if i_v=0 then
write(L,string'("RD UART : "));
if (udbus/=X"0D" and udbus/=X"0A") then
write(L,std_to_char(udbus));
end if;
i_v := i_v+1;
elsif (i_v=80 or udbus=X"0D") then
writeline(output,L);
i_v:=0;
else
if (udbus/=X"0D" and udbus/=X"0A") then
write(L,std_to_char(udbus));
end if;
i_v := i_v+1;
end if;
end if;
end process;
process (CLOCK_40MHZ,resetn) -- First/Second delay
begin
if (resetn='0') then
dind1_s <= '0';
dind2_s <= '0';
elsif (rising_edge(CLOCK_40MHZ)) then
dind1_s <= rdrf;
dind2_s <= dind1_s;
end if;
end process;
rdn_s <= '0' when (dind1_s='1' and dind2_s='0') else '1';
------------------------------------------------------------------------------
-- Top Level CPU+RAM+UART
------------------------------------------------------------------------------
U_0 : Aaatop Port map(
CLK => clk,
txd => tx,
rxd => rx,
ARD_RESET => open,
DUO_SW1 => '0',
sram_addr => open,
sram_data => open,
sram_ce => open,
sram_we => open,
sram_oe => open,
Arduino => open
);
clk <= CLOCK_32MHZ;
TXD <= tx;
rx <= txcmd;
-- w1b(1) <= resetn;
-- CTS => CTS,
-- PIN3 => resetn,
-- RXD => txcmd,
--TXD => TXD,
-- LED1 => cpuerror,
------------------------------------------------------------------------------
-- TX Uart
------------------------------------------------------------------------------
U_1 : uarttx
port map (
clk => CLOCK_40MHZ,
enable => txenable,
resetn => resetn,
dbus => char_s,
tdre => tdre_s,
wrn => wrn_s,
tx => txcmd
);
------------------------------------------------------------------------------
-- RX Uart
------------------------------------------------------------------------------
U_2 : uartrx
PORT MAP (
clk => CLOCK_40MHZ,
enable => rxenable,
resetn => resetn,
dbus => udbus,
rdn => rdn_s,
rdrf => rdrf,
ferror => OPEN,
rx => TXD
);
END struct;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1324.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p02n01i01324ent IS
END c08s04b01x00p02n01i01324ent;
ARCHITECTURE c08s04b01x00p02n01i01324arch OF c08s04b01x00p02n01i01324ent IS
signal k : BIT ;
BEGIN
TESTING: PROCESS
BEGIN
k <= '1' aftre 10 ns;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b01x00p02n01i01324 - The reserved word 'after' is misspelled in the after clause"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p02n01i01324arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1324.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p02n01i01324ent IS
END c08s04b01x00p02n01i01324ent;
ARCHITECTURE c08s04b01x00p02n01i01324arch OF c08s04b01x00p02n01i01324ent IS
signal k : BIT ;
BEGIN
TESTING: PROCESS
BEGIN
k <= '1' aftre 10 ns;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b01x00p02n01i01324 - The reserved word 'after' is misspelled in the after clause"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p02n01i01324arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1324.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p02n01i01324ent IS
END c08s04b01x00p02n01i01324ent;
ARCHITECTURE c08s04b01x00p02n01i01324arch OF c08s04b01x00p02n01i01324ent IS
signal k : BIT ;
BEGIN
TESTING: PROCESS
BEGIN
k <= '1' aftre 10 ns;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b01x00p02n01i01324 - The reserved word 'after' is misspelled in the after clause"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p02n01i01324arch;
|
----------------------------------------------------------------------------------
-- Organizacao e Arquitetura de Computadores
-- Professor: Marcelo Grandi Mandelli
-- Responsaveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimaraes
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY Uniciclo_tb IS
generic (
DATA_WIDTH : natural := 32; --32 bits para dados
ADDRESS_WIDTH : natural := 5 --5 bits para endereco
);
END Uniciclo_tb;
ARCHITECTURE Uniciclo_arch OF Uniciclo_tb IS
--declaracao de sinais
SIGNAL clk : std_logic := '1';
SIGNAL SW : std_logic_vector(13 downto 0);
SIGNAL HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7: std_logic_vector(6 downto 0);
COMPONENT Uniciclo --componente que sera testado
port (
clk : in std_logic := '1';
SW : in std_logic_vector(13 downto 0);
HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7: out std_logic_vector(6 downto 0)
);
END COMPONENT;
BEGIN
i1 : Uniciclo
PORT MAP (
clk => clk,
SW => SW,
HEX0 =>HEX0,
HEX1 =>HEX1,
HEX2 =>HEX2,
HEX3 =>HEX3,
HEX4 =>HEX4,
HEX5 =>HEX5,
HEX6 =>HEX6,
HEX7 =>HEX7
);
Clk_process : PROCESS --geracao do clock
variable auxMod : integer;
BEGIN
for op in 0 to 16383 loop
SW <= std_logic_vector(to_signed(op, SW'length));
for i in 0 to 255 loop
clk <= not(clk);
wait for 5 ps;
end loop;
end loop;
END PROCESS Clk_process;
END Uniciclo_arch; --fim do testbench |
----------------------------------------------------------------------------------
-- Organizacao e Arquitetura de Computadores
-- Professor: Marcelo Grandi Mandelli
-- Responsaveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimaraes
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY Uniciclo_tb IS
generic (
DATA_WIDTH : natural := 32; --32 bits para dados
ADDRESS_WIDTH : natural := 5 --5 bits para endereco
);
END Uniciclo_tb;
ARCHITECTURE Uniciclo_arch OF Uniciclo_tb IS
--declaracao de sinais
SIGNAL clk : std_logic := '1';
SIGNAL SW : std_logic_vector(13 downto 0);
SIGNAL HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7: std_logic_vector(6 downto 0);
COMPONENT Uniciclo --componente que sera testado
port (
clk : in std_logic := '1';
SW : in std_logic_vector(13 downto 0);
HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7: out std_logic_vector(6 downto 0)
);
END COMPONENT;
BEGIN
i1 : Uniciclo
PORT MAP (
clk => clk,
SW => SW,
HEX0 =>HEX0,
HEX1 =>HEX1,
HEX2 =>HEX2,
HEX3 =>HEX3,
HEX4 =>HEX4,
HEX5 =>HEX5,
HEX6 =>HEX6,
HEX7 =>HEX7
);
Clk_process : PROCESS --geracao do clock
variable auxMod : integer;
BEGIN
for op in 0 to 16383 loop
SW <= std_logic_vector(to_signed(op, SW'length));
for i in 0 to 255 loop
clk <= not(clk);
wait for 5 ps;
end loop;
end loop;
END PROCESS Clk_process;
END Uniciclo_arch; --fim do testbench |
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