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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc203.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p07n01i00203ent IS
END c03s01b00x00p07n01i00203ent;
ARCHITECTURE c03s01b00x00p07n01i00203arch OF c03s01b00x00p07n01i00203ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
loop1:
for J in 1 downto 30 loop
k := k + J;
end loop LOOP1;
assert NOT( k=0 )
report "***PASSED TEST: c03s01b00x00p07n01i00203"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c03s01b00x00p07n01i00203 - It is valid to have a null range."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p07n01i00203arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc203.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p07n01i00203ent IS
END c03s01b00x00p07n01i00203ent;
ARCHITECTURE c03s01b00x00p07n01i00203arch OF c03s01b00x00p07n01i00203ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
loop1:
for J in 1 downto 30 loop
k := k + J;
end loop LOOP1;
assert NOT( k=0 )
report "***PASSED TEST: c03s01b00x00p07n01i00203"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c03s01b00x00p07n01i00203 - It is valid to have a null range."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p07n01i00203arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc203.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p07n01i00203ent IS
END c03s01b00x00p07n01i00203ent;
ARCHITECTURE c03s01b00x00p07n01i00203arch OF c03s01b00x00p07n01i00203ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
loop1:
for J in 1 downto 30 loop
k := k + J;
end loop LOOP1;
assert NOT( k=0 )
report "***PASSED TEST: c03s01b00x00p07n01i00203"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c03s01b00x00p07n01i00203 - It is valid to have a null range."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p07n01i00203arch;
|
--------------------------------------------------------------------------------
-- Memory stage
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity memory is
port(
-- inputs
rst : in std_logic;
controls_in : in std_logic_vector(10 downto 0);
PC1_in : in std_logic_vector(31 downto 0);
PC2_in : in std_logic_vector(31 downto 0);
takeBranch : in std_logic;
addrMem : in std_logic_vector(31 downto 0);
writeData : in std_logic_vector(31 downto 0);
RFaddr_in : in std_logic_vector(4 downto 0);
-- outputs
controls_out : out std_logic_vector(2 downto 0);
dataOut_mem : out std_logic_vector(31 downto 0); -- data that has been read directly from memory
dataOut_exe : out std_logic_vector(31 downto 0); -- data that has been produced in exe stage
RFaddr_out : out std_logic_vector(4 downto 0);
unaligned : out std_logic;
PCsrc : out std_logic;
flush : out std_logic;
jump : out std_logic;
PC1_out : out std_logic_vector(31 downto 0);
PC2_out : out std_logic_vector(31 downto 0);
regwrite_MEM : out std_logic; -- goes to forwarding unit
RFaddr_MEM : out std_logic_vector(4 downto 0); -- goes to forwarding unit
forw_addr_MEM : out std_logic_vector(31 downto 0) -- goes to EXE stage and is used if forwarding detected by forwarding unit
);
end memory;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture struct of memory is
-- component declarations
component dram_block is
port(
-- inputs
address : in std_logic_vector(31 downto 0);
data_write : in std_logic_vector(31 downto 0);
mem_op : in std_logic_vector(5 downto 0);
rst : in std_logic;
-- outputs
unaligned : out std_logic;
data_read : out std_logic_vector(31 downto 0)
);
end component;
-- internal signals
signal PCsrc_i : std_logic;
signal jump_i : std_logic;
begin
-- concurrent signal assignments
jump_i <= controls_in(1); -- MV
PCsrc_i <= controls_in(0) and takeBranch; -- MV Branch and takeBranch
PCsrc <= PCsrc_i;
jump <= jump_i;
flush <= PCsrc_i or jump_i;
regwrite_MEM <= controls_in(10); -- to forwarding unit
RFaddr_MEM <= RFaddr_in; -- to forwarding unit
forw_addr_MEM <= addrMem; -- to forwarding unit
controls_out <= controls_in(10) & controls_in (9) & controls_in(2); -- pass regwrite, link, memtoreg to WB stage
dataOut_exe <= addrMem;
RFaddr_out <= RFaddr_in;
PC1_out <= PC1_in;
PC2_out <= PC2_in;
-- component instantiations
dram : dram_block port map (addrMem, writeData, controls_in(8 downto 3),rst, unaligned, dataOut_mem);
end struct;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_convertidor_piso_actual IS
END tb_convertidor_piso_actual;
ARCHITECTURE behavior OF tb_convertidor_piso_actual IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT convertidor_piso_actual
PORT(
clk : IN std_logic;
rst : IN std_logic;
piso_actual : IN std_logic_vector(2 downto 0);
boton_seleccionado : IN std_logic_vector(2 downto 0);
piso_actual_convertido : OUT std_logic_vector(1 downto 0);
boton_seleccionado_convertido : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal piso_actual : std_logic_vector(2 downto 0) := (others => '0');
signal boton_seleccionado : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal piso_actual_convertido : std_logic_vector(1 downto 0);
signal boton_seleccionado_convertido : std_logic_vector(1 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: convertidor_piso_actual PORT MAP (
clk => clk,
rst => rst,
piso_actual => piso_actual,
boton_seleccionado => boton_seleccionado,
piso_actual_convertido => piso_actual_convertido,
boton_seleccionado_convertido => boton_seleccionado_convertido
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '0';
boton_seleccionado <= "000";
piso_actual <= "100";
WAIT FOR 40 ns;
boton_seleccionado <= "100";
piso_actual <= "100";
WAIT FOR 10 ns;
RST <= '1';
WAIT FOR 10 ns;
RST <= '0';
WAIT FOR 45 ns;
boton_seleccionado <= "010";
piso_actual <= "010";
WAIT FOR 2 ns;
boton_seleccionado <= "101";
piso_actual <= "011";
WAIT FOR 50 ns;
boton_seleccionado <= "100";
piso_actual <= "100";
WAIT FOR 4 ns;
boton_seleccionado <= "110";
piso_actual <= "010";
WAIT FOR 2 ns;
boton_seleccionado <= "101";
piso_actual <= "101";
WAIT FOR 3 ns;
boton_seleccionado <= "010";
piso_actual <= "100";
WAIT FOR 20 ns;
boton_seleccionado <= "110";
piso_actual <= "010";
WAIT FOR 80 ns;
ASSERT false
REPORT "Simulación finalizada. Test superado."
SEVERITY FAILURE;
end process;
END; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity FractionLeftPadding is
port (
frcIn : in std_logic_vector(23 downto 0);
nlz : out std_logic_vector( 4 downto 0);
frcOut : out std_logic_vector(23 downto 0));
end FractionLeftPadding;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity FractionRightShifter is
port (
frcIn : in std_logic_vector(23 downto 0);
len : in std_logic_vector( 4 downto 0);
frcOut : out std_logic_vector(23 downto 0);
fstOverOut : out std_logic;
sndOverout : out std_logic;
tailAnyout : out std_logic);
end FractionRightShifter;
architecture PaddingL24 of FractionLeftPadding is
type ufrc_step_vector is array (3 downto 0) of unsigned(23 downto 0);
signal uFrc : ufrc_step_vector;
signal uFrcIn : unsigned(23 downto 0);
signal uFrcOut : unsigned(23 downto 0);
begin
uFrcIn <= unsigned(frcIn);
nlz(4) <= '1' when uFrcIn (23 downto 8) = 0 else '0';
uFrc(3) <= uFrcIn sll 16 when uFrcIn (23 downto 8) = 0 else uFrcIn;
nlz(3) <= '1' when uFrc(3)(23 downto 12) = 0 else '0';
uFrc(2) <= uFrc(3) sll 8 when uFrc(3)(23 downto 12) = 0 else uFrc(3);
nlz(2) <= '1' when uFrc(2)(23 downto 20) = 0 else '0';
uFrc(1) <= uFrc(2) sll 4 when uFrc(2)(23 downto 20) = 0 else uFrc(2);
nlz(1) <= '1' when uFrc(1)(23 downto 22) = 0 else '0';
uFrc(0) <= uFrc(1) sll 2 when uFrc(1)(23 downto 22) = 0 else uFrc(1);
nlz(0) <= '1' when uFrc(0)(23 downto 23) = 0 else '0';
uFrcOut <= uFrc(0) sll 1 when uFrc(0)(23 downto 23) = 0 else uFrc(0);
frcOut <= std_logic_vector(uFrcOut);
end PaddingL24;
architecture BarrelShifterR24Mod of FractionRightShifter is
type ufrc_step_vector is array (3 downto 0) of unsigned(25 downto 0);
signal uFrc: ufrc_step_vector;
signal uFrcIn: unsigned(25 downto 0);
signal uFrcOut: unsigned(25 downto 0);
signal tailAny: std_logic_vector (3 downto 0);
begin
uFrcIn <= unsigned(frcIn) & "00";
tailAny(3) <= '1' when len(4) = '1' and uFrcIn(15 downto 0) /= 0 else '0';
uFrc(3) <= uFrcIn srl 16 when len(4) = '1' else uFrcIn;
tailAny(2) <= '1' when len(3) = '1' and uFrc(3)(7 downto 0) /= 0 else tailAny(3);
uFrc(2) <= uFrc(3) srl 8 when len(3) = '1' else uFrc(3);
tailAny(1) <= '1' when len(2) = '1' and uFrc(2)(3 downto 0) /= 0 else tailAny(2);
uFrc(1) <= uFrc(2) srl 4 when len(2) = '1' else uFrc(2);
tailAny(0) <= '1' when len(1) = '1' and uFrc(1)(1 downto 0) /= 0 else tailAny(1);
uFrc(0) <= uFrc(1) srl 2 when len(1) = '1' else uFrc(1);
tailAnyOut <= '1' when len(0) = '1' and uFrc(0)(0 downto 0) /= 0 else tailAny(0);
uFrcOut <= uFrc(0) srl 1 when len(0) = '1' else uFrc(0);
sndOverOut <= uFrcOut(0);
fstOverOut <= uFrcOut(1);
frcOut <= std_logic_vector(uFrcOut(25 downto 2));
end BarrelShifterR24Mod;
|
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
|
entity loop1 is
end;
architecture behav of loop1 is
begin
process
variable i : natural := 0;
begin
report "hello";
while i < 10 loop
wait for 1 ns;
report "hello2";
i := i + 1;
end loop;
report "SUCCESS";
wait;
end process;
end behav;
|
entity loop1 is
end;
architecture behav of loop1 is
begin
process
variable i : natural := 0;
begin
report "hello";
while i < 10 loop
wait for 1 ns;
report "hello2";
i := i + 1;
end loop;
report "SUCCESS";
wait;
end process;
end behav;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2070.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02070ent IS
END c07s02b04x00p01n02i02070ent;
ARCHITECTURE c07s02b04x00p01n02i02070arch OF c07s02b04x00p01n02i02070ent IS
BEGIN
TESTING: PROCESS
-- All different type declarations.
-- integer types.
type POSITIVE is range 0 to INTEGER'HIGH;
-- Local declarations.
variable POSV : POSITIVE := 0;
variable REALV : REAL := 0.0;
BEGIN
POSV := POSV + REALV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02070 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02070arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2070.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02070ent IS
END c07s02b04x00p01n02i02070ent;
ARCHITECTURE c07s02b04x00p01n02i02070arch OF c07s02b04x00p01n02i02070ent IS
BEGIN
TESTING: PROCESS
-- All different type declarations.
-- integer types.
type POSITIVE is range 0 to INTEGER'HIGH;
-- Local declarations.
variable POSV : POSITIVE := 0;
variable REALV : REAL := 0.0;
BEGIN
POSV := POSV + REALV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02070 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02070arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2070.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02070ent IS
END c07s02b04x00p01n02i02070ent;
ARCHITECTURE c07s02b04x00p01n02i02070arch OF c07s02b04x00p01n02i02070ent IS
BEGIN
TESTING: PROCESS
-- All different type declarations.
-- integer types.
type POSITIVE is range 0 to INTEGER'HIGH;
-- Local declarations.
variable POSV : POSITIVE := 0;
variable REALV : REAL := 0.0;
BEGIN
POSV := POSV + REALV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02070 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02070arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: raphael-frey:user:axis_multiplexer:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_MUX4_0 IS
PORT (
ClkxCI : IN STD_LOGIC;
RstxRBI : IN STD_LOGIC;
SelectxDI : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Data0xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data1xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data2xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Valid0xSI : IN STD_LOGIC;
Valid1xSI : IN STD_LOGIC;
Valid2xSI : IN STD_LOGIC;
Ready0xSO : OUT STD_LOGIC;
Ready1xSO : OUT STD_LOGIC;
Ready2xSO : OUT STD_LOGIC;
DataxDO : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
ValidxSO : OUT STD_LOGIC;
ReadyxSI : IN STD_LOGIC
);
END design_1_MUX4_0;
ARCHITECTURE design_1_MUX4_0_arch OF design_1_MUX4_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_MUX4_0_arch: ARCHITECTURE IS "yes";
COMPONENT multiplexer IS
GENERIC (
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_NUM_SI_SLOTS : INTEGER
);
PORT (
ClkxCI : IN STD_LOGIC;
RstxRBI : IN STD_LOGIC;
SelectxDI : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Data0xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data1xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data2xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data3xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Valid0xSI : IN STD_LOGIC;
Valid1xSI : IN STD_LOGIC;
Valid2xSI : IN STD_LOGIC;
Valid3xSI : IN STD_LOGIC;
Ready0xSO : OUT STD_LOGIC;
Ready1xSO : OUT STD_LOGIC;
Ready2xSO : OUT STD_LOGIC;
Ready3xSO : OUT STD_LOGIC;
DataxDO : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
ValidxSO : OUT STD_LOGIC;
ReadyxSI : IN STD_LOGIC
);
END COMPONENT multiplexer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ClkxCI: SIGNAL IS "xilinx.com:signal:clock:1.0 SI_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF RstxRBI: SIGNAL IS "xilinx.com:signal:reset:1.0 SI_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF Data0xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Data1xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Data2xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI2 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Valid0xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Valid1xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Valid2xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI2 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Ready0xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF Ready1xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF Ready2xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI2 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DataxDO: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TDATA";
ATTRIBUTE X_INTERFACE_INFO OF ValidxSO: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TVALID";
ATTRIBUTE X_INTERFACE_INFO OF ReadyxSI: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TREADY";
BEGIN
U0 : multiplexer
GENERIC MAP (
C_AXIS_TDATA_WIDTH => 24,
C_AXIS_NUM_SI_SLOTS => 3
)
PORT MAP (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
SelectxDI => SelectxDI,
Data0xDI => Data0xDI,
Data1xDI => Data1xDI,
Data2xDI => Data2xDI,
Data3xDI => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
Valid0xSI => Valid0xSI,
Valid1xSI => Valid1xSI,
Valid2xSI => Valid2xSI,
Valid3xSI => '0',
Ready0xSO => Ready0xSO,
Ready1xSO => Ready1xSO,
Ready2xSO => Ready2xSO,
DataxDO => DataxDO,
ValidxSO => ValidxSO,
ReadyxSI => ReadyxSI
);
END design_1_MUX4_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: raphael-frey:user:axis_multiplexer:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_MUX4_0 IS
PORT (
ClkxCI : IN STD_LOGIC;
RstxRBI : IN STD_LOGIC;
SelectxDI : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Data0xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data1xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data2xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Valid0xSI : IN STD_LOGIC;
Valid1xSI : IN STD_LOGIC;
Valid2xSI : IN STD_LOGIC;
Ready0xSO : OUT STD_LOGIC;
Ready1xSO : OUT STD_LOGIC;
Ready2xSO : OUT STD_LOGIC;
DataxDO : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
ValidxSO : OUT STD_LOGIC;
ReadyxSI : IN STD_LOGIC
);
END design_1_MUX4_0;
ARCHITECTURE design_1_MUX4_0_arch OF design_1_MUX4_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_MUX4_0_arch: ARCHITECTURE IS "yes";
COMPONENT multiplexer IS
GENERIC (
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_NUM_SI_SLOTS : INTEGER
);
PORT (
ClkxCI : IN STD_LOGIC;
RstxRBI : IN STD_LOGIC;
SelectxDI : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Data0xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data1xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data2xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data3xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Valid0xSI : IN STD_LOGIC;
Valid1xSI : IN STD_LOGIC;
Valid2xSI : IN STD_LOGIC;
Valid3xSI : IN STD_LOGIC;
Ready0xSO : OUT STD_LOGIC;
Ready1xSO : OUT STD_LOGIC;
Ready2xSO : OUT STD_LOGIC;
Ready3xSO : OUT STD_LOGIC;
DataxDO : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
ValidxSO : OUT STD_LOGIC;
ReadyxSI : IN STD_LOGIC
);
END COMPONENT multiplexer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ClkxCI: SIGNAL IS "xilinx.com:signal:clock:1.0 SI_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF RstxRBI: SIGNAL IS "xilinx.com:signal:reset:1.0 SI_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF Data0xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Data1xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Data2xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI2 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Valid0xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Valid1xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Valid2xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI2 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Ready0xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF Ready1xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF Ready2xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI2 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DataxDO: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TDATA";
ATTRIBUTE X_INTERFACE_INFO OF ValidxSO: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TVALID";
ATTRIBUTE X_INTERFACE_INFO OF ReadyxSI: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TREADY";
BEGIN
U0 : multiplexer
GENERIC MAP (
C_AXIS_TDATA_WIDTH => 24,
C_AXIS_NUM_SI_SLOTS => 3
)
PORT MAP (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
SelectxDI => SelectxDI,
Data0xDI => Data0xDI,
Data1xDI => Data1xDI,
Data2xDI => Data2xDI,
Data3xDI => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
Valid0xSI => Valid0xSI,
Valid1xSI => Valid1xSI,
Valid2xSI => Valid2xSI,
Valid3xSI => '0',
Ready0xSO => Ready0xSO,
Ready1xSO => Ready1xSO,
Ready2xSO => Ready2xSO,
DataxDO => DataxDO,
ValidxSO => ValidxSO,
ReadyxSI => ReadyxSI
);
END design_1_MUX4_0_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc660.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:56 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00660ent IS
END c03s04b01x00p01n01i00660ent;
ARCHITECTURE c03s04b01x00p01n01i00660arch OF c03s04b01x00p01n01i00660ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type natural_vector is array (natural range <>) of natural;
subtype natural_vector_range is natural_vector(hi_to_low_range);
constant C1 : natural_vector_range := (others => 3);
type natural_vector_range_file is file of natural_vector_range;
BEGIN
TESTING: PROCESS
file filein : natural_vector_range_file open write_mode is "iofile.03";
BEGIN
for i in 1 to 100 loop
write(filein,C1);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00660 - The output file will be verified by test s010110.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00660arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc660.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:56 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00660ent IS
END c03s04b01x00p01n01i00660ent;
ARCHITECTURE c03s04b01x00p01n01i00660arch OF c03s04b01x00p01n01i00660ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type natural_vector is array (natural range <>) of natural;
subtype natural_vector_range is natural_vector(hi_to_low_range);
constant C1 : natural_vector_range := (others => 3);
type natural_vector_range_file is file of natural_vector_range;
BEGIN
TESTING: PROCESS
file filein : natural_vector_range_file open write_mode is "iofile.03";
BEGIN
for i in 1 to 100 loop
write(filein,C1);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00660 - The output file will be verified by test s010110.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00660arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc660.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:56 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00660ent IS
END c03s04b01x00p01n01i00660ent;
ARCHITECTURE c03s04b01x00p01n01i00660arch OF c03s04b01x00p01n01i00660ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type natural_vector is array (natural range <>) of natural;
subtype natural_vector_range is natural_vector(hi_to_low_range);
constant C1 : natural_vector_range := (others => 3);
type natural_vector_range_file is file of natural_vector_range;
BEGIN
TESTING: PROCESS
file filein : natural_vector_range_file open write_mode is "iofile.03";
BEGIN
for i in 1 to 100 loop
write(filein,C1);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00660 - The output file will be verified by test s010110.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00660arch;
|
--------------------------------------------------------------------------------
-- mcu80_tb.vhdl -- Minimal test bench for mcu80 (light8080 CPU wrapper).
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
use std.textio.all;
-- Package with utility functions for handling SoC object code.
use work.mcu80_pkg.all;
-- Package that contains the program object code in VHDL constant format.
use work.obj_code_pkg.all;
-- Package with TB support stuff.
use work.light8080_tb_pkg.all;
entity mcu80_tb is
end entity mcu80_tb;
architecture behavior of mcu80_tb is
--------------------------------------------------------------------------------
-- Simulation parameters
-- T: simulated clock period
constant T : time := 100 ns;
-- MAX_SIM_LENGTH: maximum simulation time
constant MAX_SIM_LENGTH : time := T*70000; -- enough for most purposes
--------------------------------------------------------------------------------
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal done : std_logic := '0';
signal interrupts : std_logic_vector(3 downto 0);
signal iop1 : std_logic_vector(7 downto 0);
signal iop2 : std_logic_vector(7 downto 0);
signal txd : std_logic;
signal rxd : std_logic;
-- Log file...
file log_file: TEXT open write_mode is "hw_sim_log.txt";
-- ...and console echo file.
file con_file: TEXT open write_mode is "hw_sim_con.txt";
begin
-- Instantiate the Unit Under Test.
uut: entity work.mcu80
generic map (
OBJ_CODE => work.obj_code_pkg.object_code,
UART_HARDWIRED => false, -- UART baud rate NOT run-time programmable.
UART_IRQ_LINE => 3, -- UART uses IRQ3 line of irq controller.
SIMULATION => True
)
port map (
clk => clk,
reset => reset,
p1_i => iop1,
p2_o => iop2,
extint_i => "0000",
rxd_i => txd, -- Plain UART loopback.
txd_o => txd
);
-- clock: Run clock until test is done.
clock:
process(done, clk)
begin
if done = '0' then
clk <= not clk after T/2;
end if;
end process clock;
-- main_test: Drive test stimulus, basically let CPU run after reset.
main_test:
process
begin
-- Assert reset for at least one full clk period
reset <= '1';
wait until clk = '1';
wait for T/2;
reset <= '0';
-- Remember to 'cut away' the preceding 3 clk semiperiods from
-- the wait statement...
wait until done='1' for (MAX_SIM_LENGTH - T*1.5);
-- If we get here with done = '0', the test timed out.
assert (done = '1')
report "Test timed out."
severity failure;
if iop2 = X"55" then
report "Test PASSED."
severity note;
else
report "Test FAILED."
severity failure;
end if;
wait;
end process main_test;
-- Logging process: launch logger functions --------------------------------
log_execution:
process
begin
con_line_ix <= 1;
con_line_buf <= (others => ' ');
-- Log cpu activity until done='1'.
mon_cpu_trace(
clk, reset, done,
con_line_buf, con_line_ix,
con_file, log_file);
wait;
end process log_execution;
end;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY grlib;
USE grlib.sparc.all;
USE grlib.stdlib.all;
LIBRARY techmap;
USE techmap.gencomp.all;
LIBRARY gaisler;
USE gaisler.leon3.all;
USE gaisler.libiu.all;
USE gaisler.arith.all;
USE grlib.sparc_disas.all;
ENTITY iu3 IS
GENERIC (
nwin : integer RANGE 2 to 32 := 8;
isets : integer RANGE 1 to 4 := 2;
dsets : integer RANGE 1 to 4 := 2;
fpu : integer RANGE 0 to 15 := 0;
v8 : integer RANGE 0 to 63 := 2;
cp : integer RANGE 0 to 1 := 0;
mac : integer RANGE 0 to 1 := 0;
dsu : integer RANGE 0 to 1 := 1;
nwp : integer RANGE 0 to 4 := 2;
pclow : integer RANGE 0 to 2 := 2;
notag : integer RANGE 0 to 1 := 0;
index : integer RANGE 0 to 15 := 0;
lddel : integer RANGE 1 to 2 := 1;
irfwt : integer RANGE 0 to 1 := 1;
disas : integer RANGE 0 to 2 := 0;
tbuf : integer RANGE 0 to 64 := 2;
pwd : integer RANGE 0 to 2 := 0;
svt : integer RANGE 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer RANGE 0 to 15 := 0;
fabtech : integer RANGE 0 to NTECH := 2;
clk2x : integer := 0
);
PORT (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
sclk : in std_ulogic
);
END ENTITY;
ARCHITECTURE rtl OF iu3 IS
CONSTANT ISETMSB : integer := log2x ( 2 ) - 1;
CONSTANT DSETMSB : integer := log2x ( 2 ) - 1;
CONSTANT RFBITS : integer RANGE 6 to 10 := log2 ( 8 + 1 ) + 4;
CONSTANT NWINLOG2 : integer RANGE 1 to 5 := log2 ( 8 );
CONSTANT CWPOPT : boolean := ( 8 = ( 2 ** LOG2 ( 8 ) ) );
CONSTANT CWPMIN : std_logic_vector ( LOG2 ( 8 ) - 1 downto 0 ) := ( OTHERS => '0' );
CONSTANT CWPMAX : std_logic_vector ( LOG2 ( 8 ) - 1 downto 0 ) := conv_std_logic_vector ( 8 - 1 , LOG2 ( 8 ) );
CONSTANT FPEN : boolean := ( 0 /= 0 );
CONSTANT CPEN : boolean := ( 0 = 1 );
CONSTANT MULEN : boolean := ( 2 /= 0 );
CONSTANT MULTYPE : integer := ( 2 / 16 );
CONSTANT DIVEN : boolean := ( 2 /= 0 );
CONSTANT MACEN : boolean := ( 0 = 1 );
CONSTANT MACPIPE : boolean := ( 0 = 1 ) and ( 2 / 2 = 1 );
CONSTANT IMPL : integer := 15;
CONSTANT VER : integer := 3;
CONSTANT DBGUNIT : boolean := ( 1 = 1 );
CONSTANT TRACEBUF : boolean := ( 2 /= 0 );
CONSTANT TBUFBITS : integer := 10 + log2 ( 2 ) - 4;
CONSTANT PWRD1 : boolean := false;
CONSTANT PWRD2 : boolean := 0 /= 0;
CONSTANT RS1OPT : boolean := ( is_fpga ( 2 ) /= 0 );
SUBTYPE word IS std_logic_vector ( 31 downto 0 );
SUBTYPE pctype IS std_logic_vector ( 31 downto 2 );
SUBTYPE rfatype IS std_logic_vector ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
SUBTYPE cwptype IS std_logic_vector ( LOG2 ( 8 ) - 1 downto 0 );
TYPE icdtype IS ARRAY ( 0 to 2 - 1 ) OF word;
TYPE dcdtype IS ARRAY ( 0 to 2 - 1 ) OF word;
SUBTYPE cword IS std_logic_vector ( 32 - 1 downto 0 );
TYPE cdatatype IS ARRAY ( 0 to 3 ) OF cword;
TYPE cpartype IS ARRAY ( 0 to 3 ) OF std_logic_vector ( 3 downto 0 );
TYPE iregfile_in_type IS RECORD
raddr1 : std_logic_vector ( 9 downto 0 );
raddr2 : std_logic_vector ( 9 downto 0 );
waddr : std_logic_vector ( 9 downto 0 );
wdata : std_logic_vector ( 31 downto 0 );
ren1 : std_ulogic;
ren2 : std_ulogic;
wren : std_ulogic;
diag : std_logic_vector ( 3 downto 0 );
END RECORD;
TYPE iregfile_out_type IS RECORD
data1 : std_logic_vector ( RDBITS - 1 downto 0 );
data2 : std_logic_vector ( RDBITS - 1 downto 0 );
END RECORD;
TYPE cctrltype IS RECORD
burst : std_ulogic;
dfrz : std_ulogic;
ifrz : std_ulogic;
dsnoop : std_ulogic;
dcs : std_logic_vector ( 1 downto 0 );
ics : std_logic_vector ( 1 downto 0 );
END RECORD;
TYPE icache_in_type IS RECORD
rpc : std_logic_vector ( 31 downto 0 );
fpc : std_logic_vector ( 31 downto 0 );
dpc : std_logic_vector ( 31 downto 0 );
rbranch : std_ulogic;
fbranch : std_ulogic;
inull : std_ulogic;
su : std_ulogic;
flush : std_ulogic;
flushl : std_ulogic;
fline : std_logic_vector ( 31 downto 3 );
pnull : std_ulogic;
END RECORD;
TYPE icache_out_type IS RECORD
data : cdatatype;
set : std_logic_vector ( 1 downto 0 );
mexc : std_ulogic;
hold : std_ulogic;
flush : std_ulogic;
diagrdy : std_ulogic;
diagdata : std_logic_vector ( IDBITS - 1 downto 0 );
mds : std_ulogic;
cfg : std_logic_vector ( 31 downto 0 );
idle : std_ulogic;
END RECORD;
TYPE icdiag_in_type IS RECORD
addr : std_logic_vector ( 31 downto 0 );
enable : std_ulogic;
read : std_ulogic;
tag : std_ulogic;
ctx : std_ulogic;
flush : std_ulogic;
ilramen : std_ulogic;
cctrl : cctrltype;
pflush : std_ulogic;
pflushaddr : std_logic_vector ( VA_I_U downto VA_I_D );
pflushtyp : std_ulogic;
ilock : std_logic_vector ( 0 to 3 );
scanen : std_ulogic;
END RECORD;
TYPE dcache_in_type IS RECORD
asi : std_logic_vector ( 7 downto 0 );
maddress : std_logic_vector ( 31 downto 0 );
eaddress : std_logic_vector ( 31 downto 0 );
edata : std_logic_vector ( 31 downto 0 );
size : std_logic_vector ( 1 downto 0 );
enaddr : std_ulogic;
eenaddr : std_ulogic;
nullify : std_ulogic;
lock : std_ulogic;
read : std_ulogic;
write : std_ulogic;
flush : std_ulogic;
flushl : std_ulogic;
dsuen : std_ulogic;
msu : std_ulogic;
esu : std_ulogic;
intack : std_ulogic;
END RECORD;
TYPE dcache_out_type IS RECORD
data : cdatatype;
set : std_logic_vector ( 1 downto 0 );
mexc : std_ulogic;
hold : std_ulogic;
mds : std_ulogic;
werr : std_ulogic;
icdiag : icdiag_in_type;
cache : std_ulogic;
idle : std_ulogic;
scanen : std_ulogic;
testen : std_ulogic;
END RECORD;
TYPE tracebuf_in_type IS RECORD
addr : std_logic_vector ( 11 downto 0 );
data : std_logic_vector ( 127 downto 0 );
enable : std_logic;
write : std_logic_vector ( 3 downto 0 );
diag : std_logic_vector ( 3 downto 0 );
END RECORD;
TYPE tracebuf_out_type IS RECORD
data : std_logic_vector ( 127 downto 0 );
END RECORD;
TYPE l3_irq_in_type IS RECORD
irl : std_logic_vector ( 3 downto 0 );
rst : std_ulogic;
run : std_ulogic;
END RECORD;
TYPE l3_irq_out_type IS RECORD
intack : std_ulogic;
irl : std_logic_vector ( 3 downto 0 );
pwd : std_ulogic;
END RECORD;
TYPE l3_debug_in_type IS RECORD
dsuen : std_ulogic;
denable : std_ulogic;
dbreak : std_ulogic;
step : std_ulogic;
halt : std_ulogic;
reset : std_ulogic;
dwrite : std_ulogic;
daddr : std_logic_vector ( 23 downto 2 );
ddata : std_logic_vector ( 31 downto 0 );
btrapa : std_ulogic;
btrape : std_ulogic;
berror : std_ulogic;
bwatch : std_ulogic;
bsoft : std_ulogic;
tenable : std_ulogic;
timer : std_logic_vector ( 30 downto 0 );
END RECORD;
TYPE l3_debug_out_type IS RECORD
data : std_logic_vector ( 31 downto 0 );
crdy : std_ulogic;
dsu : std_ulogic;
dsumode : std_ulogic;
error : std_ulogic;
halt : std_ulogic;
pwd : std_ulogic;
idle : std_ulogic;
ipend : std_ulogic;
icnt : std_ulogic;
END RECORD;
TYPE l3_debug_in_vector IS ARRAY ( natural RANGE <> ) OF l3_debug_in_type;
TYPE l3_debug_out_vector IS ARRAY ( natural RANGE <> ) OF l3_debug_out_type;
TYPE div32_in_type IS RECORD
y : std_logic_vector ( 32 downto 0 );
op1 : std_logic_vector ( 32 downto 0 );
op2 : std_logic_vector ( 32 downto 0 );
flush : std_logic;
signed : std_logic;
start : std_logic;
END RECORD;
TYPE div32_out_type IS RECORD
ready : std_logic;
nready : std_logic;
icc : std_logic_vector ( 3 downto 0 );
result : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE mul32_in_type IS RECORD
op1 : std_logic_vector ( 32 downto 0 );
op2 : std_logic_vector ( 32 downto 0 );
flush : std_logic;
signed : std_logic;
start : std_logic;
mac : std_logic;
acc : std_logic_vector ( 39 downto 0 );
END RECORD;
TYPE mul32_out_type IS RECORD
ready : std_logic;
nready : std_logic;
icc : std_logic_vector ( 3 downto 0 );
result : std_logic_vector ( 63 downto 0 );
END RECORD;
TYPE fp_rf_in_type IS RECORD
rd1addr : std_logic_vector ( 3 downto 0 );
rd2addr : std_logic_vector ( 3 downto 0 );
wraddr : std_logic_vector ( 3 downto 0 );
wrdata : std_logic_vector ( 31 downto 0 );
ren1 : std_ulogic;
ren2 : std_ulogic;
wren : std_ulogic;
END RECORD;
TYPE fp_rf_out_type IS RECORD
data1 : std_logic_vector ( 31 downto 0 );
data2 : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE fpc_pipeline_control_type IS RECORD
pc : std_logic_vector ( 31 downto 0 );
inst : std_logic_vector ( 31 downto 0 );
cnt : std_logic_vector ( 1 downto 0 );
trap : std_ulogic;
annul : std_ulogic;
pv : std_ulogic;
END RECORD;
TYPE fpc_debug_in_type IS RECORD
enable : std_ulogic;
write : std_ulogic;
fsr : std_ulogic;
addr : std_logic_vector ( 4 downto 0 );
data : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE fpc_debug_out_type IS RECORD
data : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE fpc_in_type IS RECORD
flush : std_ulogic;
exack : std_ulogic;
a_rs1 : std_logic_vector ( 4 downto 0 );
d : fpc_pipeline_control_type;
a : fpc_pipeline_control_type;
e : fpc_pipeline_control_type;
m : fpc_pipeline_control_type;
x : fpc_pipeline_control_type;
lddata : std_logic_vector ( 31 downto 0 );
dbg : fpc_debug_in_type;
END RECORD;
TYPE fpc_out_type IS RECORD
data : std_logic_vector ( 31 downto 0 );
exc : std_logic;
cc : std_logic_vector ( 1 downto 0 );
ccv : std_ulogic;
ldlock : std_logic;
holdn : std_ulogic;
dbg : fpc_debug_out_type;
END RECORD;
TYPE grfpu_in_type IS RECORD
start : std_logic;
nonstd : std_logic;
flop : std_logic_vector ( 8 downto 0 );
op1 : std_logic_vector ( 63 downto 0 );
op2 : std_logic_vector ( 63 downto 0 );
opid : std_logic_vector ( 7 downto 0 );
flush : std_logic;
flushid : std_logic_vector ( 5 downto 0 );
rndmode : std_logic_vector ( 1 downto 0 );
req : std_logic;
END RECORD;
TYPE grfpu_out_type IS RECORD
res : std_logic_vector ( 63 downto 0 );
exc : std_logic_vector ( 5 downto 0 );
allow : std_logic_vector ( 2 downto 0 );
rdy : std_logic;
cc : std_logic_vector ( 1 downto 0 );
idout : std_logic_vector ( 7 downto 0 );
END RECORD;
TYPE grfpu_out_vector_type IS ARRAY ( integer RANGE 0 to 7 ) OF grfpu_out_type;
TYPE grfpu_in_vector_type IS ARRAY ( integer RANGE 0 to 7 ) OF grfpu_in_type;
TYPE dc_in_type IS RECORD
signed : std_ulogic;
enaddr : std_ulogic;
read : std_ulogic;
write : std_ulogic;
lock : std_ulogic;
dsuen : std_ulogic;
size : std_logic_vector ( 1 downto 0 );
asi : std_logic_vector ( 7 downto 0 );
END RECORD;
TYPE pipeline_ctrl_type IS RECORD
pc : pctype;
inst : word;
cnt : std_logic_vector ( 1 downto 0 );
rd : rfatype;
tt : std_logic_vector ( 5 downto 0 );
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
END RECORD;
TYPE fetch_reg_type IS RECORD
pc : pctype;
branch : std_ulogic;
END RECORD;
TYPE decode_reg_type IS RECORD
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector ( LOG2X ( 2 ) - 1 downto 0 );
mexc : std_ulogic;
cnt : std_logic_vector ( 1 downto 0 );
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
END RECORD;
TYPE regacc_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector ( 4 downto 0 );
rfa1 : rfatype;
rfa2 : rfatype;
rsel1 : std_logic_vector ( 2 downto 0 );
rsel2 : std_logic_vector ( 2 downto 0 );
rfe1 : std_ulogic;
rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
END RECORD;
TYPE execute_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector ( 2 downto 0 );
alusel : std_logic_vector ( 1 downto 0 );
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1 : std_ulogic;
ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector ( 4 downto 0 );
sari : std_ulogic;
shleft : std_ulogic;
ymsb : std_ulogic;
rd : std_logic_vector ( 4 downto 0 );
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector ( 3 downto 0 );
mulstep : std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
END RECORD;
TYPE memory_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector ( 3 downto 0 );
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
END RECORD;
TYPE exception_state IS ( run , trap , dsu1 , dsu2 );
TYPE exception_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector ( 3 downto 0 );
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector ( LOG2X ( 2 ) - 1 downto 0 );
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector ( 1 downto 0 );
rstate : exception_state;
npc : std_logic_vector ( 2 downto 0 );
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
END RECORD;
TYPE dsu_registers IS RECORD
tt : std_logic_vector ( 7 downto 0 );
err : std_ulogic;
tbufcnt : std_logic_vector ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
asi : std_logic_vector ( 7 downto 0 );
crdy : std_logic_vector ( 2 downto 1 );
END RECORD;
TYPE irestart_register IS RECORD
addr : pctype;
pwd : std_ulogic;
END RECORD;
TYPE pwd_register_type IS RECORD
pwd : std_ulogic;
error : std_ulogic;
END RECORD;
TYPE special_register_type IS RECORD
cwp : cwptype;
icc : std_logic_vector ( 3 downto 0 );
tt : std_logic_vector ( 7 downto 0 );
tba : std_logic_vector ( 19 downto 0 );
wim : std_logic_vector ( 8 - 1 downto 0 );
pil : std_logic_vector ( 3 downto 0 );
ec : std_ulogic;
ef : std_ulogic;
ps : std_ulogic;
s : std_ulogic;
et : std_ulogic;
y : word;
asr18 : word;
svt : std_ulogic;
dwt : std_ulogic;
END RECORD;
TYPE write_reg_type IS RECORD
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
END RECORD;
TYPE registers IS RECORD
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
END RECORD;
TYPE exception_type IS RECORD
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
END RECORD;
TYPE watchpoint_register IS RECORD
addr : std_logic_vector ( 31 downto 2 );
mask : std_logic_vector ( 31 downto 2 );
exec : std_ulogic;
load : std_ulogic;
store : std_ulogic;
END RECORD;
TYPE watchpoint_registers IS ARRAY ( 0 to 3 ) OF watchpoint_register;
CONSTANT wpr_none : watchpoint_register := ( zero32 ( 31 downto 2 ) , zero32 ( 31 downto 2 ) , '0' , '0' , '0' );
FUNCTION dbgexc (
r : registers;
dbgi : l3_debug_in_type;
trap : std_ulogic;
tt : std_logic_vector ( 7 downto 0 )
) RETURN std_ulogic IS
VARIABLE dmode : std_ulogic;
BEGIN
dmode := '0';
IF ( not r.x.ctrl.annul and trap ) = '1' THEN
IF ( ( ( tt = "00" & TT_WATCH ) and ( dbgi.bwatch = '1' ) ) or ( ( dbgi.bsoft = '1' ) and ( tt = "10000001" ) ) or ( dbgi.btrapa = '1' ) or ( ( dbgi.btrape = '1' ) and not ( ( tt ( 5 downto 0 ) = TT_PRIV ) or ( tt ( 5 downto 0 ) = TT_FPDIS ) or ( tt ( 5 downto 0 ) = TT_WINOF ) or ( tt ( 5 downto 0 ) = TT_WINUF ) or ( tt ( 5 downto 4 ) = "01" ) or ( tt ( 7 ) = '1' ) ) ) or ( ( ( not r.w.s.et ) and dbgi.berror ) = '1' ) ) THEN
dmode := '1';
END IF;
END IF;
RETURN ( dmode );
END;
FUNCTION dbgerr (
r : registers;
dbgi : l3_debug_in_type;
tt : std_logic_vector ( 7 downto 0 )
) RETURN std_ulogic IS
VARIABLE err : std_ulogic;
BEGIN
err := not r.w.s.et;
IF ( ( ( dbgi.dbreak = '1' ) and ( tt = ( "00" & TT_WATCH ) ) ) or ( ( dbgi.bsoft = '1' ) and ( tt = ( "10000001" ) ) ) ) THEN
err := '0';
END IF;
RETURN ( err );
END;
PROCEDURE diagwr (
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector ( 7 downto 0 );
pc : out pctype;
npc : out pctype;
tbufcnt : out std_logic_vector ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
wr : out std_ulogic;
addr : out std_logic_vector ( 9 downto 0 );
data : out word;
fpcwr : out std_ulogic
) IS
VARIABLE i : integer RANGE 0 to 3;
BEGIN
s := r.w.s;
pc := r.f.pc;
npc := ir.addr;
wr := '0';
vwpr := wpr;
asi := dsur.asi;
addr := ( OTHERS => '0' );
data := dbg.ddata;
tbufcnt := dsur.tbufcnt;
fpcwr := '0';
IF ( dbg.dsuen and dbg.denable and dbg.dwrite ) = '1' THEN
CASE dbg.daddr ( 23 downto 20 ) IS
WHEN "0001" =>
IF dbg.daddr ( 16 ) = '1' THEN
tbufcnt := dbg.ddata ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
END IF;
WHEN "0011" =>
IF dbg.daddr ( 12 ) = '0' THEN
wr := '1';
addr := ( OTHERS => '0' );
addr ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := dbg.daddr ( LOG2 ( 8 + 1 ) + 4 + 1 downto 2 );
ELSE
fpcwr := '1';
END IF;
WHEN "0100" =>
CASE dbg.daddr ( 7 downto 6 ) IS
WHEN "00" =>
CASE dbg.daddr ( 5 downto 2 ) IS
WHEN "0000" =>
s.y := dbg.ddata;
WHEN "0001" =>
s.cwp := dbg.ddata ( LOG2 ( 8 ) - 1 downto 0 );
s.icc := dbg.ddata ( 23 downto 20 );
s.ec := dbg.ddata ( 13 );
s.pil := dbg.ddata ( 11 downto 8 );
s.s := dbg.ddata ( 7 );
s.ps := dbg.ddata ( 6 );
s.et := dbg.ddata ( 5 );
WHEN "0010" =>
s.wim := dbg.ddata ( 8 - 1 downto 0 );
WHEN "0011" =>
s.tba := dbg.ddata ( 31 downto 12 );
s.tt := dbg.ddata ( 11 downto 4 );
WHEN "0100" =>
pc := dbg.ddata ( 31 downto 2 );
WHEN "0101" =>
npc := dbg.ddata ( 31 downto 2 );
WHEN "0110" =>
fpcwr := '1';
WHEN "0111" =>
NULL;
WHEN "1001" =>
asi := dbg.ddata ( 7 downto 0 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN "01" =>
CASE dbg.daddr ( 5 downto 2 ) IS
WHEN "0001" =>
s.dwt := dbg.ddata ( 14 );
s.svt := dbg.ddata ( 13 );
WHEN "0010" =>
NULL;
WHEN "1000" =>
vwpr ( 0 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 0 ).exec := dbg.ddata ( 0 );
WHEN "1001" =>
vwpr ( 0 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 0 ).load := dbg.ddata ( 1 );
vwpr ( 0 ).store := dbg.ddata ( 0 );
WHEN "1010" =>
vwpr ( 1 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 1 ).exec := dbg.ddata ( 0 );
WHEN "1011" =>
vwpr ( 1 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 1 ).load := dbg.ddata ( 1 );
vwpr ( 1 ).store := dbg.ddata ( 0 );
WHEN "1100" =>
vwpr ( 2 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 2 ).exec := dbg.ddata ( 0 );
WHEN "1101" =>
vwpr ( 2 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 2 ).load := dbg.ddata ( 1 );
vwpr ( 2 ).store := dbg.ddata ( 0 );
WHEN "1110" =>
vwpr ( 3 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 3 ).exec := dbg.ddata ( 0 );
WHEN "1111" =>
vwpr ( 3 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 3 ).load := dbg.ddata ( 1 );
vwpr ( 3 ).store := dbg.ddata ( 0 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END;
FUNCTION asr17_gen (
r : in registers
) RETURN word IS
VARIABLE asr17 : word;
VARIABLE fpu2 : integer RANGE 0 to 3;
BEGIN
asr17 := zero32;
asr17 ( 31 downto 28 ) := conv_std_logic_vector ( 0 , 4 );
asr17 ( 14 ) := r.w.s.dwt;
asr17 ( 13 ) := r.w.s.svt;
fpu2 := 0;
asr17 ( 11 downto 10 ) := conv_std_logic_vector ( fpu2 , 2 );
asr17 ( 8 ) := '1';
asr17 ( 7 downto 5 ) := conv_std_logic_vector ( 2 , 3 );
asr17 ( 4 downto 0 ) := conv_std_logic_vector ( 8 - 1 , 5 );
RETURN ( asr17 );
END;
PROCEDURE diagread (
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
rfdata : in std_logic_vector ( 31 downto 0 );
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word
) IS
VARIABLE cwp : std_logic_vector ( 4 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE i : integer RANGE 0 to 3;
BEGIN
data := ( OTHERS => '0' );
cwp := ( OTHERS => '0' );
cwp ( LOG2 ( 8 ) - 1 downto 0 ) := r.w.s.cwp;
CASE dbgi.daddr ( 22 downto 20 ) IS
WHEN "001" =>
IF dbgi.daddr ( 16 ) = '1' THEN
data ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 ) := dsur.tbufcnt;
ELSE
CASE dbgi.daddr ( 3 downto 2 ) IS
WHEN "00" =>
data := tbufo.data ( 127 downto 96 );
WHEN "01" =>
data := tbufo.data ( 95 downto 64 );
WHEN "10" =>
data := tbufo.data ( 63 downto 32 );
WHEN OTHERS =>
data := tbufo.data ( 31 downto 0 );
END CASE;
END IF;
WHEN "011" =>
IF dbgi.daddr ( 12 ) = '0' THEN
data := rfdata ( 31 downto 0 );
ELSE
data := fpo.dbg.data;
END IF;
WHEN "100" =>
CASE dbgi.daddr ( 7 downto 6 ) IS
WHEN "00" =>
CASE dbgi.daddr ( 5 downto 2 ) IS
WHEN "0000" =>
data := r.w.s.y;
WHEN "0001" =>
data := conv_std_logic_vector ( 15 , 4 ) & conv_std_logic_vector ( 3 , 4 ) & r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil & r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
WHEN "0010" =>
data ( 8 - 1 downto 0 ) := r.w.s.wim;
WHEN "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
WHEN "0100" =>
data ( 31 downto 2 ) := r.f.pc;
WHEN "0101" =>
data ( 31 downto 2 ) := ir.addr;
WHEN "0110" =>
data := fpo.dbg.data;
WHEN "0111" =>
NULL;
WHEN "1000" =>
data ( 12 downto 4 ) := dsur.err & dsur.tt;
WHEN "1001" =>
data ( 7 downto 0 ) := dsur.asi;
WHEN OTHERS =>
NULL;
END CASE;
WHEN "01" =>
IF dbgi.daddr ( 5 ) = '0' THEN
IF dbgi.daddr ( 4 downto 2 ) = "001" THEN
data := asr17_gen ( r );
END IF;
ELSE
i := conv_integer ( dbgi.daddr ( 4 downto 3 ) );
IF dbgi.daddr ( 2 ) = '0' THEN
data ( 31 downto 2 ) := wpr ( i ).addr;
data ( 0 ) := wpr ( i ).exec;
ELSE
data ( 31 downto 2 ) := wpr ( i ).mask;
data ( 1 ) := wpr ( i ).load;
data ( 0 ) := wpr ( i ).store;
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN "111" =>
data := r.x.data ( conv_integer ( r.x.set ) );
WHEN OTHERS =>
NULL;
END CASE;
END;
PROCEDURE itrace (
r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
di : out tracebuf_in_type
) IS
VARIABLE meminst : std_ulogic;
BEGIN
di.addr := ( OTHERS => '0' );
di.data := ( OTHERS => '0' );
di.enable := '0';
di.write := ( OTHERS => '0' );
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst ( 31 ) and r.x.ctrl.inst ( 30 );
di.addr ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 ) := dsur.tbufcnt;
di.data ( 127 ) := '0';
di.data ( 126 ) := not r.x.ctrl.pv;
di.data ( 125 downto 96 ) := dbgi.timer ( 29 downto 0 );
di.data ( 95 downto 64 ) := res;
di.data ( 63 downto 34 ) := r.x.ctrl.pc ( 31 downto 2 );
di.data ( 33 ) := trap;
di.data ( 32 ) := error;
di.data ( 31 downto 0 ) := r.x.ctrl.inst;
IF ( dbgi.tenable = '0' ) or ( r.x.rstate = dsu2 ) THEN
IF ( ( dbgi.dsuen and dbgi.denable ) = '1' ) and ( dbgi.daddr ( 23 downto 20 ) & dbgi.daddr ( 16 ) = "00010" ) THEN
di.enable := '1';
di.addr ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 ) := dbgi.daddr ( 10 + LOG2 ( 2 ) - 4 - 1 + 4 downto 4 );
IF dbgi.dwrite = '1' THEN
CASE dbgi.daddr ( 3 downto 2 ) IS
WHEN "00" =>
di.write ( 3 ) := '1';
WHEN "01" =>
di.write ( 2 ) := '1';
WHEN "10" =>
di.write ( 1 ) := '1';
WHEN OTHERS =>
di.write ( 0 ) := '1';
END CASE;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
END IF;
END IF;
ELSIF ( not r.x.ctrl.annul and ( r.x.ctrl.pv or meminst ) and not r.x.debug ) = '1' THEN
di.enable := '1';
di.write := ( OTHERS => '1' );
tbufcnt := dsur.tbufcnt + 1;
END IF;
di.diag := dco.testen & "000";
IF dco.scanen = '1' THEN
di.enable := '0';
END IF;
END;
PROCEDURE dbg_cache (
holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) IS
BEGIN
mresult2 := mresult;
dci2 := dci;
dci2.dsuen := '0';
IF r.x.rstate = dsu2 THEN
dci2.asi := dsur.asi;
IF ( dbgi.daddr ( 22 downto 20 ) = "111" ) and ( dbgi.dsuen = '1' ) THEN
dci2.dsuen := ( dbgi.denable or r.m.dci.dsuen ) and not dsur.crdy ( 2 );
dci2.enaddr := dbgi.denable;
dci2.size := "10";
dci2.read := '1';
dci2.write := '0';
IF ( dbgi.denable and not r.m.dci.enaddr ) = '1' THEN
mresult2 := ( OTHERS => '0' );
mresult2 ( 19 downto 2 ) := dbgi.daddr ( 19 downto 2 );
ELSE
mresult2 := dbgi.ddata;
END IF;
IF dbgi.dwrite = '1' THEN
dci2.read := '0';
dci2.write := '1';
END IF;
END IF;
END IF;
END;
PROCEDURE fpexack (
r : in registers;
fpexc : out std_ulogic
) IS
BEGIN
fpexc := '0';
END;
PROCEDURE diagrdy (
denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector ( 2 downto 1 )
) IS
BEGIN
crdy := dsur.crdy ( 1 ) & '0';
IF dci.dsuen = '1' THEN
CASE dsur.asi ( 4 downto 0 ) IS
WHEN ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy ( 2 ) := ico.diagrdy and not dsur.crdy ( 2 );
WHEN ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy ( 1 ) := not denable and dci.enaddr and not dsur.crdy ( 1 );
WHEN OTHERS =>
crdy ( 2 ) := dci.enaddr and denable;
END CASE;
END IF;
END;
SIGNAL r : registers;
SIGNAL rin : registers;
SIGNAL wpr : watchpoint_registers;
SIGNAL wprin : watchpoint_registers;
SIGNAL dsur : dsu_registers;
SIGNAL dsuin : dsu_registers;
SIGNAL ir : irestart_register;
SIGNAL irin : irestart_register;
SIGNAL rp : pwd_register_type;
SIGNAL rpin : pwd_register_type;
SIGNAL hackState : std_logic_vector ( 1 downto 0 );
CONSTANT EXE_AND : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_XOR : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_OR : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_XNOR : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT EXE_ANDN : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_ORN : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT EXE_DIV : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT EXE_PASS1 : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_PASS2 : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_STB : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_STH : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT EXE_ONES : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_RDY : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT EXE_SPR : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT EXE_LINK : std_logic_vector ( 2 downto 0 ) := "111";
CONSTANT EXE_SLL : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_SRL : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_SRA : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_NOP : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_RES_ADD : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT EXE_RES_SHIFT : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT EXE_RES_LOGIC : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT EXE_RES_MISC : std_logic_vector ( 1 downto 0 ) := "11";
CONSTANT SZBYTE : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT SZHALF : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT SZWORD : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT SZDBL : std_logic_vector ( 1 downto 0 ) := "11";
PROCEDURE regaddr (
cwp : std_logic_vector;
reg : std_logic_vector ( 4 downto 0 );
rao : out rfatype
) IS
VARIABLE ra : rfatype;
CONSTANT globals : std_logic_vector ( LOG2 ( 8 + 1 ) + 4 - 5 downto 0 ) := conv_std_logic_vector ( 8 , LOG2 ( 8 + 1 ) + 4 - 4 );
BEGIN
ra := ( OTHERS => '0' );
ra ( 4 downto 0 ) := reg;
IF reg ( 4 downto 3 ) = "00" THEN
ra ( LOG2 ( 8 + 1 ) + 4 - 1 downto 4 ) := CONV_STD_LOGIC_VECTOR ( 8 , LOG2 ( 8 + 1 ) + 4 - 4 );
ELSE
ra ( LOG2 ( 8 ) + 3 downto 4 ) := cwp + ra ( 4 );
END IF;
rao := ra;
END;
FUNCTION branch_address (
inst : word;
pc : pctype
) RETURN std_logic_vector IS
VARIABLE baddr : pctype;
VARIABLE caddr : pctype;
VARIABLE tmp : pctype;
BEGIN
caddr := ( OTHERS => '0' );
caddr ( 31 downto 2 ) := inst ( 29 downto 0 );
caddr ( 31 downto 2 ) := caddr ( 31 downto 2 ) + pc ( 31 downto 2 );
baddr := ( OTHERS => '0' );
baddr ( 31 downto 24 ) := ( OTHERS => inst ( 21 ) );
baddr ( 23 downto 2 ) := inst ( 21 downto 0 );
baddr ( 31 downto 2 ) := baddr ( 31 downto 2 ) + pc ( 31 downto 2 );
IF inst ( 30 ) = '1' THEN
tmp := caddr;
ELSE
tmp := baddr;
END IF;
RETURN ( tmp );
END;
FUNCTION branch_true (
icc : std_logic_vector ( 3 downto 0 );
inst : word
) RETURN std_ulogic IS
VARIABLE n : std_ulogic;
VARIABLE z : std_ulogic;
VARIABLE v : std_ulogic;
VARIABLE c : std_ulogic;
VARIABLE branch : std_ulogic;
BEGIN
n := icc ( 3 );
z := icc ( 2 );
v := icc ( 1 );
c := icc ( 0 );
CASE inst ( 27 downto 25 ) IS
WHEN "000" =>
branch := inst ( 28 ) xor '0';
WHEN "001" =>
branch := inst ( 28 ) xor z;
WHEN "010" =>
branch := inst ( 28 ) xor ( z or ( n xor v ) );
WHEN "011" =>
branch := inst ( 28 ) xor ( n xor v );
WHEN "100" =>
branch := inst ( 28 ) xor ( c or z );
WHEN "101" =>
branch := inst ( 28 ) xor c;
WHEN "110" =>
branch := inst ( 28 ) xor n;
WHEN OTHERS =>
branch := inst ( 28 ) xor v;
END CASE;
RETURN ( branch );
END;
PROCEDURE su_et_select (
r : in registers;
xc_ps : in std_ulogic;
xc_s : in std_ulogic;
xc_et : in std_ulogic;
su : out std_ulogic;
et : out std_ulogic
) IS
BEGIN
IF ( ( r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett ) = '1' ) and ( r.x.annul_all = '0' ) THEN
su := xc_ps;
et := '1';
ELSE
su := xc_s;
et := xc_et;
END IF;
END;
FUNCTION wphit (
r : registers;
wpr : watchpoint_registers;
debug : l3_debug_in_type
) RETURN std_ulogic IS
VARIABLE exc : std_ulogic;
BEGIN
exc := '0';
IF ( ( wpr ( 0 ).exec and r.a.ctrl.pv and not r.a.ctrl.annul ) = '1' ) THEN
IF ( ( ( wpr ( 0 ).addr xor r.a.ctrl.pc ( 31 downto 2 ) ) and wpr ( 0 ).mask ) = Zero32 ( 31 downto 2 ) ) THEN
exc := '1';
END IF;
END IF;
IF ( ( wpr ( 1 ).exec and r.a.ctrl.pv and not r.a.ctrl.annul ) = '1' ) THEN
IF ( ( ( wpr ( 1 ).addr xor r.a.ctrl.pc ( 31 downto 2 ) ) and wpr ( 1 ).mask ) = Zero32 ( 31 downto 2 ) ) THEN
exc := '1';
END IF;
END IF;
IF ( debug.dsuen and not r.a.ctrl.annul ) = '1' THEN
exc := exc or ( r.a.ctrl.pv and ( ( debug.dbreak and debug.bwatch ) or r.a.step ) );
END IF;
RETURN ( exc );
END;
FUNCTION shift3 (
r : registers;
aluin1 : word;
aluin2 : word
) RETURN word IS
VARIABLE shiftin : unsigned ( 63 downto 0 );
VARIABLE shiftout : unsigned ( 63 downto 0 );
VARIABLE cnt : natural RANGE 0 to 31;
BEGIN
cnt := conv_integer ( r.e.shcnt );
IF r.e.shleft = '1' THEN
shiftin ( 30 downto 0 ) := ( OTHERS => '0' );
shiftin ( 63 downto 31 ) := '0' & unsigned ( aluin1 );
ELSE
shiftin ( 63 downto 32 ) := ( OTHERS => r.e.sari );
shiftin ( 31 downto 0 ) := unsigned ( aluin1 );
END IF;
shiftout := SHIFT_RIGHT ( shiftin , cnt );
RETURN ( std_logic_vector ( shiftout ( 31 downto 0 ) ) );
END;
FUNCTION shift2 (
r : registers;
aluin1 : word;
aluin2 : word
) RETURN word IS
VARIABLE ushiftin : unsigned ( 31 downto 0 );
VARIABLE sshiftin : signed ( 32 downto 0 );
VARIABLE cnt : natural RANGE 0 to 31;
BEGIN
cnt := conv_integer ( r.e.shcnt );
ushiftin := unsigned ( aluin1 );
sshiftin := signed ( '0' & aluin1 );
IF r.e.shleft = '1' THEN
RETURN ( std_logic_vector ( SHIFT_LEFT ( ushiftin , cnt ) ) );
ELSE
IF r.e.sari = '1' THEN
sshiftin ( 32 ) := aluin1 ( 31 );
END IF;
sshiftin := SHIFT_RIGHT ( sshiftin , cnt );
RETURN ( std_logic_vector ( sshiftin ( 31 downto 0 ) ) );
END IF;
END;
FUNCTION shift (
r : registers;
aluin1 : word;
aluin2 : word;
shiftcnt : std_logic_vector ( 4 downto 0 );
sari : std_ulogic
) RETURN word IS
VARIABLE shiftin : std_logic_vector ( 63 downto 0 );
BEGIN
shiftin := zero32 & aluin1;
IF r.e.shleft = '1' THEN
shiftin ( 31 downto 0 ) := zero32;
shiftin ( 63 downto 31 ) := '0' & aluin1;
ELSE
shiftin ( 63 downto 32 ) := ( OTHERS => sari );
END IF;
IF shiftcnt ( 4 ) = '1' THEN
shiftin ( 47 downto 0 ) := shiftin ( 63 downto 16 );
END IF;
IF shiftcnt ( 3 ) = '1' THEN
shiftin ( 39 downto 0 ) := shiftin ( 47 downto 8 );
END IF;
IF shiftcnt ( 2 ) = '1' THEN
shiftin ( 35 downto 0 ) := shiftin ( 39 downto 4 );
END IF;
IF shiftcnt ( 1 ) = '1' THEN
shiftin ( 33 downto 0 ) := shiftin ( 35 downto 2 );
END IF;
IF shiftcnt ( 0 ) = '1' THEN
shiftin ( 31 downto 0 ) := shiftin ( 32 downto 1 );
END IF;
RETURN ( shiftin ( 31 downto 0 ) );
END;
PROCEDURE exception_detect (
r : registers;
wpr : watchpoint_registers;
dbgi : l3_debug_in_type;
trapin : in std_ulogic;
ttin : in std_logic_vector ( 5 downto 0 );
trap : out std_ulogic;
tt : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE illegal_inst : std_ulogic;
VARIABLE privileged_inst : std_ulogic;
VARIABLE cp_disabled : std_ulogic;
VARIABLE fp_disabled : std_ulogic;
VARIABLE fpop : std_ulogic;
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE inst : word;
VARIABLE wph : std_ulogic;
BEGIN
inst := r.a.ctrl.inst;
trap := trapin;
tt := ttin;
IF r.a.ctrl.annul = '0' THEN
op := inst ( 31 downto 30 );
op2 := inst ( 24 downto 22 );
op3 := inst ( 24 downto 19 );
rd := inst ( 29 downto 25 );
illegal_inst := '0';
privileged_inst := '0';
cp_disabled := '0';
fp_disabled := '0';
fpop := '0';
CASE op IS
WHEN CALL =>
NULL;
WHEN FMT2 =>
CASE op2 IS
WHEN SETHI | BICC =>
NULL;
WHEN FBFCC =>
fp_disabled := '1';
WHEN CBCCC =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR | XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX | ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC | SAVE | RESTORE | RDY =>
NULL;
WHEN TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
NULL;
WHEN UMAC | SMAC =>
illegal_inst := '1';
WHEN UMUL | SMUL | UMULCC | SMULCC =>
NULL;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
NULL;
WHEN RETT =>
illegal_inst := r.a.et;
privileged_inst := not r.a.su;
WHEN RDPSR | RDTBR | RDWIM =>
privileged_inst := not r.a.su;
WHEN WRY =>
NULL;
WHEN WRPSR =>
privileged_inst := not r.a.su;
WHEN WRWIM | WRTBR =>
privileged_inst := not r.a.su;
WHEN FPOP1 | FPOP2 =>
fp_disabled := '1';
fpop := '0';
WHEN CPOP1 | CPOP2 =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
WHEN OTHERS =>
CASE op3 IS
WHEN LDD | ISTD =>
illegal_inst := rd ( 0 );
WHEN LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
NULL;
WHEN LDDA | STDA =>
illegal_inst := inst ( 13 ) or rd ( 0 );
privileged_inst := not r.a.su;
WHEN LDA | LDUBA | LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA | SWAPA =>
illegal_inst := inst ( 13 );
privileged_inst := not r.a.su;
WHEN LDDF | STDF | LDF | LDFSR | STF | STFSR =>
fp_disabled := '1';
WHEN STDFQ =>
privileged_inst := not r.a.su;
fp_disabled := '1';
WHEN STDCQ =>
privileged_inst := not r.a.su;
cp_disabled := '1';
WHEN LDC | LDCSR | LDDC | STC | STCSR | STDC =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
END CASE;
wph := wphit ( r , wpr , dbgi );
trap := '1';
IF r.a.ctrl.trap = '1' THEN
tt := TT_IAEX;
ELSIF privileged_inst = '1' THEN
tt := TT_PRIV;
ELSIF illegal_inst = '1' THEN
tt := TT_IINST;
ELSIF fp_disabled = '1' THEN
tt := TT_FPDIS;
ELSIF cp_disabled = '1' THEN
tt := TT_CPDIS;
ELSIF wph = '1' THEN
tt := TT_WATCH;
ELSIF r.a.wovf = '1' THEN
tt := TT_WINOF;
ELSIF r.a.wunf = '1' THEN
tt := TT_WINUF;
ELSIF r.a.ticc = '1' THEN
tt := TT_TICC;
ELSE
trap := '0';
tt := ( OTHERS => '0' );
END IF;
END IF;
END;
PROCEDURE wicc_y_gen (
inst : word;
wicc : out std_ulogic;
wy : out std_ulogic
) IS
BEGIN
wicc := '0';
wy := '0';
IF inst ( 31 downto 30 ) = FMT3 THEN
CASE inst ( 24 downto 19 ) IS
WHEN SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC | ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
WHEN WRY =>
IF r.d.inst ( conv_integer ( r.d.set ) ) ( 29 downto 25 ) = "00000" THEN
wy := '1';
END IF;
WHEN MULSCC =>
wicc := '1';
wy := '1';
WHEN UMAC | SMAC =>
NULL;
WHEN UMULCC | SMULCC =>
IF ( ( ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) ) ) THEN
wicc := '1';
wy := '1';
END IF;
WHEN UMUL | SMUL =>
IF ( ( ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) ) ) THEN
wy := '1';
END IF;
WHEN UDIVCC | SDIVCC =>
IF ( divo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
wicc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END;
PROCEDURE cwp_gen (
r : registers;
v : registers;
annul : std_ulogic;
wcwp : std_ulogic;
ncwp : cwptype;
cwp : out cwptype
) IS
BEGIN
IF ( r.x.rstate = trap ) or ( r.x.rstate = dsu2 ) or ( rstn = '0' ) THEN
cwp := v.w.s.cwp;
ELSIF ( wcwp = '1' ) and ( annul = '0' ) THEN
cwp := ncwp;
ELSIF r.m.wcwp = '1' THEN
cwp := r.m.result ( LOG2 ( 8 ) - 1 downto 0 );
ELSE
cwp := r.d.cwp;
END IF;
END;
PROCEDURE cwp_ex (
r : in registers;
wcwp : out std_ulogic
) IS
BEGIN
IF ( r.e.ctrl.inst ( 31 downto 30 ) = FMT3 ) and ( r.e.ctrl.inst ( 24 downto 19 ) = WRPSR ) THEN
wcwp := not r.e.ctrl.annul;
ELSE
wcwp := '0';
END IF;
END;
PROCEDURE cwp_ctrl (
r : in registers;
xc_wim : in std_logic_vector ( 8 - 1 downto 0 );
inst : word;
de_cwp : out cwptype;
wovf_exc : out std_ulogic;
wunf_exc : out std_ulogic;
wcwp : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE wim : word;
VARIABLE ncwp : cwptype;
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
wovf_exc := '0';
wunf_exc := '0';
wim := ( OTHERS => '0' );
wim ( 8 - 1 downto 0 ) := xc_wim;
ncwp := r.d.cwp;
wcwp := '0';
IF ( op = FMT3 ) and ( ( op3 = RETT ) or ( op3 = RESTORE ) or ( op3 = SAVE ) ) THEN
wcwp := '1';
IF ( op3 = SAVE ) THEN
ncwp := r.d.cwp - 1;
ELSE
ncwp := r.d.cwp + 1;
END IF;
IF wim ( conv_integer ( ncwp ) ) = '1' THEN
IF op3 = SAVE THEN
wovf_exc := '1';
ELSE
wunf_exc := '1';
END IF;
END IF;
END IF;
de_cwp := ncwp;
END;
PROCEDURE rs1_gen (
r : registers;
inst : word;
rs1 : out std_logic_vector ( 4 downto 0 );
rs1mod : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
rs1 := inst ( 18 downto 14 );
rs1mod := '0';
IF ( op = LDST ) THEN
IF ( ( r.d.cnt = "01" ) and ( ( op3 ( 2 ) and not op3 ( 3 ) ) = '1' ) ) or ( r.d.cnt = "10" ) THEN
rs1mod := '1';
rs1 := inst ( 29 downto 25 );
END IF;
IF ( ( r.d.cnt = "10" ) and ( op3 ( 3 downto 0 ) = "0111" ) ) THEN
rs1 ( 0 ) := '1';
END IF;
END IF;
END;
PROCEDURE lock_gen (
r : registers;
rs2 : std_logic_vector ( 4 downto 0 );
rd : std_logic_vector ( 4 downto 0 );
rfa1 : rfatype;
rfa2 : rfatype;
rfrd : rfatype;
inst : word;
fpc_lock : std_ulogic;
mulinsn : std_ulogic;
divinsn : std_ulogic;
lldcheck1 : out std_ulogic;
lldcheck2 : out std_ulogic;
lldlock : out std_ulogic;
lldchkra : out std_ulogic;
lldchkex : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE rs1 : std_logic_vector ( 4 downto 0 );
VARIABLE i : std_ulogic;
VARIABLE ldcheck1 : std_ulogic;
VARIABLE ldcheck2 : std_ulogic;
VARIABLE ldchkra : std_ulogic;
VARIABLE ldchkex : std_ulogic;
VARIABLE ldcheck3 : std_ulogic;
VARIABLE ldlock : std_ulogic;
VARIABLE icc_check : std_ulogic;
VARIABLE bicc_hold : std_ulogic;
VARIABLE chkmul : std_ulogic;
VARIABLE y_check : std_ulogic;
VARIABLE lddlock : boolean;
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
op2 := inst ( 24 downto 22 );
cond := inst ( 28 downto 25 );
rs1 := inst ( 18 downto 14 );
lddlock := false;
i := inst ( 13 );
ldcheck1 := '0';
ldcheck2 := '0';
ldcheck3 := '0';
ldlock := '0';
ldchkra := '1';
ldchkex := '1';
icc_check := '0';
bicc_hold := '0';
y_check := '0';
IF ( r.d.annul = '0' ) THEN
CASE op IS
WHEN FMT2 =>
IF ( op2 = BICC ) and ( cond ( 2 downto 0 ) /= "000" ) THEN
icc_check := '1';
END IF;
WHEN FMT3 =>
ldcheck1 := '1';
ldcheck2 := not i;
CASE op3 IS
WHEN TICC =>
IF ( cond ( 2 downto 0 ) /= "000" ) THEN
icc_check := '1';
END IF;
WHEN RDY =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN RDWIM | RDTBR =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN RDPSR =>
ldcheck1 := '0';
ldcheck2 := '0';
icc_check := '1';
icc_check := '1';
WHEN SDIV | SDIVCC | UDIV | UDIVCC =>
y_check := '1';
WHEN FPOP1 | FPOP2 =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
ldcheck1 := '1';
ldchkra := '0';
CASE r.d.cnt IS
WHEN "00" =>
ldcheck2 := not i;
ldchkra := '1';
WHEN "01" =>
ldcheck2 := not i;
WHEN OTHERS =>
ldchkex := '0';
END CASE;
IF ( op3 ( 2 downto 0 ) = "011" ) THEN
lddlock := true;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
chkmul := mulinsn;
bicc_hold := bicc_hold or ( icc_check and r.m.ctrl.wicc and ( r.m.ctrl.cnt ( 0 ) or r.m.mul ) );
bicc_hold := bicc_hold or ( y_check and ( r.a.ctrl.wy or r.e.ctrl.wy ) );
chkmul := chkmul or divinsn;
bicc_hold := bicc_hold or ( icc_check and ( r.a.ctrl.wicc or r.e.ctrl.wicc ) );
IF ( ( ( r.a.ctrl.ld or chkmul ) and r.a.ctrl.wreg and ldchkra ) = '1' ) and ( ( ( ldcheck1 = '1' ) and ( r.a.ctrl.rd = rfa1 ) ) or ( ( ldcheck2 = '1' ) and ( r.a.ctrl.rd = rfa2 ) ) or ( ( ldcheck3 = '1' ) and ( r.a.ctrl.rd = rfrd ) ) ) THEN
ldlock := '1';
END IF;
IF ( ( ( r.e.ctrl.ld or r.e.mac ) and r.e.ctrl.wreg and ldchkex ) = '1' ) and ( ( ( ldcheck1 = '1' ) and ( r.e.ctrl.rd = rfa1 ) ) or ( ( ldcheck2 = '1' ) and ( r.e.ctrl.rd = rfa2 ) ) ) THEN
ldlock := '1';
END IF;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1;
lldcheck2 := ldcheck2;
lldlock := ldlock;
lldchkra := ldchkra;
lldchkex := ldchkex;
END;
PROCEDURE fpbranch (
inst : in word;
fcc : in std_logic_vector ( 1 downto 0 );
branch : out std_ulogic
) IS
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE fbres : std_ulogic;
BEGIN
cond := inst ( 28 downto 25 );
CASE cond ( 2 downto 0 ) IS
WHEN "000" =>
fbres := '0';
WHEN "001" =>
fbres := fcc ( 1 ) or fcc ( 0 );
WHEN "010" =>
fbres := fcc ( 1 ) xor fcc ( 0 );
WHEN "011" =>
fbres := fcc ( 0 );
WHEN "100" =>
fbres := ( not fcc ( 1 ) ) and fcc ( 0 );
WHEN "101" =>
fbres := fcc ( 1 );
WHEN "110" =>
fbres := fcc ( 1 ) and not fcc ( 0 );
WHEN OTHERS =>
fbres := fcc ( 1 ) and fcc ( 0 );
END CASE;
branch := cond ( 3 ) xor fbres;
END;
PROCEDURE ic_ctrl (
r : registers;
inst : word;
annul_all : in std_ulogic;
ldlock : in std_ulogic;
branch_true : in std_ulogic;
fbranch_true : in std_ulogic;
cbranch_true : in std_ulogic;
fccv : in std_ulogic;
cccv : in std_ulogic;
cnt : out std_logic_vector ( 1 downto 0 );
de_pc : out pctype;
de_branch : out std_ulogic;
ctrl_annul : out std_ulogic;
de_annul : out std_ulogic;
jmpl_inst : out std_ulogic;
inull : out std_ulogic;
de_pv : out std_ulogic;
ctrl_pv : out std_ulogic;
de_hold_pc : out std_ulogic;
ticc_exception : out std_ulogic;
rett_inst : out std_ulogic;
mulstart : out std_ulogic;
divstart : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE hold_pc : std_ulogic;
VARIABLE annul_current : std_ulogic;
VARIABLE annul_next : std_ulogic;
VARIABLE branch : std_ulogic;
VARIABLE annul : std_ulogic;
VARIABLE pv : std_ulogic;
VARIABLE de_jmpl : std_ulogic;
BEGIN
branch := '0';
annul_next := '0';
annul_current := '0';
pv := '1';
hold_pc := '0';
ticc_exception := '0';
rett_inst := '0';
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
op2 := inst ( 24 downto 22 );
cond := inst ( 28 downto 25 );
annul := inst ( 29 );
de_jmpl := '0';
cnt := "00";
mulstart := '0';
divstart := '0';
IF r.d.annul = '0' THEN
CASE inst ( 31 downto 30 ) IS
WHEN CALL =>
branch := '1';
IF r.d.inull = '1' THEN
hold_pc := '1';
annul_current := '1';
END IF;
WHEN FMT2 =>
IF ( op2 = BICC ) THEN
branch := branch_true;
IF hold_pc = '0' THEN
IF ( branch = '1' ) THEN
IF ( cond = BA ) and ( annul = '1' ) THEN
annul_next := '1';
END IF;
ELSE
annul_next := annul;
END IF;
IF r.d.inull = '1' THEN
hold_pc := '1';
annul_current := '1';
annul_next := '0';
END IF;
END IF;
END IF;
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL | UMULCC | SMULCC =>
CASE r.d.cnt IS
WHEN "00" =>
cnt := "01";
hold_pc := '1';
pv := '0';
mulstart := '1';
WHEN "01" =>
IF mulo.nready = '1' THEN
cnt := "00";
ELSE
cnt := "01";
pv := '0';
hold_pc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
CASE r.d.cnt IS
WHEN "00" =>
cnt := "01";
hold_pc := '1';
pv := '0';
divstart := '1';
WHEN "01" =>
IF divo.nready = '1' THEN
cnt := "00";
ELSE
cnt := "01";
pv := '0';
hold_pc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN TICC =>
IF branch_true = '1' THEN
ticc_exception := '1';
END IF;
WHEN RETT =>
rett_inst := '1';
WHEN JMPL =>
de_jmpl := '1';
WHEN WRY =>
IF FALSE THEN
IF inst ( 29 downto 25 ) = "10011" THEN
CASE r.d.cnt IS
WHEN "00" =>
pv := '0';
cnt := "00";
hold_pc := '1';
IF r.x.ipend = '1' THEN
cnt := "01";
END IF;
WHEN "01" =>
cnt := "00";
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
CASE r.d.cnt IS
WHEN "00" =>
IF ( op3 ( 2 ) = '1' ) or ( op3 ( 1 downto 0 ) = "11" ) THEN
cnt := "01";
hold_pc := '1';
pv := '0';
END IF;
WHEN "01" =>
IF ( op3 ( 2 downto 0 ) = "111" ) or ( op3 ( 3 downto 0 ) = "1101" ) or ( ( ( 0 = 1 ) or ( 0 /= 0 ) ) and ( ( op3 ( 5 ) & op3 ( 2 downto 0 ) ) = "1110" ) ) THEN
cnt := "10";
pv := '0';
hold_pc := '1';
ELSE
cnt := "00";
END IF;
WHEN "10" =>
cnt := "00";
WHEN OTHERS =>
NULL;
END CASE;
END CASE;
END IF;
IF ldlock = '1' THEN
cnt := r.d.cnt;
annul_next := '0';
pv := '1';
END IF;
hold_pc := ( hold_pc or ldlock ) and not annul_all;
IF hold_pc = '1' THEN
de_pc := r.d.pc;
ELSE
de_pc := r.f.pc;
END IF;
annul_current := ( annul_current or ldlock or annul_all );
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ( ( r.d.inull and not hold_pc ) or annul_all );
jmpl_inst := de_jmpl and not annul_current;
annul_next := ( r.d.inull and not hold_pc ) or annul_next or annul_all;
IF ( annul_next = '1' ) or ( rstn = '0' ) THEN
cnt := ( OTHERS => '0' );
END IF;
de_hold_pc := hold_pc;
de_branch := branch;
de_annul := annul_next;
de_pv := pv;
ctrl_pv := r.d.pv and not ( ( r.d.annul and not r.d.pv ) or annul_all or annul_current );
inull := ( not rstn ) or r.d.inull or hold_pc or annul_all;
END;
PROCEDURE rd_gen (
r : registers;
inst : word;
wreg : out std_ulogic;
ld : out std_ulogic;
rdo : out std_logic_vector ( 4 downto 0 )
) IS
VARIABLE write_reg : std_ulogic;
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
BEGIN
op := inst ( 31 downto 30 );
op2 := inst ( 24 downto 22 );
op3 := inst ( 24 downto 19 );
write_reg := '0';
rd := inst ( 29 downto 25 );
ld := '0';
CASE op IS
WHEN CALL =>
write_reg := '1';
rd := "01111";
WHEN FMT2 =>
IF ( op2 = SETHI ) THEN
write_reg := '1';
END IF;
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL | UMULCC | SMULCC =>
IF ( ( ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) ) ) THEN
write_reg := '1';
END IF;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
IF ( divo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
write_reg := '1';
END IF;
WHEN RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH =>
NULL;
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN CPOP1 | CPOP2 =>
NULL;
WHEN OTHERS =>
write_reg := '1';
END CASE;
WHEN OTHERS =>
ld := not op3 ( 2 );
IF ( op3 ( 2 ) = '0' ) and not ( ( ( 0 = 1 ) or ( 0 /= 0 ) ) and ( op3 ( 5 ) = '1' ) ) THEN
write_reg := '1';
END IF;
CASE op3 IS
WHEN SWAP | SWAPA | LDSTUB | LDSTUBA =>
IF r.d.cnt = "00" THEN
write_reg := '1';
ld := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
IF r.d.cnt = "01" THEN
CASE op3 IS
WHEN LDD | LDDA | LDDC | LDDF =>
rd ( 0 ) := '1';
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END CASE;
IF ( rd = "00000" ) THEN
write_reg := '0';
END IF;
wreg := write_reg;
rdo := rd;
END;
FUNCTION imm_data (
r : registers;
insn : word
) RETURN word IS
VARIABLE immediate_data : word;
VARIABLE inst : word;
BEGIN
immediate_data := ( OTHERS => '0' );
inst := insn;
CASE inst ( 31 downto 30 ) IS
WHEN FMT2 =>
immediate_data := inst ( 21 downto 0 ) & "0000000000";
WHEN OTHERS =>
immediate_data ( 31 downto 13 ) := ( OTHERS => inst ( 12 ) );
immediate_data ( 12 downto 0 ) := inst ( 12 downto 0 );
END CASE;
RETURN ( immediate_data );
END;
FUNCTION get_spr (
r : registers
) RETURN word IS
VARIABLE spr : word;
BEGIN
spr := ( OTHERS => '0' );
CASE r.e.ctrl.inst ( 24 downto 19 ) IS
WHEN RDPSR =>
spr ( 31 downto 5 ) := conv_std_logic_vector ( 15 , 4 ) & conv_std_logic_vector ( 3 , 4 ) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr ( LOG2 ( 8 ) - 1 downto 0 ) := r.e.cwp;
WHEN RDTBR =>
spr ( 31 downto 4 ) := r.w.s.tba & r.w.s.tt;
WHEN RDWIM =>
spr ( 8 - 1 downto 0 ) := r.w.s.wim;
WHEN OTHERS =>
NULL;
END CASE;
RETURN ( spr );
END;
FUNCTION imm_select (
inst : word
) RETURN boolean IS
VARIABLE imm : boolean;
BEGIN
imm := false;
CASE inst ( 31 downto 30 ) IS
WHEN FMT2 =>
CASE inst ( 24 downto 22 ) IS
WHEN SETHI =>
imm := true;
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE inst ( 24 downto 19 ) IS
WHEN RDWIM | RDPSR | RDTBR =>
imm := true;
WHEN OTHERS =>
IF ( inst ( 13 ) = '1' ) THEN
imm := true;
END IF;
END CASE;
WHEN LDST =>
IF ( inst ( 13 ) = '1' ) THEN
imm := true;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
RETURN ( imm );
END;
PROCEDURE alu_op (
r : in registers;
iop1 : in word;
iop2 : in word;
me_icc : std_logic_vector ( 3 downto 0 );
my : std_ulogic;
ldbp : std_ulogic;
aop1 : out word;
aop2 : out word;
aluop : out std_logic_vector ( 2 downto 0 );
alusel : out std_logic_vector ( 1 downto 0 );
aluadd : out std_ulogic;
shcnt : out std_logic_vector ( 4 downto 0 );
sari : out std_ulogic;
shleft : out std_ulogic;
ymsb : out std_ulogic;
mulins : out std_ulogic;
divins : out std_ulogic;
mulstep : out std_ulogic;
macins : out std_ulogic;
ldbp2 : out std_ulogic;
invop2 : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE icc : std_logic_vector ( 3 downto 0 );
VARIABLE y0 : std_ulogic;
BEGIN
op := r.a.ctrl.inst ( 31 downto 30 );
op2 := r.a.ctrl.inst ( 24 downto 22 );
op3 := r.a.ctrl.inst ( 24 downto 19 );
aop1 := iop1;
aop2 := iop2;
ldbp2 := ldbp;
aluop := "000";
alusel := "11";
aluadd := '1';
shcnt := iop2 ( 4 downto 0 );
sari := '0';
shleft := '0';
invop2 := '0';
ymsb := iop1 ( 0 );
mulins := '0';
divins := '0';
mulstep := '0';
macins := '0';
IF r.e.ctrl.wy = '1' THEN
y0 := my;
ELSIF r.m.ctrl.wy = '1' THEN
y0 := r.m.y ( 0 );
ELSIF r.x.ctrl.wy = '1' THEN
y0 := r.x.y ( 0 );
ELSE
y0 := r.w.s.y ( 0 );
END IF;
IF r.e.ctrl.wicc = '1' THEN
icc := me_icc;
ELSIF r.m.ctrl.wicc = '1' THEN
icc := r.m.icc;
ELSIF r.x.ctrl.wicc = '1' THEN
icc := r.x.icc;
ELSE
icc := r.w.s.icc;
END IF;
CASE op IS
WHEN CALL =>
aluop := "111";
WHEN FMT2 =>
CASE op2 IS
WHEN SETHI =>
aluop := "001";
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE | TICC | JMPL | RETT =>
alusel := "00";
WHEN ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := "00";
aluadd := '0';
aop2 := not iop2;
invop2 := '1';
WHEN MULSCC =>
alusel := "00";
aop1 := ( icc ( 3 ) xor icc ( 1 ) ) & iop1 ( 31 downto 1 );
IF y0 = '0' THEN
aop2 := ( OTHERS => '0' );
ldbp2 := '0';
END IF;
mulstep := '1';
WHEN UMUL | UMULCC | SMUL | SMULCC =>
mulins := '1';
WHEN UMAC | SMAC =>
NULL;
WHEN UDIV | UDIVCC | SDIV | SDIVCC =>
aluop := "110";
alusel := "10";
divins := '1';
WHEN IAND | ANDCC =>
aluop := "000";
alusel := "10";
WHEN ANDN | ANDNCC =>
aluop := "100";
alusel := "10";
WHEN IOR | ORCC =>
aluop := "010";
alusel := "10";
WHEN ORN | ORNCC =>
aluop := "101";
alusel := "10";
WHEN IXNOR | XNORCC =>
aluop := "011";
alusel := "10";
WHEN XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := "001";
alusel := "10";
WHEN RDPSR | RDTBR | RDWIM =>
aluop := "110";
WHEN RDY =>
aluop := "101";
WHEN ISLL =>
aluop := "001";
alusel := "01";
shleft := '1';
shcnt := not iop2 ( 4 downto 0 );
invop2 := '1';
WHEN ISRL =>
aluop := "010";
alusel := "01";
WHEN ISRA =>
aluop := "100";
alusel := "01";
sari := iop1 ( 31 );
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
CASE r.a.ctrl.cnt IS
WHEN "00" =>
alusel := "00";
WHEN "01" =>
CASE op3 IS
WHEN LDD | LDDA | LDDC =>
alusel := "00";
WHEN LDDF =>
alusel := "00";
WHEN SWAP | SWAPA | LDSTUB | LDSTUBA =>
alusel := "00";
WHEN STF | STDF =>
NULL;
WHEN OTHERS =>
aluop := "000";
IF op3 ( 2 ) = '1' THEN
IF op3 ( 1 downto 0 ) = "01" THEN
aluop := "010";
ELSIF op3 ( 1 downto 0 ) = "10" THEN
aluop := "011";
END IF;
END IF;
END CASE;
WHEN "10" =>
aluop := "000";
IF op3 ( 2 ) = '1' THEN
IF ( op3 ( 3 ) and not op3 ( 1 ) ) = '1' THEN
aluop := "100";
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END CASE;
END;
FUNCTION ra_inull_gen (
r : registers;
v : registers
) RETURN std_ulogic IS
VARIABLE de_inull : std_ulogic;
BEGIN
de_inull := '0';
IF ( ( v.e.jmpl or v.e.ctrl.rett ) and not v.e.ctrl.annul and not ( r.e.jmpl and not r.e.ctrl.annul ) ) = '1' THEN
de_inull := '1';
END IF;
IF ( ( v.a.jmpl or v.a.ctrl.rett ) and not v.a.ctrl.annul and not ( r.a.jmpl and not r.a.ctrl.annul ) ) = '1' THEN
de_inull := '1';
END IF;
RETURN ( de_inull );
END;
PROCEDURE op_mux (
r : in registers;
rfd : in word;
ed : in word;
md : in word;
xd : in word;
im : in word;
rsel : in std_logic_vector ( 2 downto 0 );
ldbp : out std_ulogic;
d : out word
) IS
BEGIN
ldbp := '0';
CASE rsel IS
WHEN "000" =>
d := rfd;
WHEN "001" =>
d := ed;
WHEN "010" =>
d := md;
ldbp := r.m.ctrl.ld;
WHEN "011" =>
d := xd;
WHEN "100" =>
d := im;
WHEN "101" =>
d := ( OTHERS => '0' );
WHEN "110" =>
d := r.w.result;
WHEN OTHERS =>
d := ( OTHERS => '-' );
END CASE;
END;
PROCEDURE op_find (
r : in registers;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
rs1 : std_logic_vector ( 4 downto 0 );
ra : rfatype;
im : boolean;
rfe : out std_ulogic;
osel : out std_logic_vector ( 2 downto 0 );
ldcheck : std_ulogic
) IS
BEGIN
rfe := '0';
IF im THEN
osel := "100";
ELSIF rs1 = "00000" THEN
osel := "101";
ELSIF ( ( r.a.ctrl.wreg and ldchkra ) = '1' ) and ( ra = r.a.ctrl.rd ) THEN
osel := "001";
ELSIF ( ( r.e.ctrl.wreg and ldchkex ) = '1' ) and ( ra = r.e.ctrl.rd ) THEN
osel := "010";
ELSIF r.m.ctrl.wreg = '1' and ( ra = r.m.ctrl.rd ) THEN
osel := "011";
ELSE
osel := "000";
rfe := ldcheck;
END IF;
END;
PROCEDURE cin_gen (
r : registers;
me_cin : in std_ulogic;
cin : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE ncin : std_ulogic;
BEGIN
op := r.a.ctrl.inst ( 31 downto 30 );
op3 := r.a.ctrl.inst ( 24 downto 19 );
IF r.e.ctrl.wicc = '1' THEN
ncin := me_cin;
ELSE
ncin := r.m.icc ( 0 );
END IF;
cin := '0';
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN ISUB | SUBCC | TSUBCC | TSUBCCTV =>
cin := '1';
WHEN ADDX | ADDXCC =>
cin := ncin;
WHEN SUBX | SUBXCC =>
cin := not ncin;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END;
PROCEDURE logic_op (
r : registers;
aluin1 : word;
aluin2 : word;
mey : word;
ymsb : std_ulogic;
logicres : out word;
y : out word
) IS
VARIABLE logicout : word;
BEGIN
CASE r.e.aluop IS
WHEN "000" =>
logicout := aluin1 and aluin2;
WHEN "100" =>
logicout := aluin1 and not aluin2;
WHEN "010" =>
logicout := aluin1 or aluin2;
WHEN "101" =>
logicout := aluin1 or not aluin2;
WHEN "001" =>
logicout := aluin1 xor aluin2;
WHEN "011" =>
logicout := aluin1 xor not aluin2;
WHEN "110" =>
logicout := aluin2;
WHEN OTHERS =>
logicout := ( OTHERS => '-' );
END CASE;
IF ( r.e.ctrl.wy and r.e.mulstep ) = '1' THEN
y := ymsb & r.m.y ( 31 downto 1 );
ELSIF r.e.ctrl.wy = '1' THEN
y := logicout;
ELSIF r.m.ctrl.wy = '1' THEN
y := mey;
ELSIF r.x.ctrl.wy = '1' THEN
y := r.x.y;
ELSE
y := r.w.s.y;
END IF;
logicres := logicout;
END;
PROCEDURE misc_op (
r : registers;
wpr : watchpoint_registers;
aluin1 : word;
aluin2 : word;
ldata : word;
mey : word;
mout : out word;
edata : out word
) IS
VARIABLE miscout : word;
VARIABLE bpdata : word;
VARIABLE stdata : word;
VARIABLE wpi : integer;
BEGIN
wpi := 0;
miscout := r.e.ctrl.pc ( 31 downto 2 ) & "00";
edata := aluin1;
bpdata := aluin1;
IF ( ( r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul ) = '1' ) and ( r.x.ctrl.rd = r.e.ctrl.rd ) and ( r.e.ctrl.inst ( 31 downto 30 ) = LDST ) and ( r.e.ctrl.cnt /= "10" ) THEN
bpdata := ldata;
END IF;
CASE r.e.aluop IS
WHEN "010" =>
miscout := bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 );
edata := miscout;
WHEN "011" =>
miscout := bpdata ( 15 downto 0 ) & bpdata ( 15 downto 0 );
edata := miscout;
WHEN "000" =>
miscout := bpdata;
edata := miscout;
WHEN "001" =>
miscout := aluin2;
WHEN "100" =>
miscout := ( OTHERS => '1' );
edata := miscout;
WHEN "101" =>
IF ( r.m.ctrl.wy = '1' ) THEN
miscout := mey;
ELSE
miscout := r.m.y;
END IF;
IF ( r.e.ctrl.inst ( 18 downto 17 ) = "11" ) THEN
wpi := conv_integer ( r.e.ctrl.inst ( 16 downto 15 ) );
IF r.e.ctrl.inst ( 14 ) = '0' THEN
miscout := wpr ( wpi ).addr & '0' & wpr ( wpi ).exec;
ELSE
miscout := wpr ( wpi ).mask & wpr ( wpi ).load & wpr ( wpi ).store;
END IF;
END IF;
IF ( r.e.ctrl.inst ( 18 downto 17 ) = "10" ) and ( r.e.ctrl.inst ( 14 ) = '1' ) THEN
miscout := asr17_gen ( r );
END IF;
WHEN "110" =>
miscout := get_spr ( r );
WHEN OTHERS =>
NULL;
END CASE;
mout := miscout;
END;
PROCEDURE alu_select (
r : registers;
addout : std_logic_vector ( 32 downto 0 );
op1 : word;
op2 : word;
shiftout : word;
logicout : word;
miscout : word;
res : out word;
me_icc : std_logic_vector ( 3 downto 0 );
icco : out std_logic_vector ( 3 downto 0 );
divz : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE icc : std_logic_vector ( 3 downto 0 );
VARIABLE aluresult : word;
BEGIN
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
icc := ( OTHERS => '0' );
CASE r.e.alusel IS
WHEN "00" =>
aluresult := addout ( 32 downto 1 );
IF r.e.aluadd = '0' THEN
icc ( 0 ) := ( ( not op1 ( 31 ) ) and not op2 ( 31 ) ) or ( addout ( 32 ) and ( ( not op1 ( 31 ) ) or not op2 ( 31 ) ) );
icc ( 1 ) := ( op1 ( 31 ) and ( op2 ( 31 ) ) and not addout ( 32 ) ) or ( addout ( 32 ) and ( not op1 ( 31 ) ) and not op2 ( 31 ) );
ELSE
icc ( 0 ) := ( op1 ( 31 ) and op2 ( 31 ) ) or ( ( not addout ( 32 ) ) and ( op1 ( 31 ) or op2 ( 31 ) ) );
icc ( 1 ) := ( op1 ( 31 ) and op2 ( 31 ) and not addout ( 32 ) ) or ( addout ( 32 ) and ( not op1 ( 31 ) ) and ( not op2 ( 31 ) ) );
END IF;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN TADDCC | TADDCCTV =>
icc ( 1 ) := op1 ( 0 ) or op1 ( 1 ) or op2 ( 0 ) or op2 ( 1 ) or icc ( 1 );
WHEN TSUBCC | TSUBCCTV =>
icc ( 1 ) := op1 ( 0 ) or op1 ( 1 ) or ( not op2 ( 0 ) ) or ( not op2 ( 1 ) ) or icc ( 1 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
IF aluresult = zero32 THEN
icc ( 2 ) := '1';
END IF;
WHEN "01" =>
aluresult := shiftout;
WHEN "10" =>
aluresult := logicout;
IF aluresult = zero32 THEN
icc ( 2 ) := '1';
END IF;
WHEN OTHERS =>
aluresult := miscout;
END CASE;
IF r.e.jmpl = '1' THEN
aluresult := r.e.ctrl.pc ( 31 downto 2 ) & "00";
END IF;
icc ( 3 ) := aluresult ( 31 );
divz := icc ( 2 );
IF r.e.ctrl.wicc = '1' THEN
IF ( op = FMT3 ) and ( op3 = WRPSR ) THEN
icco := logicout ( 23 downto 20 );
ELSE
icco := icc;
END IF;
ELSIF r.m.ctrl.wicc = '1' THEN
icco := me_icc;
ELSIF r.x.ctrl.wicc = '1' THEN
icco := r.x.icc;
ELSE
icco := r.w.s.icc;
END IF;
res := aluresult;
END;
PROCEDURE dcache_gen (
r : registers;
v : registers;
dci : out dc_in_type;
link_pc : out std_ulogic;
jump : out std_ulogic;
force_a2 : out std_ulogic;
load : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE su : std_ulogic;
BEGIN
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
dci.signed := '0';
dci.lock := '0';
dci.dsuen := '0';
dci.size := "10";
IF op = LDST THEN
CASE op3 IS
WHEN LDUB | LDUBA =>
dci.size := "00";
WHEN LDSTUB | LDSTUBA =>
dci.size := "00";
dci.lock := '1';
WHEN LDUH | LDUHA =>
dci.size := "01";
WHEN LDSB | LDSBA =>
dci.size := "00";
dci.signed := '1';
WHEN LDSH | LDSHA =>
dci.size := "01";
dci.signed := '1';
WHEN LD | LDA | LDF | LDC =>
dci.size := "10";
WHEN SWAP | SWAPA =>
dci.size := "10";
dci.lock := '1';
WHEN LDD | LDDA | LDDF | LDDC =>
dci.size := "11";
WHEN STB | STBA =>
dci.size := "00";
WHEN STH | STHA =>
dci.size := "01";
WHEN ST | STA | STF =>
dci.size := "10";
WHEN ISTD | STDA =>
dci.size := "11";
WHEN STDF | STDFQ =>
NULL;
WHEN STDC | STDCQ =>
NULL;
WHEN OTHERS =>
dci.size := "10";
dci.lock := '0';
dci.signed := '0';
END CASE;
END IF;
link_pc := '0';
jump := '0';
force_a2 := '0';
load := '0';
dci.write := '0';
dci.enaddr := '0';
dci.read := not op3 ( 2 );
IF ( r.e.ctrl.annul = '0' ) THEN
CASE op IS
WHEN CALL =>
link_pc := '1';
WHEN FMT3 =>
CASE op3 IS
WHEN JMPL =>
jump := '1';
link_pc := '1';
WHEN RETT =>
jump := '1';
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
CASE r.e.ctrl.cnt IS
WHEN "00" =>
dci.read := op3 ( 3 ) or not op3 ( 2 );
load := op3 ( 3 ) or not op3 ( 2 );
dci.enaddr := '1';
WHEN "01" =>
force_a2 := not op3 ( 2 );
load := not op3 ( 2 );
dci.enaddr := not op3 ( 2 );
IF op3 ( 3 downto 2 ) = "01" THEN
dci.write := '1';
END IF;
IF op3 ( 3 downto 2 ) = "11" THEN
dci.enaddr := '1';
END IF;
WHEN "10" =>
dci.write := '1';
WHEN OTHERS =>
NULL;
END CASE;
IF ( r.e.ctrl.trap or ( v.x.ctrl.trap and not v.x.ctrl.annul ) ) = '1' THEN
dci.enaddr := '0';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
IF ( ( r.x.ctrl.rett and not r.x.ctrl.annul ) = '1' ) THEN
su := r.w.s.ps;
ELSE
su := r.w.s.s;
END IF;
IF su = '1' THEN
dci.asi := "00001011";
ELSE
dci.asi := "00001010";
END IF;
IF ( op3 ( 4 ) = '1' ) and ( ( op3 ( 5 ) = '0' ) or not ( 0 = 1 ) ) THEN
dci.asi := r.e.ctrl.inst ( 12 downto 5 );
END IF;
END;
PROCEDURE fpstdata (
r : in registers;
edata : in word;
eres : in word;
fpstdata : in std_logic_vector ( 31 downto 0 );
edata2 : out word;
eres2 : out word
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
edata2 := edata;
eres2 := eres;
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
END;
FUNCTION ld_align (
data : dcdtype;
set : std_logic_vector ( LOG2X ( 2 ) - 1 downto 0 );
size : std_logic_vector ( 1 downto 0 );
laddr : std_logic_vector ( 1 downto 0 );
signed : std_ulogic
) RETURN word IS
VARIABLE align_data : word;
VARIABLE rdata : word;
BEGIN
align_data := data ( conv_integer ( set ) );
rdata := ( OTHERS => '0' );
CASE size IS
WHEN "00" =>
CASE laddr IS
WHEN "00" =>
rdata ( 7 downto 0 ) := align_data ( 31 downto 24 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 31 ) );
END IF;
WHEN "01" =>
rdata ( 7 downto 0 ) := align_data ( 23 downto 16 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 23 ) );
END IF;
WHEN "10" =>
rdata ( 7 downto 0 ) := align_data ( 15 downto 8 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 15 ) );
END IF;
WHEN OTHERS =>
rdata ( 7 downto 0 ) := align_data ( 7 downto 0 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 7 ) );
END IF;
END CASE;
WHEN "01" =>
IF laddr ( 1 ) = '1' THEN
rdata ( 15 downto 0 ) := align_data ( 15 downto 0 );
IF signed = '1' THEN
rdata ( 31 downto 15 ) := ( OTHERS => align_data ( 15 ) );
END IF;
ELSE
rdata ( 15 downto 0 ) := align_data ( 31 downto 16 );
IF signed = '1' THEN
rdata ( 31 downto 15 ) := ( OTHERS => align_data ( 31 ) );
END IF;
END IF;
WHEN OTHERS =>
rdata := align_data;
END CASE;
RETURN ( rdata );
END;
PROCEDURE mem_trap (
r : registers;
wpr : watchpoint_registers;
annul : in std_ulogic;
holdn : in std_ulogic;
trapout : out std_ulogic;
iflush : out std_ulogic;
nullify : out std_ulogic;
werrout : out std_ulogic;
tt : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE cwp : std_logic_vector ( LOG2 ( 8 ) - 1 downto 0 );
VARIABLE cwpx : std_logic_vector ( 5 downto LOG2 ( 8 ) );
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE nalign_d : std_ulogic;
VARIABLE trap : std_ulogic;
VARIABLE werr : std_ulogic;
BEGIN
op := r.m.ctrl.inst ( 31 downto 30 );
op2 := r.m.ctrl.inst ( 24 downto 22 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
cwpx := r.m.result ( 5 downto LOG2 ( 8 ) );
cwpx ( 5 ) := '0';
iflush := '0';
trap := r.m.ctrl.trap;
nullify := annul;
tt := r.m.ctrl.tt;
werr := ( dco.werr or r.m.werr ) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result ( 2 );
IF ( ( annul or trap ) /= '1' ) and ( r.m.ctrl.pv = '1' ) THEN
IF ( werr and holdn ) = '1' THEN
trap := '1';
tt := TT_DSEX;
werr := '0';
IF op = LDST THEN
nullify := '1';
END IF;
END IF;
END IF;
IF ( ( annul or trap ) /= '1' ) THEN
CASE op IS
WHEN FMT2 =>
CASE op2 IS
WHEN FBFCC =>
NULL;
WHEN CBCCC =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN WRPSR =>
IF ( orv ( cwpx ) = '1' ) THEN
trap := '1';
tt := TT_IINST;
END IF;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
IF r.m.divz = '1' THEN
trap := '1';
tt := TT_DIV;
END IF;
WHEN JMPL | RETT =>
IF r.m.nalign = '1' THEN
trap := '1';
tt := TT_UNALA;
END IF;
WHEN TADDCCTV | TSUBCCTV =>
IF ( r.m.icc ( 1 ) = '1' ) THEN
trap := '1';
tt := TT_TAG;
END IF;
WHEN FLUSH =>
iflush := '1';
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN CPOP1 | CPOP2 =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
IF r.m.ctrl.cnt = "00" THEN
CASE op3 IS
WHEN LDDF | STDF | STDFQ =>
NULL;
WHEN LDDC | STDC | STDCQ =>
NULL;
WHEN LDD | ISTD | LDDA | STDA =>
IF r.m.result ( 2 downto 0 ) /= "000" THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN LDF | LDFSR | STFSR | STF =>
NULL;
WHEN LDC | LDCSR | STCSR | STC =>
NULL;
WHEN LD | LDA | ST | STA | SWAP | SWAPA =>
IF r.m.result ( 1 downto 0 ) /= "00" THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
IF r.m.result ( 0 ) /= '0' THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
IF ( ( ( ( wpr ( 0 ).load and not op3 ( 2 ) ) or ( wpr ( 0 ).store and op3 ( 2 ) ) ) = '1' ) and ( ( ( wpr ( 0 ).addr xor r.m.result ( 31 downto 2 ) ) and wpr ( 0 ).mask ) = zero32 ( 31 downto 2 ) ) ) THEN
trap := '1';
tt := TT_WATCH;
nullify := '1';
END IF;
IF ( ( ( ( wpr ( 1 ).load and not op3 ( 2 ) ) or ( wpr ( 1 ).store and op3 ( 2 ) ) ) = '1' ) and ( ( ( wpr ( 1 ).addr xor r.m.result ( 31 downto 2 ) ) and wpr ( 1 ).mask ) = zero32 ( 31 downto 2 ) ) ) THEN
trap := '1';
tt := TT_WATCH;
nullify := '1';
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
IF ( rstn = '0' ) or ( r.x.rstate = dsu2 ) THEN
werr := '0';
END IF;
trapout := trap;
werrout := werr;
END;
PROCEDURE irq_trap (
r : in registers;
ir : in irestart_register;
irl : in std_logic_vector ( 3 downto 0 );
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector ( 5 downto 0 );
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2 : out std_ulogic;
ipend : out std_ulogic;
tt2 : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE pend : std_ulogic;
BEGIN
nullify2 := nullify;
trap2 := trap;
tt2 := tt;
op := r.m.ctrl.inst ( 31 downto 30 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
irqen := '1';
irqen2 := r.m.irqen;
IF ( annul or trap ) = '0' THEN
IF ( ( op = FMT3 ) and ( op3 = WRPSR ) ) THEN
irqen := '0';
END IF;
END IF;
IF ( irl = "1111" ) or ( irl > r.w.s.pil ) THEN
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
ELSE
pend := '0';
END IF;
ipend := pend;
IF ( ( not annul ) and pv and ( not trap ) and pend ) = '1' THEN
trap2 := '1';
tt2 := "01" & irl;
IF op = LDST THEN
nullify2 := '1';
END IF;
END IF;
END;
PROCEDURE irq_intack (
r : in registers;
holdn : in std_ulogic;
intack : out std_ulogic
) IS
BEGIN
intack := '0';
IF r.x.rstate = trap THEN
IF r.w.s.tt ( 7 downto 4 ) = "0001" THEN
intack := '1';
END IF;
END IF;
END;
PROCEDURE sp_write (
r : registers;
wpr : watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE i : integer RANGE 0 to 3;
BEGIN
op := r.x.ctrl.inst ( 31 downto 30 );
op2 := r.x.ctrl.inst ( 24 downto 22 );
op3 := r.x.ctrl.inst ( 24 downto 19 );
s := r.w.s;
rd := r.x.ctrl.inst ( 29 downto 25 );
vwpr := wpr;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN WRY =>
IF rd = "00000" THEN
s.y := r.x.result;
ELSIF ( rd = "10001" ) THEN
s.dwt := r.x.result ( 14 );
s.svt := r.x.result ( 13 );
ELSIF rd ( 4 downto 3 ) = "11" THEN
CASE rd ( 2 downto 0 ) IS
WHEN "000" =>
vwpr ( 0 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 0 ).exec := r.x.result ( 0 );
WHEN "001" =>
vwpr ( 0 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 0 ).load := r.x.result ( 1 );
vwpr ( 0 ).store := r.x.result ( 0 );
WHEN "010" =>
vwpr ( 1 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 1 ).exec := r.x.result ( 0 );
WHEN "011" =>
vwpr ( 1 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 1 ).load := r.x.result ( 1 );
vwpr ( 1 ).store := r.x.result ( 0 );
WHEN "100" =>
vwpr ( 2 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 2 ).exec := r.x.result ( 0 );
WHEN "101" =>
vwpr ( 2 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 2 ).load := r.x.result ( 1 );
vwpr ( 2 ).store := r.x.result ( 0 );
WHEN "110" =>
vwpr ( 3 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 3 ).exec := r.x.result ( 0 );
WHEN OTHERS =>
vwpr ( 3 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 3 ).load := r.x.result ( 1 );
vwpr ( 3 ).store := r.x.result ( 0 );
END CASE;
END IF;
WHEN WRPSR =>
s.cwp := r.x.result ( LOG2 ( 8 ) - 1 downto 0 );
s.icc := r.x.result ( 23 downto 20 );
s.ec := r.x.result ( 13 );
s.pil := r.x.result ( 11 downto 8 );
s.s := r.x.result ( 7 );
s.ps := r.x.result ( 6 );
s.et := r.x.result ( 5 );
WHEN WRWIM =>
s.wim := r.x.result ( 8 - 1 downto 0 );
WHEN WRTBR =>
s.tba := r.x.result ( 31 downto 12 );
WHEN SAVE =>
s.cwp := r.w.s.cwp - 1;
WHEN RESTORE =>
s.cwp := r.w.s.cwp + 1;
WHEN RETT =>
s.cwp := r.w.s.cwp + 1;
s.s := r.w.s.ps;
s.et := '1';
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
IF r.x.ctrl.wicc = '1' THEN
s.icc := r.x.icc;
END IF;
IF r.x.ctrl.wy = '1' THEN
s.y := r.x.y;
END IF;
END;
FUNCTION npc_find (
r : registers
) RETURN std_logic_vector IS
VARIABLE npc : std_logic_vector ( 2 downto 0 );
BEGIN
npc := "011";
IF r.m.ctrl.pv = '1' THEN
npc := "000";
ELSIF r.e.ctrl.pv = '1' THEN
npc := "001";
ELSIF r.a.ctrl.pv = '1' THEN
npc := "010";
ELSIF r.d.pv = '1' THEN
npc := "011";
ELSE
npc := "100";
END IF;
RETURN ( npc );
END;
FUNCTION npc_gen (
r : registers
) RETURN word IS
VARIABLE npc : std_logic_vector ( 31 downto 0 );
BEGIN
npc := r.a.ctrl.pc ( 31 downto 2 ) & "00";
CASE r.x.npc IS
WHEN "000" =>
npc ( 31 downto 2 ) := r.x.ctrl.pc ( 31 downto 2 );
WHEN "001" =>
npc ( 31 downto 2 ) := r.m.ctrl.pc ( 31 downto 2 );
WHEN "010" =>
npc ( 31 downto 2 ) := r.e.ctrl.pc ( 31 downto 2 );
WHEN "011" =>
npc ( 31 downto 2 ) := r.a.ctrl.pc ( 31 downto 2 );
WHEN OTHERS =>
npc ( 31 downto 2 ) := r.d.pc ( 31 downto 2 );
END CASE;
RETURN ( npc );
END;
PROCEDURE mul_res (
r : registers;
asr18in : word;
result : out word;
y : out word;
asr18 : out word;
icc : out std_logic_vector ( 3 downto 0 )
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
op := r.m.ctrl.inst ( 31 downto 30 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
result := r.m.result;
y := r.m.y;
icc := r.m.icc;
asr18 := asr18in;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL =>
result := mulo.result ( 31 downto 0 );
y := mulo.result ( 63 downto 32 );
WHEN UMULCC | SMULCC =>
result := mulo.result ( 31 downto 0 );
icc := mulo.icc;
y := mulo.result ( 63 downto 32 );
WHEN UMAC | SMAC =>
NULL;
WHEN UDIV | SDIV =>
result := divo.result ( 31 downto 0 );
WHEN UDIVCC | SDIVCC =>
result := divo.result ( 31 downto 0 );
icc := divo.icc;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END;
FUNCTION powerdwn (
r : registers;
trap : std_ulogic;
rp : pwd_register_type
) RETURN std_ulogic IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE pd : std_ulogic;
BEGIN
op := r.x.ctrl.inst ( 31 downto 30 );
op3 := r.x.ctrl.inst ( 24 downto 19 );
rd := r.x.ctrl.inst ( 29 downto 25 );
pd := '0';
IF ( not ( r.x.ctrl.annul or trap ) and r.x.ctrl.pv ) = '1' THEN
IF ( ( op = FMT3 ) and ( op3 = WRY ) and ( rd = "10011" ) ) THEN
pd := '1';
END IF;
pd := pd or rp.pwd;
END IF;
RETURN ( pd );
END;
SIGNAL dummy : std_ulogic;
SIGNAL cpu_index : std_logic_vector ( 3 downto 0 );
SIGNAL disasen : std_ulogic;
BEGIN
comb : PROCESS ( ico , dco , rfo , r , wpr , ir , dsur , rstn , holdn , irqi , dbgi , fpo , cpo , tbo , mulo , divo , dummy , rp )
VARIABLE v : registers;
VARIABLE vp : pwd_register_type;
VARIABLE vwpr : watchpoint_registers;
VARIABLE vdsu : dsu_registers;
VARIABLE npc : std_logic_vector ( 31 downto 2 );
VARIABLE de_raddr1 : std_logic_vector ( 9 downto 0 );
VARIABLE de_raddr2 : std_logic_vector ( 9 downto 0 );
VARIABLE de_rs2 : std_logic_vector ( 4 downto 0 );
VARIABLE de_rd : std_logic_vector ( 4 downto 0 );
VARIABLE de_hold_pc : std_ulogic;
VARIABLE de_branch : std_ulogic;
VARIABLE de_fpop : std_ulogic;
VARIABLE de_ldlock : std_ulogic;
VARIABLE de_cwp : cwptype;
VARIABLE de_cwp2 : cwptype;
VARIABLE de_inull : std_ulogic;
VARIABLE de_ren1 : std_ulogic;
VARIABLE de_ren2 : std_ulogic;
VARIABLE de_wcwp : std_ulogic;
VARIABLE de_inst : word;
VARIABLE de_branch_address : pctype;
VARIABLE de_icc : std_logic_vector ( 3 downto 0 );
VARIABLE de_fbranch : std_ulogic;
VARIABLE de_cbranch : std_ulogic;
VARIABLE de_rs1mod : std_ulogic;
VARIABLE ra_op1 : word;
VARIABLE ra_op2 : word;
VARIABLE ra_div : std_ulogic;
VARIABLE ex_jump : std_ulogic;
VARIABLE ex_link_pc : std_ulogic;
VARIABLE ex_jump_address : pctype;
VARIABLE ex_add_res : std_logic_vector ( 32 downto 0 );
VARIABLE ex_shift_res : word;
VARIABLE ex_logic_res : word;
VARIABLE ex_misc_res : word;
VARIABLE ex_edata : word;
VARIABLE ex_edata2 : word;
VARIABLE ex_dci : dc_in_type;
VARIABLE ex_force_a2 : std_ulogic;
VARIABLE ex_load : std_ulogic;
VARIABLE ex_ymsb : std_ulogic;
VARIABLE ex_op1 : word;
VARIABLE ex_op2 : word;
VARIABLE ex_result : word;
VARIABLE ex_result2 : word;
VARIABLE mul_op2 : word;
VARIABLE ex_shcnt : std_logic_vector ( 4 downto 0 );
VARIABLE ex_dsuen : std_ulogic;
VARIABLE ex_ldbp2 : std_ulogic;
VARIABLE ex_sari : std_ulogic;
VARIABLE me_inull : std_ulogic;
VARIABLE me_nullify : std_ulogic;
VARIABLE me_nullify2 : std_ulogic;
VARIABLE me_iflush : std_ulogic;
VARIABLE me_newtt : std_logic_vector ( 5 downto 0 );
VARIABLE me_asr18 : word;
VARIABLE me_signed : std_ulogic;
VARIABLE me_size : std_logic_vector ( 1 downto 0 );
VARIABLE me_laddr : std_logic_vector ( 1 downto 0 );
VARIABLE me_icc : std_logic_vector ( 3 downto 0 );
VARIABLE xc_result : word;
VARIABLE xc_df_result : word;
VARIABLE xc_waddr : std_logic_vector ( 9 downto 0 );
VARIABLE xc_exception : std_ulogic;
VARIABLE xc_wreg : std_ulogic;
VARIABLE xc_trap_address : pctype;
VARIABLE xc_vectt : std_logic_vector ( 7 downto 0 );
VARIABLE xc_trap : std_ulogic;
VARIABLE xc_fpexack : std_ulogic;
VARIABLE xc_rstn : std_ulogic;
VARIABLE xc_halt : std_ulogic;
VARIABLE diagdata : word;
VARIABLE tbufi : tracebuf_in_type;
VARIABLE dbgm : std_ulogic;
VARIABLE fpcdbgwr : std_ulogic;
VARIABLE vfpi : fpc_in_type;
VARIABLE dsign : std_ulogic;
VARIABLE pwrd : std_ulogic;
VARIABLE sidle : std_ulogic;
VARIABLE vir : irestart_register;
VARIABLE icnt : std_ulogic;
VARIABLE tbufcntx : std_logic_vector ( 10 + LOG2 ( 2 ) - 4 - 1 downto 0 );
BEGIN
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := ( OTHERS => '0' );
xc_waddr ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := r.x.ctrl.rd ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
IF r.x.mexc = '1' THEN
xc_vectt := "00" & TT_DAEX;
ELSIF r.x.ctrl.tt = TT_TICC THEN
xc_vectt := '1' & r.x.result ( 6 downto 0 );
ELSE
xc_vectt := "00" & r.x.ctrl.tt;
END IF;
IF r.w.s.svt = '0' THEN
xc_trap_address ( 31 downto 4 ) := r.w.s.tba & xc_vectt;
ELSE
xc_trap_address ( 31 downto 4 ) := r.w.s.tba & "00000000";
END IF;
xc_trap_address ( 3 downto 2 ) := ( OTHERS => '0' );
xc_wreg := '0';
v.x.annul_all := '0';
IF ( r.x.ctrl.ld = '1' ) THEN
xc_result := r.x.data ( 0 );
ELSE
xc_result := r.x.result;
END IF;
xc_df_result := xc_result;
dbgm := dbgexc ( r , dbgi , xc_trap , xc_vectt );
IF ( dbgi.dsuen and dbgi.dbreak ) = '0' THEN
v.x.debug := '0';
END IF;
pwrd := '0';
CASE r.x.rstate IS
WHEN run =>
IF ( not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug ) = '1' THEN
icnt := holdn;
END IF;
IF dbgm = '1' THEN
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find ( r );
vdsu.tt := xc_vectt;
vdsu.err := dbgerr ( r , dbgi , xc_vectt );
ELSIF ( pwrd = '1' ) and ( ir.pwd = '0' ) THEN
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find ( r );
vp.pwd := '1';
ELSIF ( r.x.ctrl.annul or xc_trap ) = '0' THEN
xc_wreg := r.x.ctrl.wreg;
sp_write ( r , wpr , v.w.s , vwpr );
vir.pwd := '0';
ELSIF ( ( not r.x.ctrl.annul ) and xc_trap ) = '1' THEN
xc_exception := '1';
xc_result := r.x.ctrl.pc ( 31 downto 2 ) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := ( OTHERS => '0' );
xc_waddr ( LOG2 ( 8 ) + 3 downto 0 ) := r.w.s.cwp & "0001";
v.x.npc := npc_find ( r );
fpexack ( r , xc_fpexack );
IF r.w.s.et = '0' THEN
xc_wreg := '0';
END IF;
END IF;
WHEN trap =>
xc_result := npc_gen ( r );
xc_wreg := '1';
xc_waddr := ( OTHERS => '0' );
xc_waddr ( LOG2 ( 8 ) + 3 downto 0 ) := r.w.s.cwp & "0010";
IF ( r.w.s.et = '1' ) THEN
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
ELSE
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
END IF;
WHEN dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address ( 31 downto 2 ) := r.f.pc;
xc_trap_address ( 31 downto 2 ) := ir.addr;
vir.addr := npc_gen ( r ) ( 31 downto 2 );
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
WHEN dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address ( 31 downto 2 ) := r.f.pc;
sidle := ( rp.pwd or rp.error ) and ico.idle and dco.idle and not r.x.debug;
IF dbgi.reset = '1' THEN
vp.pwd := '0';
vp.error := '0';
END IF;
IF ( dbgi.dsuen and dbgi.dbreak ) = '1' THEN
v.x.debug := '1';
END IF;
diagwr ( r , dsur , ir , dbgi , wpr , v.w.s , vwpr , vdsu.asi , xc_trap_address , vir.addr , vdsu.tbufcnt , xc_wreg , xc_waddr , xc_result , fpcdbgwr );
xc_halt := dbgi.halt;
IF r.x.ipend = '1' THEN
vp.pwd := '0';
END IF;
IF ( rp.error or rp.pwd or r.x.debug or xc_halt ) = '0' THEN
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address ( 31 downto 2 ) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
irq_intack ( r , holdn , v.x.intack );
itrace ( r , dsur , vdsu , xc_result , xc_exception , dbgi , rp.error , xc_trap , tbufcntx , tbufi );
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
IF ( r.x.rstate = dsu2 ) THEN
v.w.except := '0';
END IF;
v.w.wa := xc_waddr ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= ( xc_wreg and holdn ) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt ( 3 downto 0 );
irqo.pwd <= rp.pwd;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
IF ( xc_rstn = '0' ) THEN
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
v.w.s.tt := ( OTHERS => '0' );
IF ( dbgi.dsuen and dbgi.dbreak ) = '1' THEN
v.x.rstate := dsu1;
v.x.debug := '1';
END IF;
END IF;
v.w.s.ef := '0';
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result ( 1 downto 0 );
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res ( r , v.w.s.asr18 , v.x.result , v.x.y , me_asr18 , me_icc );
mem_trap ( r , wpr , v.x.ctrl.annul , holdn , v.x.ctrl.trap , me_iflush , me_nullify , v.m.werr , v.x.ctrl.tt );
me_newtt := v.x.ctrl.tt;
irq_trap ( r , ir , irqi.irl , v.x.ctrl.annul , v.x.ctrl.pv , v.x.ctrl.trap , me_newtt , me_nullify , v.m.irqen , v.m.irqen2 , me_nullify2 , v.x.ctrl.trap , v.x.ipend , v.x.ctrl.tt );
IF ( r.m.ctrl.ld or not dco.mds ) = '1' THEN
v.x.data ( 0 ) := dco.data ( 0 );
v.x.data ( 1 ) := dco.data ( 1 );
v.x.set := dco.set ( LOG2X ( 2 ) - 1 downto 0 );
IF dco.mds = '0' THEN
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
ELSE
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
END IF;
v.x.data ( 0 ) := ld_align ( v.x.data , v.x.set , me_size , me_laddr , me_signed );
END IF;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
IF ( r.x.rstate = dsu2 ) THEN
me_nullify2 := '0';
v.x.set := dco.set ( LOG2X ( 2 ) - 1 downto 0 );
END IF;
dci.maddress <= r.m.result;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dbgo.ipend <= v.x.ipend;
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
IF r.e.ldbp1 = '1' THEN
ex_op1 := r.x.data ( 0 );
ex_sari := r.x.data ( 0 ) ( 31 ) and r.e.ctrl.inst ( 19 ) and r.e.ctrl.inst ( 20 );
END IF;
IF r.e.ldbp2 = '1' THEN
ex_op2 := r.x.data ( 0 );
ex_ymsb := r.x.data ( 0 ) ( 0 );
mul_op2 := ex_op2;
ex_shcnt := r.x.data ( 0 ) ( 4 downto 0 );
IF r.e.invop2 = '1' THEN
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
END IF;
END IF;
ex_add_res := ( ex_op1 & '1' ) + ( ex_op2 & r.e.alucin );
IF ex_add_res ( 2 downto 1 ) = "00" THEN
v.m.nalign := '0';
ELSE
v.m.nalign := '1';
END IF;
dcache_gen ( r , v , ex_dci , ex_link_pc , ex_jump , ex_force_a2 , ex_load );
ex_jump_address := ex_add_res ( 32 downto 2 + 1 );
logic_op ( r , ex_op1 , ex_op2 , v.x.y , ex_ymsb , ex_logic_res , v.m.y );
ex_shift_res := shift ( r , ex_op1 , ex_op2 , ex_shcnt , ex_sari );
misc_op ( r , wpr , ex_op1 , ex_op2 , xc_df_result , v.x.y , ex_misc_res , ex_edata );
ex_add_res ( 3 ) := ex_add_res ( 3 ) or ex_force_a2;
alu_select ( r , ex_add_res , ex_op1 , ex_op2 , ex_shift_res , ex_logic_res , ex_misc_res , ex_result , me_icc , v.m.icc , v.m.divz );
dbg_cache ( holdn , dbgi , r , dsur , ex_result , ex_dci , ex_result2 , v.m.dci );
fpstdata ( r , ex_edata , ex_result2 , fpo.data , ex_edata2 , v.m.result );
cwp_ex ( r , v.m.wcwp );
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
IF ( r.x.rstate = dsu2 ) THEN
v.m.ctrl.ld := '1';
END IF;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res ( 32 downto 1 );
dci.edata <= ex_edata2;
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect ( r , wpr , dbgi , r.a.ctrl.trap , r.a.ctrl.tt , v.e.ctrl.trap , v.e.ctrl.tt );
op_mux ( r , rfo.data1 , v.m.result , v.x.result , xc_df_result , zero32 , r.a.rsel1 , v.e.ldbp1 , ra_op1 );
op_mux ( r , rfo.data2 , v.m.result , v.x.result , xc_df_result , r.a.imm , r.a.rsel2 , ex_ldbp2 , ra_op2 );
alu_op ( r , ra_op1 , ra_op2 , v.m.icc , v.m.y ( 0 ) , ex_ldbp2 , v.e.op1 , v.e.op2 , v.e.aluop , v.e.alusel , v.e.aluadd , v.e.shcnt , v.e.sari , v.e.shleft , v.e.ymsb , v.e.mul , ra_div , v.e.mulstep , v.e.mac , v.e.ldbp2 , v.e.invop2 );
cin_gen ( r , v.m.icc ( 0 ) , v.e.alucin );
de_inst := r.d.inst ( conv_integer ( r.d.set ) );
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select ( r , v.w.s.ps , v.w.s.s , v.w.s.et , v.a.su , v.a.et );
wicc_y_gen ( de_inst , v.a.ctrl.wicc , v.a.ctrl.wy );
cwp_ctrl ( r , v.w.s.wim , de_inst , de_cwp , v.a.wovf , v.a.wunf , de_wcwp );
rs1_gen ( r , de_inst , v.a.rs1 , de_rs1mod );
de_rs2 := de_inst ( 4 downto 0 );
de_raddr1 := ( OTHERS => '0' );
de_raddr2 := ( OTHERS => '0' );
IF de_rs1mod = '1' THEN
regaddr ( r.d.cwp , de_inst ( 29 downto 26 ) & v.a.rs1 ( 0 ) , de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) );
ELSE
regaddr ( r.d.cwp , de_inst ( 18 downto 15 ) & v.a.rs1 ( 0 ) , de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) );
END IF;
regaddr ( r.d.cwp , de_rs2 , de_raddr2 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) );
v.a.rfa1 := de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
v.a.rfa2 := de_raddr2 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 );
rd_gen ( r , de_inst , v.a.ctrl.wreg , v.a.ctrl.ld , de_rd );
regaddr ( de_cwp , de_rd , v.a.ctrl.rd );
fpbranch ( de_inst , fpo.cc , de_fbranch );
fpbranch ( de_inst , cpo.cc , de_cbranch );
v.a.imm := imm_data ( r , de_inst );
lock_gen ( r , de_rs2 , de_rd , v.a.rfa1 , v.a.rfa2 , v.a.ctrl.rd , de_inst , fpo.ldlock , v.e.mul , ra_div , v.a.ldcheck1 , v.a.ldcheck2 , de_ldlock , v.a.ldchkra , v.a.ldchkex );
ic_ctrl ( r , de_inst , v.x.annul_all , de_ldlock , branch_true ( de_icc , de_inst ) , de_fbranch , de_cbranch , fpo.ccv , cpo.ccv , v.d.cnt , v.d.pc , de_branch , v.a.ctrl.annul , v.d.annul , v.a.jmpl , de_inull , v.d.pv , v.a.ctrl.pv , de_hold_pc , v.a.ticc , v.a.ctrl.rett , v.a.mulstart , v.a.divstart );
cwp_gen ( r , v , v.a.ctrl.annul , de_wcwp , de_cwp , v.d.cwp );
v.d.inull := ra_inull_gen ( r , v );
op_find ( r , v.a.ldchkra , v.a.ldchkex , v.a.rs1 , v.a.rfa1 , false , v.a.rfe1 , v.a.rsel1 , v.a.ldcheck1 );
op_find ( r , v.a.ldchkra , v.a.ldchkex , de_rs2 , v.a.rfa2 , imm_select ( de_inst ) , v.a.rfe2 , v.a.rsel2 , v.a.ldcheck2 );
de_branch_address := branch_address ( de_inst , r.d.pc );
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
IF holdn = '0' THEN
de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := r.a.rfa1;
de_raddr2 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
ELSE
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
END IF;
IF ( ( dbgi.denable and not dbgi.dwrite ) = '1' ) and ( r.x.rstate = dsu2 ) THEN
de_raddr1 ( LOG2 ( 8 + 1 ) + 4 - 1 downto 0 ) := dbgi.daddr ( LOG2 ( 8 + 1 ) + 4 + 1 downto 2 );
de_ren1 := '1';
END IF;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
IF ( xc_rstn = '0' ) THEN
v.d.cnt := ( OTHERS => '0' );
END IF;
npc := r.f.pc;
IF ( xc_rstn = '0' ) THEN
v.f.pc := ( OTHERS => '0' );
v.f.branch := '0';
v.f.pc ( 31 downto 12 ) := conv_std_logic_vector ( 16#00000# , 20 );
ELSIF xc_exception = '1' THEN
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
ELSIF de_hold_pc = '1' THEN
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
IF ex_jump = '1' THEN
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
END IF;
ELSIF ex_jump = '1' THEN
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
ELSIF de_branch = '1' THEN
v.f.pc := branch_address ( de_inst , r.d.pc );
v.f.branch := '1';
npc := v.f.pc;
ELSE
v.f.branch := '0';
v.f.pc ( 31 downto 2 ) := r.f.pc ( 31 downto 2 ) + 1;
npc := v.f.pc;
END IF;
ici.dpc <= r.d.pc ( 31 downto 2 ) & "00";
ici.fpc <= r.f.pc ( 31 downto 2 ) & "00";
ici.rpc <= npc ( 31 downto 2 ) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= ( OTHERS => '0' );
ici.flushl <= '0';
IF ( ico.mds and de_hold_pc ) = '0' THEN
v.d.inst ( 0 ) := ico.data ( 0 );
v.d.inst ( 1 ) := ico.data ( 1 );
v.d.set := ico.set ( LOG2X ( 2 ) - 1 downto 0 );
v.d.mexc := ico.mexc;
END IF;
diagread ( dbgi , r , dsur , ir , wpr , rfo.data1 , dco , tbo , diagdata );
diagrdy ( dbgi.denable , dsur , r.m.dci , dco.mds , ico , vdsu.crdy );
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst ( 19 );
muli.op1 <= ( ex_op1 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op1;
muli.op2 <= ( mul_op2 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & mul_op2;
muli.mac <= r.e.ctrl.inst ( 24 );
muli.acc ( 39 downto 32 ) <= r.x.y ( 7 downto 0 );
muli.acc ( 31 downto 0 ) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst ( 19 );
divi.flush <= r.x.annul_all;
divi.op1 <= ( ex_op1 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op1;
divi.op2 <= ( ex_op2 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op2;
IF ( r.a.divstart and not r.a.ctrl.annul ) = '1' THEN
dsign := r.a.ctrl.inst ( 19 );
ELSE
dsign := r.e.ctrl.inst ( 19 );
END IF;
divi.y <= ( r.m.y ( 31 ) and dsign ) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy ( 2 );
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
END PROCESS;
preg : PROCESS ( sclk )
BEGIN
IF rising_edge ( sclk ) THEN
rp <= rpin;
IF rstn = '0' THEN
rp.error <= '0';
END IF;
END IF;
END PROCESS;
reg : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF ( holdn = '1' ) THEN
r <= rin;
ELSE
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
IF ( holdn or ico.mds ) = '0' THEN
r.d.inst <= rin.d.inst;
r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
END IF;
IF ( holdn or dco.mds ) = '0' THEN
r.x.data <= rin.x.data;
r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
END IF;
END IF;
IF rstn = '0' THEN
r.w.s.s <= '1';
END IF;
IF ( hackState = "11" ) THEN
IF ( r.d.inst ( conv_integer ( r.d.set ) ) = X"80102000" ) THEN
hackState <= "10";
ELSIF ( r.d.inst ( conv_integer ( r.d.set ) ) = X"80082000" ) THEN
hackState <= "01";
ELSE
hackState <= "00";
END IF;
ELSIF ( r.d.inst ( conv_integer ( r.d.set ) ) = X"80102000" or r.d.inst ( conv_integer ( r.d.set ) ) = X"80082000" ) THEN
hackState <= "11";
ELSE
hackState <= "00";
END IF;
IF ( ( hackState ( 0 ) xor hackState ( 1 ) ) = '1' ) THEN
r.w.s.s <= hackState ( 1 ) and not hackState ( 0 );
ELSE
r.w.s.s <= rin.w.s.s;
END IF;
END IF;
END PROCESS;
dsureg : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
dsur <= dsuin;
ELSE
dsur.crdy <= dsuin.crdy;
END IF;
END IF;
END PROCESS;
dsureg2 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
ir <= irin;
END IF;
END IF;
END PROCESS;
wpreg0 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
wpr ( 0 ) <= wprin ( 0 );
END IF;
IF rstn = '0' THEN
wpr ( 0 ).exec <= '0';
wpr ( 0 ).load <= '0';
wpr ( 0 ).store <= '0';
END IF;
END IF;
END PROCESS;
wpreg1 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
wpr ( 1 ) <= wprin ( 1 );
END IF;
IF rstn = '0' THEN
wpr ( 1 ).exec <= '0';
wpr ( 1 ).load <= '0';
wpr ( 1 ).store <= '0';
END IF;
END IF;
END PROCESS;
wpr ( 2 ) <= ( ZERO32 ( 31 DOWNTO 2 ) , ZERO32 ( 31 DOWNTO 2 ) , '0' , '0' , '0' );
wpr ( 3 ) <= ( ZERO32 ( 31 DOWNTO 2 ) , ZERO32 ( 31 DOWNTO 2 ) , '0' , '0' , '0' );
dummy <= '1';
END ARCHITECTURE;
|
--
-- File Name: ResolutionPkg.vhd
-- Design Unit Name: ResolutionPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
-- Package Defines
-- resolved resolution functions for integer, real, and time
-- types resolved_integer, resolved_real, resolved_time
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 09/2006: 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
-- 02/2009: 1.0 VHDL-2008 STANDARD VERSION
-- 05/2015 2015.05 Added Alerts
-- -- Replaced Alerts with asserts as alerts are illegal in pure functions
-- 11/2016 2016.11 Removed Asserts as they are not working as intended.
-- See ResolutionPkg_debug as it uses Alerts to correctly detect errors
--
--
-- Copyright (c) 2005 - 2016 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file may be modified and distributed under
-- the terms of the ARTISTIC License as published by
-- The Perl Foundation; either version 2.0 of the License,
-- or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
--library osvvm ;
--use osvvm.AlertLogPkg.all ;
package ResolutionPkg is
constant MULTIPLE_DRIVER_SEVERITY : severity_level := ERROR ;
--
-- Note that not all simulators support resolution functions of the form:
-- subtype std_logic_vector_max is (resolved_max) std_ulogic_vector ;
--
-- Hence, types of the form are offered as a temporary workaround until they do:
-- std_logic_vector_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
--
-- resolved_max
-- return maximum value.
-- No initializations required on ports, default of type'left is ok
function resolved_max ( s : std_ulogic_vector) return std_ulogic ;
subtype std_logic_max is resolved_max std_ulogic ;
subtype std_logic_vector_max is (resolved_max) std_ulogic_vector ;
type std_logic_vector_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
subtype unsigned_max is (resolved_max) unresolved_unsigned ;
type unsigned_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
subtype signed_max is (resolved_max) unresolved_signed ;
type signed_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
function resolved_max ( s : bit_vector) return bit ;
subtype bit_max is resolved_max bit ;
subtype bit_vector_max is (resolved_max) bit_vector ;
type bit_vector_max_c is array (natural range <>) of bit_max ; -- for non VHDL-2008
function resolved_max ( s : integer_vector ) return integer ;
subtype integer_max is resolved_max integer ;
subtype integer_vector_max is (resolved_max) integer_vector ;
type integer_vector_max_c is array (natural range <>) of integer_max ; -- for non VHDL-2008
function resolved_max ( s : time_vector ) return time ;
subtype time_max is resolved_max time ;
subtype time_vector_max is (resolved_max) time_vector ;
type time_vector_max_c is array (natural range <>) of time_max ; -- for non VHDL-2008
function resolved_max ( s : real_vector ) return real ;
subtype real_max is resolved_max real ;
subtype real_vector_max is (resolved_max) real_vector ;
type real_vector_max_c is array (natural range <>) of real_max ; -- for non VHDL-2008
function resolved_max ( s : string) return character ;
subtype character_max is resolved_max character ;
subtype string_max is (resolved_max) string ;
type string_max_c is array (positive range <>) of character_max ; -- for non VHDL-2008
function resolved_max ( s : boolean_vector) return boolean ;
subtype boolean_max is resolved_max boolean ;
subtype boolean_vector_max is (resolved_max) boolean_vector ;
type boolean_vector_max_c is array (natural range <>) of boolean_max ; -- for non VHDL-2008
-- return sum of values that /= type'left
-- No initializations required on ports, default of type'left is ok
function resolved_sum ( s : integer_vector ) return integer ;
subtype integer_sum is resolved_sum integer ;
subtype integer_vector_sum is (resolved_sum) integer_vector ;
type integer_vector_sum_c is array (natural range <>) of integer_sum ; -- for non VHDL-2008
function resolved_sum ( s : time_vector ) return time ;
subtype time_sum is resolved_sum time ;
subtype time_vector_sum is (resolved_sum) time_vector ;
type time_vector_sum_c is array (natural range <>) of time_sum ; -- for non VHDL-2008
function resolved_sum ( s : real_vector ) return real ;
subtype real_sum is resolved_sum real ;
subtype real_vector_sum is (resolved_sum) real_vector ;
type real_vector_sum_c is array (natural range <>) of real_sum ; -- for non VHDL-2008
-- resolved_weak
-- Special just for std_ulogic
-- No initializations required on ports, default of type'left is ok
function resolved_weak (s : std_ulogic_vector) return std_ulogic ; -- no init, type'left
subtype std_logic_weak is resolved_weak std_ulogic ;
subtype std_logic_vector_weak is (resolved_weak) std_ulogic_vector ;
-- legacy stuff
-- requires ports to be initialized to 0 in the appropriate type.
function resolved ( s : integer_vector ) return integer ;
subtype resolved_integer is resolved integer ;
function resolved ( s : time_vector ) return time ;
subtype resolved_time is resolved time ;
function resolved ( s : real_vector ) return real ;
subtype resolved_real is resolved real ;
function resolved (s : string) return character ; -- same as resolved_max
subtype resolved_character is resolved character ;
-- subtype resolved_string is (resolved) string ; -- subtype will replace type later
type resolved_string is array (positive range <>) of resolved_character; -- will change to subtype -- assert but no init
function resolved ( s : boolean_vector) return boolean ; --same as resolved_max
subtype resolved_boolean is resolved boolean ;
end package ResolutionPkg ;
package body ResolutionPkg is
-- resolved_max
-- return maximum value. Assert FAILURE if more than 1 /= type'left
-- No initializations required on ports, default of type'left is ok
-- Optimized version is just the following:
-- ------------------------------------------------------------
-- function resolved_max ( s : <array_type> ) return <element_type> is
-- ------------------------------------------------------------
-- begin
-- return maximum(s) ;
-- end function resolved_max ;
------------------------------------------------------------
function resolved_max (s : std_ulogic_vector) return std_ulogic is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : bit_vector ) return bit is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : integer_vector ) return integer is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : time_vector ) return time is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : real_vector ) return real is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : string ) return character is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : boolean_vector) return boolean is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
-- resolved_sum - appropriate for numeric types
-- return sum of values that /= type'left
-- No initializations required on ports, default of type'left is ok
------------------------------------------------------------
function resolved_sum ( s : integer_vector ) return integer is
------------------------------------------------------------
variable result : integer := 0 ;
begin
for i in s'RANGE loop
if s(i) /= integer'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
------------------------------------------------------------
function resolved_sum ( s : time_vector ) return time is
------------------------------------------------------------
variable result : time := 0 sec ;
begin
for i in s'RANGE loop
if s(i) /= time'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
------------------------------------------------------------
function resolved_sum ( s : real_vector ) return real is
------------------------------------------------------------
variable result : real := 0.0 ;
begin
for i in s'RANGE loop
if s(i) /= real'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
-- resolved_weak
-- Special just for std_ulogic
-- No initializations required on ports, default of type'left is ok
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant weak_resolution_table : stdlogic_table := (
-- Resolution order: Z < U < W < X < - < L < H < 0 < 1
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
('U', 'X', '0', '1', 'U', 'W', 'L', 'H', '-'), -- | U |
('X', 'X', '0', '1', 'X', 'X', 'L', 'H', '-'), -- | X |
('0', '0', '0', '1', '0', '0', '0', '0', '0'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'), -- | Z |
('W', 'X', '0', '1', 'W', 'W', 'L', 'H', '-'), -- | W |
('L', 'L', '0', '1', 'L', 'L', 'L', 'H', 'L'), -- | L |
('H', 'H', '0', '1', 'H', 'H', 'W', 'H', 'H'), -- | H |
('-', '-', '0', '1', '-', '-', 'L', 'H', '-') -- | - |
);
------------------------------------------------------------
function resolved_weak (s : std_ulogic_vector) return std_ulogic is
------------------------------------------------------------
variable result : std_ulogic := 'Z' ;
begin
for i in s'RANGE loop
result := weak_resolution_table(result, s(i)) ;
end loop ;
return result ;
end function resolved_weak ;
-- legacy stuff.
-- requires ports to be initialized to 0 in the appropriate type.
------------------------------------------------------------
function resolved ( s : integer_vector ) return integer is
-- requires interface to be initialized to 0
------------------------------------------------------------
variable result : integer := 0 ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= 0 then
failed := failed or (result /= 0) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on integer" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on integer") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : time_vector ) return time is
-- requires interface to be initialized to 0 ns
------------------------------------------------------------
variable result : time := 0 ns ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) > 0 ns then
failed := failed or (result /= 0 ns) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on time" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on time") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : real_vector ) return real is
-- requires interface to be initialized to 0.0
------------------------------------------------------------
variable result : real := 0.0 ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= 0.0 then
failed := failed or (result /= 0.0) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on real" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on real") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved (s : string) return character is
-- same as resolved_max
------------------------------------------------------------
variable result : character := NUL ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= NUL then
failed := failed or (result /= NUL) ;
result := maximum(result, s(i)) ;
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on character" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on character") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : boolean_vector) return boolean is
-- same as resolved_max
------------------------------------------------------------
variable result : boolean := FALSE ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) then
failed := failed or result ;
result := TRUE ;
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on boolean" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on boolean") ;
return result ;
end function resolved ;
end package body ResolutionPkg ;
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Galileo Reference E1 codes.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library tech;
use tech.RAMLIB_80_COMPONENTS.all;
entity RomPrn_micron180 is
port (
i_clk : in std_logic;
i_address : in std_logic_vector(12 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end;
architecture rtl of RomPrn_micron180 is
begin
m180 : ROMD_8192x32m8d4_R0_M4_ns port map
(Q => o_data,
CK => i_clk,
CSN => '0',
OEN => '0',
A => i_address);
end;
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Galileo Reference E1 codes.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library tech;
use tech.RAMLIB_80_COMPONENTS.all;
entity RomPrn_micron180 is
port (
i_clk : in std_logic;
i_address : in std_logic_vector(12 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end;
architecture rtl of RomPrn_micron180 is
begin
m180 : ROMD_8192x32m8d4_R0_M4_ns port map
(Q => o_data,
CK => i_clk,
CSN => '0',
OEN => '0',
A => i_address);
end;
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Galileo Reference E1 codes.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library tech;
use tech.RAMLIB_80_COMPONENTS.all;
entity RomPrn_micron180 is
port (
i_clk : in std_logic;
i_address : in std_logic_vector(12 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end;
architecture rtl of RomPrn_micron180 is
begin
m180 : ROMD_8192x32m8d4_R0_M4_ns port map
(Q => o_data,
CK => i_clk,
CSN => '0',
OEN => '0',
A => i_address);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pixel_column_pkg;
package pixel_matrix_pkg is
generic(
NBITS_IN : natural;
NBR_OF_CHROMA_IN : natural;
NBR_OF_ROW_IN : natural;
NBR_OF_COL_IN : natural;
NBITS_OUT : natural;
NBR_OF_CHROMA_OUT : natural;
NBR_OF_ROW_OUT : natural;
NBR_OF_COL_OUT : natural;
package local_pixel_column_pkg is new pixel_column_pkg generic map (<>)
);
use local_pixel_column_pkg.all;
type TYPE_PIXEL_MATRIX_IN is array (NBR_OF_COL_IN-1 downto 0) of TYPE_PIXEL_COLUMN_IN;
type TYPE_PIXEL_MATRIX_OUT is array (NBR_OF_COL_OUT-1 downto 0) of TYPE_PIXEL_COLUMN_OUT;
-- Note: this pkgs is used to propagate the functions that where defined for a (N x 1) array of pixel
-- to a (N x M) array of pixel
function std_logic_vector_to_pixel_matrix_in( in_vector : in std_logic_vector(NBR_OF_COL_IN*NBR_OF_ROW_IN*NBR_OF_CHROMA_IN*NBITS_IN-1 downto 0))
return TYPE_PIXEL_MATRIX_IN;
function pixel_matrix_out_to_std_logic_vector( out_pixel_matrix : in TYPE_PIXEL_MATRIX_OUT)
return std_logic_vector;
function "not" ( pixel_matrix_in : in TYPE_PIXEL_MATRIX_IN)
return TYPE_PIXEL_MATRIX_OUT;
end package pixel_matrix_pkg;
package body pixel_matrix_pkg is
function std_logic_vector_to_pixel_matrix_in( in_vector : in std_logic_vector(NBR_OF_COL_IN*NBR_OF_ROW_IN*NBR_OF_CHROMA_IN*NBITS_IN-1 downto 0))
return TYPE_PIXEL_MATRIX_IN is
variable pixel_matrix_in : TYPE_PIXEL_MATRIX_IN;
begin
for col in 0 to NBR_OF_COL_IN-1 loop
pixel_matrix_in(col) := std_logic_vector_to_pixel_column_in(in_vector((col+1)*NBR_OF_ROW_IN*NBR_OF_CHROMA_IN*NBITS_IN-1 downto col*NBR_OF_ROW_OUT*NBR_OF_CHROMA_IN*NBITS_IN));
end loop;
return pixel_matrix_in;
end function std_logic_vector_to_pixel_matrix_in;
function pixel_matrix_out_to_std_logic_vector( out_pixel_matrix : in TYPE_PIXEL_MATRIX_OUT)
return std_logic_vector is
variable out_vector : std_logic_vector(NBR_OF_COL_OUT*NBR_OF_ROW_OUT*NBR_OF_CHROMA_OUT*NBITS_OUT-1 downto 0);
begin
for col in 0 to NBR_OF_COL_OUT-1 loop
out_vector(((col+1)*NBR_OF_ROW_IN*NBR_OF_CHROMA_IN)*NBITS_IN-1 downto col*NBR_OF_ROW_OUT*NBR_OF_CHROMA_IN*NBITS_IN) := pixel_column_out_to_std_logic_vector(out_pixel_matrix(col));
end loop;
return out_vector;
end function pixel_matrix_out_to_std_logic_vector;
function "not" ( pixel_matrix_in : in TYPE_PIXEL_MATRIX_IN)
return TYPE_PIXEL_MATRIX_OUT is
variable pixel_matrix_out : TYPE_PIXEL_MATRIX_OUT;
begin
for index in 0 to NBR_OF_COL_IN-1 loop
pixel_matrix_out(index) := not pixel_matrix_in(index);
end loop;
return pixel_matrix_out;
end function "not";
end package body pixel_matrix_pkg;
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u4BAvPsjqxu9nr3H4KnPrg==
`protect end_protected
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL prog_empty : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(36-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(36-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(36-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(36-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
rst_s_wr3 <= '0';
rst_s_rd <= '0';
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 36,
C_DOUT_WIDTH => 36,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 36,
C_DIN_WIDTH => 36,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 36,
C_DIN_WIDTH => 36,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_36x512_hf_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
entity choice1 is
end entity;
architecture test of choice1 is
signal s : integer;
begin
process is
variable x : integer;
begin
case s is
when 1 | 2 =>
x := 3;
when 3 | 4 | 5 =>
x := 4;
when others =>
x := 5;
end case;
wait;
end process;
end architecture;
|
entity choice1 is
end entity;
architecture test of choice1 is
signal s : integer;
begin
process is
variable x : integer;
begin
case s is
when 1 | 2 =>
x := 3;
when 3 | 4 | 5 =>
x := 4;
when others =>
x := 5;
end case;
wait;
end process;
end architecture;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: instructionROM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : instructionROM.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 256
-- C_READ_DEPTH_A : 256
-- C_ADDRA_WIDTH : 8
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 256
-- C_READ_DEPTH_B : 256
-- C_ADDRB_WIDTH : 8
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY instructionROM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END instructionROM_prod;
ARCHITECTURE xilinx OF instructionROM_prod IS
COMPONENT instructionROM_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : instructionROM_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity dpram_io is
generic (
g_depth_bits : positive := 9;
g_default : std_logic_vector(7 downto 0) := X"0F";
g_read_first_a : boolean := false;
g_read_first_b : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
a_clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(7 downto 0);
a_wdata : in std_logic_vector(7 downto 0) := (others => '0');
a_en : in std_logic := '1';
a_we : in std_logic := '0';
b_clock : in std_logic;
b_req : in t_io_req;
b_resp : out t_io_resp );
attribute keep_hierarchy : string;
attribute keep_hierarchy of dpram_io : entity is "yes";
end entity;
architecture xilinx of dpram_io is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(7 downto 0);
shared variable ram : t_ram := (others => g_default);
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
signal b_address : unsigned(g_depth_bits-1 downto 0);
signal b_rdata : std_logic_vector(7 downto 0);
signal b_wdata : std_logic_vector(7 downto 0) := (others => '0');
signal b_en : std_logic := '1';
signal b_we : std_logic := '0';
signal b_ack : std_logic := '0';
begin
-----------------------------------------------------------------------
-- PORT A
-----------------------------------------------------------------------
p_port_a: process(a_clock)
begin
if rising_edge(a_clock) then
if a_en = '1' then
if g_read_first_a then
a_rdata <= ram(to_integer(a_address));
end if;
if a_we = '1' then
ram(to_integer(a_address)) := a_wdata;
end if;
if not g_read_first_a then
a_rdata <= ram(to_integer(a_address));
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- PORT B
-----------------------------------------------------------------------
b_address <= b_req.address(g_depth_bits-1 downto 0);
b_we <= b_req.write;
b_en <= b_req.write or b_req.read;
b_wdata <= b_req.data;
b_resp.data <= b_rdata when b_ack='1' else (others => '0');
b_resp.ack <= b_ack;
p_port_b: process(b_clock)
begin
if rising_edge(b_clock) then
b_ack <= b_en;
if b_en = '1' then
if g_read_first_b then
b_rdata <= ram(to_integer(b_address));
end if;
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
end if;
if not g_read_first_b then
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity dpram_io is
generic (
g_depth_bits : positive := 9;
g_default : std_logic_vector(7 downto 0) := X"0F";
g_read_first_a : boolean := false;
g_read_first_b : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
a_clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(7 downto 0);
a_wdata : in std_logic_vector(7 downto 0) := (others => '0');
a_en : in std_logic := '1';
a_we : in std_logic := '0';
b_clock : in std_logic;
b_req : in t_io_req;
b_resp : out t_io_resp );
attribute keep_hierarchy : string;
attribute keep_hierarchy of dpram_io : entity is "yes";
end entity;
architecture xilinx of dpram_io is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(7 downto 0);
shared variable ram : t_ram := (others => g_default);
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
signal b_address : unsigned(g_depth_bits-1 downto 0);
signal b_rdata : std_logic_vector(7 downto 0);
signal b_wdata : std_logic_vector(7 downto 0) := (others => '0');
signal b_en : std_logic := '1';
signal b_we : std_logic := '0';
signal b_ack : std_logic := '0';
begin
-----------------------------------------------------------------------
-- PORT A
-----------------------------------------------------------------------
p_port_a: process(a_clock)
begin
if rising_edge(a_clock) then
if a_en = '1' then
if g_read_first_a then
a_rdata <= ram(to_integer(a_address));
end if;
if a_we = '1' then
ram(to_integer(a_address)) := a_wdata;
end if;
if not g_read_first_a then
a_rdata <= ram(to_integer(a_address));
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- PORT B
-----------------------------------------------------------------------
b_address <= b_req.address(g_depth_bits-1 downto 0);
b_we <= b_req.write;
b_en <= b_req.write or b_req.read;
b_wdata <= b_req.data;
b_resp.data <= b_rdata when b_ack='1' else (others => '0');
b_resp.ack <= b_ack;
p_port_b: process(b_clock)
begin
if rising_edge(b_clock) then
b_ack <= b_en;
if b_en = '1' then
if g_read_first_b then
b_rdata <= ram(to_integer(b_address));
end if;
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
end if;
if not g_read_first_b then
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity dpram_io is
generic (
g_depth_bits : positive := 9;
g_default : std_logic_vector(7 downto 0) := X"0F";
g_read_first_a : boolean := false;
g_read_first_b : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
a_clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(7 downto 0);
a_wdata : in std_logic_vector(7 downto 0) := (others => '0');
a_en : in std_logic := '1';
a_we : in std_logic := '0';
b_clock : in std_logic;
b_req : in t_io_req;
b_resp : out t_io_resp );
attribute keep_hierarchy : string;
attribute keep_hierarchy of dpram_io : entity is "yes";
end entity;
architecture xilinx of dpram_io is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(7 downto 0);
shared variable ram : t_ram := (others => g_default);
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
signal b_address : unsigned(g_depth_bits-1 downto 0);
signal b_rdata : std_logic_vector(7 downto 0);
signal b_wdata : std_logic_vector(7 downto 0) := (others => '0');
signal b_en : std_logic := '1';
signal b_we : std_logic := '0';
signal b_ack : std_logic := '0';
begin
-----------------------------------------------------------------------
-- PORT A
-----------------------------------------------------------------------
p_port_a: process(a_clock)
begin
if rising_edge(a_clock) then
if a_en = '1' then
if g_read_first_a then
a_rdata <= ram(to_integer(a_address));
end if;
if a_we = '1' then
ram(to_integer(a_address)) := a_wdata;
end if;
if not g_read_first_a then
a_rdata <= ram(to_integer(a_address));
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- PORT B
-----------------------------------------------------------------------
b_address <= b_req.address(g_depth_bits-1 downto 0);
b_we <= b_req.write;
b_en <= b_req.write or b_req.read;
b_wdata <= b_req.data;
b_resp.data <= b_rdata when b_ack='1' else (others => '0');
b_resp.ack <= b_ack;
p_port_b: process(b_clock)
begin
if rising_edge(b_clock) then
b_ack <= b_en;
if b_en = '1' then
if g_read_first_b then
b_rdata <= ram(to_integer(b_address));
end if;
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
end if;
if not g_read_first_b then
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity dpram_io is
generic (
g_depth_bits : positive := 9;
g_default : std_logic_vector(7 downto 0) := X"0F";
g_read_first_a : boolean := false;
g_read_first_b : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
a_clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(7 downto 0);
a_wdata : in std_logic_vector(7 downto 0) := (others => '0');
a_en : in std_logic := '1';
a_we : in std_logic := '0';
b_clock : in std_logic;
b_req : in t_io_req;
b_resp : out t_io_resp );
attribute keep_hierarchy : string;
attribute keep_hierarchy of dpram_io : entity is "yes";
end entity;
architecture xilinx of dpram_io is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(7 downto 0);
shared variable ram : t_ram := (others => g_default);
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
signal b_address : unsigned(g_depth_bits-1 downto 0);
signal b_rdata : std_logic_vector(7 downto 0);
signal b_wdata : std_logic_vector(7 downto 0) := (others => '0');
signal b_en : std_logic := '1';
signal b_we : std_logic := '0';
signal b_ack : std_logic := '0';
begin
-----------------------------------------------------------------------
-- PORT A
-----------------------------------------------------------------------
p_port_a: process(a_clock)
begin
if rising_edge(a_clock) then
if a_en = '1' then
if g_read_first_a then
a_rdata <= ram(to_integer(a_address));
end if;
if a_we = '1' then
ram(to_integer(a_address)) := a_wdata;
end if;
if not g_read_first_a then
a_rdata <= ram(to_integer(a_address));
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- PORT B
-----------------------------------------------------------------------
b_address <= b_req.address(g_depth_bits-1 downto 0);
b_we <= b_req.write;
b_en <= b_req.write or b_req.read;
b_wdata <= b_req.data;
b_resp.data <= b_rdata when b_ack='1' else (others => '0');
b_resp.ack <= b_ack;
p_port_b: process(b_clock)
begin
if rising_edge(b_clock) then
b_ack <= b_en;
if b_en = '1' then
if g_read_first_b then
b_rdata <= ram(to_integer(b_address));
end if;
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
end if;
if not g_read_first_b then
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end if;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1002.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01002pkg is
type TWO is range 1 to 2;
end c06s03b00x00p09n01i01002pkg;
use work.c06s03b00x00p09n01i01002pkg.all;
ENTITY c06s03b00x00p09n01i01002ent IS
END c06s03b00x00p09n01i01002ent;
ARCHITECTURE c06s03b00x00p09n01i01002arch OF c06s03b00x00p09n01i01002ent IS
BEGIN
TESTING: PROCESS
subtype ST7 is Q.TWO (1 to 1);
-- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p09n01i01002 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01002arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1002.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01002pkg is
type TWO is range 1 to 2;
end c06s03b00x00p09n01i01002pkg;
use work.c06s03b00x00p09n01i01002pkg.all;
ENTITY c06s03b00x00p09n01i01002ent IS
END c06s03b00x00p09n01i01002ent;
ARCHITECTURE c06s03b00x00p09n01i01002arch OF c06s03b00x00p09n01i01002ent IS
BEGIN
TESTING: PROCESS
subtype ST7 is Q.TWO (1 to 1);
-- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p09n01i01002 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01002arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1002.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01002pkg is
type TWO is range 1 to 2;
end c06s03b00x00p09n01i01002pkg;
use work.c06s03b00x00p09n01i01002pkg.all;
ENTITY c06s03b00x00p09n01i01002ent IS
END c06s03b00x00p09n01i01002ent;
ARCHITECTURE c06s03b00x00p09n01i01002arch OF c06s03b00x00p09n01i01002ent IS
BEGIN
TESTING: PROCESS
subtype ST7 is Q.TWO (1 to 1);
-- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p09n01i01002 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01002arch;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_cmdsts_if is
generic (
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
-- Width of DataMover status word
-- 8 for Determinate BTT Mode
-- 32 for Indterminate BTT Mode
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_ENABLE_QUEUE : integer range 0 to 1 := 1
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Command write interface from mm2s sm --
s2mm_cmnd_wr : in std_logic ; --
s2mm_cmnd_data : in std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
s2mm_cmnd_pending : out std_logic ; --
--
s2mm_packet_eof : out std_logic ; --
--
s2mm_sts_received_clr : in std_logic ; --
s2mm_sts_received : out std_logic ; --
s2mm_tailpntr_enble : in std_logic ; --
s2mm_desc_cmplt : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_s2mm_cmd_tvalid : out std_logic ; --
s_axis_s2mm_cmd_tready : in std_logic ; --
s_axis_s2mm_cmd_tdata : out std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_s2mm_sts_tvalid : in std_logic ; --
m_axis_s2mm_sts_tready : out std_logic ; --
m_axis_s2mm_sts_tdata : in std_logic_vector --
(C_DM_STATUS_WIDTH - 1 downto 0) ; --
m_axis_s2mm_sts_tkeep : in std_logic_vector((C_DM_STATUS_WIDTH/8)-1 downto 0); --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
s2mm_brcvd : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_done : out std_logic ; --
s2mm_error : out std_logic ; --
s2mm_interr : out std_logic ; --
s2mm_slverr : out std_logic ; --
s2mm_decerr : out std_logic ; --
s2mm_tag : out std_logic_vector(3 downto 0) --
);
end axi_dma_s2mm_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sts_tready : std_logic := '0';
signal sts_received_i : std_logic := '0';
signal stale_desc : std_logic := '0';
signal log_status : std_logic := '0';
signal s2mm_slverr_i : std_logic := '0';
signal s2mm_decerr_i : std_logic := '0';
signal s2mm_interr_i : std_logic := '0';
signal s2mm_error_or : std_logic := '0';
signal s2mm_packet_eof_i : std_logic := '0';
signal smpl_dma_overflow : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
s2mm_slverr <= s2mm_slverr_i;
s2mm_decerr <= s2mm_decerr_i;
s2mm_interr <= s2mm_interr_i or smpl_dma_overflow;
s2mm_packet_eof <= s2mm_packet_eof_i;
-- Stale descriptor if complete bit already set and in tail pointer mode.
stale_desc <= '1' when s2mm_desc_cmplt = '1' and s2mm_tailpntr_enble = '1'
else '0';
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_HOLD_NO_DATA : if C_ENABLE_QUEUE = 1 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_s2mm_cmd_tvalid <= '0';
-- s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
-- new command and descriptor not flagged as stale
elsif(s2mm_cmnd_wr = '1' and stale_desc = '0')then
s_axis_s2mm_cmd_tvalid <= '1';
-- s_axis_s2mm_cmd_tdata <= s2mm_cmnd_data;
s2mm_cmnd_pending <= '1';
-- clear flag on datamover acceptance of command
elsif(s_axis_s2mm_cmd_tready = '1')then
s_axis_s2mm_cmd_tvalid <= '0';
-- s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_s2mm_cmd_tdata <= s2mm_cmnd_data;
end generate GEN_HOLD_NO_DATA;
GEN_HOLD_DATA : if C_ENABLE_QUEUE = 0 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
-- new command and descriptor not flagged as stale
elsif(s2mm_cmnd_wr = '1' and stale_desc = '0')then
s_axis_s2mm_cmd_tvalid <= '1';
s_axis_s2mm_cmd_tdata <= s2mm_cmnd_data;
s2mm_cmnd_pending <= '1';
-- clear flag on datamover acceptance of command
elsif(s_axis_s2mm_cmd_tready = '1')then
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_HOLD_DATA;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_tready <= '0';
elsif(sts_tready = '1' and m_axis_s2mm_sts_tvalid = '1')then
sts_tready <= '0';
elsif(sts_received_i = '0') then
sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-- Pass to DataMover
m_axis_s2mm_sts_tready <= sts_tready;
log_status <= '1' when m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0'
else '0';
-- Status stream is included, and using the rxlength from the status stream and in Scatter Gather Mode
DETERMINATE_BTT_MODE : if (C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_SG_USE_STSAPP_LENGTH = 1
and C_INCLUDE_SG = 1) or (C_MICRO_DMA = 1) generate
begin
-- Bytes received not available in determinate byte mode
s2mm_brcvd <= (others => '0');
-- Simple DMA overflow not used in Scatter Gather Mode
smpl_dma_overflow <= '0';
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0')then
s2mm_done <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
s2mm_slverr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
s2mm_decerr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_DECERR_BIT);
s2mm_interr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
s2mm_tag <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- End Of Frame (EOF = 1) detected on status received. Used
-- for interrupt delay timer
REG_RX_EOF : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_packet_eof_i <= '0';
elsif(log_status = '1')then
s2mm_packet_eof_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TAGEOF_BIT)
or m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
else
s2mm_packet_eof_i <= '0';
end if;
end if;
end process REG_RX_EOF;
end generate DETERMINATE_BTT_MODE;
-- No Status Stream or not using rxlength from status stream or in Simple DMA Mode
INDETERMINATE_BTT_MODE : if (C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_SG_USE_STSAPP_LENGTH = 0
or C_INCLUDE_SG = 0) and (C_MICRO_DMA = 0) generate
-- Bytes received MSB index bit
constant BRCVD_MSB_BIT : integer := (C_DM_STATUS_WIDTH - 2) - (BUFFER_LENGTH_WIDTH - C_SG_LENGTH_WIDTH);
-- Bytes received LSB index bit
constant BRCVD_LSB_BIT : integer := (C_DM_STATUS_WIDTH - 2) - (BUFFER_LENGTH_WIDTH - 1);
begin
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_brcvd <= (others => '0');
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0')then
s2mm_brcvd <= m_axis_s2mm_sts_tdata(BRCVD_MSB_BIT downto BRCVD_LSB_BIT);
s2mm_done <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
s2mm_slverr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
s2mm_decerr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_DECERR_BIT);
s2mm_interr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
s2mm_tag <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
s2mm_brcvd <= (others => '0');
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- End Of Frame (EOF = 1) detected on statis received. Used
-- for interrupt delay timer
REG_RX_EOF : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_packet_eof_i <= '0';
elsif(log_status = '1')then
s2mm_packet_eof_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TLAST_BIT)
or m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
else
s2mm_packet_eof_i <= '0';
end if;
end if;
end process REG_RX_EOF;
-- If in Simple DMA mode then generate overflow flag
GEN_OVERFLOW_SMPL_DMA : if C_INCLUDE_SG = 0 generate
REG_OVERFLOW : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
smpl_dma_overflow <= '0';
-- If status received and TLAST bit is NOT set then packet is bigger than
-- BTT value commanded which is an invalid command
elsif(log_status = '1' and m_axis_s2mm_sts_tdata(DATAMOVER_STS_TLAST_BIT) = '0')then
smpl_dma_overflow <= '1';
end if;
end if;
end process REG_OVERFLOW;
end generate GEN_OVERFLOW_SMPL_DMA;
-- If in Scatter Gather Mode then do NOT generate simple dma mode overflow flag
GEN_NO_OVERFLOW_SMPL_DMA : if C_INCLUDE_SG = 1 generate
begin
smpl_dma_overflow <= '0';
end generate GEN_NO_OVERFLOW_SMPL_DMA;
end generate INDETERMINATE_BTT_MODE;
-- Flag when status is received. Used to hold status until sg if
-- can use status. This only has meaning when SG Engine Queues are turned
-- on
STS_RCVD_FLAG : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_sts_received_clr = '1')then
sts_received_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0')then
sts_received_i <= '1';
end if;
end if;
end process STS_RCVD_FLAG;
s2mm_sts_received <= sts_received_i;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error_or <= s2mm_slverr_i or s2mm_decerr_i or s2mm_interr_i or smpl_dma_overflow;
-- Log errors into a global error output
S2MM_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_error <= '0';
-- If Datamover issues error on the transfer or if a stale descriptor is
-- detected when in tailpointer mode then issue an error
elsif((s2mm_error_or = '1')
or (stale_desc = '1' and s2mm_cmnd_wr='1'))then
s2mm_error <= '1';
end if;
end if;
end process S2MM_ERROR_PROCESS;
end implementation;
|
-- --------------------------------------------------------------------
-- Title : Standard VHDL Synthesis Packages (1076.3, NUMERIC_STD_UNSIGNED)
--
-- This package overloaded the arithmetic operaters for
-- "STD_ULOGIC_VECTOR", and treats this vector like an
-- "UNSIGNED" from "numeric_std".
--
-- This is the updated (proposed) new package to be
-- balloted in January.
--
-- New subprograms are at the end of the package header
-- and the package body. These are to be revised, ID's
-- assigned, and voted into the ballot version.
--
-- Other changes will be noted here.
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD_UNSIGNED is
-- begin LCS-2006-141
-- Replace all subsequent occurrences of STD_LOGIC_VECTOR
-- with STD_ULOGIC_ECTOR.
-- end LCS-2006-141
-- Id: A.3
function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit STD_ULOGIC_VECTOR
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- end LCS-2006-129
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function \?>\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function \?>\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function \?>\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function \?<\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function \?<\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function \?<\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function \?<=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function \?<=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function \?<=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function \?>=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function \?>=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function \?>=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function \?=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function \?=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function \?=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function \?/=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function \?/=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function \?/=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
-- size_res versions of these functions (Bugzilla 165)
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.3
function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
-- begin LCS-2006-130
alias To_Std_Logic_Vector is
To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
-- size_res versions of these functions (Bugzilla 165)
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- end LCS-2006-130
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
-- size_res versions of these functions (Bugzilla 165)
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- begin LCS-2006-130
alias To_Std_ULogic_Vector is
To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
-- end LCS-2006-130
--============================================================================
-- Translation Functions
--============================================================================
-- Id: T.1
function TO_01 (S : STD_ULOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
-- begin LCS-2006-141
-- Replace all subsequent occurrences of STD_LOGIC_VECTOR
-- with STD_ULOGIC_ECTOR.
-- end LCS-2006-141
-- Id: A.3
function "+" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit STD_LOGIC_VECTOR
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG : STD_LOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : STD_LOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- end LCS-2006-129
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function \?>\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function \?>\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function \?>\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function \?<\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function \?<\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function \?<\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function \?<=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function \?<=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function \?<=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function \?>=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function \?>=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function \?>=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function \?=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function \?=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function \?=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function \?/=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function \?/=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function \?/=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : STD_LOGIC_VECTOR; COUNT : INTEGER) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : STD_LOGIC_VECTOR; COUNT : INTEGER) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_LOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
-- size_res versions of these functions (Bugzilla 165)
function RESIZE (ARG, SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_LOGIC_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- end LCS-2006-130
--============================================================================
-- Translation Functions
--============================================================================
-- Id: T.1
function TO_01 (S : STD_LOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
end package NUMERIC_STD_UNSIGNED;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT NUMERIC_STD_UNSIGNED package
-- This package body supplies a recommended implementation of these functions
-- Version: $Revision: 1.4 $
-- Date: $Date: 2009/08/26 19:56:30 $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use work.numeric_std_additions.all;
package body NUMERIC_STD_UNSIGNED is
-- Id: A.3
function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + UNSIGNED(R));
end function "+";
-- Id: A.3R
function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
-- Id: A.5
function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
--============================================================================
-- Id: A.9
function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - UNSIGNED(R));
end function "-";
-- Id: A.9R
function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
-- Id: A.11
function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
--============================================================================
-- Id: A.15
function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) * UNSIGNED(R));
end function "*";
-- Id: A.17
function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) * R);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L * UNSIGNED(R));
end function "*";
--============================================================================
-- Id: A.21
function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) / UNSIGNED(R));
end function "/";
-- Id: A.23
function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) / R);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L / UNSIGNED(R));
end function "/";
--============================================================================
-- Id: A.27
function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
end function "rem";
-- Id: A.29
function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) rem R);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L rem UNSIGNED(R));
end function "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
end function "mod";
-- Id: A.35
function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) mod R);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L mod UNSIGNED(R));
end function "mod";
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_leftmost(UNSIGNED(ARG), Y);
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_rightmost(UNSIGNED(ARG), Y);
end function find_rightmost;
-- end LCS-2006-129
--============================================================================
-- Id: C.1
function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) > UNSIGNED(R);
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L > UNSIGNED(R);
end function ">";
-- Id: C.5
function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) > R;
end function ">";
--============================================================================
-- Id: C.7
function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) < UNSIGNED(R);
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L < UNSIGNED(R);
end function "<";
-- Id: C.11
function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) < R;
end function "<";
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) <= UNSIGNED(R);
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L <= UNSIGNED(R);
end function "<=";
-- Id: C.17
function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) <= R;
end function "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) >= UNSIGNED(R);
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L >= UNSIGNED(R);
end function ">=";
-- Id: C.23
function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) >= R;
end function ">=";
--============================================================================
-- Id: C.25
function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end function "=";
-- Id: C.29
function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end function "=";
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end function "/=";
-- Id: C.35
function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end function "/=";
--============================================================================
-- Id: C.37
function MINIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MINIMUM;
-- Id: C.39
function MINIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(L, UNSIGNED(R)));
end function MINIMUM;
-- Id: C.41
function MINIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), R));
end function MINIMUM;
--============================================================================
-- Id: C.43
function MAXIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(L, UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), R));
end function MAXIMUM;
--============================================================================
-- Id: C.49
function \?>\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), UNSIGNED(R));
end function \?>\;
-- Id: C.51
function \?>\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (L, UNSIGNED(R));
end function \?>\;
-- Id: C.53
function \?>\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), R);
end function \?>\;
--============================================================================
-- Id: C.55
function \?<\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), UNSIGNED(R));
end function \?<\;
-- Id: C.57
function \?<\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (L, UNSIGNED(R));
end function \?<\;
-- Id: C.59
function \?<\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), R);
end function \?<\;
--============================================================================
-- Id: C.61
function \?<=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), UNSIGNED(R));
end function \?<=\;
-- Id: C.63
function \?<=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (L, UNSIGNED(R));
end function \?<=\;
-- Id: C.65
function \?<=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), R);
end function \?<=\;
--============================================================================
-- Id: C.67
function \?>=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), UNSIGNED(R));
end function \?>=\;
-- Id: C.69
function \?>=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (L, UNSIGNED(R));
end function \?>=\;
-- Id: C.71
function \?>=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), R);
end function \?>=\;
--============================================================================
-- Id: C.73
function \?=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), UNSIGNED(R));
end function \?=\;
-- Id: C.75
function \?=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (L, UNSIGNED(R));
end function \?=\;
-- Id: C.77
function \?=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), R);
end function \?=\;
--============================================================================
-- Id: C.79
function \?/=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), UNSIGNED(R));
end function \?/=\;
-- Id: C.81
function \?/=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (L, UNSIGNED(R));
end function \?/=\;
-- Id: C.83
function \?/=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), R);
end function \?/=\;
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (SHIFT_LEFT(unsigned(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (SHIFT_RIGHT(unsigned(ARG), COUNT));
end function SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (ROTATE_LEFT(unsigned(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (ROTATE_RIGHT(unsigned(ARG), COUNT));
end function ROTATE_RIGHT;
--============================================================================
-- Id: S.17
function "sla" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sla COUNT);
end function "sla";
-- Id: S.19
function "sra" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sra COUNT);
end function "sra";
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL is
begin
return TO_INTEGER(UNSIGNED(ARG));
end function TO_INTEGER;
-- Id: D.3
function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE));
end function To_StdLogicVector;
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdLogicVector;
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE));
end function To_StdULogicVector;
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdULogicVector;
--============================================================================
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0, 1, H, L).
-- Id: T.1
function TO_01 (S : STD_ULOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
TO_01 (S => UNSIGNED(S),
XMAP => XMAP));
end function TO_01;
-- Id: A.3
function "+" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) + UNSIGNED(R));
end function "+";
-- Id: A.3R
function "+"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
-- Id: A.5
function "+" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
--============================================================================
-- Id: A.9
function "-" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) - UNSIGNED(R));
end function "-";
-- Id: A.9R
function "-"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
-- Id: A.11
function "-" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
--============================================================================
-- Id: A.15
function "*" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) * UNSIGNED(R));
end function "*";
-- Id: A.17
function "*" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) * R);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L * UNSIGNED(R));
end function "*";
--============================================================================
-- Id: A.21
function "/" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) / UNSIGNED(R));
end function "/";
-- Id: A.23
function "/" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) / R);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L / UNSIGNED(R));
end function "/";
--============================================================================
-- Id: A.27
function "rem" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
end function "rem";
-- Id: A.29
function "rem" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) rem R);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L rem UNSIGNED(R));
end function "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
end function "mod";
-- Id: A.35
function "mod" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) mod R);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L mod UNSIGNED(R));
end function "mod";
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG: STD_LOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_leftmost(UNSIGNED(ARG), Y);
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG: STD_LOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_rightmost(UNSIGNED(ARG), Y);
end function find_rightmost;
-- end LCS-2006-129
--============================================================================
-- Id: C.1
function ">" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) > UNSIGNED(R);
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L > UNSIGNED(R);
end function ">";
-- Id: C.5
function ">" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) > R;
end function ">";
--============================================================================
-- Id: C.7
function "<" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) < UNSIGNED(R);
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L < UNSIGNED(R);
end function "<";
-- Id: C.11
function "<" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) < R;
end function "<";
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) <= UNSIGNED(R);
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L <= UNSIGNED(R);
end function "<=";
-- Id: C.17
function "<=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) <= R;
end function "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) >= UNSIGNED(R);
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L >= UNSIGNED(R);
end function ">=";
-- Id: C.23
function ">=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) >= R;
end function ">=";
--============================================================================
-- Id: C.25
function "=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end function "=";
-- Id: C.29
function "=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end function "=";
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end function "/=";
-- Id: C.35
function "/=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end function "/=";
--============================================================================
-- Id: C.37
function MINIMUM (L, R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MINIMUM;
-- Id: C.39
function MINIMUM (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MINIMUM(L, UNSIGNED(R)));
end function MINIMUM;
-- Id: C.41
function MINIMUM (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MINIMUM(UNSIGNED(L), R));
end function MINIMUM;
--============================================================================
-- Id: C.43
function MAXIMUM (L, R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MAXIMUM(L, UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MAXIMUM(UNSIGNED(L), R));
end function MAXIMUM;
--============================================================================
-- Id: C.49
function \?>\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), UNSIGNED(R));
end function \?>\;
-- Id: C.51
function \?>\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (L, UNSIGNED(R));
end function \?>\;
-- Id: C.53
function \?>\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), R);
end function \?>\;
--============================================================================
-- Id: C.55
function \?<\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), UNSIGNED(R));
end function \?<\;
-- Id: C.57
function \?<\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (L, UNSIGNED(R));
end function \?<\;
-- Id: C.59
function \?<\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), R);
end function \?<\;
--============================================================================
-- Id: C.61
function \?<=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), UNSIGNED(R));
end function \?<=\;
-- Id: C.63
function \?<=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (L, UNSIGNED(R));
end function \?<=\;
-- Id: C.65
function \?<=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), R);
end function \?<=\;
--============================================================================
-- Id: C.67
function \?>=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), UNSIGNED(R));
end function \?>=\;
-- Id: C.69
function \?>=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (L, UNSIGNED(R));
end function \?>=\;
-- Id: C.71
function \?>=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), R);
end function \?>=\;
--============================================================================
-- Id: C.73
function \?=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), UNSIGNED(R));
end function \?=\;
-- Id: C.75
function \?=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (L, UNSIGNED(R));
end function \?=\;
-- Id: C.77
function \?=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), R);
end function \?=\;
--============================================================================
-- Id: C.79
function \?/=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), UNSIGNED(R));
end function \?/=\;
-- Id: C.81
function \?/=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (L, UNSIGNED(R));
end function \?/=\;
-- Id: C.83
function \?/=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), R);
end function \?/=\;
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (SHIFT_LEFT(unsigned(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (SHIFT_RIGHT(unsigned(ARG), COUNT));
end function SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (ROTATE_LEFT(unsigned(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (ROTATE_RIGHT(unsigned(ARG), COUNT));
end function ROTATE_RIGHT;
--============================================================================
-- Id: S.17
function "sla" (ARG: STD_LOGIC_VECTOR; COUNT: INTEGER) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(ARG) sla COUNT);
end function "sla";
-- Id: S.19
function "sra" (ARG: STD_LOGIC_VECTOR; COUNT: INTEGER) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(ARG) sra COUNT);
end function "sra";
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_LOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : STD_LOGIC_VECTOR)
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_LOGIC_VECTOR) return NATURAL is
begin
return TO_INTEGER(UNSIGNED(ARG));
end function TO_INTEGER;
--============================================================================
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0, 1, H, L).
-- Id: T.1
function TO_01 (S : STD_LOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (
TO_01 (S => UNSIGNED(S),
XMAP => XMAP));
end function TO_01;
end package body NUMERIC_STD_UNSIGNED;
|
-- --------------------------------------------------------------------
-- Title : Standard VHDL Synthesis Packages (1076.3, NUMERIC_STD_UNSIGNED)
--
-- This package overloaded the arithmetic operaters for
-- "STD_ULOGIC_VECTOR", and treats this vector like an
-- "UNSIGNED" from "numeric_std".
--
-- This is the updated (proposed) new package to be
-- balloted in January.
--
-- New subprograms are at the end of the package header
-- and the package body. These are to be revised, ID's
-- assigned, and voted into the ballot version.
--
-- Other changes will be noted here.
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD_UNSIGNED is
-- begin LCS-2006-141
-- Replace all subsequent occurrences of STD_LOGIC_VECTOR
-- with STD_ULOGIC_ECTOR.
-- end LCS-2006-141
-- Id: A.3
function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit STD_ULOGIC_VECTOR
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- end LCS-2006-129
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function \?>\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function \?>\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function \?>\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function \?<\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function \?<\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function \?<\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function \?<=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function \?<=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function \?<=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function \?>=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function \?>=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function \?>=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function \?=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function \?=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function \?=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function \?/=\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function \?/=\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function \?/=\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
-- size_res versions of these functions (Bugzilla 165)
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.3
function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
-- begin LCS-2006-130
alias To_Std_Logic_Vector is
To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
-- size_res versions of these functions (Bugzilla 165)
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- end LCS-2006-130
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
-- size_res versions of these functions (Bugzilla 165)
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- begin LCS-2006-130
alias To_Std_ULogic_Vector is
To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
-- end LCS-2006-130
--============================================================================
-- Translation Functions
--============================================================================
-- Id: T.1
function TO_01 (S : STD_ULOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
-- begin LCS-2006-141
-- Replace all subsequent occurrences of STD_LOGIC_VECTOR
-- with STD_ULOGIC_ECTOR.
-- end LCS-2006-141
-- Id: A.3
function "+" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit STD_LOGIC_VECTOR
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG : STD_LOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : STD_LOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- end LCS-2006-129
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function \?>\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function \?>\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function \?>\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function \?<\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function \?<\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function \?<\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function \?<=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function \?<=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function \?<=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function \?>=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function \?>=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function \?>=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function \?=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function \?=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function \?=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function \?/=\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function \?/=\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function \?/=\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : STD_LOGIC_VECTOR; COUNT : INTEGER) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : STD_LOGIC_VECTOR; COUNT : INTEGER) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_LOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
-- size_res versions of these functions (Bugzilla 165)
function RESIZE (ARG, SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_LOGIC_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- end LCS-2006-130
--============================================================================
-- Translation Functions
--============================================================================
-- Id: T.1
function TO_01 (S : STD_LOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
end package NUMERIC_STD_UNSIGNED;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT NUMERIC_STD_UNSIGNED package
-- This package body supplies a recommended implementation of these functions
-- Version: $Revision: 1.4 $
-- Date: $Date: 2009/08/26 19:56:30 $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use work.numeric_std_additions.all;
package body NUMERIC_STD_UNSIGNED is
-- Id: A.3
function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + UNSIGNED(R));
end function "+";
-- Id: A.3R
function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
-- Id: A.5
function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
--============================================================================
-- Id: A.9
function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - UNSIGNED(R));
end function "-";
-- Id: A.9R
function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
-- Id: A.11
function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
--============================================================================
-- Id: A.15
function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) * UNSIGNED(R));
end function "*";
-- Id: A.17
function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) * R);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L * UNSIGNED(R));
end function "*";
--============================================================================
-- Id: A.21
function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) / UNSIGNED(R));
end function "/";
-- Id: A.23
function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) / R);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L / UNSIGNED(R));
end function "/";
--============================================================================
-- Id: A.27
function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
end function "rem";
-- Id: A.29
function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) rem R);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L rem UNSIGNED(R));
end function "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
end function "mod";
-- Id: A.35
function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) mod R);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L mod UNSIGNED(R));
end function "mod";
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_leftmost(UNSIGNED(ARG), Y);
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_rightmost(UNSIGNED(ARG), Y);
end function find_rightmost;
-- end LCS-2006-129
--============================================================================
-- Id: C.1
function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) > UNSIGNED(R);
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L > UNSIGNED(R);
end function ">";
-- Id: C.5
function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) > R;
end function ">";
--============================================================================
-- Id: C.7
function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) < UNSIGNED(R);
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L < UNSIGNED(R);
end function "<";
-- Id: C.11
function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) < R;
end function "<";
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) <= UNSIGNED(R);
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L <= UNSIGNED(R);
end function "<=";
-- Id: C.17
function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) <= R;
end function "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) >= UNSIGNED(R);
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L >= UNSIGNED(R);
end function ">=";
-- Id: C.23
function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) >= R;
end function ">=";
--============================================================================
-- Id: C.25
function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end function "=";
-- Id: C.29
function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end function "=";
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end function "/=";
-- Id: C.35
function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end function "/=";
--============================================================================
-- Id: C.37
function MINIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MINIMUM;
-- Id: C.39
function MINIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(L, UNSIGNED(R)));
end function MINIMUM;
-- Id: C.41
function MINIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), R));
end function MINIMUM;
--============================================================================
-- Id: C.43
function MAXIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(L, UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), R));
end function MAXIMUM;
--============================================================================
-- Id: C.49
function \?>\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), UNSIGNED(R));
end function \?>\;
-- Id: C.51
function \?>\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (L, UNSIGNED(R));
end function \?>\;
-- Id: C.53
function \?>\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), R);
end function \?>\;
--============================================================================
-- Id: C.55
function \?<\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), UNSIGNED(R));
end function \?<\;
-- Id: C.57
function \?<\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (L, UNSIGNED(R));
end function \?<\;
-- Id: C.59
function \?<\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), R);
end function \?<\;
--============================================================================
-- Id: C.61
function \?<=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), UNSIGNED(R));
end function \?<=\;
-- Id: C.63
function \?<=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (L, UNSIGNED(R));
end function \?<=\;
-- Id: C.65
function \?<=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), R);
end function \?<=\;
--============================================================================
-- Id: C.67
function \?>=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), UNSIGNED(R));
end function \?>=\;
-- Id: C.69
function \?>=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (L, UNSIGNED(R));
end function \?>=\;
-- Id: C.71
function \?>=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), R);
end function \?>=\;
--============================================================================
-- Id: C.73
function \?=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), UNSIGNED(R));
end function \?=\;
-- Id: C.75
function \?=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (L, UNSIGNED(R));
end function \?=\;
-- Id: C.77
function \?=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), R);
end function \?=\;
--============================================================================
-- Id: C.79
function \?/=\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), UNSIGNED(R));
end function \?/=\;
-- Id: C.81
function \?/=\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (L, UNSIGNED(R));
end function \?/=\;
-- Id: C.83
function \?/=\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), R);
end function \?/=\;
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (SHIFT_LEFT(unsigned(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (SHIFT_RIGHT(unsigned(ARG), COUNT));
end function SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (ROTATE_LEFT(unsigned(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is
begin
return std_ulogic_vector (ROTATE_RIGHT(unsigned(ARG), COUNT));
end function ROTATE_RIGHT;
--============================================================================
-- Id: S.17
function "sla" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sla COUNT);
end function "sla";
-- Id: S.19
function "sra" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sra COUNT);
end function "sra";
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL is
begin
return TO_INTEGER(UNSIGNED(ARG));
end function TO_INTEGER;
-- Id: D.3
function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE));
end function To_StdLogicVector;
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdLogicVector;
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE));
end function To_StdULogicVector;
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdULogicVector;
--============================================================================
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0, 1, H, L).
-- Id: T.1
function TO_01 (S : STD_ULOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
TO_01 (S => UNSIGNED(S),
XMAP => XMAP));
end function TO_01;
-- Id: A.3
function "+" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) + UNSIGNED(R));
end function "+";
-- Id: A.3R
function "+"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
-- Id: A.5
function "+" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
--============================================================================
-- Id: A.9
function "-" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) - UNSIGNED(R));
end function "-";
-- Id: A.9R
function "-"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
-- Id: A.11
function "-" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
--============================================================================
-- Id: A.15
function "*" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) * UNSIGNED(R));
end function "*";
-- Id: A.17
function "*" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) * R);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L * UNSIGNED(R));
end function "*";
--============================================================================
-- Id: A.21
function "/" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) / UNSIGNED(R));
end function "/";
-- Id: A.23
function "/" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) / R);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L / UNSIGNED(R));
end function "/";
--============================================================================
-- Id: A.27
function "rem" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
end function "rem";
-- Id: A.29
function "rem" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) rem R);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L rem UNSIGNED(R));
end function "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
end function "mod";
-- Id: A.35
function "mod" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(L) mod R);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L mod UNSIGNED(R));
end function "mod";
-- begin LCS-2006-129
--============================================================================
-- Id: A.39
function find_leftmost (ARG: STD_LOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_leftmost(UNSIGNED(ARG), Y);
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG: STD_LOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_rightmost(UNSIGNED(ARG), Y);
end function find_rightmost;
-- end LCS-2006-129
--============================================================================
-- Id: C.1
function ">" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) > UNSIGNED(R);
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L > UNSIGNED(R);
end function ">";
-- Id: C.5
function ">" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) > R;
end function ">";
--============================================================================
-- Id: C.7
function "<" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) < UNSIGNED(R);
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L < UNSIGNED(R);
end function "<";
-- Id: C.11
function "<" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) < R;
end function "<";
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) <= UNSIGNED(R);
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L <= UNSIGNED(R);
end function "<=";
-- Id: C.17
function "<=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) <= R;
end function "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) >= UNSIGNED(R);
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L >= UNSIGNED(R);
end function ">=";
-- Id: C.23
function ">=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) >= R;
end function ">=";
--============================================================================
-- Id: C.25
function "=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end function "=";
-- Id: C.29
function "=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end function "=";
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end function "/=";
-- Id: C.35
function "/=" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end function "/=";
--============================================================================
-- Id: C.37
function MINIMUM (L, R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MINIMUM;
-- Id: C.39
function MINIMUM (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MINIMUM(L, UNSIGNED(R)));
end function MINIMUM;
-- Id: C.41
function MINIMUM (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MINIMUM(UNSIGNED(L), R));
end function MINIMUM;
--============================================================================
-- Id: C.43
function MAXIMUM (L, R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MAXIMUM(L, UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (MAXIMUM(UNSIGNED(L), R));
end function MAXIMUM;
--============================================================================
-- Id: C.49
function \?>\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), UNSIGNED(R));
end function \?>\;
-- Id: C.51
function \?>\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>\ (L, UNSIGNED(R));
end function \?>\;
-- Id: C.53
function \?>\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>\ (UNSIGNED(L), R);
end function \?>\;
--============================================================================
-- Id: C.55
function \?<\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), UNSIGNED(R));
end function \?<\;
-- Id: C.57
function \?<\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<\ (L, UNSIGNED(R));
end function \?<\;
-- Id: C.59
function \?<\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<\ (UNSIGNED(L), R);
end function \?<\;
--============================================================================
-- Id: C.61
function \?<=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), UNSIGNED(R));
end function \?<=\;
-- Id: C.63
function \?<=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?<=\ (L, UNSIGNED(R));
end function \?<=\;
-- Id: C.65
function \?<=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?<=\ (UNSIGNED(L), R);
end function \?<=\;
--============================================================================
-- Id: C.67
function \?>=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), UNSIGNED(R));
end function \?>=\;
-- Id: C.69
function \?>=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?>=\ (L, UNSIGNED(R));
end function \?>=\;
-- Id: C.71
function \?>=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?>=\ (UNSIGNED(L), R);
end function \?>=\;
--============================================================================
-- Id: C.73
function \?=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), UNSIGNED(R));
end function \?=\;
-- Id: C.75
function \?=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (L, UNSIGNED(R));
end function \?=\;
-- Id: C.77
function \?=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?=\ (UNSIGNED(L), R);
end function \?=\;
--============================================================================
-- Id: C.79
function \?/=\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), UNSIGNED(R));
end function \?/=\;
-- Id: C.81
function \?/=\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return \?/=\ (L, UNSIGNED(R));
end function \?/=\;
-- Id: C.83
function \?/=\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return \?/=\ (UNSIGNED(L), R);
end function \?/=\;
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (SHIFT_LEFT(unsigned(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (SHIFT_RIGHT(unsigned(ARG), COUNT));
end function SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (ROTATE_LEFT(unsigned(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (ROTATE_RIGHT(unsigned(ARG), COUNT));
end function ROTATE_RIGHT;
--============================================================================
-- Id: S.17
function "sla" (ARG: STD_LOGIC_VECTOR; COUNT: INTEGER) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(ARG) sla COUNT);
end function "sla";
-- Id: S.19
function "sra" (ARG: STD_LOGIC_VECTOR; COUNT: INTEGER) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (UNSIGNED(ARG) sra COUNT);
end function "sra";
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_LOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : STD_LOGIC_VECTOR)
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_LOGIC_VECTOR) return NATURAL is
begin
return TO_INTEGER(UNSIGNED(ARG));
end function TO_INTEGER;
--============================================================================
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0, 1, H, L).
-- Id: T.1
function TO_01 (S : STD_LOGIC_VECTOR; XMAP : STD_ULOGIC := '0')
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (
TO_01 (S => UNSIGNED(S),
XMAP => XMAP));
end function TO_01;
end package body NUMERIC_STD_UNSIGNED;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_b
--
-- Generated
-- by: wig
-- on: Thu Oct 20 06:53:04 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-struct-conf-c.vhd,v 1.1 2005/10/24 12:14:04 wig Exp $
-- $Date: 2005/10/24 12:14:04 $
-- $Log: ent_b-struct-conf-c.vhd,v $
-- Revision 1.1 2005/10/24 12:14:04 wig
-- added output.language.verilog = ansistyle,2001param
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.62 2005/10/19 15:40:06 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.38 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_b_struct_conf / ent_b
--
configuration ent_b_struct_conf of ent_b is
for struct
-- Generated Configuration
for inst_ba : ent_ba
use configuration work.ent_ba_struct_conf;
end for;
end for;
end ent_b_struct_conf;
--
-- End of Generated Configuration ent_b_struct_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY rgbfifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF rgbfifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY rgbfifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF rgbfifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY rgbfifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF rgbfifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This package contains necessary types, constants, and functions for the parameterized adder
/ design.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
package adder_pkg is
/* function used to check the consistency and correctness of generics 1 */
/**************************************************************************************************/
function adder_CHECKS (
max_possible_bit_opt : integer_exc;
truncate_to_bit_opt : integer_exc;
s : positive;
p : positive;
data_high : integer;
data_low : integer)
return integer;
/* functions for corrected generics and internal/external port signals 2 */
/**************************************************************************************************/
function adder_OH(
max_possible_bit_opt : integer_exc;
s : positive;
p : positive;
data_high : integer)
return integer;
function adder_OL(
truncate_to_bit_opt : integer_exc;
data_low : integer)
return integer;
/* structures and functions to store and read pipeline positions 3 */
/**************************************************************************************************/
-- PIPELINE_POSITIONS stores the desired position for the pipelines in the adder tree,
-- accumulator and output_buffer.
-- It depends on:
-- 1. total number of possible pipeline positions = ADD_LEVELS + 1(output buffer)
-- 2. the number of desired pipelines
-- 3. '1' or '0' to indicate the presence of a pipeline on that level
/*
type T_pipeline is record
P1 : sulv_v(0 to 1)(1 to 1);
P2 : sulv_v(0 to 2)(1 to 2);
P3 : sulv_v(0 to 3)(1 to 3);
P4 : sulv_v(0 to 4)(1 to 4);
P5 : sulv_v(0 to 5)(1 to 5);
P6 : sulv_v(0 to 6)(1 to 6);
P7 : sulv_v(0 to 7)(1 to 7);
P8 : sulv_v(0 to 8)(1 to 8);
P9 : sulv_v(0 to 9)(1 to 9);
P10: sulv_v(0 to 10)(1 to 10);
P11: sulv_v(0 to 11)(1 to 11);
P12: sulv_v(0 to 12)(1 to 12); -- P12 limit => implies a maximum of 1024 parallel inputs.
-- For PX, limit is 2**(X-2)
end record;
constant PIPELINE_POSITIONS: T_pipeline:=
(P1 => (0 => "0",
1 => "1"),
P2 => (0 => "00",
1 => "01",
2 => "11"),
P3 => (0 => "000",
1 => "001",
2 => "101",
3 => "111"),
P4 => (0 => "0000",
1 => "0001",
2 => "0101",------->4 (P4) possible positions: 2 pipelines wanted=> 2nd and 4th
3 => "1011",
4 => "1111"),
P5 => (0 => "00000",
1 => "00001",
2 => "00101",
3 => "10101",
4 => "10111",
5 => "11111"),
P6 => (0 => "000000",
1 => "000001",
2 => "001001",
3 => "010101",----->6 (P6) possible positions: 3 pipelines wanted=> 2nd, 4th and 6th
4 => "101011",
5 => "101111",
6 => "111111"),
P7 => (0 => "0000000",
1 => "0000001",
2 => "0001001",
3 => "0010101",
4 => "1010101",
5 => "1010111",
6 => "1011111",
7 => "1111111"),
P8 => (0 => "00000000",
1 => "00000001",
2 => "00010001",
3 => "00100101",
4 => "01010101",
5 => "10101011",
6 => "10101111",
7 => "10111111",
8 => "11111111"),
P9 => (0 => "000000000",
1 => "000000001",
2 => "000010001",
3 => "001001001",
4 => "001010101",
5 => "101010101",
6 => "101010111",
7 => "101011111",
8 => "101111111",
9 => "111111111"),
P10 => (0 => "0000000000",
1 => "0000000001",
2 => "0000100001",
3 => "0001001001",
4 => "0010010101",
5 => "0101010101",
6 => "1010101011",
7 => "1010101111",
8 => "1010111111",
9 => "1011111111",
10 => "1111111111"),
P11 => (0 => "00000000000",
1 => "00000000001",
2 => "00000100001",
3 => "00010001001",
4 => "00100100101",
5 => "00101010101",
6 => "10101010101",
7 => "10101010111",
8 => "10101011111",
9 => "10101111111",
10 => "10111111111",
11 => "11111111111"),
P12 => (0 => "000000000000",
1 => "000000000001",
2 => "000001000001",
3 => "000100010001",
4 => "001001001001",
5 => "000101010101",
6 => "010101010101",
7 => "101010101011",
8 => "101010101111",
9 => "101010111111",
10 => "101011111111",
11 => "101111111111",
12 => "111111111111")
);
--function used to read PIPELINE_POSITIONS
function pipeline_is_present(
possible_positions : positive;
pipelines : natural;
level : natural)
return boolean;
--used to get a numerical reference to T_pipeline members, for example pipeline_positions_ref(1)
-- returns PIPELINE_POSITIONS.P1
function pipeline_positions_ref(
number : positive)
return sulv_v;
*/
/* Other functions 4 */
/**************************************************************************************************/
--returns the number of signals in a specific level of the tree adder
function signals_per_level(
P, level : natural)
return natural;
end package;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
Package body adder_pkg is
/********************************************************************************************** 1 */
function adder_CHECKS(
max_possible_bit_opt : integer_exc;
truncate_to_bit_opt : integer_exc;
s : positive;
p : positive;
data_high : integer;
data_low : integer)
return integer is
constant output_h : integer := adder_OH(max_possible_bit_opt,
s,
p,
data_high);
begin
--Errors-----------------------------------------------------------------------------------------
--trying to limit to a bit which is below the data range
assert not(max_possible_bit_opt /= integer'low and max_possible_bit_opt<data_low)
report "(3) " &
"ILLEGAL PARAMETERS in entity adder: MAX_POSSIBLE_BIT_opt set to " &
image(max_possible_bit_opt) & " but the result range is: (" & image(output_h) &
" downto " & image(data_low) & ")."
severity error;
--trying to truncate to a value higher than norm_out_high
assert not(truncate_to_bit_opt /= integer'low and truncate_to_bit_opt>output_h)
report "(4) " &
"ILLEGAL PARAMETERS in entity adder: TRUNCATE_TO_BIT_opt set to " &
image(truncate_to_bit_opt) & " but the result range is: (" & image(output_h) &
" downto " & image(data_low) & ")."
severity error;
--trying to truncate to a value higher than the bit limitation (duplicated with 4)
assert not(max_possible_bit_opt /= integer'low and truncate_to_bit_opt /= integer'low and
truncate_to_bit_opt>max_possible_bit_opt)
report "(5) " &
"ILLEGAL PARAMETERS in entity adder: TRUNCATE_TO_BIT_opt cannot have a value higher " &
"than MAX_POSSIBLE_BIT_opt"
severity error;
--Notes------------------------------------------------------------------------------------------
--defined as warning so they appear in the report after synthesis
--note when truncating
assert not(truncate_to_bit_opt /= integer'low and truncate_to_bit_opt>data_low)
report "(1) " &
"NOTE in entity adder: truncating to bit " & image(truncate_to_bit_opt) & ". " &
"The bottom " & image(truncate_to_bit_opt-data_low) &
ite(truncate_to_bit_opt-data_low>1," bits are"," bit is") & " being ignored."
severity warning;
--note when truncation adds bits to the right
assert not(truncate_to_bit_opt /= integer'low and truncate_to_bit_opt<data_low)
report "(2) " &
"NOTE in entity adder: truncating to bit " & image(truncate_to_bit_opt) & ". " &
image(data_low-truncate_to_bit_opt) &
ite(data_low-truncate_to_bit_opt>1," bits are"," bit is") & " being added to the right."
severity warning;
--note when limiting the number of bits
assert not(max_possible_bit_opt /= integer'low and output_h<(data_high+log2ceil(s*p)))
report "(3) " &
"NOTE in entity adder: limiting the result of the addition to bit " &
image(max_possible_bit_opt) & ". The top " & image((data_high+log2ceil(s*p))-output_h) &
ite((data_high+log2ceil(s*p))-output_h>1," bits are"," bit is") & " not generated."
severity warning;
return 0;
end function;
/********************************************************************************************** 2 */
function adder_OH(
max_possible_bit_opt : integer_exc;
s : positive;
p : positive;
data_high : integer)
return integer is
begin
if max_possible_bit_opt = integer'low then
return data_high+log2ceil(s*p);
else
return minimum(max_possible_bit_opt, data_high+log2ceil(s*p));
end if ;
end function;
function adder_OL(
truncate_to_bit_opt : integer_exc;
data_low : integer)
return integer is
begin
if truncate_to_bit_opt = integer'low then
return data_low;
else
return truncate_to_bit_opt;
end if ;
end function;
/********************************************************************************************** 3 */
/*
function pipeline_is_present(
possible_positions : positive;
pipelines : natural;
level : natural)
return boolean is
begin
return ite(pipeline_positions_ref(possible_positions)(pipelines)(level)='1', true, false);
end function;
function pipeline_positions_ref(
number: positive)
return sulv_v is
begin
case number is
when 1 => return PIPELINE_POSITIONS.P1;
when 2 => return PIPELINE_POSITIONS.P2;
when 3 => return PIPELINE_POSITIONS.P3;
when 4 => return PIPELINE_POSITIONS.P4;
when 5 => return PIPELINE_POSITIONS.P5;
when 6 => return PIPELINE_POSITIONS.P6;
when 7 => return PIPELINE_POSITIONS.P7;
when 8 => return PIPELINE_POSITIONS.P8;
when 9 => return PIPELINE_POSITIONS.P9;
when 10 => return PIPELINE_POSITIONS.P10;
when 11 => return PIPELINE_POSITIONS.P11;
when 12 => return PIPELINE_POSITIONS.P12;
when others => assert false
report "tried to access nonexistent member of PIPELINE_POSITIONS"
severity failure;
return PIPELINE_POSITIONS.P12;
end case;
end function;
*/
/********************************************************************************************** 4 */
function signals_per_level(
P, level : natural)
return natural is
begin
if level=0 then
return P;
else
return signals_per_level(natural(ceil(real(P)/2.0)), level-1);
end if;
end function signals_per_level;
end package body; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.c1541_pkg.all;
entity drive_registers is
generic (
g_audio_base : unsigned(27 downto 0) := X"0030000";
g_ram_base : unsigned(27 downto 0) := X"0060000" );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
iec_reset_o : in std_logic;
use_c64_reset : out std_logic;
power : out std_logic;
drv_reset : out std_logic;
drive_address : out std_logic_vector(1 downto 0);
floppy_inserted : out std_logic;
write_prot_n : out std_logic;
bank_is_ram : out std_logic_vector(7 downto 0);
dirty_led_n : out std_logic;
stop_on_freeze : out std_logic;
param_write : out std_logic;
param_ram_en : out std_logic;
param_addr : out std_logic_vector(10 downto 0);
param_wdata : out std_logic_vector(7 downto 0);
param_rdata : in std_logic_vector(7 downto 0);
track : in std_logic_vector(6 downto 0);
mode : in std_logic;
motor_on : in std_logic );
end;
architecture rtl of drive_registers is
signal dirty_bits : std_logic_vector(63 downto 0) := (others => '0');
signal any_dirty : std_logic;
signal irq_en : std_logic;
signal wr, wd : std_logic;
signal wa : integer range 0 to 63 := 0;
signal param_ack : std_logic;
signal power_i : std_logic;
signal drv_reset_i : std_logic;
signal use_c64_reset_i : std_logic;
signal drive_address_i : std_logic_vector(1 downto 0);
signal sensor_i : std_logic;
signal bank_is_ram_i : std_logic_vector(7 downto 0);
signal inserted_i : std_logic;
signal stop_when_frozen : std_logic;
begin
p_reg: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
param_ack <= '0';
wr <= '0';
wa <= to_integer(unsigned(track(6 downto 1)));
if mode = '0' and motor_on='1' and inserted_i='1' then
wr <= '1';
wd <= '1';
any_dirty <= '1';
end if;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(12 downto 11) is
when "00" => -- registers
case io_req.address(3 downto 0) is
when c_drvreg_power =>
power_i <= io_req.data(0);
when c_drvreg_reset =>
drv_reset_i <= io_req.data(0);
use_c64_reset_i <= io_req.data(1);
stop_when_frozen <= io_req.data(2);
when c_drvreg_address =>
drive_address_i <= io_req.data(1 downto 0);
when c_drvreg_sensor =>
sensor_i <= io_req.data(0);
when c_drvreg_inserted =>
inserted_i <= io_req.data(0);
when c_drvreg_rammap =>
bank_is_ram_i <= io_req.data;
when c_drvreg_anydirty =>
any_dirty <= '0';
when c_drvreg_dirtyirq =>
irq_en <= io_req.data(0);
when others =>
null;
end case;
when "01" => -- dirty block
wr <= '1';
wa <= to_integer(io_req.address(5 downto 0));
wd <= '0';
when "10" => -- param block
null;
when others => -- unused
null;
end case;
end if; -- write
if io_req.read='1' then
case io_req.address(12 downto 11) is
when "00" => -- registers
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_drvreg_power =>
io_resp.data(0) <= power_i;
when c_drvreg_reset =>
io_resp.data(0) <= drv_reset_i;
io_resp.data(1) <= use_c64_reset_i;
io_resp.data(2) <= stop_when_frozen;
when c_drvreg_address =>
io_resp.data(1 downto 0) <= drive_address_i;
when c_drvreg_sensor =>
io_resp.data(0) <= sensor_i;
when c_drvreg_inserted =>
io_resp.data(0) <= inserted_i;
when c_drvreg_rammap =>
io_resp.data <= bank_is_ram_i;
when c_drvreg_anydirty =>
io_resp.data(0) <= any_dirty;
when c_drvreg_dirtyirq =>
io_resp.data(0) <= irq_en;
when c_drvreg_track =>
io_resp.data(6 downto 0) <= track(6 downto 0);
when c_drvreg_status =>
io_resp.data(0) <= motor_on;
io_resp.data(1) <= not mode; -- mode is '0' when writing
when c_drvreg_memmap =>
io_resp.data <= std_logic_vector(g_ram_base(23 downto 16));
when c_drvreg_audiomap =>
io_resp.data <= std_logic_vector(g_audio_base(23 downto 16));
when others =>
null;
end case;
when "01" => -- dirty block
io_resp.ack <= '1';
io_resp.data(0) <= dirty_bits(to_integer(io_req.address(5 downto 0)));
when "10" => -- param block
param_ack <= '1';
when others =>
io_resp.ack <= '1';
end case;
end if; -- read
-- param response
if param_ack='1' then
io_resp.ack <= '1';
io_resp.data <= param_rdata;
end if;
-- write into memory array
if wr='1' then
dirty_bits(wa) <= wd;
end if;
drv_reset <= drv_reset_i or iec_reset_o;
if reset='1' then
power_i <= '0';
drv_reset_i <= '1';
drive_address_i <= (others => '0');
sensor_i <= '0';
bank_is_ram_i <= (others => '0');
inserted_i <= '0';
use_c64_reset_i <= '1';
any_dirty <= '0';
irq_en <= '0';
wd <= '0';
end if;
end if;
end process;
param_write <= '1' when io_req.write='1' and io_req.address(12 downto 11)="10" else '0';
param_ram_en <= '1' when (io_req.write='1' or io_req.read='1') and io_req.address(12 downto 11)="10" else '0';
param_addr <= std_logic_vector(io_req.address(10 downto 0));
param_wdata <= io_req.data;
power <= power_i;
drive_address <= drive_address_i;
floppy_inserted <= inserted_i;
write_prot_n <= sensor_i;
bank_is_ram <= bank_is_ram_i;
dirty_led_n <= not any_dirty;
use_c64_reset <= use_c64_reset_i;
stop_on_freeze <= stop_when_frozen;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.c1541_pkg.all;
entity drive_registers is
generic (
g_audio_base : unsigned(27 downto 0) := X"0030000";
g_ram_base : unsigned(27 downto 0) := X"0060000" );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
iec_reset_o : in std_logic;
use_c64_reset : out std_logic;
power : out std_logic;
drv_reset : out std_logic;
drive_address : out std_logic_vector(1 downto 0);
floppy_inserted : out std_logic;
write_prot_n : out std_logic;
bank_is_ram : out std_logic_vector(7 downto 0);
dirty_led_n : out std_logic;
stop_on_freeze : out std_logic;
param_write : out std_logic;
param_ram_en : out std_logic;
param_addr : out std_logic_vector(10 downto 0);
param_wdata : out std_logic_vector(7 downto 0);
param_rdata : in std_logic_vector(7 downto 0);
track : in std_logic_vector(6 downto 0);
mode : in std_logic;
motor_on : in std_logic );
end;
architecture rtl of drive_registers is
signal dirty_bits : std_logic_vector(63 downto 0) := (others => '0');
signal any_dirty : std_logic;
signal irq_en : std_logic;
signal wr, wd : std_logic;
signal wa : integer range 0 to 63 := 0;
signal param_ack : std_logic;
signal power_i : std_logic;
signal drv_reset_i : std_logic;
signal use_c64_reset_i : std_logic;
signal drive_address_i : std_logic_vector(1 downto 0);
signal sensor_i : std_logic;
signal bank_is_ram_i : std_logic_vector(7 downto 0);
signal inserted_i : std_logic;
signal stop_when_frozen : std_logic;
begin
p_reg: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
param_ack <= '0';
wr <= '0';
wa <= to_integer(unsigned(track(6 downto 1)));
if mode = '0' and motor_on='1' and inserted_i='1' then
wr <= '1';
wd <= '1';
any_dirty <= '1';
end if;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(12 downto 11) is
when "00" => -- registers
case io_req.address(3 downto 0) is
when c_drvreg_power =>
power_i <= io_req.data(0);
when c_drvreg_reset =>
drv_reset_i <= io_req.data(0);
use_c64_reset_i <= io_req.data(1);
stop_when_frozen <= io_req.data(2);
when c_drvreg_address =>
drive_address_i <= io_req.data(1 downto 0);
when c_drvreg_sensor =>
sensor_i <= io_req.data(0);
when c_drvreg_inserted =>
inserted_i <= io_req.data(0);
when c_drvreg_rammap =>
bank_is_ram_i <= io_req.data;
when c_drvreg_anydirty =>
any_dirty <= '0';
when c_drvreg_dirtyirq =>
irq_en <= io_req.data(0);
when others =>
null;
end case;
when "01" => -- dirty block
wr <= '1';
wa <= to_integer(io_req.address(5 downto 0));
wd <= '0';
when "10" => -- param block
null;
when others => -- unused
null;
end case;
end if; -- write
if io_req.read='1' then
case io_req.address(12 downto 11) is
when "00" => -- registers
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_drvreg_power =>
io_resp.data(0) <= power_i;
when c_drvreg_reset =>
io_resp.data(0) <= drv_reset_i;
io_resp.data(1) <= use_c64_reset_i;
io_resp.data(2) <= stop_when_frozen;
when c_drvreg_address =>
io_resp.data(1 downto 0) <= drive_address_i;
when c_drvreg_sensor =>
io_resp.data(0) <= sensor_i;
when c_drvreg_inserted =>
io_resp.data(0) <= inserted_i;
when c_drvreg_rammap =>
io_resp.data <= bank_is_ram_i;
when c_drvreg_anydirty =>
io_resp.data(0) <= any_dirty;
when c_drvreg_dirtyirq =>
io_resp.data(0) <= irq_en;
when c_drvreg_track =>
io_resp.data(6 downto 0) <= track(6 downto 0);
when c_drvreg_status =>
io_resp.data(0) <= motor_on;
io_resp.data(1) <= not mode; -- mode is '0' when writing
when c_drvreg_memmap =>
io_resp.data <= std_logic_vector(g_ram_base(23 downto 16));
when c_drvreg_audiomap =>
io_resp.data <= std_logic_vector(g_audio_base(23 downto 16));
when others =>
null;
end case;
when "01" => -- dirty block
io_resp.ack <= '1';
io_resp.data(0) <= dirty_bits(to_integer(io_req.address(5 downto 0)));
when "10" => -- param block
param_ack <= '1';
when others =>
io_resp.ack <= '1';
end case;
end if; -- read
-- param response
if param_ack='1' then
io_resp.ack <= '1';
io_resp.data <= param_rdata;
end if;
-- write into memory array
if wr='1' then
dirty_bits(wa) <= wd;
end if;
drv_reset <= drv_reset_i or iec_reset_o;
if reset='1' then
power_i <= '0';
drv_reset_i <= '1';
drive_address_i <= (others => '0');
sensor_i <= '0';
bank_is_ram_i <= (others => '0');
inserted_i <= '0';
use_c64_reset_i <= '1';
any_dirty <= '0';
irq_en <= '0';
wd <= '0';
end if;
end if;
end process;
param_write <= '1' when io_req.write='1' and io_req.address(12 downto 11)="10" else '0';
param_ram_en <= '1' when (io_req.write='1' or io_req.read='1') and io_req.address(12 downto 11)="10" else '0';
param_addr <= std_logic_vector(io_req.address(10 downto 0));
param_wdata <= io_req.data;
power <= power_i;
drive_address <= drive_address_i;
floppy_inserted <= inserted_i;
write_prot_n <= sensor_i;
bank_is_ram <= bank_is_ram_i;
dirty_led_n <= not any_dirty;
use_c64_reset <= use_c64_reset_i;
stop_on_freeze <= stop_when_frozen;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.c1541_pkg.all;
entity drive_registers is
generic (
g_audio_base : unsigned(27 downto 0) := X"0030000";
g_ram_base : unsigned(27 downto 0) := X"0060000" );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
iec_reset_o : in std_logic;
use_c64_reset : out std_logic;
power : out std_logic;
drv_reset : out std_logic;
drive_address : out std_logic_vector(1 downto 0);
floppy_inserted : out std_logic;
write_prot_n : out std_logic;
bank_is_ram : out std_logic_vector(7 downto 0);
dirty_led_n : out std_logic;
stop_on_freeze : out std_logic;
param_write : out std_logic;
param_ram_en : out std_logic;
param_addr : out std_logic_vector(10 downto 0);
param_wdata : out std_logic_vector(7 downto 0);
param_rdata : in std_logic_vector(7 downto 0);
track : in std_logic_vector(6 downto 0);
mode : in std_logic;
motor_on : in std_logic );
end;
architecture rtl of drive_registers is
signal dirty_bits : std_logic_vector(63 downto 0) := (others => '0');
signal any_dirty : std_logic;
signal irq_en : std_logic;
signal wr, wd : std_logic;
signal wa : integer range 0 to 63 := 0;
signal param_ack : std_logic;
signal power_i : std_logic;
signal drv_reset_i : std_logic;
signal use_c64_reset_i : std_logic;
signal drive_address_i : std_logic_vector(1 downto 0);
signal sensor_i : std_logic;
signal bank_is_ram_i : std_logic_vector(7 downto 0);
signal inserted_i : std_logic;
signal stop_when_frozen : std_logic;
begin
p_reg: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
param_ack <= '0';
wr <= '0';
wa <= to_integer(unsigned(track(6 downto 1)));
if mode = '0' and motor_on='1' and inserted_i='1' then
wr <= '1';
wd <= '1';
any_dirty <= '1';
end if;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(12 downto 11) is
when "00" => -- registers
case io_req.address(3 downto 0) is
when c_drvreg_power =>
power_i <= io_req.data(0);
when c_drvreg_reset =>
drv_reset_i <= io_req.data(0);
use_c64_reset_i <= io_req.data(1);
stop_when_frozen <= io_req.data(2);
when c_drvreg_address =>
drive_address_i <= io_req.data(1 downto 0);
when c_drvreg_sensor =>
sensor_i <= io_req.data(0);
when c_drvreg_inserted =>
inserted_i <= io_req.data(0);
when c_drvreg_rammap =>
bank_is_ram_i <= io_req.data;
when c_drvreg_anydirty =>
any_dirty <= '0';
when c_drvreg_dirtyirq =>
irq_en <= io_req.data(0);
when others =>
null;
end case;
when "01" => -- dirty block
wr <= '1';
wa <= to_integer(io_req.address(5 downto 0));
wd <= '0';
when "10" => -- param block
null;
when others => -- unused
null;
end case;
end if; -- write
if io_req.read='1' then
case io_req.address(12 downto 11) is
when "00" => -- registers
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_drvreg_power =>
io_resp.data(0) <= power_i;
when c_drvreg_reset =>
io_resp.data(0) <= drv_reset_i;
io_resp.data(1) <= use_c64_reset_i;
io_resp.data(2) <= stop_when_frozen;
when c_drvreg_address =>
io_resp.data(1 downto 0) <= drive_address_i;
when c_drvreg_sensor =>
io_resp.data(0) <= sensor_i;
when c_drvreg_inserted =>
io_resp.data(0) <= inserted_i;
when c_drvreg_rammap =>
io_resp.data <= bank_is_ram_i;
when c_drvreg_anydirty =>
io_resp.data(0) <= any_dirty;
when c_drvreg_dirtyirq =>
io_resp.data(0) <= irq_en;
when c_drvreg_track =>
io_resp.data(6 downto 0) <= track(6 downto 0);
when c_drvreg_status =>
io_resp.data(0) <= motor_on;
io_resp.data(1) <= not mode; -- mode is '0' when writing
when c_drvreg_memmap =>
io_resp.data <= std_logic_vector(g_ram_base(23 downto 16));
when c_drvreg_audiomap =>
io_resp.data <= std_logic_vector(g_audio_base(23 downto 16));
when others =>
null;
end case;
when "01" => -- dirty block
io_resp.ack <= '1';
io_resp.data(0) <= dirty_bits(to_integer(io_req.address(5 downto 0)));
when "10" => -- param block
param_ack <= '1';
when others =>
io_resp.ack <= '1';
end case;
end if; -- read
-- param response
if param_ack='1' then
io_resp.ack <= '1';
io_resp.data <= param_rdata;
end if;
-- write into memory array
if wr='1' then
dirty_bits(wa) <= wd;
end if;
drv_reset <= drv_reset_i or iec_reset_o;
if reset='1' then
power_i <= '0';
drv_reset_i <= '1';
drive_address_i <= (others => '0');
sensor_i <= '0';
bank_is_ram_i <= (others => '0');
inserted_i <= '0';
use_c64_reset_i <= '1';
any_dirty <= '0';
irq_en <= '0';
wd <= '0';
end if;
end if;
end process;
param_write <= '1' when io_req.write='1' and io_req.address(12 downto 11)="10" else '0';
param_ram_en <= '1' when (io_req.write='1' or io_req.read='1') and io_req.address(12 downto 11)="10" else '0';
param_addr <= std_logic_vector(io_req.address(10 downto 0));
param_wdata <= io_req.data;
power <= power_i;
drive_address <= drive_address_i;
floppy_inserted <= inserted_i;
write_prot_n <= sensor_i;
bank_is_ram <= bank_is_ram_i;
dirty_led_n <= not any_dirty;
use_c64_reset <= use_c64_reset_i;
stop_on_freeze <= stop_when_frozen;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.c1541_pkg.all;
entity drive_registers is
generic (
g_audio_base : unsigned(27 downto 0) := X"0030000";
g_ram_base : unsigned(27 downto 0) := X"0060000" );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
iec_reset_o : in std_logic;
use_c64_reset : out std_logic;
power : out std_logic;
drv_reset : out std_logic;
drive_address : out std_logic_vector(1 downto 0);
floppy_inserted : out std_logic;
write_prot_n : out std_logic;
bank_is_ram : out std_logic_vector(7 downto 0);
dirty_led_n : out std_logic;
stop_on_freeze : out std_logic;
param_write : out std_logic;
param_ram_en : out std_logic;
param_addr : out std_logic_vector(10 downto 0);
param_wdata : out std_logic_vector(7 downto 0);
param_rdata : in std_logic_vector(7 downto 0);
track : in std_logic_vector(6 downto 0);
mode : in std_logic;
motor_on : in std_logic );
end;
architecture rtl of drive_registers is
signal dirty_bits : std_logic_vector(63 downto 0) := (others => '0');
signal any_dirty : std_logic;
signal irq_en : std_logic;
signal wr, wd : std_logic;
signal wa : integer range 0 to 63 := 0;
signal param_ack : std_logic;
signal power_i : std_logic;
signal drv_reset_i : std_logic;
signal use_c64_reset_i : std_logic;
signal drive_address_i : std_logic_vector(1 downto 0);
signal sensor_i : std_logic;
signal bank_is_ram_i : std_logic_vector(7 downto 0);
signal inserted_i : std_logic;
signal stop_when_frozen : std_logic;
begin
p_reg: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
param_ack <= '0';
wr <= '0';
wa <= to_integer(unsigned(track(6 downto 1)));
if mode = '0' and motor_on='1' and inserted_i='1' then
wr <= '1';
wd <= '1';
any_dirty <= '1';
end if;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(12 downto 11) is
when "00" => -- registers
case io_req.address(3 downto 0) is
when c_drvreg_power =>
power_i <= io_req.data(0);
when c_drvreg_reset =>
drv_reset_i <= io_req.data(0);
use_c64_reset_i <= io_req.data(1);
stop_when_frozen <= io_req.data(2);
when c_drvreg_address =>
drive_address_i <= io_req.data(1 downto 0);
when c_drvreg_sensor =>
sensor_i <= io_req.data(0);
when c_drvreg_inserted =>
inserted_i <= io_req.data(0);
when c_drvreg_rammap =>
bank_is_ram_i <= io_req.data;
when c_drvreg_anydirty =>
any_dirty <= '0';
when c_drvreg_dirtyirq =>
irq_en <= io_req.data(0);
when others =>
null;
end case;
when "01" => -- dirty block
wr <= '1';
wa <= to_integer(io_req.address(5 downto 0));
wd <= '0';
when "10" => -- param block
null;
when others => -- unused
null;
end case;
end if; -- write
if io_req.read='1' then
case io_req.address(12 downto 11) is
when "00" => -- registers
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_drvreg_power =>
io_resp.data(0) <= power_i;
when c_drvreg_reset =>
io_resp.data(0) <= drv_reset_i;
io_resp.data(1) <= use_c64_reset_i;
io_resp.data(2) <= stop_when_frozen;
when c_drvreg_address =>
io_resp.data(1 downto 0) <= drive_address_i;
when c_drvreg_sensor =>
io_resp.data(0) <= sensor_i;
when c_drvreg_inserted =>
io_resp.data(0) <= inserted_i;
when c_drvreg_rammap =>
io_resp.data <= bank_is_ram_i;
when c_drvreg_anydirty =>
io_resp.data(0) <= any_dirty;
when c_drvreg_dirtyirq =>
io_resp.data(0) <= irq_en;
when c_drvreg_track =>
io_resp.data(6 downto 0) <= track(6 downto 0);
when c_drvreg_status =>
io_resp.data(0) <= motor_on;
io_resp.data(1) <= not mode; -- mode is '0' when writing
when c_drvreg_memmap =>
io_resp.data <= std_logic_vector(g_ram_base(23 downto 16));
when c_drvreg_audiomap =>
io_resp.data <= std_logic_vector(g_audio_base(23 downto 16));
when others =>
null;
end case;
when "01" => -- dirty block
io_resp.ack <= '1';
io_resp.data(0) <= dirty_bits(to_integer(io_req.address(5 downto 0)));
when "10" => -- param block
param_ack <= '1';
when others =>
io_resp.ack <= '1';
end case;
end if; -- read
-- param response
if param_ack='1' then
io_resp.ack <= '1';
io_resp.data <= param_rdata;
end if;
-- write into memory array
if wr='1' then
dirty_bits(wa) <= wd;
end if;
drv_reset <= drv_reset_i or iec_reset_o;
if reset='1' then
power_i <= '0';
drv_reset_i <= '1';
drive_address_i <= (others => '0');
sensor_i <= '0';
bank_is_ram_i <= (others => '0');
inserted_i <= '0';
use_c64_reset_i <= '1';
any_dirty <= '0';
irq_en <= '0';
wd <= '0';
end if;
end if;
end process;
param_write <= '1' when io_req.write='1' and io_req.address(12 downto 11)="10" else '0';
param_ram_en <= '1' when (io_req.write='1' or io_req.read='1') and io_req.address(12 downto 11)="10" else '0';
param_addr <= std_logic_vector(io_req.address(10 downto 0));
param_wdata <= io_req.data;
power <= power_i;
drive_address <= drive_address_i;
floppy_inserted <= inserted_i;
write_prot_n <= sensor_i;
bank_is_ram <= bank_is_ram_i;
dirty_led_n <= not any_dirty;
use_c64_reset <= use_c64_reset_i;
stop_on_freeze <= stop_when_frozen;
end rtl;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.types_pkg.all;
use util.numeric_pkg.all;
use work.sys_config_pkg.all;
package sys_pkg is
constant sys_bus_bytes : natural := 2**sys_log2_bus_bytes;
constant sys_bus_bits : natural := sys_bus_bytes*byte_bits;
constant sys_transfer_size_bits : natural := bitsize(sys_log2_bus_bytes);
constant sys_max_burst_cycles : natural := 2**sys_log2_max_burst_cycles;
constant sys_burst_cycles_bits : natural := bitsize(sys_log2_max_burst_cycles);
subtype sys_paddr_type is std_ulogic_vector(sys_paddr_bits-1 downto 0);
subtype sys_bus_bytes_type is std_ulogic_vector2(sys_bus_bytes-1 downto 0, byte_bits-1 downto 0);
subtype sys_bus_type is std_ulogic_vector(sys_bus_bits-1 downto 0);
subtype sys_transfer_size_type is std_ulogic_vector(sys_transfer_size_bits-1 downto 0);
subtype sys_burst_cycles_type is std_ulogic_vector(sys_burst_cycles_bits-1 downto 0);
type sys_master_ctrl_out_type is record
-- a request is being made
request : std_ulogic;
-- big endian if true, otherwise little endian
be : std_ulogic;
-- this request is a write
write : std_ulogic;
-- this request is cacheable
cacheable : std_ulogic;
-- this request is privileged
priv : std_ulogic;
-- this request is for an instruction
inst : std_ulogic;
-- this request is part of a burst, but not the last request
burst : std_ulogic;
-- wrapping burst
bwrap : std_ulogic;
-- size of burst
bcycles : sys_burst_cycles_type;
end record;
type sys_master_dp_out_type is record
size : sys_transfer_size_type;
paddr : sys_paddr_type;
data : sys_bus_type;
end record;
type sys_slave_ctrl_out_type is record
ready : std_ulogic;
error : std_ulogic;
end record;
type sys_slave_dp_out_type is record
data : sys_bus_type;
end record;
type sys_master_ctrl_out_vector_type is array(natural range <>) of sys_master_ctrl_out_type;
type sys_master_dp_out_vector_type is array(natural range <>) of sys_master_dp_out_type;
type sys_slave_ctrl_out_vector_type is array(natural range <>) of sys_slave_ctrl_out_type;
type sys_slave_dp_out_vector_type is array(natural range <>) of sys_slave_dp_out_type;
end package;
|
package pack is
type rec is record
x : bit_vector(1 to 3);
y : integer;
end record;
type rec_array is array (natural range <>) of rec;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
generic ( n : positive );
end entity;
architecture test of sub is
signal s : rec_array(1 to n);
begin
p1: process is
begin
assert s = ( 1 to n => (x => "000", y => integer'low) );
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack.all;
entity record37 is
end entity;
architecture test of record37 is
begin
u1: entity work.sub generic map ( 4 );
u2: entity work.sub generic map ( 5 );
end architecture;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity stimulus_interpreter is
end entity stimulus_interpreter;
architecture test of stimulus_interpreter is
quantity temperature : real;
signal temp_sig, setting : real;
signal enable, heater_fail : bit;
begin
-- code from book
stimulus_interpreter : process is
use std.textio.all;
file control : text open read_mode is "control";
variable command : line;
variable read_ok : boolean;
variable next_time : time;
variable whitespace : character;
variable signal_id : string(1 to 4);
variable temp_value, set_value : real;
variable on_value, fail_value : bit;
begin
command_loop : while not endfile(control) loop
readline ( control, command );
-- read next stimulus time, and suspend until then
read ( command, next_time, read_ok );
if not read_ok then
report "error reading time from line: " & command.all
severity warning;
next command_loop;
end if;
wait for next_time - now;
-- skip whitespace
while command'length > 0
and ( command(command'left) = ' ' -- ordinary space
or command(command'left) = ' ' -- non-breaking space
or command(command'left) = HT ) loop
read ( command, whitespace );
end loop;
-- read signal identifier string
read ( command, signal_id, read_ok );
if not read_ok then
report "error reading signal id from line: " & command.all
severity warning;
next command_loop;
end if;
-- dispatch based on signal id
case signal_id is
when "temp" =>
read ( command, temp_value, read_ok );
if not read_ok then
report "error reading temperature value from line: "
& command.all
severity warning;
next command_loop;
end if;
temp_sig <= temp_value;
when "set " =>
-- . . . -- similar to "temp"
-- not in book
read ( command, set_value, read_ok );
if not read_ok then
report "error reading setting value from line: "
& command.all
severity warning;
next command_loop;
end if;
setting <= set_value;
-- end not in book
when "on " =>
read ( command, on_value, read_ok );
if not read_ok then
report "error reading on value from line: "
& command.all
severity warning;
next command_loop;
end if;
enable <= on_value;
when "fail" =>
-- . . . -- similar to "on "
-- not in book
read ( command, fail_value, read_ok );
if not read_ok then
report "error reading fail value from line: "
& command.all
severity warning;
next command_loop;
end if;
heater_fail <= fail_value;
-- end not in book
when others =>
report "invalid signal id in line: " & signal_id
severity warning;
next command_loop;
end case;
end loop command_loop;
wait;
end process stimulus_interpreter;
-- end code from book
-- code from book (in text)
temperature == temp_sig'ramp;
-- end code from book (in text)
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity stimulus_interpreter is
end entity stimulus_interpreter;
architecture test of stimulus_interpreter is
quantity temperature : real;
signal temp_sig, setting : real;
signal enable, heater_fail : bit;
begin
-- code from book
stimulus_interpreter : process is
use std.textio.all;
file control : text open read_mode is "control";
variable command : line;
variable read_ok : boolean;
variable next_time : time;
variable whitespace : character;
variable signal_id : string(1 to 4);
variable temp_value, set_value : real;
variable on_value, fail_value : bit;
begin
command_loop : while not endfile(control) loop
readline ( control, command );
-- read next stimulus time, and suspend until then
read ( command, next_time, read_ok );
if not read_ok then
report "error reading time from line: " & command.all
severity warning;
next command_loop;
end if;
wait for next_time - now;
-- skip whitespace
while command'length > 0
and ( command(command'left) = ' ' -- ordinary space
or command(command'left) = ' ' -- non-breaking space
or command(command'left) = HT ) loop
read ( command, whitespace );
end loop;
-- read signal identifier string
read ( command, signal_id, read_ok );
if not read_ok then
report "error reading signal id from line: " & command.all
severity warning;
next command_loop;
end if;
-- dispatch based on signal id
case signal_id is
when "temp" =>
read ( command, temp_value, read_ok );
if not read_ok then
report "error reading temperature value from line: "
& command.all
severity warning;
next command_loop;
end if;
temp_sig <= temp_value;
when "set " =>
-- . . . -- similar to "temp"
-- not in book
read ( command, set_value, read_ok );
if not read_ok then
report "error reading setting value from line: "
& command.all
severity warning;
next command_loop;
end if;
setting <= set_value;
-- end not in book
when "on " =>
read ( command, on_value, read_ok );
if not read_ok then
report "error reading on value from line: "
& command.all
severity warning;
next command_loop;
end if;
enable <= on_value;
when "fail" =>
-- . . . -- similar to "on "
-- not in book
read ( command, fail_value, read_ok );
if not read_ok then
report "error reading fail value from line: "
& command.all
severity warning;
next command_loop;
end if;
heater_fail <= fail_value;
-- end not in book
when others =>
report "invalid signal id in line: " & signal_id
severity warning;
next command_loop;
end case;
end loop command_loop;
wait;
end process stimulus_interpreter;
-- end code from book
-- code from book (in text)
temperature == temp_sig'ramp;
-- end code from book (in text)
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity stimulus_interpreter is
end entity stimulus_interpreter;
architecture test of stimulus_interpreter is
quantity temperature : real;
signal temp_sig, setting : real;
signal enable, heater_fail : bit;
begin
-- code from book
stimulus_interpreter : process is
use std.textio.all;
file control : text open read_mode is "control";
variable command : line;
variable read_ok : boolean;
variable next_time : time;
variable whitespace : character;
variable signal_id : string(1 to 4);
variable temp_value, set_value : real;
variable on_value, fail_value : bit;
begin
command_loop : while not endfile(control) loop
readline ( control, command );
-- read next stimulus time, and suspend until then
read ( command, next_time, read_ok );
if not read_ok then
report "error reading time from line: " & command.all
severity warning;
next command_loop;
end if;
wait for next_time - now;
-- skip whitespace
while command'length > 0
and ( command(command'left) = ' ' -- ordinary space
or command(command'left) = ' ' -- non-breaking space
or command(command'left) = HT ) loop
read ( command, whitespace );
end loop;
-- read signal identifier string
read ( command, signal_id, read_ok );
if not read_ok then
report "error reading signal id from line: " & command.all
severity warning;
next command_loop;
end if;
-- dispatch based on signal id
case signal_id is
when "temp" =>
read ( command, temp_value, read_ok );
if not read_ok then
report "error reading temperature value from line: "
& command.all
severity warning;
next command_loop;
end if;
temp_sig <= temp_value;
when "set " =>
-- . . . -- similar to "temp"
-- not in book
read ( command, set_value, read_ok );
if not read_ok then
report "error reading setting value from line: "
& command.all
severity warning;
next command_loop;
end if;
setting <= set_value;
-- end not in book
when "on " =>
read ( command, on_value, read_ok );
if not read_ok then
report "error reading on value from line: "
& command.all
severity warning;
next command_loop;
end if;
enable <= on_value;
when "fail" =>
-- . . . -- similar to "on "
-- not in book
read ( command, fail_value, read_ok );
if not read_ok then
report "error reading fail value from line: "
& command.all
severity warning;
next command_loop;
end if;
heater_fail <= fail_value;
-- end not in book
when others =>
report "invalid signal id in line: " & signal_id
severity warning;
next command_loop;
end case;
end loop command_loop;
wait;
end process stimulus_interpreter;
-- end code from book
-- code from book (in text)
temperature == temp_sig'ramp;
-- end code from book (in text)
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Video_PR_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S_AXI
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
-- Ports of Axi Slave Bus Interface S_AXI
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
end Video_PR_v1_0;
architecture arch_imp of Video_PR_v1_0 is
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of RGB_IN: SIGNAL is "xilinx.com:interface:vid_io:1.0 RGB_IN DATA";
ATTRIBUTE X_INTERFACE_INFO of VDE_IN: SIGNAL is "xilinx.com:interface:vid_io:1.0 RGB_IN ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO of HS_IN: SIGNAL is "xilinx.com:interface:vid_io:1.0 RGB_IN HSYNC";
ATTRIBUTE X_INTERFACE_INFO of VS_IN: SIGNAL is "xilinx.com:interface:vid_io:1.0 RGB_IN VSYNC";
ATTRIBUTE X_INTERFACE_INFO of RGB_OUT: SIGNAL is "xilinx.com:interface:vid_io:1.0 RGB_OUT DATA";
ATTRIBUTE X_INTERFACE_INFO of VDE_OUT: SIGNAL is "xilinx.com:interface:vid_io:1.0 RGB_OUT ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO of HS_OUT: SIGNAL is "xilinx.com:interface:vid_io:1.0 RGB_OUT HSYNC";
ATTRIBUTE X_INTERFACE_INFO of VS_OUT: SIGNAL is "xilinx.com:interface:vid_io:1.0 RGB_OUT VSYNC";
-- component declaration
component Video_PR_v1_0_S_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
-- Users to add ports here
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component Video_PR_v1_0_S_AXI;
begin
-- Instantiation of Axi Bus Interface S_AXI
Video_PR_v1_0_S_AXI_inst : Video_PR_v1_0_S_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
--video signals
RGB_IN => RGB_IN,
VDE_IN => VDE_IN,
HS_IN => HS_IN,
VS_IN => VS_IN,
-- additional ports here
RGB_OUT => RGB_OUT,
VDE_OUT => VDE_OUT,
HS_OUT => HS_OUT,
VS_OUT => VS_OUT,
PIXEL_CLK => PIXEL_CLK,
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWPROT => s_axi_awprot,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARPROT => s_axi_arprot,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
|
-- mem_swapping.vhd
-- Jan Viktorin <[email protected]>
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.log2;
---
-- Provides BRAM memory model that swaps
-- its contents to filesystem. This can
-- solve the issue with ISIM to not allocate
-- very huge amount of memory.
---
entity mem_swapping is
generic (
MEM_CAP : integer := 640 * 480;
MEM_LINE : integer := 19200;
DWIDTH : integer := 8;
PREFIX : string := "mem"
);
port (
CLK : in std_logic;
RST : in std_logic;
MEM_A0 : in std_logic_vector(log2(MEM_CAP) - 1 downto 0);
MEM_DIN0 : in std_logic_vector(DWIDTH - 1 downto 0);
MEM_DOUT0 : out std_logic_vector(DWIDTH - 1 downto 0);
MEM_WE0 : in std_logic_vector(DWIDTH / 8 - 1 downto 0);
MEM_RE0 : in std_logic;
MEM_DRDY0 : out std_logic;
MEM_A1 : in std_logic_vector(log2(MEM_CAP) - 1 downto 0);
MEM_DIN1 : in std_logic_vector(DWIDTH - 1 downto 0);
MEM_DOUT1 : out std_logic_vector(DWIDTH - 1 downto 0);
MEM_WE1 : in std_logic_vector(DWIDTH / 8 - 1 downto 0);
MEM_RE1 : in std_logic;
MEM_DRDY1 : out std_logic
);
end entity;
architecture full of mem_swapping is
constant ADDRW : integer := log2(MEM_CAP);
subtype memaddr_t is std_logic_vector(ADDRW - 1 downto 0);
subtype memcell_t is std_logic_vector(DWIDTH - 1 downto 0);
subtype membe_t is std_logic_vector(DWIDTH / 8 - 1 downto 0);
type mempart_t is array(0 to MEM_LINE - 1) of memcell_t;
type memfile_t is file of memcell_t;
--------------------------------------------------------
function get_memname(base : in integer) return string is
begin
assert base >= 0
report "[MEM] Invalid base for access memory: " & integer'image(base)
severity failure;
return PREFIX & "/mem_" & integer'image(base);
end function;
function to_base(addr : in memaddr_t) return integer is
begin
return (conv_integer(addr) / MEM_LINE) * MEM_LINE;
end function;
--------------------------------------------------------
procedure mem_load(base : in integer; mem : out mempart_t; dirty : out boolean) is
file fd : memfile_t;
variable fstat : file_open_status;
begin
file_open(fstat, fd, get_memname(base), READ_MODE);
if fstat /= OPEN_OK then
report "[MEM] Can not open file " & get_memname(base) & ", init to X";
for i in mem'range loop
mem(i) := (others => 'X');
end loop;
else
for i in mem'range loop
if endfile(fd) then
report "[MEM] File is shorter then memory, finished at " & integer'image(i);
exit;
end if;
read(fd, mem(i));
end loop;
-- report "[MEM] Memory reloaded";
dirty := false;
file_close(fd);
end if;
end procedure;
procedure mem_save(base : in integer; mem : in mempart_t; dirty : in boolean) is
file fd : memfile_t;
variable fstat : file_open_status;
begin
if base = -1 or dirty = false then
return;
end if;
file_open(fstat, fd, get_memname(base), WRITE_MODE);
assert fstat = OPEN_OK
report "[MEM] Can not open file " & get_memname(base)
severity failure;
for i in mem'range loop
write(fd, mem(i));
end loop;
end procedure;
procedure mem_access(mem : inout mempart_t; base : inout integer;
addr : in memaddr_t; dirty : inout boolean) is
variable newbase : integer;
begin
newbase := to_base(addr);
if newbase /= base then
report "[MEM] Reloading memory block "
& integer'image(base)
& " => "
& integer'image(newbase)
& " ("
& integer'image(conv_integer(addr))
& ")";
mem_save(base, mem, dirty);
mem_load(newbase, mem, dirty);
base := newbase;
end if;
end procedure;
--------------------------------------------------------
procedure mem_read(mem : inout mempart_t; base : inout integer;
addr : in memaddr_t; data : out memcell_t;
dirty : inout boolean) is
variable addrbase : integer;
variable addroff : integer;
begin
addrbase := to_base(addr);
addroff := conv_integer(addr) - addrbase;
mem_access(mem, base, addr, dirty);
data := mem(addroff);
end procedure;
procedure mem_write(mem : inout mempart_t; base : inout integer;
addr : in memaddr_t; data : in memcell_t;
be : in membe_t; dirty : inout boolean) is
variable addrbase : integer;
variable addroff : integer;
variable val : memcell_t;
begin
addrbase := to_base(addr);
addroff := conv_integer(addr) - addrbase;
mem_access(mem, base, addr, dirty);
val := mem(addroff);
for i in val'range loop
if be(i / 8) = '1' then
val(i) := data(i);
end if;
end loop;
if mem(addroff) /= val then
mem(addroff) := val;
dirty := true;
end if;
end procedure;
--------------------------------------------------------
shared variable mem : mempart_t;
shared variable dirty: boolean := false;
shared variable base : integer := -1;
begin
assert (MEM_CAP mod MEM_LINE) = 0
report "MEM_LINE must be multiple of MEM_CAP"
severity failure;
--------------------------------------------------------
mem_writep : process(CLK, MEM_WE0, MEM_A0, MEM_DIN0, MEM_WE1, MEM_A1, MEM_DIN1)
variable addr : memaddr_t;
variable din : memcell_t;
begin
if rising_edge(CLK) then
if MEM_WE0 /= (MEM_WE0'range => '0') then
addr := MEM_A0;
din := MEM_DIN0;
mem_write(mem, base, addr, din, MEM_WE0, dirty);
end if;
if MEM_WE1 /= (MEM_WE1'range => '0') then
addr := MEM_A1;
din := MEM_DIN1;
mem_write(mem, base, addr, din, MEM_WE1, dirty);
end if;
end if;
end process;
mem_readp : process(CLK, MEM_RE0, MEM_A0, MEM_RE1, MEM_A1)
variable addr : memaddr_t;
variable dout : memcell_t;
begin
if rising_edge(CLK) then
if MEM_RE0 = '1' then
addr := MEM_A0;
mem_read(mem, base, addr, dout, dirty);
MEM_DOUT0 <= dout;
end if;
if MEM_RE1 = '1' then
addr := MEM_A1;
mem_read(mem, base, addr, dout, dirty);
MEM_DOUT1 <= dout;
end if;
end if;
end process;
mem_drdyp : process(CLK, MEM_RE0, MEM_RE1)
begin
if rising_edge(CLK) then
if RST = '1' then
MEM_DRDY0 <= '0';
MEM_DRDY1 <= '0';
else
MEM_DRDY0 <= MEM_RE0;
MEM_DRDY1 <= MEM_RE1;
end if;
end if;
end process;
end architecture;
|
entity sub is
port ( o1 : out integer;
i1 : in real );
end entity;
architecture test of sub is
begin
p1: process is
begin
o1 <= 1;
wait for 1 ns;
o1 <= 2;
assert i1 = real(5);
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity conv3 is
end entity;
architecture test of conv3 is
signal x : real;
signal y : integer;
begin
uut: entity work.sub
port map ( real(o1) => x,
i1 => real(y) );
p2: process is
begin
assert x = real(integer'left);
wait for 0 ns;
assert x = real(1);
y <= 5;
wait for 2 ns;
assert x = real(2);
wait;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: memctrl
-- File: memctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory controller package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.log2;
library techmap;
use techmap.gencomp.all;
package memctrl is
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bwidth : std_logic_vector(1 downto 0);
sd : std_logic_vector(63 downto 0);
cb : std_logic_vector(15 downto 0);
scb : std_logic_vector(15 downto 0);
edac : std_logic;
end record;
constant memory_in_none : memory_in_type :=
((others => '0'), '0', '0', '0', (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), '0');
type memory_out_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
sddata : std_logic_vector(63 downto 0);
ramsn : std_logic_vector(7 downto 0);
ramoen : std_logic_vector(7 downto 0);
ramn : std_ulogic;
romn : std_ulogic;
mben : std_logic_vector(3 downto 0);
iosn : std_logic;
romsn : std_logic_vector(7 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
vbdrive : std_logic_vector(31 downto 0); --vector bus drive
svbdrive : std_logic_vector(63 downto 0); --vector bus drive sdram
read : std_logic;
sa : std_logic_vector(14 downto 0);
cb : std_logic_vector(15 downto 0);
scb : std_logic_vector(15 downto 0);
vcdrive : std_logic_vector(15 downto 0); --vector bus drive cb
svcdrive : std_logic_vector(15 downto 0); --vector bus drive cb sdram
ce : std_ulogic;
sdram_en : std_ulogic; -- SDRAM enabled
rs_edac_en : std_ulogic; -- Reed-Solomon enabled
end record;
constant memory_out_none : memory_out_type :=
((others => '0'), (others => '0'), (others => '0'), (others => '1'),
(others => '1'), '1', '1', (others => '1'), '1', (others => '1'),
'1', '1', (others => '1'), (others => '1'), (others => '1'),
(others => '1'), '0', (others => '0'), (others => '1'), (others => '1'),
(others => '1'), (others => '1'), '0', '0', '0');
type sdctrl_in_type is record
wprot : std_ulogic;
data : std_logic_vector (127 downto 0); -- data in
cb : std_logic_vector(63 downto 0);
regrdata : std_logic_vector(63 downto 0); -- PHY-specific reg in
datavalid : std_logic; -- Data-valid signal
end record;
constant sdctrl_in_none : sdctrl_in_type :=
('0', (others => '0'), (others => '0'), (others => '0'), '0');
type sdctrl_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
xsdcsn : std_logic_vector ( 7 downto 0); -- ext. chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 15 downto 0); -- data i/o mask
bdrive : std_ulogic; -- bus drive
qdrive : std_ulogic; -- bus drive
nbdrive : std_ulogic; -- bdrive 1 cycle early
vbdrive : std_logic_vector(63 downto 0); -- vector bus drive
address : std_logic_vector (16 downto 2); -- address out
data : std_logic_vector (127 downto 0); -- data out
cb : std_logic_vector(63 downto 0);
ce : std_ulogic;
ba : std_logic_vector (2 downto 0); -- bank address
sdck : std_logic_vector(2 downto 0);
moben : std_logic; -- Mobile support
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay
cal_pll : std_logic_vector(1 downto 0); -- (enable,inc/dec) pll phase
cal_rst : std_logic; -- calibration reset
odt : std_logic_vector(1 downto 0); -- In Die Termination
conf : std_logic_vector(63 downto 0);
oct : std_logic; -- On Chip Termination
vcbdrive : std_logic_vector(31 downto 0); -- cb vector bus drive
dqs_gate : std_logic;
cbdqm : std_logic_vector(7 downto 0);
cbcal_en : std_logic_vector(3 downto 0);
cbcal_inc : std_logic_vector(3 downto 0);
read_pend : std_logic_vector(7 downto 0); -- Read pending within 7...0
-- cycles (not including phy delays)
-- PHY-specific register interface
regwdata : std_logic_vector(63 downto 0);
regwrite : std_logic_vector(1 downto 0);
end record;
constant sdctrl_out_none : sdctrl_out_type :=
((others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'),
'0', '0', '0', (others => '0'), (others => '0'), (others => '0'),
(others => '0'), '0', (others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), '0', (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'), "00000000",
(others => '0'), "00");
type sdram_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 7 downto 0); -- data i/o mask
end record;
type zbtssram_out_type is record
cen : std_ulogic;
oen : std_ulogic;
wen : std_ulogic;
advld : std_ulogic;
addr : std_logic_vector(22 downto 0);
bwn : std_logic_vector(15 downto 0);
data : std_logic_vector(127 downto 0);
dqoen : std_logic_vector(127 downto 0);
zz : std_ulogic;
shutdown : std_ulogic;
end record;
constant zbtssram_out_none : zbtssram_out_type := (
'1','1','1','1',(others => '0'),(others => '1'),(others => '0'),(others => '1'),'0','0');
type zbtssram_in_type is record
data : std_logic_vector(127 downto 0);
mbe : std_logic_vector(7 downto 0);
end record;
constant zbtssram_in_none : zbtssram_in_type := ( data => (others => '0'), mbe => (others => '0') );
component sdctrl
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component sdctrl64
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ftsdctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
edacen : integer := 1;
errcnt : integer := 0;
cntbits : integer range 1 to 8 := 1;
oepol : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ftsdctrl64
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0;
edac : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component srctrl
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
prom8en : integer := 0;
oepol : integer := 0;
srbanks : integer range 1 to 5 := 1;
banksz : integer range 0 to 13 := 13;
romasel : integer range 0 to 28 := 19
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ftsrctrl is
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
rombanks : integer range 1 to 8 := 1;
rombanksz : integer range 0 to 15 := 15;
rombankszdef : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 0;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0;
prom8en : integer := 0;
netlist : integer := 0;
tech : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
type sdram_in_type is record
haddr : std_logic_vector(31 downto 0); -- memory address
rhaddr : std_logic_vector(31 downto 0); -- latched memory address
hready : std_ulogic;
hsize : std_logic_vector(1 downto 0);
hsel : std_ulogic;
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
rhtrans : std_logic_vector(1 downto 0);
nhtrans : std_logic_vector(1 downto 0);
idle : std_ulogic;
enable : std_ulogic;
error : std_ulogic;
merror : std_ulogic;
brmw : std_ulogic;
edac : std_ulogic;
srdis : std_logic;
end record;
type sdram_mctrl_out_type is record
address : std_logic_vector(16 downto 2);
busy : std_ulogic;
aload : std_ulogic;
bdrive : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
bsel : std_ulogic;
hresp : std_logic_vector (1 downto 0);
vhready : std_ulogic;
prdata : std_logic_vector (31 downto 0);
end record;
type wprot_out_type is record
wprothit : std_ulogic;
end record;
component sdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftsdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
syncrst : integer := 0;
pageburst : integer := 0;
edac : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftmctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
edac : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
writefb : integer := 0;
netlist : integer := 0;
tech : integer := 0;
rahold : integer := 0;
wsshift : integer := 0;
brdynto : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end component;
component ssrctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
paddr : integer := 0;
pmask : integer := 16#fff#;
oepol : integer := 0;
bus16 : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
component ftsrctrl_v1
generic (
hindex: Integer := 1;
romaddr: Integer := 16#000#;
rommask: Integer := 16#ff0#;
ramaddr: Integer := 16#400#;
rammask: Integer := 16#ff0#;
ioaddr: Integer := 16#200#;
iomask: Integer := 16#ff0#;
ramws: Integer := 0;
romws: Integer := 0;
iows: Integer := 0;
rmw: Integer := 1;
srbanks: Integer range 1 to 8 := 8;
banksz: Integer range 0 to 13 := 0;
rombanks: Integer range 1 to 8 := 8;
rombanksz: Integer range 0 to 13 := 0;
rombankszdef: Integer range 0 to 13 := 6;
romasel: Integer range 0 to 28 := 0;
pindex: Integer := 0;
paddr: Integer := 16#000#;
pmask: Integer := 16#fff#;
edacen: Integer range 0 to 1 := 1;
errcnt: Integer range 0 to 1 := 0;
cntbits: Integer range 1 to 8 := 1;
wsreg: Integer := 1;
oepol: Integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ftsrctrl8 is
generic (
hindex : integer := 0;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
iows : integer := 2;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 1;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
component p8ctrl
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 0;
iomask : integer := 16#ff0#;
ioaddr : integer := 0;
rammask : integer := 16#ff0#;
romws : integer := 15;
ramws : integer := 15;
prom8en : integer := 0;
rmw : integer := 0;
oepol : integer := 0;
romasel : integer range 0 to 28 := 23
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb1_ulpi_phy_bfm is
generic (
g_rx_interval : integer := 100 );
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : out std_logic;
ULPI_NXT : out std_logic;
ULPI_STP : in std_logic );
end usb1_ulpi_phy_bfm;
architecture gideon of usb1_ulpi_phy_bfm is
type t_state is (idle, sending, receiving, read_reg, read_reg2, read_reg3, write_reg, status_update);
signal state : t_state;
signal pattern : std_logic_vector(0 to 19);
signal do_send : std_logic;
signal counter : unsigned(7 downto 0) := X"01";
signal status_in : std_logic_vector(7 downto 0) := X"00";
signal status_d : std_logic_vector(7 downto 0) := X"00";
signal ulpi_nxt_i : std_logic;
signal ulpi_dir_i : std_logic;
alias ulpi_cmd : std_logic_vector(1 downto 0) is ULPI_DATA(7 downto 6);
constant c_transmit : std_logic_vector(1 downto 0) := "01";
constant c_write_reg : std_logic_vector(1 downto 0) := "10";
constant c_read_reg : std_logic_vector(1 downto 0) := "11";
begin
process(clock)
variable byte_count : integer := 0;
variable rx_interval : integer := g_rx_interval;
variable address : std_logic_vector(5 downto 0);
procedure set_reg(addr: std_logic_vector(5 downto 0);
data: std_logic_vector(7 downto 0) ) is
begin
if addr = "001010" then
if data(5)='1' or data(6)='1' then-- poweron
report "Power On";
if status_in(3)='0' then
status_in(3 downto 2) <= transport "00",
"01" after 10 us,
"10" after 20 us,
"11" after 30 us;
end if;
else -- power off
report "Power Off";
status_in(3 downto 2) <= transport "11",
"10" after 1 us,
"01" after 2 us,
"00" after 3 us;
end if;
end if;
if addr = "000100" then
case data(2 downto 0) is
when "000" => -- host chirp
status_in(1 downto 0) <= transport "00", "10" after 10 us, "00" after 15 us;
when "001"|"011" => -- powerup
status_in(1 downto 0) <= "11";
when "010" => -- unknown
status_in(1 downto 0) <= "00";
when "100" => -- peripheral chirp
status_in(1 downto 0) <= "10";
when "101"|"111" => -- peripheral FS
status_in(1 downto 0) <= "01";
when "110" => -- peripheral LS
status_in(1 downto 0) <= "10";
when others =>
null;
end case;
end if;
end procedure;
begin
if rising_edge(clock) then
if rx_interval = 0 then
do_send <= '0'; -- autonomous send disabled
rx_interval := g_rx_interval;
else
rx_interval := rx_interval - 1;
end if;
ulpi_nxt_i <= '0';
case state is
when idle =>
status_d <= status_in;
ulpi_dir_i <= '0';
ULPI_DATA <= (others => 'Z');
if do_send = '1' then
do_send <= '0';
ulpi_dir_i <= '1';
ulpi_nxt_i <= '1';
pattern <= "01111101111011101101";
state <= sending;
byte_count := 20;
elsif ulpi_dir_i = '0' then
if ulpi_cmd = c_transmit then
pattern <= "11111111100111011010";
state <= receiving;
elsif ulpi_cmd = c_write_reg then
address := ULPI_DATA(5 downto 0);
byte_count := 2;
state <= write_reg;
elsif ulpi_cmd = c_read_reg then
state <= read_reg;
elsif status_in /= status_d then
ulpi_dir_i <= '1';
state <= status_update;
end if;
end if;
when status_update =>
ULPI_DATA <= status_d;
state <= idle;
when sending =>
pattern <= pattern(1 to 19) & '0';
if pattern(0)='1' then
ULPI_DATA <= std_logic_vector(counter);
ulpi_nxt_i <= '1';
counter <= counter + 1;
else
ULPI_DATA <= status_in;
ulpi_nxt_i <= '0';
end if;
byte_count := byte_count - 1;
if byte_count = 0 then
state <= idle;
end if;
when receiving =>
if ULPI_STP = '1' then
ulpi_nxt_i <= '0';
state <= idle;
else
ulpi_nxt_i <= pattern(0);
pattern <= pattern(1 to 19) & '1';
end if;
when write_reg =>
if byte_count = 0 then
ulpi_nxt_i <= '0';
set_reg(address, ULPI_DATA);
else
ulpi_nxt_i <= '1';
end if;
byte_count := byte_count - 1;
if ULPI_STP = '1' then
state <= idle;
end if;
when read_reg =>
ulpi_nxt_i <= '1';
state <= read_reg2;
when read_reg2 =>
ulpi_dir_i <= '1';
state <= read_reg3;
when read_reg3 =>
ULPI_DATA <= X"AA";
state <= idle;
when others =>
state <= idle;
end case;
if reset='1' then
state <= idle;
end if;
end if;
end process;
ULPI_NXT <= ulpi_nxt_i;
ULPI_DIR <= ulpi_dir_i;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb1_ulpi_phy_bfm is
generic (
g_rx_interval : integer := 100 );
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : out std_logic;
ULPI_NXT : out std_logic;
ULPI_STP : in std_logic );
end usb1_ulpi_phy_bfm;
architecture gideon of usb1_ulpi_phy_bfm is
type t_state is (idle, sending, receiving, read_reg, read_reg2, read_reg3, write_reg, status_update);
signal state : t_state;
signal pattern : std_logic_vector(0 to 19);
signal do_send : std_logic;
signal counter : unsigned(7 downto 0) := X"01";
signal status_in : std_logic_vector(7 downto 0) := X"00";
signal status_d : std_logic_vector(7 downto 0) := X"00";
signal ulpi_nxt_i : std_logic;
signal ulpi_dir_i : std_logic;
alias ulpi_cmd : std_logic_vector(1 downto 0) is ULPI_DATA(7 downto 6);
constant c_transmit : std_logic_vector(1 downto 0) := "01";
constant c_write_reg : std_logic_vector(1 downto 0) := "10";
constant c_read_reg : std_logic_vector(1 downto 0) := "11";
begin
process(clock)
variable byte_count : integer := 0;
variable rx_interval : integer := g_rx_interval;
variable address : std_logic_vector(5 downto 0);
procedure set_reg(addr: std_logic_vector(5 downto 0);
data: std_logic_vector(7 downto 0) ) is
begin
if addr = "001010" then
if data(5)='1' or data(6)='1' then-- poweron
report "Power On";
if status_in(3)='0' then
status_in(3 downto 2) <= transport "00",
"01" after 10 us,
"10" after 20 us,
"11" after 30 us;
end if;
else -- power off
report "Power Off";
status_in(3 downto 2) <= transport "11",
"10" after 1 us,
"01" after 2 us,
"00" after 3 us;
end if;
end if;
if addr = "000100" then
case data(2 downto 0) is
when "000" => -- host chirp
status_in(1 downto 0) <= transport "00", "10" after 10 us, "00" after 15 us;
when "001"|"011" => -- powerup
status_in(1 downto 0) <= "11";
when "010" => -- unknown
status_in(1 downto 0) <= "00";
when "100" => -- peripheral chirp
status_in(1 downto 0) <= "10";
when "101"|"111" => -- peripheral FS
status_in(1 downto 0) <= "01";
when "110" => -- peripheral LS
status_in(1 downto 0) <= "10";
when others =>
null;
end case;
end if;
end procedure;
begin
if rising_edge(clock) then
if rx_interval = 0 then
do_send <= '0'; -- autonomous send disabled
rx_interval := g_rx_interval;
else
rx_interval := rx_interval - 1;
end if;
ulpi_nxt_i <= '0';
case state is
when idle =>
status_d <= status_in;
ulpi_dir_i <= '0';
ULPI_DATA <= (others => 'Z');
if do_send = '1' then
do_send <= '0';
ulpi_dir_i <= '1';
ulpi_nxt_i <= '1';
pattern <= "01111101111011101101";
state <= sending;
byte_count := 20;
elsif ulpi_dir_i = '0' then
if ulpi_cmd = c_transmit then
pattern <= "11111111100111011010";
state <= receiving;
elsif ulpi_cmd = c_write_reg then
address := ULPI_DATA(5 downto 0);
byte_count := 2;
state <= write_reg;
elsif ulpi_cmd = c_read_reg then
state <= read_reg;
elsif status_in /= status_d then
ulpi_dir_i <= '1';
state <= status_update;
end if;
end if;
when status_update =>
ULPI_DATA <= status_d;
state <= idle;
when sending =>
pattern <= pattern(1 to 19) & '0';
if pattern(0)='1' then
ULPI_DATA <= std_logic_vector(counter);
ulpi_nxt_i <= '1';
counter <= counter + 1;
else
ULPI_DATA <= status_in;
ulpi_nxt_i <= '0';
end if;
byte_count := byte_count - 1;
if byte_count = 0 then
state <= idle;
end if;
when receiving =>
if ULPI_STP = '1' then
ulpi_nxt_i <= '0';
state <= idle;
else
ulpi_nxt_i <= pattern(0);
pattern <= pattern(1 to 19) & '1';
end if;
when write_reg =>
if byte_count = 0 then
ulpi_nxt_i <= '0';
set_reg(address, ULPI_DATA);
else
ulpi_nxt_i <= '1';
end if;
byte_count := byte_count - 1;
if ULPI_STP = '1' then
state <= idle;
end if;
when read_reg =>
ulpi_nxt_i <= '1';
state <= read_reg2;
when read_reg2 =>
ulpi_dir_i <= '1';
state <= read_reg3;
when read_reg3 =>
ULPI_DATA <= X"AA";
state <= idle;
when others =>
state <= idle;
end case;
if reset='1' then
state <= idle;
end if;
end if;
end process;
ULPI_NXT <= ulpi_nxt_i;
ULPI_DIR <= ulpi_dir_i;
end gideon;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 05-03-2017
-- Module Name: controller.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity controller is
port (register_load, register_shift : out std_logic;
clk, rst : in std_logic);
end entity;
architecture rtl of controller is
type state is (S0, S1, S2, S3, S4);
signal current_state : state;
signal next_state : state;
begin
-- next to current
process (clk, rst)
begin
if rst = '1' then
current_state <= S0;
elsif clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
-- next based on state
process (current_state)
begin
case current_state is
when S0 =>
next_state <= S1;
register_load <= '1';
register_shift <= '0';
when S1 =>
next_state <= S2;
register_load <= '0';
register_shift <= '1';
when S2 =>
next_state <= S3;
when S3 =>
next_state <= S4;
when S4 =>
next_state <= S0;
end case;
end process;
end architecture;
|
-- *** MOCS-COPYRIGHT-NOTICE-BEGIN ***
--
-- This copyright notice is auto-generated by ./add-copyright-notice.
-- Additional copyright notices must be added below the last line of this notice.
--
-- MoCS (https://lewis.cs.uni-saarland.de/tools/mocs/): "vhdl/pipeline.vhdl".
-- The content of this file is copyright of Saarland University -
-- Copyright (C) 2009 Saarland University, Reactive Systems Group, Lars Kuhtz.
--
-- This file is part of MoCS (https://lewis.cs.uni-saarland.de/tools/mocs/).
--
-- License: three-clause BSD style license.
-- The license text can be found in the file LICENSE.
--
-- *** MOCS-COPYRIGHT-NOTICE-END ***
-- ----------------------------------------------------------------- --
-- use work.general.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
-- the pipeline for a single prop
entity pipeline is
generic (LENGTH : integer := 32);
Port (CLOCK : in STD_LOGIC;
input : in STD_LOGIC;
output : out unsigned(LENGTH downto 0));
end pipeline;
architecture Behavioral of pipeline is
signal tmp : unsigned(LENGTH - 1 downto 0);
begin
process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then
if (LENGTH > 1) then
tmp <= tmp(LENGTH - 2 downto 0) & input;
elsif (LENGTH = 1) then
tmp <= "" & input;
end if;
end if;
end process;
output <= tmp & input;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity topo_contador is
port (BTN0, SEL_LED, CLOCK_50: in std_logic;
SEL_DISP: in std_logic_vector(1 downto 0);
CONTA_ASC: out std_logic_vector(19 downto 0);
CONTA_DESC: out std_logic_vector(9 downto 0)
);
end topo_contador;
architecture topo_contador_arch of topo_contador is
signal CLK1, CLK2: std_logic;
signal CONTA_ASC1: std_logic_vector(15 downto 0);
signal RST_CONT, RST_DESC: std_logic;
component FSM_clock
port( clock, reset: in std_logic;
c1, c2: out std_logic
);
end component;
component Cont_desc
port ( CLK1, rst, en: in std_logic;
S: out std_logic_vector(9 downto 0)
);
end component;
component Cont_asc
port ( clk, rst: in std_logic;
s: out std_logic_vector(15 downto 0)
);
end component;
begin
RST_CONT <= '0' when BTN0 = '0' or SEL_DISP = "00" or SEL_DISP = "01" or SEL_DISP = "10" else
'1';--lógica de reset do contador ascendente, conforme a saída SEL_DISP que vem da FSM_control ou o acionamento do BTN0.
RST_DESC <= '0' when BTN0 = '0' or SEL_DISP = "00" else
'1';--lógica de reset do contador descendente do saldo.
L0: FSM_clock port map(CLOCK_50, BTN0, CLK1, CLK2);
L1: Cont_desc port map(CLK2, RST_DESC, SEL_LED, CONTA_DESC);
L2: Cont_asc port map(CLK1, RST_CONT, CONTA_ASC1);
CONTA_ASC <= '0' & CONTA_ASC1(15 downto 12) & '0' & CONTA_ASC1(11 downto 8) & '0' & CONTA_ASC1(7 downto 4) & '0' & CONTA_ASC1(3 downto 0);
--concatenação de um zero aos sinais de 4 bits criados para contagem dos segundos e minutos do contador ascendente.
end topo_contador_arch; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc463.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00463ent IS
END c03s02b01x01p19n01i00463ent;
ARCHITECTURE c03s02b01x01p19n01i00463arch OF c03s02b01x01p19n01i00463ent IS
subtype delay is integer range 1 to 10;
constant C66 : delay := 2;
function complex_scalar(s : delay) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return delay is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : delay;
signal S2 : delay;
signal S3 : delay:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00463"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00463 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00463arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc463.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00463ent IS
END c03s02b01x01p19n01i00463ent;
ARCHITECTURE c03s02b01x01p19n01i00463arch OF c03s02b01x01p19n01i00463ent IS
subtype delay is integer range 1 to 10;
constant C66 : delay := 2;
function complex_scalar(s : delay) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return delay is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : delay;
signal S2 : delay;
signal S3 : delay:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00463"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00463 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00463arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc463.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00463ent IS
END c03s02b01x01p19n01i00463ent;
ARCHITECTURE c03s02b01x01p19n01i00463arch OF c03s02b01x01p19n01i00463ent IS
subtype delay is integer range 1 to 10;
constant C66 : delay := 2;
function complex_scalar(s : delay) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return delay is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : delay;
signal S2 : delay;
signal S3 : delay:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00463"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00463 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00463arch;
|
package fifo_pkg is
end package fifo_pkg;
package fifo_pkg is
end package FIFO_PKG;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:02:19 09/10/2014
-- Design Name:
-- Module Name: /home/gsanchez/Apps/TP_01/TB_GenParidad.vhd
-- Project Name: TP_01
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: GenParidad
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_GenParidad IS
END TB_GenParidad;
ARCHITECTURE behavior OF TB_GenParidad IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT GenParidad
PORT(
E : IN std_logic_vector(3 downto 0);
P : IN std_logic;
S : OUT std_logic_vector(4 downto 0)
);
END COMPONENT;
--Inputs
signal E : std_logic_vector(3 downto 0) := (others => '0');
signal P : std_logic := '0';
--Outputs
signal S : std_logic_vector(4 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: GenParidad PORT MAP (
E => E,
P => P,
S => S
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
for Paridad in 0 to 1 loop
P <= std_logic(to_unsigned(Paridad,1)(0));
for Ent in 0 to 15 loop
E <= std_logic_vector(to_unsigned(Ent,4));
wait for 10 ns;
end loop;
end loop;
wait for 100 ns;
-- wait for <clock>_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_1_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:50:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_1_e-rtl-a.vhd,v 1.4 2006/06/26 07:42:18 wig Exp $
-- $Date: 2006/06/26 07:42:18 $
-- $Log: inst_1_e-rtl-a.vhd,v $
-- Revision 1.4 2006/06/26 07:42:18 wig
-- Updated io, generic and mde_tests testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_1_e
--
architecture rtl of inst_1_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 22 02:51:56 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/system_vga_sync_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_0_0_vga_sync is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_0_0_vga_sync : entity is "vga_sync";
end system_vga_sync_0_0_vga_sync;
architecture STRUCTURE of system_vga_sync_0_0_vga_sync is
signal active0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal active_i_3_n_0 : STD_LOGIC;
signal \h_count_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal hsync_i_1_n_0 : STD_LOGIC;
signal hsync_i_2_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal sel : STD_LOGIC;
signal \v_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal vsync_i_1_n_0 : STD_LOGIC;
signal \^xaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^yaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of active_i_3 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of hsync_i_2 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_5\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair1";
begin
xaddr(9 downto 0) <= \^xaddr\(9 downto 0);
yaddr(9 downto 0) <= \^yaddr\(9 downto 0);
active_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00000A2A"
)
port map (
I0 => active_i_3_n_0,
I1 => \^xaddr\(8),
I2 => \^xaddr\(9),
I3 => \^xaddr\(7),
I4 => \^yaddr\(9),
O => active0
);
active_i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rst,
O => active_i_2_n_0
);
active_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(5),
I2 => \^yaddr\(6),
I3 => \^yaddr\(8),
O => active_i_3_n_0
);
active_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => active0,
Q => active
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(0),
O => p_0_in(0)
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
O => p_0_in(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
I2 => \^xaddr\(2),
O => p_0_in(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
O => p_0_in(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(3),
O => p_0_in(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"33332333CCCCCCCC"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(5),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \^xaddr\(7),
I5 => \h_count_reg[9]_i_2_n_0\,
O => p_0_in(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(5),
I2 => \h_count_reg[9]_i_2_n_0\,
O => p_0_in(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^xaddr\(7),
I1 => \h_count_reg[9]_i_2_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(6),
O => p_0_in(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FFFFFF7C0000000"
)
port map (
I0 => \^xaddr\(9),
I1 => \h_count_reg[9]_i_2_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(7),
I4 => \^xaddr\(6),
I5 => \^xaddr\(8),
O => \h_count_reg[8]_i_1_n_0\
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F80EF00FF00FF00"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(5),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \^xaddr\(7),
I5 => \h_count_reg[9]_i_2_n_0\,
O => p_0_in(9)
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
I2 => \^xaddr\(2),
I3 => \^xaddr\(4),
I4 => \^xaddr\(3),
O => \h_count_reg[9]_i_2_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => p_0_in(0),
Q => \^xaddr\(0)
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => p_0_in(1),
Q => \^xaddr\(1)
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => p_0_in(2),
Q => \^xaddr\(2)
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => p_0_in(3),
Q => \^xaddr\(3)
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => p_0_in(4),
Q => \^xaddr\(4)
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => p_0_in(5),
Q => \^xaddr\(5)
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => p_0_in(6),
Q => \^xaddr\(6)
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => p_0_in(7),
Q => \^xaddr\(7)
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => \h_count_reg[8]_i_1_n_0\,
Q => \^xaddr\(8)
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => p_0_in(9),
Q => \^xaddr\(9)
);
hsync_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFBFBFBFBFFF"
)
port map (
I0 => \^xaddr\(8),
I1 => \^xaddr\(9),
I2 => \^xaddr\(7),
I3 => hsync_i_2_n_0,
I4 => \^xaddr\(5),
I5 => \^xaddr\(6),
O => hsync_i_1_n_0
);
hsync_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(3),
I3 => \^xaddr\(1),
I4 => \^xaddr\(0),
O => hsync_i_2_n_0
);
hsync_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => hsync_i_1_n_0,
Q => hsync
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555555554"
)
port map (
I0 => \^yaddr\(0),
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(7),
I3 => \^yaddr\(4),
I4 => \^yaddr\(8),
I5 => \^yaddr\(6),
O => \p_0_in__0\(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => \p_0_in__0\(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"78007878"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
I2 => \^yaddr\(2),
I3 => \v_count_reg[9]_i_4_n_0\,
I4 => \v_count_reg[9]_i_3_n_0\,
O => \p_0_in__0\(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F8000007F807F80"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(0),
I2 => \^yaddr\(2),
I3 => \^yaddr\(3),
I4 => \v_count_reg[9]_i_4_n_0\,
I5 => \v_count_reg[9]_i_3_n_0\,
O => \p_0_in__0\(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(0),
I4 => \^yaddr\(1),
O => \p_0_in__0\(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^yaddr\(5),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(3),
I4 => \^yaddr\(2),
I5 => \^yaddr\(4),
O => \p_0_in__0\(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^yaddr\(6),
I1 => \v_count_reg[9]_i_6_n_0\,
I2 => \^yaddr\(5),
O => \p_0_in__0\(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(5),
I2 => \v_count_reg[9]_i_6_n_0\,
I3 => \^yaddr\(6),
O => \p_0_in__0\(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^yaddr\(8),
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \v_count_reg[9]_i_6_n_0\,
O => \p_0_in__0\(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000002000"
)
port map (
I0 => \h_count_reg[9]_i_2_n_0\,
I1 => \^xaddr\(7),
I2 => \^xaddr\(9),
I3 => \^xaddr\(8),
I4 => \^xaddr\(5),
I5 => \^xaddr\(6),
O => sel
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"D00DD0D0D0D0D0D0"
)
port map (
I0 => \v_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \v_count_reg[9]_i_5_n_0\,
I4 => \^yaddr\(8),
I5 => \v_count_reg[9]_i_6_n_0\,
O => \p_0_in__0\(9)
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(4),
I2 => \^yaddr\(8),
I3 => \^yaddr\(6),
O => \v_count_reg[9]_i_3_n_0\
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFFFFFFFFFFFFFF"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(0),
I2 => \^yaddr\(5),
I3 => \^yaddr\(9),
I4 => \^yaddr\(2),
I5 => \^yaddr\(3),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^yaddr\(6),
I1 => \^yaddr\(5),
I2 => \^yaddr\(7),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(0),
I4 => \^yaddr\(1),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(0),
Q => \^yaddr\(0)
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(1),
Q => \^yaddr\(1)
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(2),
Q => \^yaddr\(2)
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(3),
Q => \^yaddr\(3)
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(4),
Q => \^yaddr\(4)
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(5),
Q => \^yaddr\(5)
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(6),
Q => \^yaddr\(6)
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(7),
Q => \^yaddr\(7)
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(8),
Q => \^yaddr\(8)
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(9),
Q => \^yaddr\(9)
);
vsync_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEFFFFFFFFF"
)
port map (
I0 => active_i_3_n_0,
I1 => \^yaddr\(9),
I2 => \^yaddr\(3),
I3 => \^yaddr\(4),
I4 => \^yaddr\(2),
I5 => \^yaddr\(1),
O => vsync_i_1_n_0
);
vsync_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => vsync_i_1_n_0,
Q => vsync
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_0_0 : entity is "system_vga_sync_0_0,vga_sync,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_0_0 : entity is "vga_sync,Vivado 2016.4";
end system_vga_sync_0_0;
architecture STRUCTURE of system_vga_sync_0_0 is
begin
U0: entity work.system_vga_sync_0_0_vga_sync
port map (
active => active,
clk => clk,
hsync => hsync,
rst => rst,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
|
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY PI_Controller IS
PORT ( error : IN INTEGER ;
control : OUT INTEGER;
clk : in std_logic;
reset : in std_logic) ;
END PI_Controller;
architecture Behavioral of PI_Controller is
signal u1: std_logic_vector(15 downto 0);
constant k1: std_logic_vector( 6 downto 0 ):="1101011";
begin
process( clk)
begin
end process;
end Behavioral; |
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY PI_Controller IS
PORT ( error : IN INTEGER ;
control : OUT INTEGER;
clk : in std_logic;
reset : in std_logic) ;
END PI_Controller;
architecture Behavioral of PI_Controller is
signal u1: std_logic_vector(15 downto 0);
constant k1: std_logic_vector( 6 downto 0 ):="1101011";
begin
process( clk)
begin
end process;
end Behavioral; |
----------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2014 Brian K. Nemetz
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Brian Nemetz
--
-- Create Date: 08:18:42 10/26/2012
-- Design Name:
-- Module Name: classicHp_top - rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.classic_pack.all;
use work.ps2_keyboard_pack.all;
use work.rom_pack.all;
use work.tm16xxFonts.all;
entity classichp_top is
generic (
UART_TYPE : string := "TX_RX"; -- Should be: "NONE", "TX", "RX", or "TX_RX"
CALC_NAME : string := "HP55" -- Should be: "HP55", "HP45", or "HP35"
);
port ( clk_i : in std_logic;
rst_i : in std_logic;
ps2_clk_i : in std_logic;
ps2_data_i : in std_logic;
uart_rx_i : in std_logic;
dis_clk_o : out std_logic;
dis_data_o : out std_logic;
uart_tx_o : out std_logic;
leds_o : out std_logic_vector (3 downto 0)
);
end classichp_top;
architecture rtl of classichp_top is
-- Configure for the calculator desired:
constant HP35 : boolean := CALC_NAME="HP35";
constant HP45 : boolean := CALC_NAME="HP45";
constant HP55 : boolean := CALC_NAME="HP55";
constant CALC_ROM : RomType := IIF(HP55, ROM_55, IIF(HP45, ROM_45, ROM_35));
constant KEY_LUT : keyLutType := IIF(HP55, KEY_LUT_HP55, IIF(HP45, KEY_LUT_HP45, KEY_LUT_HP35));
-- Configure for UART type desired:
constant UART_TX : boolean := UART_TYPE="TX" or UART_TYPE="TX_RX";
constant UART_RX : boolean := UART_TYPE="RX" or UART_TYPE="TX_RX";
-- constant CLK_FREQ : natural := 7000000; -- sysClk Rate
constant CLK_FREQ : natural := 84000000; -- sysClk Rate
constant CLK_EN_CNT : natural := CLK_FREQ/1000000; -- CLK_EN_CNT is how many sysClk periods in 1us
-- definition for "HP-x5" where x is 3, 4, or 5 (padded out to 14 chars)
constant LED_SIGNON : ledFontRomType := (
LED_SPACE,
LED_MINUS,
LED_MINUS,
LED_SPACE,
LED_H, -- 'H'
LED_P, -- 'P'
LED_DASH, -- '-'
IIF(HP55, LED_5, IIF(HP45, LED_4, LED_3)), -- '3', '4', or '5'
LED_5, -- '5'
LED_SPACE,
LED_MINUS,
LED_MINUS,
LED_SPACE,
LED_SPACE
);
type ledFsmType is (IDLE, START, SEND1, SEND2, SEND3, END1, END2, END3, END4);
type disLedFsmType is (CMD1, CMD2, CMD2W, T0, T1, DIS_CMD1, DIS_CMD2, DIS_EX1,
DIS_EX2, ERROR_D, SIGNON_D, SIGNON_W);
subtype clkEnCntType is natural range 0 to CLK_EN_CNT-1;
type byteArrayType is array (natural range <>) of std_logic_vector(7 downto 0);
subtype idxCntType is natural range 0 to 13;
subtype ledCntType is natural range 0 to 7;
constant DELAY_100MS : natural := 100000
-- synthesis translate_off
- 99996
-- synthesis translate_on
;
constant DELAY_10MS : natural := 10000
-- synthesis translate_off
- 9996
-- synthesis translate_on
;
constant DELAY_5MS : natural := 5000
-- synthesis translate_off
- 4996
-- synthesis translate_on
;
constant DELAY_200US : natural := 200
-- synthesis translate_off
- 198
-- synthesis translate_on
;
constant DELAY_10US : natural := 10
-- synthesis translate_off
- 8
-- synthesis translate_on
;
-- delay for creating real timing of the original HP-55 => 3500 instructions per sec
-- ex: if sysClk is 7MHz: 7Mhz/3500 = 2000
constant DELAY_INST : natural := CLK_FREQ/3500
-- synthesis translate_off
- (CLK_FREQ/3500 - 10)
-- synthesis translate_on
;
subtype delayCntType is natural range 0 to DELAY_5MS-1;
subtype keyCntType is natural range 0 to DELAY_10MS-1;
subtype pCntType is natural range 0 to DELAY_100MS-1;
subtype instCntType is natural range 0 to DELAY_INST-1;
signal sysRst : std_logic;
signal sysRstLow : std_logic;
signal sysClk : std_logic;
signal error : std_logic;
signal status : std_logic_vector(11 downto 0);
signal flagsR : std_logic_vector(11 downto 0);
signal xreg : std_logic_vector(55 downto 0);
signal mask : std_logic_vector(55 downto 0);
signal clkEnR : std_logic;
signal clkEnCntR : clkEnCntType;
signal ledFsmR : ledFsmType;
signal ledSendR : std_logic;
signal ledStartR : std_logic;
signal ledEndR : std_logic;
signal ledDoneR : std_logic;
signal ledClkR : std_logic;
signal ledDataR : std_logic;
signal ledSendDataR : std_logic_vector(7 downto 0);
signal ledBrightR : unsigned(2 downto 0);
signal ledCntR : ledCntType;
signal xregLedR : std_logic_vector(55 downto 0);
signal maskLedR : std_logic_vector(55 downto 0);
signal ps2ClkR : std_logic;
signal ps2ClkRR : std_logic;
signal ps2ClkRRR : std_logic;
signal keyRdyR : std_logic;
signal keyRdyLongR : std_logic;
signal keyRdy : std_logic;
signal keyData : std_logic_vector(7 downto 0);
signal keyDataR : std_logic_vector(7 downto 0);
signal uartKeyRdyR : std_logic;
signal uartKeyDataR : std_logic_vector(7 downto 0);
signal ps2KeyRdy : std_logic;
signal ps2KeyData : std_logic_vector(7 downto 0);
signal disLedFsmR : disLedFsmType;
signal indexLedR : idxCntType;
signal ledFirstR : std_logic;
signal ledExDigit1R : std_logic_vector(7 downto 0);
signal ledExDigit2R : std_logic_vector(7 downto 0);
signal keyCntR : keyCntType;
signal instCntR : instCntType;
signal instEnR : std_logic;
signal realSpeedEnR : std_logic;
signal displayEn : std_logic;
begin
-- test outputs
leds_o(0) <= uart_rx_i;
leds_o(1) <= '0';
leds_o(2) <= clkEnR;
leds_o(3) <= '0';
-- Xilinx DCM primitive is within this component.
-- This is one thing that has to change if targetting a different FPGA.
dcm : entity work.sys_dcm(behavioral)
port map (
CLKIN_IN => clk_i,
RST_IN => rst_i,
CLKFX_OUT => sysClk,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open,
LOCKED_OUT => sysRstLow
);
sysRst <= not sysRstLow;
hpCore: entity work.classic(rtl)
generic map (
CALC_NAME => CALC_NAME,
ROM => CALC_ROM
)
PORT MAP (
clk_i => sysClk,
rst_i => sysRst,
inst_en_i => instEnR,
flags_i => flagsR,
keycode_i => keyDataR,
keyvalid_i => keyRdyLongR,
display_en_o => displayEn,
error_o => error,
xreg_o => xreg,
mask_o => mask,
status_o => status
);
-- This is the PS/2 interface and will return calculator keycodes (plus a few
-- special codes).
ps2 : entity work.ps2_keyboard(rtl)
generic map (KEY_LUT => KEY_LUT)
port map(
rst_i => sysRst,
clk_i => sysClk, -- needs to be faster than ps2_clk_i
ps2_data_i => ps2_data_i,
ps2_clk_i => ps2_clk_i,
key_rdy_o => ps2KeyRdy, -- one clock cycle pulse, notify a new byte has arrived
key_data_o => ps2KeyData
);
-- choose between UART and PS/2 keyboard input
keyRdy <= ps2KeyRdy or uartKeyRdyR;
keyData <= ps2KeyData when ps2KeyRdy='1' else uartKeyDataR;
-- Create a clock enable pulse every 1us. This is for general timing of
-- slower things.
clk_en : process (sysClk, sysRst)
begin
if sysRst = '1' then
clkEnCntR <= 0;
clkEnR <= '0';
elsif rising_edge(sysClk) then
if clkEnCntR = CLK_EN_CNT-1 then
clkEnR <= '1';
clkEnCntR <= 0;
else
clkEnR <= '0';
clkEnCntR <= clkEnCntR+1;
end if;
end if;
end process clk_en;
-- Create an enable pulse every micro-instruction execution time.
-- For slowing down the core to the same speed as the original HP-55.
inst_en : process (sysClk, sysRst)
begin
if sysRst = '1' then
instCntR <= 0;
instEnR <= '1';
elsif rising_edge(sysClk) then
if realSpeedEnR /= '1' or instCntR = instCntType'high then
instEnR <= '1';
instCntR <= 0;
else
instEnR <= '0';
instCntR <= instCntR+1;
end if;
end if;
end process inst_en;
-- We need to create a stretched key ready signal for the core on each new
-- keyboard input. This is needed since the calculator micro-code is still
-- doing key debouncing. We hold each key active for 10ms -- this should be
-- long enough for the core to "see" the key press (in real or turbo speed
-- mode).
key_stretch : process (sysClk, sysRst)
begin
if sysRst = '1' then
keyCntR <= 0;
keyRdyLongR <= '0';
elsif rising_edge(sysClk) then
if keyRdyLongR = '0' and keyRdyR = '1' then
keyRdyLongR <= '1';
keyCntR <= 0;
end if;
if clkEnR = '1' and keyRdyLongR = '1' then
if keyCntR = keyCntType'high then
keyRdyLongR <= '0';
else
keyCntR <= keyCntR+1;
end if;
end if;
end if;
end process key_stretch;
-- clock process for sync'ing FFs for the PS/2 clock input. This input
-- is async to the internal FPGA clock.
-- (The underlying PS/2 module does not seem to do this.)
clk_proc : process (sysClk, sysRst)
begin
if sysRst = '1' then
ps2ClkR <= '0';
ps2ClkRR <= '0';
ps2ClkRR <= '0';
elsif rising_edge(sysClk) then
ps2ClkR <= ps2_clk_i;
ps2ClkRR <= ps2ClkR;
ps2ClkRRR <= ps2ClkRR;
end if;
end process clk_proc;
-- Handle new key presses.
keypress : process (sysClk, sysRst)
begin
if sysRst = '1' then
keyDataR <= (others => '0');
flagsR <= (others => '0');
keyRdyR <= '0';
realSpeedEnR <= '0';
ledBrightR <= "100";
elsif rising_edge(sysClk) then
if keyRdy = '1' then keyDataR <= keyData; end if;
-- Key codes with the lower three bits set are special keys and are not
-- sent to the calculator core.
if keyRdy = '1' and keyData(2 downto 0) /= "111" then keyRdyR <= '1'; else keyRdyR <= '0'; end if;
if keyRdy = '1' and keyData(2 downto 0) = "111" then
if keyData = x"3F" then
-- change the brighness of the LED display
if ledBrightR = "000" then
ledBrightR <= (others => '1');
else
ledBrightR <= ledBrightR - 1;
end if;
elsif keyData = x"27" then
-- Fast speed
if HP55 then
if flagsR(11) /= '1' then
-- only allow fast speed when not in timer mode
realSpeedEnR <= '0';
end if;
else
realSpeedEnR <= '0';
end if;
elsif keyData = x"1F" then
-- RealSpeed
realSpeedEnR <= '1';
elsif keyData = x"07" and HP55 then
flagsR <= (others => '0'); -- Switch in RUN mode
elsif keyData = x"0F" and HP55 then
flagsR <= (others => '0');
flagsR(3) <= '1'; -- Switch in PROG mode
elsif keyData = x"17" and HP55 then
flagsR <= (others => '0');
flagsR(11) <= '1'; -- Switch in TIMER mode
realSpeedEnR <= '1'; -- need to be in realspeed mode for timer to be correct
end if;
end if;
end if;
end process keypress;
-----------------------------------------
-- Start of the UART driver
-----------------------------------------
UART_YES : if UART_TX or UART_RX generate
begin
RX_YES : if UART_RX generate
constant KEY_PREFIX : std_logic_vector(7 downto 0) := x"0F";
constant CMD_PREFIX : std_logic_vector(7 downto 0) := x"F0";
type fsmType is (IDLE, GET_KEY, GET_CMD);
signal fsmR : fsmType;
signal dataRcv : std_logic_vector(7 downto 0);
signal rxSerial : std_logic;
signal rxDataAv : std_logic;
begin
uut_rx: entity work.uart_rx(rtl)
generic map (
CLK_HZ => CLK_FREQ,
BAUD => 115200
)
port map (
clk_i => sysClk,
rst_i => sysRst,
rx_i => rxSerial,
data_o => dataRcv,
val_o => rxDataAv
);
rxSerial <= uart_rx_i;
rx_fsm : process (sysClk, sysRst)
begin
if sysRst = '1' then
fsmR <= IDLE;
uartKeyRdyR <= '0';
uartKeyDataR <= (others => '0');
elsif rising_edge(sysClk) then
uartKeyRdyR <= '0';
case fsmR is
when IDLE =>
if rxDataAv = '1' and dataRcv = KEY_PREFIX then
-- A keycode is being received
fsmR <= GET_KEY;
elsif rxDataAv = '1' and dataRcv = CMD_PREFIX then
-- A command is being received
fsmR <= GET_CMD;
end if;
when GET_KEY =>
if rxDataAv = '1' then
uartKeyRdyR <= '1';
uartKeyDataR <= dataRcv;
fsmR <= IDLE;
end if;
when GET_CMD =>
if rxDataAv = '1' then
uartKeyRdyR <= '1';
uartKeyDataR <= dataRcv;
fsmR <= IDLE;
end if;
end case;
end if;
end process rx_fsm;
end generate RX_YES;
RX_NO : if not UART_RX generate
begin
uartKeyRdyR <= '0';
uartKeyDataR <= (others => '0');
end generate RX_NO;
TX_YES : if UART_TX generate
constant PREFIX : std_logic_vector(7 downto 0) := x"FA";
constant BYTES : natural := WSIZE/2;
subtype byteCntType is natural range 0 to BYTES-1;
type fsmType is (IDLE, SEND_XREG, SEND_MASK, SEND_FLAGS);
signal fsmR : fsmType;
signal dataSendR : std_logic_vector(7 downto 0);
signal txSerial : std_logic;
signal txEot : std_logic;
signal txRdy : std_logic;
signal txWrEnR : std_logic;
signal cntR : byteCntType;
signal xregR : std_logic_vector(55 downto 0);
signal maskR : std_logic_vector(55 downto 0);
signal dcntR : pCntType;
signal pulseR : std_logic;
signal flags : std_logic_vector(7 downto 0);
begin
uut_tx: entity work.uart_tx(rtl)
generic map (
CLK_HZ => CLK_FREQ,
BAUD => 115200
)
port map (
clk_i => sysClk,
rst_i => sysRst,
data_i => dataSendR,
wr_i => txWrEnR,
tx_o => txSerial,
rdy_o => txRdy
);
uart_tx_o <= txSerial;
timer : process (sysClk, sysRst)
begin
if sysRst = '1' then
dcntR <= 0;
pulseR <= '0';
elsif rising_edge(sysClk) then
pulseR <= '0';
if clkEnR = '1' then
if dcntR = DELAY_100MS-1 then
dcntR <= 0;
pulseR <= '1';
else
dcntR <= dcntR + 1;
end if;
end if;
end if;
end process timer;
flags <= "0001" & realSpeedEnR & flagsR(11) & status(6) & status(4) when HP55 else
"0010" & realSpeedEnR & "00" & status(10) when HP45 else
"0100" & realSpeedEnR & "00" & status(10);
tx_fsm : process (sysClk, sysRst)
begin
if sysRst = '1' then
fsmR <= IDLE;
cntR <= 0;
txWrEnR <= '0';
maskR <= (others => '0');
xregR <= (others => '0');
dataSendR <= (others => '0');
elsif rising_edge(sysClk) then
txWrEnR <= '0';
case fsmR is
when IDLE =>
dataSendR <= PREFIX;
cntR <= 0;
maskR <= mask;
xregR <= xreg;
-- if txRdy = '1' and (maskR /= mask or xregR /= xreg) then
if txRdy = '1' and pulseR = '1' then
maskR <= mask;
xregR <= xreg;
txWrEnR <= '1';
fsmR <= SEND_XREG;
end if;
when SEND_XREG =>
dataSendR <= xregR(xregR'left downto xregR'left-7);
if txRdy = '1' then
txWrEnR <= '1';
xregR <= xregR(xregR'left-8 downto 0) & xregR(xregR'left downto xregR'left-7);
if cntR = BYTES-1 then
cntR <= 0;
fsmR <= SEND_MASK;
else
cntR <= cntR + 1;
end if;
end if;
when SEND_MASK =>
dataSendR <= maskR(maskR'left downto maskR'left-7);
if txRdy = '1' then
txWrEnR <= '1';
maskR <= maskR(maskR'left-8 downto 0) & maskR(maskR'left downto maskR'left-7);
if cntR = BYTES-1 then
fsmR <= SEND_FLAGS;
else
cntR <= cntR + 1;
end if;
end if;
when SEND_FLAGS =>
dataSendR <= flags;
if txRdy = '1' then
txWrEnR <= '1';
fsmR <= IDLE;
end if;
end case;
end if;
end process tx_fsm;
end generate TX_YES;
TX_NO : if not UART_TX generate
begin
end generate TX_NO;
end generate UART_YES;
UART_NO : if not(UART_TX or UART_RX) generate
begin
uart_tx_o <= '1';
uartKeyRdyR <= '0';
uartKeyDataR <= (others => '0');
end generate UART_NO;
-----------------------------------------
-- End of the UART driver
-----------------------------------------
-----------------------------------------
-- Start of the LED Display Module driver
-----------------------------------------
-- The led process is a low level driver for the LED display.
-- It will send one byte to the display.
-- Inputs:
-- ledSendR : pulse high to start sending byte to the display
-- ledStartR : should a start bit be sent first?
-- ledSendDataR : 8-bit data to send to the display
-- Output:
-- ledDoneR : pulses high when data has been sent
--
led : process (sysClk, sysRst)
begin
if sysRst = '1' then
ledFsmR <= IDLE;
ledDoneR <= '0';
ledClkR <= '1';
ledDataR <= '1';
ledCntR <= 0;
elsif rising_edge(sysClk) then
if clkEnR='1' then
ledDoneR <= '0';
case ledFsmR is
when IDLE =>
ledCntR <= 0;
if ledSendR = '1' then
if ledStartR = '1' then
ledFsmR <= START;
else
ledFsmR <= SEND1;
end if;
end if;
when START =>
-- Signal a "start" command: drive ledDataR low while ledClkR is high
-- Note: ledClkR is assumed to be already high
ledDataR <= '0';
ledFsmR <= SEND1;
when SEND1 =>
-- drive clock low (assumes it is high already)
ledClkR <= '0';
ledFsmR <= SEND2;
when SEND2 =>
-- drive data
ledDataR <= ledSendDataR(ledCntR);
ledFsmR <= SEND3;
when SEND3 =>
-- drive clock back high
ledClkR <= '1';
if ledCntR = 7 then
if ledEndR = '1' then
ledFsmR <= END1;
else
ledDoneR <= '1';
ledFsmR <= IDLE;
end if;
else
ledCntR <= ledCntR + 1;
ledFsmR <= SEND1;
end if;
when END1 =>
ledClkR <= '0';
ledFsmR <= END2;
when END2 =>
ledDataR <= '0';
ledFsmR <= END3;
when END3 =>
ledClkR <= '1';
ledFsmR <= END4;
when END4 =>
ledDoneR <= '1';
ledDataR <= '1';
ledFsmR <= IDLE;
end case;
end if;
end if;
end process led;
dis_clk_o <= ledClkR;
dis_data_o <= ledDataR;
-- there are two extra digits on the LED display that are not used to
-- dispaly calculator output. These two extra digits can display additiona
-- info. The first extra digit is not used, yet. The second digit is used
-- to display "shift" key status. The "shift" key status varies for each
-- calculator type.
HP35_DIS : if HP35 generate
-- The HP-35 only shift key to do arc-sin, arc-cos, and arc-tan
-- status bit indicates this.
ledExDigit1R <= LED_SPACE;
fShift : process (sysClk, sysRst)
begin
if sysRst = '1' then
ledExDigit2R <= LED_SPACE;
elsif rising_edge(sysClk) then
if status(10) = '1' then
ledExDigit2R <= LED_A;
else
ledExDigit2R <= LED_SPACE;
end if;
end if;
end process fShift;
end generate HP35_DIS;
HP45_DIS : if HP45 generate
-- The HP-45 has one shift key. Status
-- bit 10 indicates its state.
ledExDigit1R <= LED_SPACE;
fShift : process (sysClk, sysRst)
begin
if sysRst = '1' then
ledExDigit2R <= LED_SPACE;
elsif rising_edge(sysClk) then
if status(10) = '1' then
ledExDigit2R <= LED_F;
else
ledExDigit2R <= LED_SPACE;
end if;
end if;
end process fShift;
end generate HP45_DIS;
HP55_DIS : if HP55 generate
-- The HP-45 has two shift keys. Status bits 4, 6, and 11
-- need to be looked at to determine the shift key states.
ledExDigit1R <= LED_SPACE;
fgShift : process (sysClk, sysRst)
begin
if sysRst = '1' then
ledExDigit2R <= LED_SPACE;
elsif rising_edge(sysClk) then
-- Note: When in timer mode (flagsR(11) is set) status(6)
-- indicates if the timer is stopped (status(6)=1 if timer is stopped)
if status(6) = '1' and flagsR(11) /= '1' then
ledExDigit2R <= LED_F;
elsif status(4) = '1' then
ledExDigit2R <= LED_G;
else
ledExDigit2R <= LED_SPACE;
end if;
ledExDigit2R(7) <= realSpeedEnR;
end if;
end process fgShift;
end generate HP55_DIS;
-- The ledDisplay process is the higher level LED display
-- driver. It displays the current value of the X register,
-- the sign-on message or the error message.
ledDisplay : process (sysClk, sysRst, xregLedR, maskLedR)
variable bcd : std_logic_vector(3 downto 0);
variable dMask: std_logic_vector(3 downto 0);
begin
bcd := xregLedR(55 downto 52);
dMask := maskLedR(55 downto 52);
if sysRst = '1' then
disLedFsmR <= CMD1;
indexLedR <= 0;
ledStartR <= '0';
ledEndR <= '0';
ledSendR <= '0';
ledFirstR <= '1'; -- flag for the first time throught the FSM (for Sign On message)
ledSendDataR<= (others => '0');
maskLedR <= (others => '0');
xregLedR <= (others => '0');
elsif rising_edge(sysClk) then
if clkEnR='1' then
ledSendR <= '0';
case disLedFsmR is
when CMD1 =>
maskLedR <= mask;
xregLedR <= xreg;
indexLedR <= 0;
ledSendDataR <= "01000000"; -- Data Mode: Address Auto + 1
ledSendR <= '1';
ledEndR <= '1';
-- if realSpeedEnR /= '1' or displayEn = '1' then
if ledFirstR = '1' or error = '1' or displayEn = '1' then
ledStartR <= '1';
disLedFsmR <= CMD2;
end if;
when CMD2 =>
if ledDoneR = '1' then
ledSendDataR <= x"C0" or x"00"; -- set address
ledStartR <= '1';
ledSendR <= '1';
ledEndR <= '0';
if ledFirstR = '1' then
disLedFsmR <= SIGNON_D;
elsif error = '1' then
disLedFsmR <= ERROR_D;
else
disLedFsmR <= CMD2W;
end if;
end if;
when SIGNON_D =>
if ledDoneR = '1' then
ledSendDataR <= LED_SIGNON(indexLedR);
ledStartR <= '0';
ledSendR <= '1';
if indexLedR = 13 then
ledEndR <= '0';
disLedFsmR <= DIS_EX1;
else
indexLedR <= indexLedR + 1;
ledEndR <= '0';
end if;
end if;
when ERROR_D =>
if ledDoneR = '1' then
ledSendDataR <= LED_ERROR(indexLedR);
ledStartR <= '0';
ledSendR <= '1';
if indexLedR = 13 then
ledEndR <= '0';
disLedFsmR <= DIS_EX1;
else
indexLedR <= indexLedR + 1;
ledEndR <= '0';
end if;
end if;
when CMD2W =>
if ledDoneR = '1' then
disLedFsmR <= T0;
end if;
when T0 =>
if dMask = "1001" then
ledSendDataR <= LED_SPACE; -- space
else
if indexLedR=11 or indexLedR=0 then -- the two sign positions
if bcd = "1001" then
if dMask = "0000" then
ledSendDataR <= LED_MINUS; -- '-'
else
ledSendDataR <= LED_MINUS or LED_DP; -- '-.'
end if;
else
if dMask = "0000" then
ledSendDataR <= LED_SPACE; -- space
else
ledSendDataR <= LED_0 or LED_DP; -- space
end if;
end if;
elsif dMask = "0000" then
ledSendDataR <= LED_HEX_FONT(to_integer(unsigned(bcd)));
else
ledSendDataR <= LED_HEX_FONT(to_integer(unsigned(bcd))) or LED_DP;
end if;
end if;
ledStartR <= '0';
ledSendR <= '1';
if indexLedR = 13 then
ledEndR <= '0';
disLedFsmR <= DIS_EX1;
else
ledEndR <= '0';
disLedFsmR <= T1;
end if;
when T1 =>
if ledDoneR = '1' then
indexLedR <= indexLedR + 1;
maskLedR <= maskLedR(51 downto 0) & "0000";
xregLedR <= xregLedR(51 downto 0) & "0000";
disLedFsmR <= T0;
end if;
when DIS_EX1 =>
if ledDoneR = '1' then
ledSendDataR <= ledExDigit1R;
ledStartR <= '0';
ledSendR <= '1';
ledEndR <= '0';
disLedFsmR <= DIS_EX2;
end if;
when DIS_EX2 =>
if ledDoneR = '1' then
ledSendDataR <= ledExDigit2R;
ledStartR <= '0';
ledSendR <= '1';
ledEndR <= '1';
disLedFsmR <= DIS_CMD1;
end if;
when DIS_CMD1 =>
if ledDoneR = '1' then
ledSendDataR <= x"80" or x"08" or "00000"&std_logic_vector(ledBrightR); -- Display Command: On & full brighness
ledStartR <= '1';
ledSendR <= '1';
ledEndR <= '1';
disLedFsmR <= DIS_CMD2;
end if;
when DIS_CMD2 =>
if ledDoneR = '1' then
if ledFirstR = '1' then
disLedFsmR <= SIGNON_W;
else
disLedFsmR <= CMD1;
end if;
end if;
when SIGNON_W =>
-- wait for keyboard activity
ledFirstR <= '0'; -- reset first flag
if (ps2ClkRRR='0' and ps2ClkRR = '1') or keyRdyLongR = '1' then
disLedFsmR <= CMD1;
end if;
end case;
end if;
end if;
end process ledDisplay;
-----------------------------------------
-- End of the LED Display Module driver
-----------------------------------------
end rtl;
|
--
-- Signal edge detect
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_edge_detect is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
RE : out std_logic; -- Rising edge detected
FE : out std_logic -- Falling edge detected
);
end slib_edge_detect;
architecture rtl of slib_edge_detect is
signal iDd : std_logic; -- D register
begin
-- Store D
ED_D: process (RST, CLK)
begin
if (RST = '1') then
iDd <= '0';
elsif (CLK'event and CLK='1') then
iDd <= D;
end if;
end process;
-- Output ports
RE <= '1' when iDd = '0' and D = '1' else '0';
FE <= '1' when iDd = '1' and D = '0' else '0';
end rtl;
|
--
-- Signal edge detect
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_edge_detect is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
RE : out std_logic; -- Rising edge detected
FE : out std_logic -- Falling edge detected
);
end slib_edge_detect;
architecture rtl of slib_edge_detect is
signal iDd : std_logic; -- D register
begin
-- Store D
ED_D: process (RST, CLK)
begin
if (RST = '1') then
iDd <= '0';
elsif (CLK'event and CLK='1') then
iDd <= D;
end if;
end process;
-- Output ports
RE <= '1' when iDd = '0' and D = '1' else '0';
FE <= '1' when iDd = '1' and D = '0' else '0';
end rtl;
|
--
-- Signal edge detect
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_edge_detect is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
RE : out std_logic; -- Rising edge detected
FE : out std_logic -- Falling edge detected
);
end slib_edge_detect;
architecture rtl of slib_edge_detect is
signal iDd : std_logic; -- D register
begin
-- Store D
ED_D: process (RST, CLK)
begin
if (RST = '1') then
iDd <= '0';
elsif (CLK'event and CLK='1') then
iDd <= D;
end if;
end process;
-- Output ports
RE <= '1' when iDd = '0' and D = '1' else '0';
FE <= '1' when iDd = '1' and D = '0' else '0';
end rtl;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_18.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_18 is
end entity fg_07_18;
architecture test of fg_07_18 is
constant target_host_id : natural := 10;
constant my_host_id : natural := 5;
type pkt_types is (control_pkt, other_pkt);
type pkt_header is record
dest, src : natural;
pkt_type : pkt_types;
seq : natural;
end record;
begin
-- code from book
network_driver : process is
constant seq_modulo : natural := 2**5;
subtype seq_number is natural range 0 to seq_modulo-1;
variable next_seq_number : seq_number := 0;
-- . . .
-- not in book
variable new_header : pkt_header;
-- end not in book
impure function generate_seq_number return seq_number is
variable number : seq_number;
begin
number := next_seq_number;
next_seq_number := (next_seq_number + 1) mod seq_modulo;
return number;
end function generate_seq_number;
begin -- network_driver
-- not in book
wait for 10 ns;
-- end not in book
-- . . .
new_header := pkt_header'( dest => target_host_id,
src => my_host_id,
pkt_type => control_pkt,
seq => generate_seq_number );
-- . . .
end process network_driver;
-- end code from book
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_18.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_18 is
end entity fg_07_18;
architecture test of fg_07_18 is
constant target_host_id : natural := 10;
constant my_host_id : natural := 5;
type pkt_types is (control_pkt, other_pkt);
type pkt_header is record
dest, src : natural;
pkt_type : pkt_types;
seq : natural;
end record;
begin
-- code from book
network_driver : process is
constant seq_modulo : natural := 2**5;
subtype seq_number is natural range 0 to seq_modulo-1;
variable next_seq_number : seq_number := 0;
-- . . .
-- not in book
variable new_header : pkt_header;
-- end not in book
impure function generate_seq_number return seq_number is
variable number : seq_number;
begin
number := next_seq_number;
next_seq_number := (next_seq_number + 1) mod seq_modulo;
return number;
end function generate_seq_number;
begin -- network_driver
-- not in book
wait for 10 ns;
-- end not in book
-- . . .
new_header := pkt_header'( dest => target_host_id,
src => my_host_id,
pkt_type => control_pkt,
seq => generate_seq_number );
-- . . .
end process network_driver;
-- end code from book
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_18.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_18 is
end entity fg_07_18;
architecture test of fg_07_18 is
constant target_host_id : natural := 10;
constant my_host_id : natural := 5;
type pkt_types is (control_pkt, other_pkt);
type pkt_header is record
dest, src : natural;
pkt_type : pkt_types;
seq : natural;
end record;
begin
-- code from book
network_driver : process is
constant seq_modulo : natural := 2**5;
subtype seq_number is natural range 0 to seq_modulo-1;
variable next_seq_number : seq_number := 0;
-- . . .
-- not in book
variable new_header : pkt_header;
-- end not in book
impure function generate_seq_number return seq_number is
variable number : seq_number;
begin
number := next_seq_number;
next_seq_number := (next_seq_number + 1) mod seq_modulo;
return number;
end function generate_seq_number;
begin -- network_driver
-- not in book
wait for 10 ns;
-- end not in book
-- . . .
new_header := pkt_header'( dest => target_host_id,
src => my_host_id,
pkt_type => control_pkt,
seq => generate_seq_number );
-- . . .
end process network_driver;
-- end code from book
end architecture test;
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_nco
--
-- project: PG-Soundgates
-- author: Lukas Funke, University of Paderborn
--
-- description: Hardware thread for a numeric controlled oscillator
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_nco is
generic(
SND_COMP_CLK_FREQ : integer := 100_000_000;
SND_COMP_NCO_TPYE : integer := 0
);
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_nco;
architecture Behavioral of hwt_nco is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
component nco is
generic(
FPGA_FREQUENCY : integer := 100_000_000;
WAVEFORM : WAVEFORM_TYPE := SIN
);
Port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
phase_offset : in signed(31 downto 0);
phase_incr : in signed(31 downto 0);
data : out signed(31 downto 0)
);
end component nco;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT_PHASE_OFFSET, STATE_REFRESH_INPUT_PHASE_INCR, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 1024;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 10;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_nco : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_nco : std_logic_vector(0 to 31); -- nco to local ram
signal i_RAMData_nco : std_logic_vector(0 to 31); -- local ram to nco
signal o_RAMWE_nco : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(C_MAX_SAMPLE_COUNT, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal nco_ce : std_logic; -- nco clock enable (like a start/stop signal)
signal phase_offset_addr : std_logic_vector(31 downto 0);
signal phase_incr_addr : std_logic_vector(31 downto 0);
signal phase_offset : std_logic_vector(31 downto 0);
signal phase_incr : std_logic_vector(31 downto 0);
signal nco_data : signed(31 downto 0);
signal state_inner_process : std_logic;
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant NCO_START : std_logic_vector(31 downto 0) := x"0000000F";
constant NCO_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
o_RAMData_nco <= std_logic_vector(nco_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
nco_inst : nco
generic map(
FPGA_FREQUENCY => SND_COMP_CLK_FREQ,
WAVEFORM => WAVEFORM_TYPE'val(SND_COMP_NCO_TPYE)
)
port map(
clk => clk,
rst => rst,
ce => nco_ce,
phase_offset => signed(phase_offset),
phase_incr => signed(phase_incr),
data => nco_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_nco = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_nco))) := o_RAMData_nco;
--else -- else not needed, because nco is not consuming any samples
-- i_RAMData_nco <= local_ram(conv_integer(unsigned(o_RAMAddr_nco)));
end if;
end if;
end process;
NCO_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
osif_ctrl_signal <= (others => '0');
nco_ce <= '0';
o_RAMWE_nco <= '0';
state_inner_process <= '0';
done := False;
elsif rising_edge(clk) then
nco_ce <= '0';
o_RAMWE_nco <= '0';
osif_ctrl_signal <= ( others => '0');
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
-- Initialize your signals
phase_offset_addr <= snd_comp_header.opt_arg_addr;
phase_incr_addr <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 4);
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = NCO_START then
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
state <= STATE_REFRESH_INPUT_PHASE_OFFSET;
elsif osif_ctrl_signal = NCO_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT_PHASE_OFFSET =>
memif_read_word(i_memif, o_memif, phase_offset_addr, phase_offset, done);
if done then
state <= STATE_REFRESH_INPUT_PHASE_INCR;
end if;
when STATE_REFRESH_INPUT_PHASE_INCR =>
memif_read_word(i_memif, o_memif, phase_incr_addr, phase_incr, done);
if done then
state <= STATE_PROCESS;
end if;
when STATE_PROCESS =>
if sample_count > 0 then
case state_inner_process is
when '0' =>
o_RAMWE_nco <= '1';
nco_ce <= '1'; -- ein takt früher
state_inner_process <= '1';
when '1' =>
o_RAMAddr_nco <= std_logic_vector(unsigned(o_RAMAddr_nco) + 1);
sample_count <= sample_count - 1;
state_inner_process <= '0';
end case;
else
-- Samples have been generated
o_RAMAddr_nco <= (others => '0');
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
|
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <[email protected]>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file sim_package.vhd
--! @brief this is a package witch supplies functions for simplification of testbench building
--! @author Benjamin Bässler
--! @email [email protected]
--! @date 2013-06-12
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pbm_package is
--! defines the possible maximum width of images
constant C_MAX_WIDTH : natural := 6000;
--! defines the possible maximum height of images
constant C_MAX_HEIGHT : natural := 6000;
type line_type is array (1 to C_MAX_WIDTH) of std_logic;
type image_type is array (1 to C_MAX_HEIGHT) of line_type;
type image_file_type is file of character;
type T_LINE is array(1 to 100) of character;
procedure read_line(file pbm_file : image_file_type; line_in : inout T_LINE; length : inout natural);
function line2str(l : T_LINE; length : natural) return string;
impure function read_natural (file pbm_file : image_file_type) return natural;
procedure read_pbm(constant filename : in string;
variable image : out image_type;
variable width : out positive;
variable height : out positive
);
end package pbm_package;
package body pbm_package is
file pbm_file : image_file_type;
type input_type is (RAW, ASCII);
procedure read_line(file pbm_file : image_file_type; line_in : inout T_LINE; length : inout natural)
is
variable c : character := ' ';
begin
length := 0;
while not endfile(pbm_file) and (length = 0 or (length > 0 and c /= LF)) loop
read(pbm_file, c);
-- ignore control characters
if character'pos(c) > 30 then
length := length + 1;
line_in(length) := c;
end if;
end loop;
end procedure read_line;
function line2str(l : T_LINE; length : natural) return string
is
variable s : string(1 to length);
begin
for i in s'range loop
s(i) := l (i);
end loop;
return s;
end function line2str;
--! Read the next natural ignore comments and white space
impure function read_natural (file pbm_file : image_file_type) return natural
is
variable value : natural;
variable s_val : string (1 to 70);
variable s_pos : natural;
variable comment : boolean;
variable done : boolean;
variable char : character;
variable tmp : natural;
begin
s_val := (others => nul);
s_pos := 0;
comment := false;
done := false;
value := 0;
while not endfile(pbm_file) and not done loop
read(pbm_file, char);
if comment = false then
if char = '#' and s_pos = 0 then
-- this is the start of a comment
comment := true;
elsif character'pos(char) >= character'pos('0') and character'pos(char) <= character'pos('9') then
s_pos := s_pos + 1;
s_val(s_pos) := char;
elsif s_pos /= 0 then
done := true;
end if;
elsif char = lf then
-- comment ends by line feed
comment := false;
end if;
end loop;
if s_pos > 0 then
-- convert string to natural
for i in s_pos downto 1 loop
tmp := character'pos(s_val(i))-character'pos('0');
value := value + (character'pos(s_val(i))-character'pos('0')) * (10**(s_pos - i));
end loop;
else
report "no Natural found in file" severity failure;
end if;
return value;
end function read_natural;
--! Read the next character as raw value and return as natural
procedure read_raw (variable n : out natural)
is
variable char : character;
begin
read(pbm_file, char);
n := character'pos(char);
end procedure read_raw;
--! Read the next value as hex ignore comments and white space
procedure read_hex (variable n : out natural)
is
variable value : natural;
variable s_val : string (1 to 70);
variable s_pos : natural;
variable comment : boolean;
variable done : boolean;
variable char : character;
variable par_val : natural;
begin
s_val := (others => nul);
s_pos := 0;
comment := false;
done := false;
value := 0;
while not endfile(pbm_file) and not done loop
read(pbm_file, char);
if comment = false then
if char = '#' and s_pos = 0 then
-- this is the start of a comment
comment := true;
elsif (character'pos(char) >= character'pos('0') and character'pos(char) <= character'pos('9')) or
(character'pos(char) >= character'pos('a') and character'pos(char) <= character'pos('f')) or
(character'pos(char) >= character'pos('A') and character'pos(char) <= character'pos('F'))
then
s_pos := s_pos + 1;
s_val(s_pos) := char;
elsif s_pos /= 0 then
done := true;
end if;
elsif char = lf then
-- comment ends by line feed
comment := false;
end if;
end loop;
if s_pos > 0 then
-- convert string to natural
for i in s_pos downto 1 loop
if character'pos(s_val(i)) >= character'pos('0') and character'pos(s_val(i)) <= character'pos('9') then
par_val := character'pos(s_val(i)) - character'pos('0');
elsif s_val(i) = 'a' or s_val(i) = 'A' then
par_val := 10;
elsif s_val(i) = 'b' or s_val(i) = 'B' then
par_val := 11;
elsif s_val(i) = 'c' or s_val(i) = 'C' then
par_val := 12;
elsif s_val(i) = 'd' or s_val(i) = 'D' then
par_val := 13;
elsif s_val(i) = 'e' or s_val(i) = 'E' then
par_val := 14;
elsif s_val(i) = 'f' or s_val(i) = 'F' then
par_val := 15;
end if;
value := value + par_val * (16**(s_pos - i));
end loop;
else
report "no Natural found in file" severity failure;
end if;
n := value;
end procedure read_hex;
--! Open the image and read file to buffer
procedure read_pbm(constant filename : in string;
variable image : out image_type;
variable width : out positive;
variable height : out positive)
is
variable char : character;
variable len : natural;
variable v_width : natural;
variable v_height : natural;
variable pos_x : positive;
variable pos_y : positive;
variable pixel : std_ulogic;
variable file_type : input_type;
variable read_v : natural;
variable byte : unsigned (7 downto 0);
variable start_y : natural;
begin
file_open(pbm_file, filename, read_mode);
-- the first two bits defines the type of the image file P1 means binary and P4 means ASCII values
read(pbm_file, char);
assert char = 'P'
report filename & " is not PBM format" severity failure;
read(pbm_file, char);
if char = '1' then
file_type := ASCII;
elsif char = '4' then
file_type := RAW;
else
report "Filetype P" & char & " not supported" severity failure;
end if;
-- next should be the width in ASCII decimal
v_width := read_natural(pbm_file);
width := v_width;
-- next should be the height in ASCII decimal
v_height := read_natural(pbm_file);
height := v_height;
-- header should end by a whitespace (is already read by read_natural)
assert v_width <= C_MAX_WIDTH
report "The width of the image is bigger than the max width. Change the constants in the package.";
assert v_height <= C_MAX_HEIGHT
report "The height of the image is bigger than the max height. Change the constants in the package";
-- read the whole image
pos_x := 1;
pos_y := 1;
while not endfile (pbm_file) loop
if file_type = ASCII then
assert pos_y <= v_height
report "There are more pixels than described in the header" severity error;
read_v := read_natural(pbm_file);
if read_v = 0 then
image(pos_y)(pos_x) := '0';
elsif read_v = 1 then
image(pos_y)(pos_x) := '1';
else
report "pbm inputfile is corrupt" severity error;
end if;
if pos_x = v_width then
pos_x := 1;
pos_y := pos_y + 1;
else
pos_x := pos_x + 1;
end if;
elsif file_type = RAW then
read_raw(read_v);
byte := to_unsigned(read_v, 8);
start_y := pos_y;
for i in byte'range loop
-- dump fill bits of last char in line
if start_y = pos_y then
image(pos_y)(pos_x) := byte(i);
if pos_x = v_width then
pos_x := 1;
pos_y := pos_y + 1;
else
pos_x := pos_x + 1;
end if;
end if;
end loop;
end if;
end loop;
-- read is done, close file...
file_close(pbm_file);
end procedure read_pbm;
end package body pbm_package;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
use work.license_pkg.all;
use work.global_signals_and_shared_variables_pkg.all;
use work.alert_hierarchy_pkg.all;
use work.protected_types_pkg.all;
use std.env.all;
package methods_pkg is
constant C_UVVM_VERSION : string := "v2 2021.10.22";
-- -- ============================================================================
-- -- Initialisation and license
-- -- ============================================================================
-- procedure initialise_util(
-- constant dummy : in t_void
-- );
--
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string;
constant scope : in string := C_SCOPE
);
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME
);
-- msg_id is unused. This is a deprecated overload
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id
);
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME
);
-- msg_id is unused. This is a deprecated overload
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id
);
-- ============================================================================
-- Log-related
-- ============================================================================
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
);
procedure log(
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
);
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
);
procedure write_to_file (
file_name : string;
open_mode : file_open_kind;
variable my_line : inout line
);
procedure write_line_to_log_destination(
variable log_line : inout line;
constant log_destination : in t_log_destination := shared_default_log_destination;
constant log_file_name : in string := C_LOG_FILE_NAME;
constant open_mode : in file_open_kind := append_mode
);
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
);
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
);
procedure enable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
);
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
);
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
);
procedure disable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
);
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean;
procedure set_log_destination(
constant log_destination : t_log_destination;
constant quietness : t_quietness := NON_QUIET
);
-- ============================================================================
-- Alert-related
-- ============================================================================
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure report_alert_counters(
constant order : in t_order
);
procedure report_alert_counters(
constant dummy : in t_void
);
procedure report_global_ctrl(
constant dummy : in t_void
);
procedure report_msg_id_panel(
constant dummy : in t_void
);
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
);
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
);
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural;
impure function get_alert_counter(
alert_level : t_alert_level;
attention : t_attention := REGARD
) return natural;
procedure increment_alert_counter(
alert_level : t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
);
procedure increment_expected_alerts_and_stop_limit(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure report_check_counters(
constant dummy : in t_void
);
procedure report_check_counters(
constant order : in t_order
);
-- ============================================================================
-- Deprecate message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
);
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1 : std_logic_vector;
value2 : std_logic_vector
) return boolean;
function matching_widths(
value1 : unsigned;
value2 : unsigned
) return boolean;
function matching_widths(
value1 : signed;
value2 : signed
) return boolean;
-- function version of check_value (with return value)
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value(
constant value : signed;
constant exp : signed;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) return boolean;
impure function check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) return boolean;
impure function check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) return boolean;
impure function check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) return boolean;
impure function check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) return boolean;
impure function check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) return boolean;
-- overloads for function versions of check_value (alert level optional)
impure function check_value(
constant value : boolean;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value(
constant value : signed;
constant exp : signed;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean;
impure function check_value(
constant value : signed;
constant exp : signed;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean;
impure function check_value(
constant value : integer;
constant exp : integer;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : real;
constant exp : real;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : time;
constant exp : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : string;
constant exp : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) return boolean;
impure function check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) return boolean;
impure function check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) return boolean;
impure function check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) return boolean;
impure function check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) return boolean;
impure function check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) return boolean;
-- overloads for procedure version of check_value (no return value)
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
);
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
);
procedure check_value(
constant value : signed;
constant exp : signed;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
);
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
);
procedure check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
);
procedure check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
);
procedure check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
);
procedure check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
);
procedure check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
);
-- Procedure overloads for check_value without mandatory alert_level
procedure check_value(
constant value : boolean;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
);
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
);
procedure check_value(
constant value : signed;
constant exp : signed;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
);
procedure check_value(
constant value : signed;
constant exp : signed;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : integer;
constant exp : integer;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : real;
constant exp : real;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : time;
constant exp : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : string;
constant exp : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
);
procedure check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
);
procedure check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
);
procedure check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
);
procedure check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
);
procedure check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
);
--
-- Check_value_in_range
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean;
-- Function overloads for check_value_in_range without mandatory alert_level
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean;
-- Procedure overloads for check_value_in_range
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
-- Procedure overloads for check_value_in_range without mandatory alert_level
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
-- Check_stable
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "boolean"
);
procedure check_stable(
signal target : in std_logic_vector;
constant stable_req : in time;
constant alert_level : in t_alert_level;
variable success : out boolean;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant msg_id : in t_msg_id := ID_POS_ACK;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant caller_name : in string := "check_stable()";
constant value_type : in string := "slv"
);
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "slv"
);
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "unsigned"
);
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "signed"
);
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "std_logic"
);
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "integer"
);
procedure check_stable(
signal target : real;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "real"
);
-- Procedure overloads for check_stable without mandatory alert_level
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "boolean"
);
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "slv"
);
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "unsigned"
);
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "signed"
);
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "std_logic"
);
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "integer"
);
procedure check_stable(
signal target : real;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "real"
);
impure function random (
constant length : integer
) return std_logic_vector;
impure function random (
constant VOID : t_void
) return std_logic;
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer;
impure function random (
constant min_value : real;
constant max_value : real
) return real;
impure function random (
constant min_value : time;
constant max_value : time
) return time;
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
);
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
);
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
);
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
);
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
);
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
function convert_byte_array_to_slv(
constant byte_array : t_byte_array;
constant byte_endianness : t_byte_endianness
) return std_logic_vector;
function convert_slv_to_byte_array(
constant slv : std_logic_vector;
constant byte_endianness : t_byte_endianness
) return t_byte_array;
function convert_byte_array_to_slv_array(
constant byte_array : t_byte_array;
constant bytes_in_word : natural;
constant byte_endianness : t_byte_endianness := LOWER_BYTE_LEFT
) return t_slv_array;
function convert_slv_array_to_byte_array(
constant slv_array : t_slv_array;
constant byte_endianness : t_byte_endianness := LOWER_BYTE_LEFT
) return t_byte_array;
function convert_slv_array_to_byte_array(
constant slv_array : t_slv_array;
constant ascending : boolean := false;
constant byte_endianness : t_byte_endianness := FIRST_BYTE_LEFT
) return t_byte_array;
function reverse_vector(
constant value : std_logic_vector
) return std_logic_vector;
impure function reverse_vectors_in_array(
constant value : t_slv_array
) return t_slv_array;
function log2(
constant num : positive
) return natural;
-- Warning! This function should NOT be used outside the UVVM library.
-- Function is only included to support internal functionality.
-- The function can be removed without notification.
function matching_values(
constant value1 : in std_logic_vector;
constant value2 : in std_logic_vector;
constant match_strictness : in t_match_strictness := MATCH_STD
) return boolean;
-- ============================================================================
-- Time consuming checks
-- ============================================================================
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
);
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
);
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
);
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
);
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
);
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
);
procedure await_change(
signal target : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "real"
);
-- Procedure overloads for await_change without mandatory alert_level
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
);
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
);
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
);
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
);
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
);
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
);
procedure await_change(
signal target : real;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "real"
);
-- Await Value procedures
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : in std_logic_vector;
constant exp : in std_logic_vector;
constant match_strictness : in t_match_strictness;
constant min_time : in time;
constant max_time : in time;
constant alert_level : in t_alert_level;
variable success : out boolean;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant radix : in t_radix := HEX_BIN_IF_INVALID;
constant format : in t_format_zeros := SKIP_LEADING_0;
constant msg_id : in t_msg_id := ID_POS_ACK;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant caller_name : in string := ""
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : real;
constant exp : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
-- Await Value Overloads without Mandatory Alert_Level
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : real;
constant exp : real;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
-- Await Stable Procedures
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : in std_logic_vector;
constant stable_req : in time; -- Minimum stable requirement
constant stable_req_from : in t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : in time; -- Timeout if stable_req not achieved
constant timeout_from : in t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : in t_alert_level;
variable success : out boolean;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant msg_id : in t_msg_id := ID_POS_ACK;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant caller_name : in string := ""
);
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : real;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
-- Await Stable Procedures without Mandatory Alert_Level
-- Await Stable Procedures
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : real;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
-----------------------------------------------------
-- Pulse Generation Procedures
-----------------------------------------------------
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
-----------------------------------------------------
-- Clock Generator Procedures
-----------------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with duty cycle in time
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_time : in time
);
-- Overloaded version with clock count
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with clock count and duty cycle in time
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_time : in time
);
-- Overloaded version with clock enable and clock name
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with clock enable, clock name
-- and duty cycle in time.
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
);
-- Overloaded version with clock enable, clock name
-- and clock count
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with clock enable, clock name,
-- clock count and duty cycle in time.
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
);
-----------------------------------------------------
-- Adjustable Clock Generator Procedures
-----------------------------------------------------
procedure adjustable_clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
signal clock_high_percentage : in natural range 0 to 100
);
procedure adjustable_clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
signal clock_high_percentage : in natural range 0 to 100
);
-- Overloaded version with clock enable, clock name
-- and clock count
procedure adjustable_clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
signal clock_high_percentage : in natural range 0 to 100
);
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
);
-- ============================================================================
-- Synchronization methods
-- ============================================================================
-- method to block a global flag with the name flag_name
procedure block_flag(
constant flag_name : in string;
constant msg : in string;
constant already_blocked_severity : in t_alert_level := warning;
constant scope : in string := C_TB_SCOPE_DEFAULT
);
-- method to unblock a global flag with the name flag_name
procedure unblock_flag(
constant flag_name : in string;
constant msg : in string;
signal trigger : inout std_logic; -- Parameter must be global_trigger as method await_unblock_flag() uses that global signal to detect unblocking.
constant scope : in string := C_TB_SCOPE_DEFAULT
);
-- method to wait for the global flag with the name flag_name
procedure await_unblock_flag(
constant flag_name : in string;
constant timeout : in time;
constant msg : in string;
constant flag_returning : in t_flag_returning := KEEP_UNBLOCKED;
constant timeout_severity : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT
);
procedure await_barrier(
signal barrier_signal : inout std_logic;
constant timeout : in time;
constant msg : in string;
constant timeout_severity : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT
);
-------------------------------------------
-- await_semaphore_in_delta_cycles
-------------------------------------------
-- tries to lock the semaphore for C_NUM_SEMAPHORE_LOCK_TRIES in adaptations_pkg
procedure await_semaphore_in_delta_cycles(
variable semaphore : inout t_protected_semaphore
);
-------------------------------------------
-- release_semaphore
-------------------------------------------
-- releases the semaphore
procedure release_semaphore(
variable semaphore : inout t_protected_semaphore
);
-- ============================================================================
-- Watchdog-related
-- ============================================================================
procedure watchdog_timer(
signal watchdog_ctrl : in t_watchdog_ctrl;
constant timeout : time;
constant alert_level : t_alert_level := error;
constant msg : string := ""
);
procedure extend_watchdog(
signal watchdog_ctrl : inout t_watchdog_ctrl;
constant time_extend : time := 0 ns
);
procedure reinitialize_watchdog(
signal watchdog_ctrl : inout t_watchdog_ctrl;
constant timeout : time
);
procedure terminate_watchdog(
signal watchdog_ctrl : inout t_watchdog_ctrl
);
-- ============================================================================
-- generate_crc
-- ============================================================================
--
-- This function generate the CRC based on the input values. CRC is generated
-- MSb first.
--
-- Input criteria:
-- - Inputs have to be decending (CRC generated from high to low)
-- - crc_in must be one bit shorter than polynomial
--
-- Return vector is one bit shorter than polynomial
--
---------------------------------------------------------------------------------
impure function generate_crc(
constant data : in std_logic_vector;
constant crc_in : in std_logic_vector;
constant polynomial : in std_logic_vector
) return std_logic_vector;
-- slv array have to be acending
impure function generate_crc(
constant data : in t_slv_array;
constant crc_in : in std_logic_vector;
constant polynomial : in std_logic_vector
) return std_logic_vector;
end package methods_pkg;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package body methods_pkg is
constant C_BURIED_SCOPE : string := "(Util buried)";
-- The following constants are not used. Report statements in the given functions allow elaboration time messages
constant C_BITVIS_LICENSE_INITIALISED : boolean := show_license(VOID);
constant C_BITVIS_LIBRARY_INFO_SHOWN : boolean := show_uvvm_utility_library_info(VOID);
constant C_BITVIS_LIBRARY_RELEASE_INFO_SHOWN : boolean := show_uvvm_utility_library_release_info(VOID);
-- ============================================================================
-- Initialisation and license
-- ============================================================================
-- -- Executed a single time ONLY
-- procedure pot_show_license(
-- constant dummy : in t_void
-- ) is
-- begin
-- if not shared_license_shown then
-- show_license(v_trial_license);
-- shared_license_shown := true;
-- end if;
-- end;
-- -- Executed a single time ONLY
-- procedure initialise_util(
-- constant dummy : in t_void
-- ) is
-- begin
-- set_log_file_name(C_LOG_FILE_NAME);
-- set_alert_file_name(C_ALERT_FILE_NAME);
-- shared_license_shown.set(1);
-- shared_initialised_util.set(true);
-- end;
procedure pot_initialise_util(
constant dummy : in t_void
) is
variable v_minimum_log_line_width : natural := 0;
begin
if not shared_initialised_util then
shared_initialised_util := true;
if not shared_log_file_name_is_set then
set_log_file_name(C_LOG_FILE_NAME);
end if;
if not shared_alert_file_name_is_set then
set_alert_file_name(C_ALERT_FILE_NAME);
end if;
if C_ENABLE_HIERARCHICAL_ALERTS then
initialize_hierarchy;
end if;
-- Check that all log widths are valid
v_minimum_log_line_width := v_minimum_log_line_width + C_LOG_PREFIX_WIDTH + C_LOG_TIME_WIDTH + 5; -- Add 5 for spaces
if not (C_SHOW_LOG_ID or C_SHOW_LOG_SCOPE) then
v_minimum_log_line_width := v_minimum_log_line_width + 10; -- Minimum length in order to wrap lines properly
else
if C_SHOW_LOG_ID then
v_minimum_log_line_width := v_minimum_log_line_width + C_LOG_MSG_ID_WIDTH;
end if;
if C_SHOW_LOG_SCOPE then
v_minimum_log_line_width := v_minimum_log_line_width + C_LOG_SCOPE_WIDTH;
end if;
end if;
bitvis_assert(C_LOG_LINE_WIDTH >= v_minimum_log_line_width, failure, "C_LOG_LINE_WIDTH is too low. Needs to higher than " & to_string(v_minimum_log_line_width) & ". ", C_SCOPE);
--show_license(VOID);
-- if C_SHOW_uvvm_utilITY_LIBRARY_INFO then
-- show_uvvm_utility_library_info(VOID);
-- end if;
-- if C_SHOW_uvvm_utilITY_LIBRARY_RELEASE_INFO then
-- show_uvvm_utility_library_release_info(VOID);
-- end if;
end if;
end;
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
) is
begin
if line_to_be_deallocated /= null then
deallocate(line_to_be_deallocated);
end if;
end procedure deallocate_line_if_exists;
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string;
constant scope : in string := C_SCOPE
) is
begin
case status is
when open_ok =>
null; --**** logmsg (if log is open for write)
when status_error =>
alert(tb_warning, "File: " & file_name & " is already open", scope);
when name_error =>
alert(tb_error, "Cannot open file: " & file_name, scope);
when mode_error =>
alert(tb_error, "File: " & file_name & " exists, but cannot be opened in write mode", scope);
end case;
end;
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME
) is
variable v_file_open_status : file_open_status;
begin
if C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME and shared_alert_file_name_is_set then
warning("alert file name already set. Setting new alert file " & file_name);
end if;
shared_alert_file_name_is_set := true;
file_close(ALERT_FILE);
file_open(v_file_open_status, ALERT_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the log file and therefore blocking subsequent set_log_file_name().
report "alert file name set: " & file_name;
end if;
end;
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id
) is
variable v_file_open_status : file_open_status;
begin
deprecate(get_procedure_name_from_instance_name(file_name'instance_name), "msg_id parameter is no longer in use. Please call this procedure without the msg_id parameter.");
set_alert_file_name(file_name);
end;
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME
) is
variable v_file_open_status : file_open_status;
begin
if C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME and shared_log_file_name_is_set then
warning("log file name already set. Setting new log file " & file_name);
end if;
shared_log_file_name_is_set := true;
file_close(LOG_FILE);
file_open(v_file_open_status, LOG_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the alert file and therefore blocking subsequent set_alert_file_name().
report "log file name set: " & file_name;
end if;
end;
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id
) is
begin
-- msg_id is no longer in use. However, can not call deprecate() since Util may not
-- have opened a log file yet. Attempting to call deprecate() when there is no open
-- log file will cause a fatal error. Leaving this alone with no message.
set_log_file_name(file_name);
end;
-- ============================================================================
-- Log-related
-- ============================================================================
impure function align_log_time(
value : time
) return string is
variable v_line : line;
variable v_value_width : natural;
variable v_result : string(1 to 50); -- sufficient for any relevant time value
variable v_result_width : natural;
variable v_delimeter_pos : natural;
variable v_time_number_width : natural;
variable v_time_width : natural;
variable v_num_initial_blanks : integer;
variable v_found_decimal_point : boolean;
begin
-- 1. Store normal write (to string) and note width
write(v_line, value, left, 0, C_LOG_TIME_BASE); -- required as width is unknown
v_value_width := v_line'length;
v_result(1 to v_value_width) := v_line.all;
deallocate(v_line);
-- 2. Search for decimal point or space between number and unit
v_found_decimal_point := true; -- default
v_delimeter_pos := pos_of_leftmost('.', v_result(1 to v_value_width), 0);
if v_delimeter_pos = 0 then -- No decimal point found
v_found_decimal_point := false;
v_delimeter_pos := pos_of_leftmost(' ', v_result(1 to v_value_width), 0);
end if;
-- Potentially alert if time stamp is truncated.
if C_LOG_TIME_TRUNC_WARNING then
if not shared_warned_time_stamp_trunc then
if (C_LOG_TIME_DECIMALS < (v_value_width - 3 - v_delimeter_pos)) then
alert(TB_WARNING, "Time stamp has been truncated to " & to_string(C_LOG_TIME_DECIMALS) &
" decimal(s) in the next log message - settable in adaptations_pkg." &
" (Actual time stamp has more decimals than displayed) " &
"\nThis alert is shown once only.",
C_BURIED_SCOPE);
shared_warned_time_stamp_trunc := true;
end if;
end if;
end if;
-- 3. Derive Time number (integer or real)
if C_LOG_TIME_DECIMALS = 0 then
v_time_number_width := v_delimeter_pos - 1;
-- v_result as is
else -- i.e. a decimal value is required
if v_found_decimal_point then
v_result(v_value_width - 2 to v_result'right) := (others => '0'); -- Zero extend
else -- Shift right after integer part and add point
v_result(v_delimeter_pos + 1 to v_result'right) := v_result(v_delimeter_pos to v_result'right - 1);
v_result(v_delimeter_pos) := '.';
v_result(v_value_width - 1 to v_result'right) := (others => '0'); -- Zero extend
end if;
v_time_number_width := v_delimeter_pos + C_LOG_TIME_DECIMALS;
end if;
-- 4. Add time unit for full time specification
v_time_width := v_time_number_width + 3;
if C_LOG_TIME_BASE = ns then
v_result(v_time_number_width + 1 to v_time_width) := " ns";
else
v_result(v_time_number_width + 1 to v_time_width) := " ps";
end if;
-- 5. Prefix
v_num_initial_blanks := maximum(0, (C_LOG_TIME_WIDTH - v_time_width));
if v_num_initial_blanks > 0 then
v_result(v_num_initial_blanks + 1 to v_result'right) := v_result(1 to v_result'right - v_num_initial_blanks);
v_result(1 to v_num_initial_blanks) := fill_string(' ', v_num_initial_blanks);
v_result_width := C_LOG_TIME_WIDTH;
else
-- v_result as is
v_result_width := v_time_width;
end if;
return v_result(1 to v_result_width);
end function align_log_time;
-- Writes Line to a file without modifying the contents of the line
-- Not yet available in VHDL
procedure tee (
file file_handle : text;
variable my_line : inout line
) is
variable v_line : line;
begin
write (v_line, my_line.all);
writeline(file_handle, v_line);
deallocate(v_line);
end procedure tee;
-- Open, append/write to and close file. Also deallocates contents of the line
procedure write_to_file (
file_name : string;
open_mode : file_open_kind;
variable my_line : inout line
) is
file v_specified_file_pointer : text;
begin
file_open(v_specified_file_pointer, file_name, open_mode);
writeline(v_specified_file_pointer, my_line);
file_close(v_specified_file_pointer);
end procedure write_to_file;
procedure write_line_to_log_destination(
variable log_line : inout line;
constant log_destination : in t_log_destination := shared_default_log_destination;
constant log_file_name : in string := C_LOG_FILE_NAME;
constant open_mode : in file_open_kind := append_mode) is
begin
-- Write the info string to the target file
if log_file_name = "" and (log_destination = LOG_ONLY or log_destination = CONSOLE_AND_LOG) then
-- Output file specified, but file name was invalid.
alert(TB_ERROR, "log called with log_destination " & to_upper(to_string(log_destination)) & ", but log file name was empty.");
else
case log_destination is
when CONSOLE_AND_LOG =>
tee(OUTPUT, log_line); -- write to transcript, while keeping the line contents
-- write to file
if log_file_name = C_LOG_FILE_NAME then
-- If the log file is the default file, it is not necessary to open and close it again
writeline(LOG_FILE, log_line);
else
-- If the log file is a custom file name, the file will have to be opened.
write_to_file(log_file_name, open_mode, log_line);
end if;
when CONSOLE_ONLY =>
writeline(OUTPUT, log_line); -- Write to console and deallocate line
when LOG_ONLY =>
if log_file_name = C_LOG_FILE_NAME then
-- If the log file is the default file, it is not necessary to open and close it again
writeline(LOG_FILE, log_line);
else
-- If the log file is a custom file name, the file will have to be opened.
write_to_file(log_file_name, open_mode, log_line);
end if;
end case;
end if;
end procedure;
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel; -- compatible with old code
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
) is
variable v_msg : line;
variable v_msg_indent : line;
variable v_msg_indent_width : natural;
variable v_info : line;
variable v_info_final : line;
variable v_log_msg_id : string(1 to C_LOG_MSG_ID_WIDTH);
variable v_log_scope : string(1 to C_LOG_SCOPE_WIDTH);
variable v_log_pre_msg_width : natural;
variable v_idx : natural := 1;
begin
-- Check if message ID is enabled
if (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
-- Prepare strings for msg_id and scope
v_log_msg_id := to_upper(justify(to_string(msg_id), left, C_LOG_MSG_ID_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE));
if (scope = "") then
v_log_scope := justify("(non scoped)", left, C_LOG_SCOPE_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
else
v_log_scope := justify(to_string(scope), left, C_LOG_SCOPE_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
end if;
-- Handle actual log info line
-- First write all fields preceeding the actual message - in order to measure their width
-- (Prefix is taken care of later)
write(v_info,
return_string_if_true(v_log_msg_id, C_SHOW_LOG_ID) & -- Optional
" " & align_log_time(now) & " " &
return_string_if_true(v_log_scope, C_SHOW_LOG_SCOPE) & " "); -- Optional
v_log_pre_msg_width := v_info'length; -- Width of string preceeding the actual message
-- Handle \r as potential initial open line
if msg'length > 1 then
if C_USE_BACKSLASH_R_AS_LF then
loop
if (msg(v_idx to v_idx+1) = "\r") then
write(v_info_final, LF); -- Start transcript with an empty line
v_idx := v_idx + 2;
else
write(v_msg, remove_initial_chars(msg, v_idx-1));
exit;
end if;
end loop;
else
write(v_msg, msg);
end if;
end if;
-- Handle dedicated ID indentation.
write(v_msg_indent, to_string(C_MSG_ID_INDENT(msg_id)));
v_msg_indent_width := v_msg_indent'length;
write(v_info, v_msg_indent.all);
deallocate_line_if_exists(v_msg_indent);
-- Then add the message it self (after replacing \n with LF
if msg'length > 1 then
write(v_info, to_string(replace_backslash_n_with_lf(v_msg.all)));
end if;
deallocate_line_if_exists(v_msg);
if not C_SINGLE_LINE_LOG then
-- Modify and align info-string if additional lines are required (after wrapping lines)
wrap_lines(v_info, 1, v_log_pre_msg_width + v_msg_indent_width + 1, C_LOG_LINE_WIDTH-C_LOG_PREFIX_WIDTH);
else
-- Remove line feed character if
-- single line log/alert enabled
replace(v_info, LF, ' ');
end if;
-- Handle potential log header by including info-lines inside the log header format and update of waveview header.
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & LF);
-- also update the Log header string
shared_current_log_hdr.normal := justify(msg, left, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
shared_log_hdr_for_waveview := justify(msg, left, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & LF);
shared_current_log_hdr.large := justify(msg, left, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
write(v_info_final, fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF);
shared_current_log_hdr.xl := justify(msg, left, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
write(v_info_final, LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH))& LF & LF);
end if;
write(v_info_final, v_info.all); -- include actual info
deallocate_line_if_exists(v_info);
-- Handle rest of potential log header
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF & LF);
end if;
-- Add prefix to all lines
prefix_lines(v_info_final);
-- Write the info string to the target file
if log_file_name = "" and (log_destination = LOG_ONLY or log_destination = CONSOLE_AND_LOG) then
-- Output file specified, but file name was invalid.
alert(TB_ERROR, "log called with log_destination " & to_upper(to_string(log_destination)) & ", but log file name was empty.");
else
case log_destination is
when CONSOLE_AND_LOG =>
tee(OUTPUT, v_info_final); -- write to transcript, while keeping the line contents
-- write to file
if log_file_name = C_LOG_FILE_NAME then
-- If the log file is the default file, it is not necessary to open and close it again
writeline(LOG_FILE, v_info_final);
else
-- If the log file is a custom file name, the file will have to be opened.
write_to_file(log_file_name, open_mode, v_info_final);
end if;
when CONSOLE_ONLY =>
writeline(OUTPUT, v_info_final); -- Write to console and deallocate line
when LOG_ONLY =>
if log_file_name = C_LOG_FILE_NAME then
-- If the log file is the default file, it is not necessary to open and close it again
writeline(LOG_FILE, v_info_final);
else
-- If the log file is a custom file name, the file will have to be opened.
write_to_file(log_file_name, open_mode, v_info_final);
end if;
end case;
deallocate_line_if_exists(v_info_final);
end if;
end if;
end;
-- Calls overloaded log procedure with default msg_id
procedure log(
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel; -- compatible with old code
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
) is
begin
log(C_TB_MSG_ID_DEFAULT, msg, scope, msg_id_panel, log_destination, log_file_name, open_mode);
end procedure log;
-- Logging for multi line text. Also deallocates the text_block, for consistency.
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
) is
variable v_text_block_empty_note : string(1 to 26) := "Note: Text block was empty";
variable v_header_line : line;
variable v_log_body : line;
variable v_text_block_is_empty : boolean;
begin
if ((log_file_name = "") and ((log_destination = CONSOLE_AND_LOG) or (log_destination = LOG_ONLY))) then
alert(TB_ERROR, "log_text_block called with log_destination " & to_upper(to_string(log_destination)) & ", but log file name was empty.");
-- Check if message ID is enabled
elsif (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
v_text_block_is_empty := (text_block = null);
if(formatting = UNFORMATTED) then
if(not v_text_block_is_empty) then
-- Write the info string to the target file without any header, footer or indentation
case log_destination is
when CONSOLE_AND_LOG =>
tee(OUTPUT, text_block); -- Write to console, but keep text_block
-- Write to log and deallocate text_block. Open specified file if not open.
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, text_block);
else
write_to_file(log_file_name, open_mode, text_block);
end if;
when CONSOLE_ONLY =>
writeline(OUTPUT, text_block); -- Write to console and deallocate text_block
when LOG_ONLY =>
-- Write to log and deallocate text_block. Open specified file if not open.
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, text_block);
else
write_to_file(log_file_name, open_mode, text_block);
end if;
end case;
end if;
elsif not (v_text_block_is_empty and (log_if_block_empty = SKIP_LOG_IF_BLOCK_EMPTY)) then
-- Add and print header
write(v_header_line, LF & LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
prefix_lines(v_header_line);
-- Add header underline, body and footer
write(v_log_body, fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
if v_text_block_is_empty then
if log_if_block_empty = NOTIFY_IF_BLOCK_EMPTY then
write(v_log_body, v_text_block_empty_note); -- Notify that the text block was empty
end if;
else
write(v_log_body, text_block.all); -- include input text
end if;
write(v_log_body, LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
prefix_lines(v_log_body);
case log_destination is
when CONSOLE_AND_LOG =>
-- Write header to console
tee(OUTPUT, v_header_line);
-- Write header to file, and open/close if not default log file
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, v_header_line);
else
write_to_file(log_file_name, open_mode, v_header_line);
end if;
-- Write header message to specified destination
log(msg_id, msg_header, scope, msg_id_panel, CONSOLE_AND_LOG, log_file_name, append_mode);
-- Write log body to console
tee(OUTPUT, v_log_body);
-- Write log body to specified file
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, v_log_body);
else
write_to_file(log_file_name, append_mode, v_log_body);
end if;
when CONSOLE_ONLY =>
-- Write to console and deallocate all lines
writeline(OUTPUT, v_header_line);
log(msg_id, msg_header, scope, msg_id_panel, CONSOLE_ONLY);
writeline(OUTPUT, v_log_body);
when LOG_ONLY =>
-- Write to log and deallocate text_block. Open specified file if not open.
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, v_header_line);
log(msg_id, msg_header, scope, msg_id_panel, LOG_ONLY);
writeline(LOG_FILE, v_log_body);
else
write_to_file(log_file_name, open_mode, v_header_line);
log(msg_id, msg_header, scope, msg_id_panel, LOG_ONLY, log_file_name, append_mode);
write_to_file(log_file_name, append_mode, v_log_body);
end if;
end case;
-- Deallocate text block to give writeline()-like behaviour
-- for formatted output
deallocate(v_header_line);
deallocate(v_log_body);
deallocate(text_block);
end if;
end if;
end;
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
) is
begin
case msg_id is
when ID_NEVER =>
null; -- Shall not be possible to enable
tb_warning("enable_log_msg() ignored for " & to_upper(to_string(msg_id)) & " (not allowed). " & add_msg_delimiter(msg), scope);
when ALL_MESSAGES =>
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := ENABLED;
end loop;
msg_id_panel(ID_NEVER) := DISABLED;
msg_id_panel(ID_BITVIS_DEBUG) := DISABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
when others =>
msg_id_panel(msg_id) := ENABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
end case;
end;
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
) is
begin
enable_log_msg(msg_id, shared_msg_id_panel, msg, scope, quietness);
end;
procedure enable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
) is
begin
enable_log_msg(msg_id, shared_msg_id_panel, "", scope, quietness);
end;
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
) is
begin
case msg_id is
when ALL_MESSAGES =>
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := DISABLED;
end loop;
msg_id_panel(ID_LOG_MSG_CTRL) := ENABLED; -- keep
when others =>
msg_id_panel(msg_id) := DISABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
end case;
end;
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
) is
begin
disable_log_msg(msg_id, shared_msg_id_panel, msg, scope, quietness);
end;
procedure disable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
) is
begin
disable_log_msg(msg_id, shared_msg_id_panel, "", scope, quietness);
end;
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean is
begin
if msg_id_panel(msg_id) = ENABLED then
return true;
else
return false;
end if;
end;
procedure set_log_destination(
constant log_destination : t_log_destination;
constant quietness : t_quietness := NON_QUIET
) is
begin
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "Changing log destination to " & to_string(log_destination) & ". Was " & to_string(shared_default_log_destination) & ". ", C_TB_SCOPE_DEFAULT);
end if;
shared_default_log_destination := log_destination;
end;
-- ============================================================================
-- Check counters related
-- ============================================================================
-- Shared variable for all the check counters
shared variable protected_check_counters : t_protected_check_counters;
-- ============================================================================
-- Alert-related
-- ============================================================================
-- Shared variable for all the alert counters for different attention
shared variable protected_alert_attention_counters : t_protected_alert_attention_counters;
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
variable v_msg : line; -- msg after pot. replacement of \n
variable v_info : line;
constant C_ATTENTION : t_attention := get_alert_attention(alert_level);
begin
if alert_level /= NO_ALERT then
pot_initialise_util(VOID); -- Only executed the first time called
if C_ENABLE_HIERARCHICAL_ALERTS then
-- Call the hierarchical alert function
hierarchical_alert(alert_level, to_string(msg), to_string(scope), C_ATTENTION);
else
-- Perform the non-hierarchical alert function
write(v_msg, replace_backslash_n_with_lf(to_string(msg)));
-- 1. Increase relevant alert counter. Exit if ignore is set for this alert type.
if get_alert_attention(alert_level) = IGNORE then
-- protected_alert_counters.increment(alert_level, IGNORE);
increment_alert_counter(alert_level, IGNORE);
else
--protected_alert_counters.increment(alert_level, REGARD);
increment_alert_counter(alert_level, REGARD);
-- 2. Write first part of alert message
-- Serious alerts need more attention - thus more space and lines
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH));
end if;
write(v_info, LF & "*** ");
-- 3. Remove line feed character (LF)
-- if single line alert enabled.
if not C_SINGLE_LINE_ALERT then
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" & LF &
justify(to_string(now, C_LOG_TIME_BASE), right, C_LOG_TIME_WIDTH) & " " & to_string(scope) & LF &
wrap_lines(v_msg.all, C_LOG_TIME_WIDTH + 4, C_LOG_TIME_WIDTH + 4, C_LOG_INFO_WIDTH));
else
replace(v_msg, LF, ' ');
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" &
justify(to_string(now, C_LOG_TIME_BASE), right, C_LOG_TIME_WIDTH) & " " & to_string(scope) &
" " & v_msg.all);
end if;
deallocate_line_if_exists(v_msg);
-- 4. Write stop message if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
write(v_info, LF & LF & "Simulator has been paused as requested after " &
to_string(get_alert_counter(alert_level)) & " " &
to_upper(to_string(alert_level)) & LF);
if (alert_level = MANUAL_CHECK) then
write(v_info, "Carry out above check." & LF &
"Then continue simulation from within simulator." & LF);
else
write(v_info, string'("*** To find the root cause of this alert, " &
"step out the HDL calling stack in your simulator. ***" & LF &
"*** For example, step out until you reach the call from the test sequencer. ***"));
end if;
end if;
-- 5. Write last part of alert message
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH) & LF & LF);
else
write(v_info, LF);
end if;
prefix_lines(v_info);
tee(OUTPUT, v_info);
tee(ALERT_FILE, v_info);
writeline(LOG_FILE, v_info);
deallocate_line_if_exists(v_info);
-- 6. Stop simulation if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) then
if (get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
if C_USE_STD_STOP_ON_ALERT_STOP_LIMIT then
std.env.stop(1);
else
assert false report "This single Failure line has been provoked to stop the simulation. See alert-message above" severity failure;
end if;
end if;
end if;
end if;
end if;
end if;
end;
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(note, msg, scope);
end;
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_note, msg, scope);
end;
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(warning, msg, scope);
end;
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_warning, msg, scope);
end;
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(manual_check, msg, scope);
end;
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(error, msg, scope);
end;
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_error, msg, scope);
end;
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(failure, msg, scope);
end;
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_failure, msg, scope);
end;
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
if alert_level = NO_ALERT then
alert(TB_WARNING, "increment_expected_alerts not allowed for alert_level NO_ALERT. " & add_msg_delimiter(msg), scope);
else
if not C_ENABLE_HIERARCHICAL_ALERTS then
increment_alert_counter(alert_level, EXPECT, number);
log(ID_UTIL_SETUP, "incremented expected " & to_upper(to_string(alert_level)) & "s by " & to_string(number) & ". " & add_msg_delimiter(msg), scope);
else
increment_expected_alerts(C_BASE_HIERARCHY_LEVEL, alert_level, number);
end if;
end if;
end;
-- Arguments:
-- - order = FINAL : print out Simulation Success/Fail
procedure report_alert_counters(
constant order : in t_order
) is
begin
pot_initialise_util(VOID); -- Only executed the first time called
if not C_ENABLE_HIERARCHICAL_ALERTS then
protected_alert_attention_counters.to_string(order);
else
print_hierarchical_log(order);
end if;
end;
-- This version (with the t_void argument) is kept for backwards compatibility
procedure report_alert_counters(
constant dummy : in t_void
) is
begin
report_alert_counters(FINAL); -- Default when calling this old method is order=FINAL
end;
procedure report_global_ctrl(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF GLOBAL CTRL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" IGNORE STOP_LIMIT" & LF);
for i in note to t_alert_level'right loop
write(v_line, " " & to_upper(to_string(i, 13, left)) & ": "); -- Severity
write(v_line, to_string(get_alert_attention(i), 7, right) & " "); -- column 1
write(v_line, to_string(integer'(get_alert_stop_limit(i)), 6, right, KEEP_LEADING_SPACE) & LF); -- column 2
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
deallocate(v_line);
end;
procedure report_msg_id_panel(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF MSG ID PANEL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" " & justify("ID", left, C_LOG_MSG_ID_WIDTH) & " Status" & LF &
" " & fill_string('-', C_LOG_MSG_ID_WIDTH) & " ------" & LF);
for i in t_msg_id'left to t_msg_id'right loop
if ((i /= ALL_MESSAGES) and ((i /= NO_ID) and (i /= ID_NEVER))) then -- report all but ID_NEVER, NO_ID and ALL_MESSAGES
write(v_line, " " & to_upper(to_string(i, C_LOG_MSG_ID_WIDTH+5, left)) & ": "); -- MSG_ID
write(v_line, to_upper(to_string(shared_msg_id_panel(i))) & LF); -- Enabled/disabled
end if;
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
deallocate(v_line);
end;
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
) is
begin
if alert_level = NO_ALERT then
tb_warning("set_alert_attention not allowed for alert_level NO_ALERT (always IGNORE).");
else
check_value(attention = IGNORE or attention = REGARD, TB_ERROR,
"set_alert_attention only supported for IGNORE and REGARD", C_BURIED_SCOPE, ID_NEVER);
shared_alert_attention(alert_level) := attention;
log(ID_ALERT_CTRL, "set_alert_attention(" & to_upper(to_string(alert_level)) & ", " & to_string(attention) & "). " & add_msg_delimiter(msg));
end if;
end;
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention is
begin
if alert_level = NO_ALERT then
return IGNORE;
else
return shared_alert_attention(alert_level);
end if;
end;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
) is
begin
if alert_level = NO_ALERT then
tb_warning("set_alert_stop_limit not allowed for alert_level NO_ALERT (stop limit always 0).");
else
if not C_ENABLE_HIERARCHICAL_ALERTS then
shared_stop_limit(alert_level) := value;
-- Evaluate new stop limit in case it is less than or equal to the current alert counter for this alert level
-- If that is the case, a new alert with the same alert level shall be triggered.
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
alert(alert_level, "Alert stop limit for " & to_upper(to_string(alert_level)) & " set to " & to_string(value) &
", which is lower than the current " & to_upper(to_string(alert_level)) & " count (" & to_string(get_alert_counter(alert_level)) & ").");
end if;
else
-- If hierarchical alerts enabled, update top level
-- alert stop limit.
set_hierarchical_alert_top_level_stop_limit(alert_level, value);
end if;
end if;
end;
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural is
begin
if alert_level = NO_ALERT then
return 0;
else
if not C_ENABLE_HIERARCHICAL_ALERTS then
return shared_stop_limit(alert_level);
else
return get_hierarchical_alert_top_level_stop_limit(alert_level);
end if;
end if;
end;
impure function get_alert_counter(
alert_level : t_alert_level;
attention : t_attention := REGARD
) return natural is
begin
return protected_alert_attention_counters.get(alert_level, attention);
end;
procedure increment_alert_counter(
alert_level : t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
) is
type alert_array is array (1 to 6) of t_alert_level;
constant alert_check_array : alert_array := (warning, TB_WARNING, error, TB_ERROR, failure, TB_FAILURE);
alias found_unexpected_simulation_warnings_or_worse is shared_uvvm_status.found_unexpected_simulation_warnings_or_worse;
alias found_unexpected_simulation_errors_or_worse is shared_uvvm_status.found_unexpected_simulation_errors_or_worse;
alias mismatch_on_expected_simulation_warnings_or_worse is shared_uvvm_status.mismatch_on_expected_simulation_warnings_or_worse;
alias mismatch_on_expected_simulation_errors_or_worse is shared_uvvm_status.mismatch_on_expected_simulation_errors_or_worse;
begin
protected_alert_attention_counters.increment(alert_level, attention, number);
-- Update simulation status
if (attention = REGARD) or (attention = EXPECT) then
if (alert_level /= NO_ALERT) and (alert_level /= note) and (alert_level /= TB_NOTE) and (alert_level /= MANUAL_CHECK) then
found_unexpected_simulation_warnings_or_worse := 0; -- default
found_unexpected_simulation_errors_or_worse := 0; -- default
mismatch_on_expected_simulation_warnings_or_worse := 0; -- default
mismatch_on_expected_simulation_errors_or_worse := 0; -- default
-- Compare expected and current allerts
for i in 1 to alert_check_array'high loop
if (get_alert_counter(alert_check_array(i), REGARD) /= get_alert_counter(alert_check_array(i), EXPECT)) then
-- MISMATCH
-- warning or worse
mismatch_on_expected_simulation_warnings_or_worse := 1;
-- error or worse
if not(alert_check_array(i) = warning) and not(alert_check_array(i) = TB_WARNING) then
mismatch_on_expected_simulation_errors_or_worse := 1;
end if;
-- FOUND UNEXPECTED ALERT
if (get_alert_counter(alert_check_array(i), REGARD) > get_alert_counter(alert_check_array(i), EXPECT)) then
-- warning and worse
found_unexpected_simulation_warnings_or_worse := 1;
-- error and worse
if not(alert_check_array(i) = warning) and not(alert_check_array(i) = TB_WARNING) then
found_unexpected_simulation_errors_or_worse := 1;
end if;
end if;
end if;
end loop;
end if;
end if;
end;
procedure increment_expected_alerts_and_stop_limit(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
variable v_alert_stop_limit : natural := get_alert_stop_limit(alert_level);
begin
increment_expected_alerts(alert_level, number, msg, scope);
set_alert_stop_limit(alert_level, v_alert_stop_limit + number);
end;
procedure report_check_counters(
constant order : in t_order
) is
begin
protected_check_counters.to_string(order);
end procedure report_check_counters;
procedure report_check_counters(
constant dummy : in t_void
) is
begin
report_check_counters(FINAL);
end procedure report_check_counters;
-- ============================================================================
-- Deprecation message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
) is
variable v_found : boolean;
begin
v_found := false;
if C_DEPRECATE_SETTING /= NO_DEPRECATE then -- only perform if deprecation enabled
l_find_caller_name_in_list :
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify(caller_name, right, 100) then
v_found := true;
exit l_find_caller_name_in_list;
end if;
end loop;
if v_found then
-- Has already been printed.
if C_DEPRECATE_SETTING = ALWAYS_DEPRECATE then
log(ID_UTIL_SETUP, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
else -- C_DEPRECATE_SETTING = DEPRECATE_ONCE
null;
end if;
else
-- Has not been printed yet.
l_insert_caller_name_in_first_available :
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify("", right, 100) then
deprecated_subprogram_list(i) := justify(caller_name, right, 100);
exit l_insert_caller_name_in_first_available;
end if;
end loop;
log(ID_UTIL_SETUP, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
end if;
end if;
end;
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- NOTE: Index in range N downto 0, with -1 meaning not found
function idx_leftmost_p1_in_p2(
target : std_logic;
vector : std_logic_vector
) return integer is
alias a_vector : std_logic_vector(vector'length - 1 downto 0) is vector;
constant result_if_not_found : integer := -1; -- To indicate not found
begin
bitvis_assert(vector'length > 0, error, "idx_leftmost_p1_in_p2()", "String input is empty");
for i in a_vector'left downto a_vector'right loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1 : std_logic_vector;
value2 : std_logic_vector
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1 : std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2 : std_logic_vector(value2'length - 1 downto 0) is value2;
begin
if (a_value1'left >= maximum(idx_leftmost_p1_in_p2('1', a_value2), 0) and
a_value1'left >= maximum(idx_leftmost_p1_in_p2('H', a_value2), 0) and
a_value1'left >= maximum(idx_leftmost_p1_in_p2('Z', a_value2), 0)) and
(a_value2'left >= maximum(idx_leftmost_p1_in_p2('1', a_value1), 0) and
a_value2'left >= maximum(idx_leftmost_p1_in_p2('H', a_value1), 0) and
a_value2'left >= maximum(idx_leftmost_p1_in_p2('Z', a_value1), 0)) then
return true;
else
return false;
end if;
end;
function matching_widths(
value1 : unsigned;
value2 : unsigned
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
function matching_widths(
value1 : signed;
value2 : signed
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
-- Compare values, but ignore any leading zero's at higher indexes than v_min_length-1.
function matching_values(
constant value1 : in std_logic_vector;
constant value2 : in std_logic_vector;
constant match_strictness : in t_match_strictness := MATCH_STD
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1 : std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2 : std_logic_vector(value2'length - 1 downto 0) is value2;
variable v_min_length : natural := minimum(a_value1'length, a_value2'length);
variable v_match : boolean := true; -- as default prior to checking
begin
if matching_widths(a_value1, a_value2) then
case match_strictness is
when MATCH_STD =>
if not std_match(a_value1(v_min_length-1 downto 0), a_value2(v_min_length-1 downto 0)) then
v_match := false;
end if;
when MATCH_STD_INCL_Z =>
for i in v_min_length-1 downto 0 loop
if not(std_match(a_value1(i), a_value2(i)) or
(a_value1(i) = 'Z' and a_value2(i) = 'Z') or
(a_value1(i) = '-' or a_value2(i) = '-')) then
v_match := false;
exit;
end if;
end loop;
when MATCH_STD_INCL_ZXUW =>
for i in v_min_length-1 downto 0 loop
if not(std_match(a_value1(i), a_value2(i)) or
(a_value1(i) = 'Z' and a_value2(i) = 'Z') or
(a_value1(i) = 'X' and a_value2(i) = 'X') or
(a_value1(i) = 'U' and a_value2(i) = 'U') or
(a_value1(i) = 'W' and a_value2(i) = 'W') or
(a_value1(i) = '-' or a_value2(i) = '-')) then
v_match := false;
exit;
end if;
end loop;
when others =>
if a_value1(v_min_length-1 downto 0) /= a_value2(v_min_length-1 downto 0) then
v_match := false;
end if;
end case;
else
v_match := false;
end if;
return v_match;
end;
function matching_values(
value1 : unsigned;
value2 : unsigned
) return boolean is
begin
return matching_values(std_logic_vector(value1), std_logic_vector(value2));
end;
function matching_values(
value1 : signed;
value2 : signed
) return boolean is
begin
return matching_values(std_logic_vector(value1), std_logic_vector(value2));
end;
-- Function check_value,
-- returning 'true' if OK
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
begin
protected_check_counters.increment(CHECK_VALUE);
if value then
log(msg_id, caller_name & " => OK, for boolean true. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Boolean was false. " & add_msg_delimiter(msg), scope);
end if;
return value;
end;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
protected_check_counters.increment(CHECK_VALUE);
if value = exp then
log(msg_id, caller_name & " => OK, for boolean " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. Boolean was " & v_value_str & ". Expected " & v_exp_str & ". " & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "std_logic";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
variable v_failed : boolean := false;
begin
protected_check_counters.increment(CHECK_VALUE);
case match_strictness is
when MATCH_STD =>
if std_match(value, exp) then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & v_value_str & "' (exp: '" & v_exp_str & "'). " & add_msg_delimiter(msg), scope, msg_id_panel);
else
v_failed := true;
end if;
when MATCH_STD_INCL_Z =>
if (value = 'Z' and exp = 'Z') or std_match(value, exp) then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & v_value_str & "' (exp: '" & v_exp_str & "'). " & add_msg_delimiter(msg), scope, msg_id_panel);
else
v_failed := true;
end if;
when MATCH_STD_INCL_ZXUW =>
if (value = 'Z' and exp = 'Z') or (value = 'X' and exp = 'X') or
(value = 'U' and exp = 'U') or (value = 'W' and exp = 'W') or std_match(value, exp)then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & v_value_str & "' (exp: '" & v_exp_str & "'). " & add_msg_delimiter(msg), scope, msg_id_panel);
else
v_failed := true;
end if;
when others =>
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & v_value_str & "'. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
v_failed := true;
end if;
end case;
if v_failed = true then
alert(alert_level, caller_name & " => Failed. " & value_type & " Was '" & v_value_str & "'. Expected '" & v_exp_str & "'" & LF & msg, scope);
return false;
else
return true;
end if;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "std_logic";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
return check_value(value, exp, MATCH_STD, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
-- Normalise vectors to (N downto 0)
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_exp : std_logic_vector(exp'length - 1 downto 0) is exp;
constant v_value_str : string := to_string(a_value, radix, format, INCL_RADIX);
constant v_exp_str : string := to_string(a_exp, radix, format, INCL_RADIX);
variable v_check_ok : boolean := true; -- as default prior to checking
variable v_trigger_alert : boolean := false; -- trigger alert and log message
-- Match length of short string with long string
function pad_short_string(short, long : string) return string is
variable v_padding : string(1 to (long'length - short'length)) := (others => '0');
begin
-- Include leading 'x"'
return short(1 to 2) & v_padding & short(3 to short'length);
end function pad_short_string;
begin
protected_check_counters.increment(CHECK_VALUE);
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(value'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
v_check_ok := matching_values(a_value, a_exp, match_strictness);
if v_check_ok then
if v_value_str = v_exp_str then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & "'. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- H,L or - is present in v_exp_str
if match_strictness = MATCH_STD then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & "' (exp: " & v_exp_str & "'). " & add_msg_delimiter(msg),
scope, msg_id_panel);
else
v_trigger_alert := true; -- alert and log
end if;
end if;
else
v_trigger_alert := true; -- alert and log
end if;
-- trigger alert and log message
if v_trigger_alert then
if v_value_str'length > v_exp_str'length then
if radix = HEX_BIN_IF_INVALID then
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & "." & LF & msg, scope);
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & pad_short_string(v_exp_str, v_value_str) & "." & LF & msg, scope);
end if;
elsif v_value_str'length < v_exp_str'length then
if radix = HEX_BIN_IF_INVALID then
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & "." & LF & msg, scope);
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & pad_short_string(v_value_str, v_exp_str) & ". Expected " & v_exp_str & "." & LF & msg, scope);
end if;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & "." & LF & msg, scope);
end if;
end if;
return v_check_ok;
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
-- Normalise vectors to (N downto 0)
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_exp : std_logic_vector(exp'length - 1 downto 0) is exp;
constant v_value_str : string := to_string(a_value, radix, format);
constant v_exp_str : string := to_string(a_exp, radix, format);
variable v_check_ok : boolean := true; -- as default prior to checking
begin
return check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), match_strictness, alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), MATCH_STD, alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : signed;
constant exp : signed;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), match_strictness, alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), MATCH_STD, alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "int";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
protected_check_counters.increment(CHECK_VALUE);
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "real";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
protected_check_counters.increment(CHECK_VALUE);
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
protected_check_counters.increment(CHECK_VALUE);
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "string";
begin
protected_check_counters.increment(CHECK_VALUE);
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & value & "'. " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was '" & value & "'. Expected '" & exp & "'" & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) return boolean is
variable v_len_check_ok : boolean := (value'length = exp'length);
variable v_dir_check_ok : boolean := (value'ascending = exp'ascending);
-- adjust for array index differences
variable v_adj_idx : integer := (value'low - exp'low);
begin
protected_check_counters.increment(CHECK_VALUE);
check_value(v_dir_check_ok = true, TB_WARNING, "array directions do not match", scope);
check_value(v_len_check_ok = true, TB_ERROR, "array lengths do not match", scope);
if v_len_check_ok and v_dir_check_ok then
for idx in exp'range loop
-- do not count CHECK_VALUE multiple times
protected_check_counters.decrement(CHECK_VALUE);
if not(check_value(value(idx + v_adj_idx), exp(idx), match_strictness, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type)) then
return false;
end if;
end loop;
else -- lenght or direction check not ok
return false;
end if;
return true;
end;
impure function check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) return boolean is
variable v_len_check_ok : boolean := (value'length = exp'length);
variable v_dir_check_ok : boolean := (value'ascending = exp'ascending);
-- adjust for array index differences
variable v_adj_idx : integer := (value'low - exp'low);
begin
protected_check_counters.increment(CHECK_VALUE);
check_value(v_dir_check_ok = true, TB_WARNING, "array directions do not match", scope);
check_value(v_len_check_ok = true, TB_ERROR, "array lengths do not match", scope);
if v_len_check_ok and v_dir_check_ok then
for idx in exp'range loop
-- do not count CHECK_VALUE multiple times
protected_check_counters.decrement(CHECK_VALUE);
if not(check_value(std_logic_vector(value(idx + v_adj_idx)), std_logic_vector(exp(idx)), alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type)) then
return false;
end if;
end loop;
else -- length or direction check not ok
return false;
end if;
return true;
end;
impure function check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) return boolean is
variable v_len_check_ok : boolean := (value'length = exp'length);
variable v_dir_check_ok : boolean := (value'ascending = exp'ascending);
-- adjust for array index differences
variable v_adj_idx : integer := (value'low - exp'low);
begin
protected_check_counters.increment(CHECK_VALUE);
check_value(v_dir_check_ok = true, TB_WARNING, "array directions do not match", scope);
check_value(v_len_check_ok = true, TB_ERROR, "array lengths do not match", scope);
for idx in exp'range loop
-- do not count CHECK_VALUE multiple times
protected_check_counters.decrement(CHECK_VALUE);
if not(check_value(std_logic_vector(value(idx + v_adj_idx)), std_logic_vector(exp(idx)), alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type)) then
return false;
end if;
end loop;
return true;
end;
impure function check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
----------------------------------------------------------------------
-- Overloads for impure function check_value methods,
-- to allow optional alert_level
----------------------------------------------------------------------
impure function check_value(
constant value : boolean;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, match_strictness, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, MATCH_STD, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), match_strictness, error, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), MATCH_STD, error, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : signed;
constant exp : signed;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), match_strictness, error, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : signed;
constant exp : signed;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), MATCH_STD, error, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : integer;
constant exp : integer;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
impure function check_value(
constant value : real;
constant exp : real;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
impure function check_value(
constant value : time;
constant exp : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
impure function check_value(
constant value : string;
constant exp : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
impure function check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
----------------------------------------------------------------------
-- Overloads for procedural check_value methods,
-- to allow for no return value
----------------------------------------------------------------------
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, match_strictness, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, match_strictness, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, match_strictness, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : signed;
constant exp : signed;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, match_strictness, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) is
variable v_check_ok : boolean;
variable v_len_check_ok : boolean := (value'length = exp'length);
variable v_dir_check_ok : boolean := (value'ascending = exp'ascending);
-- adjust for array index differences
variable v_adj_idx : integer := (value'low - exp'low);
begin
protected_check_counters.increment(CHECK_VALUE);
check_value(v_dir_check_ok = true, TB_WARNING, "array directions do not match", scope);
check_value(v_len_check_ok = true, TB_ERROR, "array lengths do not match", scope);
-- do not count called CHECK_VALUE
protected_check_counters.decrement(CHECK_VALUE, 2);
if v_len_check_ok and v_dir_check_ok then
for idx in exp'range loop
v_check_ok := check_value(value(idx + v_adj_idx), exp(idx), match_strictness, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
-- do not count called CHECK_VALUE
protected_check_counters.decrement(CHECK_VALUE);
end loop;
end if;
end;
procedure check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) is
variable v_check_ok : boolean;
variable v_len_check_ok : boolean := (value'length = exp'length);
variable v_dir_check_ok : boolean := (value'ascending = exp'ascending);
-- adjust for array index differences
variable v_adj_idx : integer := (value'low - exp'low);
begin
protected_check_counters.increment(CHECK_VALUE);
check_value(v_dir_check_ok = true, warning, "array directions do not match", scope);
check_value(v_len_check_ok = true, warning, "array lengths do not match", scope);
-- do not count called CHECK_VALUE
protected_check_counters.decrement(CHECK_VALUE, 2);
if v_len_check_ok and v_dir_check_ok then
for idx in exp'range loop
v_check_ok := check_value(std_logic_vector(value(idx + v_adj_idx)), std_logic_vector(exp(idx)), match_strictness, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
-- do not count called CHECK_VALUE
protected_check_counters.decrement(CHECK_VALUE);
end loop;
end if;
end;
procedure check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) is
variable v_check_ok : boolean;
variable v_len_check_ok : boolean := (value'length = exp'length);
variable v_dir_check_ok : boolean := (value'ascending = exp'ascending);
-- adjust for array index differences
variable v_adj_idx : integer := (value'low - exp'low);
begin
protected_check_counters.increment(CHECK_VALUE);
check_value(v_dir_check_ok = true, warning, "array directions do not match", scope);
check_value(v_len_check_ok = true, warning, "array lengths do not match", scope);
-- do not count called CHECK_VALUE
protected_check_counters.decrement(CHECK_VALUE, 2);
if v_len_check_ok and v_dir_check_ok then
for idx in exp'range loop
v_check_ok := check_value(std_logic_vector(value(idx + v_adj_idx)), std_logic_vector(exp(idx)), match_strictness, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
-- do not count called CHECK_VALUE
protected_check_counters.decrement(CHECK_VALUE);
end loop;
end if;
end;
procedure check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
----------------------------------------------------------------------
-- Overloads to allow check_value to be called without alert_level
----------------------------------------------------------------------
procedure check_value(
constant value : boolean;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
begin
check_value(value, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
begin
check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
begin
check_value(value, exp, match_strictness, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
begin
check_value(value, exp, MATCH_STD, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) is
begin
check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) is
begin
check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) is
begin
check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) is
begin
check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : signed;
constant exp : signed;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) is
begin
check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : signed;
constant exp : signed;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) is
begin
check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : integer;
constant exp : integer;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
begin
check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : real;
constant exp : real;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
begin
check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : time;
constant exp : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
begin
check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : string;
constant exp : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
begin
check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) is
begin
check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) is
begin
check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) is
begin
check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) is
begin
check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) is
begin
check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) is
begin
check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
------------------------------------------------------------------------
-- check_value_in_range
------------------------------------------------------------------------
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
protected_check_counters.increment(CHECK_VALUE_IN_RANGE);
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
-- do not count CHECK_VALUE from CHECK_VALUE_IN_RANGE
protected_check_counters.decrement(CHECK_VALUE);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
begin
protected_check_counters.increment(CHECK_VALUE_IN_RANGE);
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
-- do not count CHECK_VALUE from CHECK_VALUE_IN_RANGE
protected_check_counters.decrement(CHECK_VALUE);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
begin
protected_check_counters.increment(CHECK_VALUE_IN_RANGE);
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
-- do not count CHECK_VALUE from CHECK_VALUE_IN_RANGE
protected_check_counters.decrement(CHECK_VALUE);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
protected_check_counters.increment(CHECK_VALUE_IN_RANGE);
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
-- do not count CHECK_VALUE from CHECK_VALUE_IN_RANGE
protected_check_counters.decrement(CHECK_VALUE);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "real";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
protected_check_counters.increment(CHECK_VALUE_IN_RANGE);
-- Sanity check
check_value(max_value >= min_value, TB_ERROR,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, scope,
ID_NEVER, msg_id_panel, caller_name);
-- do not count CHECK_VALUE from CHECK_VALUE_IN_RANGE
protected_check_counters.decrement(CHECK_VALUE);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
-- check_value_in_range without mandatory alert_level
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
--------------------------------------------------------------------------------
-- check_value_in_range procedures :
-- Call the corresponding function and discard the return value
--------------------------------------------------------------------------------
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- check_value_in_range procedures without mandatory alert_level
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
begin
check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
begin
check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
begin
check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
begin
check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
begin
check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
--------------------------------------------------------------------------------
-- check_stable
--------------------------------------------------------------------------------
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "boolean"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
protected_check_counters.increment(CHECK_STABLE);
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : in std_logic_vector;
constant stable_req : in time;
constant alert_level : in t_alert_level;
variable success : out boolean;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant msg_id : in t_msg_id := ID_POS_ACK;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant caller_name : in string := "check_stable()";
constant value_type : in string := "slv"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
protected_check_counters.increment(CHECK_STABLE);
success := true;
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
success := false;
end if;
end;
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "slv"
) is
variable v_success : boolean;
begin
check_stable(target, stable_req, alert_level, v_success, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "unsigned"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
protected_check_counters.increment(CHECK_STABLE);
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "signed"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
protected_check_counters.increment(CHECK_STABLE);
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "std_logic"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
protected_check_counters.increment(CHECK_STABLE);
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "integer"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
protected_check_counters.increment(CHECK_STABLE);
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK." & value_string & " stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : real;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "real"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
protected_check_counters.increment(CHECK_STABLE);
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK." & value_string & " stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
-- check stable overloads without mandatory alert level
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "boolean"
) is
begin
check_stable(target, stable_req, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "slv"
) is
begin
check_stable(target, stable_req, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "unsigned"
) is
begin
check_stable(target, stable_req, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "signed"
) is
begin
check_stable(target, stable_req, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "std_logic"
) is
begin
check_stable(target, stable_req, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "integer"
) is
begin
check_stable(target, stable_req, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_stable(
signal target : real;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "real"
) is
begin
check_stable(target, stable_req, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
end;
----------------------------------------------------------------------------
-- check_time_window is used to check if a given condition occurred between
-- min_time and max_time
-- Usage: wait for requested condition until max_time is reached, then call check_time_window().
-- The input 'success' is needed to distinguish between the following cases:
-- - the signal reached success condition at max_time,
-- - max_time was reached with no success condition
----------------------------------------------------------------------------
procedure check_time_window(
constant success : in boolean; -- F.ex target'event, or target=exp
constant elapsed_time : in time;
constant min_time : in time;
constant max_time : in time;
constant alert_level : in t_alert_level;
constant name : in string;
variable check_is_ok : out boolean;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant msg_id : in t_msg_id := ID_POS_ACK;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) is
begin
protected_check_counters.increment(CHECK_TIME_WINDOW);
check_is_ok := true;
-- Sanity check
check_value(max_time >= min_time, TB_ERROR, name & " => min_time must be less than max_time." & LF & msg, scope, ID_NEVER, msg_id_panel, name);
-- do not count CHECK_VALUE from CHECK_TIME_WINDOW
protected_check_counters.decrement(CHECK_VALUE);
if elapsed_time < min_time then
alert(alert_level, name & " => Failed. Condition occurred too early, after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope);
check_is_ok := false;
elsif success then
log(msg_id, name & " => OK. Condition occurred after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else -- max_time reached with no success
alert(alert_level, name & " => Failed. Timed out after " &
to_string(max_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope);
check_is_ok := false;
end if;
end;
procedure check_time_window(
constant success : boolean; -- F.ex target'event, or target=exp
constant elapsed_time : time;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant name : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
variable v_check_is_ok : boolean;
begin
check_time_window(success, elapsed_time, min_time, max_time, alert_level, name, v_check_is_ok, msg, scope, msg_id, msg_id_panel);
end;
----------------------------------------------------------------------------
-- Random functions
----------------------------------------------------------------------------
-- Return a random std_logic_vector, using overload for the integer version of random()
impure function random (
constant length : integer
) return std_logic_vector is
variable random_vec : std_logic_vector(length-1 downto 0);
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to length-1 loop
random_vec(i downto i) := std_logic_vector(to_unsigned(random(0, 1), 1));
end loop;
return random_vec;
end;
-- Return a random std_logic, using overload for the SLV version of random()
impure function random (
constant VOID : t_void
) return std_logic is
variable v_random_bit : std_logic_vector(0 downto 0);
begin
-- randomly set bit to 0 or 1
v_random_bit := random(1);
return v_random_bit(0);
end;
-- Return a random integer between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer is
variable v_rand_scaled : integer;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random real between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : real;
constant max_value : real
) return real is
variable v_rand_scaled : real;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random time between min time and max time
-- Use global seeds
impure function random (
constant min_value : time;
constant max_value : time
) return time is
variable v_rand_scaled : time;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
--
-- Procedure versions of random(), where seeds can be specified
--
-- Set target to a random SLV, using overload for the integer version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
) is
variable v_length : integer := v_target'length;
variable v_rand : integer;
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to v_length-1 loop
random(0, 1, v_seed1, v_seed2, v_rand);
v_target(i downto i) := std_logic_vector(to_unsigned(v_rand, 1));
end loop;
end;
-- Set target to a random SL, using overload for the SLV version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
) is
variable v_random_slv : std_logic_vector(0 downto 0);
begin
random(v_seed1, v_seed2, v_random_slv);
v_target := v_random_slv(0);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := integer(real(min_value) + trunc(v_rand*(1.0+real(max_value)-real(min_value))));
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := min_value + v_rand*(max_value-min_value);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
) is
constant time_unit : time := std.env.resolution_limit;
variable v_rand : real;
variable v_rand_int : integer;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_rand_int := integer(real(min_value/time_unit) + trunc(v_rand*(1.0+real(max_value/time_unit)-real(min_value/time_unit))));
v_target := v_rand_int * time_unit;
end;
-- Set global seeds
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- Set global seeds
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
deprecate(get_procedure_name_from_instance_name(seed1'instance_name), "Use randomize().");
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- Converts a t_byte_array (ascending) to a std_logic_vector
function convert_byte_array_to_slv(
constant byte_array : t_byte_array;
constant byte_endianness : t_byte_endianness
) return std_logic_vector is
constant c_num_bytes : integer := byte_array'length;
alias normalized_byte_array : t_byte_array(0 to c_num_bytes-1) is byte_array;
variable v_slv : std_logic_vector(8*c_num_bytes-1 downto 0);
begin
assert byte_array'ascending report "byte_array must be ascending" severity error;
for byte_idx in 0 to c_num_bytes-1 loop
if (byte_endianness = LOWER_BYTE_LEFT) or (byte_endianness = FIRST_BYTE_LEFT) then
v_slv(8*(c_num_bytes-byte_idx)-1 downto 8*(c_num_bytes-1-byte_idx)) := normalized_byte_array(byte_idx);
else -- LOWER_BYTE_RIGHT or FIRST_BYTE_RIGHT
v_slv(8*(byte_idx+1)-1 downto 8*byte_idx) := normalized_byte_array(byte_idx);
end if;
end loop;
return v_slv;
end function;
-- Converts a std_logic_vector to a t_byte_array (ascending)
function convert_slv_to_byte_array(
constant slv : std_logic_vector;
constant byte_endianness : t_byte_endianness
) return t_byte_array is
variable v_num_bytes : integer := slv'length/8+1; -- +1 in case there's a division remainder
alias normalized_slv : std_logic_vector(slv'length-1 downto 0) is slv;
variable v_byte_array : t_byte_array(0 to v_num_bytes-1);
variable v_slv_idx : integer := normalized_slv'high;
variable v_slv_idx_min : integer;
begin
-- Adjust value if there was no remainder
if (slv'length rem 8) = 0 then
v_num_bytes := v_num_bytes-1;
end if;
for byte_idx in 0 to v_num_bytes-1 loop
for bit_idx in 7 downto 0 loop
if v_slv_idx = -1 then
v_byte_array(byte_idx)(bit_idx) := 'Z'; -- Pads 'Z'
else
if (byte_endianness = LOWER_BYTE_LEFT) or (byte_endianness = FIRST_BYTE_LEFT) then
v_byte_array(byte_idx)(bit_idx) := normalized_slv(v_slv_idx);
else -- LOWER_BYTE_RIGHT or FIRST_BYTE_RIGHT
v_slv_idx_min := MINIMUM(8*byte_idx+bit_idx, normalized_slv'high); -- avoid indexing outside the slv
v_byte_array(byte_idx)(bit_idx) := normalized_slv(v_slv_idx_min);
end if;
v_slv_idx := v_slv_idx-1;
end if;
end loop;
end loop;
return v_byte_array(0 to v_num_bytes-1);
end function;
-- Converts a t_byte_array (any direction) to a t_slv_array (same direction)
function convert_byte_array_to_slv_array(
constant byte_array : t_byte_array;
constant bytes_in_word : natural;
constant byte_endianness : t_byte_endianness := LOWER_BYTE_LEFT
) return t_slv_array is
constant c_num_words : integer := byte_array'length/bytes_in_word;
variable v_ascending_array : t_slv_array(0 to c_num_words-1)((8*bytes_in_word)-1 downto 0);
variable v_descending_array : t_slv_array(c_num_words-1 downto 0)((8*bytes_in_word)-1 downto 0);
variable v_byte_idx : integer := 0;
begin
for slv_idx in 0 to c_num_words-1 loop
if (byte_endianness = LOWER_BYTE_LEFT) or (byte_endianness = FIRST_BYTE_LEFT) then
for byte_in_word in bytes_in_word downto 1 loop
v_ascending_array(slv_idx)((8*byte_in_word)-1 downto (byte_in_word-1)*8) := byte_array(v_byte_idx);
v_descending_array(slv_idx)((8*byte_in_word)-1 downto (byte_in_word-1)*8) := byte_array(v_byte_idx);
v_byte_idx := v_byte_idx + 1;
end loop;
else -- LOWER_BYTE_RIGHT or FIRST_BYTE_RIGHT
for byte_in_word in 1 to bytes_in_word loop
v_ascending_array(slv_idx)((8*byte_in_word)-1 downto (byte_in_word-1)*8) := byte_array(v_byte_idx);
v_descending_array(slv_idx)((8*byte_in_word)-1 downto (byte_in_word-1)*8) := byte_array(v_byte_idx);
v_byte_idx := v_byte_idx + 1;
end loop;
end if;
end loop;
if byte_array'ascending then
return v_ascending_array;
else -- byte array is descending
return v_descending_array;
end if;
end function;
-- Converts a t_slv_array (any direction) to a t_byte_array (same direction)
function convert_slv_array_to_byte_array(
constant slv_array : t_slv_array;
constant byte_endianness : t_byte_endianness := LOWER_BYTE_LEFT
) return t_byte_array is
constant c_num_bytes_in_word : integer := (slv_array(slv_array'low)'length/8);
constant c_byte_array_length : integer := (slv_array'length * c_num_bytes_in_word);
constant c_vector_is_ascending : boolean := slv_array(slv_array'low)'ascending;
variable v_ascending_array : t_byte_array(0 to c_byte_array_length-1);
variable v_descending_array : t_byte_array(c_byte_array_length-1 downto 0);
variable v_byte_idx : integer := 0;
variable v_offset : natural := 0;
begin
-- Use this offset in case the slv_array doesn't start at 0
v_offset := slv_array'low;
for slv_idx in 0 to slv_array'length-1 loop
if (byte_endianness = LOWER_BYTE_LEFT) or (byte_endianness = FIRST_BYTE_LEFT) then
for byte in c_num_bytes_in_word downto 1 loop
if c_vector_is_ascending then
v_ascending_array(v_byte_idx) := slv_array(slv_idx+v_offset)((byte-1)*8 to (8*byte)-1);
v_descending_array(v_byte_idx) := slv_array(slv_idx+v_offset)((byte-1)*8 to (8*byte)-1);
else -- SLV vector is descending
v_ascending_array(v_byte_idx) := slv_array(slv_idx+v_offset)((8*byte)-1 downto (byte-1)*8);
v_descending_array(v_byte_idx) := slv_array(slv_idx+v_offset)((8*byte)-1 downto (byte-1)*8);
end if;
v_byte_idx := v_byte_idx + 1;
end loop;
else -- LOWER_BYTE_RIGHT or FIRST_BYTE_RIGHT
for byte in 1 to c_num_bytes_in_word loop
if c_vector_is_ascending then
v_ascending_array(v_byte_idx) := slv_array(slv_idx+v_offset)((byte-1)*8 to (8*byte)-1);
v_descending_array(v_byte_idx) := slv_array(slv_idx+v_offset)((byte-1)*8 to (8*byte)-1);
else -- SLV vector is descending
v_ascending_array(v_byte_idx) := slv_array(slv_idx+v_offset)((8*byte)-1 downto (byte-1)*8);
v_descending_array(v_byte_idx) := slv_array(slv_idx+v_offset)((8*byte)-1 downto (byte-1)*8);
end if;
v_byte_idx := v_byte_idx + 1;
end loop;
end if;
end loop;
if slv_array'ascending then
return v_ascending_array;
else -- SLV array is descending
return v_descending_array;
end if;
end function;
function convert_slv_array_to_byte_array(
constant slv_array : t_slv_array;
constant ascending : boolean := false;
constant byte_endianness : t_byte_endianness := FIRST_BYTE_LEFT
) return t_byte_array is
variable v_bytes_in_word : integer := (slv_array(0)'length/8);
variable v_byte_array_length : integer := (slv_array'length * v_bytes_in_word);
variable v_ascending_array : t_byte_array(0 to v_byte_array_length-1);
variable v_descending_array : t_byte_array(v_byte_array_length-1 downto 0);
variable v_ascending_vector : boolean := false;
variable v_byte_number : integer := 0;
begin
-- The ascending parameter should match the array direction. We could also just remove the ascending
-- parameter and use the t'ascending attribute.
bitvis_assert((slv_array'ascending and ascending) or (not(slv_array'ascending) and not(ascending)), ERROR,
"convert_slv_array_to_byte_array()", "slv_array direction doesn't match ascending parameter");
v_ascending_vector := slv_array(0)'ascending;
if (byte_endianness = LOWER_BYTE_LEFT) or (byte_endianness = FIRST_BYTE_LEFT) then
for slv_idx in 0 to slv_array'length-1 loop
for byte in v_bytes_in_word downto 1 loop
if v_ascending_vector then
v_ascending_array(v_byte_number) := slv_array(slv_idx)((byte-1)*8 to (8*byte)-1);
v_descending_array(v_byte_number) := slv_array(slv_idx)((byte-1)*8 to (8*byte)-1);
else -- SLV vector is descending
v_ascending_array(v_byte_number) := slv_array(slv_idx)((8*byte)-1 downto (byte-1)*8);
v_descending_array(v_byte_number) := slv_array(slv_idx)((8*byte)-1 downto (byte-1)*8);
end if;
v_byte_number := v_byte_number + 1;
end loop;
end loop;
else -- LOWER_BYTE_RIGHT or FIRST_BYTE_RIGHT
for slv_idx in 0 to slv_array'length-1 loop
for byte in 1 to v_bytes_in_word loop
if v_ascending_vector then
v_ascending_array(v_byte_number) := slv_array(slv_idx)((byte-1)*8 to (8*byte)-1);
v_descending_array(v_byte_number) := slv_array(slv_idx)((byte-1)*8 to (8*byte)-1);
else -- SLV vector is descending
v_ascending_array(v_byte_number) := slv_array(slv_idx)((8*byte)-1 downto (byte-1)*8);
v_descending_array(v_byte_number) := slv_array(slv_idx)((8*byte)-1 downto (byte-1)*8);
end if;
v_byte_number := v_byte_number + 1;
end loop;
end loop;
end if;
if ascending then
return v_ascending_array;
else -- descending
return v_descending_array;
end if;
end function;
function reverse_vector(
constant value : std_logic_vector
) return std_logic_vector is
variable return_val : std_logic_vector(value'range);
begin
for i in 0 to value'length-1 loop
return_val(value'low + i) := value(value'high - i);
end loop;
return return_val;
end function reverse_vector;
impure function reverse_vectors_in_array(
constant value : t_slv_array
) return t_slv_array is
variable return_val : t_slv_array(value'range)(value(value'low)'range);
begin
for i in value'range loop
return_val(i) := reverse_vector(value(i));
end loop;
return return_val;
end function reverse_vectors_in_array;
function log2(
constant num : positive)
return natural is
variable return_val : natural := 0;
begin
while (2**return_val < num) and (return_val < 31) loop
return_val := return_val + 1;
end loop;
return return_val;
end function;
-- ============================================================================
-- Time consuming checks
-- ============================================================================
--------------------------------------------------------------------------------
-- await_change
-- A signal change is required, but may happen already after 1 delta if min_time = 0 ns
--------------------------------------------------------------------------------
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
-- Note that overloading by casting target to slv without creating a new signal doesn't work
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "real"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
-- Await Change overloads without mandatory alert level
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
) is
begin
await_change(target, min_time, max_time, error, msg, scope, msg_id, msg_id_panel, value_type);
end;
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
) is
begin
await_change(target, min_time, max_time, error, msg, scope, msg_id, msg_id_panel, value_type);
end;
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
) is
begin
await_change(target, min_time, max_time, error, msg, scope, msg_id, msg_id_panel, value_type);
end;
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
) is
begin
await_change(target, min_time, max_time, error, msg, scope, msg_id, msg_id_panel, value_type);
end;
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
) is
begin
await_change(target, min_time, max_time, error, msg, scope, msg_id, msg_id_panel, value_type);
end;
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
) is
begin
await_change(target, min_time, max_time, error, msg, scope, msg_id, msg_id_panel, value_type);
end;
procedure await_change(
signal target : real;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "real"
) is
begin
await_change(target, min_time, max_time, error, msg, scope, msg_id, msg_id_panel, value_type);
end;
--------------------------------------------------------------------------------
-- await_value
--------------------------------------------------------------------------------
-- Potential improvements
-- - Adding an option that the signal must last for more than one delta cycle
-- or a specified time
-- - Adding an "AS_IS" option that does not allow the signal to change to other values
-- before it changes to the expected value
--
-- The input signal is allowed to change to other values before ending up on the expected value,
-- as long as it changes to the expected value within the time window (min_time to max_time).
-- Wait for target = expected or timeout after max_time.
-- Then check if (and when) the value changed to the expected
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
variable success : boolean := false;
begin
success := false;
if match_strictness = MATCH_EXACT then
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
if (target = exp) then
success := true;
end if;
elsif match_strictness = MATCH_STD_INCL_Z then
if not(std_match(target, exp) or (target = 'Z' and exp = 'Z')) then
wait until (std_match(target, exp) or (target = 'Z' and exp = 'Z')) for max_time;
end if;
if std_match(target, exp) or (target = 'Z' and exp = 'Z') then
success := true;
end if;
elsif match_strictness = MATCH_STD_INCL_ZXUW then
if not(std_match(target, exp) or (target = 'Z' and exp = 'Z') or
(target = 'X' and exp = 'X') or (target = 'U' and exp = 'U') or
(target = 'W' and exp = 'W')) then
wait until (std_match(target, exp) or (target = 'Z' and exp = 'Z') or
(target = 'X' and exp = 'X') or (target = 'U' and exp = 'U') or
(target = 'W' and exp = 'W')) for max_time;
end if;
if std_match(target, exp) or (target = 'Z' and exp = 'Z') or (target = 'X' and exp = 'X') or
(target = 'U' and exp = 'U') or (target = 'W' and exp = 'W') then
success := true;
end if;
else
if ((exp = '1' or exp = 'H') and (target /= '1') and (target /= 'H')) then
wait until (target = '1' or target = 'H') for max_time;
elsif ((exp = '0' or exp = 'L') and (target /= '0') and (target /= 'L')) then
wait until (target = '0' or target = 'L') for max_time;
end if;
if ((exp = '1' or exp = 'H') and (target = '1' or target = 'H')) then
success := true;
elsif ((exp = '0' or exp = 'L') and (target = '0' or target = 'L')) then
success := true;
end if;
end if;
check_time_window(success, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
await_value(target, exp, MATCH_EXACT, min_time, max_time, alert_level, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : in std_logic_vector;
constant exp : in std_logic_vector;
constant match_strictness : in t_match_strictness;
constant min_time : in time;
constant max_time : in time;
constant alert_level : in t_alert_level;
variable success : out boolean;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant radix : in t_radix := HEX_BIN_IF_INVALID;
constant format : in t_format_zeros := SKIP_LEADING_0;
constant msg_id : in t_msg_id := ID_POS_ACK;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant caller_name : in string := ""
) is
constant value_type : string := "slv";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
variable v_proc_call : line;
begin
if caller_name = "" then
write(v_proc_call, name);
else
write(v_proc_call, caller_name);
end if;
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(target'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
if matching_widths(target, exp) then
if match_strictness = MATCH_STD then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, v_proc_call.all, success, msg, scope, msg_id, msg_id_panel);
elsif match_strictness = MATCH_STD_INCL_Z then
if not matching_values(target, exp, MATCH_STD_INCL_Z) then
wait until matching_values(target, exp, MATCH_STD_INCL_Z) for max_time;
end if;
check_time_window(matching_values(target, exp, MATCH_STD_INCL_Z), now-start_time, min_time, max_time, alert_level, v_proc_call.all, success, msg, scope, msg_id, msg_id_panel);
elsif match_strictness = MATCH_STD_INCL_ZXUW then
if not matching_values(target, exp, MATCH_STD_INCL_ZXUW) then
wait until matching_values(target, exp, MATCH_STD_INCL_ZXUW) for max_time;
end if;
check_time_window(matching_values(target, exp, MATCH_STD_INCL_ZXUW), now-start_time, min_time, max_time, alert_level, v_proc_call.all, success, msg, scope, msg_id, msg_id_panel);
else
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, v_proc_call.all, success, msg, scope, msg_id, msg_id_panel);
end if;
else
alert(alert_level, v_proc_call.all & " => Failed. Widths did not match. " & add_msg_delimiter(msg), scope);
success := false;
end if;
DEALLOCATE(v_proc_call);
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
variable v_success : boolean;
begin
await_value(target, exp, match_strictness, min_time, max_time, alert_level, v_success, msg, scope, radix, format, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "slv";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
await_value(target, exp, MATCH_STD, min_time, max_time, alert_level, msg, scope, radix, format, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(target'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & add_msg_delimiter(msg), scope);
end if;
end;
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(target'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & add_msg_delimiter(msg), scope);
end if;
end;
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : real;
constant exp : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "real";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
-- Await Value Overloads without alert_level
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_value(target, exp, min_time, max_time, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_value(target, exp, match_strictness, min_time, max_time, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_value(target, exp, min_time, max_time, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_value(target, exp, match_strictness, min_time, max_time, error, msg, scope, radix, format, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_value(target, exp, min_time, max_time, error, msg, scope, radix, format, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_value(target, exp, min_time, max_time, error, msg, scope, radix, format, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_value(target, exp, min_time, max_time, error, msg, scope, radix, format, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_value(target, exp, min_time, max_time, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : real;
constant exp : real;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_value(target, exp, min_time, max_time, error, msg, scope, msg_id, msg_id_panel);
end;
-- Helper procedure:
-- Convert time from 'FROM_LAST_EVENT' to 'FROM_NOW'
procedure await_stable_calc_time (
constant target_last_event : in time;
constant stable_req : in time; -- Minimum stable requirement
constant stable_req_from : in t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : in time; -- Timeout if stable_req not achieved
constant timeout_from : in t_from_point_in_time; -- Which point in time the timeout starts
variable stable_req_from_now : inout time; -- Calculated stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Calculated timeout from procedure entry
constant alert_level : in t_alert_level;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant msg_id : in t_msg_id := ID_POS_ACK;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant caller_name : in string := "await_stable_calc_time()";
variable stable_req_met : inout boolean; -- When true, the stable requirement is satisfied
variable stable_req_success : out boolean
) is
begin
stable_req_met := false;
stable_req_success := true;
-- Convert stable_req so that it points to "time_from_now"
if stable_req_from = FROM_NOW then
stable_req_from_now := stable_req;
elsif stable_req_from = FROM_LAST_EVENT then
-- Signal has already been stable for target'last_event,
-- so we can subtract this in the FROM_NOW version.
stable_req_from_now := stable_req - target_last_event;
else
alert(tb_error, caller_name & " => Unknown stable_req_from. " & add_msg_delimiter(msg), scope);
stable_req_success := false;
end if;
-- Convert timeout so that it points to "time_from_now"
if timeout_from = FROM_NOW then
timeout_from_await_stable_entry := timeout;
elsif timeout_from = FROM_LAST_EVENT then
timeout_from_await_stable_entry := timeout - target_last_event;
else
alert(tb_error, caller_name & " => Unknown timeout_from. " & add_msg_delimiter(msg), scope);
stable_req_success := false;
end if;
-- Check if requirement is already OK
if (stable_req_from_now <= 0 ns) then
log(msg_id, caller_name & " => OK. Condition occurred immediately. " & add_msg_delimiter(msg), scope, msg_id_panel);
stable_req_met := true;
end if;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > timeout_from_await_stable_entry) then
alert(alert_level, caller_name & " => Failed immediately: Stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
". " & add_msg_delimiter(msg), scope);
stable_req_met := true;
stable_req_success := false;
end if;
end;
procedure await_stable_calc_time (
constant target_last_event : time;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
variable stable_req_from_now : inout time; -- Calculated stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Calculated timeout from procedure entry
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "await_stable_calc_time()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
variable v_stable_req_success : boolean;
begin
await_stable_calc_time(target_last_event, stable_req, stable_req_from, timeout, timeout_from, stable_req_from_now,
timeout_from_await_stable_entry, alert_level, msg, scope, msg_id, msg_id_panel, caller_name, stable_req_met, v_stable_req_success);
end;
-- Helper procedure:
procedure await_stable_checks (
constant start_time : in time; -- Time at await_stable() procedure entry
constant stable_req : in time; -- Minimum stable requirement
variable stable_req_from_now : inout time; -- Minimum stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Timeout value converted to FROM_NOW
constant time_since_last_event : in time; -- Time since previous event
constant alert_level : in t_alert_level;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant msg_id : in t_msg_id := ID_POS_ACK;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant caller_name : in string := "await_stable_checks()";
variable stable_req_met : inout boolean; -- When true, the stable requirement is satisfied
variable stable_req_success : out boolean
) is
variable v_time_left : time; -- Remaining time until timeout
variable v_elapsed_time : time := 0 ns; -- Time since procedure entry
begin
stable_req_met := false;
v_elapsed_time := now - start_time;
v_time_left := timeout_from_await_stable_entry - v_elapsed_time;
-- Check if target has been stable for stable_req
if (time_since_last_event >= stable_req_from_now) then
log(msg_id, caller_name & " => OK. Condition occurred after " &
to_string(v_elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
stable_req_met := true;
stable_req_success := true;
end if;
--
-- Prepare for the next iteration in the loop in await_stable() procedure:
--
if not stable_req_met then
-- Now that an event has occurred, the stable requirement is stable_req from now (regardless of stable_req_from)
stable_req_from_now := stable_req;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > v_time_left) then
alert(alert_level, caller_name & " => Failed. After " & to_string(v_elapsed_time, C_LOG_TIME_BASE) &
", stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
"(time since last event = " & to_string(time_since_last_event, ns) &
". " & add_msg_delimiter(msg), scope);
stable_req_met := true;
stable_req_success := false;
end if;
end if;
end;
procedure await_stable_checks (
constant start_time : time; -- Time at await_stable() procedure entry
constant stable_req : time; -- Minimum stable requirement
variable stable_req_from_now : inout time; -- Minimum stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Timeout value converted to FROM_NOW
constant time_since_last_event : time; -- Time since previous event
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "await_stable_checks()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
variable v_stable_req_success : boolean;
begin
await_stable_checks(start_time, stable_req, stable_req_from_now, timeout_from_await_stable_entry, time_since_last_event,
alert_level, msg, scope, msg_id, msg_id_panel, caller_name, stable_req_met, v_stable_req_success);
end;
-- Await Stable Procedures
-- Wait until the target signal has been stable for at least 'stable_req'
-- Report an error if this does not occurr within the time specified by 'timeout'.
-- Note : 'Stable' refers to that the signal has not had an event (i.e. not changed value).
-- Description of arguments:
-- stable_req_from = FROM_NOW : Target must be stable 'stable_req' from now
-- stable_req_from = FROM_LAST_EVENT : Target must be stable 'stable_req' from the last event of target.
-- timeout_from = FROM_NOW : The timeout argument is given in time from now
-- timeout_from = FROM_LAST_EVENT : The timeout argument is given in time the last event of target.
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-- Note that the waiting for target'event can't be called from overloaded procedures where 'target' is a different type.
-- Instead, the common code is put in helper procedures
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : in std_logic_vector;
constant stable_req : in time; -- Minimum stable requirement
constant stable_req_from : in t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : in time; -- Timeout if stable_req not achieved
constant timeout_from : in t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : in t_alert_level;
variable success : out boolean;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant msg_id : in t_msg_id := ID_POS_ACK;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant caller_name : in string := ""
) is
constant value_type : string := "std_logic_vector";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
variable v_proc_call : line;
begin
if caller_name = "" then
write(v_proc_call, name);
else
write(v_proc_call, caller_name);
end if;
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => v_proc_call.all,
stable_req_met => v_stable_req_met,
stable_req_success => success);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => v_proc_call.all,
stable_req_met => v_stable_req_met,
stable_req_success => success);
end loop;
DEALLOCATE(v_proc_call);
end;
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
variable v_success : boolean;
begin
await_stable(target, stable_req, stable_req_from, timeout, timeout_from, alert_level, v_success, msg, scope, msg_id, msg_id_panel);
end;
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occur
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : real;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "real";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occur
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-- Procedure overloads for await_stable() without mandatory Alert_Level
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_stable(target, stable_req, stable_req_from, timeout, timeout_from, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_stable(target, stable_req, stable_req_from, timeout, timeout_from, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_stable(target, stable_req, stable_req_from, timeout, timeout_from, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_stable(target, stable_req, stable_req_from, timeout, timeout_from, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_stable(target, stable_req, stable_req_from, timeout, timeout_from, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_stable(target, stable_req, stable_req_from, timeout, timeout_from, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_stable (
signal target : real;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_stable(target, stable_req, stable_req_from, timeout, timeout_from, error, msg, scope, msg_id, msg_id_panel);
end;
-----------------------------------------------------------------------------------
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain amount of time
--
-- If blocking_mode = BLOCKING : Procedure waits until the pulse is done before returning to the caller.
-- If blocking_mode = NON_BLOCKING : Procedure starts the pulse, schedules the end of the pulse, then returns to the caller immediately.
--
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic := target;
begin
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value; -- Generate pulse
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= init_value;
else
check_value(pulse_duration /= 0 ns, TB_ERROR, "gen_pulse: The combination of NON_BLOCKING mode and 0 ns pulse duration results in the pulse being ignored.", scope, ID_NEVER);
target <= transport init_value after pulse_duration;
end if;
log(msg_id, "Pulsed to " & to_string(pulse_value) & " for " & to_string(pulse_duration) & ". " & add_msg_delimiter(msg), scope);
wait for 0 ns; -- wait a delta cycle for signal to update
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = '1' by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, '1', pulse_duration, blocking_mode, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode and pulse_value arguments:
-- Make blocking_mode = BLOCKING and pulse_value = '1' by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, '1', pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain number of clock cycles
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic := target;
begin
wait until falling_edge(clock_signal);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value; -- Generate pulse
if (num_periods > 0) then
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
end if;
target <= init_value;
log(msg_id, "Pulsed to " & to_string(pulse_value) & " for " & to_string(num_periods) & " clk cycles. " & add_msg_delimiter(msg), scope);
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = '1' by default
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, '1', clock_signal, num_periods, msg, scope, msg_id, msg_id_panel); -- pulse_value = '1' by default
end;
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : boolean := target;
begin
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value; -- Generate pulse
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= init_value;
else
check_value(pulse_duration /= 0 ns, TB_ERROR, "gen_pulse: The combination of NON_BLOCKING mode and 0 ns pulse duration results in the pulse being ignored.", scope, ID_NEVER);
target <= transport init_value after pulse_duration;
end if;
log(msg_id, "Pulsed to " & to_string(pulse_value) & " for " & to_string(pulse_duration) & ". " & add_msg_delimiter(msg), scope);
wait for 0 ns; -- wait a delta cycle for signal to update
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = true by default
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, true, pulse_duration, blocking_mode, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode and pulse_value arguments:
-- Make blocking_mode = BLOCKING and pulse_value = true by default
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, true, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Generate a pulse on a boolean for a certain number of clock cycles
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : boolean := target;
begin
wait until falling_edge(clock_signal);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value; -- Generate pulse
if (num_periods > 0) then
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
end if;
target <= init_value;
log(msg_id, "Pulsed to " & to_string(pulse_value) & " for " & to_string(num_periods) & " clk cycles. " & add_msg_delimiter(msg), scope);
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = true by default
procedure gen_pulse(
signal target : inout boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, true, clock_signal, num_periods, msg, scope, msg_id, msg_id_panel); -- pulse_value = '1' by default
end;
-- gen_pulse(slv)
-- Generate a pulse on a std_logic_vector for a certain amount of time
--
-- If blocking_mode = BLOCKING : Procedure waits until the pulse is done before returning to the caller.
-- If blocking_mode = NON_BLOCKING : Procedure starts the pulse, schedules the end of the pulse, then returns to the caller immediately.
--
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic_vector(target'range) := target;
variable v_target : std_logic_vector(target'length-1 downto 0) := target;
variable v_pulse : std_logic_vector(pulse_value'length-1 downto 0) := pulse_value;
begin
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
for i in 0 to (v_target'length-1) loop
if v_pulse(i) /= '-' then
v_target(i) := v_pulse(i); -- Generate pulse
end if;
end loop;
target <= v_target;
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= init_value;
else
check_value(pulse_duration /= 0 ns, TB_ERROR, "gen_pulse: The combination of NON_BLOCKING mode and 0 ns pulse duration results in the pulse being ignored.", scope, ID_NEVER);
target <= transport init_value after pulse_duration;
end if;
log(msg_id, "Pulsed to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) & " for " & to_string(pulse_duration) & ". " & add_msg_delimiter(msg), scope);
wait for 0 ns; -- wait a delta cycle for signal to update
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = (others => '1') by default
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant pulse_value : std_logic_vector(target'range) := (others => '1');
begin
gen_pulse(target, pulse_value, pulse_duration, blocking_mode, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode and pulse_value arguments:
-- Make blocking_mode = BLOCKING and pulse_value = (others => '1') by default
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant pulse_value : std_logic_vector(target'range) := (others => '1');
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- gen_pulse(slv)
-- Generate a pulse on a std_logic_vector for a certain number of clock cycles
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic_vector(target'range) := target;
constant v_pulse : std_logic_vector(pulse_value'length-1 downto 0) := pulse_value;
variable v_target : std_logic_vector(target'length-1 downto 0) := target;
begin
wait until falling_edge(clock_signal);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
for i in 0 to (v_target'length-1) loop
if v_pulse(i) /= '-' then
v_target(i) := v_pulse(i); -- Generate pulse
end if;
end loop;
target <= v_target;
if (num_periods > 0) then
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
end if;
target <= init_value;
log(msg_id, "Pulsed to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) & " for " & to_string(num_periods) & " clk cycles. " & add_msg_delimiter(msg), scope);
wait for 0 ns; -- wait a delta cycle for signal to update
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = (others => '1') by default
procedure gen_pulse(
signal target : inout std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant pulse_value : std_logic_vector(target'range) := (others => '1');
begin
gen_pulse(target, pulse_value, clock_signal, num_periods, msg, scope, msg_id, msg_id_panel); -- pulse_value = (others => '1') by default
end;
--------------------------------------------
-- Clock generators :
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
-- Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
begin
loop
clock_signal <= '1';
wait for C_FIRST_HALF_CLK_PERIOD;
clock_signal <= '0';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
-- Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_time : in time
) is
begin
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
clock_signal <= '1';
wait for clock_high_time;
clock_signal <= '0';
wait for (clock_period - clock_high_time);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Count variable (clock_count) is added as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
begin
clock_count <= 0;
loop
clock_signal <= '0'; -- Should start on 0
wait for C_FIRST_HALF_CLK_PERIOD;
-- Update clock_count when clock_signal is set to '1'
if clock_count < natural'right then
clock_count <= clock_count + 1;
else -- Wrap when reached max value of natural
clock_count <= 0;
end if;
clock_signal <= '1';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Counter clock_count is given as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_time : in time
) is
begin
clock_count <= 0;
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
clock_signal <= '0';
wait for (clock_period - clock_high_time);
if clock_count < natural'right then
clock_count <= clock_count + 1;
else -- Wrap when reached max value of natural
clock_count <= 0;
end if;
clock_signal <= '1';
wait for clock_high_time;
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- - Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
begin
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for C_FIRST_HALF_CLK_PERIOD;
clock_signal <= '0';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- inferred to be low time.
-- - Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
) is
begin
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for clock_high_time;
clock_signal <= '0';
wait for (clock_period - clock_high_time);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- - Count variable (clock_count) is added as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
variable v_clock_count : natural := 0;
begin
clock_count <= v_clock_count;
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for C_FIRST_HALF_CLK_PERIOD;
clock_signal <= '0';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
if v_clock_count < natural'right then
v_clock_count := v_clock_count + 1;
else -- Wrap when reached max value of natural
v_clock_count := 0;
end if;
clock_count <= v_clock_count;
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- inferred to be low time.
-- - Count variable (clock_count) is added as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
) is
variable v_clock_count : natural := 0;
begin
clock_count <= v_clock_count;
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for clock_high_time;
clock_signal <= '0';
wait for (clock_period - clock_high_time);
if v_clock_count < natural'right then
v_clock_count := v_clock_count + 1;
else -- Wrap when reached max value of natural
v_clock_count := 0;
end if;
clock_count <= v_clock_count;
end loop;
end;
--------------------------------------------
-- Adjustable clock generators :
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
-- Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure adjustable_clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
signal clock_high_percentage : in natural range 0 to 100
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
variable v_first_half_clk_period : time := clock_period * clock_high_percentage/100;
begin
-- alert if init value is not set
check_value(clock_high_percentage /= 0, TB_ERROR, "clock_generator: parameter clock_high_percentage must be set!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock: " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock: " & clock_name);
-- alert if unvalid value is set
check_value_in_range(clock_high_percentage, 1, 99, TB_ERROR, "adjustable_clock_generator: parameter clock_high_percentage must be in range 1 to 99!", C_TB_SCOPE_DEFAULT, ID_NEVER);
end if;
v_first_half_clk_period := clock_period * clock_high_percentage/100;
clock_signal <= '1';
wait for v_first_half_clk_period;
clock_signal <= '0';
wait for (clock_period - v_first_half_clk_period);
end loop;
end procedure;
procedure adjustable_clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
signal clock_high_percentage : in natural range 0 to 100
) is
constant v_clock_name : string := "";
begin
adjustable_clock_generator(clock_signal, clock_ena, clock_period, v_clock_name, clock_high_percentage);
end procedure;
-- Overloaded version with clock enable, clock name
-- and clock count
procedure adjustable_clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
signal clock_high_percentage : in natural range 0 to 100
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
variable v_first_half_clk_period : time := clock_period * clock_high_percentage/100;
variable v_clock_count : natural := 0;
begin
-- alert if init value is not set
check_value(clock_high_percentage /= 0, TB_ERROR, "clock_generator: parameter clock_high_percentage must be set!", C_TB_SCOPE_DEFAULT, ID_NEVER);
clock_count <= v_clock_count;
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock: " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock: " & clock_name);
-- alert if unvalid value is set
check_value_in_range(clock_high_percentage, 1, 99, TB_ERROR, "adjustable_clock_generator: parameter clock_high_percentage must be in range 1 to 99!", C_TB_SCOPE_DEFAULT, ID_NEVER);
end if;
v_first_half_clk_period := clock_period * clock_high_percentage/100;
clock_signal <= '1';
wait for v_first_half_clk_period;
clock_signal <= '0';
wait for (clock_period - v_first_half_clk_period);
if v_clock_count < natural'right then
v_clock_count := v_clock_count + 1;
else -- Wrap when reached max value of natural
v_clock_count := 0;
end if;
clock_count <= v_clock_count;
end loop;
end procedure;
-- ============================================================================
-- Synchronization methods
-- ============================================================================
-- Local type used in synchronization methods
type t_flag_array_idx_and_status_record is record
flag_idx : integer;
flag_is_new : boolean;
flag_array_full : boolean;
end record;
-- Local function used in synchronization methods to search through shared_flag_array for flag_name or available index
-- Returns:
-- Flag index in the shared array
-- If the flag is new or already in the array
-- If the array is full, and the flag can not be added (alerts an error).
impure function find_or_add_sync_flag(
constant flag_name : string
) return t_flag_array_idx_and_status_record is
variable v_idx : integer := 0;
variable v_is_new : boolean := false;
variable v_is_array_full : boolean := true;
begin
for i in shared_flag_array'range loop
-- Search for empty index. If found add a new flag
if (shared_flag_array(i).flag_name = (shared_flag_array(i).flag_name'range => NUL)) then
shared_flag_array(i).flag_name(flag_name'range) := flag_name;
v_is_new := true;
end if;
-- Check if flag exists in the array
if (shared_flag_array(i).flag_name(flag_name'range) = flag_name) then
v_idx := i;
v_is_array_full := false;
exit;
end if;
end loop;
return (v_idx, v_is_new, v_is_array_full);
end;
procedure block_flag(
constant flag_name : in string;
constant msg : in string;
constant already_blocked_severity : in t_alert_level := warning;
constant scope : in string := C_TB_SCOPE_DEFAULT
) is
variable v_idx : integer := 0;
variable v_is_new : boolean := false;
variable v_is_array_full : boolean := true;
begin
-- Find flag, or add a new provided the array is not full.
(v_idx, v_is_new, v_is_array_full) := find_or_add_sync_flag(flag_name);
if (v_is_array_full = true) then
alert(TB_ERROR, "The flag " & flag_name & " was not found and the maximum number of flags (" & to_string(C_NUM_SYNC_FLAGS) & ") have been used. Configure in adaptations_pkg. " & add_msg_delimiter(msg), scope);
else -- Block flag
if (v_is_new = true) then
log(ID_BLOCKING, flag_name & ": New blocked synchronization flag added. " & add_msg_delimiter(msg), scope);
else
-- Check if the flag to be blocked already is blocked
if (shared_flag_array(v_idx).is_blocked = true) then
alert(already_blocked_severity, "The flag " & flag_name & " was already blocked. " & add_msg_delimiter(msg), scope);
else
log(ID_BLOCKING, flag_name & ": Blocking flag. " & add_msg_delimiter(msg), scope);
end if;
end if;
shared_flag_array(v_idx).is_blocked := true;
end if;
end procedure;
procedure unblock_flag(
constant flag_name : in string;
constant msg : in string;
signal trigger : inout std_logic; -- Parameter must be global_trigger as method await_unblock_flag() uses that global signal to detect unblocking.
constant scope : in string := C_TB_SCOPE_DEFAULT
) is
variable v_idx : integer := 0;
variable v_is_new : boolean := false;
variable v_is_array_full : boolean := true;
begin
-- Find flag, or add a new provided the array is not full.
(v_idx, v_is_new, v_is_array_full) := find_or_add_sync_flag(flag_name);
if (v_is_array_full = true) then
alert(TB_ERROR, "The flag " & flag_name & " was not found and the maximum number of flags (" & to_string(C_NUM_SYNC_FLAGS) & ") have been used. Configure in adaptations_pkg. " & add_msg_delimiter(msg), scope);
else -- Unblock flag
if (v_is_new = true) then
log(ID_BLOCKING, flag_name & ": New unblocked synchronization flag added. " & add_msg_delimiter(msg), scope);
else
log(ID_BLOCKING, flag_name & ": Unblocking flag. " & add_msg_delimiter(msg), scope);
end if;
shared_flag_array(v_idx).is_blocked := false;
-- Triggers a signal to allow await_unblock_flag() to detect unblocking.
gen_pulse(trigger, 0 ns, "pulsing global_trigger. " & add_msg_delimiter(msg), C_TB_SCOPE_DEFAULT, ID_NEVER);
end if;
end procedure;
procedure await_unblock_flag(
constant flag_name : in string;
constant timeout : in time;
constant msg : in string;
constant flag_returning : in t_flag_returning := KEEP_UNBLOCKED;
constant timeout_severity : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT
) is
variable v_idx : integer := 0;
variable v_is_new : boolean := false;
variable v_is_array_full : boolean := true;
variable v_flag_is_blocked : boolean := true;
constant start_time : time := now;
begin
-- Find flag, or add a new provided the array is not full.
(v_idx, v_is_new, v_is_array_full) := find_or_add_sync_flag(flag_name);
if (v_is_array_full = true) then
alert(TB_ERROR, "The flag " & flag_name & " was not found and the maximum number of flags (" & to_string(C_NUM_SYNC_FLAGS) & ") have been used. Configure in adaptations_pkg. " & add_msg_delimiter(msg), scope);
else -- Waits only if the flag is found and is blocked. Will wait when a new flag is added, as it is default blocked.
v_flag_is_blocked := shared_flag_array(v_idx).is_blocked;
if (v_flag_is_blocked = false) then
if (flag_returning = RETURN_TO_BLOCK) then
-- wait for all sequencer that are waiting for that flag before reseting it
wait for 0 ns;
shared_flag_array(v_idx).is_blocked := true;
log(ID_BLOCKING, flag_name & ": Was already unblocked. Returned to blocked. " & add_msg_delimiter(msg), scope);
else
log(ID_BLOCKING, flag_name & ": Was already unblocked. " & add_msg_delimiter(msg), scope);
end if;
else -- Flag is blocked (or a new flag was added), starts waiting. log before while loop. Otherwise the message will be printed everytime the global_trigger was triggered.
if (v_is_new = true) then
log(ID_BLOCKING, flag_name & ": New blocked synchronization flag added. Waiting to be unblocked. " & add_msg_delimiter(msg), scope);
else
log(ID_BLOCKING, flag_name & ": Waiting to be unblocked. " & add_msg_delimiter(msg), scope);
end if;
end if;
-- Waiting for flag to be unblocked
while v_flag_is_blocked = true loop
if (timeout /= 0 ns) then
wait until rising_edge(global_trigger) for ((start_time + timeout) - now);
check_value(global_trigger = '1', timeout_severity, flag_name & " timed out. " & add_msg_delimiter(msg), scope, ID_NEVER);
if global_trigger /= '1' then
exit;
end if;
else
wait until rising_edge(global_trigger);
end if;
v_flag_is_blocked := shared_flag_array(v_idx).is_blocked;
if (v_flag_is_blocked = false) then
if flag_returning = KEEP_UNBLOCKED then
log(ID_BLOCKING, flag_name & ": Has been unblocked. ", scope);
else
log(ID_BLOCKING, flag_name & ": Has been unblocked. Returned to blocked. ", scope);
-- wait for all sequencer that are waiting for that flag before reseting it
wait for 0 ns;
shared_flag_array(v_idx).is_blocked := true;
end if;
end if;
end loop;
end if;
end procedure;
procedure await_barrier(
signal barrier_signal : inout std_logic;
constant timeout : in time;
constant msg : in string;
constant timeout_severity : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT
)is
begin
-- set barrier signal to 0
barrier_signal <= '0';
log(ID_BLOCKING, "Waiting for barrier. " & add_msg_delimiter(msg), scope);
-- wait until all sequencer using that barrier_signal wait for it
if timeout = 0 ns then
wait until barrier_signal = '0';
else
wait until barrier_signal = '0' for timeout;
end if;
if barrier_signal /= '0' then
-- timeout
alert(timeout_severity, "Timeout while waiting for barrier signal. " & add_msg_delimiter(msg), scope);
else
log(ID_BLOCKING, "Barrier received. " & add_msg_delimiter(msg), scope);
end if;
barrier_signal <= '1';
end procedure;
procedure await_semaphore_in_delta_cycles(
variable semaphore : inout t_protected_semaphore
) is
variable v_cnt_lock_tries : natural := 0;
begin
while semaphore.get_semaphore = false and v_cnt_lock_tries < C_NUM_SEMAPHORE_LOCK_TRIES loop
wait for 0 ns;
v_cnt_lock_tries := v_cnt_lock_tries + 1;
end loop;
if v_cnt_lock_tries = C_NUM_SEMAPHORE_LOCK_TRIES then
tb_error("Failed to acquire semaphore when sending command to VVC", C_SCOPE);
end if;
end procedure;
procedure release_semaphore(
variable semaphore : inout t_protected_semaphore
) is
begin
semaphore.release_semaphore;
end procedure;
-- ============================================================================
-- General Watchdog-related
-- ============================================================================
-------------------------------------------------------------------------------
-- General Watchdog timer:
-- Include this as a concurrent procedure from your testbench.
-- Use extend_watchdog(), reinitialize_watchdog() or terminate_watchdog() to
-- modify the watchdog timer from the test sequencer.
-------------------------------------------------------------------------------
procedure watchdog_timer(
signal watchdog_ctrl : in t_watchdog_ctrl;
constant timeout : time;
constant alert_level : t_alert_level := error;
constant msg : string := ""
) is
variable v_timeout : time;
variable v_prev_timeout : time;
begin
-- This delta cycle is needed due to a problem with external tools that
-- without it, they wouldn't print the first log message.
wait for 0 ns;
log(ID_WATCHDOG, "Starting general watchdog: " & to_string(timeout) & ". " & msg);
v_prev_timeout := 0 ns;
v_timeout := timeout;
loop
wait until (watchdog_ctrl.extend or watchdog_ctrl.restart or watchdog_ctrl.terminate) for v_timeout;
-- Watchdog was extended
if watchdog_ctrl.extend then
if watchdog_ctrl.extension = 0 ns then
log(ID_WATCHDOG, "Extending general watchdog by default value: " & to_string(timeout) & ". " & msg);
v_timeout := (v_prev_timeout + v_timeout - now) + timeout;
else
log(ID_WATCHDOG, "Extending general watchdog by " & to_string(watchdog_ctrl.extension) & ". " & msg);
v_timeout := (v_prev_timeout + v_timeout - now) + watchdog_ctrl.extension;
end if;
v_prev_timeout := now;
-- Watchdog was reinitialized
elsif watchdog_ctrl.restart then
log(ID_WATCHDOG, "Reinitializing general watchdog: " & to_string(watchdog_ctrl.new_timeout) & ". " & msg);
v_timeout := watchdog_ctrl.new_timeout;
v_prev_timeout := now;
else
-- Watchdog was terminated
if watchdog_ctrl.terminate then
log(ID_WATCHDOG, "Terminating general watchdog. " & msg);
-- Watchdog has timed out
else
alert(alert_level, "General watchdog timer ended! " & msg);
end if;
exit;
end if;
end loop;
wait;
end procedure;
procedure extend_watchdog(
signal watchdog_ctrl : inout t_watchdog_ctrl;
constant time_extend : time := 0 ns
) is
begin
if not watchdog_ctrl.terminate then
watchdog_ctrl.extension <= time_extend;
watchdog_ctrl.extend <= true;
wait for 0 ns; -- delta cycle to propagate signal
watchdog_ctrl.extend <= false;
end if;
end procedure;
procedure reinitialize_watchdog(
signal watchdog_ctrl : inout t_watchdog_ctrl;
constant timeout : time
) is
begin
if not watchdog_ctrl.terminate then
watchdog_ctrl.new_timeout <= timeout;
watchdog_ctrl.restart <= true;
wait for 0 ns; -- delta cycle to propagate signal
watchdog_ctrl.restart <= false;
end if;
end procedure;
procedure terminate_watchdog(
signal watchdog_ctrl : inout t_watchdog_ctrl
) is
begin
watchdog_ctrl.terminate <= true;
wait for 0 ns; -- delta cycle to propagate signal
end procedure;
-- ============================================================================
-- generate_crc
-- ============================================================================
impure function generate_crc(
constant data : in std_logic_vector;
constant crc_in : in std_logic_vector;
constant polynomial : in std_logic_vector
) return std_logic_vector is
variable crc_out : std_logic_vector(crc_in'range) := crc_in;
begin
-- Sanity checks
check_value(not data'ascending, TB_FAILURE, "data have to be decending", C_SCOPE, ID_NEVER);
check_value(not crc_in'ascending, TB_FAILURE, "crc_in have to be decending", C_SCOPE, ID_NEVER);
check_value(not polynomial'ascending, TB_FAILURE, "polynomial have to be decending", C_SCOPE, ID_NEVER);
check_value(crc_in'length, polynomial'length-1, TB_FAILURE, "crc_in have to be one bit shorter than polynomial", C_SCOPE, ID_NEVER);
for i in data'high downto data'low loop
if crc_out(crc_out'high) xor data(i) then
crc_out := crc_out sll 1;
crc_out := crc_out xor polynomial(polynomial'high-1 downto polynomial'low);
else
crc_out := crc_out sll 1;
end if;
end loop;
return crc_out;
end function generate_crc;
impure function generate_crc(
constant data : in t_slv_array;
constant crc_in : in std_logic_vector;
constant polynomial : in std_logic_vector
) return std_logic_vector is
variable crc_out : std_logic_vector(crc_in'range) := crc_in;
begin
-- Sanity checks
check_value(data'ascending, TB_FAILURE, "slv array have to be acending", C_SCOPE, ID_NEVER);
for i in data'low to data'high loop
crc_out := generate_crc(data(i), crc_out, polynomial);
end loop;
return crc_out;
end function generate_crc;
end package body methods_pkg;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: Mem_B_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY Mem_B_tb IS
END ENTITY;
ARCHITECTURE Mem_B_tb_ARCH OF Mem_B_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
Mem_B_synth_inst:ENTITY work.Mem_B_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
LIBRARY ieee;
use IEEE.std_logic_1164.all;
--use work.iface.all;
use work.amba.all;
--use work.mdctrom256.all;
package mdctlib is
constant MDCT_wsize : integer := 32;
-- size of data words
constant MDCT_csize : integer := 32;
-- size of the word of look-up tables
constant TRIGBITS: integer := 14;
-- number of bits to shift right after
-- multiplication
--constant rom_lenght: integer:=14;
constant cPI3_8 :std_logic_vector ( MDCT_csize-1 downto 0) := "00000000000000000001100001111110";
constant cPI2_8 :std_logic_vector (MDCT_csize-1 downto 0) := "00000000000000000010110101000001";
constant cPI1_8 :std_logic_vector (MDCT_csize-1 downto 0) := "00000000000000000011101100100001";
constant zero32 : std_logic_vector (MDCT_csize-1 downto 0):= "00000000000000000000000000000000";
type block_data is array (natural range <>) of std_logic_vector (MDCT_wsize-1 downto 0);
subtype block32_data is block_data (0 to 31);
subtype block8_data is block_data (0 to 7);
subtype block4_data is block_data (0 to 3);
type in_multadd is record
op1_m1: std_logic_vector (MDCT_wsize-1 downto 0);
op2_m1: std_logic_vector (MDCT_csize-1 downto 0);
op1_m2: std_logic_vector (MDCT_wsize-1 downto 0);
op2_m2: std_logic_vector (MDCT_csize-1 downto 0);
add_fun: std_logic;
end record;
type out_multadd is record
r_m1: std_logic_vector (MDCT_wsize-1 downto 0);
r_m2: std_logic_vector (MDCT_wsize-1 downto 0);
r_mult: std_logic_vector (MDCT_wsize-1 downto 0);
end record;
type in_addbank is record
op1_a1 : std_logic_vector(MDCT_wsize-1 downto 0);
op2_a1 : std_logic_vector(MDCT_wsize-1 downto 0);
op1_a2 : std_logic_vector(MDCT_wsize-1 downto 0);
op2_a2 : std_logic_vector(MDCT_wsize-1 downto 0);
op1_a3 : std_logic_vector(MDCT_wsize-1 downto 0);
op2_a3 : std_logic_vector(MDCT_wsize-1 downto 0);
op1_s1 : std_logic_vector(MDCT_wsize-1 downto 0);
op2_s1 : std_logic_vector(MDCT_wsize-1 downto 0);
op1_s2 : std_logic_vector(MDCT_wsize-1 downto 0);
op2_s2 : std_logic_vector(MDCT_wsize-1 downto 0);
op1_s3 : std_logic_vector(MDCT_wsize-1 downto 0);
op2_s3 : std_logic_vector(MDCT_wsize-1 downto 0);
act_trig: integer;
end record;
type out_addbank is record
r_a1: std_logic_vector(MDCT_wsize-1 downto 0);
r_a2: std_logic_vector(MDCT_wsize-1 downto 0);
r_a3: std_logic_vector(MDCT_wsize-1 downto 0);
r_s1: std_logic_vector(MDCT_wsize-1 downto 0);
r_s2: std_logic_vector(MDCT_wsize-1 downto 0);
r_s3: std_logic_vector(MDCT_wsize-1 downto 0);
next_trig: integer;
end record;
type ctrlregs is record
-- registers and signals used to communicate mdctctrl with amba wrapper
ntoprocess : std_logic_vector(5 downto 0); -- number of resting elements to be processed
memwr : std_logic; -- '1' for write, '0' for read
startadr: std_logic_vector(31 downto 0); -- start address of current block
incr : std_logic; -- Bytes increment for blocks ('0'=>4 '1'=>8)
pos : std_logic_vector(1 downto 0);
-- Pointer to read/store from buffer
-- (00,01,10,11)=>(0,4,8,12)
trigpos: std_logic; -- Signalize store at 16 position in
-- input buffer, when reading a trig or
-- bitreverse tables.
finish : std_logic; -- '1' if whole mdct is finished
rcopy : std_logic; -- Copy out buffer into in buffer
end record;
type mdctregs is record
-- ***********************
-- memory mapped registers
-- Control register
-- bit 0 of 0x80000300
mdctenreq : std_logic; -- mdct function enabled
-- bit 1 at 0x80000300
size : std_logic; -- number of points of mdct '0'=>256 '1'=>2048
-- bit 2 of 0x80000300
irqen : std_logic; -- enable interrupt
-- bit 3 of 0x80000300
irq : std_logic; -- irq request
-- 32 bit at 0x80000304
bitrevaddr : std_logic_vector(31 downto 0); -- read dma transfer start address
-- 32 bit at 0x80000308
trigaddr : std_logic_vector(31 downto 0); -- read dma transfer start address
-- 32 bit at 0x8000030C
rdstartaddr : std_logic_vector(31 downto 0); -- read dma transfer start address
-- 32 bit at 0x8000310
wrstartaddr : std_logic_vector(31 downto 0); -- write dma transfer start address
-- Status register
-- bit 0 of 0x80000314
ready : std_logic; -- '1' if function done, '0' if busy / read only
-- bit 1 of 0x80000314
memwr : std_logic; -- '1' if writting, '0' if reading data from memory /read only
-- 32 bit at 0x80000318
memoryadr : std_logic_vector(31 downto 0); -- actual dma address /read only
-- memory mapped registers end
-- ***************************
-- internal registers
mdcten : std_logic;
dmatransfreq : std_logic;
ntoprocess : std_logic_vector(5 downto 0); -- number of resting elements to be processed
trigpos : std_logic; -- signalize if trig or beitreverse
-- tables are read
inputdata : block32_data; -- original data from memory
-- amba status registers
skipblk: std_logic;
busact : std_logic;
busown : std_logic;
busgrant : std_logic;
busown2cyc : std_logic;
end record;
function MULT_NORM(w :std_logic_vector (MDCT_csize+MDCT_wsize-1 downto 0))
return std_logic_vector;
function HALVE(w :std_logic_vector (MDCT_wsize-1 downto 0))
return std_logic_vector;
end;
package body mdctlib is
function MULT_NORM(w :std_logic_vector (MDCT_csize+MDCT_wsize-1 downto 0))
return std_logic_vector is
variable result: std_logic_vector (MDCT_wsize-1 downto 0);
variable rshift: bit_vector (MDCT_csize+MDCT_wsize-1 downto 0);
begin
rshift := TO_BITVECTOR (w); -- convert to bitvector in order to prepare shift
rshift := rshift sra TRIGBITS; -- shift arithmetic right
result := TO_STDLOGICVECTOR(rshift(MDCT_wsize-1 downto 0));-- convert to std_logic_vector again
return result;
end MULT_NORM;
function HALVE(w :std_logic_vector (MDCT_wsize-1 downto 0))
return std_logic_vector is
variable result: std_logic_vector (MDCT_wsize-1 downto 0);
variable rshift: bit_vector (MDCT_wsize-1 downto 0);
begin
rshift := TO_BITVECTOR (w); -- convert to bitvector in order to prepare shift
rshift := rshift sra 1; -- shift arithmetic right
result := TO_STDLOGICVECTOR(rshift);-- convert to std_logic_vector again
return result;
end HALVE;
end; -- end mdct lib
|
----------------------------------------------------------------------------------
-- Engineer: Longofono
-- Create Date: 04/20/2017 05:59:28 PM
-- Description: Debouncing Circuit For Buttons
-- Based on starter code by Scott Larson of DigiKey
-- Retrieved 4/25/16
-- https://eewiki.net/pages/viewpage.action?pageId=4980758#DebounceLogicCircuit(withVHDLexample)-ExampleVHDLCode
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity button is
generic(counter_size : INTEGER := 20); -- debounce time control
port(
clk : in std_logic; -- system clock, assumed 100 MHz
rst : in std_logic; -- system reset
hw_in : in std_logic; -- input from physical button
button_assert : out std_logic);--debounced signal
end button;
architecture behav of button is
signal buf1, buf2 : std_logic; -- input buffer digits
signal reset_counter : std_logic; -- toggle reset_counter
signal counter : std_logic_vector(counter_size downto 0);-- := (OTHERS => '0'); --counter output
begin
reset_counter <= buf1 xor buf2; -- on change, reset_counter is high
process(clk)
begin
if('1' = rst) then
counter <= (others => '0');
elsif(rising_edge(clk)) then
buf1 <= hw_in;
buf2 <= buf1;
if(reset_counter = '1') then --input changed, start timer
counter <= (others => '0');
elsif(counter(counter_size) = '1') then -- debounced, output last matched signal
button_assert <= buf2;
else
counter <= counter + 1; -- not debounced yet, keep waiting
end if;
end if;
end process;
end behav;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed Sep 24 16:19:15 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 4
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset_port0 : out std_logic;
reset_response_port0 : in std_logic;
reset_port1 : out std_logic;
reset_response_port1 : in std_logic;
reset_port2 : out std_logic;
reset_response_port2 : in std_logic;
reset_port3 : out std_logic;
reset_response_port3 : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 3);
signal slv_reg_read_sel : std_logic_vector(0 to 3);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 3);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 3);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);
-- Connect reset signal ports from reg0
reset_port0 <= slv_reg0(C_SLV_DWIDTH-1);
reset_port1 <= slv_reg0(C_SLV_DWIDTH-2);
reset_port2 <= slv_reg0(C_SLV_DWIDTH-3);
reset_port3 <= slv_reg0(C_SLV_DWIDTH-4);
-- Connect reg1 to reset responses so that they can be read
RESET_RESPONSE_REG : process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
slv_reg1 <= (others => '0');
else
slv_reg1(C_SLV_DWIDTH-1) <= reset_response_port0;
slv_reg1(C_SLV_DWIDTH-2) <= reset_response_port1;
slv_reg1(C_SLV_DWIDTH-3) <= reset_response_port2;
slv_reg1(C_SLV_DWIDTH-4) <= reset_response_port3;
end if;
end if;
end process RESET_RESPONSE_REG;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
-- slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
case slv_reg_write_sel is
when "1000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
-- when "0100" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
-- end loop;
when "0010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
begin
case slv_reg_read_sel is
when "1000" => slv_ip2bus_data <= slv_reg0;
when "0100" => slv_ip2bus_data <= slv_reg1;
when "0010" => slv_ip2bus_data <= slv_reg2;
when "0001" => slv_ip2bus_data <= slv_reg3;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed Sep 24 16:19:15 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 4
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset_port0 : out std_logic;
reset_response_port0 : in std_logic;
reset_port1 : out std_logic;
reset_response_port1 : in std_logic;
reset_port2 : out std_logic;
reset_response_port2 : in std_logic;
reset_port3 : out std_logic;
reset_response_port3 : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 3);
signal slv_reg_read_sel : std_logic_vector(0 to 3);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 3);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 3);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);
-- Connect reset signal ports from reg0
reset_port0 <= slv_reg0(C_SLV_DWIDTH-1);
reset_port1 <= slv_reg0(C_SLV_DWIDTH-2);
reset_port2 <= slv_reg0(C_SLV_DWIDTH-3);
reset_port3 <= slv_reg0(C_SLV_DWIDTH-4);
-- Connect reg1 to reset responses so that they can be read
RESET_RESPONSE_REG : process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
slv_reg1 <= (others => '0');
else
slv_reg1(C_SLV_DWIDTH-1) <= reset_response_port0;
slv_reg1(C_SLV_DWIDTH-2) <= reset_response_port1;
slv_reg1(C_SLV_DWIDTH-3) <= reset_response_port2;
slv_reg1(C_SLV_DWIDTH-4) <= reset_response_port3;
end if;
end if;
end process RESET_RESPONSE_REG;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
-- slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
case slv_reg_write_sel is
when "1000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
-- when "0100" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
-- end loop;
when "0010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
begin
case slv_reg_read_sel is
when "1000" => slv_ip2bus_data <= slv_reg0;
when "0100" => slv_ip2bus_data <= slv_reg1;
when "0010" => slv_ip2bus_data <= slv_reg2;
when "0001" => slv_ip2bus_data <= slv_reg3;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed Sep 24 16:19:15 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 4
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset_port0 : out std_logic;
reset_response_port0 : in std_logic;
reset_port1 : out std_logic;
reset_response_port1 : in std_logic;
reset_port2 : out std_logic;
reset_response_port2 : in std_logic;
reset_port3 : out std_logic;
reset_response_port3 : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 3);
signal slv_reg_read_sel : std_logic_vector(0 to 3);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 3);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 3);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);
-- Connect reset signal ports from reg0
reset_port0 <= slv_reg0(C_SLV_DWIDTH-1);
reset_port1 <= slv_reg0(C_SLV_DWIDTH-2);
reset_port2 <= slv_reg0(C_SLV_DWIDTH-3);
reset_port3 <= slv_reg0(C_SLV_DWIDTH-4);
-- Connect reg1 to reset responses so that they can be read
RESET_RESPONSE_REG : process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
slv_reg1 <= (others => '0');
else
slv_reg1(C_SLV_DWIDTH-1) <= reset_response_port0;
slv_reg1(C_SLV_DWIDTH-2) <= reset_response_port1;
slv_reg1(C_SLV_DWIDTH-3) <= reset_response_port2;
slv_reg1(C_SLV_DWIDTH-4) <= reset_response_port3;
end if;
end if;
end process RESET_RESPONSE_REG;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
-- slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
case slv_reg_write_sel is
when "1000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
-- when "0100" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
-- end loop;
when "0010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
begin
case slv_reg_read_sel is
when "1000" => slv_ip2bus_data <= slv_reg0;
when "0100" => slv_ip2bus_data <= slv_reg1;
when "0010" => slv_ip2bus_data <= slv_reg2;
when "0001" => slv_ip2bus_data <= slv_reg3;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed Sep 24 16:19:15 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 4
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset_port0 : out std_logic;
reset_response_port0 : in std_logic;
reset_port1 : out std_logic;
reset_response_port1 : in std_logic;
reset_port2 : out std_logic;
reset_response_port2 : in std_logic;
reset_port3 : out std_logic;
reset_response_port3 : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 3);
signal slv_reg_read_sel : std_logic_vector(0 to 3);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 3);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 3);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);
-- Connect reset signal ports from reg0
reset_port0 <= slv_reg0(C_SLV_DWIDTH-1);
reset_port1 <= slv_reg0(C_SLV_DWIDTH-2);
reset_port2 <= slv_reg0(C_SLV_DWIDTH-3);
reset_port3 <= slv_reg0(C_SLV_DWIDTH-4);
-- Connect reg1 to reset responses so that they can be read
RESET_RESPONSE_REG : process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
slv_reg1 <= (others => '0');
else
slv_reg1(C_SLV_DWIDTH-1) <= reset_response_port0;
slv_reg1(C_SLV_DWIDTH-2) <= reset_response_port1;
slv_reg1(C_SLV_DWIDTH-3) <= reset_response_port2;
slv_reg1(C_SLV_DWIDTH-4) <= reset_response_port3;
end if;
end if;
end process RESET_RESPONSE_REG;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
-- slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
case slv_reg_write_sel is
when "1000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
-- when "0100" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
-- end loop;
when "0010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
begin
case slv_reg_read_sel is
when "1000" => slv_ip2bus_data <= slv_reg0;
when "0100" => slv_ip2bus_data <= slv_reg1;
when "0010" => slv_ip2bus_data <= slv_reg2;
when "0001" => slv_ip2bus_data <= slv_reg3;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed Sep 24 16:19:15 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 4
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset_port0 : out std_logic;
reset_response_port0 : in std_logic;
reset_port1 : out std_logic;
reset_response_port1 : in std_logic;
reset_port2 : out std_logic;
reset_response_port2 : in std_logic;
reset_port3 : out std_logic;
reset_response_port3 : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 3);
signal slv_reg_read_sel : std_logic_vector(0 to 3);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 3);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 3);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);
-- Connect reset signal ports from reg0
reset_port0 <= slv_reg0(C_SLV_DWIDTH-1);
reset_port1 <= slv_reg0(C_SLV_DWIDTH-2);
reset_port2 <= slv_reg0(C_SLV_DWIDTH-3);
reset_port3 <= slv_reg0(C_SLV_DWIDTH-4);
-- Connect reg1 to reset responses so that they can be read
RESET_RESPONSE_REG : process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
slv_reg1 <= (others => '0');
else
slv_reg1(C_SLV_DWIDTH-1) <= reset_response_port0;
slv_reg1(C_SLV_DWIDTH-2) <= reset_response_port1;
slv_reg1(C_SLV_DWIDTH-3) <= reset_response_port2;
slv_reg1(C_SLV_DWIDTH-4) <= reset_response_port3;
end if;
end if;
end process RESET_RESPONSE_REG;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
-- slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
case slv_reg_write_sel is
when "1000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
-- when "0100" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
-- end loop;
when "0010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
begin
case slv_reg_read_sel is
when "1000" => slv_ip2bus_data <= slv_reg0;
when "0100" => slv_ip2bus_data <= slv_reg1;
when "0010" => slv_ip2bus_data <= slv_reg2;
when "0001" => slv_ip2bus_data <= slv_reg3;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed Sep 24 16:19:15 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 4
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset_port0 : out std_logic;
reset_response_port0 : in std_logic;
reset_port1 : out std_logic;
reset_response_port1 : in std_logic;
reset_port2 : out std_logic;
reset_response_port2 : in std_logic;
reset_port3 : out std_logic;
reset_response_port3 : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 3);
signal slv_reg_read_sel : std_logic_vector(0 to 3);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 3);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 3);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);
-- Connect reset signal ports from reg0
reset_port0 <= slv_reg0(C_SLV_DWIDTH-1);
reset_port1 <= slv_reg0(C_SLV_DWIDTH-2);
reset_port2 <= slv_reg0(C_SLV_DWIDTH-3);
reset_port3 <= slv_reg0(C_SLV_DWIDTH-4);
-- Connect reg1 to reset responses so that they can be read
RESET_RESPONSE_REG : process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
slv_reg1 <= (others => '0');
else
slv_reg1(C_SLV_DWIDTH-1) <= reset_response_port0;
slv_reg1(C_SLV_DWIDTH-2) <= reset_response_port1;
slv_reg1(C_SLV_DWIDTH-3) <= reset_response_port2;
slv_reg1(C_SLV_DWIDTH-4) <= reset_response_port3;
end if;
end if;
end process RESET_RESPONSE_REG;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
-- slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
case slv_reg_write_sel is
when "1000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
-- when "0100" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
-- end loop;
when "0010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
begin
case slv_reg_read_sel is
when "1000" => slv_ip2bus_data <= slv_reg0;
when "0100" => slv_ip2bus_data <= slv_reg1;
when "0010" => slv_ip2bus_data <= slv_reg2;
when "0001" => slv_ip2bus_data <= slv_reg3;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed Sep 24 16:19:15 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 4
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset_port0 : out std_logic;
reset_response_port0 : in std_logic;
reset_port1 : out std_logic;
reset_response_port1 : in std_logic;
reset_port2 : out std_logic;
reset_response_port2 : in std_logic;
reset_port3 : out std_logic;
reset_response_port3 : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 3);
signal slv_reg_read_sel : std_logic_vector(0 to 3);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 3);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 3);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);
-- Connect reset signal ports from reg0
reset_port0 <= slv_reg0(C_SLV_DWIDTH-1);
reset_port1 <= slv_reg0(C_SLV_DWIDTH-2);
reset_port2 <= slv_reg0(C_SLV_DWIDTH-3);
reset_port3 <= slv_reg0(C_SLV_DWIDTH-4);
-- Connect reg1 to reset responses so that they can be read
RESET_RESPONSE_REG : process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
slv_reg1 <= (others => '0');
else
slv_reg1(C_SLV_DWIDTH-1) <= reset_response_port0;
slv_reg1(C_SLV_DWIDTH-2) <= reset_response_port1;
slv_reg1(C_SLV_DWIDTH-3) <= reset_response_port2;
slv_reg1(C_SLV_DWIDTH-4) <= reset_response_port3;
end if;
end if;
end process RESET_RESPONSE_REG;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
-- slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
case slv_reg_write_sel is
when "1000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
-- when "0100" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
-- end loop;
when "0010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
begin
case slv_reg_read_sel is
when "1000" => slv_ip2bus_data <= slv_reg0;
when "0100" => slv_ip2bus_data <= slv_reg1;
when "0010" => slv_ip2bus_data <= slv_reg2;
when "0001" => slv_ip2bus_data <= slv_reg3;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed Sep 24 16:19:15 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 4
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset_port0 : out std_logic;
reset_response_port0 : in std_logic;
reset_port1 : out std_logic;
reset_response_port1 : in std_logic;
reset_port2 : out std_logic;
reset_response_port2 : in std_logic;
reset_port3 : out std_logic;
reset_response_port3 : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 3);
signal slv_reg_read_sel : std_logic_vector(0 to 3);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 3);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 3);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);
-- Connect reset signal ports from reg0
reset_port0 <= slv_reg0(C_SLV_DWIDTH-1);
reset_port1 <= slv_reg0(C_SLV_DWIDTH-2);
reset_port2 <= slv_reg0(C_SLV_DWIDTH-3);
reset_port3 <= slv_reg0(C_SLV_DWIDTH-4);
-- Connect reg1 to reset responses so that they can be read
RESET_RESPONSE_REG : process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
slv_reg1 <= (others => '0');
else
slv_reg1(C_SLV_DWIDTH-1) <= reset_response_port0;
slv_reg1(C_SLV_DWIDTH-2) <= reset_response_port1;
slv_reg1(C_SLV_DWIDTH-3) <= reset_response_port2;
slv_reg1(C_SLV_DWIDTH-4) <= reset_response_port3;
end if;
end if;
end process RESET_RESPONSE_REG;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
-- slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
case slv_reg_write_sel is
when "1000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
-- when "0100" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
-- end loop;
when "0010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
begin
case slv_reg_read_sel is
when "1000" => slv_ip2bus_data <= slv_reg0;
when "0100" => slv_ip2bus_data <= slv_reg1;
when "0010" => slv_ip2bus_data <= slv_reg2;
when "0001" => slv_ip2bus_data <= slv_reg3;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed Sep 24 16:19:15 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 4
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset_port0 : out std_logic;
reset_response_port0 : in std_logic;
reset_port1 : out std_logic;
reset_response_port1 : in std_logic;
reset_port2 : out std_logic;
reset_response_port2 : in std_logic;
reset_port3 : out std_logic;
reset_response_port3 : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 3);
signal slv_reg_read_sel : std_logic_vector(0 to 3);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 3);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 3);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);
-- Connect reset signal ports from reg0
reset_port0 <= slv_reg0(C_SLV_DWIDTH-1);
reset_port1 <= slv_reg0(C_SLV_DWIDTH-2);
reset_port2 <= slv_reg0(C_SLV_DWIDTH-3);
reset_port3 <= slv_reg0(C_SLV_DWIDTH-4);
-- Connect reg1 to reset responses so that they can be read
RESET_RESPONSE_REG : process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
slv_reg1 <= (others => '0');
else
slv_reg1(C_SLV_DWIDTH-1) <= reset_response_port0;
slv_reg1(C_SLV_DWIDTH-2) <= reset_response_port1;
slv_reg1(C_SLV_DWIDTH-3) <= reset_response_port2;
slv_reg1(C_SLV_DWIDTH-4) <= reset_response_port3;
end if;
end if;
end process RESET_RESPONSE_REG;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
-- slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
case slv_reg_write_sel is
when "1000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
-- when "0100" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
-- end loop;
when "0010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
begin
case slv_reg_read_sel is
when "1000" => slv_ip2bus_data <= slv_reg0;
when "0100" => slv_ip2bus_data <= slv_reg1;
when "0010" => slv_ip2bus_data <= slv_reg2;
when "0001" => slv_ip2bus_data <= slv_reg3;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruct_Memory_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Instruct_Memory_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END Instruct_Memory_exdes;
ARCHITECTURE xilinx OF Instruct_Memory_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT Instruct_Memory IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : Instruct_Memory
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruct_Memory_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Instruct_Memory_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END Instruct_Memory_exdes;
ARCHITECTURE xilinx OF Instruct_Memory_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT Instruct_Memory IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : Instruct_Memory
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.TbFuncs.all;
entity ByteMuxQuad_tb is
end ByteMuxQuad_tb;
architecture behavior of ByteMuxQuad_tb is
component ByteMuxQuad
port (
A_i : in std_logic_vector(7 downto 0);
B_i : in std_logic_vector(7 downto 0);
C_i : in std_logic_vector(7 downto 0);
D_i : in std_logic_vector(7 downto 0);
SAB_i : in std_logic;
SC_i : in std_logic;
SD_i : in std_logic;
Y_o : out std_logic_vector(7 downto 0)
);
end component;
constant TestCases : natural := 100;
constant CheckOutputDelay : time := 20 ns;
constant SetupNextInputDelay : time := 20 ns;
signal A_i : std_logic_vector(7 downto 0);
signal B_i : std_logic_vector(7 downto 0);
signal C_i : std_logic_vector(7 downto 0);
signal D_i : std_logic_vector(7 downto 0);
signal SAB_i : std_logic;
signal SC_i : std_logic;
signal SD_i : std_logic;
signal Y_o : std_logic_vector(7 downto 0);
begin
DUT: ByteMuxQuad
port map (
A_i => A_i,
B_i => B_i,
C_i => C_i,
D_i => D_i,
SAB_i => SAB_i,
SC_i => SC_i,
SD_i => SD_i,
Y_o => Y_o
);
StimulusProc: process
variable S1 : positive;
variable S2 : positive;
variable R : real;
procedure Check (
constant SAB : in std_logic;
constant SC : in std_logic;
constant SD : in std_logic;
constant Correct : in std_logic_vector(7 downto 0)) is
begin -- Check
SAB_i <= SAB; SC_i <= SC; SD_i <= SD;
wait for CheckOutputDelay;
assert Y_o = Correct
report "Wrong Result Y_o = " & Vector2String(Y_o) &
" for A_i = " & Vector2String(A_i) &
", B_i = " & Vector2String(B_i) &
", C_i = " & Vector2String(C_i) &
", D_i = " & Vector2String(D_i) &
", SAB_i = " & std_logic'image(SAB_i) &
", SC_i = " & std_logic'image(SC_i) &
", SD_i = " & std_logic'image(SD_i) &
", should be " & Vector2String(A_i) severity error;
end Check;
begin
A_i <= "00000000";
B_i <= "00000000";
C_i <= "00000000";
D_i <= "00000000";
SAB_i <= '0';
SC_i <= '0';
SD_i <= '0';
wait for SetupNextInputDelay;
for i in 1 to TestCases loop
Uniform(S1,S2,R);
A_i <= std_logic_vector(to_unsigned(integer(trunc(R * real(255))),8));
Uniform(S1,S2,R);
B_i <= std_logic_vector(to_unsigned(integer(trunc(R * real(255))),8));
Uniform(S1,S2,R);
C_i <= std_logic_vector(to_unsigned(integer(trunc(R * real(255))),8));
Uniform(S1,S2,R);
D_i <= std_logic_vector(to_unsigned(integer(trunc(R * real(255))),8));
Check('0','0','0',A_i);
Check('1','0','0',B_i);
Check('0','1','0',C_i);
Check('1','1','0',C_i);
Check('0','0','1',D_i);
Check('1','0','1',D_i);
Check('0','1','1',D_i);
Check('1','1','1',D_i);
wait for SetupNextInputDelay;
end loop;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
|
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